1 From 7670ec4a14891a1a182b98a9c403ffbf6b49e4b1 Mon Sep 17 00:00:00 2001
2 From: "SkyLake.Huang" <skylake.huang@mediatek.com>
3 Date: Thu, 23 Jun 2022 18:39:56 +0800
4 Subject: [PATCH 5/6] drivers: mtd: spinand: Add calibration support for
7 Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
9 drivers/mtd/nand/spi/core.c | 54 +++++++++++++++++++++++++++++++++++++
10 1 file changed, 54 insertions(+)
12 --- a/drivers/mtd/nand/spi/core.c
13 +++ b/drivers/mtd/nand/spi/core.c
14 @@ -977,6 +977,56 @@ static int spinand_manufacturer_match(st
18 +int spinand_cal_read(void *priv, u32 *addr, int addrlen, u8 *buf, int readlen) {
19 + struct spinand_device *spinand = (struct spinand_device *)priv;
20 + struct device *dev = &spinand->spimem->spi->dev;
21 + struct spi_mem_op op = SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, buf, readlen);
22 + struct nand_pos pos;
23 + struct nand_page_io_req req;
27 + if(addrlen != sizeof(struct nand_addr)/sizeof(unsigned int)) {
28 + dev_err(dev, "Must provide correct addr(length) for spinand calibration\n");
32 + ret = spinand_reset_op(spinand);
36 + /* We should store our golden data in first target because
37 + * we can't switch target at this moment.
39 + pos = (struct nand_pos){
43 + .eraseblock = *(addr+2),
47 + req = (struct nand_page_io_req){
49 + .dataoffs = *(addr+4),
52 + .mode = MTD_OPS_AUTO_OOB,
55 + ret = spinand_load_page_op(spinand, &req);
59 + ret = spinand_wait(spinand, &status);
63 + ret = spi_mem_exec_op(spinand->spimem, &op);
68 static int spinand_id_detect(struct spinand_device *spinand)
70 u8 *id = spinand->id.data;
71 @@ -1227,6 +1277,10 @@ static int spinand_init(struct spinand_d
72 if (!spinand->scratchbuf)
75 + ret = spi_mem_do_calibration(spinand->spimem, spinand_cal_read, spinand);
77 + dev_err(dev, "Failed to calibrate SPI-NAND (err = %d)\n", ret);
79 ret = spinand_detect(spinand);