1 From: Felix Fietkau <nbd@nbd.name>
2 Date: Fri, 4 Sep 2020 18:42:42 +0200
3 Subject: [PATCH] pci: pcie-mediatek: add support for coherent DMA
5 It improves performance by eliminating the need for a cache flush for DMA on
8 Signed-off-by: Felix Fietkau <nbd@nbd.name>
11 --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
12 +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
14 bus-range = <0x00 0xff>;
15 ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x8000000>;
18 + mediatek,hifsys = <&hifsys>;
19 + mediatek,cci-control = <&cci_control2>;
21 #interrupt-cells = <1>;
22 interrupt-map-mask = <0 0 0 7>;
24 bus-range = <0x00 0xff>;
25 ranges = <0x82000000 0 0x28000000 0x0 0x28000000 0 0x8000000>;
28 + mediatek,hifsys = <&hifsys>;
29 + mediatek,cci-control = <&cci_control2>;
31 #interrupt-cells = <1>;
32 interrupt-map-mask = <0 0 0 7>;
33 --- a/drivers/pci/controller/pcie-mediatek.c
34 +++ b/drivers/pci/controller/pcie-mediatek.c
36 #include <linux/of_address.h>
37 #include <linux/of_pci.h>
38 #include <linux/of_platform.h>
39 +#include <linux/of_address.h>
40 #include <linux/pci.h>
41 #include <linux/phy/phy.h>
42 #include <linux/platform_device.h>
44 #define PCIE_LINK_STATUS_V2 0x804
45 #define PCIE_PORT_LINKUP_V2 BIT(10)
47 +/* DMA channel mapping */
48 +#define HIFSYS_DMA_AG_MAP 0x008
49 +#define HIFSYS_DMA_AG_MAP_PCIE0 BIT(0)
50 +#define HIFSYS_DMA_AG_MAP_PCIE1 BIT(1)
55 @@ -1060,6 +1066,27 @@ static int mtk_pcie_setup(struct mtk_pci
56 struct mtk_pcie_port *port, *tmp;
59 + if (of_dma_is_coherent(node)) {
63 + con = syscon_regmap_lookup_by_phandle(node,
64 + "mediatek,cci-control");
65 + /* enable CPU/bus coherency */
67 + regmap_write(con, 0, 3);
69 + con = syscon_regmap_lookup_by_phandle(node,
72 + dev_err(dev, "missing hifsys node\n");
73 + return PTR_ERR(con);
76 + mask = HIFSYS_DMA_AG_MAP_PCIE0 | HIFSYS_DMA_AG_MAP_PCIE1;
77 + regmap_update_bits(con, HIFSYS_DMA_AG_MAP, mask, mask);
80 slot = of_get_pci_domain_nr(dev->of_node);
82 for_each_available_child_of_node(node, child) {