1 From 41ffe32e7ec23f592e21c508b5108899ad393059 Mon Sep 17 00:00:00 2001
2 From: Zhanyong Wang <zhanyong.wang@mediatek.com>
3 Date: Tue, 25 Jan 2022 16:50:47 +0800
4 Subject: [PATCH 4/5] phy: phy-mtk-tphy: Add PCIe 2 lane efuse support
6 Add PCIe 2 lane efuse support in tphy driver.
8 Signed-off-by: Jie Yang <jieyy.yang@mediatek.com>
9 Signed-off-by: Zhanyong Wang <zhanyong.wang@mediatek.com>
11 drivers/phy/mediatek/phy-mtk-tphy.c | 140 ++++++++++++++++++++++++++++
12 1 file changed, 140 insertions(+)
14 --- a/drivers/phy/mediatek/phy-mtk-tphy.c
15 +++ b/drivers/phy/mediatek/phy-mtk-tphy.c
17 #define SSUSB_SIFSLV_V2_U3PHYD 0x200
18 #define SSUSB_SIFSLV_V2_U3PHYA 0x400
20 +/* version V4 sub-banks offset base address */
22 +#define SSUSB_SIFSLV_V4_SPLLC 0x000
23 +#define SSUSB_SIFSLV_V4_CHIP 0x100
24 +#define SSUSB_SIFSLV_V4_U3PHYD 0x900
25 +#define SSUSB_SIFSLV_V4_U3PHYA 0xb00
27 +#define SSUSB_LN1_OFFSET 0x10000
29 #define U3P_MISC_REG1 0x04
30 #define MR1_EFUSE_AUTO_LOAD_DIS BIT(6)
32 @@ -320,6 +329,7 @@ enum mtk_phy_version {
39 struct mtk_phy_pdata {
40 @@ -369,6 +379,9 @@ struct mtk_phy_instance {
45 + u32 efuse_tx_imp_ln1;
46 + u32 efuse_rx_imp_ln1;
50 @@ -946,6 +959,36 @@ static void phy_v2_banks_init(struct mtk
54 +static void phy_v4_banks_init(struct mtk_tphy *tphy,
55 + struct mtk_phy_instance *instance)
57 + struct u2phy_banks *u2_banks = &instance->u2_banks;
58 + struct u3phy_banks *u3_banks = &instance->u3_banks;
60 + switch (instance->type) {
62 + u2_banks->misc = instance->port_base + SSUSB_SIFSLV_V2_MISC;
63 + u2_banks->fmreg = instance->port_base + SSUSB_SIFSLV_V2_U2FREQ;
64 + u2_banks->com = instance->port_base + SSUSB_SIFSLV_V2_U2PHY_COM;
67 + u3_banks->spllc = instance->port_base + SSUSB_SIFSLV_V2_SPLLC;
68 + u3_banks->chip = instance->port_base + SSUSB_SIFSLV_V2_CHIP;
69 + u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V2_U3PHYD;
70 + u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V2_U3PHYA;
73 + u3_banks->spllc = instance->port_base + SSUSB_SIFSLV_V4_SPLLC;
74 + u3_banks->chip = instance->port_base + SSUSB_SIFSLV_V4_CHIP;
75 + u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V4_U3PHYD;
76 + u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V4_U3PHYA;
79 + dev_err(tphy->dev, "incompatible PHY type\n");
84 static void phy_parse_property(struct mtk_tphy *tphy,
85 struct mtk_phy_instance *instance)
87 @@ -1144,6 +1187,40 @@ static int phy_efuse_get(struct mtk_tphy
89 dev_dbg(dev, "u3 efuse - intr %x, rx_imp %x, tx_imp %x\n",
90 instance->efuse_intr, instance->efuse_rx_imp,instance->efuse_tx_imp);
92 + if (tphy->pdata->version != MTK_PHY_V4)
95 + ret = nvmem_cell_read_variable_le_u32(dev, "intr_ln1", &instance->efuse_intr_ln1);
97 + dev_err(dev, "fail to get u3 lane1 intr efuse, %d\n", ret);
101 + ret = nvmem_cell_read_variable_le_u32(dev, "rx_imp_ln1", &instance->efuse_rx_imp_ln1);
103 + dev_err(dev, "fail to get u3 lane1 rx_imp efuse, %d\n", ret);
107 + ret = nvmem_cell_read_variable_le_u32(dev, "tx_imp_ln1", &instance->efuse_tx_imp_ln1);
109 + dev_err(dev, "fail to get u3 lane1 tx_imp efuse, %d\n", ret);
113 + /* no efuse, ignore it */
114 + if (!instance->efuse_intr_ln1 &&
115 + !instance->efuse_rx_imp_ln1 &&
116 + !instance->efuse_tx_imp_ln1) {
117 + dev_warn(dev, "no u3 lane1 efuse, but dts enable it\n");
118 + instance->efuse_sw_en = 0;
122 + dev_info(dev, "u3 lane1 efuse - intr %x, rx_imp %x, tx_imp %x\n",
123 + instance->efuse_intr_ln1, instance->efuse_rx_imp_ln1,
124 + instance->efuse_tx_imp_ln1);
127 dev_err(dev, "no sw efuse for type %d\n", instance->type);
128 @@ -1175,6 +1252,31 @@ static void phy_efuse_set(struct mtk_phy
129 writel(tmp, u2_banks->com + U3P_USBPHYACR1);
132 + tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RSV);
133 + tmp |= P3D_RG_EFUSE_AUTO_LOAD_DIS;
134 + writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RSV);
136 + tmp = readl(u3_banks->phyd + U3P_U3_PHYD_IMPCAL0);
137 + tmp &= ~P3D_RG_TX_IMPEL;
138 + tmp |= P3D_RG_TX_IMPEL_VAL(instance->efuse_tx_imp);
139 + tmp |= P3D_RG_FORCE_TX_IMPEL;
140 + writel(tmp, u3_banks->phyd + U3P_U3_PHYD_IMPCAL0);
142 + tmp = readl(u3_banks->phyd + U3P_U3_PHYD_IMPCAL1);
143 + tmp &= ~P3D_RG_RX_IMPEL;
144 + tmp |= P3D_RG_RX_IMPEL_VAL(instance->efuse_rx_imp);
145 + tmp |= P3D_RG_FORCE_RX_IMPEL;
146 + writel(tmp, u3_banks->phyd + U3P_U3_PHYD_IMPCAL1);
148 + tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG0);
149 + tmp &= ~P3A_RG_IEXT_INTR;
150 + tmp |= P3A_RG_IEXT_INTR_VAL(instance->efuse_intr);
151 + writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG0);
152 + pr_err("%s set efuse, tx_imp %x, rx_imp %x intr %x\n",
153 + __func__, instance->efuse_tx_imp,
154 + instance->efuse_rx_imp, instance->efuse_intr);
158 tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RSV);
159 tmp |= P3D_RG_EFUSE_AUTO_LOAD_DIS;
160 @@ -1196,6 +1298,34 @@ static void phy_efuse_set(struct mtk_phy
161 tmp &= ~P3A_RG_IEXT_INTR;
162 tmp |= P3A_RG_IEXT_INTR_VAL(instance->efuse_intr);
163 writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG0);
164 + if (!instance->efuse_intr_ln1 &&
165 + !instance->efuse_rx_imp_ln1 &&
166 + !instance->efuse_tx_imp_ln1)
169 + tmp = readl(u3_banks->phyd + SSUSB_LN1_OFFSET + U3P_U3_PHYD_RSV);
170 + tmp |= P3D_RG_EFUSE_AUTO_LOAD_DIS;
171 + writel(tmp, u3_banks->phyd + SSUSB_LN1_OFFSET + U3P_U3_PHYD_RSV);
173 + tmp = readl(u3_banks->phyd + SSUSB_LN1_OFFSET + U3P_U3_PHYD_IMPCAL0);
174 + tmp &= ~P3D_RG_TX_IMPEL;
175 + tmp |= P3D_RG_TX_IMPEL_VAL(instance->efuse_tx_imp_ln1);
176 + tmp |= P3D_RG_FORCE_TX_IMPEL;
177 + writel(tmp, u3_banks->phyd + SSUSB_LN1_OFFSET + U3P_U3_PHYD_IMPCAL0);
179 + tmp = readl(u3_banks->phyd + SSUSB_LN1_OFFSET + U3P_U3_PHYD_IMPCAL1);
180 + tmp &= ~P3D_RG_RX_IMPEL;
181 + tmp |= P3D_RG_RX_IMPEL_VAL(instance->efuse_rx_imp_ln1);
182 + tmp |= P3D_RG_FORCE_RX_IMPEL;
183 + writel(tmp, u3_banks->phyd + SSUSB_LN1_OFFSET + U3P_U3_PHYD_IMPCAL1);
185 + tmp = readl(u3_banks->phya + SSUSB_LN1_OFFSET + U3P_U3_PHYA_REG0);
186 + tmp &= ~P3A_RG_IEXT_INTR;
187 + tmp |= P3A_RG_IEXT_INTR_VAL(instance->efuse_intr_ln1);
188 + writel(tmp, u3_banks->phya + SSUSB_LN1_OFFSET + U3P_U3_PHYA_REG0);
189 + dev_info(dev, "%s set LN1 efuse, tx_imp %x, rx_imp %x intr %x\n",
190 + __func__, instance->efuse_tx_imp_ln1,
191 + instance->efuse_rx_imp_ln1, instance->efuse_intr_ln1);
194 dev_warn(dev, "no sw efuse for type %d\n", instance->type);
195 @@ -1335,6 +1465,9 @@ static struct phy *mtk_phy_xlate(struct
197 phy_v2_banks_init(tphy, instance);
200 + phy_v4_banks_init(tphy, instance);
203 dev_err(dev, "phy version is not supported\n");
204 return ERR_PTR(-EINVAL);
205 @@ -1375,6 +1508,12 @@ static const struct mtk_phy_pdata tphy_v
206 .version = MTK_PHY_V3,
209 +static const struct mtk_phy_pdata tphy_v4_pdata = {
210 + .avoid_rx_sen_degradation = false,
211 + .sw_efuse_supported = true,
212 + .version = MTK_PHY_V4,
215 static const struct mtk_phy_pdata mt8173_pdata = {
216 .avoid_rx_sen_degradation = true,
217 .version = MTK_PHY_V1,
218 @@ -1394,6 +1533,7 @@ static const struct of_device_id mtk_tph
219 { .compatible = "mediatek,generic-tphy-v1", .data = &tphy_v1_pdata },
220 { .compatible = "mediatek,generic-tphy-v2", .data = &tphy_v2_pdata },
221 { .compatible = "mediatek,generic-tphy-v3", .data = &tphy_v3_pdata },
222 + { .compatible = "mediatek,generic-tphy-v4", .data = &tphy_v4_pdata },
225 MODULE_DEVICE_TABLE(of, mtk_tphy_id_table);