1 From 1d5819e90f2ef6dead11809744372a9863227a92 Mon Sep 17 00:00:00 2001
2 From: Zhanyong Wang <zhanyong.wang@mediatek.com>
3 Date: Tue, 25 Jan 2022 19:03:34 +0800
4 Subject: [PATCH 5/5] phy: phy-mtk-tphy: add auto-load-valid check mechanism
7 add auto-load-valid check mechanism support
9 Signed-off-by: Zhanyong Wang <zhanyong.wang@mediatek.com>
11 drivers/phy/mediatek/phy-mtk-tphy.c | 67 +++++++++++++++++++++++++++--
12 1 file changed, 64 insertions(+), 3 deletions(-)
14 --- a/drivers/phy/mediatek/phy-mtk-tphy.c
15 +++ b/drivers/phy/mediatek/phy-mtk-tphy.c
16 @@ -376,9 +376,13 @@ struct mtk_phy_instance {
21 + u32 efuse_autoloadvalid;
25 + bool efuse_alv_ln1_en;
26 + u32 efuse_ln1_autoloadvalid;
30 @@ -1126,6 +1130,7 @@ static int phy_efuse_get(struct mtk_tphy
32 struct device *dev = &instance->phy->dev;
36 /* tphy v1 doesn't support sw efuse, skip it */
37 if (!tphy->pdata->sw_efuse_supported) {
38 @@ -1140,6 +1145,20 @@ static int phy_efuse_get(struct mtk_tphy
40 switch (instance->type) {
42 + alv = of_property_read_bool(dev->of_node, "auto_load_valid");
44 + instance->efuse_alv_en = alv;
45 + ret = nvmem_cell_read_variable_le_u32(dev, "auto_load_valid",
46 + &instance->efuse_autoloadvalid);
48 + dev_err(dev, "fail to get u2 alv efuse, %d\n", ret);
52 + "u2 auto load valid efuse: ENABLE with value: %u\n",
53 + instance->efuse_autoloadvalid);
56 ret = nvmem_cell_read_variable_le_u32(dev, "intr", &instance->efuse_intr);
58 dev_err(dev, "fail to get u2 intr efuse, %d\n", ret);
59 @@ -1158,6 +1177,20 @@ static int phy_efuse_get(struct mtk_tphy
63 + alv = of_property_read_bool(dev->of_node, "auto_load_valid");
65 + instance->efuse_alv_en = alv;
66 + ret = nvmem_cell_read_variable_le_u32(dev, "auto_load_valid",
67 + &instance->efuse_autoloadvalid);
69 + dev_err(dev, "fail to get u3(pcei) alv efuse, %d\n", ret);
73 + "u3 auto load valid efuse: ENABLE with value: %u\n",
74 + instance->efuse_autoloadvalid);
77 ret = nvmem_cell_read_variable_le_u32(dev, "intr", &instance->efuse_intr);
79 dev_err(dev, "fail to get u3 intr efuse, %d\n", ret);
80 @@ -1191,6 +1224,20 @@ static int phy_efuse_get(struct mtk_tphy
81 if (tphy->pdata->version != MTK_PHY_V4)
84 + alv = of_property_read_bool(dev->of_node, "auto_load_valid_ln1");
86 + instance->efuse_alv_ln1_en = alv;
87 + ret = nvmem_cell_read_variable_le_u32(dev, "auto_load_valid_ln1",
88 + &instance->efuse_ln1_autoloadvalid);
90 + dev_err(dev, "fail to get pcie auto_load_valid efuse, %d\n", ret);
94 + "pcie auto load valid efuse: ENABLE with value: %u\n",
95 + instance->efuse_ln1_autoloadvalid);
98 ret = nvmem_cell_read_variable_le_u32(dev, "intr_ln1", &instance->efuse_intr_ln1);
100 dev_err(dev, "fail to get u3 lane1 intr efuse, %d\n", ret);
101 @@ -1242,6 +1289,10 @@ static void phy_efuse_set(struct mtk_phy
103 switch (instance->type) {
105 + if (instance->efuse_alv_en &&
106 + instance->efuse_autoloadvalid == 1)
109 tmp = readl(u2_banks->misc + U3P_MISC_REG1);
110 tmp |= MR1_EFUSE_AUTO_LOAD_DIS;
111 writel(tmp, u2_banks->misc + U3P_MISC_REG1);
112 @@ -1252,6 +1303,10 @@ static void phy_efuse_set(struct mtk_phy
113 writel(tmp, u2_banks->com + U3P_USBPHYACR1);
116 + if (instance->efuse_alv_en &&
117 + instance->efuse_autoloadvalid == 1)
120 tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RSV);
121 tmp |= P3D_RG_EFUSE_AUTO_LOAD_DIS;
122 writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RSV);
123 @@ -1278,6 +1333,10 @@ static void phy_efuse_set(struct mtk_phy
127 + if (instance->efuse_alv_en &&
128 + instance->efuse_autoloadvalid == 1)
131 tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RSV);
132 tmp |= P3D_RG_EFUSE_AUTO_LOAD_DIS;
133 writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RSV);
134 @@ -1298,9 +1357,12 @@ static void phy_efuse_set(struct mtk_phy
135 tmp &= ~P3A_RG_IEXT_INTR;
136 tmp |= P3A_RG_IEXT_INTR_VAL(instance->efuse_intr);
137 writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG0);
138 - if (!instance->efuse_intr_ln1 &&
139 - !instance->efuse_rx_imp_ln1 &&
140 - !instance->efuse_tx_imp_ln1)
142 + if ((!instance->efuse_intr_ln1 &&
143 + !instance->efuse_rx_imp_ln1 &&
144 + !instance->efuse_tx_imp_ln1) ||
145 + (instance->efuse_alv_ln1_en &&
146 + instance->efuse_ln1_autoloadvalid == 1))
149 tmp = readl(u3_banks->phyd + SSUSB_LN1_OFFSET + U3P_U3_PHYD_RSV);