target/linux/mediatek/patches-5.15/811-pwm-mediatek-Add-support-for-MT7981.patch

   1 From 947b535ebfe161e1725f1030a09de10d1460371c Mon Sep 17 00:00:00 2001
   2 From: Daniel Golle <daniel@makrotopia.org>
   3 Date: Mon, 23 Jan 2023 20:47:34 +0000
   4 Subject: [PATCH] pwm: mediatek: Add support for MT7981
   5
   6 The PWM unit on MT7981 uses different register offsets than previous
   7 MediaTek PWM units. Add support for these new offsets and add support
   8 for PWM on MT7981 which has 3 PWM channels, one of them is typically
   9 used for a temperature controlled fan.
  10
  11 Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  12 ---
  13  drivers/pwm/pwm-mediatek.c | 54 ++++++++++++++++++++++++++++++++------
  14  1 file changed, 46 insertions(+), 8 deletions(-)
  15
  16 --- a/drivers/pwm/pwm-mediatek.c
  17 +++ b/drivers/pwm/pwm-mediatek.c
  18 @@ -34,10 +34,14 @@
  19
  20  #define PWM_CLK_DIV_MAX                7
  21
  22 +#define REG_V1                 1
  23 +#define REG_V2                 2
  24 +
  25  struct pwm_mediatek_of_data {
  26         unsigned int num_pwms;
  27         bool pwm45_fixup;
  28         bool has_ck_26m_sel;
  29 +       u8 reg_ver;
  30  };
  31
  32  /**
  33 @@ -59,10 +63,14 @@ struct pwm_mediatek_chip {
  34         const struct pwm_mediatek_of_data *soc;
  35  };
  36
  37 -static const unsigned int pwm_mediatek_reg_offset[] = {
  38 +static const unsigned int mtk_pwm_reg_offset_v1[] = {
  39         0x0010, 0x0050, 0x0090, 0x00d0, 0x0110, 0x0150, 0x0190, 0x0220
  40  };
  41
  42 +static const unsigned int mtk_pwm_reg_offset_v2[] = {
  43 +       0x0080, 0x00c0, 0x0100, 0x0140, 0x0180, 0x1c0, 0x200, 0x0240
  44 +};
  45 +
  46  static inline struct pwm_mediatek_chip *
  47  to_pwm_mediatek_chip(struct pwm_chip *chip)
  48  {
  49 @@ -111,7 +119,19 @@ static inline void pwm_mediatek_writel(s
  50                                        unsigned int num, unsigned int offset,
  51                                        u32 value)
  52  {
  53 -       writel(value, chip->regs + pwm_mediatek_reg_offset[num] + offset);
  54 +       u32 pwm_offset;
  55 +
  56 +       switch (chip->soc->reg_ver) {
  57 +       case REG_V2:
  58 +               pwm_offset = mtk_pwm_reg_offset_v2[num];
  59 +               break;
  60 +
  61 +       case REG_V1:
  62 +       default:
  63 +               pwm_offset = mtk_pwm_reg_offset_v1[num];
  64 +       }
  65 +
  66 +       writel(value, chip->regs + pwm_offset + offset);
  67  }
  68
  69  static int pwm_mediatek_config(struct pwm_chip *chip, struct pwm_device *pwm,
  70 @@ -146,7 +166,7 @@ static int pwm_mediatek_config(struct pw
  71
  72         if (clkdiv > PWM_CLK_DIV_MAX) {
  73                 pwm_mediatek_clk_disable(chip, pwm);
  74 -               dev_err(chip->dev, "period %d not supported\n", period_ns);
  75 +               dev_err(chip->dev, "period of %d ns not supported\n", period_ns);
  76                 return -EINVAL;
  77         }
  78
  79 @@ -221,24 +241,20 @@ static int pwm_mediatek_probe(struct pla
  80         if (IS_ERR(pc->regs))
  81                 return PTR_ERR(pc->regs);
  82
  83 -       pc->clk_pwms = devm_kcalloc(&pdev->dev, pc->soc->num_pwms,
  84 +       pc->clk_pwms = devm_kmalloc_array(&pdev->dev, pc->soc->num_pwms,
  85                                     sizeof(*pc->clk_pwms), GFP_KERNEL);
  86         if (!pc->clk_pwms)
  87                 return -ENOMEM;
  88
  89         pc->clk_top = devm_clk_get(&pdev->dev, "top");
  90 -       if (IS_ERR(pc->clk_top)) {
  91 -               dev_err(&pdev->dev, "clock: top fail: %ld\n",
  92 -                       PTR_ERR(pc->clk_top));
  93 -               return PTR_ERR(pc->clk_top);
  94 -       }
  95 +       if (IS_ERR(pc->clk_top))
  96 +               return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk_top),
  97 +                                    "Failed to get top clock\n");
  98
  99         pc->clk_main = devm_clk_get(&pdev->dev, "main");
 100 -       if (IS_ERR(pc->clk_main)) {
 101 -               dev_err(&pdev->dev, "clock: main fail: %ld\n",
 102 -                       PTR_ERR(pc->clk_main));
 103 -               return PTR_ERR(pc->clk_main);
 104 -       }
 105 +       if (IS_ERR(pc->clk_main))
 106 +               return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk_main),
 107 +                                    "Failed to get main clock\n");
 108
 109         for (i = 0; i < pc->soc->num_pwms; i++) {
 110                 char name[8];
 111 @@ -246,11 +262,9 @@ static int pwm_mediatek_probe(struct pla
 112                 snprintf(name, sizeof(name), "pwm%d", i + 1);
 113
 114                 pc->clk_pwms[i] = devm_clk_get(&pdev->dev, name);
 115 -               if (IS_ERR(pc->clk_pwms[i])) {
 116 -                       dev_err(&pdev->dev, "clock: %s fail: %ld\n",
 117 -                               name, PTR_ERR(pc->clk_pwms[i]));
 118 -                       return PTR_ERR(pc->clk_pwms[i]);
 119 -               }
 120 +               if (IS_ERR(pc->clk_pwms[i]))
 121 +                       return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk_pwms[i]),
 122 +                                            "Failed to get %s clock\n", name);
 123         }
 124
 125         pc->chip.dev = &pdev->dev;
 126 @@ -258,10 +272,8 @@ static int pwm_mediatek_probe(struct pla
 127         pc->chip.npwm = pc->soc->num_pwms;
 128
 129         ret = devm_pwmchip_add(&pdev->dev, &pc->chip);
 130 -       if (ret < 0) {
 131 -               dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
 132 -               return ret;
 133 -       }
 134 +       if (ret < 0)
 135 +               return dev_err_probe(&pdev->dev, ret, "pwmchip_add() failed\n");
 136
 137         return 0;
 138  }
 139 @@ -270,48 +282,63 @@ static const struct pwm_mediatek_of_data
 140         .num_pwms = 8,
 141         .pwm45_fixup = false,
 142         .has_ck_26m_sel = false,
 143 +       .reg_ver = REG_V1,
 144  };
 145
 146  static const struct pwm_mediatek_of_data mt7622_pwm_data = {
 147         .num_pwms = 6,
 148         .pwm45_fixup = false,
 149         .has_ck_26m_sel = true,
 150 +       .reg_ver = REG_V1,
 151  };
 152
 153  static const struct pwm_mediatek_of_data mt7623_pwm_data = {
 154         .num_pwms = 5,
 155         .pwm45_fixup = true,
 156         .has_ck_26m_sel = false,
 157 +       .reg_ver = REG_V1,
 158  };
 159
 160  static const struct pwm_mediatek_of_data mt7628_pwm_data = {
 161         .num_pwms = 4,
 162         .pwm45_fixup = true,
 163         .has_ck_26m_sel = false,
 164 +       .reg_ver = REG_V1,
 165  };
 166
 167  static const struct pwm_mediatek_of_data mt7629_pwm_data = {
 168         .num_pwms = 1,
 169         .pwm45_fixup = false,
 170         .has_ck_26m_sel = false,
 171 +       .reg_ver = REG_V1,
 172  };
 173
 174 -static const struct pwm_mediatek_of_data mt8183_pwm_data = {
 175 -       .num_pwms = 4,
 176 +static const struct pwm_mediatek_of_data mt7981_pwm_data = {
 177 +       .num_pwms = 3,
 178         .pwm45_fixup = false,
 179         .has_ck_26m_sel = true,
 180 +       .reg_ver = REG_V2,
 181  };
 182
 183  static const struct pwm_mediatek_of_data mt7986_pwm_data = {
 184         .num_pwms = 2,
 185         .pwm45_fixup = false,
 186         .has_ck_26m_sel = true,
 187 +       .reg_ver = REG_V1,
 188 +};
 189 +
 190 +static const struct pwm_mediatek_of_data mt8183_pwm_data = {
 191 +       .num_pwms = 4,
 192 +       .pwm45_fixup = false,
 193 +       .has_ck_26m_sel = true,
 194 +       .reg_ver = REG_V1,
 195  };
 196
 197  static const struct pwm_mediatek_of_data mt8516_pwm_data = {
 198         .num_pwms = 5,
 199         .pwm45_fixup = false,
 200         .has_ck_26m_sel = true,
 201 +       .reg_ver = REG_V1,
 202  };
 203
 204  static const struct of_device_id pwm_mediatek_of_match[] = {
 205 @@ -320,6 +347,7 @@ static const struct of_device_id pwm_med
 206         { .compatible = "mediatek,mt7623-pwm", .data = &mt7623_pwm_data },
 207         { .compatible = "mediatek,mt7628-pwm", .data = &mt7628_pwm_data },
 208         { .compatible = "mediatek,mt7629-pwm", .data = &mt7629_pwm_data },
 209 +       { .compatible = "mediatek,mt7981-pwm", .data = &mt7981_pwm_data },
 210         { .compatible = "mediatek,mt7986-pwm", .data = &mt7986_pwm_data },
 211         { .compatible = "mediatek,mt8183-pwm", .data = &mt8183_pwm_data },
 212         { .compatible = "mediatek,mt8516-pwm", .data = &mt8516_pwm_data },