1 From fc7776dee86bc07d22820a904760a95f49a2f12e Mon Sep 17 00:00:00 2001
2 From: Maso Huang <maso.huang@mediatek.com>
3 Date: Thu, 17 Aug 2023 18:13:35 +0800
4 Subject: [PATCH 3/9] ASoC: mediatek: mt7986: add platform driver
6 Add mt7986 platform driver.
8 Signed-off-by: Maso Huang <maso.huang@mediatek.com>
9 Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
10 Link: https://lore.kernel.org/r/20230817101338.18782-4-maso.huang@mediatek.com
11 Signed-off-by: Mark Brown <broonie@kernel.org>
13 sound/soc/mediatek/Kconfig | 10 +
14 sound/soc/mediatek/Makefile | 1 +
15 sound/soc/mediatek/mt7986/Makefile | 8 +
16 sound/soc/mediatek/mt7986/mt7986-afe-pcm.c | 622 +++++++++++++++++++++
17 4 files changed, 641 insertions(+)
18 create mode 100644 sound/soc/mediatek/mt7986/Makefile
19 create mode 100644 sound/soc/mediatek/mt7986/mt7986-afe-pcm.c
21 --- a/sound/soc/mediatek/Kconfig
22 +++ b/sound/soc/mediatek/Kconfig
23 @@ -54,6 +54,16 @@ config SND_SOC_MT6797_MT6351
24 Select Y if you have such device.
27 +config SND_SOC_MT7986
28 + tristate "ASoC support for Mediatek MT7986 chip"
29 + depends on ARCH_MEDIATEK
30 + select SND_SOC_MEDIATEK
32 + This adds ASoC platform driver support for MediaTek MT7986 chip
33 + that can be used with other codecs.
34 + Select Y if you have such device.
35 + If unsure select "N".
38 tristate "ASoC support for Mediatek MT8173 chip"
39 depends on ARCH_MEDIATEK
40 --- a/sound/soc/mediatek/Makefile
41 +++ b/sound/soc/mediatek/Makefile
43 obj-$(CONFIG_SND_SOC_MEDIATEK) += common/
44 obj-$(CONFIG_SND_SOC_MT2701) += mt2701/
45 obj-$(CONFIG_SND_SOC_MT6797) += mt6797/
46 +obj-$(CONFIG_SND_SOC_MT7986) += mt7986/
47 obj-$(CONFIG_SND_SOC_MT8173) += mt8173/
48 obj-$(CONFIG_SND_SOC_MT8183) += mt8183/
49 obj-$(CONFIG_SND_SOC_MT8192) += mt8192/
51 +++ b/sound/soc/mediatek/mt7986/Makefile
53 +# SPDX-License-Identifier: GPL-2.0
56 +snd-soc-mt7986-afe-objs := \
60 +obj-$(CONFIG_SND_SOC_MT7986) += snd-soc-mt7986-afe.o
62 +++ b/sound/soc/mediatek/mt7986/mt7986-afe-pcm.c
64 +// SPDX-License-Identifier: GPL-2.0
66 + * MediaTek ALSA SoC AFE platform driver for MT7986
68 + * Copyright (c) 2023 MediaTek Inc.
69 + * Authors: Vic Wu <vic.wu@mediatek.com>
70 + * Maso Huang <maso.huang@mediatek.com>
73 +#include <linux/clk.h>
74 +#include <linux/delay.h>
75 +#include <linux/module.h>
76 +#include <linux/of.h>
77 +#include <linux/of_address.h>
78 +#include <linux/pm_runtime.h>
80 +#include "mt7986-afe-common.h"
81 +#include "mt7986-reg.h"
82 +#include "../common/mtk-afe-platform-driver.h"
83 +#include "../common/mtk-afe-fe-dai.h"
86 + MTK_AFE_RATE_8K = 0,
87 + MTK_AFE_RATE_11K = 1,
88 + MTK_AFE_RATE_12K = 2,
89 + MTK_AFE_RATE_16K = 4,
90 + MTK_AFE_RATE_22K = 5,
91 + MTK_AFE_RATE_24K = 6,
92 + MTK_AFE_RATE_32K = 8,
93 + MTK_AFE_RATE_44K = 9,
94 + MTK_AFE_RATE_48K = 10,
95 + MTK_AFE_RATE_88K = 13,
96 + MTK_AFE_RATE_96K = 14,
97 + MTK_AFE_RATE_176K = 17,
98 + MTK_AFE_RATE_192K = 18,
102 + CLK_INFRA_AUD_BUS_CK = 0,
103 + CLK_INFRA_AUD_26M_CK,
104 + CLK_INFRA_AUD_L_CK,
105 + CLK_INFRA_AUD_AUD_CK,
106 + CLK_INFRA_AUD_EG2_CK,
110 +static const char *aud_clks[CLK_NUM] = {
111 + [CLK_INFRA_AUD_BUS_CK] = "aud_bus_ck",
112 + [CLK_INFRA_AUD_26M_CK] = "aud_26m_ck",
113 + [CLK_INFRA_AUD_L_CK] = "aud_l_ck",
114 + [CLK_INFRA_AUD_AUD_CK] = "aud_aud_ck",
115 + [CLK_INFRA_AUD_EG2_CK] = "aud_eg2_ck",
118 +unsigned int mt7986_afe_rate_transform(struct device *dev, unsigned int rate)
122 + return MTK_AFE_RATE_8K;
124 + return MTK_AFE_RATE_11K;
126 + return MTK_AFE_RATE_12K;
128 + return MTK_AFE_RATE_16K;
130 + return MTK_AFE_RATE_22K;
132 + return MTK_AFE_RATE_24K;
134 + return MTK_AFE_RATE_32K;
136 + return MTK_AFE_RATE_44K;
138 + return MTK_AFE_RATE_48K;
140 + return MTK_AFE_RATE_88K;
142 + return MTK_AFE_RATE_96K;
144 + return MTK_AFE_RATE_176K;
146 + return MTK_AFE_RATE_192K;
148 + dev_warn(dev, "%s(), rate %u invalid, using %d!!!\n",
149 + __func__, rate, MTK_AFE_RATE_48K);
150 + return MTK_AFE_RATE_48K;
154 +static const struct snd_pcm_hardware mt7986_afe_hardware = {
155 + .info = SNDRV_PCM_INFO_MMAP |
156 + SNDRV_PCM_INFO_INTERLEAVED |
157 + SNDRV_PCM_INFO_MMAP_VALID,
158 + .formats = SNDRV_PCM_FMTBIT_S16_LE |
159 + SNDRV_PCM_FMTBIT_S24_LE |
160 + SNDRV_PCM_FMTBIT_S32_LE,
161 + .period_bytes_min = 256,
162 + .period_bytes_max = 4 * 48 * 1024,
164 + .periods_max = 256,
165 + .buffer_bytes_max = 8 * 48 * 1024,
169 +static int mt7986_memif_fs(struct snd_pcm_substream *substream,
172 + struct snd_soc_pcm_runtime *rtd = substream->private_data;
173 + struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
174 + struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
176 + return mt7986_afe_rate_transform(afe->dev, rate);
179 +static int mt7986_irq_fs(struct snd_pcm_substream *substream,
182 + struct snd_soc_pcm_runtime *rtd = substream->private_data;
183 + struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
184 + struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
186 + return mt7986_afe_rate_transform(afe->dev, rate);
189 +#define MTK_PCM_RATES (SNDRV_PCM_RATE_8000_48000 |\
190 + SNDRV_PCM_RATE_88200 |\
191 + SNDRV_PCM_RATE_96000 |\
192 + SNDRV_PCM_RATE_176400 |\
193 + SNDRV_PCM_RATE_192000)
195 +#define MTK_PCM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
196 + SNDRV_PCM_FMTBIT_S24_LE |\
197 + SNDRV_PCM_FMTBIT_S32_LE)
199 +static struct snd_soc_dai_driver mt7986_memif_dai_driver[] = {
200 + /* FE DAIs: memory intefaces to CPU */
203 + .id = MT7986_MEMIF_DL1,
205 + .stream_name = "DL1",
208 + .rates = MTK_PCM_RATES,
209 + .formats = MTK_PCM_FORMATS,
211 + .ops = &mtk_afe_fe_ops,
215 + .id = MT7986_MEMIF_VUL12,
217 + .stream_name = "UL1",
220 + .rates = MTK_PCM_RATES,
221 + .formats = MTK_PCM_FORMATS,
223 + .ops = &mtk_afe_fe_ops,
227 +static const struct snd_kcontrol_new o018_mix[] = {
228 + SOC_DAPM_SINGLE_AUTODISABLE("I150_Switch", AFE_CONN018_4, 22, 1, 0),
231 +static const struct snd_kcontrol_new o019_mix[] = {
232 + SOC_DAPM_SINGLE_AUTODISABLE("I151_Switch", AFE_CONN019_4, 23, 1, 0),
235 +static const struct snd_soc_dapm_widget mt7986_memif_widgets[] = {
237 + SND_SOC_DAPM_MIXER("I032", SND_SOC_NOPM, 0, 0, NULL, 0),
238 + SND_SOC_DAPM_MIXER("I033", SND_SOC_NOPM, 0, 0, NULL, 0),
241 + SND_SOC_DAPM_MIXER("O018", SND_SOC_NOPM, 0, 0,
242 + o018_mix, ARRAY_SIZE(o018_mix)),
243 + SND_SOC_DAPM_MIXER("O019", SND_SOC_NOPM, 0, 0,
244 + o019_mix, ARRAY_SIZE(o019_mix)),
247 +static const struct snd_soc_dapm_route mt7986_memif_routes[] = {
248 + {"I032", NULL, "DL1"},
249 + {"I033", NULL, "DL1"},
250 + {"UL1", NULL, "O018"},
251 + {"UL1", NULL, "O019"},
252 + {"O018", "I150_Switch", "I150"},
253 + {"O019", "I151_Switch", "I151"},
256 +static const struct snd_soc_component_driver mt7986_afe_pcm_dai_component = {
257 + .name = "mt7986-afe-pcm-dai",
260 +static const struct mtk_base_memif_data memif_data[MT7986_MEMIF_NUM] = {
261 + [MT7986_MEMIF_DL1] = {
263 + .id = MT7986_MEMIF_DL1,
264 + .reg_ofs_base = AFE_DL0_BASE,
265 + .reg_ofs_cur = AFE_DL0_CUR,
266 + .reg_ofs_end = AFE_DL0_END,
267 + .reg_ofs_base_msb = AFE_DL0_BASE_MSB,
268 + .reg_ofs_cur_msb = AFE_DL0_CUR_MSB,
269 + .reg_ofs_end_msb = AFE_DL0_END_MSB,
270 + .fs_reg = AFE_DL0_CON0,
271 + .fs_shift = DL0_MODE_SFT,
272 + .fs_maskbit = DL0_MODE_MASK,
273 + .mono_reg = AFE_DL0_CON0,
274 + .mono_shift = DL0_MONO_SFT,
275 + .enable_reg = AFE_DL0_CON0,
276 + .enable_shift = DL0_ON_SFT,
277 + .hd_reg = AFE_DL0_CON0,
278 + .hd_shift = DL0_HD_MODE_SFT,
279 + .hd_align_reg = AFE_DL0_CON0,
280 + .hd_align_mshift = DL0_HALIGN_SFT,
281 + .pbuf_reg = AFE_DL0_CON0,
282 + .pbuf_shift = DL0_PBUF_SIZE_SFT,
283 + .minlen_reg = AFE_DL0_CON0,
284 + .minlen_shift = DL0_MINLEN_SFT,
286 + [MT7986_MEMIF_VUL12] = {
288 + .id = MT7986_MEMIF_VUL12,
289 + .reg_ofs_base = AFE_VUL0_BASE,
290 + .reg_ofs_cur = AFE_VUL0_CUR,
291 + .reg_ofs_end = AFE_VUL0_END,
292 + .reg_ofs_base_msb = AFE_VUL0_BASE_MSB,
293 + .reg_ofs_cur_msb = AFE_VUL0_CUR_MSB,
294 + .reg_ofs_end_msb = AFE_VUL0_END_MSB,
295 + .fs_reg = AFE_VUL0_CON0,
296 + .fs_shift = VUL0_MODE_SFT,
297 + .fs_maskbit = VUL0_MODE_MASK,
298 + .mono_reg = AFE_VUL0_CON0,
299 + .mono_shift = VUL0_MONO_SFT,
300 + .enable_reg = AFE_VUL0_CON0,
301 + .enable_shift = VUL0_ON_SFT,
302 + .hd_reg = AFE_VUL0_CON0,
303 + .hd_shift = VUL0_HD_MODE_SFT,
304 + .hd_align_reg = AFE_VUL0_CON0,
305 + .hd_align_mshift = VUL0_HALIGN_SFT,
309 +static const struct mtk_base_irq_data irq_data[MT7986_IRQ_NUM] = {
311 + .id = MT7986_IRQ_0,
312 + .irq_cnt_reg = AFE_IRQ0_MCU_CFG1,
313 + .irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
314 + .irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
315 + .irq_fs_reg = AFE_IRQ0_MCU_CFG0,
316 + .irq_fs_shift = IRQ_MCU_MODE_SFT,
317 + .irq_fs_maskbit = IRQ_MCU_MODE_MASK,
318 + .irq_en_reg = AFE_IRQ0_MCU_CFG0,
319 + .irq_en_shift = IRQ_MCU_ON_SFT,
320 + .irq_clr_reg = AFE_IRQ_MCU_CLR,
321 + .irq_clr_shift = IRQ0_MCU_CLR_SFT,
324 + .id = MT7986_IRQ_1,
325 + .irq_cnt_reg = AFE_IRQ1_MCU_CFG1,
326 + .irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
327 + .irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
328 + .irq_fs_reg = AFE_IRQ1_MCU_CFG0,
329 + .irq_fs_shift = IRQ_MCU_MODE_SFT,
330 + .irq_fs_maskbit = IRQ_MCU_MODE_MASK,
331 + .irq_en_reg = AFE_IRQ1_MCU_CFG0,
332 + .irq_en_shift = IRQ_MCU_ON_SFT,
333 + .irq_clr_reg = AFE_IRQ_MCU_CLR,
334 + .irq_clr_shift = IRQ1_MCU_CLR_SFT,
337 + .id = MT7986_IRQ_2,
338 + .irq_cnt_reg = AFE_IRQ2_MCU_CFG1,
339 + .irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
340 + .irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
341 + .irq_fs_reg = AFE_IRQ2_MCU_CFG0,
342 + .irq_fs_shift = IRQ_MCU_MODE_SFT,
343 + .irq_fs_maskbit = IRQ_MCU_MODE_MASK,
344 + .irq_en_reg = AFE_IRQ2_MCU_CFG0,
345 + .irq_en_shift = IRQ_MCU_ON_SFT,
346 + .irq_clr_reg = AFE_IRQ_MCU_CLR,
347 + .irq_clr_shift = IRQ2_MCU_CLR_SFT,
351 +static bool mt7986_is_volatile_reg(struct device *dev, unsigned int reg)
354 + * Those auto-gen regs are read-only, so put it as volatile because
355 + * volatile registers cannot be cached, which means that they cannot
356 + * be set when power is off
360 + case AFE_DL0_CUR_MSB:
362 + case AFE_DL0_RCH_MON:
363 + case AFE_DL0_LCH_MON:
364 + case AFE_VUL0_CUR_MSB:
366 + case AFE_IRQ_MCU_STATUS:
367 + case AFE_MEMIF_RD_MON:
368 + case AFE_MEMIF_WR_MON:
375 +static const struct regmap_config mt7986_afe_regmap_config = {
379 + .volatile_reg = mt7986_is_volatile_reg,
380 + .max_register = AFE_MAX_REGISTER,
381 + .num_reg_defaults_raw = ((AFE_MAX_REGISTER / 4) + 1),
384 +static int mt7986_init_clock(struct mtk_base_afe *afe)
386 + struct mt7986_afe_private *afe_priv = afe->platform_priv;
389 + afe_priv->clks = devm_kcalloc(afe->dev, CLK_NUM,
390 + sizeof(*afe_priv->clks), GFP_KERNEL);
391 + if (!afe_priv->clks)
393 + afe_priv->num_clks = CLK_NUM;
395 + for (i = 0; i < afe_priv->num_clks; i++)
396 + afe_priv->clks[i].id = aud_clks[i];
398 + ret = devm_clk_bulk_get(afe->dev, afe_priv->num_clks, afe_priv->clks);
400 + return dev_err_probe(afe->dev, ret, "Failed to get clocks\n");
405 +static irqreturn_t mt7986_afe_irq_handler(int irq_id, void *dev)
407 + struct mtk_base_afe *afe = dev;
408 + struct mtk_base_afe_irq *irq;
409 + u32 mcu_en, status, status_mcu;
411 + irqreturn_t irq_ret = IRQ_HANDLED;
413 + /* get irq that is sent to MCU */
414 + regmap_read(afe->regmap, AFE_IRQ_MCU_EN, &mcu_en);
416 + ret = regmap_read(afe->regmap, AFE_IRQ_MCU_STATUS, &status);
417 + /* only care IRQ which is sent to MCU */
418 + status_mcu = status & mcu_en & AFE_IRQ_STATUS_BITS;
420 + if (ret || status_mcu == 0) {
421 + dev_err(afe->dev, "%s(), irq status err, ret %d, status 0x%x, mcu_en 0x%x\n",
422 + __func__, ret, status, mcu_en);
424 + irq_ret = IRQ_NONE;
428 + for (i = 0; i < MT7986_MEMIF_NUM; i++) {
429 + struct mtk_base_afe_memif *memif = &afe->memif[i];
431 + if (!memif->substream)
434 + if (memif->irq_usage < 0)
437 + irq = &afe->irqs[memif->irq_usage];
439 + if (status_mcu & (1 << irq->irq_data->irq_en_shift))
440 + snd_pcm_period_elapsed(memif->substream);
445 + regmap_write(afe->regmap, AFE_IRQ_MCU_CLR, status_mcu);
450 +static int mt7986_afe_runtime_suspend(struct device *dev)
452 + struct mtk_base_afe *afe = dev_get_drvdata(dev);
453 + struct mt7986_afe_private *afe_priv = afe->platform_priv;
455 + if (!afe->regmap || afe_priv->pm_runtime_bypass_reg_ctl)
459 + regmap_update_bits(afe->regmap, AUDIO_TOP_CON4, 0x3fff, 0x3fff);
460 + regmap_update_bits(afe->regmap, AUDIO_ENGEN_CON0, AUD_APLL2_EN_MASK, 0);
461 + regmap_update_bits(afe->regmap, AUDIO_ENGEN_CON0, AUD_26M_EN_MASK, 0);
463 + /* make sure all irq status are cleared, twice intended */
464 + regmap_update_bits(afe->regmap, AFE_IRQ_MCU_CLR, 0xffff, 0xffff);
467 + clk_bulk_disable_unprepare(afe_priv->num_clks, afe_priv->clks);
472 +static int mt7986_afe_runtime_resume(struct device *dev)
474 + struct mtk_base_afe *afe = dev_get_drvdata(dev);
475 + struct mt7986_afe_private *afe_priv = afe->platform_priv;
478 + ret = clk_bulk_prepare_enable(afe_priv->num_clks, afe_priv->clks);
480 + return dev_err_probe(afe->dev, ret, "Failed to enable clocks\n");
482 + if (!afe->regmap || afe_priv->pm_runtime_bypass_reg_ctl)
486 + regmap_update_bits(afe->regmap, AUDIO_TOP_CON4, 0x3fff, 0);
487 + regmap_update_bits(afe->regmap, AUDIO_ENGEN_CON0, AUD_APLL2_EN_MASK,
489 + regmap_update_bits(afe->regmap, AUDIO_ENGEN_CON0, AUD_26M_EN_MASK,
495 +static int mt7986_afe_component_probe(struct snd_soc_component *component)
497 + return mtk_afe_add_sub_dai_control(component);
500 +static const struct snd_soc_component_driver mt7986_afe_component = {
501 + .name = AFE_PCM_NAME,
502 + .probe = mt7986_afe_component_probe,
503 + .pointer = mtk_afe_pcm_pointer,
504 + .pcm_construct = mtk_afe_pcm_new,
507 +static int mt7986_dai_memif_register(struct mtk_base_afe *afe)
509 + struct mtk_base_afe_dai *dai;
511 + dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
515 + list_add(&dai->list, &afe->sub_dais);
517 + dai->dai_drivers = mt7986_memif_dai_driver;
518 + dai->num_dai_drivers = ARRAY_SIZE(mt7986_memif_dai_driver);
520 + dai->dapm_widgets = mt7986_memif_widgets;
521 + dai->num_dapm_widgets = ARRAY_SIZE(mt7986_memif_widgets);
522 + dai->dapm_routes = mt7986_memif_routes;
523 + dai->num_dapm_routes = ARRAY_SIZE(mt7986_memif_routes);
528 +typedef int (*dai_register_cb)(struct mtk_base_afe *);
529 +static const dai_register_cb dai_register_cbs[] = {
530 + mt7986_dai_etdm_register,
531 + mt7986_dai_memif_register,
534 +static int mt7986_afe_pcm_dev_probe(struct platform_device *pdev)
536 + struct mtk_base_afe *afe;
537 + struct mt7986_afe_private *afe_priv;
538 + struct device *dev;
539 + int i, irq_id, ret;
541 + afe = devm_kzalloc(&pdev->dev, sizeof(*afe), GFP_KERNEL);
544 + platform_set_drvdata(pdev, afe);
546 + afe->platform_priv = devm_kzalloc(&pdev->dev, sizeof(*afe_priv),
548 + if (!afe->platform_priv)
551 + afe_priv = afe->platform_priv;
552 + afe->dev = &pdev->dev;
555 + afe->base_addr = devm_platform_ioremap_resource(pdev, 0);
556 + if (IS_ERR(afe->base_addr))
557 + return PTR_ERR(afe->base_addr);
559 + /* initial audio related clock */
560 + ret = mt7986_init_clock(afe);
562 + return dev_err_probe(dev, ret, "Cannot initialize clocks\n");
564 + ret = devm_pm_runtime_enable(dev);
568 + /* enable clock for regcache get default value from hw */
569 + afe_priv->pm_runtime_bypass_reg_ctl = true;
570 + pm_runtime_get_sync(&pdev->dev);
572 + afe->regmap = devm_regmap_init_mmio(&pdev->dev, afe->base_addr,
573 + &mt7986_afe_regmap_config);
575 + pm_runtime_put_sync(&pdev->dev);
576 + if (IS_ERR(afe->regmap))
577 + return PTR_ERR(afe->regmap);
579 + afe_priv->pm_runtime_bypass_reg_ctl = false;
582 + afe->memif_size = MT7986_MEMIF_NUM;
583 + afe->memif = devm_kcalloc(dev, afe->memif_size, sizeof(*afe->memif),
588 + for (i = 0; i < afe->memif_size; i++) {
589 + afe->memif[i].data = &memif_data[i];
590 + afe->memif[i].irq_usage = -1;
593 + mutex_init(&afe->irq_alloc_lock);
595 + /* irq initialize */
596 + afe->irqs_size = MT7986_IRQ_NUM;
597 + afe->irqs = devm_kcalloc(dev, afe->irqs_size, sizeof(*afe->irqs),
602 + for (i = 0; i < afe->irqs_size; i++)
603 + afe->irqs[i].irq_data = &irq_data[i];
606 + irq_id = platform_get_irq(pdev, 0);
609 + return dev_err_probe(dev, ret, "No irq found\n");
611 + ret = devm_request_irq(dev, irq_id, mt7986_afe_irq_handler,
612 + IRQF_TRIGGER_NONE, "asys-isr", (void *)afe);
614 + return dev_err_probe(dev, ret, "Failed to request irq for asys-isr\n");
616 + /* init sub_dais */
617 + INIT_LIST_HEAD(&afe->sub_dais);
619 + for (i = 0; i < ARRAY_SIZE(dai_register_cbs); i++) {
620 + ret = dai_register_cbs[i](afe);
622 + return dev_err_probe(dev, ret, "DAI register failed, i: %d\n", i);
625 + /* init dai_driver and component_driver */
626 + ret = mtk_afe_combine_sub_dai(afe);
628 + return dev_err_probe(dev, ret, "mtk_afe_combine_sub_dai fail\n");
630 + afe->mtk_afe_hardware = &mt7986_afe_hardware;
631 + afe->memif_fs = mt7986_memif_fs;
632 + afe->irq_fs = mt7986_irq_fs;
634 + afe->runtime_resume = mt7986_afe_runtime_resume;
635 + afe->runtime_suspend = mt7986_afe_runtime_suspend;
637 + /* register component */
638 + ret = devm_snd_soc_register_component(&pdev->dev,
639 + &mt7986_afe_component,
642 + return dev_err_probe(dev, ret, "Cannot register AFE component\n");
644 + ret = devm_snd_soc_register_component(afe->dev,
645 + &mt7986_afe_pcm_dai_component,
647 + afe->num_dai_drivers);
649 + return dev_err_probe(dev, ret, "Cannot register PCM DAI component\n");
654 +static void mt7986_afe_pcm_dev_remove(struct platform_device *pdev)
656 + pm_runtime_disable(&pdev->dev);
657 + if (!pm_runtime_status_suspended(&pdev->dev))
658 + mt7986_afe_runtime_suspend(&pdev->dev);
661 +static const struct of_device_id mt7986_afe_pcm_dt_match[] = {
662 + { .compatible = "mediatek,mt7986-afe" },
665 +MODULE_DEVICE_TABLE(of, mt7986_afe_pcm_dt_match);
667 +static const struct dev_pm_ops mt7986_afe_pm_ops = {
668 + SET_RUNTIME_PM_OPS(mt7986_afe_runtime_suspend,
669 + mt7986_afe_runtime_resume, NULL)
672 +static struct platform_driver mt7986_afe_pcm_driver = {
674 + .name = "mt7986-audio",
675 + .of_match_table = mt7986_afe_pcm_dt_match,
676 + .pm = &mt7986_afe_pm_ops,
678 + .probe = mt7986_afe_pcm_dev_probe,
679 + .remove_new = mt7986_afe_pcm_dev_remove,
681 +module_platform_driver(mt7986_afe_pcm_driver);
683 +MODULE_DESCRIPTION("MediaTek SoC AFE platform driver for ALSA MT7986");
684 +MODULE_AUTHOR("Vic Wu <vic.wu@mediatek.com>");
685 +MODULE_LICENSE("GPL");