1 diff -urN a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
2 --- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts 2019-12-02 14:33:30.126586402 +0800
3 +++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts 2019-12-02 14:35:02.304005081 +0800
9 + compatible = "mediatek,mt753x";
10 + mediatek,ethsys = <ðsys>;
11 + #address-cells = <1>;
16 compatible = "gpio-leds";
23 + mediatek,mdio = <&mdio>;
24 + mediatek,portmap = "wllll";
25 + mediatek,mdio_master_pinmux = <0>;
26 + reset-gpios = <&pio 54 0>;
27 + interrupt-parent = <&pio>;
28 + interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
32 + compatible = "mediatek,mt753x-port";
42 + compatible = "mediatek,mt753x-port";
53 pinctrl-names = "default";
54 pinctrl-0 = <&i2c1_pins>;
55 --- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts 2020-01-12 19:21:53.000000000 +0800
56 +++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts 2020-01-15 15:36:50.987901563 +0800
59 - * Copyright (c) 2017 MediaTek Inc.
60 - * Author: Ming Huang <ming.huang@mediatek.com>
61 - * Sean Wang <sean.wang@mediatek.com>
62 + * Copyright (c) 2018 MediaTek Inc.
63 + * Author: Ryder Lee <ryder.lee@mediatek.com>
65 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
68 #include "mt6380.dtsi"
71 - model = "MediaTek MT7622 RFB1 board";
72 - compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
73 + model = "MT7622_MT7531 RFB";
74 + compatible = "bananapi,bpi-r64", "mediatek,mt7622";
81 stdout-path = "serial0:115200n8";
82 - bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512";
83 + bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512";
90 compatible = "gpio-keys";
91 - poll-interval = <100>;
97 + gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
102 linux,code = <KEY_WPS_BUTTON>;
103 - gpios = <&pio 102 0>;
104 + gpios = <&pio 102 GPIO_ACTIVE_HIGH>;
109 + compatible = "mediatek,mt753x";
110 + mediatek,ethsys = <ðsys>;
111 + #address-cells = <1>;
116 + compatible = "gpio-leds";
119 + label = "bpi-r64:pio:green";
120 + gpios = <&pio 89 GPIO_ACTIVE_HIGH>;
121 + default-state = "off";
125 + label = "bpi-r64:pio:red";
126 + gpios = <&pio 88 GPIO_ACTIVE_HIGH>;
127 + default-state = "off";
132 - reg = <0 0x40000000 0 0x20000000>;
133 + reg = <0 0x40000000 0 0x40000000>;
136 reg_1p8v: regulator-1p8v {
137 @@ -101,27 +122,67 @@
141 - pinctrl-names = "default";
142 - pinctrl-0 = <ð_pins>;
145 + compatible = "mediatek,eth-mac";
147 + phy-mode = "2500base-x";
157 compatible = "mediatek,eth-mac";
159 - phy-handle = <&phy5>;
160 + phy-mode = "rgmii";
171 #address-cells = <1>;
174 - phy5: ethernet-phy@5 {
176 - phy-mode = "sgmii";
182 + mediatek,mdio = <&mdio>;
183 + mediatek,portmap = "llllw";
184 + mediatek,mdio_master_pinmux = <0>;
185 + reset-gpios = <&pio 54 0>;
186 + interrupt-parent = <&pio>;
187 + interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
191 + compatible = "mediatek,mt753x-port";
193 + phy-mode = "rgmii";
201 + compatible = "mediatek,mt753x-port";
203 + phy-mode = "sgmii";
212 pinctrl-names = "default";
213 pinctrl-0 = <&i2c1_pins>;
214 @@ -185,15 +246,28 @@
217 pinctrl-names = "default";
218 - pinctrl-0 = <&pcie0_pins>;
219 + pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>;
232 + /* Attention: GPIO 90 is used to switch between PCIe@1,0 and
233 + * SATA functions. i.e. output-high: PCIe, output-low: SATA
237 + gpios = <90 GPIO_ACTIVE_HIGH>;
241 /* eMMC is shared pin with parallel NAND */
242 emmc_pins_default: emmc-pins-default {
244 @@ -460,11 +534,11 @@
249 + status = "disable";
254 + status = "disable";