1 --- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
2 +++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
8 + compatible = "mediatek,mt753x";
9 + mediatek,ethsys = <ðsys>;
10 + #address-cells = <1>;
15 compatible = "gpio-leds";
22 + mediatek,mdio = <&mdio>;
23 + mediatek,portmap = "wllll";
24 + mediatek,mdio_master_pinmux = <0>;
25 + reset-gpios = <&pio 54 0>;
26 + interrupt-parent = <&pio>;
27 + interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
31 + compatible = "mediatek,mt753x-port";
41 + compatible = "mediatek,mt753x-port";
52 pinctrl-names = "default";
53 pinctrl-0 = <&i2c1_pins>;
54 --- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
55 +++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
58 - * Copyright (c) 2017 MediaTek Inc.
59 - * Author: Ming Huang <ming.huang@mediatek.com>
60 - * Sean Wang <sean.wang@mediatek.com>
61 + * Copyright (c) 2018 MediaTek Inc.
62 + * Author: Ryder Lee <ryder.lee@mediatek.com>
64 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
67 #include "mt6380.dtsi"
70 - model = "MediaTek MT7622 RFB1 board";
71 - compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
72 + model = "MT7622_MT7531 RFB";
73 + compatible = "bananapi,bpi-r64", "mediatek,mt7622";
80 stdout-path = "serial0:115200n8";
81 - bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512";
82 + bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512";
89 compatible = "gpio-keys";
90 - poll-interval = <100>;
96 + gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
101 linux,code = <KEY_WPS_BUTTON>;
102 - gpios = <&pio 102 0>;
103 + gpios = <&pio 102 GPIO_ACTIVE_HIGH>;
108 + compatible = "mediatek,mt753x";
109 + mediatek,ethsys = <ðsys>;
110 + #address-cells = <1>;
115 + compatible = "gpio-leds";
118 + label = "bpi-r64:pio:green";
119 + gpios = <&pio 89 GPIO_ACTIVE_HIGH>;
120 + default-state = "off";
124 + label = "bpi-r64:pio:red";
125 + gpios = <&pio 88 GPIO_ACTIVE_HIGH>;
126 + default-state = "off";
131 - reg = <0 0x40000000 0 0x20000000>;
132 + reg = <0 0x40000000 0 0x40000000>;
135 reg_1p8v: regulator-1p8v {
136 @@ -101,27 +122,67 @@
140 - pinctrl-names = "default";
141 - pinctrl-0 = <ð_pins>;
144 + compatible = "mediatek,eth-mac";
146 + phy-mode = "2500base-x";
156 compatible = "mediatek,eth-mac";
158 - phy-handle = <&phy5>;
159 + phy-mode = "rgmii";
170 #address-cells = <1>;
173 - phy5: ethernet-phy@5 {
175 - phy-mode = "sgmii";
181 + mediatek,mdio = <&mdio>;
182 + mediatek,portmap = "llllw";
183 + mediatek,mdio_master_pinmux = <0>;
184 + reset-gpios = <&pio 54 0>;
185 + interrupt-parent = <&pio>;
186 + interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
190 + compatible = "mediatek,mt753x-port";
192 + phy-mode = "rgmii";
200 + compatible = "mediatek,mt753x-port";
202 + phy-mode = "sgmii";
211 pinctrl-names = "default";
212 pinctrl-0 = <&i2c1_pins>;
213 @@ -185,15 +246,28 @@
216 pinctrl-names = "default";
217 - pinctrl-0 = <&pcie0_pins>;
218 + pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>;
231 + /* Attention: GPIO 90 is used to switch between PCIe@1,0 and
232 + * SATA functions. i.e. output-high: PCIe, output-low: SATA
236 + gpios = <90 GPIO_ACTIVE_HIGH>;
240 /* eMMC is shared pin with parallel NAND */
241 emmc_pins_default: emmc-pins-default {
243 @@ -460,11 +534,11 @@
248 + status = "disable";
253 + status = "disable";