1 From 004eb24e939b5b31f828333f37fb5cb2a877d6f2 Mon Sep 17 00:00:00 2001
2 From: Kristian Evensen <kristian.evensen@gmail.com>
3 Date: Sun, 17 Jun 2018 14:41:47 +0200
4 Subject: [PATCH] arm: dts: Add Unielec U7623 DTS
7 arch/arm/boot/dts/Makefile | 1 +
8 .../dts/mt7623a-unielec-u7623-02-emmc-512m.dts | 18 +
9 .../boot/dts/mt7623a-unielec-u7623-02-emmc.dtsi | 366 +++++++++++++++++++++
10 3 files changed, 385 insertions(+)
11 create mode 100644 arch/arm/boot/dts/mt7623a-unielec-u7623-02-emmc-512m.dts
12 create mode 100644 arch/arm/boot/dts/mt7623a-unielec-u7623-02-emmc.dtsi
14 --- a/arch/arm/boot/dts/Makefile
15 +++ b/arch/arm/boot/dts/Makefile
16 @@ -1193,6 +1193,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
17 mt7623a-rfb-nand.dtb \
18 mt7623n-rfb-emmc.dtb \
19 mt7623n-bananapi-bpi-r2.dtb \
20 + mt7623a-unielec-u7623-02-emmc-512m.dtb \
24 dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb
26 +++ b/arch/arm/boot/dts/mt7623a-unielec-u7623-02-emmc-512m.dts
29 + * Copyright 2018 Kristian Evensen <kristian.evensen@gmail.com>
31 + * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
35 +#include "mt7623a-unielec-u7623-02-emmc.dtsi"
38 + model = "UniElec U7623-02 eMMC (512M RAM)";
39 + compatible = "unielec,u7623-02-emmc-512m", "unielec,u7623-02-emmc", "mediatek,mt7623";
42 + device_type = "memory";
43 + reg = <0 0x80000000 0 0x20000000>;
47 +++ b/arch/arm/boot/dts/mt7623a-unielec-u7623-02-emmc.dtsi
50 + * Copyright 2018 Kristian Evensen <kristian.evensen@gmail.com>
52 + * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
55 +#include <dt-bindings/input/input.h>
56 +#include "mt7623.dtsi"
57 +#include "mt6323.dtsi"
60 + compatible = "unielec,u7623-02-emmc", "mediatek,mt7623";
67 + bootargs = "root=/dev/mmcblk0p2 rootfstype=squashfs,f2fs";
68 + stdout-path = "serial2:115200n8";
73 + proc-supply = <&mt6323_vproc_reg>;
77 + proc-supply = <&mt6323_vproc_reg>;
81 + proc-supply = <&mt6323_vproc_reg>;
85 + proc-supply = <&mt6323_vproc_reg>;
89 + reg_1p8v: regulator-1p8v {
90 + compatible = "regulator-fixed";
91 + regulator-name = "fixed-1.8V";
92 + regulator-min-microvolt = <1800000>;
93 + regulator-max-microvolt = <1800000>;
95 + regulator-always-on;
98 + reg_3p3v: regulator-3p3v {
99 + compatible = "regulator-fixed";
100 + regulator-name = "fixed-3.3V";
101 + regulator-min-microvolt = <3300000>;
102 + regulator-max-microvolt = <3300000>;
104 + regulator-always-on;
107 + reg_5v: regulator-5v {
108 + compatible = "regulator-fixed";
109 + regulator-name = "fixed-5V";
110 + regulator-min-microvolt = <5000000>;
111 + regulator-max-microvolt = <5000000>;
113 + regulator-always-on;
117 + compatible = "gpio-keys";
118 + pinctrl-names = "default";
119 + pinctrl-0 = <&key_pins_a>;
123 + linux,code = <KEY_RESTART>;
124 + gpios = <&pio 256 GPIO_ACTIVE_LOW>;
129 + compatible = "gpio-leds";
130 + pinctrl-names = "default";
131 + pinctrl-0 = <&led_pins_unielec>;
134 + label = "u7623-01:green:led3";
135 + gpios = <&pio 14 GPIO_ACTIVE_LOW>;
136 + default-state = "off";
140 + label = "u7623-01:green:led4";
141 + gpios = <&pio 15 GPIO_ACTIVE_LOW>;
142 + default-state = "off";
147 + compatible = "mediatek,mt7530";
148 + #address-cells = <1>;
161 + compatible = "mediatek,eth-mac";
163 + phy-mode = "trgmii";
173 + #address-cells = <1>;
175 + phy5: ethernet-phy@5 {
177 + phy-mode = "rgmii-rxid";
183 + compatible = "mediatek,mt7530";
184 + #address-cells = <1>;
187 + pinctrl-names = "default";
189 + resets = <ðsys 2>;
190 + reset-names = "mcm";
191 + core-supply = <&mt6323_vpa_reg>;
192 + io-supply = <&mt6323_vemc3v3_reg>;
194 + dsa,mii-bus = <&mdio>;
197 + #address-cells = <1>;
204 + cpu = <&cpu_port0>;
210 + cpu = <&cpu_port0>;
216 + cpu = <&cpu_port0>;
222 + cpu = <&cpu_port0>;
228 + cpu = <&cpu_port0>;
231 + cpu_port0: port@6 {
234 + ethernet = <&gmac0>;
235 + phy-mode = "trgmii";
246 + pinctrl-names = "default", "state_uhs";
247 + pinctrl-0 = <&mmc0_pins_default>;
248 + pinctrl-1 = <&mmc0_pins_uhs>;
251 + max-frequency = <50000000>;
253 + vmmc-supply = <®_3p3v>;
254 + vqmmc-supply = <®_1p8v>;
259 + key_pins_a: keys-alt {
261 + pinmux = <MT7623_PIN_256_GPIO256_FUNC_GPIO256>,
262 + <MT7623_PIN_257_GPIO257_FUNC_GPIO257>;
267 + led_pins_unielec: leds-unielec {
269 + pinmux = <MT7623_PIN_14_GPIO14_FUNC_GPIO14>,
270 + <MT7623_PIN_15_GPIO15_FUNC_GPIO15>;
274 + mmc0_pins_default: mmc0default {
276 + pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
277 + <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
278 + <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
279 + <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
280 + <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
281 + <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
282 + <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
283 + <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
284 + <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
290 + pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
295 + pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
300 + mmc0_pins_uhs: mmc0 {
302 + pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
303 + <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
304 + <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
305 + <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
306 + <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
307 + <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
308 + <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
309 + <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
310 + <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
312 + drive-strength = <MTK_DRIVE_2mA>;
313 + bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
317 + pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
318 + drive-strength = <MTK_DRIVE_2mA>;
319 + bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
323 + pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
328 + pcie_default: pcie_pin_default {
330 + pinmux = <MT7623_PIN_208_AUD_EXT_CK1_FUNC_PCIE0_PERST_N>,
331 + <MT7623_PIN_209_AUD_EXT_CK2_FUNC_PCIE1_PERST_N>;
338 + pinctrl-names = "default";
339 + pinctrl-0 = <&pwm_pins_a>;
346 + compatible = "mediatek,mt6323-led";
347 + #address-cells = <1>;
353 + default-state = "off";
360 + pinctrl-names = "default";
361 + pinctrl-0 = <&uart2_pins_b>;
366 + vusb33-supply = <®_3p3v>;
367 + vbus-supply = <®_3p3v>;
377 + mediatek,phy-switch = <&hifsys>;
381 + pinctrl-names = "default";
382 + pinctrl-0 = <&pcie_default>;