1 From a751f7412e0098801673b80bc7a4738ae7d710ce Mon Sep 17 00:00:00 2001
2 From: Frank Wunderlich <frank-w@public-files.de>
3 Date: Fri, 6 Jan 2023 16:28:45 +0100
4 Subject: [PATCH 10/19] arm64: dts: mt7986: add Bananapi R3
6 Add support for Bananapi R3 SBC.
8 - SD/eMMC support (switching first 4 bits of data-bus with sw6/D)
9 - SPI-NAND/NOR support (switched CS by sw5/C)
10 - all rj45 ports and both SFP working (eth1/lan4)
11 - all USB-Ports + SIM-Slot tested
12 - i2c and all uarts tested
13 - wifi tested (with eeprom calibration data)
15 The device can boot from all 4 storage options. Both, SPI and MMC, can
16 be switched using hardware switches on the board, see
17 https://wiki.banana-pi.org/Banana_Pi_BPI-R3#Jumper_setting
19 Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
20 Link: https://lore.kernel.org/r/20230106152845.88717-6-linux@fw-web.de
21 Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
23 arch/arm64/boot/dts/mediatek/Makefile | 5 +
24 .../mt7986a-bananapi-bpi-r3-emmc.dtso | 29 ++
25 .../mt7986a-bananapi-bpi-r3-nand.dtso | 55 +++
26 .../mediatek/mt7986a-bananapi-bpi-r3-nor.dtso | 68 +++
27 .../mediatek/mt7986a-bananapi-bpi-r3-sd.dtso | 23 +
28 .../dts/mediatek/mt7986a-bananapi-bpi-r3.dts | 450 ++++++++++++++++++
29 6 files changed, 630 insertions(+)
30 create mode 100644 arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso
31 create mode 100644 arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso
32 create mode 100644 arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso
33 create mode 100644 arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso
34 create mode 100644 arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
36 --- a/arch/arm64/boot/dts/mediatek/Makefile
37 +++ b/arch/arm64/boot/dts/mediatek/Makefile
38 @@ -7,6 +7,11 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-ev
39 dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb
40 dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb
41 dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-bananapi-bpi-r64.dtb
42 +dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3.dtb
43 +dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-emmc.dtbo
44 +dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-nand.dtbo
45 +dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-nor.dtbo
46 +dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-sd.dtbo
47 dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-rfb.dtb
48 dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986b-rfb.dtb
49 dtb-$(CONFIG_ARCH_MEDIATEK) += mt8167-pumpkin.dtb
51 +++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso
53 +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
55 + * Copyright (C) 2021 MediaTek Inc.
56 + * Author: Sam.Shih <sam.shih@mediatek.com>
63 + compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
66 + target-path = "/soc/mmc@11230000";
69 + max-frequency = <200000000>;
73 + hs400-ds-delay = <0x14014>;
83 +++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso
85 +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
87 + * Authors: Daniel Golle <daniel@makrotopia.org>
88 + * Frank Wunderlich <frank-w@public-files.de>
95 + compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
98 + target-path = "/soc/spi@1100a000";
100 + #address-cells = <1>;
102 + spi_nand: spi_nand@0 {
103 + compatible = "spi-nand";
105 + spi-max-frequency = <10000000>;
106 + spi-tx-bus-width = <4>;
107 + spi-rx-bus-width = <4>;
110 + compatible = "fixed-partitions";
111 + #address-cells = <1>;
116 + reg = <0x0 0x80000>;
121 + label = "reserved";
122 + reg = <0x80000 0x300000>;
127 + reg = <0x380000 0x200000>;
133 + reg = <0x580000 0x7a80000>;
141 +++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso
143 +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
145 + * Authors: Daniel Golle <daniel@makrotopia.org>
146 + * Frank Wunderlich <frank-w@public-files.de>
153 + compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
156 + target-path = "/soc/spi@1100a000";
158 + #address-cells = <1>;
161 + compatible = "jedec,spi-nor";
163 + spi-max-frequency = <10000000>;
166 + compatible = "fixed-partitions";
167 + #address-cells = <1>;
172 + reg = <0x0 0x20000>;
177 + label = "reserved";
178 + reg = <0x20000 0x20000>;
182 + label = "u-boot-env";
183 + reg = <0x40000 0x40000>;
187 + label = "reserved2";
188 + reg = <0x80000 0x80000>;
193 + reg = <0x100000 0x80000>;
198 + label = "recovery";
199 + reg = <0x180000 0xa80000>;
204 + reg = <0xc00000 0x1400000>;
212 +++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso
214 +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
216 + * Copyright (C) 2021 MediaTek Inc.
217 + * Author: Sam.Shih <sam.shih@mediatek.com>
224 + compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
227 + target-path = "/soc/mmc@11230000";
230 + max-frequency = <52000000>;
238 +++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
240 +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
242 + * Copyright (C) 2021 MediaTek Inc.
243 + * Authors: Sam.Shih <sam.shih@mediatek.com>
244 + * Frank Wunderlich <frank-w@public-files.de>
245 + * Daniel Golle <daniel@makrotopia.org>
249 +#include <dt-bindings/gpio/gpio.h>
250 +#include <dt-bindings/input/input.h>
251 +#include <dt-bindings/leds/common.h>
252 +#include <dt-bindings/pinctrl/mt65xx.h>
254 +#include "mt7986a.dtsi"
257 + model = "Bananapi BPI-R3";
258 + compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
262 + ethernet0 = &gmac0;
263 + ethernet1 = &gmac1;
267 + stdout-path = "serial0:115200n8";
270 + dcin: regulator-12vd {
271 + compatible = "regulator-fixed";
272 + regulator-name = "12vd";
273 + regulator-min-microvolt = <12000000>;
274 + regulator-max-microvolt = <12000000>;
276 + regulator-always-on;
280 + compatible = "gpio-keys";
284 + linux,code = <KEY_RESTART>;
285 + gpios = <&pio 9 GPIO_ACTIVE_LOW>;
290 + linux,code = <KEY_WPS_BUTTON>;
291 + gpios = <&pio 10 GPIO_ACTIVE_LOW>;
295 + /* i2c of the left SFP cage (wan) */
296 + i2c_sfp1: i2c-gpio-0 {
297 + compatible = "i2c-gpio";
298 + sda-gpios = <&pio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
299 + scl-gpios = <&pio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
300 + i2c-gpio,delay-us = <2>;
301 + #address-cells = <1>;
305 + /* i2c of the right SFP cage (lan) */
306 + i2c_sfp2: i2c-gpio-1 {
307 + compatible = "i2c-gpio";
308 + sda-gpios = <&pio 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
309 + scl-gpios = <&pio 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
310 + i2c-gpio,delay-us = <2>;
311 + #address-cells = <1>;
316 + compatible = "gpio-leds";
319 + color = <LED_COLOR_ID_GREEN>;
320 + function = LED_FUNCTION_POWER;
321 + gpios = <&pio 69 GPIO_ACTIVE_HIGH>;
322 + default-state = "on";
326 + color = <LED_COLOR_ID_BLUE>;
327 + function = LED_FUNCTION_STATUS;
328 + gpios = <&pio 86 GPIO_ACTIVE_HIGH>;
329 + default-state = "off";
333 + reg_1p8v: regulator-1p8v {
334 + compatible = "regulator-fixed";
335 + regulator-name = "1.8vd";
336 + regulator-min-microvolt = <1800000>;
337 + regulator-max-microvolt = <1800000>;
339 + regulator-always-on;
340 + vin-supply = <&dcin>;
343 + reg_3p3v: regulator-3p3v {
344 + compatible = "regulator-fixed";
345 + regulator-name = "3.3vd";
346 + regulator-min-microvolt = <3300000>;
347 + regulator-max-microvolt = <3300000>;
349 + regulator-always-on;
350 + vin-supply = <&dcin>;
353 + /* left SFP cage (wan) */
355 + compatible = "sff,sfp";
356 + i2c-bus = <&i2c_sfp1>;
357 + los-gpios = <&pio 46 GPIO_ACTIVE_HIGH>;
358 + mod-def0-gpios = <&pio 49 GPIO_ACTIVE_LOW>;
359 + tx-disable-gpios = <&pio 20 GPIO_ACTIVE_HIGH>;
360 + tx-fault-gpios = <&pio 7 GPIO_ACTIVE_HIGH>;
363 + /* right SFP cage (lan) */
365 + compatible = "sff,sfp";
366 + i2c-bus = <&i2c_sfp2>;
367 + los-gpios = <&pio 31 GPIO_ACTIVE_HIGH>;
368 + mod-def0-gpios = <&pio 47 GPIO_ACTIVE_LOW>;
369 + tx-disable-gpios = <&pio 15 GPIO_ACTIVE_HIGH>;
370 + tx-fault-gpios = <&pio 48 GPIO_ACTIVE_HIGH>;
382 + compatible = "mediatek,eth-mac";
384 + phy-mode = "2500base-x";
394 + compatible = "mediatek,eth-mac";
396 + phy-mode = "2500base-x";
398 + managed = "in-band-status";
402 + #address-cells = <1>;
408 + switch: switch@1f {
409 + compatible = "mediatek,mt7531";
411 + interrupt-controller;
412 + #interrupt-cells = <1>;
413 + interrupt-parent = <&pio>;
414 + interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
415 + reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
420 + pinctrl-names = "default", "state_uhs";
421 + pinctrl-0 = <&mmc0_pins_default>;
422 + pinctrl-1 = <&mmc0_pins_uhs>;
423 + vmmc-supply = <®_3p3v>;
424 + vqmmc-supply = <®_1p8v>;
428 + pinctrl-names = "default";
429 + pinctrl-0 = <&i2c_pins>;
434 + pinctrl-names = "default";
435 + pinctrl-0 = <&pcie_pins>;
444 + i2c_pins: i2c-pins {
451 + mmc0_pins_default: mmc0-pins {
454 + groups = "emmc_51";
457 + pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
458 + "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
459 + "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
461 + drive-strength = <4>;
462 + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
466 + drive-strength = <6>;
467 + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
471 + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
474 + pins = "EMMC_RSTB";
475 + drive-strength = <4>;
476 + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
480 + mmc0_pins_uhs: mmc0-uhs-pins {
483 + groups = "emmc_51";
486 + pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
487 + "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
488 + "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
490 + drive-strength = <4>;
491 + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
495 + drive-strength = <6>;
496 + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
500 + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
503 + pins = "EMMC_RSTB";
504 + drive-strength = <4>;
505 + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
509 + pcie_pins: pcie-pins {
512 + groups = "pcie_clk", "pcie_pereset";
516 + spi_flash_pins: spi-flash-pins {
519 + groups = "spi0", "spi0_wp_hold";
523 + spic_pins: spic-pins {
530 + uart1_pins: uart1-pins {
533 + groups = "uart1_rx_tx";
537 + uart2_pins: uart2-pins {
540 + groups = "uart2_0_rx_tx";
544 + wf_2g_5g_pins: wf-2g-5g-pins {
547 + groups = "wf_2g", "wf_5g";
550 + pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
551 + "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
552 + "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
553 + "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
554 + "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
555 + "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
556 + "WF1_TOP_CLK", "WF1_TOP_DATA";
557 + drive-strength = <4>;
561 + wf_dbdc_pins: wf-dbdc-pins {
564 + groups = "wf_dbdc";
567 + pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
568 + "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
569 + "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
570 + "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
571 + "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
572 + "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
573 + "WF1_TOP_CLK", "WF1_TOP_DATA";
574 + drive-strength = <4>;
578 + wf_led_pins: wf-led-pins {
581 + groups = "wifi_led";
587 + pinctrl-names = "default";
588 + pinctrl-0 = <&spi_flash_pins>;
593 + pinctrl-names = "default";
594 + pinctrl-0 = <&spic_pins>;
604 + #address-cells = <1>;
635 + phy-mode = "2500base-x";
637 + managed = "in-band-status";
643 + ethernet = <&gmac0>;
644 + phy-mode = "2500base-x";
664 + pinctrl-names = "default";
665 + pinctrl-0 = <&uart1_pins>;
670 + pinctrl-names = "default";
671 + pinctrl-0 = <&uart2_pins>;
685 + pinctrl-names = "default", "dbdc";
686 + pinctrl-0 = <&wf_2g_5g_pins>, <&wf_led_pins>;
687 + pinctrl-1 = <&wf_dbdc_pins>, <&wf_led_pins>;