target/linux/mediatek/patches-6.1/241-clk-mediatek-Add-pcw-chg-shift-control.patch

   1 --- a/drivers/clk/mediatek/clk-pll.c
   2 +++ b/drivers/clk/mediatek/clk-pll.c
   3 @@ -141,7 +141,10 @@ static void mtk_pll_set_rate_regs(struct
   4                         pll->data->pcw_shift);
   5         val |= pcw << pll->data->pcw_shift;
   6         writel(val, pll->pcw_addr);
   7 -       chg = readl(pll->pcw_chg_addr) | PCW_CHG_MASK;
   8 +       if (pll->data->pcw_chg_shift)
   9 +               chg = readl(pll->pcw_chg_addr) | BIT(pll->data->pcw_chg_shift);
  10 +       else
  11 +               chg = readl(pll->pcw_chg_addr) | PCW_CHG_MASK;
  12         writel(chg, pll->pcw_chg_addr);
  13         if (pll->tuner_addr)
  14                 writel(val + 1, pll->tuner_addr);
  15 --- a/drivers/clk/mediatek/clk-pll.h
  16 +++ b/drivers/clk/mediatek/clk-pll.h
  17 @@ -42,6 +42,7 @@ struct mtk_pll_data {
  18         u32 pcw_reg;
  19         int pcw_shift;
  20         u32 pcw_chg_reg;
  21 +       int pcw_chg_shift;
  22         const struct mtk_pll_div_table *div_table;
  23         const char *parent_name;
  24         u32 en_reg;