1 From c202f510bbaa34ab5d65a69a61e0e72761374b17 Mon Sep 17 00:00:00 2001
2 From: Daniel Golle <daniel@makrotopia.org>
3 Date: Mon, 11 Mar 2024 17:14:19 +0000
4 Subject: [PATCH] clk: mediatek: mt7988-infracfg: fix clocks for 2nd PCIe port
6 Due to what seems to be an undocumented oddity in MediaTek's MT7988
7 SoC design the CLK_INFRA_PCIE_PERI_26M_CK_P2 clock requires
8 CLK_INFRA_PCIE_PERI_26M_CK_P3 to be enabled.
10 This currently leads to PCIe port 2 not working in Linux.
12 Reflect the apparent relationship in the clk driver to make sure PCIe
13 port 2 of the MT7988 SoC works.
15 Suggested-by: Sam Shih <sam.shih@mediatek.com>
16 Signed-off-by: Daniel Golle <daniel@makrotopia.org>
18 drivers/clk/mediatek/clk-mt7988-infracfg.c | 2 +-
19 1 file changed, 1 insertion(+), 1 deletion(-)
21 --- a/drivers/clk/mediatek/clk-mt7988-infracfg.c
22 +++ b/drivers/clk/mediatek/clk-mt7988-infracfg.c
23 @@ -156,7 +156,7 @@ static const struct mtk_gate infra_clks[
24 GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P1, "infra_pcie_peri_ck_26m_ck_p1",
25 "csw_infra_f26m_sel", 8),
26 GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P2, "infra_pcie_peri_ck_26m_ck_p2",
27 - "csw_infra_f26m_sel", 9),
28 + "infra_pcie_peri_ck_26m_ck_p3", 9),
29 GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P3, "infra_pcie_peri_ck_26m_ck_p3",
30 "csw_infra_f26m_sel", 10),