1 --- a/drivers/ata/Kconfig
2 +++ b/drivers/ata/Kconfig
3 @@ -1019,5 +1019,12 @@ config PATA_LEGACY
8 + tristate "MikroTik RB600 PATA support"
11 + This option enables support for PATA devices on MikroTik RouterBOARD
16 --- a/drivers/ata/Makefile
17 +++ b/drivers/ata/Makefile
18 @@ -99,6 +99,7 @@ obj-$(CONFIG_PATA_PALMLD) += pata_palmld
19 obj-$(CONFIG_PATA_PLATFORM) += pata_platform.o
20 obj-$(CONFIG_PATA_OF_PLATFORM) += pata_of_platform.o
21 obj-$(CONFIG_PATA_RB532) += pata_rb532_cf.o
22 +obj-$(CONFIG_PATA_RB_PPC) += pata_rbppc_cf.o
23 obj-$(CONFIG_PATA_RZ1000) += pata_rz1000.o
24 obj-$(CONFIG_PATA_SAMSUNG_CF) += pata_samsung_cf.o
27 +++ b/drivers/ata/pata_rbppc_cf.c
30 + * Copyright (C) 2008-2009 Noah Fontes <nfontes@transtruct.org>
31 + * Copyright (C) Mikrotik 2007
33 + * This program is free software; you can redistribute it and/or modify it
34 + * under the terms of the GNU General Public License as published by the
35 + * Free Software Foundation; either version 2 of the License, or (at your
36 + * option) any later version.
39 +#include <linux/kernel.h>
40 +#include <linux/module.h>
41 +#include <linux/init.h>
42 +#include <scsi/scsi_host.h>
43 +#include <linux/libata.h>
44 +#include <linux/of_platform.h>
45 +#include <linux/ata_platform.h>
46 +#include <linux/slab.h>
47 +#include <linux/of_address.h>
48 +#include <linux/of_irq.h>
52 +#define DRV_NAME "pata_rbppc_cf"
53 +#define DRV_VERSION "0.0.2"
55 +#define DEV2SEL_OFFSET 0x00100000
57 +#define IMMR_LBCFG_OFFSET 0x00005000
58 +#define IMMR_LBCFG_SIZE 0x00001000
60 +#define LOCAL_BUS_MCMR 0x00000078
61 +#define MxMR_OP_MASK 0x30000000
62 +#define MxMR_OP_NORMAL 0x00000000
63 +#define MxMR_OP_WRITE 0x10000000
64 +#define MxMR_OP_READ 0x20000000
65 +#define MxMR_OP_RUN 0x30000000
66 +#define MxMR_LUPWAIT_LOW 0x08000000
67 +#define MxMR_LUPWAIT_HIGH 0x00000000
68 +#define MxMR_LUPWAIT_ENABLE 0x00040000
69 +#define MxMR_RLF_MASK 0x0003c000
70 +#define MxMR_RLF_SHIFT 14
71 +#define MxMR_WLF_MASK 0x00003c00
72 +#define MxMR_WLF_SHIFT 10
73 +#define MxMR_MAD_MASK 0x0000003f
74 +#define LOCAL_BUS_MDR 0x00000088
75 +#define LOCAL_BUS_LCRR 0x000000D4
76 +#define LCRR_CLKDIV_MASK 0x0000000f
80 +#define UPM_READ_SINGLE_OFFSET 0x00
81 +#define UPM_WRITE_SINGLE_OFFSET 0x18
82 +#define UPM_DATA_SIZE 0x40
84 +#define LBT_CPUIN_MIN 0
85 +#define LBT_CPUOUT_MIN 1
86 +#define LBT_CPUOUT_MAX 2
87 +#define LBT_EXTDEL_MIN 3
88 +#define LBT_EXTDEL_MAX 4
91 +/* UPM machine configuration bits */
92 +#define N_BASE 0x00f00000
93 +#define N_CS 0xf0000000
94 +#define N_CS_H1 0xc0000000
95 +#define N_CS_H2 0x30000000
96 +#define N_WE 0x0f000000
97 +#define N_WE_H1 0x0c000000
98 +#define N_WE_H2 0x03000000
99 +#define N_OE 0x00030000
100 +#define N_OE_H1 0x00020000
101 +#define N_OE_H2 0x00010000
102 +#define WAEN 0x00001000
103 +#define REDO_2 0x00000100
104 +#define REDO_3 0x00000200
105 +#define REDO_4 0x00000300
106 +#define LOOP 0x00000080
107 +#define NA 0x00000008
108 +#define UTA 0x00000004
109 +#define LAST 0x00000001
111 +#define REDO_VAL(mult) (REDO_2 * ((mult) - 1))
112 +#define REDO_MAX_MULT 4
114 +#define READ_BASE (N_BASE | N_WE)
115 +#define WRITE_BASE (N_BASE | N_OE)
116 +#define EMPTY (N_BASE | N_CS | N_OE | N_WE | LAST)
118 +#define EOF_UPM_SETTINGS 0
119 +#define ANOTHER_TIMING 1
121 +#define OA_CPUIN_MIN 0x01
122 +#define OA_CPUOUT_MAX 0x02
123 +#define OD_CPUOUT_MIN 0x04
124 +#define OA_CPUOUT_DELTA 0x06
125 +#define OA_EXTDEL_MAX 0x08
126 +#define OD_EXTDEL_MIN 0x10
127 +#define OA_EXTDEL_DELTA 0x18
128 +#define O_MIN_CYCLE_TIME 0x20
129 +#define O_MINUS_PREV 0x40
130 +#define O_HALF_CYCLE 0x80
132 +extern void __iomem *localbus_map(unsigned long addr, unsigned int len);
133 +extern void localbus_unmap(void __iomem *addr);
135 +struct rbppc_cf_info {
136 + unsigned lbcfg_addr;
137 + unsigned clk_time_ps;
139 + u32 lb_timings[LBT_SIZE];
141 +static struct rbppc_cf_info *rbinfo = NULL;
143 +struct upm_setting {
146 + unsigned clk_minus;
147 + unsigned group_size;
151 +static const struct upm_setting cfUpmReadSingle[] = {
152 + { READ_BASE | N_OE,
153 + /* t1 - ADDR setup time */
154 + { 70, 50, 30, 30, 25, 15, 10 }, 0, 0, (OA_CPUOUT_DELTA |
156 + { READ_BASE | N_OE_H1,
157 + { 0, 0, 0, 0, 0, 0, 0 }, 0, 0, O_HALF_CYCLE },
159 + /* t2 - OE0 time */
160 + { 290, 290, 290, 80, 70, 65, 55 }, 0, 2, (OA_CPUOUT_MAX |
162 + { READ_BASE | WAEN,
163 + { 1, 1, 1, 1, 1, 0, 0 }, 0, 0, 0 },
165 + { 1, 1, 1, 1, 1, 1, 1 }, 0, 0, 0 },
166 + { READ_BASE | N_OE,
167 + /* t9 - ADDR hold time */
168 + { 20, 15, 10, 10, 10, 10, 10 }, 0, 0, (OA_CPUOUT_DELTA |
170 + { READ_BASE | N_OE | N_CS_H2,
171 + { 0, 0, 0, 0, 0, 0, 0 }, 0, 0, O_HALF_CYCLE },
172 + { READ_BASE | N_OE | N_CS,
173 + /* t6Z -IORD data tristate */
174 + { 30, 30, 30, 30, 30, 20, 20 }, 1, 1, O_MINUS_PREV },
176 + /* t2i -IORD recovery time */
177 + { 0, 0, 0, 70, 25, 25, 20 }, 2, 0, 0 },
179 + /* CS 0 -> 1 MAX */
180 + { 0, 0, 0, 0, 0, 0, 0 }, 1, 0, (OA_CPUOUT_DELTA |
182 + { READ_BASE | N_OE | N_CS | LAST,
183 + { 1, 1, 1, 1, 1, 1, 1 }, 0, 0, 0 },
184 + { EOF_UPM_SETTINGS,
185 + /* min total cycle time - includes turnaround and ALE cycle */
186 + { 600, 383, 240, 180, 120, 100, 80 }, 2, 0, O_MIN_CYCLE_TIME },
189 +static const struct upm_setting cfUpmWriteSingle[] = {
190 + { WRITE_BASE | N_WE,
191 + /* t1 - ADDR setup time */
192 + { 70, 50, 30, 30, 25, 15, 10 }, 0, 0, (OA_CPUOUT_DELTA |
194 + { WRITE_BASE | N_WE_H1,
195 + { 0, 0, 0, 0, 0, 0, 0 }, 0, 0, O_HALF_CYCLE },
197 + /* t2 - WE0 time */
198 + { 290, 290, 290, 80, 70, 65, 55 }, 0, 1, OA_CPUOUT_DELTA },
199 + { WRITE_BASE | WAEN,
200 + { 1, 1, 1, 1, 1, 0, 0 }, 0, 0, 0 },
201 + { WRITE_BASE | N_WE,
202 + /* t9 - ADDR hold time */
203 + { 20, 15, 10, 10, 10, 10, 10 }, 0, 0, (OA_CPUOUT_DELTA |
205 + { WRITE_BASE | N_WE | N_CS_H2,
206 + { 0, 0, 0, 0, 0, 0, 0 }, 0, 0, O_HALF_CYCLE },
207 + { WRITE_BASE | N_WE | N_CS,
208 + /* t4 - DATA hold time */
209 + { 30, 20, 15, 10, 10, 10, 10 }, 0, 1, O_MINUS_PREV },
211 + /* t2i -IOWR recovery time */
212 + { 0, 0, 0, 70, 25, 25, 20 }, 1, 0, 0 },
214 + /* CS 0 -> 1 MAX */
215 + { 0, 0, 0, 0, 0, 0, 0 }, 0, 0, (OA_CPUOUT_DELTA |
217 + { WRITE_BASE | N_WE | N_CS | UTA | LAST,
218 + { 1, 1, 1, 1, 1, 1, 1 }, 0, 0, 0 },
219 + /* min total cycle time - includes ALE cycle */
220 + { EOF_UPM_SETTINGS,
221 + { 600, 383, 240, 180, 120, 100, 80 }, 1, 0, O_MIN_CYCLE_TIME },
224 +static u8 rbppc_cf_check_status(struct ata_port *ap) {
225 + u8 val = ioread8(ap->ioaddr.status_addr);
231 +static u8 rbppc_cf_check_altstatus(struct ata_port *ap) {
232 + u8 val = ioread8(ap->ioaddr.altstatus_addr);
238 +static void rbppc_cf_dummy_noret(struct ata_port *ap) { }
239 +static int rbppc_cf_dummy_ret0(struct ata_port *ap) { return 0; }
241 +static int ps2clk(int ps, unsigned clk_time_ps) {
243 + if (ps <= 0) return 0;
245 + /* round down if <= 2% over clk border, but no more than 1/4 clk cycle */
246 + psMaxOver = ps * 2 / 100;
247 + if (4 * psMaxOver > clk_time_ps) {
248 + psMaxOver = clk_time_ps / 4;
250 + return (ps + clk_time_ps - 1 - psMaxOver) / clk_time_ps;
253 +static int upm_gen_ps_table(const struct upm_setting *upm,
254 + int mode, struct rbppc_cf_info *info,
257 + int lastUpmValIdx = 0;
258 + int group_start_idx = -1;
259 + int group_left_num = -1;
260 + int clk_time_ps = info->clk_time_ps;
262 + for (uidx = 0; upm[uidx].value != EOF_UPM_SETTINGS; ++uidx) {
263 + const struct upm_setting *us = upm + uidx;
264 + unsigned opt = us->options;
265 + int ps = us->ns[mode] * 1000 - us->clk_minus * clk_time_ps;
267 + if (opt & OA_CPUIN_MIN) ps += info->lb_timings[LBT_CPUIN_MIN];
268 + if (opt & OD_CPUOUT_MIN) ps -= info->lb_timings[LBT_CPUOUT_MIN];
269 + if (opt & OA_CPUOUT_MAX) ps += info->lb_timings[LBT_CPUOUT_MAX];
270 + if (opt & OD_EXTDEL_MIN) ps -= info->lb_timings[LBT_EXTDEL_MIN];
271 + if (opt & OA_EXTDEL_MAX) ps += info->lb_timings[LBT_EXTDEL_MAX];
273 + if (us->value == ANOTHER_TIMING) {
274 + /* use longest timing from alternatives */
275 + if (psFinal[lastUpmValIdx] < ps) {
276 + psFinal[lastUpmValIdx] = ps;
281 + if (us->group_size) {
282 + group_start_idx = uidx;
283 + group_left_num = us->group_size;
285 + else if (group_left_num > 0) {
286 + /* group time is divided on all group members */
287 + int clk = ps2clk(ps, clk_time_ps);
288 + psFinal[group_start_idx] -= clk * clk_time_ps;
291 + if ((opt & O_MINUS_PREV) && lastUpmValIdx > 0) {
292 + int clk = ps2clk(psFinal[lastUpmValIdx],
294 + ps -= clk * clk_time_ps;
296 + lastUpmValIdx = uidx;
298 + psFinal[uidx] = ps;
303 +static int free_half(int ps, int clk, int clk_time_ps) {
304 + if (clk < 2) return 0;
305 + return (clk * clk_time_ps - ps) * 2 >= clk_time_ps;
308 +static void upm_gen_clk_table(const struct upm_setting *upm,
309 + int mode, int clk_time_ps,
310 + int max_uidx, const int *psFinal, int *clkFinal) {
311 + int clk_cycle_time;
315 + /* convert picoseconds to clocks */
317 + for (uidx = 0; uidx < max_uidx; ++uidx) {
318 + int clk = ps2clk(psFinal[uidx], clk_time_ps);
319 + clkFinal[uidx] = clk;
323 + /* check possibility of half cycle usage */
324 + for (uidx = 1; uidx < max_uidx - 1; ++uidx) {
325 + if ((upm[uidx].options & O_HALF_CYCLE) &&
326 + free_half(psFinal[uidx - 1], clkFinal[uidx - 1],
328 + free_half(psFinal[uidx + 1], clkFinal[uidx + 1],
331 + --clkFinal[uidx - 1];
332 + --clkFinal[uidx + 1];
336 + if ((upm[max_uidx].options & O_MIN_CYCLE_TIME) == 0) return;
338 + /* check cycle time, adjust timings if needed */
339 + clk_cycle_time = (ps2clk(upm[max_uidx].ns[mode] * 1000, clk_time_ps) -
340 + upm[max_uidx].clk_minus);
342 + while (clk_total < clk_cycle_time) {
343 + /* extend all timings in round-robin to match cycle time */
344 + if (clkFinal[uidx]) {
346 + printk(KERN_INFO "extending %u by 1 clk\n", uidx);
352 + if (uidx == max_uidx) uidx = 0;
356 +static void add_data_val(unsigned val, int *clkLeft, int maxClk,
357 + unsigned *data, int *dataIdx) {
358 + if (*clkLeft == 0) return;
360 + if (maxClk == 0 && *clkLeft >= LOOP_SIZE * 2) {
365 + times = *clkLeft / LOOP_SIZE;
366 + if (times > REDO_MAX_MULT * 2) times = REDO_MAX_MULT * 2;
367 + times1 = times / 2;
368 + times2 = times - times1;
371 + data[*dataIdx] = val | REDO_VAL(times1);
373 + data[*dataIdx] = val | REDO_VAL(times2);
376 + *clkLeft -= times * LOOP_SIZE;
380 + if (maxClk < 1 || maxClk > REDO_MAX_MULT) maxClk = REDO_MAX_MULT;
381 + if (*clkLeft < maxClk) maxClk = *clkLeft;
383 + *clkLeft -= maxClk;
384 + val |= REDO_VAL(maxClk);
386 + data[*dataIdx] = val;
390 +static int upm_gen_final_data(const struct upm_setting *upm,
391 + int max_uidx, int *clkFinal, unsigned *data) {
396 + for (uidx = 0; uidx < max_uidx; ++uidx) {
397 + int clk = clkFinal[uidx];
399 + add_data_val(upm[uidx].value, &clk, 0,
406 +static int conv_upm_table(const struct upm_setting *upm,
407 + int mode, struct rbppc_cf_info *info,
417 + max_uidx = upm_gen_ps_table(upm, mode, info, psFinal);
419 + upm_gen_clk_table(upm, mode, info->clk_time_ps, max_uidx,
420 + psFinal, clkFinal);
423 + /* dump out debug info */
424 + for (uidx = 0; uidx < max_uidx; ++uidx) {
425 + if (clkFinal[uidx]) {
426 + printk(KERN_INFO "idx %d val %08x clk %d ps %d\n",
427 + uidx, upm[uidx].value,
428 + clkFinal[uidx], psFinal[uidx]);
433 + data_len = upm_gen_final_data(upm, max_uidx, clkFinal, data);
436 + for (uidx = 0; uidx < data_len; ++uidx) {
437 + printk(KERN_INFO "cf UPM x result: idx %d val %08x\n",
444 +static int gen_upm_data(int mode, struct rbppc_cf_info *info, unsigned *data) {
447 + for (i = 0; i < UPM_DATA_SIZE; ++i) {
451 + if (conv_upm_table(cfUpmReadSingle, mode, info, data + UPM_READ_SINGLE_OFFSET)) {
454 + if (conv_upm_table(cfUpmWriteSingle, mode, info, data + UPM_WRITE_SINGLE_OFFSET)) {
460 +static void rbppc_cf_program_upm(void *upmMemAddr, volatile void *lbcfg_mxmr, volatile void *lbcfg_mdr, const unsigned *upmData, unsigned offset, unsigned len) {
464 + mxmr = in_be32(lbcfg_mxmr);
465 + mxmr &= ~(MxMR_OP_MASK | MxMR_MAD_MASK);
466 + mxmr |= (MxMR_OP_WRITE | offset);
467 + out_be32(lbcfg_mxmr, mxmr);
468 + in_be32(lbcfg_mxmr); /* flush MxMR write */
470 + for (i = 0; i < len; ++i) {
472 + unsigned data = upmData[i + offset];
473 + out_be32(lbcfg_mdr, data);
474 + in_be32(lbcfg_mdr); /* flush MDR write */
476 + iowrite8(1, upmMemAddr); /* dummy write to any CF addr */
478 + /* wait for dummy write to complete */
479 + for (to = 10000; to >= 0; --to) {
480 + mxmr = in_be32(lbcfg_mxmr);
481 + if (((mxmr ^ (i + 1)) & MxMR_MAD_MASK) == 0) {
485 + printk(KERN_ERR "rbppc_cf_program_upm: UPMx program error at 0x%x: Timeout\n", i);
489 + mxmr &= ~(MxMR_OP_MASK | MxMR_RLF_MASK | MxMR_WLF_MASK);
490 + mxmr |= (MxMR_OP_NORMAL | (LOOP_SIZE << MxMR_RLF_SHIFT) | (LOOP_SIZE << MxMR_WLF_SHIFT));
491 + out_be32(lbcfg_mxmr, mxmr);
494 +static int rbppc_cf_update_piomode(struct ata_port *ap, int mode) {
495 + struct rbppc_cf_info *info = (struct rbppc_cf_info *)ap->host->private_data;
497 + unsigned upmData[UPM_DATA_SIZE];
499 + if (gen_upm_data(mode, info, upmData)) {
503 + lbcfgBase = ioremap_nocache(info->lbcfg_addr, IMMR_LBCFG_SIZE);
505 + rbppc_cf_program_upm(ap->ioaddr.cmd_addr, ((char *)lbcfgBase) + LOCAL_BUS_MCMR, ((char *)lbcfgBase) + LOCAL_BUS_MDR, upmData, 0, UPM_DATA_SIZE);
506 + iounmap(lbcfgBase);
510 +static void rbppc_cf_set_piomode(struct ata_port *ap, struct ata_device *adev)
512 + struct rbppc_cf_info *info = (struct rbppc_cf_info *)ap->host->private_data;
513 + int mode = adev->pio_mode - XFER_PIO_0;
515 + DPRINTK("rbppc_cf_set_piomode: PIO %d\n", mode);
516 + if (mode < 0) mode = 0;
517 + if (mode > 6) mode = 6;
519 + if (info->cur_mode < 0 || info->cur_mode > mode) {
520 + if (rbppc_cf_update_piomode(ap, mode) == 0) {
521 + printk(KERN_INFO "rbppc_cf_set_piomode: PIO mode changed to %d\n", mode);
522 + info->cur_mode = mode;
527 +static struct scsi_host_template rbppc_cf_sht = {
528 + ATA_BASE_SHT(DRV_NAME),
531 +static struct ata_port_operations rbppc_cf_port_ops = {
532 + .inherits = &ata_bmdma_port_ops,
534 + .sff_check_status = rbppc_cf_check_status,
535 + .sff_check_altstatus = rbppc_cf_check_altstatus,
537 + .set_piomode = rbppc_cf_set_piomode,
539 + .port_start = rbppc_cf_dummy_ret0,
541 + .sff_irq_clear = rbppc_cf_dummy_noret,
544 +static int rbppc_cf_init_info(struct platform_device *pdev, struct rbppc_cf_info *info) {
545 + struct device_node *np;
546 + struct resource res;
550 + unsigned lbc_clk_khz;
551 + unsigned lbc_extra_divider = 1;
552 + unsigned ccb_freq_hz;
555 + u32ptr = of_get_property(pdev->dev.of_node, "lbc_extra_divider", NULL);
556 + if (u32ptr && *u32ptr) {
557 + lbc_extra_divider = *u32ptr;
559 + printk(KERN_INFO "rbppc_cf_init_info: LBC extra divider %u\n",
560 + lbc_extra_divider);
564 + np = of_find_node_by_type(NULL, "serial");
566 + printk(KERN_ERR "rbppc_cf_init_info: No serial node found\n");
569 + u32ptr = of_get_property(np, "clock-frequency", NULL);
570 + if (u32ptr == 0 || *u32ptr == 0) {
571 + printk(KERN_ERR "rbppc_cf_init_info: Serial does not have clock-frequency\n");
575 + ccb_freq_hz = *u32ptr;
578 + np = of_find_node_by_type(NULL, "soc");
580 + printk(KERN_ERR "rbppc_cf_init_info: No soc node found\n");
583 + if (of_address_to_resource(np, 0, &res)) {
584 + printk(KERN_ERR "rbppc_cf_init_info: soc does not have resource\n");
588 + info->lbcfg_addr = res.start + IMMR_LBCFG_OFFSET;
591 + lbcfgBase = ioremap_nocache(info->lbcfg_addr, IMMR_LBCFG_SIZE);
592 + lbcfg_lcrr = ((char*)lbcfgBase) + LOCAL_BUS_LCRR;
593 + lb_div = (in_be32(lbcfg_lcrr) & LCRR_CLKDIV_MASK) * lbc_extra_divider;
594 + iounmap(lbcfgBase);
596 + lbc_clk_khz = ccb_freq_hz / (1000 * lb_div);
597 + info->clk_time_ps = 1000000000 / lbc_clk_khz;
598 + printk(KERN_INFO "rbppc_cf_init_info: Using Local-Bus clock %u kHz %u ps\n",
599 + lbc_clk_khz, info->clk_time_ps);
601 + u32ptr = of_get_property(pdev->dev.of_node, "lb-timings", NULL);
603 + memcpy(info->lb_timings, u32ptr, LBT_SIZE * sizeof(*u32ptr));
605 + printk(KERN_INFO "rbppc_cf_init_info: Got LB timings <%u %u %u %u %u>\n",
606 + u32ptr[0], u32ptr[1], u32ptr[2], u32ptr[3], u32ptr[4]);
609 + info->cur_mode = -1;
613 +static int rbppc_cf_probe(struct platform_device *pdev)
615 + struct ata_host *host;
616 + struct ata_port *ap;
617 + struct rbppc_cf_info *info = NULL;
618 + struct resource res;
624 + printk(KERN_INFO "rbppc_cf_probe: MikroTik RouterBOARD 600 series Compact Flash PATA driver, version " DRV_VERSION "\n");
626 + if (rbinfo == NULL) {
627 + info = kmalloc(sizeof(*info), GFP_KERNEL);
628 + if (info == NULL) {
629 + printk(KERN_ERR "rbppc_cf_probe: Out of memory\n");
632 + memset(info, 0, sizeof(*info));
634 + if (rbppc_cf_init_info(pdev, info)) {
640 + u32ptr = of_get_property(pdev->dev.of_node, "interrupt-at-level", NULL);
642 + irq_level = *u32ptr;
643 + printk(KERN_INFO "rbppc_cf_probe: IRQ level %u\n", irq_level);
646 + if (of_address_to_resource(pdev->dev.of_node, 0, &res)) {
647 + printk(KERN_ERR "rbppc_cf_probe: No reg property found\n");
651 + host = ata_host_alloc(&pdev->dev, 1);
655 + baddr = localbus_map(res.start, res.end - res.start + 1);
656 + host->iomap = baddr;
657 + host->private_data = rbinfo;
659 + ap = host->ports[0];
660 + ap->ops = &rbppc_cf_port_ops;
661 + ap->pio_mask = 0x7F; /* PIO modes 0-6 */
662 + ap->mwdma_mask = 0;
664 + ap->ioaddr.cmd_addr = baddr;
665 + ata_sff_std_ports(&ap->ioaddr);
666 + ap->ioaddr.ctl_addr = ap->ioaddr.cmd_addr + 14;
667 + ap->ioaddr.altstatus_addr = ap->ioaddr.ctl_addr;
668 + ap->ioaddr.bmdma_addr = 0;
670 + err = ata_host_activate(
672 + irq_of_parse_and_map(pdev->dev.of_node, 0), ata_sff_interrupt,
673 + irq_level ? IRQF_TRIGGER_HIGH : IRQF_TRIGGER_LOW,
675 + if (!err) return 0;
677 + localbus_unmap(baddr);
686 +static int rbppc_cf_remove(struct platform_device *pdev)
688 + struct device *dev = &pdev->dev;
689 + struct ata_host *host = dev_get_drvdata(dev);
691 + if (host == NULL) return -1;
693 + ata_host_detach(host);
697 +static struct of_device_id rbppc_cf_ids[] = {
702 +static struct platform_driver rbppc_cf_driver = {
703 + .probe = rbppc_cf_probe,
704 + .remove = rbppc_cf_remove,
706 + .name = "rbppc-cf",
707 + .owner = THIS_MODULE,
708 + .of_match_table = rbppc_cf_ids,
712 +static int __init rbppc_init(void)
714 + return platform_driver_register(&rbppc_cf_driver);
717 +static void __exit rbppc_exit(void)
719 + platform_driver_unregister(&rbppc_cf_driver);
722 +MODULE_AUTHOR("Mikrotikls SIA");
723 +MODULE_AUTHOR("Noah Fontes");
724 +MODULE_DESCRIPTION("MikroTik RouterBOARD 600 series Compact Flash PATA driver");
725 +MODULE_LICENSE("GPL");
726 +MODULE_VERSION(DRV_VERSION);
728 +module_init(rbppc_init);
729 +module_exit(rbppc_exit);