target/linux/mpc85xx/files/arch/powerpc/boot/dts/hiveap-330.dts

   1 /*
   2  * Aerohive HiveAP-330 Device Tree Source
   3  *
   4  * Copyright (C) 2017 Chris Blake <chrisrblake93@gmail.com>
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  */
  11
  12 #include <dt-bindings/leds/common.h>
  13 #include <dt-bindings/input/input.h>
  14 #include <dt-bindings/gpio/gpio.h>
  15
  16 /include/ "fsl/p1020si-pre.dtsi"
  17 / {
  18         model = "Aerohive HiveAP-330";
  19         compatible = "aerohive,hiveap-330";
  20
  21         aliases {
  22                 led-boot = &led_power_green;
  23                 led-failsafe = &led_fault_red;
  24                 led-running = &led_power_green;
  25                 led-upgrade = &led_fault_red;
  26                 label-mac-device = &enet0;
  27                 spi0 = &spi0;
  28         };
  29
  30         chosen {
  31                 /*
  32                  * not yet implemented.
  33                  * stdout-path = &serial0 ":9600n8";
  34                  * <https://www.spinics.net/lists/devicetree-compiler/msg02487.html>
  35                  *
  36                  * this should work... but it doesn't because CONFIG_CMDLINE in our
  37                  * OpenWrt's target config sets "console=ttyS0,115200"
  38                  * stdout-path = "/soc@ffe00000/serial@4500:9600n8";
  39                  */
  40
  41                 bootargs = "console=ttyS0,9600n8";
  42         };
  43
  44         cpus {
  45                 PowerPC,P1020@0 {
  46                         i-cache-sets = <0x80>;
  47                         i-cache-size = <0x8000>;
  48                         i-cache-block-size = <0x20>;
  49                         d-cache-sets = <0x80>;
  50                         d-cache-size = <0x8000>;
  51                         d-cache-block-size = <0x20>;
  52                         status = "okay";
  53                         clock-frequency = <533333328>; /* 533.33 MHz */
  54                         bus-frequency = <266666664>;  /* 266.66 MHz */
  55                         timebase-frequency = <33333333>; /* 33.33 MHz */
  56                 };
  57
  58                 PowerPC,P1020@1 {
  59                         i-cache-sets = <0x80>;
  60                         i-cache-size = <0x8000>;
  61                         i-cache-block-size = <0x20>;
  62                         d-cache-sets = <0x80>;
  63                         d-cache-size = <0x8000>;
  64                         d-cache-block-size = <0x20>;
  65                         cpu-release-addr = <0x00 0xffff240>;
  66                         enable-method = "spin-table";
  67                         status = "disabled";
  68                         clock-frequency = <533333328>;
  69                         bus-frequency = <266666664>;
  70                         timebase-frequency = <33333333>;
  71                 };
  72         };
  73
  74         memory {
  75                 #address-cells = <2>;
  76                 #size-cells = <2>;
  77
  78                 reg = <0x00 0x00 0x00 0x10000000>;
  79                 device_type = "memory";
  80         };
  81
  82         /*
  83          * Usually, u-boot provided /memreserve/ properties by adding them during boot.
  84          * these have been converted to reserved-memory entries.
  85          */
  86         reserved-memory {
  87                 #address-cells = <2>;
  88                 #size-cells = <2>;
  89                 ranges;
  90
  91                 /*
  92                  * /memreserve/   0x0000000000ffa000 0x0000000000004000;
  93                  * The kernel complains when booting:
  94                  *
  95                  * | OF: fdt: Reserved memory: failed to reserve memory for node
  96                  *              'firmware@ffa000': base 0x00ffa000, size 0 MiB
  97                  *
  98                  * But this likely uboot's bootargs + modified DTB. And if so, we don't care.
  99                  * This is because we rely on our own dtb that's in the simpleImage.
 100                  *
 101                  * Note: This is backed up by u-boot. just before the kernel executes
 102                  *       it prints this final line:
 103                  *       |  Loading Device Tree to 00ff9000, end 00fff1c4 ... OK
 104                  *
 105                  * firmware@ffa000 {
 106                  *      reg = <0x0 0xffa000 0x0 0x4000>;
 107                  *      no-map;
 108                  * };
 109                  */
 110
 111                 // /memreserve/   0x000000000fe2f000 0x0000000000000021;
 112                 firmware@fe2f000 {
 113                         reg = <0x0 0xfe2f000 0x0 0x21>;
 114                         no-map;
 115                 };
 116
 117                 /*
 118                  * /memreserve/   0x000000000ffff000 0x0000000000001000;
 119                  * that's the spin-table - see second CPU core binding.
 120                  */
 121                 firmware@ffff000 {
 122                         reg = <0x0 0xffff000 0x0 0x1000>;
 123                         no-map;
 124                 };
 125         };
 126
 127         board_lbc: lbc: localbus@ffe05000 {
 128                 bus-frequency = <16666666>; /* 16.66 MHz */
 129                 reg = <0 0xffe05000 0 0x1000>;
 130                 ranges = <0x0 0x0 0x0 0xec000000 0x4000000>;
 131
 132                 nor@0 {
 133                         #address-cells = <1>;
 134                         #size-cells = <1>;
 135                         compatible = "cfi-flash";
 136                         reg = <0x0 0x0 0x4000000>;
 137                         bank-width = <2>;
 138                         device-width = <1>;
 139
 140                         partitions {
 141                                 compatible = "fixed-partitions";
 142                                 #address-cells = <1>;
 143                                 #size-cells = <1>;
 144
 145                                 firmware@0 {
 146                                         reg = <0x0 0x3f00000>;
 147                                         label = "firmware";
 148                                         /*
 149                                          * This unknown/invalid compatible prevents
 150                                          * openwrt's mtdsplit_fit to go off a tangent if it
 151                                          * finds a magic value inside the uncompressed kernel
 152                                          * at a blocksized aligned place.
 153                                          */
 154                                         compatible = "areohive,hiveap-330-image";
 155                                 };
 156
 157                                 partition@0 {
 158                                         reg = <0x0 0x40000>;
 159                                         label = "dtb";
 160                                 };
 161
 162                                 partition@40000 {
 163                                         compatible = "openwrt,uimage", "denx,uimage";
 164                                         reg = <0x40000 0x3ec0000>;
 165                                         label = "kernel";
 166                                 };
 167
 168                                 partition@3f00000 {
 169                                         reg = <0x3f00000 0x20000>;
 170                                         label = "hw-info";
 171                                         read-only;
 172
 173                                         nvmem-layout {
 174                                                 compatible = "fixed-layout";
 175                                                 #address-cells = <1>;
 176                                                 #size-cells = <1>;
 177
 178                                                 macaddr_hwinfo_0: macaddr@0 {
 179                                                         compatible = "mac-base";
 180                                                         reg = <0x0 0x6>;
 181                                                         #nvmem-cell-cells = <1>;
 182                                                 };
 183                                         };
 184                                 };
 185
 186                                 partition@3f20000 {
 187                                         reg = <0x3f20000 0x20000>;
 188                                         label = "boot-info";
 189                                         read-only;
 190                                 };
 191
 192                                 partition@3f40000 {
 193                                         reg = <0x3f40000 0x20000>;
 194                                         label = "boot-info-backup";
 195                                         read-only;
 196                                 };
 197
 198                                 partition@3f60000 {
 199                                         reg = <0x3f60000 0x20000>;
 200                                         label = "u-boot-env";
 201                                 };
 202
 203                                 partition@3f80000 {
 204                                         reg = <0x3f80000 0x80000>;
 205                                         label = "u-boot";
 206                                         read-only;
 207                                 };
 208                         };
 209                 };
 210         };
 211
 212         board_soc: soc: soc@ffe00000 {
 213                 ranges = <0x0 0x0 0xffe00000 0x100000>;
 214                 bus-frequency = <266666664>;
 215
 216                 spi0: spi@7000 {
 217                         #address-cells = <1>;
 218                         #size-cells = <0>;
 219
 220                         temperature-sensor@1 {
 221                                 compatible = "ti,tmp125";
 222                                 reg = <1>;
 223                                 spi-max-frequency = <5000000>;
 224                         };
 225                 };
 226
 227                 i2c@3100 {
 228                         tpm@29 {
 229                                 compatible = "atmel,at97sc3204t";
 230                                 reg = <0x29>;
 231                         };
 232
 233                         lp5521@32 {
 234                                 compatible = "national,lp5521";
 235                                 reg = <0x32>;
 236                                 clock-mode = /bits/ 8 <2>;
 237                                 #address-cells = <1>;
 238                                 #size-cells = <0>;
 239
 240 #if 1
 241                                 led_fault_red: led@0 {
 242                                         reg = <0>;
 243                                         chan-name = "fault:red";
 244                                         led-cur = /bits/ 8 <0x2f>;
 245                                         max-cur = /bits/ 8 <0x5f>;
 246                                         color = <LED_COLOR_ID_RED>;
 247                                         function = LED_FUNCTION_FAULT;
 248                                 };
 249                                 led_power_green: led@1 {
 250                                         reg = <1>;
 251                                         chan-name = "power:green";
 252                                         led-cur = /bits/ 8 <0x2f>;
 253                                         max-cur = /bits/ 8 <0x5f>;
 254                                         color = <LED_COLOR_ID_GREEN>;
 255                                         function = LED_FUNCTION_POWER;
 256                                 };
 257                                 led@2{
 258                                         reg = <2>;
 259                                         chan-name = "blue";
 260                                         led-cur = /bits/ 8 <0x2f>;
 261                                         max-cur = /bits/ 8 <0x5f>;
 262                                         color = <LED_COLOR_ID_BLUE>;
 263                                 };
 264 #else
 265                                 /*
 266                                  * openwrt isn't ready to handle multi-intensity leds yet
 267                                  * # echo 255 255 255 > /sys/class/leds/tricolor/multi_intensity
 268                                  * # echo 255 > /sys/class/leds/tricolor/brightness
 269                                  */
 270
 271                                 rgbled-0 {
 272                                         function = LED_FUNCTION_POWER;
 273                                         color = <LED_COLOR_ID_RGB>;
 274                                         #address-cells = <1>;
 275                                         #size-cells = <0>;
 276
 277                                         led@0 {
 278                                                 reg = <0>;
 279                                                 chan-name = "tricolor";
 280                                                 led-cur = /bits/ 8 <0x2f>;
 281                                                 max-cur = /bits/ 8 <0x5f>;
 282                                                 color = <LED_COLOR_ID_RED>;
 283                                         };
 284                                         led@1 {
 285                                                 reg = <1>;
 286                                                 chan-name = "tricolor";
 287                                                 led-cur = /bits/ 8 <0x2f>;
 288                                                 max-cur = /bits/ 8 <0x5f>;
 289                                                 color = <LED_COLOR_ID_GREEN>;
 290                                         };
 291                                         led@2{
 292                                                 reg = <2>;
 293                                                 chan-name = "tricolor";
 294                                                 led-cur = /bits/ 8 <0x2f>;
 295                                                 max-cur = /bits/ 8 <0x5f>;
 296                                                 color = <LED_COLOR_ID_BLUE>;
 297                                         };
 298                                 };
 299 #endif
 300                         };
 301
 302                         eeprom@51 {
 303                                 /*
 304                                  * 1Kbit I2C/SMBus EEPROM with SHA-1 Engine
 305                                  * Aerohive calls it "dallas".
 306                                  */
 307                                 compatible = "adi,ds28cn01";
 308                                 reg = <0x51>;
 309                                 read-only;
 310                         };
 311                 };
 312
 313                 mdio@24000 {
 314                         phy0: ethernet-phy@0 {
 315                                 /* interrupts = <3 1 0 0>; */
 316                                 reg = <0x1>;
 317                         };
 318
 319                         phy1: ethernet-phy@1 {
 320                                 /* interrupts = <2 1 0 0>; */
 321                                 reg = <0x2>;
 322                         };
 323                 };
 324
 325                 mdio@25000 {
 326                         status = "disabled";
 327                 };
 328
 329                 mdio@26000 {
 330                         status = "disabled";
 331                 };
 332
 333                 enet0: ethernet@b0000 {
 334                         rx-stash-idx = <0x00>;
 335                         rx-stash-len = <0x60>;
 336                         bd-stash;
 337                         status = "okay";
 338                         phy-handle = <&phy0>;
 339                         phy-connection-type = "rgmii-id";
 340                         nvmem-cells = <&macaddr_hwinfo_0 0>;
 341                         nvmem-cell-names = "mac-address";
 342                 };
 343
 344                 enet1: ethernet@b1000 {
 345                         status = "disabled";
 346                 };
 347
 348                 enet2: ethernet@b2000 {
 349                         rx-stash-idx = <0x00>;
 350                         rx-stash-len = <0x60>;
 351                         bd-stash;
 352                         status = "okay";
 353                         phy-handle = <&phy1>;
 354                         phy-connection-type = "rgmii-id";
 355                         nvmem-cells = <&macaddr_hwinfo_0 1>;
 356                         nvmem-cell-names = "mac-address";
 357                 };
 358
 359                 gpio0: gpio-controller@fc00 {
 360                 };
 361
 362                 usb@22000 {
 363                         phy_type = "ulpi";
 364                         dr_mode = "host";
 365                 };
 366
 367                 usb@23000 {
 368                         status = "disabled";
 369                 };
 370         };
 371
 372         pci0: pcie@ffe09000 {
 373                 reg = <0x0 0xffe09000 0x0 0x1000>;
 374                 ranges = <0x2000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x20000000>,
 375                          <0x1000000 0x0 0x00000000 0x0 0xffc30000 0x0 0x10000>;
 376                 pcie@0 {
 377                         ranges = <0x2000000 0x0 0xa0000000 0x2000000 0x0 0xa0000000 0x0 0x20000000>,
 378                                  <0x1000000 0x0 0x00000000 0x1000000 0x0 0x00000000 0x0 0x00100000>;
 379                 };
 380         };
 381
 382         pci1: pcie@ffe0a000 {
 383                 reg = <0x0 0xffe0a000 0x0 0x1000>;
 384                 ranges = <0x2000000 0x0 0xc0000000 0x0 0xc0000000 0x0 0x20000000>,
 385                          <0x1000000 0x0 0x00000000 0x0 0xffc20000 0x0 0x10000>;
 386
 387                 pcie@0 {
 388                         ranges = <0x2000000 0x0 0xc0000000 0x2000000 0x0 0xc0000000 0x0 0x20000000>,
 389                                  <0x1000000 0x0 0x00000000 0x1000000 0x0 0x00000000 0x0 0x00100000>;
 390                 };
 391         };
 392
 393         buttons {
 394                 compatible = "gpio-keys";
 395
 396                 reset {
 397                         label = "Reset button";
 398                         gpios = <&gpio0 8 GPIO_ACTIVE_LOW>;
 399                         linux,code = <KEY_RESTART>;
 400                 };
 401         };
 402 };
 403
 404 /include/ "fsl/p1020si-post.dtsi"
 405 &serial0 {
 406         clock-frequency = <266666664>;
 407 };
 408
 409 &serial1 {
 410         clock-frequency = <266666664>;
 411 };
 412
 413 /*
 414  * For the OpenWrt 22.03 release, since Linux 5.10.138 now uses
 415  * aliases to determine PCI domain numbers, drop aliases so as not to
 416  * change the sysfs path of our wireless netdevs.
 417  */
 418
 419 / {
 420         aliases {
 421                 /delete-property/ pci0;
 422                 /delete-property/ pci1;
 423         };
 424 };