target/linux/mpc85xx/image/spi-loader/drivers/spi/fsl_espi.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * eSPI controller driver.
   4  *
   5  * Copyright (c) 2022 Matthias Schiffer <mschiffer@universe-factory.net>
   6  *
   7  * Based on U-Boot code:
   8  *
   9  * Copyright 2010-2011 Freescale Semiconductor, Inc.
  10  * Copyright 2020 NXP
  11  * Author: Mingkai Hu (Mingkai.hu@freescale.com)
  12  *         Chuanhua Han (chuanhua.han@nxp.com)
  13  */
  14
  15 #include <io.h>
  16 #include <stdio.h>
  17 #include <spi.h>
  18
  19 /* eSPI Registers */
  20 typedef struct ccsr_espi {
  21         uint32_t mode;       /* eSPI mode */
  22         uint32_t event;      /* eSPI event */
  23         uint32_t mask;       /* eSPI mask */
  24         uint32_t com;        /* eSPI command */
  25         uint32_t tx;         /* eSPI transmit FIFO access */
  26         uint32_t rx;         /* eSPI receive FIFO access */
  27         uint8_t  res1[8];    /* reserved */
  28         uint32_t csmode[4];  /* 0x2c: sSPI CS0/1/2/3 mode */
  29         uint8_t  res2[4048]; /* fill up to 0x1000 */
  30 } ccsr_espi_t;
  31
  32 struct fsl_spi {
  33         ccsr_espi_t     *espi;
  34         uint32_t        cs;
  35         uint32_t        div16;
  36         uint32_t        pm;
  37         uint32_t        mode;
  38 };
  39
  40 #define ESPI_MAX_CS_NUM         4
  41 #define ESPI_FIFO_WIDTH_BIT     32
  42
  43 #define ESPI_EV_RNE             BIT(9)
  44 #define ESPI_EV_TNF             BIT(8)
  45 #define ESPI_EV_DON             BIT(14)
  46 #define ESPI_EV_TXE             BIT(15)
  47 #define ESPI_EV_RFCNT_SHIFT     24
  48 #define ESPI_EV_RFCNT_MASK      (0x3f << ESPI_EV_RFCNT_SHIFT)
  49
  50 #define ESPI_MODE_EN            BIT(31) /* Enable interface */
  51 #define ESPI_MODE_TXTHR(x)      ((x) << 8)      /* Tx FIFO threshold */
  52 #define ESPI_MODE_RXTHR(x)      ((x) << 0)      /* Rx FIFO threshold */
  53
  54 #define ESPI_COM_CS(x)          ((x) << 30)
  55 #define ESPI_COM_TRANLEN(x)     ((x) << 0)
  56
  57 #define ESPI_CSMODE_CI_INACTIVEHIGH     BIT(31)
  58 #define ESPI_CSMODE_CP_BEGIN_EDGCLK     BIT(30)
  59 #define ESPI_CSMODE_REV_MSB_FIRST       BIT(29)
  60 #define ESPI_CSMODE_DIV16               BIT(28)
  61 #define ESPI_CSMODE_PM(x)               ((x) << 24)
  62 #define ESPI_CSMODE_POL_ASSERTED_LOW    BIT(20)
  63 #define ESPI_CSMODE_LEN(x)              ((x) << 16)
  64 #define ESPI_CSMODE_CSBEF(x)            ((x) << 12)
  65 #define ESPI_CSMODE_CSAFT(x)            ((x) << 8)
  66 #define ESPI_CSMODE_CSCG(x)             ((x) << 3)
  67
  68 #define ESPI_CSMODE_INIT_VAL (ESPI_CSMODE_POL_ASSERTED_LOW | \
  69                 ESPI_CSMODE_CSBEF(0) | ESPI_CSMODE_CSAFT(0) | \
  70                 ESPI_CSMODE_CSCG(1))
  71
  72 #define ESPI_MAX_DATA_TRANSFER_LEN 0x10000
  73
  74 static int espi_xfer(struct fsl_spi *fsl, const struct spi_transfer *msg, int n)
  75 {
  76         ccsr_espi_t *espi = fsl->espi;
  77         size_t len = spi_message_len(msg, n);
  78
  79         if (len > ESPI_MAX_DATA_TRANSFER_LEN)
  80                 return -1;
  81
  82         /* clear the RXCNT and TXCNT */
  83         out_be32(&espi->mode, in_be32(&espi->mode) & (~ESPI_MODE_EN));
  84         out_be32(&espi->mode, in_be32(&espi->mode) | ESPI_MODE_EN);
  85         out_be32(&espi->com, ESPI_COM_CS(fsl->cs) | ESPI_COM_TRANLEN(len - 1));
  86
  87         int last_msg = n - 1;
  88         int tx_msg = -1, rx_msg = -1;
  89         size_t tx_len = 0, rx_len = 0, tx_pos = 0, rx_pos = 0;
  90
  91         while (true) {
  92                 if (tx_pos == tx_len && tx_msg < last_msg) {
  93                         tx_msg++;
  94                         tx_pos = 0;
  95                         tx_len = msg[tx_msg].len;
  96                 }
  97                 if (rx_pos == rx_len && rx_msg < last_msg) {
  98                         rx_msg++;
  99                         rx_pos = 0;
 100                         rx_len = msg[rx_msg].len;
 101                 }
 102                 if (rx_pos == rx_len)
 103                         break;
 104
 105                 const uint8_t *tx_buf = msg[tx_msg].tx_buf;
 106                 uint8_t *rx_buf = msg[rx_msg].rx_buf;
 107
 108                 uint32_t event = in_be32(&espi->event);
 109
 110                 /* TX */
 111                 if ((event & ESPI_EV_TNF) && tx_len > 0) {
 112                         uint8_t v = 0;
 113                         if (tx_buf)
 114                                 v = tx_buf[tx_pos];
 115                         out_8((uint8_t *)&espi->tx, v);
 116                         tx_pos++;
 117                 }
 118
 119                 /* RX */
 120                 if (event & ESPI_EV_RNE) {
 121                         uint8_t v = in_8((uint8_t *)&espi->rx);
 122                         if (rx_buf)
 123                                 rx_buf[rx_pos] = v;
 124                         rx_pos++;
 125                 }
 126         }
 127
 128         return 0;
 129 }
 130
 131 static void espi_claim_bus(struct fsl_spi *fsl)
 132 {
 133         ccsr_espi_t *espi = fsl->espi;
 134         uint32_t csmode;
 135         int i;
 136
 137         /* Enable eSPI interface */
 138         out_be32(&espi->mode, ESPI_MODE_RXTHR(3)
 139                         | ESPI_MODE_TXTHR(4) | ESPI_MODE_EN);
 140
 141         out_be32(&espi->mask, 0x00000000); /* Mask  all eSPI interrupts */
 142
 143         /* Init CS mode interface */
 144         for (i = 0; i < ESPI_MAX_CS_NUM; i++)
 145                 out_be32(&espi->csmode[i], ESPI_CSMODE_INIT_VAL);
 146
 147         csmode = ESPI_CSMODE_INIT_VAL;
 148
 149         /* Set eSPI BRG clock source */
 150         csmode |= ESPI_CSMODE_PM(fsl->pm) | fsl->div16;
 151
 152         /* Set eSPI mode */
 153         if (fsl->mode & SPI_CPHA)
 154                 csmode |= ESPI_CSMODE_CP_BEGIN_EDGCLK;
 155         if (fsl->mode & SPI_CPOL)
 156                 csmode |= ESPI_CSMODE_CI_INACTIVEHIGH;
 157
 158         /* Character bit order: msb first */
 159         csmode |= ESPI_CSMODE_REV_MSB_FIRST;
 160
 161         /* Character length in bits, between 0x3~0xf, i.e. 4bits~16bits */
 162         csmode |= ESPI_CSMODE_LEN(7);
 163
 164         out_be32(&espi->csmode[fsl->cs], csmode);
 165 }
 166
 167 static void espi_release_bus(struct fsl_spi *fsl)
 168 {
 169         /* Disable the SPI hardware */
 170         out_be32(&fsl->espi->mode,
 171                 in_be32(&fsl->espi->mode) & (~ESPI_MODE_EN));
 172 }
 173
 174 static void espi_setup_spi(struct fsl_spi *fsl, unsigned int max_hz)
 175 {
 176         unsigned long spibrg;
 177         uint32_t pm;
 178
 179         spibrg = CONFIG_FREQ_SYSTEMBUS / 2;
 180         fsl->div16 = 0;
 181         if ((spibrg / max_hz) > 32) {
 182                 fsl->div16 = ESPI_CSMODE_DIV16;
 183                 pm = spibrg / (max_hz * 16 * 2);
 184                 if (pm > 16) {
 185                         /* max_hz too low */
 186                         pm = 16;
 187                 }
 188         } else {
 189                 pm = spibrg / (max_hz * 2);
 190         }
 191         if (pm)
 192                 pm--;
 193         fsl->pm = pm;
 194 }
 195
 196 static struct fsl_spi spi;
 197
 198 int spi_init(unsigned int cs, unsigned int max_hz, unsigned int mode)
 199 {
 200         if (cs >= ESPI_MAX_CS_NUM)
 201                 return -1;
 202
 203         spi.espi = (ccsr_espi_t *)CONFIG_SPI_FSL_ESPI_REG_BASE;
 204         spi.cs = cs;
 205         spi.mode = mode;
 206
 207         espi_setup_spi(&spi, max_hz);
 208
 209         return 0;
 210 }
 211
 212 int spi_claim_bus(void)
 213 {
 214         espi_claim_bus(&spi);
 215
 216         return 0;
 217 }
 218
 219 void spi_release_bus(void)
 220 {
 221         espi_release_bus(&spi);
 222 }
 223
 224 int spi_xfer(const struct spi_transfer *msg, int n)
 225 {
 226         return espi_xfer(&spi, msg, n);
 227 }
 228
 229 size_t spi_max_xfer(void)
 230 {
 231         return ESPI_MAX_DATA_TRANSFER_LEN;
 232 }