target/linux/mvebu/files/arch/arm64/boot/dts/marvell/cn9131-puzzle-m901.dts

   1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
   2 /*
   3  * Copyright (C) 2019 Marvell International Ltd.
   4  *
   5  * Device tree for the CN9131-DB board.
   6  */
   7
   8 #include "cn9130.dtsi"
   9 #include "puzzle-thermal.dtsi"
  10
  11 #include <dt-bindings/gpio/gpio.h>
  12 #include <dt-bindings/input/input.h>
  13
  14 / {
  15         model = "iEi Puzzle-M901";
  16         compatible = "iei,puzzle-m901",
  17                      "marvell,armada-ap807-quad", "marvell,armada-ap807";
  18
  19         chosen {
  20                 stdout-path = "serial0:115200n8";
  21         };
  22
  23         aliases {
  24                 i2c0 = &cp1_i2c0;
  25                 i2c1 = &cp0_i2c0;
  26                 ethernet0 = &cp0_eth0;
  27                 ethernet1 = &cp0_eth1;
  28                 ethernet2 = &cp0_eth2;
  29                 ethernet3 = &cp1_eth0;
  30                 ethernet4 = &cp1_eth1;
  31                 ethernet5 = &cp1_eth2;
  32                 gpio1 = &cp0_gpio1;
  33                 gpio2 = &cp0_gpio2;
  34                 gpio3 = &cp1_gpio1;
  35                 gpio4 = &cp1_gpio2;
  36                 led-boot = &led_power;
  37                 led-failsafe = &led_info;
  38                 led-running = &led_power;
  39                 led-upgrade = &led_info;
  40         };
  41
  42         memory@00000000 {
  43                 device_type = "memory";
  44                 reg = <0x0 0x0 0x0 0x80000000>;
  45         };
  46
  47         gpio_keys {
  48                 compatible = "gpio-keys";
  49
  50                 reset {
  51                         label = "Reset";
  52                         linux,code = <KEY_RESTART>;
  53                         gpios = <&cp0_gpio2 4 GPIO_ACTIVE_LOW>;
  54                 };
  55         };
  56 };
  57
  58 &uart0 {
  59         status = "okay";
  60 };
  61
  62 &cp0_uart0 {
  63         status = "okay";
  64
  65         puzzle-mcu {
  66                 compatible = "iei,wt61p803-puzzle";
  67                 #address-cells = <1>;
  68                 #size-cells = <1>;
  69                 current-speed = <115200>;
  70                 enable-beep;
  71                 status = "okay";
  72
  73                 leds {
  74                         compatible = "iei,wt61p803-puzzle-leds";
  75                         #address-cells = <1>;
  76                         #size-cells = <0>;
  77                         status = "okay";
  78
  79                         led@0 {
  80                                 reg = <0>;
  81                                 label = "white:network";
  82                                 active-low;
  83                         };
  84
  85                         led@1 {
  86                                 reg = <1>;
  87                                 label = "green:cloud";
  88                                 active-low;
  89                         };
  90
  91                         led_info: led@2 {
  92                                 reg = <2>;
  93                                 label = "orange:info";
  94                                 active-low;
  95                         };
  96
  97                         led_power: led@3 {
  98                                 reg = <3>;
  99                                 label = "yellow:power";
 100                                 active-low;
 101                                 default-state = "on";
 102                         };
 103                 };
 104
 105                 hwmon {
 106                         compatible = "iei,wt61p803-puzzle-hwmon";
 107                         #address-cells = <1>;
 108                         #size-cells = <0>;
 109
 110                         chassis_fan_group0: fan-group@0 {
 111                                 #cooling-cells = <2>;
 112                                 reg = <0x00>;
 113                                 cooling-levels = <80 102 170 230 255>;
 114                         };
 115                 };
 116         };
 117 };
 118
 119 &ap_thermal_ic {
 120         PUZZLE_FAN_THERMAL(ic, &chassis_fan_group0);
 121 };
 122
 123 &cp0_thermal_ic {
 124         PUZZLE_FAN_THERMAL(cp0, &chassis_fan_group0);
 125 };
 126
 127 /* on-board eMMC - U9 */
 128 &ap_sdhci0 {
 129         pinctrl-names = "default";
 130         bus-width = <8>;
 131         status = "okay";
 132         mmc-ddr-1_8v;
 133         mmc-hs400-1_8v;
 134 };
 135
 136 &cp0_crypto {
 137         status = "okay";
 138 };
 139
 140 &cp0_xmdio {
 141         status = "okay";
 142         cp0_nbaset_phy0: ethernet-phy@0 {
 143                 compatible = "ethernet-phy-ieee802.3-c45";
 144                 reg = <2>;
 145         };
 146         cp0_nbaset_phy1: ethernet-phy@1 {
 147                 compatible = "ethernet-phy-ieee802.3-c45";
 148                 reg = <0>;
 149         };
 150         cp0_nbaset_phy2: ethernet-phy@2 {
 151                 compatible = "ethernet-phy-ieee802.3-c45";
 152                 reg = <8>;
 153         };
 154 };
 155
 156 &cp0_ethernet {
 157         status = "okay";
 158 };
 159
 160 /* SLM-1521-V2, CON9 */
 161 &cp0_eth0 {
 162         status = "okay";
 163         phy-mode = "2500base-x";
 164         phys = <&cp0_comphy2 0>;
 165         phy = <&cp0_nbaset_phy0>;
 166 };
 167
 168 &cp0_eth1 {
 169         status = "okay";
 170         phy-mode = "2500base-x";
 171         phys = <&cp0_comphy4 1>;
 172         phy = <&cp0_nbaset_phy1>;
 173 };
 174
 175 &cp0_eth2 {
 176         status = "okay";
 177         phy-mode = "2500base-x";
 178         phys = <&cp0_comphy5 2>;
 179         phy = <&cp0_nbaset_phy2>;
 180 };
 181
 182 &cp0_gpio1 {
 183         status = "okay";
 184 };
 185
 186 &cp0_gpio2 {
 187         status = "okay";
 188 };
 189
 190 &cp0_i2c0 {
 191         pinctrl-names = "default";
 192         pinctrl-0 = <&cp0_i2c0_pins>;
 193         status = "okay";
 194         clock-frequency = <100000>;
 195         rtc@32 {
 196                 compatible = "epson,rx8130";
 197                 reg = <0x32>;
 198                 wakeup-source;
 199         };
 200 };
 201
 202 /* SLM-1521-V2, CON6 */
 203 &cp0_pcie0 {
 204         status = "okay";
 205         num-lanes = <2>;
 206         num-viewport = <8>;
 207         phys = <&cp0_comphy0 0>, <&cp0_comphy1 0>;
 208 };
 209
 210 /* U55 */
 211 &cp0_spi1 {
 212         pinctrl-names = "default";
 213         pinctrl-0 = <&cp0_spi0_pins>;
 214         reg = <0x700680 0x50>,          /* control */
 215               <0x2000000 0x1000000>;    /* CS0 */
 216         status = "okay";
 217         spi-flash@0 {
 218                 #address-cells = <0x1>;
 219                 #size-cells = <0x1>;
 220                 compatible = "jedec,spi-nor";
 221                 reg = <0x0>;
 222                 spi-max-frequency = <40000000>;
 223                 partitions {
 224                         compatible = "fixed-partitions";
 225                         #address-cells = <1>;
 226                         #size-cells = <1>;
 227                         partition@0 {
 228                                 label = "U-Boot";
 229                                 reg = <0x0 0x1f0000>;
 230                         };
 231                         partition@1f0000 {
 232                                 label = "U-Boot ENV Factory";
 233                                 reg = <0x1f0000 0x10000>;
 234                         };
 235                         partition@200000 {
 236                                 label = "Reserved";
 237                                 reg = <0x200000 0x1f0000>;
 238                         };
 239                         partition@3f0000 {
 240                                 label = "U-Boot ENV";
 241                                 reg = <0x3f0000 0x10000>;
 242                         };
 243                 };
 244         };
 245 };
 246
 247 &cp0_syscon0 {
 248         cp0_pinctrl: pinctrl {
 249                 compatible = "marvell,cp115-standalone-pinctrl";
 250                 cp0_i2c0_pins: cp0-i2c-pins-0 {
 251                         marvell,pins = "mpp37", "mpp38";
 252                         marvell,function = "i2c0";
 253                 };
 254                 cp0_i2c1_pins: cp0-i2c-pins-1 {
 255                         marvell,pins = "mpp35", "mpp36";
 256                         marvell,function = "i2c1";
 257                 };
 258                 cp0_ge1_rgmii_pins: cp0-ge-rgmii-pins-0 {
 259                         marvell,pins = "mpp0", "mpp1", "mpp2",
 260                                        "mpp3", "mpp4", "mpp5",
 261                                        "mpp6", "mpp7", "mpp8",
 262                                        "mpp9", "mpp10", "mpp11";
 263                         marvell,function = "ge0";
 264                 };
 265                 cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-1 {
 266                         marvell,pins = "mpp44", "mpp45", "mpp46",
 267                                        "mpp47", "mpp48", "mpp49",
 268                                        "mpp50", "mpp51", "mpp52",
 269                                        "mpp53", "mpp54", "mpp55";
 270                         marvell,function = "ge1";
 271                 };
 272                 cp0_spi0_pins: cp0-spi-pins-0 {
 273                         marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
 274                         marvell,function = "spi1";
 275                 };
 276         };
 277 };
 278
 279 /*
 280  * Instantiate the first connected CP115
 281  */
 282
 283 #define CP11X_NAME              cp1
 284 #define CP11X_BASE              f6000000
 285 #define CP11X_PCIEx_MEM_BASE(iface) (0xe2000000 + (iface * 0x1000000))
 286 #define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
 287 #define CP11X_PCIE0_BASE        f6600000
 288 #define CP11X_PCIE1_BASE        f6620000
 289 #define CP11X_PCIE2_BASE        f6640000
 290
 291 #include "armada-cp115.dtsi"
 292
 293 #undef CP11X_NAME
 294 #undef CP11X_BASE
 295 #undef CP11X_PCIEx_MEM_BASE
 296 #undef CP11X_PCIEx_MEM_SIZE
 297 #undef CP11X_PCIE0_BASE
 298 #undef CP11X_PCIE1_BASE
 299 #undef CP11X_PCIE2_BASE
 300
 301 &cp1_crypto {
 302         status = "okay";
 303 };
 304
 305 &cp1_xmdio {
 306         status = "okay";
 307         cp1_nbaset_phy0: ethernet-phy@3 {
 308                 compatible = "ethernet-phy-ieee802.3-c45";
 309                 reg = <2>;
 310         };
 311         cp1_nbaset_phy1: ethernet-phy@4 {
 312                 compatible = "ethernet-phy-ieee802.3-c45";
 313                 reg = <0>;
 314         };
 315         cp1_nbaset_phy2: ethernet-phy@5 {
 316                 compatible = "ethernet-phy-ieee802.3-c45";
 317                 reg = <8>;
 318         };
 319 };
 320
 321 &cp1_ethernet {
 322         status = "okay";
 323 };
 324
 325 /* CON50 */
 326 &cp1_eth0 {
 327         status = "okay";
 328         phy-mode = "2500base-x";
 329         phys = <&cp1_comphy2 0>;
 330         phy = <&cp1_nbaset_phy0>;
 331 };
 332
 333 &cp1_eth1 {
 334         status = "okay";
 335         phy-mode = "2500base-x";
 336         phys = <&cp1_comphy4 1>;
 337         phy = <&cp1_nbaset_phy1>;
 338 };
 339
 340 &cp1_eth2 {
 341         status = "okay";
 342         phy-mode = "2500base-x";
 343         phys = <&cp1_comphy5 2>;
 344         phy = <&cp1_nbaset_phy2>;
 345 };
 346
 347 &cp1_sata0 {
 348         status = "okay";
 349         sata-port@1 {
 350                 status = "okay";
 351                 phys = <&cp1_comphy0 1>;
 352         };
 353 };
 354
 355 &cp1_gpio1 {
 356         status = "okay";
 357 };
 358
 359 &cp1_gpio2 {
 360         status = "okay";
 361 };
 362
 363 &cp1_i2c0 {
 364         status = "okay";
 365         pinctrl-names = "default";
 366         pinctrl-0 = <&cp1_i2c0_pins>;
 367         clock-frequency = <100000>;
 368 };
 369
 370 &cp1_syscon0 {
 371         cp1_pinctrl: pinctrl {
 372                 compatible = "marvell,cp115-standalone-pinctrl";
 373                 cp1_i2c0_pins: cp1-i2c-pins-0 {
 374                         marvell,pins = "mpp37", "mpp38";
 375                         marvell,function = "i2c0";
 376                 };
 377                 cp1_spi0_pins: cp1-spi-pins-0 {
 378                         marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
 379                         marvell,function = "spi1";
 380                 };
 381                 cp1_xhci0_vbus_pins: cp1-xhci0-vbus-pins {
 382                         marvell,pins = "mpp3";
 383                         marvell,function = "gpio";
 384                 };
 385                 cp1_sfp_pins: sfp-pins {
 386                         marvell,pins = "mpp8", "mpp9", "mpp10", "mpp11";
 387                         marvell,function = "gpio";
 388                 };
 389         };
 390 };
 391
 392 &cp1_thermal_ic {
 393         PUZZLE_FAN_THERMAL(cp1, &chassis_fan_group0);
 394 };
 395
 396 &cp1_usb3_1 {
 397         status = "okay";
 398         phys = <&cp1_comphy3 1>;
 399         phy-names = "usb";
 400 };