1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
3 * Copyright (C) 2019 Marvell International Ltd.
5 * Device tree for the CN9131-DB board.
10 #include <dt-bindings/gpio/gpio.h>
13 model = "iEi Puzzle-M901";
14 compatible = "iei,puzzle-m901",
15 "marvell,armada-ap807-quad", "marvell,armada-ap807";
18 stdout-path = "serial0:115200n8";
24 ethernet0 = &cp0_eth0;
25 ethernet1 = &cp0_eth1;
26 ethernet2 = &cp0_eth2;
27 ethernet3 = &cp1_eth0;
28 ethernet4 = &cp1_eth1;
29 ethernet5 = &cp1_eth2;
37 device_type = "memory";
38 reg = <0x0 0x0 0x0 0x80000000>;
50 /* on-board eMMC - U9 */
52 pinctrl-names = "default";
65 cp0_nbaset_phy0: ethernet-phy@0 {
66 compatible = "ethernet-phy-ieee802.3-c45";
69 cp0_nbaset_phy1: ethernet-phy@1 {
70 compatible = "ethernet-phy-ieee802.3-c45";
73 cp0_nbaset_phy2: ethernet-phy@2 {
74 compatible = "ethernet-phy-ieee802.3-c45";
83 /* SLM-1521-V2, CON9 */
86 phy-mode = "2500base-x";
87 phys = <&cp0_comphy2 0>;
88 managed = "in-band-status";
93 phy-mode = "2500base-x";
94 phys = <&cp0_comphy4 1>;
95 managed = "in-band-status";
100 phy-mode = "2500base-x";
101 phys = <&cp0_comphy5 2>;
102 managed = "in-band-status";
114 pinctrl-names = "default";
115 pinctrl-0 = <&cp0_i2c0_pins>;
117 clock-frequency = <100000>;
119 compatible = "epson,rx8130";
125 /* SLM-1521-V2, CON6 */
130 phys = <&cp0_comphy0 0>, <&cp0_comphy1 0>;
135 pinctrl-names = "default";
136 pinctrl-0 = <&cp0_spi0_pins>;
137 reg = <0x700680 0x50>, /* control */
138 <0x2000000 0x1000000>; /* CS0 */
141 #address-cells = <0x1>;
143 compatible = "jedec,spi-nor";
145 spi-max-frequency = <40000000>;
147 compatible = "fixed-partitions";
148 #address-cells = <1>;
152 reg = <0x0 0x1f0000>;
155 label = "U-Boot ENV Factory";
156 reg = <0x1f0000 0x10000>;
160 reg = <0x200000 0x1f0000>;
163 label = "U-Boot ENV";
164 reg = <0x3f0000 0x10000>;
171 cp0_pinctrl: pinctrl {
172 compatible = "marvell,cp115-standalone-pinctrl";
173 cp0_i2c0_pins: cp0-i2c-pins-0 {
174 marvell,pins = "mpp37", "mpp38";
175 marvell,function = "i2c0";
177 cp0_i2c1_pins: cp0-i2c-pins-1 {
178 marvell,pins = "mpp35", "mpp36";
179 marvell,function = "i2c1";
181 cp0_ge1_rgmii_pins: cp0-ge-rgmii-pins-0 {
182 marvell,pins = "mpp0", "mpp1", "mpp2",
183 "mpp3", "mpp4", "mpp5",
184 "mpp6", "mpp7", "mpp8",
185 "mpp9", "mpp10", "mpp11";
186 marvell,function = "ge0";
188 cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-1 {
189 marvell,pins = "mpp44", "mpp45", "mpp46",
190 "mpp47", "mpp48", "mpp49",
191 "mpp50", "mpp51", "mpp52",
192 "mpp53", "mpp54", "mpp55";
193 marvell,function = "ge1";
195 cp0_spi0_pins: cp0-spi-pins-0 {
196 marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
197 marvell,function = "spi1";
203 * Instantiate the first connected CP115
206 #define CP11X_NAME cp1
207 #define CP11X_BASE f6000000
208 #define CP11X_PCIEx_MEM_BASE(iface) (0xe2000000 + (iface * 0x1000000))
209 #define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
210 #define CP11X_PCIE0_BASE f6600000
211 #define CP11X_PCIE1_BASE f6620000
212 #define CP11X_PCIE2_BASE f6640000
214 #include "armada-cp115.dtsi"
218 #undef CP11X_PCIEx_MEM_BASE
219 #undef CP11X_PCIEx_MEM_SIZE
220 #undef CP11X_PCIE0_BASE
221 #undef CP11X_PCIE1_BASE
222 #undef CP11X_PCIE2_BASE
230 cp1_nbaset_phy0: ethernet-phy@3 {
231 compatible = "ethernet-phy-ieee802.3-c45";
234 cp1_nbaset_phy1: ethernet-phy@4 {
235 compatible = "ethernet-phy-ieee802.3-c45";
238 cp1_nbaset_phy2: ethernet-phy@5 {
239 compatible = "ethernet-phy-ieee802.3-c45";
251 phy-mode = "2500base-x";
252 phys = <&cp1_comphy2 0>;
253 managed = "in-band-status";
258 phy-mode = "2500base-x";
259 phys = <&cp1_comphy4 1>;
260 managed = "in-band-status";
265 phy-mode = "2500base-x";
266 phys = <&cp1_comphy5 2>;
267 managed = "in-band-status";
274 phys = <&cp1_comphy0 1>;
288 pinctrl-names = "default";
289 pinctrl-0 = <&cp1_i2c0_pins>;
290 clock-frequency = <100000>;
294 cp1_pinctrl: pinctrl {
295 compatible = "marvell,cp115-standalone-pinctrl";
296 cp1_i2c0_pins: cp1-i2c-pins-0 {
297 marvell,pins = "mpp37", "mpp38";
298 marvell,function = "i2c0";
300 cp1_spi0_pins: cp1-spi-pins-0 {
301 marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
302 marvell,function = "spi1";
304 cp1_xhci0_vbus_pins: cp1-xhci0-vbus-pins {
305 marvell,pins = "mpp3";
306 marvell,function = "gpio";
308 cp1_sfp_pins: sfp-pins {
309 marvell,pins = "mpp8", "mpp9", "mpp10", "mpp11";
310 marvell,function = "gpio";
317 phys = <&cp1_comphy3 1>;