1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
3 * Copyright (C) 2019 Marvell International Ltd.
5 * Device tree for the CN9131-DB board.
9 #include "puzzle-thermal.dtsi"
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/leds/common.h>
16 model = "iEi Puzzle-M901";
17 compatible = "iei,puzzle-m901",
18 "marvell,armada-ap807-quad", "marvell,armada-ap807";
21 stdout-path = "serial0:115200n8";
27 ethernet0 = &cp0_eth0;
28 ethernet1 = &cp0_eth1;
29 ethernet2 = &cp0_eth2;
30 ethernet3 = &cp1_eth0;
31 ethernet4 = &cp1_eth1;
32 ethernet5 = &cp1_eth2;
37 led-boot = &led_power;
38 led-failsafe = &led_info;
39 led-running = &led_power;
40 led-upgrade = &led_info;
44 device_type = "memory";
45 reg = <0x0 0x0 0x0 0x80000000>;
49 compatible = "gpio-keys";
53 linux,code = <KEY_RESTART>;
54 gpios = <&cp0_gpio2 4 GPIO_ACTIVE_LOW>;
67 compatible = "iei,wt61p803-puzzle";
70 current-speed = <115200>;
75 compatible = "iei,wt61p803-puzzle-leds";
82 label = "white:network";
88 label = "green:cloud";
94 label = "orange:info";
100 function = LED_FUNCTION_POWER;
101 color = <LED_COLOR_ID_YELLOW>;
103 default-state = "on";
108 compatible = "iei,wt61p803-puzzle-hwmon";
109 #address-cells = <1>;
112 chassis_fan_group0: fan-group@0 {
113 #cooling-cells = <2>;
115 cooling-levels = <0 159 195 211 223 241 255>;
122 PUZZLE_FAN_THERMAL(ic, &chassis_fan_group0);
126 PUZZLE_FAN_THERMAL(cp0, &chassis_fan_group0);
129 /* on-board eMMC - U9 */
131 pinctrl-names = "default";
144 cp0_nbaset_phy0: ethernet-phy@0 {
145 compatible = "ethernet-phy-ieee802.3-c45";
148 cp0_nbaset_phy1: ethernet-phy@1 {
149 compatible = "ethernet-phy-ieee802.3-c45";
152 cp0_nbaset_phy2: ethernet-phy@2 {
153 compatible = "ethernet-phy-ieee802.3-c45";
162 /* SLM-1521-V2, CON9 */
165 phy-mode = "2500base-x";
166 phys = <&cp0_comphy2 0>;
167 phy = <&cp0_nbaset_phy0>;
172 phy-mode = "2500base-x";
173 phys = <&cp0_comphy4 1>;
174 phy = <&cp0_nbaset_phy1>;
179 phy-mode = "2500base-x";
180 phys = <&cp0_comphy5 2>;
181 phy = <&cp0_nbaset_phy2>;
193 pinctrl-names = "default";
194 pinctrl-0 = <&cp0_i2c0_pins>;
196 clock-frequency = <100000>;
198 compatible = "epson,rx8130";
204 /* SLM-1521-V2, CON6 */
209 phys = <&cp0_comphy0 0>, <&cp0_comphy1 0>;
214 pinctrl-names = "default";
215 pinctrl-0 = <&cp0_spi0_pins>;
216 reg = <0x700680 0x50>, /* control */
217 <0x2000000 0x1000000>; /* CS0 */
220 #address-cells = <0x1>;
222 compatible = "jedec,spi-nor";
224 spi-max-frequency = <40000000>;
226 compatible = "fixed-partitions";
227 #address-cells = <1>;
231 reg = <0x0 0x1f0000>;
234 label = "U-Boot ENV Factory";
235 reg = <0x1f0000 0x10000>;
239 reg = <0x200000 0x1f0000>;
242 label = "U-Boot ENV";
243 reg = <0x3f0000 0x10000>;
254 cp0_pinctrl: pinctrl {
255 compatible = "marvell,cp115-standalone-pinctrl";
256 cp0_i2c0_pins: cp0-i2c-pins-0 {
257 marvell,pins = "mpp37", "mpp38";
258 marvell,function = "i2c0";
260 cp0_i2c1_pins: cp0-i2c-pins-1 {
261 marvell,pins = "mpp35", "mpp36";
262 marvell,function = "i2c1";
264 cp0_ge1_rgmii_pins: cp0-ge-rgmii-pins-0 {
265 marvell,pins = "mpp0", "mpp1", "mpp2",
266 "mpp3", "mpp4", "mpp5",
267 "mpp6", "mpp7", "mpp8",
268 "mpp9", "mpp10", "mpp11";
269 marvell,function = "ge0";
271 cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-1 {
272 marvell,pins = "mpp44", "mpp45", "mpp46",
273 "mpp47", "mpp48", "mpp49",
274 "mpp50", "mpp51", "mpp52",
275 "mpp53", "mpp54", "mpp55";
276 marvell,function = "ge1";
278 cp0_spi0_pins: cp0-spi-pins-0 {
279 marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
280 marvell,function = "spi1";
286 * Instantiate the first connected CP115
289 #define CP11X_NAME cp1
290 #define CP11X_BASE f6000000
291 #define CP11X_PCIEx_MEM_BASE(iface) (0xe2000000 + (iface * 0x1000000))
292 #define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
293 #define CP11X_PCIE0_BASE f6600000
294 #define CP11X_PCIE1_BASE f6620000
295 #define CP11X_PCIE2_BASE f6640000
297 #include "armada-cp115.dtsi"
301 #undef CP11X_PCIEx_MEM_BASE
302 #undef CP11X_PCIEx_MEM_SIZE
303 #undef CP11X_PCIE0_BASE
304 #undef CP11X_PCIE1_BASE
305 #undef CP11X_PCIE2_BASE
313 cp1_nbaset_phy0: ethernet-phy@3 {
314 compatible = "ethernet-phy-ieee802.3-c45";
317 cp1_nbaset_phy1: ethernet-phy@4 {
318 compatible = "ethernet-phy-ieee802.3-c45";
321 cp1_nbaset_phy2: ethernet-phy@5 {
322 compatible = "ethernet-phy-ieee802.3-c45";
334 phy-mode = "2500base-x";
335 phys = <&cp1_comphy2 0>;
336 phy = <&cp1_nbaset_phy0>;
341 phy-mode = "2500base-x";
342 phys = <&cp1_comphy4 1>;
343 phy = <&cp1_nbaset_phy1>;
348 phy-mode = "2500base-x";
349 phys = <&cp1_comphy5 2>;
350 phy = <&cp1_nbaset_phy2>;
357 phys = <&cp1_comphy0 1>;
371 pinctrl-names = "default";
372 pinctrl-0 = <&cp1_i2c0_pins>;
373 clock-frequency = <100000>;
381 cp1_pinctrl: pinctrl {
382 compatible = "marvell,cp115-standalone-pinctrl";
383 cp1_i2c0_pins: cp1-i2c-pins-0 {
384 marvell,pins = "mpp37", "mpp38";
385 marvell,function = "i2c0";
387 cp1_spi0_pins: cp1-spi-pins-0 {
388 marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
389 marvell,function = "spi1";
391 cp1_xhci0_vbus_pins: cp1-xhci0-vbus-pins {
392 marvell,pins = "mpp3";
393 marvell,function = "gpio";
395 cp1_sfp_pins: sfp-pins {
396 marvell,pins = "mpp8", "mpp9", "mpp10", "mpp11";
397 marvell,function = "gpio";
403 PUZZLE_FAN_THERMAL(cp1, &chassis_fan_group0);
408 phys = <&cp1_comphy3 1>;