target/linux/mvebu/files/arch/arm64/boot/dts/marvell/cn9132-puzzle-m902.dts

   1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
   2 /*
   3  * Copyright (C) 2019 Marvell International Ltd.
   4  *
   5  * Device tree for the CN9132-DB board.
   6  */
   7
   8 #include "cn9130.dtsi"
   9 #include "puzzle-thermal.dtsi"
  10
  11 #include <dt-bindings/gpio/gpio.h>
  12 #include <dt-bindings/input/input.h>
  13
  14 / {
  15         model = "iEi Puzzle-M902";
  16         compatible = "iei,puzzle-m902",
  17                      "marvell,armada-ap807-quad", "marvell,armada-ap807";
  18
  19         chosen {
  20                 stdout-path = "serial0:115200n8";
  21         };
  22
  23         aliases {
  24                 i2c0 = &cp1_i2c0;
  25                 i2c1 = &cp0_i2c0;
  26                 gpio1 = &cp0_gpio1;
  27                 gpio2 = &cp0_gpio2;
  28                 gpio3 = &cp1_gpio1;
  29                 gpio4 = &cp1_gpio2;
  30                 gpio5 = &cp2_gpio1;
  31                 gpio6 = &cp2_gpio2;
  32                 ethernet0 = &cp0_eth0;
  33                 ethernet1 = &cp0_eth1;
  34                 ethernet2 = &cp0_eth2;
  35                 ethernet3 = &cp1_eth0;
  36                 ethernet4 = &cp1_eth1;
  37                 ethernet5 = &cp1_eth2;
  38                 ethernet6 = &cp2_eth0;
  39                 ethernet7 = &cp2_eth1;
  40                 ethernet8 = &cp2_eth2;
  41                 spi1 = &cp0_spi0;
  42                 spi2 = &cp0_spi1;
  43                 led-boot = &led_power;
  44                 led-failsafe = &led_info;
  45                 led-running = &led_power;
  46                 led-upgrade = &led_info;
  47         };
  48
  49         memory@00000000 {
  50                 device_type = "memory";
  51                 reg = <0x0 0x0 0x0 0x80000000>;
  52         };
  53
  54         gpio_keys {
  55                 compatible = "gpio-keys";
  56
  57                 reset {
  58                         label = "Reset";
  59                         linux,code = <KEY_RESTART>;
  60                         gpios = <&cp0_gpio2 4 GPIO_ACTIVE_LOW>;
  61                 };
  62         };
  63
  64         cp2_reg_usb3_vbus0: cp2_usb3_vbus@0 {
  65                 compatible = "regulator-fixed";
  66                 regulator-name = "cp2-xhci0-vbus";
  67                 regulator-min-microvolt = <5000000>;
  68                 regulator-max-microvolt = <5000000>;
  69                 enable-active-high;
  70                 gpio = <&cp2_gpio1 2 GPIO_ACTIVE_HIGH>;
  71         };
  72
  73         cp2_usb3_0_phy0: cp2_usb3_phy0 {
  74                 compatible = "usb-nop-xceiv";
  75                 vcc-supply = <&cp2_reg_usb3_vbus0>;
  76         };
  77
  78         cp2_reg_usb3_vbus1: cp2_usb3_vbus@1 {
  79                 compatible = "regulator-fixed";
  80                 regulator-name = "cp2-xhci1-vbus";
  81                 regulator-min-microvolt = <5000000>;
  82                 regulator-max-microvolt = <5000000>;
  83                 enable-active-high;
  84                 gpio = <&cp2_gpio1 3 GPIO_ACTIVE_HIGH>;
  85         };
  86
  87         cp2_usb3_0_phy1: cp2_usb3_phy1 {
  88                 compatible = "usb-nop-xceiv";
  89                 vcc-supply = <&cp2_reg_usb3_vbus1>;
  90         };
  91
  92         cp2_sfp_eth0: sfp-eth0 {
  93                 compatible = "sff,sfp";
  94                 i2c-bus = <&cp2_sfpp0_i2c>;
  95                 los-gpio = <&cp2_module_expander1 11 GPIO_ACTIVE_HIGH>;
  96                 mod-def0-gpio = <&cp2_module_expander1 10 GPIO_ACTIVE_LOW>;
  97                 tx-disable-gpio = <&cp2_module_expander1 9 GPIO_ACTIVE_HIGH>;
  98                 tx-fault-gpio = <&cp2_module_expander1 8 GPIO_ACTIVE_HIGH>;
  99                 status = "disabled";
 100         };
 101 };
 102
 103 &uart0 {
 104         status = "okay";
 105 };
 106
 107 &cp0_uart0 {
 108         status = "okay";
 109
 110         puzzle-mcu {
 111                 compatible = "iei,wt61p803-puzzle";
 112                 #address-cells = <1>;
 113                 #size-cells = <1>;
 114                 current-speed = <115200>;
 115                 enable-beep;
 116                 status = "okay";
 117
 118                 leds {
 119                         compatible = "iei,wt61p803-puzzle-leds";
 120                         #address-cells = <1>;
 121                         #size-cells = <0>;
 122                         status = "okay";
 123
 124                         led@0 {
 125                                 reg = <0>;
 126                                 label = "white:network";
 127                                 active-low;
 128                         };
 129
 130                         led@1 {
 131                                 reg = <1>;
 132                                 label = "green:cloud";
 133                                 active-low;
 134                         };
 135
 136                         led_info: led@2 {
 137                                 reg = <2>;
 138                                 label = "orange:info";
 139                                 active-low;
 140                         };
 141
 142                         led_power: led@3 {
 143                                 reg = <3>;
 144                                 label = "yellow:power";
 145                                 active-low;
 146                                 default-state = "on";
 147                         };
 148                 };
 149
 150                 hwmon {
 151                         compatible = "iei,wt61p803-puzzle-hwmon";
 152                         #address-cells = <1>;
 153                         #size-cells = <0>;
 154
 155                         chassis_fan_group0: fan-group@0 {
 156                                 #cooling-cells = <2>;
 157                                 reg = <0x00>;
 158                                 cooling-levels = <80 102 170 230 255>;
 159                         };
 160                 };
 161         };
 162 };
 163
 164 &ap_thermal_ic {
 165         PUZZLE_FAN_THERMAL(ic, &chassis_fan_group0);
 166 };
 167
 168 &cp0_thermal_ic {
 169         PUZZLE_FAN_THERMAL(cp0, &chassis_fan_group0);
 170 };
 171
 172
 173 /* on-board eMMC - U9 */
 174 &ap_sdhci0 {
 175         pinctrl-names = "default";
 176         bus-width = <8>;
 177         status = "okay";
 178         mmc-ddr-1_8v;
 179         mmc-hs400-1_8v;
 180 };
 181
 182 &cp0_crypto {
 183         status = "okay";
 184 };
 185
 186 &cp0_xmdio {
 187         status = "okay";
 188         cp0_nbaset_phy0: ethernet-phy@0 {
 189                 compatible = "ethernet-phy-ieee802.3-c45";
 190                 reg = <2>;
 191         };
 192         cp0_nbaset_phy1: ethernet-phy@1 {
 193                 compatible = "ethernet-phy-ieee802.3-c45";
 194                 reg = <0>;
 195         };
 196         cp0_nbaset_phy2: ethernet-phy@2 {
 197                 compatible = "ethernet-phy-ieee802.3-c45";
 198                 reg = <8>;
 199         };
 200 };
 201
 202 &cp0_ethernet {
 203         status = "okay";
 204 };
 205
 206 /* SLM-1521-V2, CON9 */
 207 &cp0_eth0 {
 208         status = "okay";
 209         phy-mode = "10gbase-kr";
 210         phys = <&cp0_comphy2 0>;
 211         phy = <&cp0_nbaset_phy0>;
 212 };
 213
 214 &cp0_eth1 {
 215         status = "okay";
 216         phy-mode = "2500base-x";
 217         phys = <&cp0_comphy4 1>;
 218         phy = <&cp0_nbaset_phy1>;
 219 };
 220
 221 &cp0_eth2 {
 222         status = "okay";
 223         phy-mode = "2500base-x";
 224         phys = <&cp0_comphy1 2>;
 225         phy = <&cp0_nbaset_phy2>;
 226 };
 227
 228 &cp0_gpio1 {
 229         status = "okay";
 230 };
 231
 232 &cp0_gpio2 {
 233         status = "okay";
 234 };
 235
 236 &cp0_i2c0 {
 237         pinctrl-names = "default";
 238         pinctrl-0 = <&cp0_i2c0_pins>;
 239         status = "okay";
 240         clock-frequency = <100000>;
 241         rtc@32 {
 242                 compatible = "epson,rx8130";
 243                 reg = <0x32>;
 244                 wakeup-source;
 245         };
 246 };
 247
 248 &cp0_i2c1 {
 249         clock-frequency = <100000>;
 250 };
 251
 252 /* SLM-1521-V2, CON6 */
 253 &cp0_sata0 {
 254         status = "okay";
 255         sata-port@1 {
 256                 status = "okay";
 257                 phys = <&cp0_comphy0 1>;
 258         };
 259 };
 260
 261 &cp0_pcie2 {
 262         status = "okay";
 263         num-lanes = <1>;
 264         num-viewport = <8>;
 265         phys = <&cp0_comphy5 2>;
 266 };
 267
 268 /* U55 */
 269 &cp0_spi1 {
 270         pinctrl-names = "default";
 271         pinctrl-0 = <&cp0_spi0_pins>;
 272         reg = <0x700680 0x50>,          /* control */
 273               <0x2000000 0x1000000>;    /* CS0 */
 274         status = "okay";
 275         spi-flash@0 {
 276                 #address-cells = <0x1>;
 277                 #size-cells = <0x1>;
 278                 compatible = "jedec,spi-nor";
 279                 reg = <0x0>;
 280                 spi-max-frequency = <40000000>;
 281                 partitions {
 282                         compatible = "fixed-partitions";
 283                         #address-cells = <1>;
 284                         #size-cells = <1>;
 285                         partition@0 {
 286                                 label = "U-Boot";
 287                                 reg = <0x0 0x1f0000>;
 288                         };
 289                         partition@1f0000 {
 290                                 label = "U-Boot ENV Factory";
 291                                 reg = <0x1f0000 0x10000>;
 292                         };
 293                         partition@200000 {
 294                                 label = "Reserved";
 295                                 reg = <0x200000 0x1f0000>;
 296                         };
 297                         partition@3f0000 {
 298                                 label = "U-Boot ENV";
 299                                 reg = <0x3f0000 0x10000>;
 300                         };
 301                 };
 302         };
 303 };
 304
 305 &cp0_syscon0 {
 306         cp0_pinctrl: pinctrl {
 307                 compatible = "marvell,cp115-standalone-pinctrl";
 308                 cp0_i2c0_pins: cp0-i2c-pins-0 {
 309                         marvell,pins = "mpp37", "mpp38";
 310                         marvell,function = "i2c0";
 311                 };
 312                 cp0_i2c1_pins: cp0-i2c-pins-1 {
 313                         marvell,pins = "mpp35", "mpp36";
 314                         marvell,function = "i2c1";
 315                 };
 316                 cp0_ge1_rgmii_pins: cp0-ge-rgmii-pins-0 {
 317                         marvell,pins = "mpp0", "mpp1", "mpp2",
 318                                        "mpp3", "mpp4", "mpp5",
 319                                        "mpp6", "mpp7", "mpp8",
 320                                        "mpp9", "mpp10", "mpp11";
 321                         marvell,function = "ge0";
 322                 };
 323                 cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-1 {
 324                         marvell,pins = "mpp44", "mpp45", "mpp46",
 325                                        "mpp47", "mpp48", "mpp49",
 326                                        "mpp50", "mpp51", "mpp52",
 327                                        "mpp53", "mpp54", "mpp55";
 328                         marvell,function = "ge1";
 329                 };
 330                 cp0_spi0_pins: cp0-spi-pins-0 {
 331                         marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
 332                         marvell,function = "spi1";
 333                 };
 334         };
 335 };
 336
 337 &cp0_usb3_1 {
 338         status = "okay";
 339         phys = <&cp0_comphy3 1>;
 340         phy-names = "usb";
 341 };
 342
 343 /*
 344  * Instantiate the first connected CP115
 345  */
 346
 347 #define CP11X_NAME              cp1
 348 #define CP11X_BASE              f4000000
 349 #define CP11X_PCIEx_MEM_BASE(iface) (0xe2000000 + (iface * 0x1000000))
 350 #define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
 351 #define CP11X_PCIE0_BASE        f4600000
 352 #define CP11X_PCIE1_BASE        f4620000
 353 #define CP11X_PCIE2_BASE        f4640000
 354
 355 #include "armada-cp115.dtsi"
 356
 357 #undef CP11X_NAME
 358 #undef CP11X_BASE
 359 #undef CP11X_PCIEx_MEM_BASE
 360 #undef CP11X_PCIEx_MEM_SIZE
 361 #undef CP11X_PCIE0_BASE
 362 #undef CP11X_PCIE1_BASE
 363 #undef CP11X_PCIE2_BASE
 364
 365 &cp1_crypto {
 366         status = "okay";
 367 };
 368
 369 &cp1_xmdio {
 370         status = "okay";
 371         cp1_nbaset_phy0: ethernet-phy@3 {
 372                 compatible = "ethernet-phy-ieee802.3-c45";
 373                 reg = <2>;
 374         };
 375         cp1_nbaset_phy1: ethernet-phy@4 {
 376                 compatible = "ethernet-phy-ieee802.3-c45";
 377                 reg = <0>;
 378         };
 379         cp1_nbaset_phy2: ethernet-phy@5 {
 380                 compatible = "ethernet-phy-ieee802.3-c45";
 381                 reg = <8>;
 382         };
 383 };
 384
 385 &cp1_ethernet {
 386         status = "okay";
 387 };
 388
 389 /* CON50 */
 390 &cp1_eth0 {
 391         status = "okay";
 392         phy-mode = "10gbase-kr";
 393         phys = <&cp1_comphy2 0>;
 394         phy = <&cp1_nbaset_phy0>;
 395 };
 396
 397 &cp1_eth1 {
 398         status = "okay";
 399         phy-mode = "2500base-x";
 400         phys = <&cp1_comphy4 1>;
 401         phy = <&cp1_nbaset_phy1>;
 402 };
 403
 404 &cp1_eth2 {
 405         status = "okay";
 406         phy-mode = "2500base-x";
 407         phys = <&cp1_comphy1 2>;
 408         phy = <&cp1_nbaset_phy2>;
 409 };
 410
 411 &cp1_gpio1 {
 412         status = "okay";
 413 };
 414
 415 &cp1_gpio2 {
 416         status = "okay";
 417 };
 418
 419 &cp1_i2c0 {
 420         status = "okay";
 421         pinctrl-names = "default";
 422         pinctrl-0 = <&cp1_i2c0_pins>;
 423         clock-frequency = <100000>;
 424 };
 425
 426 &cp1_syscon0 {
 427         cp1_pinctrl: pinctrl {
 428                 compatible = "marvell,cp115-standalone-pinctrl";
 429                 cp1_i2c0_pins: cp1-i2c-pins-0 {
 430                         marvell,pins = "mpp37", "mpp38";
 431                         marvell,function = "i2c0";
 432                 };
 433                 cp1_spi0_pins: cp1-spi-pins-0 {
 434                         marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
 435                         marvell,function = "spi1";
 436                 };
 437                 cp1_xhci0_vbus_pins: cp1-xhci0-vbus-pins {
 438                         marvell,pins = "mpp3";
 439                         marvell,function = "gpio";
 440                 };
 441         };
 442 };
 443
 444 &cp1_thermal_ic {
 445         PUZZLE_FAN_THERMAL(cp1, &chassis_fan_group0);
 446 };
 447
 448 /*
 449  * Instantiate the second connected CP115
 450  */
 451
 452 #define CP11X_NAME              cp2
 453 #define CP11X_BASE              f6000000
 454 #define CP11X_PCIEx_MEM_BASE(iface) (0xe5000000 + (iface * 0x1000000))
 455 #define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
 456 #define CP11X_PCIE0_BASE        f6600000
 457 #define CP11X_PCIE1_BASE        f6620000
 458 #define CP11X_PCIE2_BASE        f6640000
 459
 460 #include "armada-cp115.dtsi"
 461
 462 #undef CP11X_NAME
 463 #undef CP11X_BASE
 464 #undef CP11X_PCIEx_MEM_BASE
 465 #undef CP11X_PCIEx_MEM_SIZE
 466 #undef CP11X_PCIE0_BASE
 467 #undef CP11X_PCIE1_BASE
 468 #undef CP11X_PCIE2_BASE
 469
 470 &cp2_crypto {
 471         status = "okay";
 472 };
 473
 474 &cp2_ethernet {
 475         status = "okay";
 476 };
 477
 478 &cp2_xmdio {
 479         status = "okay";
 480         cp2_nbaset_phy0: ethernet-phy@6 {
 481                 compatible = "ethernet-phy-ieee802.3-c45";
 482                 reg = <2>;
 483         };
 484         cp2_nbaset_phy1: ethernet-phy@7 {
 485                 compatible = "ethernet-phy-ieee802.3-c45";
 486                 reg = <0>;
 487         };
 488         cp2_nbaset_phy2: ethernet-phy@8 {
 489                 compatible = "ethernet-phy-ieee802.3-c45";
 490                 reg = <8>;
 491         };
 492 };
 493
 494 /* SLM-1521-V2, CON9 */
 495 &cp2_eth0 {
 496         status = "okay";
 497         phy-mode = "10gbase-kr";
 498         phys = <&cp2_comphy2 0>;
 499         phy = <&cp2_nbaset_phy0>;
 500 };
 501
 502 &cp2_eth1 {
 503         status = "okay";
 504         phy-mode = "2500base-x";
 505         phys = <&cp2_comphy4 1>;
 506         phy = <&cp2_nbaset_phy1>;
 507 };
 508
 509 &cp2_eth2 {
 510         status = "okay";
 511         phy-mode = "2500base-x";
 512         phys = <&cp2_comphy1 2>;
 513         phy = <&cp2_nbaset_phy2>;
 514 };
 515
 516 &cp2_gpio1 {
 517         status = "okay";
 518 };
 519
 520 &cp2_gpio2 {
 521         status = "okay";
 522 };
 523
 524 &cp2_i2c0 {
 525         clock-frequency = <100000>;
 526         /* SLM-1521-V2 - U3 */
 527         i2c-mux@72 {
 528                 compatible = "nxp,pca9544";
 529                 #address-cells = <1>;
 530                 #size-cells = <0>;
 531                 reg = <0x72>;
 532                 cp2_sfpp0_i2c: i2c@0 {
 533                         #address-cells = <1>;
 534                         #size-cells = <0>;
 535                         reg = <0>;
 536                 };
 537
 538                 i2c@1 {
 539                         #address-cells = <1>;
 540                         #size-cells = <0>;
 541                         reg = <1>;
 542                         /* U12 */
 543                         cp2_module_expander1: pca9555@21 {
 544                                 compatible = "nxp,pca9555";
 545                                 pinctrl-names = "default";
 546                                 gpio-controller;
 547                                 #gpio-cells = <2>;
 548                                 reg = <0x21>;
 549                         };
 550                 };
 551         };
 552 };
 553
 554 &cp2_syscon0 {
 555         cp2_pinctrl: pinctrl {
 556                 compatible = "marvell,cp115-standalone-pinctrl";
 557                 cp2_i2c0_pins: cp2-i2c-pins-0 {
 558                         marvell,pins = "mpp37", "mpp38";
 559                         marvell,function = "i2c0";
 560                 };
 561         };
 562 };
 563
 564 &cp2_thermal_ic {
 565         PUZZLE_FAN_THERMAL(cp2, &chassis_fan_group0);
 566 };