1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
3 * Copyright (C) 2019 Marvell International Ltd.
5 * Device tree for the CN9132-DB board.
10 #include <dt-bindings/gpio/gpio.h>
13 model = "iEi Puzzle-M902";
14 compatible = "iei,puzzle-m902",
15 "marvell,armada-ap807-quad", "marvell,armada-ap807";
18 stdout-path = "serial0:115200n8";
30 ethernet0 = &cp0_eth0;
31 ethernet1 = &cp0_eth1;
32 ethernet2 = &cp0_eth2;
33 ethernet3 = &cp1_eth0;
34 ethernet4 = &cp1_eth1;
35 ethernet5 = &cp1_eth2;
36 ethernet6 = &cp2_eth0;
37 ethernet7 = &cp2_eth1;
38 ethernet8 = &cp2_eth2;
45 device_type = "memory";
46 reg = <0x0 0x0 0x0 0x80000000>;
49 cp2_reg_usb3_vbus0: cp2_usb3_vbus@0 {
50 compatible = "regulator-fixed";
51 regulator-name = "cp2-xhci0-vbus";
52 regulator-min-microvolt = <5000000>;
53 regulator-max-microvolt = <5000000>;
55 gpio = <&cp2_gpio1 2 GPIO_ACTIVE_HIGH>;
58 cp2_usb3_0_phy0: cp2_usb3_phy0 {
59 compatible = "usb-nop-xceiv";
60 vcc-supply = <&cp2_reg_usb3_vbus0>;
63 cp2_reg_usb3_vbus1: cp2_usb3_vbus@1 {
64 compatible = "regulator-fixed";
65 regulator-name = "cp2-xhci1-vbus";
66 regulator-min-microvolt = <5000000>;
67 regulator-max-microvolt = <5000000>;
69 gpio = <&cp2_gpio1 3 GPIO_ACTIVE_HIGH>;
72 cp2_usb3_0_phy1: cp2_usb3_phy1 {
73 compatible = "usb-nop-xceiv";
74 vcc-supply = <&cp2_reg_usb3_vbus1>;
77 cp2_sfp_eth0: sfp-eth0 {
78 compatible = "sff,sfp";
79 i2c-bus = <&cp2_sfpp0_i2c>;
80 los-gpio = <&cp2_module_expander1 11 GPIO_ACTIVE_HIGH>;
81 mod-def0-gpio = <&cp2_module_expander1 10 GPIO_ACTIVE_LOW>;
82 tx-disable-gpio = <&cp2_module_expander1 9 GPIO_ACTIVE_HIGH>;
83 tx-fault-gpio = <&cp2_module_expander1 8 GPIO_ACTIVE_HIGH>;
96 /* on-board eMMC - U9 */
98 pinctrl-names = "default";
111 cp0_nbaset_phy0: ethernet-phy@0 {
112 compatible = "ethernet-phy-ieee802.3-c45";
115 cp0_nbaset_phy1: ethernet-phy@1 {
116 compatible = "ethernet-phy-ieee802.3-c45";
119 cp0_nbaset_phy2: ethernet-phy@2 {
120 compatible = "ethernet-phy-ieee802.3-c45";
129 /* SLM-1521-V2, CON9 */
132 phy-mode = "10gbase-kr";
133 phys = <&cp0_comphy2 0>;
134 managed = "in-band-status";
139 phy-mode = "2500base-x";
140 phys = <&cp0_comphy4 1>;
141 managed = "in-band-status";
146 phy-mode = "2500base-x";
147 phys = <&cp0_comphy1 2>;
148 managed = "in-band-status";
160 pinctrl-names = "default";
161 pinctrl-0 = <&cp0_i2c0_pins>;
163 clock-frequency = <100000>;
165 compatible = "epson,rx8130";
172 clock-frequency = <100000>;
175 /* SLM-1521-V2, CON6 */
180 phys = <&cp0_comphy0 1>;
188 phys = <&cp0_comphy5 2>;
193 pinctrl-names = "default";
194 pinctrl-0 = <&cp0_spi0_pins>;
195 reg = <0x700680 0x50>, /* control */
196 <0x2000000 0x1000000>; /* CS0 */
199 #address-cells = <0x1>;
201 compatible = "jedec,spi-nor";
203 spi-max-frequency = <40000000>;
205 compatible = "fixed-partitions";
206 #address-cells = <1>;
210 reg = <0x0 0x1f0000>;
213 label = "U-Boot ENV Factory";
214 reg = <0x1f0000 0x10000>;
218 reg = <0x200000 0x1f0000>;
221 label = "U-Boot ENV";
222 reg = <0x3f0000 0x10000>;
229 cp0_pinctrl: pinctrl {
230 compatible = "marvell,cp115-standalone-pinctrl";
231 cp0_i2c0_pins: cp0-i2c-pins-0 {
232 marvell,pins = "mpp37", "mpp38";
233 marvell,function = "i2c0";
235 cp0_i2c1_pins: cp0-i2c-pins-1 {
236 marvell,pins = "mpp35", "mpp36";
237 marvell,function = "i2c1";
239 cp0_ge1_rgmii_pins: cp0-ge-rgmii-pins-0 {
240 marvell,pins = "mpp0", "mpp1", "mpp2",
241 "mpp3", "mpp4", "mpp5",
242 "mpp6", "mpp7", "mpp8",
243 "mpp9", "mpp10", "mpp11";
244 marvell,function = "ge0";
246 cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-1 {
247 marvell,pins = "mpp44", "mpp45", "mpp46",
248 "mpp47", "mpp48", "mpp49",
249 "mpp50", "mpp51", "mpp52",
250 "mpp53", "mpp54", "mpp55";
251 marvell,function = "ge1";
253 cp0_spi0_pins: cp0-spi-pins-0 {
254 marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
255 marvell,function = "spi1";
262 phys = <&cp0_comphy3 1>;
267 * Instantiate the first connected CP115
270 #define CP11X_NAME cp1
271 #define CP11X_BASE f4000000
272 #define CP11X_PCIEx_MEM_BASE(iface) (0xe2000000 + (iface * 0x1000000))
273 #define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
274 #define CP11X_PCIE0_BASE f4600000
275 #define CP11X_PCIE1_BASE f4620000
276 #define CP11X_PCIE2_BASE f4640000
278 #include "armada-cp115.dtsi"
282 #undef CP11X_PCIEx_MEM_BASE
283 #undef CP11X_PCIEx_MEM_SIZE
284 #undef CP11X_PCIE0_BASE
285 #undef CP11X_PCIE1_BASE
286 #undef CP11X_PCIE2_BASE
294 cp1_nbaset_phy0: ethernet-phy@3 {
295 compatible = "ethernet-phy-ieee802.3-c45";
298 cp1_nbaset_phy1: ethernet-phy@4 {
299 compatible = "ethernet-phy-ieee802.3-c45";
302 cp1_nbaset_phy2: ethernet-phy@5 {
303 compatible = "ethernet-phy-ieee802.3-c45";
315 phy-mode = "10gbase-kr";
316 phys = <&cp1_comphy2 0>;
317 managed = "in-band-status";
322 phy-mode = "2500base-x";
323 phys = <&cp1_comphy4 1>;
324 managed = "in-band-status";
329 phy-mode = "2500base-x";
330 phys = <&cp1_comphy1 2>;
331 managed = "in-band-status";
344 pinctrl-names = "default";
345 pinctrl-0 = <&cp1_i2c0_pins>;
346 clock-frequency = <100000>;
350 cp1_pinctrl: pinctrl {
351 compatible = "marvell,cp115-standalone-pinctrl";
352 cp1_i2c0_pins: cp1-i2c-pins-0 {
353 marvell,pins = "mpp37", "mpp38";
354 marvell,function = "i2c0";
356 cp1_spi0_pins: cp1-spi-pins-0 {
357 marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
358 marvell,function = "spi1";
360 cp1_xhci0_vbus_pins: cp1-xhci0-vbus-pins {
361 marvell,pins = "mpp3";
362 marvell,function = "gpio";
368 * Instantiate the second connected CP115
371 #define CP11X_NAME cp2
372 #define CP11X_BASE f6000000
373 #define CP11X_PCIEx_MEM_BASE(iface) (0xe5000000 + (iface * 0x1000000))
374 #define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
375 #define CP11X_PCIE0_BASE f6600000
376 #define CP11X_PCIE1_BASE f6620000
377 #define CP11X_PCIE2_BASE f6640000
379 #include "armada-cp115.dtsi"
383 #undef CP11X_PCIEx_MEM_BASE
384 #undef CP11X_PCIEx_MEM_SIZE
385 #undef CP11X_PCIE0_BASE
386 #undef CP11X_PCIE1_BASE
387 #undef CP11X_PCIE2_BASE
399 cp2_nbaset_phy0: ethernet-phy@6 {
400 compatible = "ethernet-phy-ieee802.3-c45";
403 cp2_nbaset_phy1: ethernet-phy@7 {
404 compatible = "ethernet-phy-ieee802.3-c45";
407 cp2_nbaset_phy2: ethernet-phy@8 {
408 compatible = "ethernet-phy-ieee802.3-c45";
413 /* SLM-1521-V2, CON9 */
416 phy-mode = "10gbase-kr";
417 phys = <&cp2_comphy2 0>;
418 managed = "in-band-status";
423 phy-mode = "2500base-x";
424 phys = <&cp2_comphy4 1>;
425 managed = "in-band-status";
430 phy-mode = "2500base-x";
431 phys = <&cp2_comphy1 2>;
432 managed = "in-band-status";
444 clock-frequency = <100000>;
445 /* SLM-1521-V2 - U3 */
447 compatible = "nxp,pca9544";
448 #address-cells = <1>;
451 cp2_sfpp0_i2c: i2c@0 {
452 #address-cells = <1>;
458 #address-cells = <1>;
462 cp2_module_expander1: pca9555@21 {
463 compatible = "nxp,pca9555";
464 pinctrl-names = "default";
474 cp2_pinctrl: pinctrl {
475 compatible = "marvell,cp115-standalone-pinctrl";
476 cp2_i2c0_pins: cp2-i2c-pins-0 {
477 marvell,pins = "mpp37", "mpp38";
478 marvell,function = "i2c0";