target/linux/mvebu/files/arch/arm64/boot/dts/marvell/cn9132-puzzle-m902.dts

   1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
   2 /*
   3  * Copyright (C) 2019 Marvell International Ltd.
   4  *
   5  * Device tree for the CN9132-DB board.
   6  */
   7
   8 #include "cn9130.dtsi"
   9
  10 #include <dt-bindings/gpio/gpio.h>
  11
  12 / {
  13         model = "iEi Puzzle-M902";
  14         compatible = "iei,puzzle-m902",
  15                      "marvell,armada-ap807-quad", "marvell,armada-ap807";
  16
  17         chosen {
  18                 stdout-path = "serial0:115200n8";
  19         };
  20
  21         aliases {
  22                 i2c0 = &cp1_i2c0;
  23                 i2c1 = &cp0_i2c0;
  24                 gpio1 = &cp0_gpio1;
  25                 gpio2 = &cp0_gpio2;
  26                 gpio3 = &cp1_gpio1;
  27                 gpio4 = &cp1_gpio2;
  28                 gpio5 = &cp2_gpio1;
  29                 gpio6 = &cp2_gpio2;
  30                 ethernet0 = &cp0_eth0;
  31                 ethernet1 = &cp0_eth1;
  32                 ethernet2 = &cp0_eth2;
  33                 ethernet3 = &cp1_eth0;
  34                 ethernet4 = &cp1_eth1;
  35                 ethernet5 = &cp1_eth2;
  36                 ethernet6 = &cp2_eth0;
  37                 ethernet7 = &cp2_eth1;
  38                 ethernet8 = &cp2_eth2;
  39                 spi1 = &cp0_spi0;
  40                 spi2 = &cp0_spi1;
  41                 serial1 = &cp0_uart0;
  42         };
  43
  44         memory@00000000 {
  45                 device_type = "memory";
  46                 reg = <0x0 0x0 0x0 0x80000000>;
  47         };
  48
  49         cp2_reg_usb3_vbus0: cp2_usb3_vbus@0 {
  50                 compatible = "regulator-fixed";
  51                 regulator-name = "cp2-xhci0-vbus";
  52                 regulator-min-microvolt = <5000000>;
  53                 regulator-max-microvolt = <5000000>;
  54                 enable-active-high;
  55                 gpio = <&cp2_gpio1 2 GPIO_ACTIVE_HIGH>;
  56         };
  57
  58         cp2_usb3_0_phy0: cp2_usb3_phy0 {
  59                 compatible = "usb-nop-xceiv";
  60                 vcc-supply = <&cp2_reg_usb3_vbus0>;
  61         };
  62
  63         cp2_reg_usb3_vbus1: cp2_usb3_vbus@1 {
  64                 compatible = "regulator-fixed";
  65                 regulator-name = "cp2-xhci1-vbus";
  66                 regulator-min-microvolt = <5000000>;
  67                 regulator-max-microvolt = <5000000>;
  68                 enable-active-high;
  69                 gpio = <&cp2_gpio1 3 GPIO_ACTIVE_HIGH>;
  70         };
  71
  72         cp2_usb3_0_phy1: cp2_usb3_phy1 {
  73                 compatible = "usb-nop-xceiv";
  74                 vcc-supply = <&cp2_reg_usb3_vbus1>;
  75         };
  76
  77         cp2_sfp_eth0: sfp-eth0 {
  78                 compatible = "sff,sfp";
  79                 i2c-bus = <&cp2_sfpp0_i2c>;
  80                 los-gpio = <&cp2_module_expander1 11 GPIO_ACTIVE_HIGH>;
  81                 mod-def0-gpio = <&cp2_module_expander1 10 GPIO_ACTIVE_LOW>;
  82                 tx-disable-gpio = <&cp2_module_expander1 9 GPIO_ACTIVE_HIGH>;
  83                 tx-fault-gpio = <&cp2_module_expander1 8 GPIO_ACTIVE_HIGH>;
  84                 status = "disabled";
  85         };
  86 };
  87
  88 &uart0 {
  89         status = "okay";
  90 };
  91
  92 &cp0_uart0 {
  93         status = "okay";
  94 };
  95
  96 /* on-board eMMC - U9 */
  97 &ap_sdhci0 {
  98         pinctrl-names = "default";
  99         bus-width = <8>;
 100         status = "okay";
 101         mmc-ddr-1_8v;
 102         mmc-hs400-1_8v;
 103 };
 104
 105 &cp0_crypto {
 106         status = "okay";
 107 };
 108
 109 &cp0_xmdio {
 110         status = "okay";
 111         cp0_nbaset_phy0: ethernet-phy@0 {
 112                 compatible = "ethernet-phy-ieee802.3-c45";
 113                 reg = <2>;
 114         };
 115         cp0_nbaset_phy1: ethernet-phy@1 {
 116                 compatible = "ethernet-phy-ieee802.3-c45";
 117                 reg = <0>;
 118         };
 119         cp0_nbaset_phy2: ethernet-phy@2 {
 120                 compatible = "ethernet-phy-ieee802.3-c45";
 121                 reg = <8>;
 122         };
 123 };
 124
 125 &cp0_ethernet {
 126         status = "okay";
 127 };
 128
 129 /* SLM-1521-V2, CON9 */
 130 &cp0_eth0 {
 131         status = "okay";
 132         phy-mode = "10gbase-kr";
 133         phys = <&cp0_comphy2 0>;
 134         managed = "in-band-status";
 135 };
 136
 137 &cp0_eth1 {
 138         status = "okay";
 139         phy-mode = "2500base-x";
 140         phys = <&cp0_comphy4 1>;
 141         managed = "in-band-status";
 142 };
 143
 144 &cp0_eth2 {
 145         status = "okay";
 146         phy-mode = "2500base-x";
 147         phys = <&cp0_comphy1 2>;
 148         managed = "in-band-status";
 149 };
 150
 151 &cp0_gpio1 {
 152         status = "okay";
 153 };
 154
 155 &cp0_gpio2 {
 156         status = "okay";
 157 };
 158
 159 &cp0_i2c0 {
 160         pinctrl-names = "default";
 161         pinctrl-0 = <&cp0_i2c0_pins>;
 162         status = "okay";
 163         clock-frequency = <100000>;
 164         rtc@32 {
 165                 compatible = "epson,rx8130";
 166                 reg = <0x32>;
 167                 wakeup-source;
 168         };
 169 };
 170
 171 &cp0_i2c1 {
 172         clock-frequency = <100000>;
 173 };
 174
 175 /* SLM-1521-V2, CON6 */
 176 &cp0_sata0 {
 177         status = "okay";
 178         sata-port@1 {
 179                 status = "okay";
 180                 phys = <&cp0_comphy0 1>;
 181         };
 182 };
 183
 184 &cp0_pcie2 {
 185         status = "okay";
 186         num-lanes = <1>;
 187         num-viewport = <8>;
 188         phys = <&cp0_comphy5 2>;
 189 };
 190
 191 /* U55 */
 192 &cp0_spi1 {
 193         pinctrl-names = "default";
 194         pinctrl-0 = <&cp0_spi0_pins>;
 195         reg = <0x700680 0x50>,          /* control */
 196               <0x2000000 0x1000000>;    /* CS0 */
 197         status = "okay";
 198         spi-flash@0 {
 199                 #address-cells = <0x1>;
 200                 #size-cells = <0x1>;
 201                 compatible = "jedec,spi-nor";
 202                 reg = <0x0>;
 203                 spi-max-frequency = <40000000>;
 204                 partitions {
 205                         compatible = "fixed-partitions";
 206                         #address-cells = <1>;
 207                         #size-cells = <1>;
 208                         partition@0 {
 209                                 label = "U-Boot";
 210                                 reg = <0x0 0x1f0000>;
 211                         };
 212                         partition@1f0000 {
 213                                 label = "U-Boot ENV Factory";
 214                                 reg = <0x1f0000 0x10000>;
 215                         };
 216                         partition@200000 {
 217                                 label = "Reserved";
 218                                 reg = <0x200000 0x1f0000>;
 219                         };
 220                         partition@3f0000 {
 221                                 label = "U-Boot ENV";
 222                                 reg = <0x3f0000 0x10000>;
 223                         };
 224                 };
 225         };
 226 };
 227
 228 &cp0_syscon0 {
 229         cp0_pinctrl: pinctrl {
 230                 compatible = "marvell,cp115-standalone-pinctrl";
 231                 cp0_i2c0_pins: cp0-i2c-pins-0 {
 232                         marvell,pins = "mpp37", "mpp38";
 233                         marvell,function = "i2c0";
 234                 };
 235                 cp0_i2c1_pins: cp0-i2c-pins-1 {
 236                         marvell,pins = "mpp35", "mpp36";
 237                         marvell,function = "i2c1";
 238                 };
 239                 cp0_ge1_rgmii_pins: cp0-ge-rgmii-pins-0 {
 240                         marvell,pins = "mpp0", "mpp1", "mpp2",
 241                                        "mpp3", "mpp4", "mpp5",
 242                                        "mpp6", "mpp7", "mpp8",
 243                                        "mpp9", "mpp10", "mpp11";
 244                         marvell,function = "ge0";
 245                 };
 246                 cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-1 {
 247                         marvell,pins = "mpp44", "mpp45", "mpp46",
 248                                        "mpp47", "mpp48", "mpp49",
 249                                        "mpp50", "mpp51", "mpp52",
 250                                        "mpp53", "mpp54", "mpp55";
 251                         marvell,function = "ge1";
 252                 };
 253                 cp0_spi0_pins: cp0-spi-pins-0 {
 254                         marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
 255                         marvell,function = "spi1";
 256                 };
 257         };
 258 };
 259
 260 &cp0_usb3_1 {
 261         status = "okay";
 262         phys = <&cp0_comphy3 1>;
 263         phy-names = "usb";
 264 };
 265
 266 /*
 267  * Instantiate the first connected CP115
 268  */
 269
 270 #define CP11X_NAME              cp1
 271 #define CP11X_BASE              f4000000
 272 #define CP11X_PCIEx_MEM_BASE(iface) (0xe2000000 + (iface * 0x1000000))
 273 #define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
 274 #define CP11X_PCIE0_BASE        f4600000
 275 #define CP11X_PCIE1_BASE        f4620000
 276 #define CP11X_PCIE2_BASE        f4640000
 277
 278 #include "armada-cp115.dtsi"
 279
 280 #undef CP11X_NAME
 281 #undef CP11X_BASE
 282 #undef CP11X_PCIEx_MEM_BASE
 283 #undef CP11X_PCIEx_MEM_SIZE
 284 #undef CP11X_PCIE0_BASE
 285 #undef CP11X_PCIE1_BASE
 286 #undef CP11X_PCIE2_BASE
 287
 288 &cp1_crypto {
 289         status = "okay";
 290 };
 291
 292 &cp1_xmdio {
 293         status = "okay";
 294         cp1_nbaset_phy0: ethernet-phy@3 {
 295                 compatible = "ethernet-phy-ieee802.3-c45";
 296                 reg = <2>;
 297         };
 298         cp1_nbaset_phy1: ethernet-phy@4 {
 299                 compatible = "ethernet-phy-ieee802.3-c45";
 300                 reg = <0>;
 301         };
 302         cp1_nbaset_phy2: ethernet-phy@5 {
 303                 compatible = "ethernet-phy-ieee802.3-c45";
 304                 reg = <8>;
 305         };
 306 };
 307
 308 &cp1_ethernet {
 309         status = "okay";
 310 };
 311
 312 /* CON50 */
 313 &cp1_eth0 {
 314         status = "okay";
 315         phy-mode = "10gbase-kr";
 316         phys = <&cp1_comphy2 0>;
 317         managed = "in-band-status";
 318 };
 319
 320 &cp1_eth1 {
 321         status = "okay";
 322         phy-mode = "2500base-x";
 323         phys = <&cp1_comphy4 1>;
 324         managed = "in-band-status";
 325 };
 326
 327 &cp1_eth2 {
 328         status = "okay";
 329         phy-mode = "2500base-x";
 330         phys = <&cp1_comphy1 2>;
 331         managed = "in-band-status";
 332 };
 333
 334 &cp1_gpio1 {
 335         status = "okay";
 336 };
 337
 338 &cp1_gpio2 {
 339         status = "okay";
 340 };
 341
 342 &cp1_i2c0 {
 343         status = "okay";
 344         pinctrl-names = "default";
 345         pinctrl-0 = <&cp1_i2c0_pins>;
 346         clock-frequency = <100000>;
 347 };
 348
 349 &cp1_syscon0 {
 350         cp1_pinctrl: pinctrl {
 351                 compatible = "marvell,cp115-standalone-pinctrl";
 352                 cp1_i2c0_pins: cp1-i2c-pins-0 {
 353                         marvell,pins = "mpp37", "mpp38";
 354                         marvell,function = "i2c0";
 355                 };
 356                 cp1_spi0_pins: cp1-spi-pins-0 {
 357                         marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
 358                         marvell,function = "spi1";
 359                 };
 360                 cp1_xhci0_vbus_pins: cp1-xhci0-vbus-pins {
 361                         marvell,pins = "mpp3";
 362                         marvell,function = "gpio";
 363                 };
 364         };
 365 };
 366
 367 /*
 368  * Instantiate the second connected CP115
 369  */
 370
 371 #define CP11X_NAME              cp2
 372 #define CP11X_BASE              f6000000
 373 #define CP11X_PCIEx_MEM_BASE(iface) (0xe5000000 + (iface * 0x1000000))
 374 #define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
 375 #define CP11X_PCIE0_BASE        f6600000
 376 #define CP11X_PCIE1_BASE        f6620000
 377 #define CP11X_PCIE2_BASE        f6640000
 378
 379 #include "armada-cp115.dtsi"
 380
 381 #undef CP11X_NAME
 382 #undef CP11X_BASE
 383 #undef CP11X_PCIEx_MEM_BASE
 384 #undef CP11X_PCIEx_MEM_SIZE
 385 #undef CP11X_PCIE0_BASE
 386 #undef CP11X_PCIE1_BASE
 387 #undef CP11X_PCIE2_BASE
 388
 389 &cp2_crypto {
 390         status = "okay";
 391 };
 392
 393 &cp2_ethernet {
 394         status = "okay";
 395 };
 396
 397 &cp2_xmdio {
 398         status = "okay";
 399         cp2_nbaset_phy0: ethernet-phy@6 {
 400                 compatible = "ethernet-phy-ieee802.3-c45";
 401                 reg = <2>;
 402         };
 403         cp2_nbaset_phy1: ethernet-phy@7 {
 404                 compatible = "ethernet-phy-ieee802.3-c45";
 405                 reg = <0>;
 406         };
 407         cp2_nbaset_phy2: ethernet-phy@8 {
 408                 compatible = "ethernet-phy-ieee802.3-c45";
 409                 reg = <8>;
 410         };
 411 };
 412
 413 /* SLM-1521-V2, CON9 */
 414 &cp2_eth0 {
 415         status = "okay";
 416         phy-mode = "10gbase-kr";
 417         phys = <&cp2_comphy2 0>;
 418         managed = "in-band-status";
 419 };
 420
 421 &cp2_eth1 {
 422         status = "okay";
 423         phy-mode = "2500base-x";
 424         phys = <&cp2_comphy4 1>;
 425         managed = "in-band-status";
 426 };
 427
 428 &cp2_eth2 {
 429         status = "okay";
 430         phy-mode = "2500base-x";
 431         phys = <&cp2_comphy1 2>;
 432         managed = "in-band-status";
 433 };
 434
 435 &cp2_gpio1 {
 436         status = "okay";
 437 };
 438
 439 &cp2_gpio2 {
 440         status = "okay";
 441 };
 442
 443 &cp2_i2c0 {
 444         clock-frequency = <100000>;
 445         /* SLM-1521-V2 - U3 */
 446         i2c-mux@72 {
 447                 compatible = "nxp,pca9544";
 448                 #address-cells = <1>;
 449                 #size-cells = <0>;
 450                 reg = <0x72>;
 451                 cp2_sfpp0_i2c: i2c@0 {
 452                         #address-cells = <1>;
 453                         #size-cells = <0>;
 454                         reg = <0>;
 455                 };
 456
 457                 i2c@1 {
 458                         #address-cells = <1>;
 459                         #size-cells = <0>;
 460                         reg = <1>;
 461                         /* U12 */
 462                         cp2_module_expander1: pca9555@21 {
 463                                 compatible = "nxp,pca9555";
 464                                 pinctrl-names = "default";
 465                                 gpio-controller;
 466                                 #gpio-cells = <2>;
 467                                 reg = <0x21>;
 468                         };
 469                 };
 470         };
 471 };
 472
 473 &cp2_syscon0 {
 474         cp2_pinctrl: pinctrl {
 475                 compatible = "marvell,cp115-standalone-pinctrl";
 476                 cp2_i2c0_pins: cp2-i2c-pins-0 {
 477                         marvell,pins = "mpp37", "mpp38";
 478                         marvell,function = "i2c0";
 479                 };
 480         };
 481 };