target/linux/mvebu/files/arch/arm64/boot/dts/marvell/cn9132-puzzle-m902.dts

   1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
   2 /*
   3  * Copyright (C) 2019 Marvell International Ltd.
   4  *
   5  * Device tree for the CN9132-DB board.
   6  */
   7
   8 #include "cn9130.dtsi"
   9
  10 #include <dt-bindings/gpio/gpio.h>
  11 #include <dt-bindings/input/input.h>
  12
  13 / {
  14         model = "iEi Puzzle-M902";
  15         compatible = "iei,puzzle-m902",
  16                      "marvell,armada-ap807-quad", "marvell,armada-ap807";
  17
  18         chosen {
  19                 stdout-path = "serial0:115200n8";
  20         };
  21
  22         aliases {
  23                 i2c0 = &cp1_i2c0;
  24                 i2c1 = &cp0_i2c0;
  25                 gpio1 = &cp0_gpio1;
  26                 gpio2 = &cp0_gpio2;
  27                 gpio3 = &cp1_gpio1;
  28                 gpio4 = &cp1_gpio2;
  29                 gpio5 = &cp2_gpio1;
  30                 gpio6 = &cp2_gpio2;
  31                 ethernet0 = &cp0_eth0;
  32                 ethernet1 = &cp0_eth1;
  33                 ethernet2 = &cp0_eth2;
  34                 ethernet3 = &cp1_eth0;
  35                 ethernet4 = &cp1_eth1;
  36                 ethernet5 = &cp1_eth2;
  37                 ethernet6 = &cp2_eth0;
  38                 ethernet7 = &cp2_eth1;
  39                 ethernet8 = &cp2_eth2;
  40                 spi1 = &cp0_spi0;
  41                 spi2 = &cp0_spi1;
  42                 led-boot = &led_power;
  43                 led-failsafe = &led_info;
  44                 led-running = &led_power;
  45                 led-upgrade = &led_info;
  46         };
  47
  48         memory@00000000 {
  49                 device_type = "memory";
  50                 reg = <0x0 0x0 0x0 0x80000000>;
  51         };
  52
  53         gpio_keys {
  54                 compatible = "gpio-keys";
  55
  56                 reset {
  57                         label = "Reset";
  58                         linux,code = <KEY_RESTART>;
  59                         gpios = <&cp0_gpio2 4 GPIO_ACTIVE_LOW>;
  60                 };
  61         };
  62
  63         cp2_reg_usb3_vbus0: cp2_usb3_vbus@0 {
  64                 compatible = "regulator-fixed";
  65                 regulator-name = "cp2-xhci0-vbus";
  66                 regulator-min-microvolt = <5000000>;
  67                 regulator-max-microvolt = <5000000>;
  68                 enable-active-high;
  69                 gpio = <&cp2_gpio1 2 GPIO_ACTIVE_HIGH>;
  70         };
  71
  72         cp2_usb3_0_phy0: cp2_usb3_phy0 {
  73                 compatible = "usb-nop-xceiv";
  74                 vcc-supply = <&cp2_reg_usb3_vbus0>;
  75         };
  76
  77         cp2_reg_usb3_vbus1: cp2_usb3_vbus@1 {
  78                 compatible = "regulator-fixed";
  79                 regulator-name = "cp2-xhci1-vbus";
  80                 regulator-min-microvolt = <5000000>;
  81                 regulator-max-microvolt = <5000000>;
  82                 enable-active-high;
  83                 gpio = <&cp2_gpio1 3 GPIO_ACTIVE_HIGH>;
  84         };
  85
  86         cp2_usb3_0_phy1: cp2_usb3_phy1 {
  87                 compatible = "usb-nop-xceiv";
  88                 vcc-supply = <&cp2_reg_usb3_vbus1>;
  89         };
  90
  91         cp2_sfp_eth0: sfp-eth0 {
  92                 compatible = "sff,sfp";
  93                 i2c-bus = <&cp2_sfpp0_i2c>;
  94                 los-gpio = <&cp2_module_expander1 11 GPIO_ACTIVE_HIGH>;
  95                 mod-def0-gpio = <&cp2_module_expander1 10 GPIO_ACTIVE_LOW>;
  96                 tx-disable-gpio = <&cp2_module_expander1 9 GPIO_ACTIVE_HIGH>;
  97                 tx-fault-gpio = <&cp2_module_expander1 8 GPIO_ACTIVE_HIGH>;
  98                 status = "disabled";
  99         };
 100 };
 101
 102 &uart0 {
 103         status = "okay";
 104 };
 105
 106 &cp0_uart0 {
 107         status = "okay";
 108
 109         puzzle-mcu {
 110                 compatible = "iei,wt61p803-puzzle";
 111                 #address-cells = <1>;
 112                 #size-cells = <1>;
 113                 current-speed = <115200>;
 114                 enable-beep;
 115                 status = "okay";
 116
 117                 leds {
 118                         compatible = "iei,wt61p803-puzzle-leds";
 119                         #address-cells = <1>;
 120                         #size-cells = <0>;
 121                         status = "okay";
 122
 123                         led@0 {
 124                                 reg = <0>;
 125                                 label = "white:network";
 126                                 active-low;
 127                         };
 128
 129                         led@1 {
 130                                 reg = <1>;
 131                                 label = "green:cloud";
 132                                 active-low;
 133                         };
 134
 135                         led_info: led@2 {
 136                                 reg = <2>;
 137                                 label = "orange:info";
 138                                 active-low;
 139                         };
 140
 141                         led_power: led@3 {
 142                                 reg = <3>;
 143                                 label = "yellow:power";
 144                                 active-low;
 145                                 default-state = "on";
 146                         };
 147                 };
 148
 149                 hwmon {
 150                         compatible = "iei,wt61p803-puzzle-hwmon";
 151                         #address-cells = <1>;
 152                         #size-cells = <0>;
 153
 154                         chassis_fan_group0: fan-group@0 {
 155                                 #cooling-cells = <2>;
 156                                 reg = <0x00>;
 157                                 cooling-levels = <64 102 170 230 250>;
 158                         };
 159                 };
 160         };
 161 };
 162
 163 &ap_thermal_cpu1 {
 164         trips {
 165                 cpu_active: cpu-active {
 166                         temperature = <44000>;
 167                         hysteresis = <2000>;
 168                         type = "active";
 169                 };
 170         };
 171         cooling-maps {
 172                 fan-map {
 173                         trip = <&cpu_active>;
 174                         cooling-device = <&chassis_fan_group0 64 THERMAL_NO_LIMIT>;
 175                 };
 176         };
 177 };
 178
 179 /* on-board eMMC - U9 */
 180 &ap_sdhci0 {
 181         pinctrl-names = "default";
 182         bus-width = <8>;
 183         status = "okay";
 184         mmc-ddr-1_8v;
 185         mmc-hs400-1_8v;
 186 };
 187
 188 &cp0_crypto {
 189         status = "okay";
 190 };
 191
 192 &cp0_xmdio {
 193         status = "okay";
 194         cp0_nbaset_phy0: ethernet-phy@0 {
 195                 compatible = "ethernet-phy-ieee802.3-c45";
 196                 reg = <2>;
 197         };
 198         cp0_nbaset_phy1: ethernet-phy@1 {
 199                 compatible = "ethernet-phy-ieee802.3-c45";
 200                 reg = <0>;
 201         };
 202         cp0_nbaset_phy2: ethernet-phy@2 {
 203                 compatible = "ethernet-phy-ieee802.3-c45";
 204                 reg = <8>;
 205         };
 206 };
 207
 208 &cp0_ethernet {
 209         status = "okay";
 210 };
 211
 212 /* SLM-1521-V2, CON9 */
 213 &cp0_eth0 {
 214         status = "okay";
 215         phy-mode = "10gbase-kr";
 216         phys = <&cp0_comphy2 0>;
 217         phy = <&cp0_nbaset_phy0>;
 218 };
 219
 220 &cp0_eth1 {
 221         status = "okay";
 222         phy-mode = "2500base-x";
 223         phys = <&cp0_comphy4 1>;
 224         phy = <&cp0_nbaset_phy1>;
 225 };
 226
 227 &cp0_eth2 {
 228         status = "okay";
 229         phy-mode = "2500base-x";
 230         phys = <&cp0_comphy1 2>;
 231         phy = <&cp0_nbaset_phy2>;
 232 };
 233
 234 &cp0_gpio1 {
 235         status = "okay";
 236 };
 237
 238 &cp0_gpio2 {
 239         status = "okay";
 240 };
 241
 242 &cp0_i2c0 {
 243         pinctrl-names = "default";
 244         pinctrl-0 = <&cp0_i2c0_pins>;
 245         status = "okay";
 246         clock-frequency = <100000>;
 247         rtc@32 {
 248                 compatible = "epson,rx8130";
 249                 reg = <0x32>;
 250                 wakeup-source;
 251         };
 252 };
 253
 254 &cp0_i2c1 {
 255         clock-frequency = <100000>;
 256 };
 257
 258 /* SLM-1521-V2, CON6 */
 259 &cp0_sata0 {
 260         status = "okay";
 261         sata-port@1 {
 262                 status = "okay";
 263                 phys = <&cp0_comphy0 1>;
 264         };
 265 };
 266
 267 &cp0_pcie2 {
 268         status = "okay";
 269         num-lanes = <1>;
 270         num-viewport = <8>;
 271         phys = <&cp0_comphy5 2>;
 272 };
 273
 274 /* U55 */
 275 &cp0_spi1 {
 276         pinctrl-names = "default";
 277         pinctrl-0 = <&cp0_spi0_pins>;
 278         reg = <0x700680 0x50>,          /* control */
 279               <0x2000000 0x1000000>;    /* CS0 */
 280         status = "okay";
 281         spi-flash@0 {
 282                 #address-cells = <0x1>;
 283                 #size-cells = <0x1>;
 284                 compatible = "jedec,spi-nor";
 285                 reg = <0x0>;
 286                 spi-max-frequency = <40000000>;
 287                 partitions {
 288                         compatible = "fixed-partitions";
 289                         #address-cells = <1>;
 290                         #size-cells = <1>;
 291                         partition@0 {
 292                                 label = "U-Boot";
 293                                 reg = <0x0 0x1f0000>;
 294                         };
 295                         partition@1f0000 {
 296                                 label = "U-Boot ENV Factory";
 297                                 reg = <0x1f0000 0x10000>;
 298                         };
 299                         partition@200000 {
 300                                 label = "Reserved";
 301                                 reg = <0x200000 0x1f0000>;
 302                         };
 303                         partition@3f0000 {
 304                                 label = "U-Boot ENV";
 305                                 reg = <0x3f0000 0x10000>;
 306                         };
 307                 };
 308         };
 309 };
 310
 311 &cp0_syscon0 {
 312         cp0_pinctrl: pinctrl {
 313                 compatible = "marvell,cp115-standalone-pinctrl";
 314                 cp0_i2c0_pins: cp0-i2c-pins-0 {
 315                         marvell,pins = "mpp37", "mpp38";
 316                         marvell,function = "i2c0";
 317                 };
 318                 cp0_i2c1_pins: cp0-i2c-pins-1 {
 319                         marvell,pins = "mpp35", "mpp36";
 320                         marvell,function = "i2c1";
 321                 };
 322                 cp0_ge1_rgmii_pins: cp0-ge-rgmii-pins-0 {
 323                         marvell,pins = "mpp0", "mpp1", "mpp2",
 324                                        "mpp3", "mpp4", "mpp5",
 325                                        "mpp6", "mpp7", "mpp8",
 326                                        "mpp9", "mpp10", "mpp11";
 327                         marvell,function = "ge0";
 328                 };
 329                 cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-1 {
 330                         marvell,pins = "mpp44", "mpp45", "mpp46",
 331                                        "mpp47", "mpp48", "mpp49",
 332                                        "mpp50", "mpp51", "mpp52",
 333                                        "mpp53", "mpp54", "mpp55";
 334                         marvell,function = "ge1";
 335                 };
 336                 cp0_spi0_pins: cp0-spi-pins-0 {
 337                         marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
 338                         marvell,function = "spi1";
 339                 };
 340         };
 341 };
 342
 343 &cp0_usb3_1 {
 344         status = "okay";
 345         phys = <&cp0_comphy3 1>;
 346         phy-names = "usb";
 347 };
 348
 349 /*
 350  * Instantiate the first connected CP115
 351  */
 352
 353 #define CP11X_NAME              cp1
 354 #define CP11X_BASE              f4000000
 355 #define CP11X_PCIEx_MEM_BASE(iface) (0xe2000000 + (iface * 0x1000000))
 356 #define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
 357 #define CP11X_PCIE0_BASE        f4600000
 358 #define CP11X_PCIE1_BASE        f4620000
 359 #define CP11X_PCIE2_BASE        f4640000
 360
 361 #include "armada-cp115.dtsi"
 362
 363 #undef CP11X_NAME
 364 #undef CP11X_BASE
 365 #undef CP11X_PCIEx_MEM_BASE
 366 #undef CP11X_PCIEx_MEM_SIZE
 367 #undef CP11X_PCIE0_BASE
 368 #undef CP11X_PCIE1_BASE
 369 #undef CP11X_PCIE2_BASE
 370
 371 &cp1_crypto {
 372         status = "okay";
 373 };
 374
 375 &cp1_xmdio {
 376         status = "okay";
 377         cp1_nbaset_phy0: ethernet-phy@3 {
 378                 compatible = "ethernet-phy-ieee802.3-c45";
 379                 reg = <2>;
 380         };
 381         cp1_nbaset_phy1: ethernet-phy@4 {
 382                 compatible = "ethernet-phy-ieee802.3-c45";
 383                 reg = <0>;
 384         };
 385         cp1_nbaset_phy2: ethernet-phy@5 {
 386                 compatible = "ethernet-phy-ieee802.3-c45";
 387                 reg = <8>;
 388         };
 389 };
 390
 391 &cp1_ethernet {
 392         status = "okay";
 393 };
 394
 395 /* CON50 */
 396 &cp1_eth0 {
 397         status = "okay";
 398         phy-mode = "10gbase-kr";
 399         phys = <&cp1_comphy2 0>;
 400         phy = <&cp1_nbaset_phy0>;
 401 };
 402
 403 &cp1_eth1 {
 404         status = "okay";
 405         phy-mode = "2500base-x";
 406         phys = <&cp1_comphy4 1>;
 407         phy = <&cp1_nbaset_phy1>;
 408 };
 409
 410 &cp1_eth2 {
 411         status = "okay";
 412         phy-mode = "2500base-x";
 413         phys = <&cp1_comphy1 2>;
 414         phy = <&cp1_nbaset_phy2>;
 415 };
 416
 417 &cp1_gpio1 {
 418         status = "okay";
 419 };
 420
 421 &cp1_gpio2 {
 422         status = "okay";
 423 };
 424
 425 &cp1_i2c0 {
 426         status = "okay";
 427         pinctrl-names = "default";
 428         pinctrl-0 = <&cp1_i2c0_pins>;
 429         clock-frequency = <100000>;
 430 };
 431
 432 &cp1_syscon0 {
 433         cp1_pinctrl: pinctrl {
 434                 compatible = "marvell,cp115-standalone-pinctrl";
 435                 cp1_i2c0_pins: cp1-i2c-pins-0 {
 436                         marvell,pins = "mpp37", "mpp38";
 437                         marvell,function = "i2c0";
 438                 };
 439                 cp1_spi0_pins: cp1-spi-pins-0 {
 440                         marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
 441                         marvell,function = "spi1";
 442                 };
 443                 cp1_xhci0_vbus_pins: cp1-xhci0-vbus-pins {
 444                         marvell,pins = "mpp3";
 445                         marvell,function = "gpio";
 446                 };
 447         };
 448 };
 449
 450 /*
 451  * Instantiate the second connected CP115
 452  */
 453
 454 #define CP11X_NAME              cp2
 455 #define CP11X_BASE              f6000000
 456 #define CP11X_PCIEx_MEM_BASE(iface) (0xe5000000 + (iface * 0x1000000))
 457 #define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
 458 #define CP11X_PCIE0_BASE        f6600000
 459 #define CP11X_PCIE1_BASE        f6620000
 460 #define CP11X_PCIE2_BASE        f6640000
 461
 462 #include "armada-cp115.dtsi"
 463
 464 #undef CP11X_NAME
 465 #undef CP11X_BASE
 466 #undef CP11X_PCIEx_MEM_BASE
 467 #undef CP11X_PCIEx_MEM_SIZE
 468 #undef CP11X_PCIE0_BASE
 469 #undef CP11X_PCIE1_BASE
 470 #undef CP11X_PCIE2_BASE
 471
 472 &cp2_crypto {
 473         status = "okay";
 474 };
 475
 476 &cp2_ethernet {
 477         status = "okay";
 478 };
 479
 480 &cp2_xmdio {
 481         status = "okay";
 482         cp2_nbaset_phy0: ethernet-phy@6 {
 483                 compatible = "ethernet-phy-ieee802.3-c45";
 484                 reg = <2>;
 485         };
 486         cp2_nbaset_phy1: ethernet-phy@7 {
 487                 compatible = "ethernet-phy-ieee802.3-c45";
 488                 reg = <0>;
 489         };
 490         cp2_nbaset_phy2: ethernet-phy@8 {
 491                 compatible = "ethernet-phy-ieee802.3-c45";
 492                 reg = <8>;
 493         };
 494 };
 495
 496 /* SLM-1521-V2, CON9 */
 497 &cp2_eth0 {
 498         status = "okay";
 499         phy-mode = "10gbase-kr";
 500         phys = <&cp2_comphy2 0>;
 501         phy = <&cp2_nbaset_phy0>;
 502 };
 503
 504 &cp2_eth1 {
 505         status = "okay";
 506         phy-mode = "2500base-x";
 507         phys = <&cp2_comphy4 1>;
 508         phy = <&cp2_nbaset_phy1>;
 509 };
 510
 511 &cp2_eth2 {
 512         status = "okay";
 513         phy-mode = "2500base-x";
 514         phys = <&cp2_comphy1 2>;
 515         phy = <&cp2_nbaset_phy2>;
 516 };
 517
 518 &cp2_gpio1 {
 519         status = "okay";
 520 };
 521
 522 &cp2_gpio2 {
 523         status = "okay";
 524 };
 525
 526 &cp2_i2c0 {
 527         clock-frequency = <100000>;
 528         /* SLM-1521-V2 - U3 */
 529         i2c-mux@72 {
 530                 compatible = "nxp,pca9544";
 531                 #address-cells = <1>;
 532                 #size-cells = <0>;
 533                 reg = <0x72>;
 534                 cp2_sfpp0_i2c: i2c@0 {
 535                         #address-cells = <1>;
 536                         #size-cells = <0>;
 537                         reg = <0>;
 538                 };
 539
 540                 i2c@1 {
 541                         #address-cells = <1>;
 542                         #size-cells = <0>;
 543                         reg = <1>;
 544                         /* U12 */
 545                         cp2_module_expander1: pca9555@21 {
 546                                 compatible = "nxp,pca9555";
 547                                 pinctrl-names = "default";
 548                                 gpio-controller;
 549                                 #gpio-cells = <2>;
 550                                 reg = <0x21>;
 551                         };
 552                 };
 553         };
 554 };
 555
 556 &cp2_syscon0 {
 557         cp2_pinctrl: pinctrl {
 558                 compatible = "marvell,cp115-standalone-pinctrl";
 559                 cp2_i2c0_pins: cp2-i2c-pins-0 {
 560                         marvell,pins = "mpp37", "mpp38";
 561                         marvell,function = "i2c0";
 562                 };
 563         };
 564 };