1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 * Device Tree file for Globalscale MOCHAbin
4 * Copyright (C) 2019 Globalscale technologies, Inc.
5 * Copyright (C) 2021 Sartura Ltd.
11 #include <dt-bindings/gpio/gpio.h>
12 #include "armada-7040.dtsi"
15 model = "Globalscale MOCHAbin";
16 compatible = "globalscale,mochabin", "marvell,armada7040",
17 "marvell,armada-ap806-quad", "marvell,armada-ap806";
20 stdout-path = "serial0:115200n8";
24 ethernet0 = &cp0_eth0;
25 ethernet1 = &cp0_eth1;
26 ethernet2 = &cp0_eth2;
35 compatible = "sff,sfp";
36 i2c-bus = <&cp0_i2c1>;
37 los-gpio = <&sfp_gpio 3 GPIO_ACTIVE_HIGH>;
38 mod-def0-gpio = <&sfp_gpio 2 GPIO_ACTIVE_LOW>;
39 tx-disable-gpio = <&sfp_gpio 1 GPIO_ACTIVE_HIGH>;
40 tx-fault-gpio = <&sfp_gpio 0 GPIO_ACTIVE_HIGH>;
45 compatible = "sff,sfp";
46 i2c-bus = <&cp0_i2c0>;
47 los-gpio = <&sfp_gpio 7 GPIO_ACTIVE_HIGH>;
48 mod-def0-gpio = <&sfp_gpio 6 GPIO_ACTIVE_LOW>;
49 tx-disable-gpio = <&sfp_gpio 5 GPIO_ACTIVE_HIGH>;
50 tx-fault-gpio = <&sfp_gpio 4 GPIO_ACTIVE_HIGH>;
54 /* microUSB UART console */
58 pinctrl-0 = <&uart0_pins>;
59 pinctrl-names = "default";
68 /delete-property/ marvell,xenon-phy-slow-mode;
73 cp0_uart0_pins: cp0-uart0-pins {
74 marvell,pins = "mpp6", "mpp7";
75 marvell,function = "uart0";
78 cp0_spi0_pins: cp0-spi0-pins {
79 marvell,pins = "mpp56", "mpp57", "mpp58", "mpp59";
80 marvell,function = "spi0";
83 cp0_spi1_pins: cp0-spi1-pins {
84 marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
85 marvell,function = "spi1";
88 cp0_i2c0_pins: cp0-i2c0-pins {
89 marvell,pins = "mpp37", "mpp38";
90 marvell,function = "i2c0";
93 cp0_i2c1_pins: cp0-i2c1-pins {
94 marvell,pins = "mpp2", "mpp3";
95 marvell,function = "i2c1";
98 pca9554_int_pins: pca9554-int-pins {
99 marvell,pins = "mpp27";
100 marvell,function = "gpio";
103 cp0_rgmii1_pins: cp0-rgmii1-pins {
104 marvell,pins = "mpp44", "mpp45", "mpp46", "mpp47", "mpp48", "mpp49",
105 "mpp50", "mpp51", "mpp52", "mpp53", "mpp54", "mpp55";
106 marvell,function = "ge1";
109 is31_sdb_pins: is31-sdb-pins {
110 marvell,pins = "mpp30";
111 marvell,function = "gpio";
114 cp0_pcie_reset_pins: cp0-pcie-reset-pins {
115 marvell,pins = "mpp9";
116 marvell,function = "gpio";
119 cp0_switch_pins: cp0-switch-pins {
120 marvell,pins = "mpp0", "mpp1";
121 marvell,function = "gpio";
124 cp0_phy_pins: cp0-phy-pins {
125 marvell,pins = "mpp12";
126 marvell,function = "gpio";
134 pinctrl-names = "default";
135 pinctrl-0 = <&cp0_uart0_pins>;
142 pinctrl-names = "default";
143 pinctrl-0 = <&cp0_spi0_pins>;
150 pinctrl-names = "default";
151 pinctrl-0 = <&cp0_spi1_pins>;
154 #address-cells = <1>;
156 compatible = "jedec,spi-nor";
158 spi-max-frequency = <20000000>;
161 compatible = "fixed-partitions";
162 #address-cells = <1>;
167 reg = <0x0 0x3e0000>;
173 reg = <0x3e0000 0x10000>;
178 label = "u-boot-env";
179 reg = <0x3f0000 0x10000>;
185 /* mikroBUS, 1G SFP and GPIO expander */
189 pinctrl-names = "default";
190 pinctrl-0 = <&cp0_i2c0_pins>;
191 clock-frequency = <100000>;
193 sfp_gpio: pca9554@39 {
194 compatible = "nxp,pca9554";
195 pinctrl-names = "default";
196 pinctrl-0 = <&pca9554_int_pins>;
199 interrupt-parent = <&cp0_gpio1>;
200 interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
201 interrupt-controller;
202 #interrupt-cells = <2>;
208 * IO0_0: SFP+_TX_FAULT
209 * IO0_1: SFP+_TX_DISABLE
212 * IO0_4: SFP_TX_FAULT
213 * IO0_5: SFP_TX_DISABLE
220 /* IS31FL3199, mini-PCIe and 10G SFP+ */
224 pinctrl-names = "default";
225 pinctrl-0 = <&cp0_i2c1_pins>;
226 clock-frequency = <100000>;
229 compatible = "issi,is31fl3199";
230 #address-cells = <1>;
232 pinctrl-names = "default";
233 pinctrl-0 = <&is31_sdb_pins>;
234 shutdown-gpios = <&cp0_gpio1 30 GPIO_ACTIVE_HIGH>;
240 led-max-microamp = <20000>;
244 label = "green:led1";
259 label = "green:led2";
274 label = "green:led3";
289 eth2phy: ethernet-phy@1 {
293 pinctrl-names = "default";
294 pinctrl-0 = <&cp0_phy_pins>;
295 reset-gpios = <&cp0_gpio1 12 GPIO_ACTIVE_LOW>;
298 /* 88E6141 Topaz switch */
300 compatible = "marvell,mv88e6085";
301 #address-cells = <1>;
305 pinctrl-names = "default";
306 pinctrl-0 = <&cp0_switch_pins>;
307 reset-gpios = <&cp0_gpio1 0 GPIO_ACTIVE_LOW>;
309 interrupt-parent = <&cp0_gpio1>;
310 interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
313 #address-cells = <1>;
319 phy-handle = <&swphy1>;
325 phy-handle = <&swphy2>;
331 phy-handle = <&swphy3>;
337 phy-handle = <&swphy4>;
342 ethernet = <&cp0_eth1>;
343 phy-mode = "2500base-x";
344 managed = "in-band-status";
349 #address-cells = <1>;
379 phy-mode = "10gbase-r";
380 phys = <&cp0_comphy4 0>;
381 managed = "in-band-status";
385 /* Topaz switch uplink */
389 phy-mode = "2500base-x";
390 phys = <&cp0_comphy0 1>;
398 /* 1G SFP or 1G RJ45 */
402 pinctrl-names = "default";
403 pinctrl-0 = <&cp0_rgmii1_pins>;
406 phy-mode = "rgmii-id";
409 /* SMSC USB5434B hub */
413 phys = <&cp0_comphy1 0>;
414 phy-names = "cp0-usb3h0-comphy";
425 /* 7 + 12 SATA connector (J24) */
427 phys = <&cp0_comphy2 0>;
428 phy-names = "cp0-sata0-0-phy";
431 /* M.2-2250 B-key (J39) */
433 phys = <&cp0_comphy3 1>;
434 phy-names = "cp0-sata0-1-phy";
442 pinctrl-names = "default";
443 pinctrl-0 = <&cp0_pcie_reset_pins>;
444 phys = <&cp0_comphy5 2>;
445 phy-names = "cp0-pcie2-x1-phy";
446 reset-gpio = <&cp0_gpio1 9 GPIO_ACTIVE_LOW>;
447 ranges = <0x82000000 0x0 0xc0000000 0x0 0xc0000000 0x0 0x8000000>;