1 From bcb0e54d62804f1f986ad478a11235dadb1b61bb Mon Sep 17 00:00:00 2001
2 From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
3 Date: Fri, 14 Jun 2013 10:44:57 -0300
4 Subject: [PATCH 058/203] ARM: mvebu: Relocate Armada 370/XP DeviceBus device
7 Now that mbus has been added to the device tree, it's possible to
8 move the DeviceBus out of internal registers, placing it directly
9 below the mbus. This is a more accurate representation of the hardware.
11 Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
12 Tested-by: Andrew Lunn <andrew@lunn.ch>
13 Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
15 arch/arm/boot/dts/armada-370-xp.dtsi | 94 +++++++++++++-----------
16 arch/arm/boot/dts/armada-xp-db.dts | 59 +++++++--------
17 arch/arm/boot/dts/armada-xp-gp.dts | 60 +++++++--------
18 arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts | 60 +++++++--------
19 4 files changed, 140 insertions(+), 133 deletions(-)
21 --- a/arch/arm/boot/dts/armada-370-xp.dtsi
22 +++ b/arch/arm/boot/dts/armada-370-xp.dtsi
24 controller = <&mbusc>;
25 interrupt-parent = <&mpic>;
28 + compatible = "marvell,mvebu-devbus";
29 + reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
30 + ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
31 + #address-cells = <1>;
33 + clocks = <&coreclk 0>;
34 + status = "disabled";
38 + compatible = "marvell,mvebu-devbus";
39 + reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
40 + ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
41 + #address-cells = <1>;
43 + clocks = <&coreclk 0>;
44 + status = "disabled";
48 + compatible = "marvell,mvebu-devbus";
49 + reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
50 + ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
51 + #address-cells = <1>;
53 + clocks = <&coreclk 0>;
54 + status = "disabled";
58 + compatible = "marvell,mvebu-devbus";
59 + reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
60 + ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
61 + #address-cells = <1>;
63 + clocks = <&coreclk 0>;
64 + status = "disabled";
68 + compatible = "marvell,mvebu-devbus";
69 + reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
70 + ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
71 + #address-cells = <1>;
73 + clocks = <&coreclk 0>;
74 + status = "disabled";
78 compatible = "simple-bus";
84 - devbus-bootcs@10400 {
85 - compatible = "marvell,mvebu-devbus";
86 - reg = <0x10400 0x8>;
87 - #address-cells = <1>;
89 - clocks = <&coreclk 0>;
90 - status = "disabled";
94 - compatible = "marvell,mvebu-devbus";
95 - reg = <0x10408 0x8>;
96 - #address-cells = <1>;
98 - clocks = <&coreclk 0>;
99 - status = "disabled";
103 - compatible = "marvell,mvebu-devbus";
104 - reg = <0x10410 0x8>;
105 - #address-cells = <1>;
107 - clocks = <&coreclk 0>;
108 - status = "disabled";
112 - compatible = "marvell,mvebu-devbus";
113 - reg = <0x10418 0x8>;
114 - #address-cells = <1>;
116 - clocks = <&coreclk 0>;
117 - status = "disabled";
121 - compatible = "marvell,mvebu-devbus";
122 - reg = <0x10420 0x8>;
123 - #address-cells = <1>;
125 - clocks = <&coreclk 0>;
126 - status = "disabled";
131 --- a/arch/arm/boot/dts/armada-xp-db.dts
132 +++ b/arch/arm/boot/dts/armada-xp-db.dts
136 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
137 - MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>;
138 + MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
139 + MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>;
144 + /* Device Bus parameters are required */
146 + /* Read parameters */
147 + devbus,bus-width = <8>;
148 + devbus,turn-off-ps = <60000>;
149 + devbus,badr-skew-ps = <0>;
150 + devbus,acc-first-ps = <124000>;
151 + devbus,acc-next-ps = <248000>;
152 + devbus,rd-setup-ps = <0>;
153 + devbus,rd-hold-ps = <0>;
155 + /* Write parameters */
156 + devbus,sync-enable = <0>;
157 + devbus,wr-high-ps = <60000>;
158 + devbus,wr-low-ps = <60000>;
159 + devbus,ale-wr-ps = <60000>;
163 + compatible = "cfi-flash";
164 + reg = <0 0x1000000>;
175 - devbus-bootcs@10400 {
177 - ranges = <0 0xf0000000 0x1000000>;
179 - /* Device Bus parameters are required */
181 - /* Read parameters */
182 - devbus,bus-width = <8>;
183 - devbus,turn-off-ps = <60000>;
184 - devbus,badr-skew-ps = <0>;
185 - devbus,acc-first-ps = <124000>;
186 - devbus,acc-next-ps = <248000>;
187 - devbus,rd-setup-ps = <0>;
188 - devbus,rd-hold-ps = <0>;
190 - /* Write parameters */
191 - devbus,sync-enable = <0>;
192 - devbus,wr-high-ps = <60000>;
193 - devbus,wr-low-ps = <60000>;
194 - devbus,ale-wr-ps = <60000>;
198 - compatible = "cfi-flash";
199 - reg = <0 0x1000000>;
206 --- a/arch/arm/boot/dts/armada-xp-gp.dts
207 +++ b/arch/arm/boot/dts/armada-xp-gp.dts
211 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
212 - MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>;
213 + MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
214 + MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>;
219 + /* Device Bus parameters are required */
221 + /* Read parameters */
222 + devbus,bus-width = <8>;
223 + devbus,turn-off-ps = <60000>;
224 + devbus,badr-skew-ps = <0>;
225 + devbus,acc-first-ps = <124000>;
226 + devbus,acc-next-ps = <248000>;
227 + devbus,rd-setup-ps = <0>;
228 + devbus,rd-hold-ps = <0>;
230 + /* Write parameters */
231 + devbus,sync-enable = <0>;
232 + devbus,wr-high-ps = <60000>;
233 + devbus,wr-low-ps = <60000>;
234 + devbus,ale-wr-ps = <60000>;
238 + compatible = "cfi-flash";
239 + reg = <0 0x1000000>;
250 - devbus-bootcs@10400 {
252 - ranges = <0 0xf0000000 0x1000000>; /* @addr 0xf000000, size 0x1000000 */
254 - /* Device Bus parameters are required */
256 - /* Read parameters */
257 - devbus,bus-width = <8>;
258 - devbus,turn-off-ps = <60000>;
259 - devbus,badr-skew-ps = <0>;
260 - devbus,acc-first-ps = <124000>;
261 - devbus,acc-next-ps = <248000>;
262 - devbus,rd-setup-ps = <0>;
263 - devbus,rd-hold-ps = <0>;
265 - /* Write parameters */
266 - devbus,sync-enable = <0>;
267 - devbus,wr-high-ps = <60000>;
268 - devbus,wr-low-ps = <60000>;
269 - devbus,ale-wr-ps = <60000>;
273 - compatible = "cfi-flash";
274 - reg = <0 0x1000000>;
282 --- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
283 +++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
287 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
288 - MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>;
289 + MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
290 + MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x8000000>;
295 + /* Device Bus parameters are required */
297 + /* Read parameters */
298 + devbus,bus-width = <8>;
299 + devbus,turn-off-ps = <60000>;
300 + devbus,badr-skew-ps = <0>;
301 + devbus,acc-first-ps = <124000>;
302 + devbus,acc-next-ps = <248000>;
303 + devbus,rd-setup-ps = <0>;
304 + devbus,rd-hold-ps = <0>;
306 + /* Write parameters */
307 + devbus,sync-enable = <0>;
308 + devbus,wr-high-ps = <60000>;
309 + devbus,wr-low-ps = <60000>;
310 + devbus,ale-wr-ps = <60000>;
314 + compatible = "cfi-flash";
315 + reg = <0 0x8000000>;
326 - devbus-bootcs@10400 {
328 - ranges = <0 0xf0000000 0x8000000>; /* @addr 0xf000000, size 0x8000000 */
330 - /* Device Bus parameters are required */
332 - /* Read parameters */
333 - devbus,bus-width = <8>;
334 - devbus,turn-off-ps = <60000>;
335 - devbus,badr-skew-ps = <0>;
336 - devbus,acc-first-ps = <124000>;
337 - devbus,acc-next-ps = <248000>;
338 - devbus,rd-setup-ps = <0>;
339 - devbus,rd-hold-ps = <0>;
341 - /* Write parameters */
342 - devbus,sync-enable = <0>;
343 - devbus,wr-high-ps = <60000>;
344 - devbus,wr-low-ps = <60000>;
345 - devbus,ale-wr-ps = <60000>;
349 - compatible = "cfi-flash";
350 - reg = <0 0x8000000>;
357 /* Internal mini-PCIe connector */