target/linux/mvebu/patches-3.8/009-mmc_mvsdio_add_pinctrl.patch

   1 On many Marvell SoCs, the pins used for the SDIO interface are part of
   2 the MPP pins, that are muxable pins. In order to get the muxing of
   3 those pins correct, this commit integrates the mvsdio driver with the
   4 pinctrl infrastructure by calling devm_pinctrl_get_select_default()
   5 during ->probe().
   6
   7 Note that we permit this function to fail because not all Marvell
   8 platforms have yet been fully converted to using the pinctrl
   9 infrastructure.
  10
  11 Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  12 ---
  13  drivers/mmc/host/mvsdio.c |    6 ++++++
  14  1 file changed, 6 insertions(+)
  15
  16 diff --git a/drivers/mmc/host/mvsdio.c b/drivers/mmc/host/mvsdio.c
  17 index 56954bc..feb16bd 100644
  18 --- a/drivers/mmc/host/mvsdio.c
  19 +++ b/drivers/mmc/host/mvsdio.c
  20 @@ -25,6 +25,7 @@
  21  #include <linux/of_irq.h>
  22  #include <linux/mmc/host.h>
  23  #include <linux/mmc/slot-gpio.h>
  24 +#include <linux/pinctrl/consumer.h>
  25
  26  #include <asm/sizes.h>
  27  #include <asm/unaligned.h>
  28 @@ -692,6 +693,7 @@ static int __init mvsd_probe(struct platform_device *pdev)
  29         struct resource *r;
  30         int ret, irq;
  31         int gpio_card_detect, gpio_write_protect;
  32 +       struct pinctrl *pinctrl;
  33
  34         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  35         irq = platform_get_irq(pdev, 0);
  36 @@ -713,6 +715,10 @@ static int __init mvsd_probe(struct platform_device *pdev)
  37         host->dev = &pdev->dev;
  38         host->res = r;
  39
  40 +       pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
  41 +       if (IS_ERR(pinctrl))
  42 +               dev_warn(&pdev->dev, "no pins associated\n");
  43 +
  44         /* Some non-DT platforms do not pass a clock, and the clock
  45            frequency is passed through platform_data. On DT platforms,
  46            a clock must always be passed, even if there is no gatable
  47 --
  48 1.7.9.5