1 From: =?UTF-8?q?Ezequiel=20Garc=C3=ADa?= <ezequiel@vanguardiasur.com.ar>
2 Date: Wed, 4 Nov 2015 13:13:42 -0300
3 Subject: [PATCH] mtd: pxa3xx_nand: Fix initial controller configuration
5 The Data Flash Control Register (NDCR) contains two types
6 of parameters: those that are needed for device identification,
7 and those that can only be set after device identification.
9 Therefore, the driver can't set them all at once and instead
10 needs to configure the first group before nand_scan_ident()
11 and the second group later.
13 Let's split pxa3xx_nand_config in two halves, and set the
14 parameters that depend on the device geometry once this is known.
16 Signed-off-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
17 Signed-off-by: Brian Norris <computersforpeace@gmail.com>
20 --- a/drivers/mtd/nand/pxa3xx_nand.c
21 +++ b/drivers/mtd/nand/pxa3xx_nand.c
22 @@ -1420,34 +1420,43 @@ static int pxa3xx_nand_waitfunc(struct m
23 return NAND_STATUS_READY;
26 -static int pxa3xx_nand_config_flash(struct pxa3xx_nand_info *info)
27 +static int pxa3xx_nand_config_ident(struct pxa3xx_nand_info *info)
29 struct platform_device *pdev = info->pdev;
30 struct pxa3xx_nand_platform_data *pdata = dev_get_platdata(&pdev->dev);
31 - struct pxa3xx_nand_host *host = info->host[info->cs];
32 - struct mtd_info *mtd = host->mtd;
33 - struct nand_chip *chip = mtd->priv;
35 - /* configure default flash values */
36 + /* Configure default flash values */
37 + info->chunk_size = PAGE_CHUNK_SIZE;
38 info->reg_ndcr = 0x0; /* enable all interrupts */
39 info->reg_ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0;
40 info->reg_ndcr |= NDCR_RD_ID_CNT(READ_ID_BYTES);
41 - info->reg_ndcr |= NDCR_SPARE_EN; /* enable spare by default */
42 + info->reg_ndcr |= NDCR_SPARE_EN;
47 +static void pxa3xx_nand_config_tail(struct pxa3xx_nand_info *info)
49 + struct pxa3xx_nand_host *host = info->host[info->cs];
50 + struct mtd_info *mtd = host->mtd;
51 + struct nand_chip *chip = mtd->priv;
53 info->reg_ndcr |= (host->col_addr_cycles == 2) ? NDCR_RA_START : 0;
54 info->reg_ndcr |= (chip->page_shift == 6) ? NDCR_PG_PER_BLK : 0;
55 info->reg_ndcr |= (mtd->writesize == 2048) ? NDCR_PAGE_SZ : 0;
60 static int pxa3xx_nand_detect_config(struct pxa3xx_nand_info *info)
62 + struct platform_device *pdev = info->pdev;
63 + struct pxa3xx_nand_platform_data *pdata = dev_get_platdata(&pdev->dev);
64 uint32_t ndcr = nand_readl(info, NDCR);
66 /* Set an initial chunk size */
67 info->chunk_size = ndcr & NDCR_PAGE_SZ ? 2048 : 512;
68 info->reg_ndcr = ndcr &
69 ~(NDCR_INT_MASK | NDCR_ND_ARB_EN | NFCV1_NDCR_ARB_CNTL);
70 + info->reg_ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0;
71 info->ndtr0cs0 = nand_readl(info, NDTR0CS0);
72 info->ndtr1cs0 = nand_readl(info, NDTR1CS0);
74 @@ -1636,10 +1645,7 @@ static int pxa3xx_nand_scan(struct mtd_i
75 if (pdata->keep_config && !pxa3xx_nand_detect_config(info))
78 - /* Set a default chunk size */
79 - info->chunk_size = PAGE_CHUNK_SIZE;
81 - ret = pxa3xx_nand_config_flash(info);
82 + ret = pxa3xx_nand_config_ident(info);
86 @@ -1652,7 +1658,6 @@ static int pxa3xx_nand_scan(struct mtd_i
90 - info->reg_ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0;
91 if (info->reg_ndcr & NDCR_DWIDTH_M)
92 chip->options |= NAND_BUSWIDTH_16;
94 @@ -1737,6 +1742,10 @@ KEEP_CONFIG:
95 host->row_addr_cycles = 3;
97 host->row_addr_cycles = 2;
99 + if (!pdata->keep_config)
100 + pxa3xx_nand_config_tail(info);
102 return nand_scan_tail(mtd);