1 From 30d53abdc60a6515f02f181e7c39b7b23d5fb3aa Mon Sep 17 00:00:00 2001
2 From: Grzegorz Jaszczyk <jaz@semihalf.com>
3 Date: Fri, 4 Oct 2019 16:27:27 +0200
4 Subject: [PATCH] arm64: dts: marvell: Add AP807-quad cache description
6 Adding appropriate entries to device-tree allows the cache description
7 to show up in sysfs under: /sys/devices/system/cpu/cpuX/cache/.
9 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
10 Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
11 Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
13 .../boot/dts/marvell/armada-ap807-quad.dtsi | 42 +++++++++++++++++++
14 1 file changed, 42 insertions(+)
16 --- a/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi
17 +++ b/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi
19 enable-method = "psci";
21 clocks = <&cpu_clk 0>;
22 + i-cache-size = <0xc000>;
23 + i-cache-line-size = <64>;
24 + i-cache-sets = <256>;
25 + d-cache-size = <0x8000>;
26 + d-cache-line-size = <64>;
27 + d-cache-sets = <256>;
28 + next-level-cache = <&l2_0>;
33 enable-method = "psci";
35 clocks = <&cpu_clk 0>;
36 + i-cache-size = <0xc000>;
37 + i-cache-line-size = <64>;
38 + i-cache-sets = <256>;
39 + d-cache-size = <0x8000>;
40 + d-cache-line-size = <64>;
41 + d-cache-sets = <256>;
42 + next-level-cache = <&l2_0>;
47 enable-method = "psci";
49 clocks = <&cpu_clk 1>;
50 + i-cache-size = <0xc000>;
51 + i-cache-line-size = <64>;
52 + i-cache-sets = <256>;
53 + d-cache-size = <0x8000>;
54 + d-cache-line-size = <64>;
55 + d-cache-sets = <256>;
56 + next-level-cache = <&l2_1>;
61 enable-method = "psci";
63 clocks = <&cpu_clk 1>;
64 + i-cache-size = <0xc000>;
65 + i-cache-line-size = <64>;
66 + i-cache-sets = <256>;
67 + d-cache-size = <0x8000>;
68 + d-cache-line-size = <64>;
69 + d-cache-sets = <256>;
70 + next-level-cache = <&l2_1>;
74 + compatible = "cache";
75 + cache-size = <0x80000>;
76 + cache-line-size = <64>;
81 + compatible = "cache";
82 + cache-size = <0x80000>;
83 + cache-line-size = <64>;