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ipq806x: remove obsolete Kernel 5.4
[openwrt/staging/robimarko.git] / target / linux / mvebu / patches-5.4 / 005-v5.5-arm64-dts-marvell-Drop-PCIe-I-O-ranges-from-CP11x-fi.patch
1 From 1399672e48b573f6526b9ac78cfd50314f0b01a6 Mon Sep 17 00:00:00 2001
2 From: Miquel Raynal <miquel.raynal@bootlin.com>
3 Date: Fri, 4 Oct 2019 16:27:30 +0200
4 Subject: [PATCH] arm64: dts: marvell: Drop PCIe I/O ranges from CP11x file
5
6 As an example, Armada 70x0 and 80x0 SoC 0xf9000000 region points to
7 RUNIT/SPICS0 while it is referenced in the DT as PCIe I/O memory
8 range. This shows that I/O memory has never been used/working on the
9 old SoCs despite the region being advertised. As PCIe I/O ranges will
10 not be supported in newer SoCs using CP11x co-processors, let's
11 simply drop them. It is not harmful in any case as PCIe device drivers
12 can do it all with the regular mapped memory anyway.
13
14 Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
15 Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
16 ---
17 arch/arm64/boot/dts/marvell/armada-70x0.dtsi | 2 --
18 .../boot/dts/marvell/armada-8040-mcbin.dtsi | 3 +--
19 arch/arm64/boot/dts/marvell/armada-80x0.dtsi | 4 ----
20 arch/arm64/boot/dts/marvell/armada-cp11x.dtsi | 16 +++-------------
21 4 files changed, 4 insertions(+), 21 deletions(-)
22
23 --- a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
24 +++ b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
25 @@ -19,7 +19,6 @@
26 */
27 #define CP11X_NAME cp0
28 #define CP11X_BASE f2000000
29 -#define CP11X_PCIE_IO_BASE 0xf9000000
30 #define CP11X_PCIE_MEM_BASE 0xf6000000
31 #define CP11X_PCIE0_BASE f2600000
32 #define CP11X_PCIE1_BASE f2620000
33 @@ -29,7 +28,6 @@
34
35 #undef CP11X_NAME
36 #undef CP11X_BASE
37 -#undef CP11X_PCIE_IO_BASE
38 #undef CP11X_PCIE_MEM_BASE
39 #undef CP11X_PCIE0_BASE
40 #undef CP11X_PCIE1_BASE
41 --- a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
42 +++ b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
43 @@ -179,8 +179,7 @@
44 num-lanes = <4>;
45 num-viewport = <8>;
46 reset-gpios = <&cp0_gpio2 20 GPIO_ACTIVE_LOW>;
47 - ranges = <0x81000000 0x0 0xf9010000 0x0 0xf9010000 0x0 0x10000
48 - 0x82000000 0x0 0xc0000000 0x0 0xc0000000 0x0 0x20000000>;
49 + ranges = <0x82000000 0x0 0xc0000000 0x0 0xc0000000 0x0 0x20000000>;
50 phys = <&cp0_comphy0 0>, <&cp0_comphy1 0>,
51 <&cp0_comphy2 0>, <&cp0_comphy3 0>;
52 phy-names = "cp0-pcie0-x4-lane0-phy", "cp0-pcie0-x4-lane1-phy",
53 --- a/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
54 +++ b/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
55 @@ -21,7 +21,6 @@
56 */
57 #define CP11X_NAME cp0
58 #define CP11X_BASE f2000000
59 -#define CP11X_PCIE_IO_BASE 0xf9000000
60 #define CP11X_PCIE_MEM_BASE 0xf6000000
61 #define CP11X_PCIE0_BASE f2600000
62 #define CP11X_PCIE1_BASE f2620000
63 @@ -31,7 +30,6 @@
64
65 #undef CP11X_NAME
66 #undef CP11X_BASE
67 -#undef CP11X_PCIE_IO_BASE
68 #undef CP11X_PCIE_MEM_BASE
69 #undef CP11X_PCIE0_BASE
70 #undef CP11X_PCIE1_BASE
71 @@ -42,7 +40,6 @@
72 */
73 #define CP11X_NAME cp1
74 #define CP11X_BASE f4000000
75 -#define CP11X_PCIE_IO_BASE 0xfd000000
76 #define CP11X_PCIE_MEM_BASE 0xfa000000
77 #define CP11X_PCIE0_BASE f4600000
78 #define CP11X_PCIE1_BASE f4620000
79 @@ -52,7 +49,6 @@
80
81 #undef CP11X_NAME
82 #undef CP11X_BASE
83 -#undef CP11X_PCIE_IO_BASE
84 #undef CP11X_PCIE_MEM_BASE
85 #undef CP11X_PCIE0_BASE
86 #undef CP11X_PCIE1_BASE
87 --- a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
88 +++ b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
89 @@ -10,7 +10,6 @@
90
91 #include "armada-common.dtsi"
92
93 -#define CP11X_PCIEx_IO_BASE(iface) (CP11X_PCIE_IO_BASE + (iface * 0x10000))
94 #define CP11X_PCIEx_MEM_BASE(iface) (CP11X_PCIE_MEM_BASE + (iface * 0x1000000))
95 #define CP11X_PCIEx_CONF_BASE(iface) (CP11X_PCIEx_MEM_BASE(iface) + 0xf00000)
96
97 @@ -507,11 +506,8 @@
98 msi-parent = <&gic_v2m0>;
99
100 bus-range = <0 0xff>;
101 - ranges =
102 - /* downstream I/O */
103 - <0x81000000 0 CP11X_PCIEx_IO_BASE(0) 0 CP11X_PCIEx_IO_BASE(0) 0 0x10000
104 /* non-prefetchable memory */
105 - 0x82000000 0 CP11X_PCIEx_MEM_BASE(0) 0 CP11X_PCIEx_MEM_BASE(0) 0 0xf00000>;
106 + ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(0) 0 CP11X_PCIEx_MEM_BASE(0) 0 0xf00000>;
107 interrupt-map-mask = <0 0 0 0>;
108 interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 22 IRQ_TYPE_LEVEL_HIGH>;
109 interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
110 @@ -534,11 +530,8 @@
111 msi-parent = <&gic_v2m0>;
112
113 bus-range = <0 0xff>;
114 - ranges =
115 - /* downstream I/O */
116 - <0x81000000 0 CP11X_PCIEx_IO_BASE(1) 0 CP11X_PCIEx_IO_BASE(1) 0 0x10000
117 /* non-prefetchable memory */
118 - 0x82000000 0 CP11X_PCIEx_MEM_BASE(1) 0 CP11X_PCIEx_MEM_BASE(1) 0 0xf00000>;
119 + ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(1) 0 CP11X_PCIEx_MEM_BASE(1) 0 0xf00000>;
120 interrupt-map-mask = <0 0 0 0>;
121 interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 24 IRQ_TYPE_LEVEL_HIGH>;
122 interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
123 @@ -562,11 +555,8 @@
124 msi-parent = <&gic_v2m0>;
125
126 bus-range = <0 0xff>;
127 - ranges =
128 - /* downstream I/O */
129 - <0x81000000 0 CP11X_PCIEx_IO_BASE(2) 0 CP11X_PCIEx_IO_BASE(2) 0 0x10000
130 /* non-prefetchable memory */
131 - 0x82000000 0 CP11X_PCIEx_MEM_BASE(2) 0 CP11X_PCIEx_MEM_BASE(2) 0 0xf00000>;
132 + ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(2) 0 CP11X_PCIEx_MEM_BASE(2) 0 0xf00000>;
133 interrupt-map-mask = <0 0 0 0>;
134 interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 23 IRQ_TYPE_LEVEL_HIGH>;
135 interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
Staging tree of Robert Marko