1 From 7409b155562cc19b929b57692b334c5758ffc75d Mon Sep 17 00:00:00 2001
2 From: Konstantin Porotchkin <kostap@marvell.com>
3 Date: Fri, 4 Oct 2019 16:27:22 +0200
4 Subject: [PATCH] arm64: dts: marvell: Prepare the introduction of AP807 based
7 Prepare the support for Marvell AP807 die. This die is very similar to
8 AP806 but uses different DDR PHY. AP807 is a major component of CN9130
11 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
12 Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
13 Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
15 arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 448 +----------------
16 arch/arm64/boot/dts/marvell/armada-ap80x.dtsi | 456 ++++++++++++++++++
17 2 files changed, 458 insertions(+), 446 deletions(-)
18 create mode 100644 arch/arm64/boot/dts/marvell/armada-ap80x.dtsi
20 --- a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
21 +++ b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
23 * Device Tree file for Marvell Armada AP806.
26 -#include <dt-bindings/interrupt-controller/arm-gic.h>
27 -#include <dt-bindings/thermal/thermal.h>
30 +#define AP_NAME ap806
31 +#include "armada-ap80x.dtsi"
34 model = "Marvell Armada AP806";
35 compatible = "marvell,armada-ap806";
36 - #address-cells = <2>;
47 - compatible = "arm,psci-0.2";
52 - #address-cells = <2>;
57 - * This area matches the mapping done with a
58 - * mainline U-Boot, and should be updated by the
63 - reg = <0x0 0x4000000 0x0 0x200000>;
69 - #address-cells = <2>;
71 - compatible = "simple-bus";
72 - interrupt-parent = <&gic>;
75 - config-space@f0000000 {
76 - #address-cells = <1>;
78 - compatible = "simple-bus";
79 - ranges = <0x0 0x0 0xf0000000 0x1000000>;
81 - gic: interrupt-controller@210000 {
82 - compatible = "arm,gic-400";
83 - #interrupt-cells = <3>;
84 - #address-cells = <1>;
87 - interrupt-controller;
88 - interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
89 - reg = <0x210000 0x10000>,
94 - gic_v2m0: v2m@280000 {
95 - compatible = "arm,gic-v2m-frame";
97 - reg = <0x280000 0x1000>;
98 - arm,msi-base-spi = <160>;
99 - arm,msi-num-spis = <32>;
101 - gic_v2m1: v2m@290000 {
102 - compatible = "arm,gic-v2m-frame";
104 - reg = <0x290000 0x1000>;
105 - arm,msi-base-spi = <192>;
106 - arm,msi-num-spis = <32>;
108 - gic_v2m2: v2m@2a0000 {
109 - compatible = "arm,gic-v2m-frame";
111 - reg = <0x2a0000 0x1000>;
112 - arm,msi-base-spi = <224>;
113 - arm,msi-num-spis = <32>;
115 - gic_v2m3: v2m@2b0000 {
116 - compatible = "arm,gic-v2m-frame";
118 - reg = <0x2b0000 0x1000>;
119 - arm,msi-base-spi = <256>;
120 - arm,msi-num-spis = <32>;
125 - compatible = "arm,armv8-timer";
126 - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
127 - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
128 - <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
129 - <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
133 - compatible = "arm,cortex-a72-pmu";
134 - interrupt-parent = <&pic>;
138 - odmi: odmi@300000 {
139 - compatible = "marvell,odmi-controller";
140 - interrupt-controller;
142 - marvell,odmi-frames = <4>;
143 - reg = <0x300000 0x4000>,
147 - marvell,spi-base = <128>, <136>, <144>, <152>;
150 - gicp: gicp@3f0040 {
151 - compatible = "marvell,ap806-gicp";
152 - reg = <0x3f0040 0x10>;
153 - marvell,spi-ranges = <64 64>, <288 64>;
157 - pic: interrupt-controller@3f0100 {
158 - compatible = "marvell,armada-8k-pic";
159 - reg = <0x3f0100 0x10>;
160 - #interrupt-cells = <1>;
161 - interrupt-controller;
162 - interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
165 - sei: interrupt-controller@3f0200 {
166 - compatible = "marvell,ap806-sei";
167 - reg = <0x3f0200 0x40>;
168 - interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
169 - #interrupt-cells = <1>;
170 - interrupt-controller;
175 - compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
176 - reg = <0x400000 0x1000>,
178 - msi-parent = <&gic_v2m0>;
179 - clocks = <&ap_clk 3>;
184 - compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
185 - reg = <0x420000 0x1000>,
187 - msi-parent = <&gic_v2m0>;
188 - clocks = <&ap_clk 3>;
193 - compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
194 - reg = <0x440000 0x1000>,
196 - msi-parent = <&gic_v2m0>;
197 - clocks = <&ap_clk 3>;
202 - compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
203 - reg = <0x460000 0x1000>,
205 - msi-parent = <&gic_v2m0>;
206 - clocks = <&ap_clk 3>;
211 - compatible = "marvell,armada-380-spi";
212 - reg = <0x510600 0x50>;
213 - #address-cells = <1>;
215 - interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
216 - clocks = <&ap_clk 3>;
217 - status = "disabled";
221 - compatible = "marvell,mv78230-i2c";
222 - reg = <0x511000 0x20>;
223 - #address-cells = <1>;
225 - interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
226 - timeout-ms = <1000>;
227 - clocks = <&ap_clk 3>;
228 - status = "disabled";
231 - uart0: serial@512000 {
232 - compatible = "snps,dw-apb-uart";
233 - reg = <0x512000 0x100>;
235 - interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
236 - reg-io-width = <1>;
237 - clocks = <&ap_clk 3>;
238 - status = "disabled";
241 - uart1: serial@512100 {
242 - compatible = "snps,dw-apb-uart";
243 - reg = <0x512100 0x100>;
245 - interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
246 - reg-io-width = <1>;
247 - clocks = <&ap_clk 3>;
248 - status = "disabled";
252 - watchdog: watchdog@610000 {
253 - compatible = "arm,sbsa-gwdt";
254 - reg = <0x610000 0x1000>, <0x600000 0x1000>;
255 - interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
258 - ap_sdhci0: sdhci@6e0000 {
259 - compatible = "marvell,armada-ap806-sdhci";
260 - reg = <0x6e0000 0x300>;
261 - interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
262 - clock-names = "core";
263 - clocks = <&ap_clk 4>;
265 - marvell,xenon-phy-slow-mode;
266 - status = "disabled";
269 - ap_syscon0: system-controller@6f4000 {
270 - compatible = "syscon", "simple-mfd";
271 - reg = <0x6f4000 0x2000>;
274 - compatible = "marvell,ap806-clock";
275 - #clock-cells = <1>;
278 - ap_pinctrl: pinctrl {
279 - compatible = "marvell,ap806-pinctrl";
281 - uart0_pins: uart0-pins {
282 - marvell,pins = "mpp11", "mpp19";
283 - marvell,function = "uart0";
287 - ap_gpio: gpio@1040 {
288 - compatible = "marvell,armada-8k-gpio";
293 - gpio-ranges = <&ap_pinctrl 0 0 20>;
297 - ap_syscon1: system-controller@6f8000 {
298 - compatible = "syscon", "simple-mfd";
299 - reg = <0x6f8000 0x1000>;
300 - #address-cells = <1>;
303 - cpu_clk: clock-cpu@278 {
304 - compatible = "marvell,ap806-cpu-clock";
305 - clocks = <&ap_clk 0>, <&ap_clk 1>;
306 - #clock-cells = <1>;
307 - reg = <0x278 0xa30>;
310 - ap_thermal: thermal-sensor@80 {
311 - compatible = "marvell,armada-ap806-thermal";
313 - interrupt-parent = <&sei>;
315 - #thermal-sensor-cells = <1>;
322 - * The thermal IP features one internal sensor plus, if applicable, one
323 - * remote channel wired to one sensor per CPU.
325 - * Only one thermal zone per AP/CP may trigger interrupts at a time, the
326 - * first one that will have a critical trip point will be chosen.
329 - ap_thermal_ic: ap-thermal-ic {
330 - polling-delay-passive = <0>; /* Interrupt driven */
331 - polling-delay = <0>; /* Interrupt driven */
333 - thermal-sensors = <&ap_thermal 0>;
337 - temperature = <100000>; /* mC degrees */
338 - hysteresis = <2000>; /* mC degrees */
346 - ap_thermal_cpu0: ap-thermal-cpu0 {
347 - polling-delay-passive = <1000>;
348 - polling-delay = <1000>;
350 - thermal-sensors = <&ap_thermal 1>;
353 - cpu0_hot: cpu0-hot {
354 - temperature = <85000>;
355 - hysteresis = <2000>;
358 - cpu0_emerg: cpu0-emerg {
359 - temperature = <95000>;
360 - hysteresis = <2000>;
366 - map0_hot: map0-hot {
367 - trip = <&cpu0_hot>;
368 - cooling-device = <&cpu0 1 2>,
371 - map0_emerg: map0-ermerg {
372 - trip = <&cpu0_emerg>;
373 - cooling-device = <&cpu0 3 3>,
379 - ap_thermal_cpu1: ap-thermal-cpu1 {
380 - polling-delay-passive = <1000>;
381 - polling-delay = <1000>;
383 - thermal-sensors = <&ap_thermal 2>;
386 - cpu1_hot: cpu1-hot {
387 - temperature = <85000>;
388 - hysteresis = <2000>;
391 - cpu1_emerg: cpu1-emerg {
392 - temperature = <95000>;
393 - hysteresis = <2000>;
399 - map1_hot: map1-hot {
400 - trip = <&cpu1_hot>;
401 - cooling-device = <&cpu0 1 2>,
404 - map1_emerg: map1-emerg {
405 - trip = <&cpu1_emerg>;
406 - cooling-device = <&cpu0 3 3>,
412 - ap_thermal_cpu2: ap-thermal-cpu2 {
413 - polling-delay-passive = <1000>;
414 - polling-delay = <1000>;
416 - thermal-sensors = <&ap_thermal 3>;
419 - cpu2_hot: cpu2-hot {
420 - temperature = <85000>;
421 - hysteresis = <2000>;
424 - cpu2_emerg: cpu2-emerg {
425 - temperature = <95000>;
426 - hysteresis = <2000>;
432 - map2_hot: map2-hot {
433 - trip = <&cpu2_hot>;
434 - cooling-device = <&cpu2 1 2>,
437 - map2_emerg: map2-emerg {
438 - trip = <&cpu2_emerg>;
439 - cooling-device = <&cpu2 3 3>,
445 - ap_thermal_cpu3: ap-thermal-cpu3 {
446 - polling-delay-passive = <1000>;
447 - polling-delay = <1000>;
449 - thermal-sensors = <&ap_thermal 4>;
452 - cpu3_hot: cpu3-hot {
453 - temperature = <85000>;
454 - hysteresis = <2000>;
457 - cpu3_emerg: cpu3-emerg {
458 - temperature = <95000>;
459 - hysteresis = <2000>;
465 - map3_hot: map3-bhot {
466 - trip = <&cpu3_hot>;
467 - cooling-device = <&cpu2 1 2>,
470 - map3_emerg: map3-emerg {
471 - trip = <&cpu3_emerg>;
472 - cooling-device = <&cpu2 3 3>,
480 +++ b/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi
482 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
484 + * Copyright (C) 2019 Marvell Technology Group Ltd.
486 + * Device Tree file for Marvell Armada AP80x.
489 +#include <dt-bindings/interrupt-controller/arm-gic.h>
490 +#include <dt-bindings/thermal/thermal.h>
495 + #address-cells = <2>;
506 + compatible = "arm,psci-0.2";
511 + #address-cells = <2>;
516 + * This area matches the mapping done with a
517 + * mainline U-Boot, and should be updated by the
521 + psci-area@4000000 {
522 + reg = <0x0 0x4000000 0x0 0x200000>;
528 + #address-cells = <2>;
530 + compatible = "simple-bus";
531 + interrupt-parent = <&gic>;
534 + config-space@f0000000 {
535 + #address-cells = <1>;
537 + compatible = "simple-bus";
538 + ranges = <0x0 0x0 0xf0000000 0x1000000>;
540 + gic: interrupt-controller@210000 {
541 + compatible = "arm,gic-400";
542 + #interrupt-cells = <3>;
543 + #address-cells = <1>;
546 + interrupt-controller;
547 + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
548 + reg = <0x210000 0x10000>,
549 + <0x220000 0x20000>,
550 + <0x240000 0x20000>,
551 + <0x260000 0x20000>;
553 + gic_v2m0: v2m@280000 {
554 + compatible = "arm,gic-v2m-frame";
556 + reg = <0x280000 0x1000>;
557 + arm,msi-base-spi = <160>;
558 + arm,msi-num-spis = <32>;
560 + gic_v2m1: v2m@290000 {
561 + compatible = "arm,gic-v2m-frame";
563 + reg = <0x290000 0x1000>;
564 + arm,msi-base-spi = <192>;
565 + arm,msi-num-spis = <32>;
567 + gic_v2m2: v2m@2a0000 {
568 + compatible = "arm,gic-v2m-frame";
570 + reg = <0x2a0000 0x1000>;
571 + arm,msi-base-spi = <224>;
572 + arm,msi-num-spis = <32>;
574 + gic_v2m3: v2m@2b0000 {
575 + compatible = "arm,gic-v2m-frame";
577 + reg = <0x2b0000 0x1000>;
578 + arm,msi-base-spi = <256>;
579 + arm,msi-num-spis = <32>;
584 + compatible = "arm,armv8-timer";
585 + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
586 + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
587 + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
588 + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
592 + compatible = "arm,cortex-a72-pmu";
593 + interrupt-parent = <&pic>;
597 + odmi: odmi@300000 {
598 + compatible = "marvell,odmi-controller";
599 + interrupt-controller;
601 + marvell,odmi-frames = <4>;
602 + reg = <0x300000 0x4000>,
606 + marvell,spi-base = <128>, <136>, <144>, <152>;
609 + gicp: gicp@3f0040 {
610 + compatible = "marvell,ap806-gicp";
611 + reg = <0x3f0040 0x10>;
612 + marvell,spi-ranges = <64 64>, <288 64>;
616 + pic: interrupt-controller@3f0100 {
617 + compatible = "marvell,armada-8k-pic";
618 + reg = <0x3f0100 0x10>;
619 + #interrupt-cells = <1>;
620 + interrupt-controller;
621 + interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
624 + sei: interrupt-controller@3f0200 {
625 + compatible = "marvell,ap806-sei";
626 + reg = <0x3f0200 0x40>;
627 + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
628 + #interrupt-cells = <1>;
629 + interrupt-controller;
634 + compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
635 + reg = <0x400000 0x1000>,
637 + msi-parent = <&gic_v2m0>;
638 + clocks = <&ap_clk 3>;
643 + compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
644 + reg = <0x420000 0x1000>,
646 + msi-parent = <&gic_v2m0>;
647 + clocks = <&ap_clk 3>;
652 + compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
653 + reg = <0x440000 0x1000>,
655 + msi-parent = <&gic_v2m0>;
656 + clocks = <&ap_clk 3>;
661 + compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
662 + reg = <0x460000 0x1000>,
664 + msi-parent = <&gic_v2m0>;
665 + clocks = <&ap_clk 3>;
670 + compatible = "marvell,armada-380-spi";
671 + reg = <0x510600 0x50>;
672 + #address-cells = <1>;
674 + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
675 + clocks = <&ap_clk 3>;
676 + status = "disabled";
680 + compatible = "marvell,mv78230-i2c";
681 + reg = <0x511000 0x20>;
682 + #address-cells = <1>;
684 + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
685 + timeout-ms = <1000>;
686 + clocks = <&ap_clk 3>;
687 + status = "disabled";
690 + uart0: serial@512000 {
691 + compatible = "snps,dw-apb-uart";
692 + reg = <0x512000 0x100>;
694 + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
695 + reg-io-width = <1>;
696 + clocks = <&ap_clk 3>;
697 + status = "disabled";
700 + uart1: serial@512100 {
701 + compatible = "snps,dw-apb-uart";
702 + reg = <0x512100 0x100>;
704 + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
705 + reg-io-width = <1>;
706 + clocks = <&ap_clk 3>;
707 + status = "disabled";
711 + watchdog: watchdog@610000 {
712 + compatible = "arm,sbsa-gwdt";
713 + reg = <0x610000 0x1000>, <0x600000 0x1000>;
714 + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
717 + ap_sdhci0: sdhci@6e0000 {
718 + compatible = "marvell,armada-ap806-sdhci";
719 + reg = <0x6e0000 0x300>;
720 + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
721 + clock-names = "core";
722 + clocks = <&ap_clk 4>;
724 + marvell,xenon-phy-slow-mode;
725 + status = "disabled";
728 + ap_syscon0: system-controller@6f4000 {
729 + compatible = "syscon", "simple-mfd";
730 + reg = <0x6f4000 0x2000>;
733 + compatible = "marvell,ap806-clock";
734 + #clock-cells = <1>;
737 + ap_pinctrl: pinctrl {
738 + compatible = "marvell,ap806-pinctrl";
740 + uart0_pins: uart0-pins {
741 + marvell,pins = "mpp11", "mpp19";
742 + marvell,function = "uart0";
746 + ap_gpio: gpio@1040 {
747 + compatible = "marvell,armada-8k-gpio";
752 + gpio-ranges = <&ap_pinctrl 0 0 20>;
756 + ap_syscon1: system-controller@6f8000 {
757 + compatible = "syscon", "simple-mfd";
758 + reg = <0x6f8000 0x1000>;
759 + #address-cells = <1>;
762 + cpu_clk: clock-cpu@278 {
763 + compatible = "marvell,ap806-cpu-clock";
764 + clocks = <&ap_clk 0>, <&ap_clk 1>;
765 + #clock-cells = <1>;
766 + reg = <0x278 0xa30>;
769 + ap_thermal: thermal-sensor@80 {
770 + compatible = "marvell,armada-ap806-thermal";
772 + interrupt-parent = <&sei>;
774 + #thermal-sensor-cells = <1>;
781 + * The thermal IP features one internal sensor plus, if applicable, one
782 + * remote channel wired to one sensor per CPU.
784 + * Only one thermal zone per AP/CP may trigger interrupts at a time, the
785 + * first one that will have a critical trip point will be chosen.
788 + ap_thermal_ic: ap-thermal-ic {
789 + polling-delay-passive = <0>; /* Interrupt driven */
790 + polling-delay = <0>; /* Interrupt driven */
792 + thermal-sensors = <&ap_thermal 0>;
796 + temperature = <100000>; /* mC degrees */
797 + hysteresis = <2000>; /* mC degrees */
805 + ap_thermal_cpu0: ap-thermal-cpu0 {
806 + polling-delay-passive = <1000>;
807 + polling-delay = <1000>;
809 + thermal-sensors = <&ap_thermal 1>;
812 + cpu0_hot: cpu0-hot {
813 + temperature = <85000>;
814 + hysteresis = <2000>;
817 + cpu0_emerg: cpu0-emerg {
818 + temperature = <95000>;
819 + hysteresis = <2000>;
825 + map0_hot: map0-hot {
826 + trip = <&cpu0_hot>;
827 + cooling-device = <&cpu0 1 2>,
830 + map0_emerg: map0-ermerg {
831 + trip = <&cpu0_emerg>;
832 + cooling-device = <&cpu0 3 3>,
838 + ap_thermal_cpu1: ap-thermal-cpu1 {
839 + polling-delay-passive = <1000>;
840 + polling-delay = <1000>;
842 + thermal-sensors = <&ap_thermal 2>;
845 + cpu1_hot: cpu1-hot {
846 + temperature = <85000>;
847 + hysteresis = <2000>;
850 + cpu1_emerg: cpu1-emerg {
851 + temperature = <95000>;
852 + hysteresis = <2000>;
858 + map1_hot: map1-hot {
859 + trip = <&cpu1_hot>;
860 + cooling-device = <&cpu0 1 2>,
863 + map1_emerg: map1-emerg {
864 + trip = <&cpu1_emerg>;
865 + cooling-device = <&cpu0 3 3>,
871 + ap_thermal_cpu2: ap-thermal-cpu2 {
872 + polling-delay-passive = <1000>;
873 + polling-delay = <1000>;
875 + thermal-sensors = <&ap_thermal 3>;
878 + cpu2_hot: cpu2-hot {
879 + temperature = <85000>;
880 + hysteresis = <2000>;
883 + cpu2_emerg: cpu2-emerg {
884 + temperature = <95000>;
885 + hysteresis = <2000>;
891 + map2_hot: map2-hot {
892 + trip = <&cpu2_hot>;
893 + cooling-device = <&cpu2 1 2>,
896 + map2_emerg: map2-emerg {
897 + trip = <&cpu2_emerg>;
898 + cooling-device = <&cpu2 3 3>,
904 + ap_thermal_cpu3: ap-thermal-cpu3 {
905 + polling-delay-passive = <1000>;
906 + polling-delay = <1000>;
908 + thermal-sensors = <&ap_thermal 4>;
911 + cpu3_hot: cpu3-hot {
912 + temperature = <85000>;
913 + hysteresis = <2000>;
916 + cpu3_emerg: cpu3-emerg {
917 + temperature = <95000>;
918 + hysteresis = <2000>;
924 + map3_hot: map3-bhot {
925 + trip = <&cpu3_hot>;
926 + cooling-device = <&cpu2 1 2>,
929 + map3_emerg: map3-emerg {
930 + trip = <&cpu3_emerg>;
931 + cooling-device = <&cpu2 3 3>,