target/linux/octeon/patches-3.10/130-gpio.patch

   1 Index: linux-3.10.49/drivers/gpio/Kconfig
   2 ===================================================================
   3 --- linux-3.10.49.orig/drivers/gpio/Kconfig     2014-07-18 00:58:15.000000000 +0200
   4 +++ linux-3.10.49/drivers/gpio/Kconfig  2014-08-07 11:41:16.517169817 +0200
   5 @@ -171,6 +171,14 @@
   6           Qualcomm MSM chips.  Most of the pins on the MSM can be
   7           selected for GPIO, and are controlled by this driver.
   8
   9 +config GPIO_OCTEON
  10 +       tristate "Cavium OCTEON GPIO"
  11 +       depends on GPIOLIB && CPU_CAVIUM_OCTEON
  12 +       default y
  13 +       help
  14 +         Say yes here to support the on-chip GPIO lines on the OCTEON
  15 +         family of SOCs.
  16 +
  17  config GPIO_MVEBU
  18         def_bool y
  19         depends on PLAT_ORION
  20 Index: linux-3.10.49/drivers/gpio/Makefile
  21 ===================================================================
  22 --- linux-3.10.49.orig/drivers/gpio/Makefile    2014-07-18 00:58:15.000000000 +0200
  23 +++ linux-3.10.49/drivers/gpio/Makefile 2014-08-07 11:41:16.517169817 +0200
  24 @@ -10,6 +10,7 @@
  25  # Device drivers. Generally keep list sorted alphabetically
  26  obj-$(CONFIG_GPIO_GENERIC)     += gpio-generic.o
  27
  28 +obj-$(CONFIG_GPIO_OCTEON)      += gpio-octeon.o
  29  obj-$(CONFIG_GPIO_74X164)      += gpio-74x164.o
  30  obj-$(CONFIG_GPIO_ADNP)                += gpio-adnp.o
  31  obj-$(CONFIG_GPIO_ADP5520)     += gpio-adp5520.o
  32 Index: linux-3.10.49/drivers/gpio/gpio-octeon.c
  33 ===================================================================
  34 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
  35 +++ linux-3.10.49/drivers/gpio/gpio-octeon.c    2014-08-07 11:53:14.733161106 +0200
  36 @@ -0,0 +1,166 @@
  37 +/*
  38 + * This file is subject to the terms and conditions of the GNU General Public
  39 + * License.  See the file "COPYING" in the main directory of this archive
  40 + * for more details.
  41 + *
  42 + * Copyright (C) 2011,2012 Cavium Inc.
  43 + */
  44 +
  45 +#include <linux/platform_device.h>
  46 +#include <linux/kernel.h>
  47 +#include <linux/module.h>
  48 +#include <linux/gpio.h>
  49 +#include <linux/io.h>
  50 +
  51 +#include <asm/octeon/octeon.h>
  52 +#include <asm/octeon/cvmx-gpio-defs.h>
  53 +
  54 +#define DRV_VERSION "1.0"
  55 +#define DRV_DESCRIPTION "Cavium Inc. OCTEON GPIO Driver"
  56 +
  57 +#define RX_DAT 0x80
  58 +#define TX_SET 0x88
  59 +#define TX_CLEAR 0x90
  60 +
  61 +int gpio_to_irq(unsigned gpio)
  62 +{
  63 +       return -EINVAL;
  64 +}
  65 +EXPORT_SYMBOL(gpio_to_irq);
  66 +
  67 +/*
  68 + * The address offset of the GPIO configuration register for a given
  69 + * line.
  70 + */
  71 +static unsigned int bit_cfg_reg(unsigned int gpio)
  72 +{
  73 +       if (gpio < 16)
  74 +               return 8 * gpio;
  75 +       else
  76 +               return 8 * (gpio - 16) + 0x100;
  77 +}
  78 +
  79 +struct octeon_gpio {
  80 +       struct gpio_chip chip;
  81 +       u64 register_base;
  82 +};
  83 +
  84 +static int octeon_gpio_dir_in(struct gpio_chip *chip, unsigned offset)
  85 +{
  86 +       struct octeon_gpio *gpio = container_of(chip, struct octeon_gpio, chip);
  87 +
  88 +       cvmx_write_csr(gpio->register_base + bit_cfg_reg(offset), 0);
  89 +       return 0;
  90 +}
  91 +
  92 +static void octeon_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
  93 +{
  94 +       struct octeon_gpio *gpio = container_of(chip, struct octeon_gpio, chip);
  95 +       u64 mask = 1ull << offset;
  96 +       u64 reg = gpio->register_base + (value ? TX_SET : TX_CLEAR);
  97 +       cvmx_write_csr(reg, mask);
  98 +}
  99 +
 100 +static int octeon_gpio_dir_out(struct gpio_chip *chip, unsigned offset,
 101 +                              int value)
 102 +{
 103 +       struct octeon_gpio *gpio = container_of(chip, struct octeon_gpio, chip);
 104 +       union cvmx_gpio_bit_cfgx cfgx;
 105 +
 106 +
 107 +       octeon_gpio_set(chip, offset, value);
 108 +
 109 +       cfgx.u64 = 0;
 110 +       cfgx.s.tx_oe = 1;
 111 +
 112 +       cvmx_write_csr(gpio->register_base + bit_cfg_reg(offset), cfgx.u64);
 113 +       return 0;
 114 +}
 115 +
 116 +static int octeon_gpio_get(struct gpio_chip *chip, unsigned offset)
 117 +{
 118 +       struct octeon_gpio *gpio = container_of(chip, struct octeon_gpio, chip);
 119 +       u64 read_bits = cvmx_read_csr(gpio->register_base + RX_DAT);
 120 +
 121 +       return ((1ull << offset) & read_bits) != 0;
 122 +}
 123 +
 124 +static int octeon_gpio_probe(struct platform_device *pdev)
 125 +{
 126 +       struct octeon_gpio *gpio;
 127 +       struct gpio_chip *chip;
 128 +       struct resource *res_mem;
 129 +       int err = 0;
 130 +
 131 +       gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
 132 +       if (!gpio)
 133 +               return -ENOMEM;
 134 +       chip = &gpio->chip;
 135 +
 136 +       res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 137 +       if (res_mem == NULL) {
 138 +               dev_err(&pdev->dev, "found no memory resource\n");
 139 +               err = -ENXIO;
 140 +               goto out;
 141 +       }
 142 +       if (!devm_request_mem_region(&pdev->dev, res_mem->start,
 143 +                                       resource_size(res_mem),
 144 +                                    res_mem->name)) {
 145 +               dev_err(&pdev->dev, "request_mem_region failed\n");
 146 +               err = -ENXIO;
 147 +               goto out;
 148 +       }
 149 +       gpio->register_base = (u64)devm_ioremap(&pdev->dev, res_mem->start,
 150 +                                               resource_size(res_mem));
 151 +
 152 +
 153 +       pdev->dev.platform_data = chip;
 154 +       chip->label = "octeon-gpio";
 155 +       chip->dev = &pdev->dev;
 156 +       chip->owner = THIS_MODULE;
 157 +       chip->base = 0;
 158 +       chip->can_sleep = 0;
 159 +       chip->ngpio = 20;
 160 +       chip->direction_input = octeon_gpio_dir_in;
 161 +       chip->get = octeon_gpio_get;
 162 +       chip->direction_output = octeon_gpio_dir_out;
 163 +       chip->set = octeon_gpio_set;
 164 +       err = gpiochip_add(chip);
 165 +       if (err)
 166 +               goto out;
 167 +
 168 +       dev_info(&pdev->dev, "version: " DRV_VERSION "\n");
 169 +out:
 170 +       return err;
 171 +}
 172 +
 173 +static int octeon_gpio_remove(struct platform_device *pdev)
 174 +{
 175 +       struct gpio_chip *chip = pdev->dev.platform_data;
 176 +       return gpiochip_remove(chip);
 177 +}
 178 +
 179 +static struct of_device_id octeon_gpio_match[] = {
 180 +       {
 181 +               .compatible = "cavium,octeon-3860-gpio",
 182 +       },
 183 +       {},
 184 +};
 185 +MODULE_DEVICE_TABLE(of, octeon_gpio_match);
 186 +
 187 +static struct platform_driver octeon_gpio_driver = {
 188 +       .probe          = octeon_gpio_probe,
 189 +       .remove         = octeon_gpio_remove,
 190 +       .driver = {
 191 +               .name           = "octeon_gpio",
 192 +               .owner          = THIS_MODULE,
 193 +               .of_match_table = octeon_gpio_match,
 194 +       },
 195 +};
 196 +
 197 +module_platform_driver(octeon_gpio_driver);
 198 +
 199 +MODULE_DESCRIPTION(DRV_DESCRIPTION);
 200 +MODULE_AUTHOR("David Daney");
 201 +MODULE_LICENSE("GPL");
 202 +MODULE_VERSION(DRV_VERSION);
 203 Index: linux-3.10.49/arch/mips/Kconfig
 204 ===================================================================
 205 --- linux-3.10.49.orig/arch/mips/Kconfig        2014-08-07 11:41:14.809169838 +0200
 206 +++ linux-3.10.49/arch/mips/Kconfig     2014-08-07 11:41:16.521169817 +0200
 207 @@ -769,6 +769,7 @@
 208         select USB_ARCH_HAS_OHCI
 209         select USB_ARCH_HAS_EHCI
 210         select HOLES_IN_ZONE
 211 +       select ARCH_REQUIRE_GPIOLIB
 212         help
 213           This option supports all of the Octeon reference boards from Cavium
 214           Networks. It builds a kernel that dynamically determines the Octeon