1 From b1e7791e688620c9bb8476ac2d0bc99abeb7f825 Mon Sep 17 00:00:00 2001
2 From: Tim Harvey <tharvey@gateworks.com>
3 Date: Fri, 29 Dec 2017 16:48:04 -0800
4 Subject: [PATCH] net: thunderx: workaround BGX TX Underflow issue
6 While it is not yet understood why a TX underflow can easily occur
7 for SGMII interfaces resulting in a TX wedge. It has been found that
8 disabling/re-enabling the LMAC resolves the issue.
10 Signed-off-by: Tim Harvey <tharvey@gateworks.com>
12 drivers/net/ethernet/cavium/thunder/thunder_bgx.c | 54 +++++++++++++++++++++++
13 drivers/net/ethernet/cavium/thunder/thunder_bgx.h | 9 ++++
14 2 files changed, 63 insertions(+)
16 diff --git a/drivers/net/ethernet/cavium/thunder/thunder_bgx.c b/drivers/net/ethernet/cavium/thunder/thunder_bgx.c
17 index 805c02a..0690966 100644
18 --- a/drivers/net/ethernet/cavium/thunder/thunder_bgx.c
19 +++ b/drivers/net/ethernet/cavium/thunder/thunder_bgx.c
20 @@ -1344,6 +1344,54 @@ static int bgx_init_phy(struct bgx *bgx)
21 return bgx_init_of_phy(bgx);
24 +static irqreturn_t bgx_intr_handler(int irq, void *data)
26 + struct bgx *bgx = (struct bgx *)data;
27 + struct device *dev = &bgx->pdev->dev;
31 + for (lmac = 0; lmac < bgx->lmac_count; lmac++) {
32 + status = bgx_reg_read(bgx, lmac, BGX_GMP_GMI_TXX_INT);
33 + if (status & GMI_TXX_INT_UNDFLW) {
34 + dev_err(dev, "BGX%d lmac%d UNDFLW\n", bgx->bgx_id,
36 + val = bgx_reg_read(bgx, lmac, BGX_CMRX_CFG);
38 + bgx_reg_write(bgx, lmac, BGX_CMRX_CFG, val);
40 + bgx_reg_write(bgx, lmac, BGX_CMRX_CFG, val);
42 + /* clear interrupts */
43 + bgx_reg_write(bgx, lmac, BGX_GMP_GMI_TXX_INT, status);
49 +static int bgx_register_intr(struct pci_dev *pdev)
51 + struct bgx *bgx = pci_get_drvdata(pdev);
52 + struct device *dev = &pdev->dev;
57 + num_vec = pci_msix_vec_count(pdev);
58 + ret = pci_alloc_irq_vectors(pdev, num_vec, num_vec, PCI_IRQ_MSIX);
60 + dev_err(dev, "Req for #%d msix vectors failed\n", num_vec);
63 + sprintf(irq_name, "BGX%d", bgx->bgx_id);
64 + ret = request_irq(pci_irq_vector(pdev, GMPX_GMI_TX_INT),
65 + bgx_intr_handler, 0, irq_name, bgx);
72 static int bgx_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
75 @@ -1414,6 +1462,8 @@ static int bgx_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
76 xcv_init_hw(bgx->phy_mode);
79 + bgx_register_intr(pdev);
81 /* Enable all LMACs */
82 for (lmac = 0; lmac < bgx->lmac_count; lmac++) {
83 err = bgx_lmac_enable(bgx, lmac);
84 @@ -1424,6 +1474,10 @@ static int bgx_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
85 bgx_lmac_disable(bgx, --lmac);
89 + /* enable TX FIFO Underflow interrupt */
90 + bgx_reg_modify(bgx, lmac, BGX_GMP_GMI_TXX_INT_ENA_W1S,
91 + GMI_TXX_INT_UNDFLW);
95 diff --git a/drivers/net/ethernet/cavium/thunder/thunder_bgx.h b/drivers/net/ethernet/cavium/thunder/thunder_bgx.h
96 index 2bba9d1..be9148f9 100644
97 --- a/drivers/net/ethernet/cavium/thunder/thunder_bgx.h
98 +++ b/drivers/net/ethernet/cavium/thunder/thunder_bgx.h
100 #define BGX_GMP_GMI_TXX_BURST 0x38228
101 #define BGX_GMP_GMI_TXX_MIN_PKT 0x38240
102 #define BGX_GMP_GMI_TXX_SGMII_CTL 0x38300
103 +#define BGX_GMP_GMI_TXX_INT 0x38500
104 +#define BGX_GMP_GMI_TXX_INT_W1S 0x38508
105 +#define BGX_GMP_GMI_TXX_INT_ENA_W1C 0x38510
106 +#define BGX_GMP_GMI_TXX_INT_ENA_W1S 0x38518
107 +#define GMI_TXX_INT_PTP_LOST BIT_ULL(4)
108 +#define GMI_TXX_INT_LATE_COL BIT_ULL(3)
109 +#define GMI_TXX_INT_XSDEF BIT_ULL(2)
110 +#define GMI_TXX_INT_XSCOL BIT_ULL(1)
111 +#define GMI_TXX_INT_UNDFLW BIT_ULL(0)
113 #define BGX_MSIX_VEC_0_29_ADDR 0x400000 /* +(0..29) << 4 */
114 #define BGX_MSIX_VEC_0_29_CTL 0x400008