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ar71xx: add profile for the WR842N/ND v2
[openwrt/staging/wigyori.git] / target / linux / omap / patches-3.12 / 001-ti_git.patch
1 --- a/arch/arm/boot/dts/am335x-boneblack.dts
2 +++ b/arch/arm/boot/dts/am335x-boneblack.dts
3 @@ -15,3 +15,80 @@
4 regulator-max-microvolt = <1800000>;
5 regulator-always-on;
6 };
7 +
8 +&mmc1 {
9 + vmmc-supply = <&vmmcsd_fixed>;
10 +};
11 +
12 +&mmc2 {
13 + vmmc-supply = <&vmmcsd_fixed>;
14 + pinctrl-names = "default";
15 + pinctrl-0 = <&emmc_pins>;
16 + bus-width = <8>;
17 + ti,non-removable;
18 + status = "okay";
19 +};
20 +
21 +&am33xx_pinmux {
22 + nxp_hdmi_bonelt_pins: nxp_hdmi_bonelt_pins {
23 + pinctrl-single,pins = <
24 + 0x1b0 0x03 /* xdma_event_intr0, OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT */
25 + 0xa0 0x08 /* lcd_data0.lcd_data0, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
26 + 0xa4 0x08 /* lcd_data1.lcd_data1, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
27 + 0xa8 0x08 /* lcd_data2.lcd_data2, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
28 + 0xac 0x08 /* lcd_data3.lcd_data3, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
29 + 0xb0 0x08 /* lcd_data4.lcd_data4, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
30 + 0xb4 0x08 /* lcd_data5.lcd_data5, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
31 + 0xb8 0x08 /* lcd_data6.lcd_data6, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
32 + 0xbc 0x08 /* lcd_data7.lcd_data7, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
33 + 0xc0 0x08 /* lcd_data8.lcd_data8, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
34 + 0xc4 0x08 /* lcd_data9.lcd_data9, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
35 + 0xc8 0x08 /* lcd_data10.lcd_data10, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
36 + 0xcc 0x08 /* lcd_data11.lcd_data11, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
37 + 0xd0 0x08 /* lcd_data12.lcd_data12, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
38 + 0xd4 0x08 /* lcd_data13.lcd_data13, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
39 + 0xd8 0x08 /* lcd_data14.lcd_data14, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
40 + 0xdc 0x08 /* lcd_data15.lcd_data15, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
41 + 0xe0 0x00 /* lcd_vsync.lcd_vsync, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */
42 + 0xe4 0x00 /* lcd_hsync.lcd_hsync, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */
43 + 0xe8 0x00 /* lcd_pclk.lcd_pclk, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */
44 + 0xec 0x00 /* lcd_ac_bias_en.lcd_ac_bias_en, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */
45 + >;
46 + };
47 + nxp_hdmi_bonelt_off_pins: nxp_hdmi_bonelt_off_pins {
48 + pinctrl-single,pins = <
49 + 0x1b0 0x03 /* xdma_event_intr0, OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT */
50 + >;
51 + };
52 +};
53 +
54 +&i2c0 {
55 + hdmi1: hdmi@70 {
56 + compatible = "nxp,tda998x";
57 + reg = <0x70>;
58 + };
59 +};
60 +
61 +&lcdc {
62 + pinctrl-names = "default", "off";
63 + pinctrl-0 = <&nxp_hdmi_bonelt_pins>;
64 + pinctrl-1 = <&nxp_hdmi_bonelt_off_pins>;
65 + status = "okay";
66 + hdmi = <&hdmi1>;
67 + display-timings {
68 + 640x480P60 {
69 + clock-frequency = <25200000>;
70 + hactive = <640>;
71 + vactive = <480>;
72 + hfront-porch = <16>;
73 + hback-porch = <48>;
74 + hsync-len = <96>;
75 + vback-porch = <31>;
76 + vfront-porch = <11>;
77 + vsync-len = <2>;
78 + hsync-active = <0>;
79 + vsync-active = <0>;
80 + };
81 + };
82 +};
83 +
84 --- a/arch/arm/boot/dts/am335x-bone-common.dtsi
85 +++ b/arch/arm/boot/dts/am335x-bone-common.dtsi
86 @@ -107,6 +107,27 @@
87 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
88 >;
89 };
90 +
91 + mmc1_pins: pinmux_mmc1_pins {
92 + pinctrl-single,pins = <
93 + 0x160 (PIN_INPUT | MUX_MODE7) /* GPIO0_6 */
94 + >;
95 + };
96 +
97 + emmc_pins: pinmux_emmc_pins {
98 + pinctrl-single,pins = <
99 + 0x80 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */
100 + 0x84 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
101 + 0x00 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
102 + 0x04 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
103 + 0x08 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
104 + 0x0c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
105 + 0x10 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */
106 + 0x14 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */
107 + 0x18 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */
108 + 0x1c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */
109 + >;
110 + };
111 };
112
113 ocp {
114 @@ -183,15 +204,24 @@
115 led@4 {
116 label = "beaglebone:green:usr2";
117 gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>;
118 + linux,default-trigger = "cpu0";
119 default-state = "off";
120 };
121
122 led@5 {
123 label = "beaglebone:green:usr3";
124 gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>;
125 + linux,default-trigger = "mmc1";
126 default-state = "off";
127 };
128 };
129 +
130 + vmmcsd_fixed: fixedregulator@0 {
131 + compatible = "regulator-fixed";
132 + regulator-name = "vmmcsd_fixed";
133 + regulator-min-microvolt = <3300000>;
134 + regulator-max-microvolt = <3300000>;
135 + };
136 };
137
138 /include/ "tps65217.dtsi"
139 @@ -260,3 +290,12 @@
140 pinctrl-0 = <&davinci_mdio_default>;
141 pinctrl-1 = <&davinci_mdio_sleep>;
142 };
143 +
144 +&mmc1 {
145 + status = "okay";
146 + bus-width = <0x4>;
147 + pinctrl-names = "default";
148 + pinctrl-0 = <&mmc1_pins>;
149 + cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
150 + cd-inverted;
151 +};
152 --- a/arch/arm/boot/dts/am335x-bone.dts
153 +++ b/arch/arm/boot/dts/am335x-bone.dts
154 @@ -9,3 +9,13 @@
155
156 #include "am33xx.dtsi"
157 #include "am335x-bone-common.dtsi"
158 +
159 +&ldo3_reg {
160 + regulator-min-microvolt = <1800000>;
161 + regulator-max-microvolt = <3300000>;
162 + regulator-always-on;
163 +};
164 +
165 +&mmc1 {
166 + vmmc-supply = <&ldo3_reg>;
167 +};
168 --- a/arch/arm/boot/dts/am335x-evm.dts
169 +++ b/arch/arm/boot/dts/am335x-evm.dts
170 @@ -149,6 +149,54 @@
171 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
172 >;
173 };
174 +
175 + mmc1_pins: pinmux_mmc1_pins {
176 + pinctrl-single,pins = <
177 + 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
178 + >;
179 + };
180 +
181 + lcd_pins_s0: lcd_pins_s0 {
182 + pinctrl-single,pins = <
183 + 0x20 0x01 /* gpmc_ad8.lcd_data16, OUTPUT | MODE1 */
184 + 0x24 0x01 /* gpmc_ad9.lcd_data17, OUTPUT | MODE1 */
185 + 0x28 0x01 /* gpmc_ad10.lcd_data18, OUTPUT | MODE1 */
186 + 0x2c 0x01 /* gpmc_ad11.lcd_data19, OUTPUT | MODE1 */
187 + 0x30 0x01 /* gpmc_ad12.lcd_data20, OUTPUT | MODE1 */
188 + 0x34 0x01 /* gpmc_ad13.lcd_data21, OUTPUT | MODE1 */
189 + 0x38 0x01 /* gpmc_ad14.lcd_data22, OUTPUT | MODE1 */
190 + 0x3c 0x01 /* gpmc_ad15.lcd_data23, OUTPUT | MODE1 */
191 + 0xa0 0x00 /* lcd_data0.lcd_data0, OUTPUT | MODE0 */
192 + 0xa4 0x00 /* lcd_data1.lcd_data1, OUTPUT | MODE0 */
193 + 0xa8 0x00 /* lcd_data2.lcd_data2, OUTPUT | MODE0 */
194 + 0xac 0x00 /* lcd_data3.lcd_data3, OUTPUT | MODE0 */
195 + 0xb0 0x00 /* lcd_data4.lcd_data4, OUTPUT | MODE0 */
196 + 0xb4 0x00 /* lcd_data5.lcd_data5, OUTPUT | MODE0 */
197 + 0xb8 0x00 /* lcd_data6.lcd_data6, OUTPUT | MODE0 */
198 + 0xbc 0x00 /* lcd_data7.lcd_data7, OUTPUT | MODE0 */
199 + 0xc0 0x00 /* lcd_data8.lcd_data8, OUTPUT | MODE0 */
200 + 0xc4 0x00 /* lcd_data9.lcd_data9, OUTPUT | MODE0 */
201 + 0xc8 0x00 /* lcd_data10.lcd_data10, OUTPUT | MODE0 */
202 + 0xcc 0x00 /* lcd_data11.lcd_data11, OUTPUT | MODE0 */
203 + 0xd0 0x00 /* lcd_data12.lcd_data12, OUTPUT | MODE0 */
204 + 0xd4 0x00 /* lcd_data13.lcd_data13, OUTPUT | MODE0 */
205 + 0xd8 0x00 /* lcd_data14.lcd_data14, OUTPUT | MODE0 */
206 + 0xdc 0x00 /* lcd_data15.lcd_data15, OUTPUT | MODE0 */
207 + 0xe0 0x00 /* lcd_vsync.lcd_vsync, OUTPUT | MODE0 */
208 + 0xe4 0x00 /* lcd_hsync.lcd_hsync, OUTPUT | MODE0 */
209 + 0xe8 0x00 /* lcd_pclk.lcd_pclk, OUTPUT | MODE0 */
210 + 0xec 0x00 /* lcd_ac_bias_en.lcd_ac_bias_en, OUTPUT | MODE0 */
211 + >;
212 + };
213 +
214 + am335x_evm_audio_pins: am335x_evm_audio_pins {
215 + pinctrl-single,pins = <
216 + 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rx_dv.mcasp1_aclkx */
217 + 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_txd3.mcasp1_fsx */
218 + 0x108 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */
219 + 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
220 + >;
221 + };
222 };
223
224 ocp {
225 @@ -244,6 +292,18 @@
226 compatible = "ti,tmp275";
227 reg = <0x48>;
228 };
229 +
230 + tlv320aic3106: tlv320aic3106@1b {
231 + compatible = "ti,tlv320aic3106";
232 + reg = <0x1b>;
233 + status = "okay";
234 +
235 + /* Regulators */
236 + AVDD-supply = <&vaux2_reg>;
237 + IOVDD-supply = <&vaux2_reg>;
238 + DRVDD-supply = <&vaux2_reg>;
239 + DVDD-supply = <&vbat>;
240 + };
241 };
242
243 elm: elm@48080000 {
244 @@ -268,8 +328,7 @@
245 nand@0,0 {
246 reg = <0 0 0>; /* CS0, offset 0 */
247 nand-bus-width = <8>;
248 - ti,nand-ecc-opt = "bch8";
249 - gpmc,device-nand = "true";
250 + ti,nand-ecc-opt= "bch8";
251 gpmc,device-width = <1>;
252 gpmc,sync-clk-ps = <0>;
253 gpmc,cs-on-ns = <0>;
254 @@ -293,53 +352,78 @@
255 gpmc,wait-monitoring-ns = <0>;
256 gpmc,wr-access-ns = <40>;
257 gpmc,wr-data-mux-bus-ns = <0>;
258 -
259 #address-cells = <1>;
260 #size-cells = <1>;
261 - elm_id = <&elm>;
262 -
263 + ti,elm-id = <&elm>;
264 /* MTD partition table */
265 partition@0 {
266 label = "SPL1";
267 reg = <0x00000000 0x000020000>;
268 };
269 -
270 partition@1 {
271 label = "SPL2";
272 reg = <0x00020000 0x00020000>;
273 };
274 -
275 partition@2 {
276 label = "SPL3";
277 reg = <0x00040000 0x00020000>;
278 };
279 -
280 partition@3 {
281 label = "SPL4";
282 reg = <0x00060000 0x00020000>;
283 };
284 -
285 partition@4 {
286 label = "U-boot";
287 reg = <0x00080000 0x001e0000>;
288 };
289 -
290 partition@5 {
291 label = "environment";
292 reg = <0x00260000 0x00020000>;
293 };
294 -
295 partition@6 {
296 label = "Kernel";
297 reg = <0x00280000 0x00500000>;
298 };
299 -
300 partition@7 {
301 label = "File-System";
302 reg = <0x00780000 0x0F880000>;
303 };
304 };
305 };
306 +
307 + lcdc: lcdc@0x4830e000 {
308 + pinctrl-names = "default";
309 + pinctrl-0 = <&lcd_pins_s0>;
310 + status = "okay";
311 + display-timings {
312 + 800x480p62 {
313 + clock-frequency = <30000000>;
314 + hactive = <800>;
315 + vactive = <480>;
316 + hfront-porch = <39>;
317 + hback-porch = <39>;
318 + hsync-len = <47>;
319 + vback-porch = <29>;
320 + vfront-porch = <13>;
321 + vsync-len = <2>;
322 + hsync-active = <1>;
323 + vsync-active = <1>;
324 + };
325 + };
326 + };
327 +
328 + sound {
329 + compatible = "ti,da830-evm-audio";
330 + ti,model = "AM335x-EVM";
331 + ti,audio-codec = <&tlv320aic3106>;
332 + ti,mcasp-controller = <&mcasp1>;
333 + ti,codec-clock-rate = <12000000>;
334 + ti,audio-routing =
335 + "Headphone Jack", "HPLOUT",
336 + "Headphone Jack", "HPROUT",
337 + "LINE1L", "Line In",
338 + "LINE1R", "Line In";
339 + };
340 };
341
342 vbat: fixedregulator@0 {
343 @@ -403,10 +487,63 @@
344 brightness-levels = <0 51 53 56 62 75 101 152 255>;
345 default-brightness-level = <8>;
346 };
347 +
348 + panel {
349 + compatible = "ti,tilcdc,panel";
350 + status = "okay";
351 + pinctrl-names = "default";
352 + pinctrl-0 = <&lcd_pins_s0>;
353 + panel-info {
354 + ac-bias = <255>;
355 + ac-bias-intrpt = <0>;
356 + dma-burst-sz = <16>;
357 + bpp = <32>;
358 + fdd = <0x80>;
359 + sync-edge = <0>;
360 + sync-ctrl = <1>;
361 + raster-order = <0>;
362 + fifo-th = <0>;
363 + };
364 +
365 + display-timings {
366 + 800x480p62 {
367 + clock-frequency = <30000000>;
368 + hactive = <800>;
369 + vactive = <480>;
370 + hfront-porch = <39>;
371 + hback-porch = <39>;
372 + hsync-len = <47>;
373 + vback-porch = <29>;
374 + vfront-porch = <13>;
375 + vsync-len = <2>;
376 + hsync-active = <1>;
377 + vsync-active = <1>;
378 + };
379 + };
380 + };
381 };
382
383 #include "tps65910.dtsi"
384
385 +&mcasp1 {
386 + pinctrl-names = "default";
387 + pinctrl-0 = <&am335x_evm_audio_pins>;
388 +
389 + status = "okay";
390 +
391 + op-mode = <0>; /* MCASP_IIS_MODE */
392 + tdm-slots = <2>;
393 + /* 16 serializer */
394 + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
395 + 0 0 1 2
396 + 0 0 0 0
397 + 0 0 0 0
398 + 0 0 0 0
399 + >;
400 + tx-num-evt = <1>;
401 + rx-num-evt = <1>;
402 +};
403 +
404 &tps {
405 vcc1-supply = <&vbat>;
406 vcc2-supply = <&vbat>;
407 @@ -477,6 +614,8 @@
408 };
409
410 vmmc_reg: regulator@12 {
411 + regulator-min-microvolt = <1800000>;
412 + regulator-max-microvolt = <3300000>;
413 regulator-always-on;
414 };
415 };
416 @@ -509,7 +648,7 @@
417 tsc {
418 ti,wires = <4>;
419 ti,x-plate-resistance = <200>;
420 - ti,coordiante-readouts = <5>;
421 + ti,coordinate-readouts = <5>;
422 ti,wire-config = <0x00 0x11 0x22 0x33>;
423 };
424
425 @@ -517,3 +656,12 @@
426 ti,adc-channels = <4 5 6 7>;
427 };
428 };
429 +
430 +&mmc1 {
431 + status = "okay";
432 + vmmc-supply = <&vmmc_reg>;
433 + bus-width = <4>;
434 + pinctrl-names = "default";
435 + pinctrl-0 = <&mmc1_pins>;
436 + cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
437 +};
438 --- /dev/null
439 +++ b/arch/arm/boot/dts/am335x-evm-profile2.dts
440 @@ -0,0 +1,296 @@
441 +/*
442 + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
443 + *
444 + * This program is free software; you can redistribute it and/or modify
445 + * it under the terms of the GNU General Public License version 2 as
446 + * published by the Free Software Foundation.
447 + */
448 +/dts-v1/;
449 +
450 +#include "am33xx.dtsi"
451 +
452 +/ {
453 + model = "TI AM335x EVM";
454 + compatible = "ti,am335x-evm", "ti,am33xx";
455 +
456 + cpus {
457 + cpu@0 {
458 + cpu0-supply = <&vdd1_reg>;
459 + };
460 + };
461 +
462 + memory {
463 + device_type = "memory";
464 + reg = <0x80000000 0x10000000>; /* 256 MB */
465 + };
466 +
467 + am33xx_pinmux: pinmux@44e10800 {
468 + pinctrl-names = "default";
469 + pinctrl-0 = <&matrix_keypad_s0 &clkout2_pin>;
470 +
471 + matrix_keypad_s0: matrix_keypad_s0 {
472 + pinctrl-single,pins = <
473 + 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */
474 + 0x58 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a6.gpio1_22 */
475 + 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a9.gpio1_25 */
476 + 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a10.gpio1_26 */
477 + 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a11.gpio1_27 */
478 + >;
479 + };
480 +
481 + i2c0_pins: pinmux_i2c0_pins {
482 + pinctrl-single,pins = <
483 + 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
484 + 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
485 + >;
486 + };
487 +
488 + spi0_pins: pinmux_spi0_pins {
489 + pinctrl-single,pins = <
490 + 0x150 (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_clk.spi0_clk */
491 + 0x154 (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_d0.spi0_d0 */
492 + 0x158 (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_d1.spi0_d1 */
493 + 0x15c (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_cs0.spi0_cs0 */
494 + >;
495 + };
496 +
497 + uart0_pins: pinmux_uart0_pins {
498 + pinctrl-single,pins = <
499 + 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
500 + 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
501 + >;
502 + };
503 +
504 + clkout2_pin: pinmux_clkout2_pin {
505 + pinctrl-single,pins = <
506 + 0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
507 + >;
508 + };
509 +
510 + cpsw_default: cpsw_default {
511 + pinctrl-single,pins = <
512 + /* Slave 1 */
513 + 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */
514 + 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */
515 + 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */
516 + 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */
517 + 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */
518 + 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */
519 + 0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */
520 + 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */
521 + 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */
522 + 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */
523 + 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */
524 + 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */
525 + >;
526 + };
527 +
528 + cpsw_sleep: cpsw_sleep {
529 + pinctrl-single,pins = <
530 + /* Slave 1 reset value */
531 + 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
532 + 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
533 + 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
534 + 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
535 + 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
536 + 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
537 + 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
538 + 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
539 + 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
540 + 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
541 + 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
542 + 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
543 + >;
544 + };
545 +
546 + davinci_mdio_default: davinci_mdio_default {
547 + pinctrl-single,pins = <
548 + /* MDIO */
549 + 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
550 + 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
551 + >;
552 + };
553 +
554 + davinci_mdio_sleep: davinci_mdio_sleep {
555 + pinctrl-single,pins = <
556 + /* MDIO reset value */
557 + 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
558 + 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
559 + >;
560 + };
561 + };
562 +
563 + ocp {
564 + uart0: serial@44e09000 {
565 + pinctrl-names = "default";
566 + pinctrl-0 = <&uart0_pins>;
567 +
568 + status = "okay";
569 + };
570 +
571 + i2c0: i2c@44e0b000 {
572 + pinctrl-names = "default";
573 + pinctrl-0 = <&i2c0_pins>;
574 +
575 + status = "okay";
576 + clock-frequency = <400000>;
577 +
578 + tps: tps@2d {
579 + reg = <0x2d>;
580 + };
581 + };
582 +
583 + spi0: spi@48030000 {
584 + pinctrl-names = "default";
585 + pinctrl-0 = <&spi0_pins>;
586 +
587 + status = "okay";
588 + m25p80@0 {
589 + compatible = "w25q64";
590 + spi-max-frequency = <24000000>;
591 + reg = <0x0>;
592 + };
593 + };
594 + };
595 +
596 + vbat: fixedregulator@0 {
597 + compatible = "regulator-fixed";
598 + regulator-name = "vbat";
599 + regulator-min-microvolt = <5000000>;
600 + regulator-max-microvolt = <5000000>;
601 + regulator-boot-on;
602 + };
603 +
604 + lis3_reg: fixedregulator@1 {
605 + compatible = "regulator-fixed";
606 + regulator-name = "lis3_reg";
607 + regulator-boot-on;
608 + };
609 +
610 + matrix_keypad: matrix_keypad@0 {
611 + compatible = "gpio-matrix-keypad";
612 + debounce-delay-ms = <5>;
613 + col-scan-delay-us = <2>;
614 +
615 + row-gpios = <&gpio1 25 GPIO_ACTIVE_HIGH /* Bank1, pin25 */
616 + &gpio1 26 GPIO_ACTIVE_HIGH /* Bank1, pin26 */
617 + &gpio1 27 GPIO_ACTIVE_HIGH>; /* Bank1, pin27 */
618 +
619 + col-gpios = <&gpio1 21 GPIO_ACTIVE_HIGH /* Bank1, pin21 */
620 + &gpio1 22 GPIO_ACTIVE_HIGH>; /* Bank1, pin22 */
621 +
622 + linux,keymap = <0x0000008b /* MENU */
623 + 0x0100009e /* BACK */
624 + 0x02000069 /* LEFT */
625 + 0x0001006a /* RIGHT */
626 + 0x0101001c /* ENTER */
627 + 0x0201006c>; /* DOWN */
628 + };
629 +};
630 +
631 +#include "tps65910.dtsi"
632 +
633 +&tps {
634 + vcc1-supply = <&vbat>;
635 + vcc2-supply = <&vbat>;
636 + vcc3-supply = <&vbat>;
637 + vcc4-supply = <&vbat>;
638 + vcc5-supply = <&vbat>;
639 + vcc6-supply = <&vbat>;
640 + vcc7-supply = <&vbat>;
641 + vccio-supply = <&vbat>;
642 +
643 + regulators {
644 + vrtc_reg: regulator@0 {
645 + regulator-always-on;
646 + };
647 +
648 + vio_reg: regulator@1 {
649 + regulator-always-on;
650 + };
651 +
652 + vdd1_reg: regulator@2 {
653 + /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
654 + regulator-name = "vdd_mpu";
655 + regulator-min-microvolt = <912500>;
656 + regulator-max-microvolt = <1312500>;
657 + regulator-boot-on;
658 + regulator-always-on;
659 + };
660 +
661 + vdd2_reg: regulator@3 {
662 + /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
663 + regulator-name = "vdd_core";
664 + regulator-min-microvolt = <912500>;
665 + regulator-max-microvolt = <1150000>;
666 + regulator-boot-on;
667 + regulator-always-on;
668 + };
669 +
670 + vdd3_reg: regulator@4 {
671 + regulator-always-on;
672 + };
673 +
674 + vdig1_reg: regulator@5 {
675 + regulator-always-on;
676 + };
677 +
678 + vdig2_reg: regulator@6 {
679 + regulator-always-on;
680 + };
681 +
682 + vpll_reg: regulator@7 {
683 + regulator-always-on;
684 + };
685 +
686 + vdac_reg: regulator@8 {
687 + regulator-always-on;
688 + };
689 +
690 + vaux1_reg: regulator@9 {
691 + regulator-always-on;
692 + };
693 +
694 + vaux2_reg: regulator@10 {
695 + regulator-always-on;
696 + };
697 +
698 + vaux33_reg: regulator@11 {
699 + regulator-always-on;
700 + };
701 +
702 + vmmc_reg: regulator@12 {
703 + regulator-min-microvolt = <1800000>;
704 + regulator-max-microvolt = <3300000>;
705 + regulator-always-on;
706 + };
707 + };
708 +};
709 +
710 +&mac {
711 + pinctrl-names = "default", "sleep";
712 + pinctrl-0 = <&cpsw_default>;
713 + pinctrl-1 = <&cpsw_sleep>;
714 +};
715 +
716 +&davinci_mdio {
717 + pinctrl-names = "default", "sleep";
718 + pinctrl-0 = <&davinci_mdio_default>;
719 + pinctrl-1 = <&davinci_mdio_sleep>;
720 +};
721 +
722 +&cpsw_emac0 {
723 + phy_id = <&davinci_mdio>, <0>;
724 + phy-mode = "rgmii-txid";
725 +};
726 +
727 +&cpsw_emac1 {
728 + phy_id = <&davinci_mdio>, <1>;
729 + phy-mode = "rgmii-txid";
730 +};
731 +
732 +&mmc1 {
733 + status = "okay";
734 + vmmc-supply = <&vmmc_reg>;
735 + bus-width = <4>;
736 +};
737 --- a/arch/arm/boot/dts/am335x-evmsk.dts
738 +++ b/arch/arm/boot/dts/am335x-evmsk.dts
739 @@ -35,6 +35,39 @@
740 pinctrl-names = "default";
741 pinctrl-0 = <&gpio_keys_s0 &clkout2_pin>;
742
743 + lcd_pins_s0: lcd_pins_s0 {
744 + pinctrl-single,pins = <
745 + 0x20 0x01 /* gpmc_ad8.lcd_data16, OUTPUT | MODE1 */
746 + 0x24 0x01 /* gpmc_ad9.lcd_data17, OUTPUT | MODE1 */
747 + 0x28 0x01 /* gpmc_ad10.lcd_data18, OUTPUT | MODE1 */
748 + 0x2c 0x01 /* gpmc_ad11.lcd_data19, OUTPUT | MODE1 */
749 + 0x30 0x01 /* gpmc_ad12.lcd_data20, OUTPUT | MODE1 */
750 + 0x34 0x01 /* gpmc_ad13.lcd_data21, OUTPUT | MODE1 */
751 + 0x38 0x01 /* gpmc_ad14.lcd_data22, OUTPUT | MODE1 */
752 + 0x3c 0x01 /* gpmc_ad15.lcd_data23, OUTPUT | MODE1 */
753 + 0xa0 0x00 /* lcd_data0.lcd_data0, OUTPUT | MODE0 */
754 + 0xa4 0x00 /* lcd_data1.lcd_data1, OUTPUT | MODE0 */
755 + 0xa8 0x00 /* lcd_data2.lcd_data2, OUTPUT | MODE0 */
756 + 0xac 0x00 /* lcd_data3.lcd_data3, OUTPUT | MODE0 */
757 + 0xb0 0x00 /* lcd_data4.lcd_data4, OUTPUT | MODE0 */
758 + 0xb4 0x00 /* lcd_data5.lcd_data5, OUTPUT | MODE0 */
759 + 0xb8 0x00 /* lcd_data6.lcd_data6, OUTPUT | MODE0 */
760 + 0xbc 0x00 /* lcd_data7.lcd_data7, OUTPUT | MODE0 */
761 + 0xc0 0x00 /* lcd_data8.lcd_data8, OUTPUT | MODE0 */
762 + 0xc4 0x00 /* lcd_data9.lcd_data9, OUTPUT | MODE0 */
763 + 0xc8 0x00 /* lcd_data10.lcd_data10, OUTPUT | MODE0 */
764 + 0xcc 0x00 /* lcd_data11.lcd_data11, OUTPUT | MODE0 */
765 + 0xd0 0x00 /* lcd_data12.lcd_data12, OUTPUT | MODE0 */
766 + 0xd4 0x00 /* lcd_data13.lcd_data13, OUTPUT | MODE0 */
767 + 0xd8 0x00 /* lcd_data14.lcd_data14, OUTPUT | MODE0 */
768 + 0xdc 0x00 /* lcd_data15.lcd_data15, OUTPUT | MODE0 */
769 + 0xe0 0x00 /* lcd_vsync.lcd_vsync, OUTPUT | MODE0 */
770 + 0xe4 0x00 /* lcd_hsync.lcd_hsync, OUTPUT | MODE0 */
771 + 0xe8 0x00 /* lcd_pclk.lcd_pclk, OUTPUT | MODE0 */
772 + 0xec 0x00 /* lcd_ac_bias_en.lcd_ac_bias_en, OUTPUT | MODE0 */
773 + >;
774 + };
775 +
776 user_leds_s0: user_leds_s0 {
777 pinctrl-single,pins = <
778 0x10 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad4.gpio1_4 */
779 @@ -158,6 +191,21 @@
780 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
781 >;
782 };
783 +
784 + mmc1_pins: pinmux_mmc1_pins {
785 + pinctrl-single,pins = <
786 + 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
787 + >;
788 + };
789 +
790 + mcasp1_pins: mcasp1_pins {
791 + pinctrl-single,pins = <
792 + 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */
793 + 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */
794 + 0x108 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */
795 + 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
796 + >;
797 + };
798 };
799
800 ocp {
801 @@ -206,6 +254,18 @@
802 st,max-limit-y = <550>;
803 st,max-limit-z = <750>;
804 };
805 +
806 + tlv320aic3106: tlv320aic3106@1b {
807 + compatible = "ti,tlv320aic3106";
808 + reg = <0x1b>;
809 + status = "okay";
810 +
811 + /* Regulators */
812 + AVDD-supply = <&vaux2_reg>;
813 + IOVDD-supply = <&vaux2_reg>;
814 + DRVDD-supply = <&vaux2_reg>;
815 + DVDD-supply = <&vbat>;
816 + };
817 };
818
819 musb: usb@47400000 {
820 @@ -219,9 +279,22 @@
821 status = "okay";
822 };
823
824 + usb-phy@47401b00 {
825 + status = "okay";
826 + };
827 +
828 usb@47401000 {
829 status = "okay";
830 };
831 +
832 + usb@47401800 {
833 + status = "okay";
834 + dr_mode = "host";
835 + };
836 +
837 + dma-controller@07402000 {
838 + status = "okay";
839 + };
840 };
841
842 epwmss2: epwmss@48304000 {
843 @@ -233,6 +306,38 @@
844 pinctrl-0 = <&ecap2_pins>;
845 };
846 };
847 +
848 + lcdc: lcdc@0x4830e000 {
849 + pinctrl-names = "default";
850 + pinctrl-0 = <&lcd_pins_s0>;
851 + status = "okay";
852 + display-timings {
853 + 480x272 {
854 + hactive = <480>;
855 + vactive = <272>;
856 + hback-porch = <43>;
857 + hfront-porch = <8>;
858 + hsync-len = <4>;
859 + vback-porch = <12>;
860 + vfront-porch = <4>;
861 + vsync-len = <10>;
862 + clock-frequency = <9000000>;
863 + hsync-active = <0>;
864 + vsync-active = <0>;
865 + };
866 + };
867 + };
868 +
869 + sound {
870 + compatible = "ti,da830-evm-audio";
871 + ti,model = "AM335x-EVMSK";
872 + ti,audio-codec = <&tlv320aic3106>;
873 + ti,mcasp-controller = <&mcasp1>;
874 + ti,codec-clock-rate = <24576000>;
875 + ti,audio-routing =
876 + "Headphone Jack", "HPLOUT",
877 + "Headphone Jack", "HPROUT";
878 + };
879 };
880
881 vbat: fixedregulator@0 {
882 @@ -393,6 +498,8 @@
883 };
884
885 vmmc_reg: regulator@12 {
886 + regulator-min-microvolt = <1800000>;
887 + regulator-max-microvolt = <3300000>;
888 regulator-always-on;
889 };
890 };
891 @@ -419,3 +526,45 @@
892 phy_id = <&davinci_mdio>, <1>;
893 phy-mode = "rgmii-txid";
894 };
895 +
896 +&tscadc {
897 + status = "okay";
898 + tsc {
899 + ti,wires = <4>;
900 + ti,x-plate-resistance = <200>;
901 + ti,coordinate-readouts = <5>;
902 + ti,wire-config = <0x00 0x11 0x22 0x33>;
903 + };
904 +};
905 +
906 +&gpio0 {
907 + ti,no-reset;
908 +};
909 +
910 +&mmc1 {
911 + status = "okay";
912 + vmmc-supply = <&vmmc_reg>;
913 + bus-width = <4>;
914 + pinctrl-names = "default";
915 + pinctrl-0 = <&mmc1_pins>;
916 + cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
917 +};
918 +
919 +&mcasp1 {
920 + pinctrl-names = "default";
921 + pinctrl-0 = <&mcasp1_pins>;
922 +
923 + status = "okay";
924 +
925 + op-mode = <0>; /* MCASP_IIS_MODE */
926 + tdm-slots = <2>;
927 + /* 16 serializer */
928 + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
929 + 0 0 1 2
930 + 0 0 0 0
931 + 0 0 0 0
932 + 0 0 0 0
933 + >;
934 + tx-num-evt = <1>;
935 + rx-num-evt = <1>;
936 +};
937 --- /dev/null
938 +++ b/arch/arm/boot/dts/am33xx-clocks.dtsi
939 @@ -0,0 +1,661 @@
940 +/*
941 + * Device Tree Source for AM33xx clock data
942 + *
943 + * Copyright (C) 2013 Texas Instruments, Inc.
944 + *
945 + * This program is free software; you can redistribute it and/or modify
946 + * it under the terms of the GNU General Public License version 2 as
947 + * published by the Free Software Foundation.
948 + */
949 +
950 +clk_32768_ck: clk_32768_ck {
951 + #clock-cells = <0>;
952 + compatible = "fixed-clock";
953 + clock-frequency = <32768>;
954 +};
955 +
956 +clk_rc32k_ck: clk_rc32k_ck {
957 + #clock-cells = <0>;
958 + compatible = "fixed-clock";
959 + clock-frequency = <32000>;
960 +};
961 +
962 +virt_19200000_ck: virt_19200000_ck {
963 + #clock-cells = <0>;
964 + compatible = "fixed-clock";
965 + clock-frequency = <19200000>;
966 +};
967 +
968 +virt_24000000_ck: virt_24000000_ck {
969 + #clock-cells = <0>;
970 + compatible = "fixed-clock";
971 + clock-frequency = <24000000>;
972 +};
973 +
974 +virt_25000000_ck: virt_25000000_ck {
975 + #clock-cells = <0>;
976 + compatible = "fixed-clock";
977 + clock-frequency = <25000000>;
978 +};
979 +
980 +virt_26000000_ck: virt_26000000_ck {
981 + #clock-cells = <0>;
982 + compatible = "fixed-clock";
983 + clock-frequency = <26000000>;
984 +};
985 +
986 +sys_clkin_ck: sys_clkin_ck@44e10040 {
987 + #clock-cells = <0>;
988 + compatible = "mux-clock";
989 + clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
990 + bit-shift = <22>;
991 + reg = <0x44e10040 0x4>;
992 + bit-mask = <0x3>;
993 +};
994 +
995 +tclkin_ck: tclkin_ck {
996 + #clock-cells = <0>;
997 + compatible = "fixed-clock";
998 + clock-frequency = <12000000>;
999 +};
1000 +
1001 +dpll_core_ck: dpll_core_ck@44e00490 {
1002 + #clock-cells = <0>;
1003 + compatible = "ti,omap4-dpll-core-clock";
1004 + clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
1005 + reg = <0x44e00490 0x4>, <0x44e0045c 0x4>, <0x44e00468 0x4>;
1006 + reg-names = "control", "idlest", "mult-div1";
1007 +};
1008 +
1009 +dpll_core_x2_ck: dpll_core_x2_ck {
1010 + #clock-cells = <0>;
1011 + compatible = "ti,omap4-dpll-x2-clock";
1012 + clocks = <&dpll_core_ck>;
1013 +};
1014 +
1015 +dpll_core_m4_ck: dpll_core_m4_ck@44e00480 {
1016 + #clock-cells = <0>;
1017 + compatible = "divider-clock";
1018 + clocks = <&dpll_core_x2_ck>;
1019 + reg = <0x44e00480 0x4>;
1020 + bit-mask = <0x1f>;
1021 + index-starts-at-one;
1022 +};
1023 +
1024 +dpll_core_m5_ck: dpll_core_m5_ck@44e00484 {
1025 + #clock-cells = <0>;
1026 + compatible = "divider-clock";
1027 + clocks = <&dpll_core_x2_ck>;
1028 + reg = <0x44e00484 0x4>;
1029 + bit-mask = <0x1f>;
1030 + index-starts-at-one;
1031 +};
1032 +
1033 +dpll_core_m6_ck: dpll_core_m6_ck@44e004d8 {
1034 + #clock-cells = <0>;
1035 + compatible = "divider-clock";
1036 + clocks = <&dpll_core_x2_ck>;
1037 + reg = <0x44e004d8 0x4>;
1038 + bit-mask = <0x1f>;
1039 + index-starts-at-one;
1040 +};
1041 +
1042 +dpll_mpu_ck: dpll_mpu_ck@44e00488 {
1043 + #clock-cells = <0>;
1044 + compatible = "ti,omap4-dpll-clock";
1045 + clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
1046 + reg = <0x44e00488 0x4>, <0x44e00420 0x4>, <0x44e0042c 0x4>;
1047 + reg-names = "control", "idlest", "mult-div1";
1048 +};
1049 +
1050 +dpll_mpu_m2_ck: dpll_mpu_m2_ck@44e004a8 {
1051 + #clock-cells = <0>;
1052 + compatible = "divider-clock";
1053 + clocks = <&dpll_mpu_ck>;
1054 + reg = <0x44e004a8 0x4>;
1055 + bit-mask = <0x1f>;
1056 + index-starts-at-one;
1057 +};
1058 +
1059 +dpll_ddr_ck: dpll_ddr_ck@44e00494 {
1060 + #clock-cells = <0>;
1061 + compatible = "ti,omap4-dpll-no-gate-clock";
1062 + clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
1063 + reg = <0x44e00494 0x4>, <0x44e00434 0x4>, <0x44e00440 0x4>;
1064 + reg-names = "control", "idlest", "mult-div1";
1065 +};
1066 +
1067 +dpll_ddr_m2_ck: dpll_ddr_m2_ck@44e004a0 {
1068 + #clock-cells = <0>;
1069 + compatible = "divider-clock";
1070 + clocks = <&dpll_ddr_ck>;
1071 + reg = <0x44e004a0 0x4>;
1072 + bit-mask = <0x1f>;
1073 + index-starts-at-one;
1074 +};
1075 +
1076 +dpll_ddr_m2_div2_ck: dpll_ddr_m2_div2_ck {
1077 + #clock-cells = <0>;
1078 + compatible = "fixed-factor-clock";
1079 + clocks = <&dpll_ddr_m2_ck>;
1080 + clock-mult = <1>;
1081 + clock-div = <2>;
1082 +};
1083 +
1084 +dpll_disp_ck: dpll_disp_ck@44e00498 {
1085 + #clock-cells = <0>;
1086 + compatible = "ti,omap4-dpll-no-gate-clock";
1087 + clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
1088 + reg = <0x44e00498 0x4>, <0x44e00448 0x4>, <0x44e00454 0x4>;
1089 + reg-names = "control", "idlest", "mult-div1";
1090 +};
1091 +
1092 +dpll_disp_m2_ck: dpll_disp_m2_ck@44e004a4 {
1093 + #clock-cells = <0>;
1094 + compatible = "divider-clock";
1095 + clocks = <&dpll_disp_ck>;
1096 + reg = <0x44e004a4 0x4>;
1097 + bit-mask = <0x1f>;
1098 + index-starts-at-one;
1099 + set-rate-parent;
1100 +};
1101 +
1102 +dpll_per_ck: dpll_per_ck@44e0048c {
1103 + #clock-cells = <0>;
1104 + compatible = "ti,omap4-dpll-no-gate-j-type-clock";
1105 + clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
1106 + reg = <0x44e0048c 0x4>, <0x44e00470 0x4>, <0x44e0049c 0x4>;
1107 + reg-names = "control", "idlest", "mult-div1";
1108 +};
1109 +
1110 +dpll_per_m2_ck: dpll_per_m2_ck@44e004ac {
1111 + #clock-cells = <0>;
1112 + compatible = "divider-clock";
1113 + clocks = <&dpll_per_ck>;
1114 + reg = <0x44e004ac 0x4>;
1115 + bit-mask = <0x1f>;
1116 + index-starts-at-one;
1117 +};
1118 +
1119 +dpll_per_m2_div4_wkupdm_ck: dpll_per_m2_div4_wkupdm_ck {
1120 + #clock-cells = <0>;
1121 + compatible = "fixed-factor-clock";
1122 + clocks = <&dpll_per_m2_ck>;
1123 + clock-mult = <1>;
1124 + clock-div = <4>;
1125 +};
1126 +
1127 +dpll_per_m2_div4_ck: dpll_per_m2_div4_ck {
1128 + #clock-cells = <0>;
1129 + compatible = "fixed-factor-clock";
1130 + clocks = <&dpll_per_m2_ck>;
1131 + clock-mult = <1>;
1132 + clock-div = <4>;
1133 +};
1134 +
1135 +adc_tsc_fck: adc_tsc_fck {
1136 + #clock-cells = <0>;
1137 + compatible = "fixed-factor-clock";
1138 + clocks = <&sys_clkin_ck>;
1139 + clock-mult = <1>;
1140 + clock-div = <1>;
1141 +};
1142 +
1143 +cefuse_fck: cefuse_fck@44e00a20 {
1144 + #clock-cells = <0>;
1145 + compatible = "gate-clock";
1146 + clocks = <&sys_clkin_ck>;
1147 + bit-shift = <1>;
1148 + reg = <0x44e00a20 0x4>;
1149 +};
1150 +
1151 +clk_24mhz: clk_24mhz {
1152 + #clock-cells = <0>;
1153 + compatible = "fixed-factor-clock";
1154 + clocks = <&dpll_per_m2_ck>;
1155 + clock-mult = <1>;
1156 + clock-div = <8>;
1157 +};
1158 +
1159 +clkdiv32k_ck: clkdiv32k_ck {
1160 + #clock-cells = <0>;
1161 + compatible = "fixed-factor-clock";
1162 + clocks = <&clk_24mhz>;
1163 + clock-mult = <1>;
1164 + clock-div = <732>;
1165 +};
1166 +
1167 +clkdiv32k_ick: clkdiv32k_ick@44e0014c {
1168 + #clock-cells = <0>;
1169 + compatible = "ti,gate-clock";
1170 + clocks = <&clkdiv32k_ck>;
1171 + reg = <0x44e0014c 0x4>;
1172 + bit-shift = <1>;
1173 +};
1174 +
1175 +dcan0_fck: dcan0_fck {
1176 + #clock-cells = <0>;
1177 + compatible = "fixed-factor-clock";
1178 + clocks = <&sys_clkin_ck>;
1179 + clock-mult = <1>;
1180 + clock-div = <1>;
1181 +};
1182 +
1183 +dcan1_fck: dcan1_fck {
1184 + #clock-cells = <0>;
1185 + compatible = "fixed-factor-clock";
1186 + clocks = <&sys_clkin_ck>;
1187 + clock-mult = <1>;
1188 + clock-div = <1>;
1189 +};
1190 +
1191 +l3_gclk: l3_gclk {
1192 + #clock-cells = <0>;
1193 + compatible = "fixed-factor-clock";
1194 + clocks = <&dpll_core_m4_ck>;
1195 + clock-mult = <1>;
1196 + clock-div = <1>;
1197 +};
1198 +
1199 +pruss_ocp_gclk: pruss_ocp_gclk@44e00530 {
1200 + #clock-cells = <0>;
1201 + compatible = "mux-clock";
1202 + clocks = <&l3_gclk>, <&dpll_disp_m2_ck>;
1203 + reg = <0x44e00530 0x4>;
1204 + bit-mask = <0x1>;
1205 +};
1206 +
1207 +mcasp0_fck: mcasp0_fck {
1208 + #clock-cells = <0>;
1209 + compatible = "fixed-factor-clock";
1210 + clocks = <&sys_clkin_ck>;
1211 + clock-mult = <1>;
1212 + clock-div = <1>;
1213 +};
1214 +
1215 +mcasp1_fck: mcasp1_fck {
1216 + #clock-cells = <0>;
1217 + compatible = "fixed-factor-clock";
1218 + clocks = <&sys_clkin_ck>;
1219 + clock-mult = <1>;
1220 + clock-div = <1>;
1221 +};
1222 +
1223 +mmu_fck: mmu_fck@44e00914 {
1224 + #clock-cells = <0>;
1225 + compatible = "gate-clock";
1226 + clocks = <&dpll_core_m4_ck>;
1227 + bit-shift = <1>;
1228 + reg = <0x44e00914 0x4>;
1229 +};
1230 +
1231 +smartreflex0_fck: smartreflex0_fck {
1232 + #clock-cells = <0>;
1233 + compatible = "fixed-factor-clock";
1234 + clocks = <&sys_clkin_ck>;
1235 + clock-mult = <1>;
1236 + clock-div = <1>;
1237 +};
1238 +
1239 +smartreflex1_fck: smartreflex1_fck {
1240 + #clock-cells = <0>;
1241 + compatible = "fixed-factor-clock";
1242 + clocks = <&sys_clkin_ck>;
1243 + clock-mult = <1>;
1244 + clock-div = <1>;
1245 +};
1246 +
1247 +sha0_fck: sha0_fck {
1248 + #clock-cells = <0>;
1249 + compatible = "fixed-factor-clock";
1250 + clocks = <&sys_clkin_ck>;
1251 + clock-mult = <1>;
1252 + clock-div = <1>;
1253 +};
1254 +
1255 +rng_fck: rng_fck {
1256 + #clock-cells = <0>;
1257 + compatible = "fixed-factor-clock";
1258 + clocks = <&sys_clkin_ck>;
1259 + clock-mult = <1>;
1260 + clock-div = <1>;
1261 +};
1262 +
1263 +aes0_fck: aes0_fck {
1264 + #clock-cells = <0>;
1265 + compatible = "fixed-factor-clock";
1266 + clocks = <&sys_clkin_ck>;
1267 + clock-mult = <1>;
1268 + clock-div = <1>;
1269 +};
1270 +
1271 +timer1_fck: timer1_fck@44e00528 {
1272 + #clock-cells = <0>;
1273 + compatible = "mux-clock";
1274 + clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>;
1275 + reg = <0x44e00528 0x4>;
1276 + bit-mask = <0x7>;
1277 +};
1278 +
1279 +timer2_fck: timer2_fck@44e00508 {
1280 + #clock-cells = <0>;
1281 + compatible = "mux-clock";
1282 + clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
1283 + reg = <0x44e00508 0x4>;
1284 + bit-mask = <0x3>;
1285 +};
1286 +
1287 +timer3_fck: timer3_fck@44e0050c {
1288 + #clock-cells = <0>;
1289 + compatible = "mux-clock";
1290 + clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
1291 + reg = <0x44e0050c 0x4>;
1292 + bit-mask = <0x3>;
1293 +};
1294 +
1295 +timer4_fck: timer4_fck@44e00510 {
1296 + #clock-cells = <0>;
1297 + compatible = "mux-clock";
1298 + clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
1299 + reg = <0x44e00510 0x4>;
1300 + bit-mask = <0x3>;
1301 +};
1302 +
1303 +timer5_fck: timer5_fck@44e00518 {
1304 + #clock-cells = <0>;
1305 + compatible = "mux-clock";
1306 + clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
1307 + reg = <0x44e00518 0x4>;
1308 + bit-mask = <0x3>;
1309 +};
1310 +
1311 +timer6_fck: timer6_fck@44e0051c {
1312 + #clock-cells = <0>;
1313 + compatible = "mux-clock";
1314 + clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
1315 + reg = <0x44e0051c 0x4>;
1316 + bit-mask = <0x3>;
1317 +};
1318 +
1319 +timer7_fck: timer7_fck@44e00504 {
1320 + #clock-cells = <0>;
1321 + compatible = "mux-clock";
1322 + clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
1323 + reg = <0x44e00504 0x4>;
1324 + bit-mask = <0x3>;
1325 +};
1326 +
1327 +usbotg_fck: usbotg_fck@44e0047c {
1328 + #clock-cells = <0>;
1329 + compatible = "gate-clock";
1330 + clocks = <&dpll_per_ck>;
1331 + bit-shift = <8>;
1332 + reg = <0x44e0047c 0x4>;
1333 +};
1334 +
1335 +dpll_core_m4_div2_ck: dpll_core_m4_div2_ck {
1336 + #clock-cells = <0>;
1337 + compatible = "fixed-factor-clock";
1338 + clocks = <&dpll_core_m4_ck>;
1339 + clock-mult = <1>;
1340 + clock-div = <2>;
1341 +};
1342 +
1343 +ieee5000_fck: ieee5000_fck@44e000e4 {
1344 + #clock-cells = <0>;
1345 + compatible = "gate-clock";
1346 + clocks = <&dpll_core_m4_div2_ck>;
1347 + bit-shift = <1>;
1348 + reg = <0x44e000e4 0x4>;
1349 +};
1350 +
1351 +wdt1_fck: wdt1_fck@44e00538 {
1352 + #clock-cells = <0>;
1353 + compatible = "mux-clock";
1354 + clocks = <&clk_rc32k_ck>, <&clkdiv32k_ick>;
1355 + reg = <0x44e00538 0x4>;
1356 + bit-mask = <0x3>;
1357 +};
1358 +
1359 +l4_rtc_gclk: l4_rtc_gclk {
1360 + #clock-cells = <0>;
1361 + compatible = "fixed-factor-clock";
1362 + clocks = <&dpll_core_m4_ck>;
1363 + clock-mult = <1>;
1364 + clock-div = <2>;
1365 +};
1366 +
1367 +l4hs_gclk: l4hs_gclk {
1368 + #clock-cells = <0>;
1369 + compatible = "fixed-factor-clock";
1370 + clocks = <&dpll_core_m4_ck>;
1371 + clock-mult = <1>;
1372 + clock-div = <1>;
1373 +};
1374 +
1375 +l3s_gclk: l3s_gclk {
1376 + #clock-cells = <0>;
1377 + compatible = "fixed-factor-clock";
1378 + clocks = <&dpll_core_m4_div2_ck>;
1379 + clock-mult = <1>;
1380 + clock-div = <1>;
1381 +};
1382 +
1383 +l4fw_gclk: l4fw_gclk {
1384 + #clock-cells = <0>;
1385 + compatible = "fixed-factor-clock";
1386 + clocks = <&dpll_core_m4_div2_ck>;
1387 + clock-mult = <1>;
1388 + clock-div = <1>;
1389 +};
1390 +
1391 +l4ls_gclk: l4ls_gclk {
1392 + #clock-cells = <0>;
1393 + compatible = "fixed-factor-clock";
1394 + clocks = <&dpll_core_m4_div2_ck>;
1395 + clock-mult = <1>;
1396 + clock-div = <1>;
1397 +};
1398 +
1399 +sysclk_div_ck: sysclk_div_ck {
1400 + #clock-cells = <0>;
1401 + compatible = "fixed-factor-clock";
1402 + clocks = <&dpll_core_m4_ck>;
1403 + clock-mult = <1>;
1404 + clock-div = <1>;
1405 +};
1406 +
1407 +cpsw_125mhz_gclk: cpsw_125mhz_gclk {
1408 + #clock-cells = <0>;
1409 + compatible = "fixed-factor-clock";
1410 + clocks = <&dpll_core_m5_ck>;
1411 + clock-mult = <1>;
1412 + clock-div = <2>;
1413 +};
1414 +
1415 +cpsw_cpts_rft_clk: cpsw_cpts_rft_clk@44e00520 {
1416 + #clock-cells = <0>;
1417 + compatible = "mux-clock";
1418 + clocks = <&dpll_core_m5_ck>, <&dpll_core_m4_ck>;
1419 + reg = <0x44e00520 0x4>;
1420 + bit-mask = <0x1>;
1421 +};
1422 +
1423 +gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck@44e0053c {
1424 + #clock-cells = <0>;
1425 + compatible = "mux-clock";
1426 + clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clkdiv32k_ick>;
1427 + reg = <0x44e0053c 0x4>;
1428 + bit-mask = <0x3>;
1429 +};
1430 +
1431 +gpio0_dbclk: gpio0_dbclk@44e00408 {
1432 + #clock-cells = <0>;
1433 + compatible = "gate-clock";
1434 + clocks = <&gpio0_dbclk_mux_ck>;
1435 + bit-shift = <18>;
1436 + reg = <0x44e00408 0x4>;
1437 +};
1438 +
1439 +gpio1_dbclk: gpio1_dbclk@44e000ac {
1440 + #clock-cells = <0>;
1441 + compatible = "gate-clock";
1442 + clocks = <&clkdiv32k_ick>;
1443 + bit-shift = <18>;
1444 + reg = <0x44e000ac 0x4>;
1445 +};
1446 +
1447 +gpio2_dbclk: gpio2_dbclk@44e000b0 {
1448 + #clock-cells = <0>;
1449 + compatible = "gate-clock";
1450 + clocks = <&clkdiv32k_ick>;
1451 + bit-shift = <18>;
1452 + reg = <0x44e000b0 0x4>;
1453 +};
1454 +
1455 +gpio3_dbclk: gpio3_dbclk@44e000b4 {
1456 + #clock-cells = <0>;
1457 + compatible = "gate-clock";
1458 + clocks = <&clkdiv32k_ick>;
1459 + bit-shift = <18>;
1460 + reg = <0x44e000b4 0x4>;
1461 +};
1462 +
1463 +lcd_gclk: lcd_gclk@44e00534 {
1464 + #clock-cells = <0>;
1465 + compatible = "mux-clock";
1466 + clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>;
1467 + reg = <0x44e00534 0x4>;
1468 + bit-mask = <0x3>;
1469 + set-rate-parent;
1470 +};
1471 +
1472 +mmc_clk: mmc_clk {
1473 + #clock-cells = <0>;
1474 + compatible = "fixed-factor-clock";
1475 + clocks = <&dpll_per_m2_ck>;
1476 + clock-mult = <1>;
1477 + clock-div = <2>;
1478 +};
1479 +
1480 +gfx_fclk_clksel_ck: gfx_fclk_clksel_ck@44e0052c {
1481 + #clock-cells = <0>;
1482 + compatible = "mux-clock";
1483 + clocks = <&dpll_core_m4_ck>, <&dpll_per_m2_ck>;
1484 + bit-shift = <1>;
1485 + reg = <0x44e0052c 0x4>;
1486 + bit-mask = <0x1>;
1487 +};
1488 +
1489 +gfx_fck_div_ck: gfx_fck_div_ck@44e0052c {
1490 + #clock-cells = <0>;
1491 + compatible = "divider-clock";
1492 + clocks = <&gfx_fclk_clksel_ck>;
1493 + reg = <0x44e0052c 0x4>;
1494 + table = < 1 0 >, < 2 1 >;
1495 + bit-mask = <0x1>;
1496 +};
1497 +
1498 +sysclkout_pre_ck: sysclkout_pre_ck@44e00700 {
1499 + #clock-cells = <0>;
1500 + compatible = "mux-clock";
1501 + clocks = <&clk_32768_ck>, <&l3_gclk>, <&dpll_ddr_m2_ck>, <&dpll_per_m2_ck>, <&lcd_gclk>;
1502 + reg = <0x44e00700 0x4>;
1503 + bit-mask = <0x7>;
1504 +};
1505 +
1506 +clkout2_div_ck: clkout2_div_ck@44e00700 {
1507 + #clock-cells = <0>;
1508 + compatible = "divider-clock";
1509 + clocks = <&sysclkout_pre_ck>;
1510 + bit-shift = <3>;
1511 + reg = <0x44e00700 0x4>;
1512 + table = < 1 0 >, < 2 1 >, < 3 2 >, < 4 3 >, < 5 4 >, < 6 5 >, < 7 6 >, < 8 7 >;
1513 + bit-mask = <0x7>;
1514 +};
1515 +
1516 +dbg_sysclk_ck: dbg_sysclk_ck@44e00414 {
1517 + #clock-cells = <0>;
1518 + compatible = "gate-clock";
1519 + clocks = <&sys_clkin_ck>;
1520 + bit-shift = <19>;
1521 + reg = <0x44e00414 0x4>;
1522 +};
1523 +
1524 +dbg_clka_ck: dbg_clka_ck@44e00414 {
1525 + #clock-cells = <0>;
1526 + compatible = "gate-clock";
1527 + clocks = <&dpll_core_m4_ck>;
1528 + bit-shift = <30>;
1529 + reg = <0x44e00414 0x4>;
1530 +};
1531 +
1532 +stm_pmd_clock_mux_ck: stm_pmd_clock_mux_ck@44e00414 {
1533 + #clock-cells = <0>;
1534 + compatible = "mux-clock";
1535 + clocks = <&dbg_sysclk_ck>, <&dbg_clka_ck>;
1536 + bit-shift = <22>;
1537 + reg = <0x44e00414 0x4>;
1538 + bit-mask = <0x3>;
1539 +};
1540 +
1541 +trace_pmd_clk_mux_ck: trace_pmd_clk_mux_ck@44e00414 {
1542 + #clock-cells = <0>;
1543 + compatible = "mux-clock";
1544 + clocks = <&dbg_sysclk_ck>, <&dbg_clka_ck>;
1545 + bit-shift = <20>;
1546 + reg = <0x44e00414 0x4>;
1547 + bit-mask = <0x3>;
1548 +};
1549 +
1550 +stm_clk_div_ck: stm_clk_div_ck@44e00414 {
1551 + #clock-cells = <0>;
1552 + compatible = "divider-clock";
1553 + clocks = <&stm_pmd_clock_mux_ck>;
1554 + bit-shift = <27>;
1555 + reg = <0x44e00414 0x4>;
1556 + bit-mask = <0x7>;
1557 + index-power-of-two;
1558 +};
1559 +
1560 +trace_clk_div_ck: trace_clk_div_ck@44e00414 {
1561 + #clock-cells = <0>;
1562 + compatible = "divider-clock";
1563 + clocks = <&trace_pmd_clk_mux_ck>;
1564 + bit-shift = <24>;
1565 + reg = <0x44e00414 0x4>;
1566 + bit-mask = <0x7>;
1567 + index-power-of-two;
1568 +};
1569 +
1570 +clkout2_ck: clkout2_ck@44e00700 {
1571 + #clock-cells = <0>;
1572 + compatible = "gate-clock";
1573 + clocks = <&clkout2_div_ck>;
1574 + bit-shift = <7>;
1575 + reg = <0x44e00700 0x4>;
1576 +};
1577 +
1578 +ehrpwm0_tbclk: ehrpwm0_tbclk@44e10664 {
1579 + #clock-cells = <0>;
1580 + compatible = "gate-clock";
1581 + clocks = <&dpll_per_m2_ck>;
1582 + bit-shift = <0>;
1583 + reg = <0x44e10664 0x4>;
1584 +};
1585 +
1586 +ehrpwm1_tbclk: ehrpwm1_tbclk@44e10664 {
1587 + #clock-cells = <0>;
1588 + compatible = "gate-clock";
1589 + clocks = <&dpll_per_m2_ck>;
1590 + bit-shift = <1>;
1591 + reg = <0x44e10664 0x4>;
1592 +};
1593 +
1594 +ehrpwm2_tbclk: ehrpwm2_tbclk@44e10664 {
1595 + #clock-cells = <0>;
1596 + compatible = "gate-clock";
1597 + clocks = <&dpll_per_m2_ck>;
1598 + bit-shift = <2>;
1599 + reg = <0x44e10664 0x4>;
1600 +};
1601 --- a/arch/arm/boot/dts/am33xx.dtsi
1602 +++ b/arch/arm/boot/dts/am33xx.dtsi
1603 @@ -18,6 +18,9 @@
1604 interrupt-parent = <&intc>;
1605
1606 aliases {
1607 + i2c0 = &i2c0;
1608 + i2c1 = &i2c1;
1609 + i2c2 = &i2c2;
1610 serial0 = &uart0;
1611 serial1 = &uart1;
1612 serial2 = &uart2;
1613 @@ -30,6 +33,8 @@
1614 usb1 = &usb1;
1615 phy0 = &usb0_phy;
1616 phy1 = &usb1_phy;
1617 + ethernet0 = &cpsw_emac0;
1618 + ethernet1 = &cpsw_emac1;
1619 };
1620
1621 cpus {
1622 @@ -53,6 +58,10 @@
1623 275000 1125000
1624 >;
1625 voltage-tolerance = <2>; /* 2 percentage */
1626 +
1627 + clocks = <&dpll_mpu_ck>;
1628 + clock-names = "cpu";
1629 +
1630 clock-latency = <300000>; /* From omap-cpufreq driver */
1631 };
1632 };
1633 @@ -91,6 +100,8 @@
1634 #size-cells = <1>;
1635 ranges;
1636 ti,hwmods = "l3_main";
1637 + clocks = <&l3_gclk>;
1638 + clock-names = "fck";
1639
1640 intc: interrupt-controller@48200000 {
1641 compatible = "ti,omap2-intc";
1642 @@ -100,9 +111,23 @@
1643 reg = <0x48200000 0x1000>;
1644 };
1645
1646 + edma: edma@49000000 {
1647 + compatible = "ti,edma3";
1648 + ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";
1649 + reg = <0x49000000 0x10000>,
1650 + <0x44e10f90 0x10>;
1651 + interrupts = <12 13 14>;
1652 + #dma-cells = <1>;
1653 + dma-channels = <64>;
1654 + ti,edma-regions = <4>;
1655 + ti,edma-slots = <256>;
1656 + };
1657 +
1658 gpio0: gpio@44e07000 {
1659 compatible = "ti,omap4-gpio";
1660 ti,hwmods = "gpio1";
1661 + clocks = <&dpll_core_m4_div2_ck>, <&gpio0_dbclk>;
1662 + clock-names = "fck", "dbclk";
1663 gpio-controller;
1664 #gpio-cells = <2>;
1665 interrupt-controller;
1666 @@ -114,6 +139,8 @@
1667 gpio1: gpio@4804c000 {
1668 compatible = "ti,omap4-gpio";
1669 ti,hwmods = "gpio2";
1670 + clocks = <&l4ls_gclk>, <&gpio1_dbclk>;
1671 + clock-names = "fck", "dbclk";
1672 gpio-controller;
1673 #gpio-cells = <2>;
1674 interrupt-controller;
1675 @@ -125,6 +152,8 @@
1676 gpio2: gpio@481ac000 {
1677 compatible = "ti,omap4-gpio";
1678 ti,hwmods = "gpio3";
1679 + clocks = <&l4ls_gclk>, <&gpio2_dbclk>;
1680 + clock-names = "fck", "dbclk";
1681 gpio-controller;
1682 #gpio-cells = <2>;
1683 interrupt-controller;
1684 @@ -136,6 +165,8 @@
1685 gpio3: gpio@481ae000 {
1686 compatible = "ti,omap4-gpio";
1687 ti,hwmods = "gpio4";
1688 + clocks = <&l4ls_gclk>, <&gpio3_dbclk>;
1689 + clock-names = "fck", "dbclk";
1690 gpio-controller;
1691 #gpio-cells = <2>;
1692 interrupt-controller;
1693 @@ -147,6 +178,8 @@
1694 uart0: serial@44e09000 {
1695 compatible = "ti,omap3-uart";
1696 ti,hwmods = "uart1";
1697 + clocks = <&dpll_per_m2_div4_wkupdm_ck>;
1698 + clock-names = "fck";
1699 clock-frequency = <48000000>;
1700 reg = <0x44e09000 0x2000>;
1701 interrupts = <72>;
1702 @@ -156,6 +189,8 @@
1703 uart1: serial@48022000 {
1704 compatible = "ti,omap3-uart";
1705 ti,hwmods = "uart2";
1706 + clocks = <&dpll_per_m2_div4_ck>;
1707 + clock-names = "fck";
1708 clock-frequency = <48000000>;
1709 reg = <0x48022000 0x2000>;
1710 interrupts = <73>;
1711 @@ -165,6 +200,8 @@
1712 uart2: serial@48024000 {
1713 compatible = "ti,omap3-uart";
1714 ti,hwmods = "uart3";
1715 + clocks = <&dpll_per_m2_div4_ck>;
1716 + clock-names = "fck";
1717 clock-frequency = <48000000>;
1718 reg = <0x48024000 0x2000>;
1719 interrupts = <74>;
1720 @@ -174,6 +211,8 @@
1721 uart3: serial@481a6000 {
1722 compatible = "ti,omap3-uart";
1723 ti,hwmods = "uart4";
1724 + clocks = <&dpll_per_m2_div4_ck>;
1725 + clock-names = "fck";
1726 clock-frequency = <48000000>;
1727 reg = <0x481a6000 0x2000>;
1728 interrupts = <44>;
1729 @@ -183,6 +222,8 @@
1730 uart4: serial@481a8000 {
1731 compatible = "ti,omap3-uart";
1732 ti,hwmods = "uart5";
1733 + clocks = <&dpll_per_m2_div4_ck>;
1734 + clock-names = "fck";
1735 clock-frequency = <48000000>;
1736 reg = <0x481a8000 0x2000>;
1737 interrupts = <45>;
1738 @@ -192,6 +233,8 @@
1739 uart5: serial@481aa000 {
1740 compatible = "ti,omap3-uart";
1741 ti,hwmods = "uart6";
1742 + clocks = <&dpll_per_m2_div4_ck>;
1743 + clock-names = "fck";
1744 clock-frequency = <48000000>;
1745 reg = <0x481aa000 0x2000>;
1746 interrupts = <46>;
1747 @@ -203,6 +246,8 @@
1748 #address-cells = <1>;
1749 #size-cells = <0>;
1750 ti,hwmods = "i2c1";
1751 + clocks = <&dpll_per_m2_div4_wkupdm_ck>;
1752 + clock-names = "fck";
1753 reg = <0x44e0b000 0x1000>;
1754 interrupts = <70>;
1755 status = "disabled";
1756 @@ -213,6 +258,8 @@
1757 #address-cells = <1>;
1758 #size-cells = <0>;
1759 ti,hwmods = "i2c2";
1760 + clocks = <&dpll_per_m2_div4_ck>;
1761 + clock-names = "fck";
1762 reg = <0x4802a000 0x1000>;
1763 interrupts = <71>;
1764 status = "disabled";
1765 @@ -223,14 +270,62 @@
1766 #address-cells = <1>;
1767 #size-cells = <0>;
1768 ti,hwmods = "i2c3";
1769 + clocks = <&dpll_per_m2_div4_ck>;
1770 + clock-names = "fck";
1771 reg = <0x4819c000 0x1000>;
1772 interrupts = <30>;
1773 status = "disabled";
1774 };
1775
1776 + mmc1: mmc@48060000 {
1777 + compatible = "ti,omap4-hsmmc";
1778 + ti,hwmods = "mmc1";
1779 + clocks = <&mmc_clk>, <&clkdiv32k_ick>;
1780 + clock-names = "fck", "mmchsdb_fck";
1781 + ti,dual-volt;
1782 + ti,needs-special-reset;
1783 + ti,needs-special-hs-handling;
1784 + dmas = <&edma 24
1785 + &edma 25>;
1786 + dma-names = "tx", "rx";
1787 + interrupts = <64>;
1788 + interrupt-parent = <&intc>;
1789 + reg = <0x48060000 0x1000>;
1790 + status = "disabled";
1791 + };
1792 +
1793 + mmc2: mmc@481d8000 {
1794 + compatible = "ti,omap4-hsmmc";
1795 + ti,hwmods = "mmc2";
1796 + clocks = <&mmc_clk>, <&clkdiv32k_ick>;
1797 + clock-names = "fck", "mmchsdb_fck";
1798 + ti,needs-special-reset;
1799 + dmas = <&edma 2
1800 + &edma 3>;
1801 + dma-names = "tx", "rx";
1802 + interrupts = <28>;
1803 + interrupt-parent = <&intc>;
1804 + reg = <0x481d8000 0x1000>;
1805 + status = "disabled";
1806 + };
1807 +
1808 + mmc3: mmc@47810000 {
1809 + compatible = "ti,omap4-hsmmc";
1810 + ti,hwmods = "mmc3";
1811 + clocks = <&mmc_clk>, <&clkdiv32k_ick>;
1812 + clock-names = "fck", "mmchsdb_fck";
1813 + ti,needs-special-reset;
1814 + interrupts = <29>;
1815 + interrupt-parent = <&intc>;
1816 + reg = <0x47810000 0x1000>;
1817 + status = "disabled";
1818 + };
1819 +
1820 wdt2: wdt@44e35000 {
1821 compatible = "ti,omap3-wdt";
1822 ti,hwmods = "wd_timer2";
1823 + clocks = <&wdt1_fck>;
1824 + clock-names = "fck";
1825 reg = <0x44e35000 0x1000>;
1826 interrupts = <91>;
1827 };
1828 @@ -238,6 +333,8 @@
1829 dcan0: d_can@481cc000 {
1830 compatible = "bosch,d_can";
1831 ti,hwmods = "d_can0";
1832 + clocks = <&dcan0_fck>;
1833 + clock-names = "fck";
1834 reg = <0x481cc000 0x2000
1835 0x44e10644 0x4>;
1836 interrupts = <52>;
1837 @@ -247,17 +344,32 @@
1838 dcan1: d_can@481d0000 {
1839 compatible = "bosch,d_can";
1840 ti,hwmods = "d_can1";
1841 + clocks = <&dcan1_fck>;
1842 + clock-names = "fck";
1843 reg = <0x481d0000 0x2000
1844 0x44e10644 0x4>;
1845 interrupts = <55>;
1846 status = "disabled";
1847 };
1848
1849 + mailbox: mailbox@480C8000 {
1850 + compatible = "ti,omap4-mailbox";
1851 + reg = <0x480C8000 0x200>;
1852 + interrupts = <77>;
1853 + ti,hwmods = "mailbox";
1854 + ti,mbox-num-users = <4>;
1855 + ti,mbox-num-fifos = <8>;
1856 + ti,mbox-names = "wkup_m3";
1857 + ti,mbox-data = <0 0 0 0>;
1858 + };
1859 +
1860 timer1: timer@44e31000 {
1861 compatible = "ti,am335x-timer-1ms";
1862 reg = <0x44e31000 0x400>;
1863 interrupts = <67>;
1864 ti,hwmods = "timer1";
1865 + clocks = <&timer1_fck>;
1866 + clock-names = "fck";
1867 ti,timer-alwon;
1868 };
1869
1870 @@ -266,6 +378,8 @@
1871 reg = <0x48040000 0x400>;
1872 interrupts = <68>;
1873 ti,hwmods = "timer2";
1874 + clocks = <&timer2_fck>;
1875 + clock-names = "fck";
1876 };
1877
1878 timer3: timer@48042000 {
1879 @@ -273,6 +387,8 @@
1880 reg = <0x48042000 0x400>;
1881 interrupts = <69>;
1882 ti,hwmods = "timer3";
1883 + clocks = <&timer3_fck>;
1884 + clock-names = "fck";
1885 };
1886
1887 timer4: timer@48044000 {
1888 @@ -280,6 +396,8 @@
1889 reg = <0x48044000 0x400>;
1890 interrupts = <92>;
1891 ti,hwmods = "timer4";
1892 + clocks = <&timer4_fck>;
1893 + clock-names = "fck";
1894 ti,timer-pwm;
1895 };
1896
1897 @@ -288,6 +406,8 @@
1898 reg = <0x48046000 0x400>;
1899 interrupts = <93>;
1900 ti,hwmods = "timer5";
1901 + clocks = <&timer5_fck>;
1902 + clock-names = "fck";
1903 ti,timer-pwm;
1904 };
1905
1906 @@ -296,6 +416,8 @@
1907 reg = <0x48048000 0x400>;
1908 interrupts = <94>;
1909 ti,hwmods = "timer6";
1910 + clocks = <&timer6_fck>;
1911 + clock-names = "fck";
1912 ti,timer-pwm;
1913 };
1914
1915 @@ -304,6 +426,8 @@
1916 reg = <0x4804a000 0x400>;
1917 interrupts = <95>;
1918 ti,hwmods = "timer7";
1919 + clocks = <&timer7_fck>;
1920 + clock-names = "fck";
1921 ti,timer-pwm;
1922 };
1923
1924 @@ -313,6 +437,8 @@
1925 interrupts = <75
1926 76>;
1927 ti,hwmods = "rtc";
1928 + clocks = <&clk_32768_ck>;
1929 + clock-names = "fck";
1930 };
1931
1932 spi0: spi@48030000 {
1933 @@ -323,6 +449,13 @@
1934 interrupts = <65>;
1935 ti,spi-num-cs = <2>;
1936 ti,hwmods = "spi0";
1937 + clocks = <&dpll_per_m2_div4_ck>;
1938 + clock-names = "fck";
1939 + dmas = <&edma 16
1940 + &edma 17
1941 + &edma 18
1942 + &edma 19>;
1943 + dma-names = "tx0", "rx0", "tx1", "rx1";
1944 status = "disabled";
1945 };
1946
1947 @@ -334,6 +467,13 @@
1948 interrupts = <125>;
1949 ti,spi-num-cs = <2>;
1950 ti,hwmods = "spi1";
1951 + clocks = <&dpll_per_m2_div4_ck>;
1952 + clock-names = "fck";
1953 + dmas = <&edma 42
1954 + &edma 43
1955 + &edma 44
1956 + &edma 45>;
1957 + dma-names = "tx0", "rx0", "tx1", "rx1";
1958 status = "disabled";
1959 };
1960
1961 @@ -345,6 +485,8 @@
1962 #size-cells = <1>;
1963 ti,hwmods = "usb_otg_hs";
1964 status = "disabled";
1965 + clocks = <&usbotg_fck>;
1966 + clock-names = "fck";
1967
1968 ctrl_mod: control@44e10000 {
1969 compatible = "ti,am335x-usb-ctrl-module";
1970 @@ -469,6 +611,8 @@
1971 compatible = "ti,am33xx-pwmss";
1972 reg = <0x48300000 0x10>;
1973 ti,hwmods = "epwmss0";
1974 + clocks = <&l4ls_gclk>;
1975 + clock-names = "fck";
1976 #address-cells = <1>;
1977 #size-cells = <1>;
1978 status = "disabled";
1979 @@ -481,6 +625,8 @@
1980 #pwm-cells = <3>;
1981 reg = <0x48300100 0x80>;
1982 ti,hwmods = "ecap0";
1983 + clocks = <&l4ls_gclk>;
1984 + clock-names = "fck";
1985 status = "disabled";
1986 };
1987
1988 @@ -489,6 +635,8 @@
1989 #pwm-cells = <3>;
1990 reg = <0x48300200 0x80>;
1991 ti,hwmods = "ehrpwm0";
1992 + clocks = <&l4ls_gclk>;
1993 + clock-names = "fck";
1994 status = "disabled";
1995 };
1996 };
1997 @@ -497,6 +645,8 @@
1998 compatible = "ti,am33xx-pwmss";
1999 reg = <0x48302000 0x10>;
2000 ti,hwmods = "epwmss1";
2001 + clocks = <&l4ls_gclk>;
2002 + clock-names = "fck";
2003 #address-cells = <1>;
2004 #size-cells = <1>;
2005 status = "disabled";
2006 @@ -509,6 +659,8 @@
2007 #pwm-cells = <3>;
2008 reg = <0x48302100 0x80>;
2009 ti,hwmods = "ecap1";
2010 + clocks = <&l4ls_gclk>;
2011 + clock-names = "fck";
2012 status = "disabled";
2013 };
2014
2015 @@ -517,6 +669,8 @@
2016 #pwm-cells = <3>;
2017 reg = <0x48302200 0x80>;
2018 ti,hwmods = "ehrpwm1";
2019 + clocks = <&l4ls_gclk>;
2020 + clock-names = "fck";
2021 status = "disabled";
2022 };
2023 };
2024 @@ -525,6 +679,8 @@
2025 compatible = "ti,am33xx-pwmss";
2026 reg = <0x48304000 0x10>;
2027 ti,hwmods = "epwmss2";
2028 + clocks = <&l4ls_gclk>;
2029 + clock-names = "fck";
2030 #address-cells = <1>;
2031 #size-cells = <1>;
2032 status = "disabled";
2033 @@ -537,6 +693,8 @@
2034 #pwm-cells = <3>;
2035 reg = <0x48304100 0x80>;
2036 ti,hwmods = "ecap2";
2037 + clocks = <&l4ls_gclk>;
2038 + clock-names = "fck";
2039 status = "disabled";
2040 };
2041
2042 @@ -545,6 +703,8 @@
2043 #pwm-cells = <3>;
2044 reg = <0x48304200 0x80>;
2045 ti,hwmods = "ehrpwm2";
2046 + clocks = <&l4ls_gclk>;
2047 + clock-names = "fck";
2048 status = "disabled";
2049 };
2050 };
2051 @@ -552,6 +712,8 @@
2052 mac: ethernet@4a100000 {
2053 compatible = "ti,cpsw";
2054 ti,hwmods = "cpgmac0";
2055 + clocks = <&cpsw_125mhz_gclk>;
2056 + clock-names = "fck";
2057 cpdma_channels = <8>;
2058 ale_entries = <1024>;
2059 bd_ram_size = <0x2000>;
2060 @@ -581,6 +743,8 @@
2061 #address-cells = <1>;
2062 #size-cells = <0>;
2063 ti,hwmods = "davinci_mdio";
2064 + clocks = <&cpsw_125mhz_gclk>;
2065 + clock-names = "fck";
2066 bus_freq = <1000000>;
2067 reg = <0x4a101000 0x100>;
2068 };
2069 @@ -594,19 +758,33 @@
2070 /* Filled in by U-Boot */
2071 mac-address = [ 00 00 00 00 00 00 ];
2072 };
2073 +
2074 + phy_sel: cpsw-phy-sel@44e10650 {
2075 + compatible = "ti,am3352-cpsw-phy-sel";
2076 + reg= <0x44e10650 0x4>;
2077 + reg-names = "gmii-sel";
2078 + };
2079 };
2080
2081 ocmcram: ocmcram@40300000 {
2082 compatible = "ti,am3352-ocmcram";
2083 reg = <0x40300000 0x10000>;
2084 ti,hwmods = "ocmcram";
2085 + clocks = <&l3_gclk>;
2086 + clock-names = "fck";
2087 };
2088
2089 wkup_m3: wkup_m3@44d00000 {
2090 compatible = "ti,am3353-wkup-m3";
2091 - reg = <0x44d00000 0x4000 /* M3 UMEM */
2092 - 0x44d80000 0x2000>; /* M3 DMEM */
2093 + reg = <0x44d00000 0x4000
2094 + 0x44d80000 0x2000
2095 + 0x44e11324 0x0024>;
2096 + reg-names = "m3_umem", "m3_dmem", "ipc_regs";
2097 + interrupts = <78>;
2098 ti,hwmods = "wkup_m3";
2099 + ti,no-reset;
2100 + clocks = <&dpll_core_m4_div2_ck>;
2101 + clock-names = "fck";
2102 };
2103
2104 elm: elm@48080000 {
2105 @@ -614,6 +792,8 @@
2106 reg = <0x48080000 0x2000>;
2107 interrupts = <4>;
2108 ti,hwmods = "elm";
2109 + clocks = <&l4ls_gclk>;
2110 + clock-names = "fck";
2111 status = "disabled";
2112 };
2113
2114 @@ -623,6 +803,8 @@
2115 interrupt-parent = <&intc>;
2116 interrupts = <16>;
2117 ti,hwmods = "adc_tsc";
2118 + clocks = <&adc_tsc_fck>;
2119 + clock-names = "fck";
2120 status = "disabled";
2121
2122 tsc {
2123 @@ -637,6 +819,9 @@
2124 gpmc: gpmc@50000000 {
2125 compatible = "ti,am3352-gpmc";
2126 ti,hwmods = "gpmc";
2127 + ti,no-idle;
2128 + clocks = <&l3s_gclk>;
2129 + clock-names = "fck";
2130 reg = <0x50000000 0x2000>;
2131 interrupts = <100>;
2132 gpmc,num-cs = <7>;
2133 @@ -645,5 +830,102 @@
2134 #size-cells = <1>;
2135 status = "disabled";
2136 };
2137 +
2138 + prcm: prcm@44e00000 {
2139 + compatible = "ti,am3352-prcm";
2140 + reg = <0x44e00000 0x1300>;
2141 + #reset-cells = <1>;
2142 + };
2143 +
2144 + sham: sham@53100000 {
2145 + compatible = "ti,omap4-sham";
2146 + ti,hwmods = "sham";
2147 + #address-cells = <1>;
2148 + #size-cells = <0>;
2149 + reg = <0x53100000 0x200>;
2150 + interrupt-parent = <&intc>;
2151 + interrupts = <109>;
2152 + dmas = <&edma 36>;
2153 + dma-names = "rx";
2154 + clocks = <&l3_gclk>;
2155 + clock-names = "fck";
2156 + };
2157 +
2158 + aes: aes@53500000 {
2159 + compatible = "ti,omap4-aes";
2160 + ti,hwmods = "aes";
2161 + #address-cells = <1>;
2162 + #size-cells = <0>;
2163 + reg = <0x53500000 0xa0>;
2164 + interrupt-parent = <&intc>;
2165 + interrupts = <103>;
2166 + dmas = <&edma 6
2167 + &edma 5>;
2168 + dma-names = "tx", "rx";
2169 + clocks = <&aes0_fck>;
2170 + clock-names = "fck";
2171 + };
2172 +
2173 + rng: rng@48310000 {
2174 + compatible = "ti,omap4-rng";
2175 + ti,hwmods = "rng";
2176 + reg = <0x48310000 0x2000>;
2177 + interrupts = <111>;
2178 + clocks = <&rng_fck>;
2179 + clock-names = "fck";
2180 + };
2181 +
2182 + lcdc: lcdc@0x4830e000 {
2183 + compatible = "ti,am33xx-tilcdc";
2184 + reg = <0x4830e000 0x1000>;
2185 + interrupt-parent = <&intc>;
2186 + interrupts = <36>;
2187 + clocks = <&lcd_gclk>;
2188 + clock-names = "fck";
2189 + ti,hwmods = "lcdc";
2190 + status = "disabled";
2191 + };
2192 +
2193 + mcasp0: mcasp@48038000 {
2194 + compatible = "ti,omap2-mcasp-audio";
2195 + ti,hwmods = "mcasp0";
2196 + reg = <0x48038000 0x2000>,
2197 + <0x46400000 0x400000>;
2198 + reg-names = "mpu", "dma";
2199 + interrupts = <80 81>;
2200 + interrupts-names = "tx", "rx";
2201 + status = "disabled";
2202 + dmas = <&edma 8
2203 + &edma 9>;
2204 + dma-names = "tx", "rx";
2205 + };
2206 +
2207 + mcasp1: mcasp@4803C000 {
2208 + compatible = "ti,omap2-mcasp-audio";
2209 + ti,hwmods = "mcasp1";
2210 + reg = <0x4803C000 0x2000>,
2211 + <0x46400000 0x400000>;
2212 + reg-names = "mpu", "dma";
2213 + interrupts = <82 83>;
2214 + interrupts-names = "tx", "rx";
2215 + status = "disabled";
2216 + dmas = <&edma 10
2217 + &edma 11>;
2218 + dma-names = "tx", "rx";
2219 + };
2220 + };
2221 +
2222 + clocks {
2223 + #address-cells = <1>;
2224 + #size-cells = <1>;
2225 + ranges;
2226 + /include/ "am33xx-clocks.dtsi"
2227 };
2228 +
2229 + clockdomains {
2230 + clk_24mhz_clkdm: clk_24mhz_clkdm {
2231 + compatible = "ti,clockdomain";
2232 + clocks = <&clkdiv32k_ick>;
2233 + };
2234 + };
2235 };
2236 --- /dev/null
2237 +++ b/arch/arm/boot/dts/am3517.dtsi
2238 @@ -0,0 +1,116 @@
2239 +/*
2240 + * Device Tree Source for AM3517 SoC
2241 + *
2242 + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
2243 + *
2244 + * This file is licensed under the terms of the GNU General Public License
2245 + * version 2. This program is licensed "as is" without any warranty of any
2246 + * kind, whether express or implied.
2247 + */
2248 +
2249 +#include "omap3.dtsi"
2250 +
2251 +/ {
2252 + cpus {
2253 + cpu@0 {
2254 + /* OMAP343x/OMAP35xx variants OPP1-5 */
2255 + operating-points = <
2256 + /* kHz uV */
2257 + 125000 975000
2258 + 250000 1075000
2259 + 500000 1200000
2260 + 550000 1270000
2261 + 600000 1350000
2262 + >;
2263 + clock-latency = <300000>; /* From legacy driver */
2264 + };
2265 + };
2266 +
2267 + clocks {
2268 + #address-cells = <1>;
2269 + #size-cells = <1>;
2270 + ranges;
2271 + /include/ "am35xx-clocks.dtsi"
2272 + /include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
2273 + };
2274 +
2275 + clockdomains {
2276 + dss_clkdm: dss_clkdm {
2277 + compatible = "ti,clockdomain";
2278 + clocks = <&dss1_alwon_fck_3430es2>, <&dss_ick_3430es2>;
2279 + };
2280 +
2281 + usbhost_clkdm: usbhost_clkdm {
2282 + compatible = "ti,clockdomain";
2283 + clocks = <&usbhost_48m_fck>, <&usbhost_ick>;
2284 + };
2285 +
2286 + core_l4_clkdm: core_l4_clkdm {
2287 + compatible = "ti,clockdomain";
2288 + clocks = <&mmchs1_ick>, <&mmchs2_ick>, <&hdq_fck>,
2289 + <&uart1_ick>, <&mcspi4_fck>, <&i2c3_fck>,
2290 + <&mcspi2_ick>, <&uart2_ick>, <&mcspi3_ick>,
2291 + <&i2c1_fck>, <&hdq_ick>, <&sha12_ick>,
2292 + <&mcbsp5_ick>, <&mcspi3_fck>, <&aes2_ick>,
2293 + <&mcspi1_ick>, <&uart2_fck>, <&mmchs2_fck>,
2294 + <&mmchs1_fck>, <&i2c3_ick>, <&mcspi1_fck>,
2295 + <&mcspi4_ick>, <&omapctrl_ick>, <&mcbsp1_ick>,
2296 + <&mcspi2_fck>, <&gpt10_ick>, <&i2c2_fck>,
2297 + <&i2c2_ick>, <&gpt11_ick>, <&i2c1_ick>,
2298 + <&uart1_fck>;
2299 + };
2300 +
2301 + wkup_clkdm: wkup_clkdm {
2302 + compatible = "ti,clockdomain";
2303 + clocks = <&wdt1_ick>, <&gpt12_ick>, <&gpio1_ick>,
2304 + <&gpt1_ick>, <&omap_32ksync_ick>, <&wdt2_ick>,
2305 + <&wdt2_fck>;
2306 + };
2307 +
2308 + dpll4_clkdm: dpll4_clkdm {
2309 + compatible = "ti,clockdomain";
2310 + clocks = <&dpll4_ck>;
2311 + };
2312 +
2313 + core_l3_clkdm: core_l3_clkdm {
2314 + compatible = "ti,clockdomain";
2315 + clocks = <&sdrc_ick>;
2316 + };
2317 +
2318 + per_clkdm: per_clkdm {
2319 + compatible = "ti,clockdomain";
2320 + clocks = <&gpt2_ick>, <&uart3_fck>, <&gpio3_ick>,
2321 + <&mcbsp2_ick>, <&gpt6_ick>, <&mcbsp4_ick>,
2322 + <&gpt4_ick>, <&mcbsp3_ick>, <&gpt8_ick>,
2323 + <&uart3_ick>, <&gpt5_ick>, <&gpt7_ick>,
2324 + <&gpio2_ick>, <&gpio6_ick>, <&gpt9_ick>,
2325 + <&gpt3_ick>, <&gpio5_ick>, <&wdt3_ick>,
2326 + <&gpio4_ick>, <&wdt3_fck>, <&uart4_ick>;
2327 + };
2328 +
2329 + emu_clkdm: emu_clkdm {
2330 + compatible = "ti,clockdomain";
2331 + clocks = <&emu_src_ck>;
2332 + };
2333 +
2334 + sgx_clkdm: sgx_clkdm {
2335 + compatible = "ti,clockdomain";
2336 + clocks = <&sgx_ick>;
2337 + };
2338 +
2339 + dpll3_clkdm: dpll3_clkdm {
2340 + compatible = "ti,clockdomain";
2341 + clocks = <&dpll3_ck>;
2342 + };
2343 +
2344 + dpll5_clkdm: dpll5_clkdm {
2345 + compatible = "ti,clockdomain";
2346 + clocks = <&dpll5_ck>;
2347 + };
2348 +
2349 + dpll1_clkdm: dpll1_clkdm {
2350 + compatible = "ti,clockdomain";
2351 + clocks = <&dpll1_ck>;
2352 + };
2353 + };
2354 +};
2355 --- a/arch/arm/boot/dts/am3517-evm.dts
2356 +++ b/arch/arm/boot/dts/am3517-evm.dts
2357 @@ -7,7 +7,7 @@
2358 */
2359 /dts-v1/;
2360
2361 -#include "omap34xx.dtsi"
2362 +#include "am3517.dtsi"
2363
2364 / {
2365 model = "TI AM3517 EVM (AM3517/05)";
2366 --- a/arch/arm/boot/dts/am3517_mt_ventoux.dts
2367 +++ b/arch/arm/boot/dts/am3517_mt_ventoux.dts
2368 @@ -7,7 +7,7 @@
2369 */
2370 /dts-v1/;
2371
2372 -#include "omap34xx.dtsi"
2373 +#include "am3517.dtsi"
2374
2375 / {
2376 model = "TeeJet Mt.Ventoux";
2377 --- /dev/null
2378 +++ b/arch/arm/boot/dts/am35xx-clocks.dtsi
2379 @@ -0,0 +1,101 @@
2380 +/*
2381 + * Device Tree Source for AM35xx clock data
2382 + *
2383 + * Copyright (C) 2013 Texas Instruments, Inc.
2384 + *
2385 + * This program is free software; you can redistribute it and/or modify
2386 + * it under the terms of the GNU General Public License version 2 as
2387 + * published by the Free Software Foundation.
2388 + */
2389 +
2390 +ipss_ick: ipss_ick@48004a10 {
2391 + #clock-cells = <0>;
2392 + compatible = "ti,am35xx-interface-clock";
2393 + clocks = <&core_l3_ick>;
2394 + reg = <0x48004a10 0x4>;
2395 + ti,enable-bit = <4>;
2396 +};
2397 +
2398 +rmii_ck: rmii_ck {
2399 + #clock-cells = <0>;
2400 + compatible = "fixed-clock";
2401 + clock-frequency = <50000000>;
2402 +};
2403 +
2404 +pclk_ck: pclk_ck {
2405 + #clock-cells = <0>;
2406 + compatible = "fixed-clock";
2407 + clock-frequency = <27000000>;
2408 +};
2409 +
2410 +emac_ick: emac_ick@4800259c {
2411 + #clock-cells = <0>;
2412 + compatible = "ti,am35xx-gate-clock";
2413 + clocks = <&ipss_ick>;
2414 + reg = <0x4800259c 0x4>;
2415 + ti,enable-bit = <1>;
2416 +};
2417 +
2418 +emac_fck: emac_fck@4800259c {
2419 + #clock-cells = <0>;
2420 + compatible = "gate-clock";
2421 + clocks = <&rmii_ck>;
2422 + reg = <0x4800259c 0x4>;
2423 + bit-shift = <9>;
2424 +};
2425 +
2426 +vpfe_ick: vpfe_ick@4800259c {
2427 + #clock-cells = <0>;
2428 + compatible = "ti,am35xx-gate-clock";
2429 + clocks = <&ipss_ick>;
2430 + reg = <0x4800259c 0x4>;
2431 + ti,enable-bit = <2>;
2432 +};
2433 +
2434 +vpfe_fck: vpfe_fck@4800259c {
2435 + #clock-cells = <0>;
2436 + compatible = "gate-clock";
2437 + clocks = <&pclk_ck>;
2438 + reg = <0x4800259c 0x4>;
2439 + bit-shift = <10>;
2440 +};
2441 +
2442 +hsotgusb_ick: hsotgusb_ick@4800259c {
2443 + #clock-cells = <0>;
2444 + compatible = "ti,am35xx-gate-clock";
2445 + clocks = <&ipss_ick>;
2446 + reg = <0x4800259c 0x4>;
2447 + ti,enable-bit = <0>;
2448 +};
2449 +
2450 +hsotgusb_fck_am35xx: hsotgusb_fck_am35xx@4800259c {
2451 + #clock-cells = <0>;
2452 + compatible = "gate-clock";
2453 + clocks = <&sys_ck>;
2454 + reg = <0x4800259c 0x4>;
2455 + bit-shift = <8>;
2456 +};
2457 +
2458 +hecc_ck: hecc_ck@4800259c {
2459 + #clock-cells = <0>;
2460 + compatible = "ti,am35xx-gate-clock";
2461 + clocks = <&sys_ck>;
2462 + reg = <0x4800259c 0x4>;
2463 + ti,enable-bit = <3>;
2464 +};
2465 +
2466 +uart4_ick_am35xx: uart4_ick_am35xx@48004a10 {
2467 + #clock-cells = <0>;
2468 + compatible = "ti,omap3-interface-clock";
2469 + clocks = <&core_l4_ick>;
2470 + reg = <0x48004a10 0x4>;
2471 + ti,enable-bit = <23>;
2472 +};
2473 +
2474 +uart4_fck_am35xx: uart4_fck_am35xx@48004a00 {
2475 + #clock-cells = <0>;
2476 + compatible = "ti,gate-clock";
2477 + clocks = <&core_48m_fck>;
2478 + reg = <0x48004a00 0x4>;
2479 + ti,enable-bit = <23>;
2480 +};
2481 --- a/arch/arm/boot/dts/am4372.dtsi
2482 +++ b/arch/arm/boot/dts/am4372.dtsi
2483 @@ -8,6 +8,7 @@
2484 * kind, whether express or implied.
2485 */
2486
2487 +#include <dt-bindings/gpio/gpio.h>
2488 #include <dt-bindings/interrupt-controller/arm-gic.h>
2489
2490 #include "skeleton.dtsi"
2491 @@ -18,12 +19,21 @@
2492
2493
2494 aliases {
2495 + i2c0 = &i2c0;
2496 + i2c1 = &i2c1;
2497 + i2c2 = &i2c2;
2498 serial0 = &uart0;
2499 + ethernet0 = &cpsw_emac0;
2500 + ethernet1 = &cpsw_emac1;
2501 };
2502
2503 cpus {
2504 + #address-cells = <1>;
2505 + #size-cells = <0>;
2506 cpu@0 {
2507 compatible = "arm,cortex-a9";
2508 + device_type = "cpu";
2509 + reg = <0>;
2510 };
2511 };
2512
2513 @@ -35,16 +45,124 @@
2514 <0x48240100 0x0100>;
2515 };
2516
2517 + l2-cache-controller@48242000 {
2518 + compatible = "arm,pl310-cache";
2519 + reg = <0x48242000 0x1000>;
2520 + cache-unified;
2521 + cache-level = <2>;
2522 + };
2523 +
2524 + am43xx_pinmux: pinmux@44e10800 {
2525 + compatible = "pinctrl-single";
2526 + reg = <0x44e10800 0x31c>;
2527 + #address-cells = <1>;
2528 + #size-cells = <0>;
2529 + pinctrl-single,register-width = <32>;
2530 + pinctrl-single,function-mask = <0xffffffff>;
2531 + };
2532 +
2533 ocp {
2534 compatible = "simple-bus";
2535 #address-cells = <1>;
2536 #size-cells = <1>;
2537 ranges;
2538 + ti,hwmods = "l3_main";
2539 + clocks = <&l3_gclk>;
2540 + clock-names = "fck";
2541 +
2542 + edma: edma@49000000 {
2543 + compatible = "ti,edma3";
2544 + ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";
2545 + reg = <0x49000000 0x10000>,
2546 + <0x44e10f90 0x10>;
2547 + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
2548 + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
2549 + <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
2550 + #dma-cells = <1>;
2551 + dma-channels = <64>;
2552 + ti,edma-regions = <4>;
2553 + ti,edma-slots = <256>;
2554 + };
2555
2556 uart0: serial@44e09000 {
2557 compatible = "ti,am4372-uart","ti,omap2-uart";
2558 reg = <0x44e09000 0x2000>;
2559 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
2560 + ti,hwmods = "uart1";
2561 + clocks = <&dpll_per_m2_div4_wkupdm_ck>;
2562 + clock-names = "fck";
2563 + };
2564 +
2565 + uart1: serial@48022000 {
2566 + compatible = "ti,am4372-uart","ti,omap2-uart";
2567 + reg = <0x48022000 0x2000>;
2568 + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
2569 + ti,hwmods = "uart2";
2570 + clocks = <&dpll_per_m2_div4_ck>;
2571 + clock-names = "fck";
2572 + status = "disabled";
2573 + };
2574 +
2575 + uart2: serial@48024000 {
2576 + compatible = "ti,am4372-uart","ti,omap2-uart";
2577 + reg = <0x48024000 0x2000>;
2578 + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
2579 + ti,hwmods = "uart3";
2580 + clocks = <&dpll_per_m2_div4_ck>;
2581 + clock-names = "fck";
2582 + status = "disabled";
2583 + };
2584 +
2585 + uart3: serial@481a6000 {
2586 + compatible = "ti,am4372-uart","ti,omap2-uart";
2587 + reg = <0x481a6000 0x2000>;
2588 + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
2589 + ti,hwmods = "uart4";
2590 + clocks = <&dpll_per_m2_div4_ck>;
2591 + clock-names = "fck";
2592 + status = "disabled";
2593 + };
2594 +
2595 + uart4: serial@481a8000 {
2596 + compatible = "ti,am4372-uart","ti,omap2-uart";
2597 + reg = <0x481a8000 0x2000>;
2598 + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
2599 + ti,hwmods = "uart5";
2600 + clocks = <&dpll_per_m2_div4_ck>;
2601 + clock-names = "fck";
2602 + status = "disabled";
2603 + };
2604 +
2605 + uart5: serial@481aa000 {
2606 + compatible = "ti,am4372-uart","ti,omap2-uart";
2607 + reg = <0x481aa000 0x2000>;
2608 + interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
2609 + ti,hwmods = "uart6";
2610 + clocks = <&dpll_per_m2_div4_ck>;
2611 + clock-names = "fck";
2612 + status = "disabled";
2613 + };
2614 +
2615 + mailbox: mailbox@480C8000 {
2616 + compatible = "ti,omap4-mailbox";
2617 + reg = <0x480C8000 0x200>;
2618 + interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
2619 + ti,hwmods = "mailbox";
2620 + ti,mbox-num-users = <4>;
2621 + ti,mbox-num-fifos = <8>;
2622 + ti,mbox-names = "wkup_m3";
2623 + ti,mbox-data = <0 0 0 0>;
2624 + };
2625 +
2626 + qspi: qspi@47900000 {
2627 + compatible = "ti,am4372-qspi";
2628 + reg = <0x47900000 0x100>;
2629 + #address-cells = <1>;
2630 + #size-cells = <0>;
2631 + ti,hwmods = "qspi";
2632 + interrupts = <0 138 0x4>;
2633 + num-cs = <4>;
2634 + mmap_read;
2635 };
2636
2637 timer1: timer@44e31000 {
2638 @@ -52,17 +170,818 @@
2639 reg = <0x44e31000 0x400>;
2640 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
2641 ti,timer-alwon;
2642 + ti,hwmods = "timer1";
2643 + clocks = <&timer1_fck>;
2644 + clock-names = "fck";
2645 };
2646
2647 timer2: timer@48040000 {
2648 compatible = "ti,am4372-timer","ti,am335x-timer";
2649 reg = <0x48040000 0x400>;
2650 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
2651 + ti,hwmods = "timer2";
2652 + clocks = <&timer2_fck>;
2653 + clock-names = "fck";
2654 + };
2655 +
2656 + timer3: timer@48042000 {
2657 + compatible = "ti,am4372-timer","ti,am335x-timer";
2658 + reg = <0x48042000 0x400>;
2659 + interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
2660 + ti,hwmods = "timer3";
2661 + clocks = <&timer3_fck>;
2662 + clock-names = "fck";
2663 + status = "disabled";
2664 + };
2665 +
2666 + timer4: timer@48044000 {
2667 + compatible = "ti,am4372-timer","ti,am335x-timer";
2668 + reg = <0x48044000 0x400>;
2669 + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
2670 + ti,timer-pwm;
2671 + ti,hwmods = "timer4";
2672 + clocks = <&timer4_fck>;
2673 + clock-names = "fck";
2674 + status = "disabled";
2675 + };
2676 +
2677 + timer5: timer@48046000 {
2678 + compatible = "ti,am4372-timer","ti,am335x-timer";
2679 + reg = <0x48046000 0x400>;
2680 + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
2681 + ti,timer-pwm;
2682 + ti,hwmods = "timer5";
2683 + clocks = <&timer5_fck>;
2684 + clock-names = "fck";
2685 + status = "disabled";
2686 + };
2687 +
2688 + timer6: timer@48048000 {
2689 + compatible = "ti,am4372-timer","ti,am335x-timer";
2690 + reg = <0x48048000 0x400>;
2691 + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
2692 + ti,timer-pwm;
2693 + ti,hwmods = "timer6";
2694 + clocks = <&timer6_fck>;
2695 + clock-names = "fck";
2696 + status = "disabled";
2697 + };
2698 +
2699 + timer7: timer@4804a000 {
2700 + compatible = "ti,am4372-timer","ti,am335x-timer";
2701 + reg = <0x4804a000 0x400>;
2702 + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
2703 + ti,timer-pwm;
2704 + ti,hwmods = "timer7";
2705 + clocks = <&timer7_fck>;
2706 + clock-names = "fck";
2707 + status = "disabled";
2708 + };
2709 +
2710 + timer8: timer@481c1000 {
2711 + compatible = "ti,am4372-timer","ti,am335x-timer";
2712 + reg = <0x481c1000 0x400>;
2713 + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
2714 + ti,hwmods = "timer8";
2715 + clocks = <&timer8_fck>;
2716 + clock-names = "fck";
2717 + status = "disabled";
2718 + };
2719 +
2720 + timer9: timer@4833d000 {
2721 + compatible = "ti,am4372-timer","ti,am335x-timer";
2722 + reg = <0x4833d000 0x400>;
2723 + interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
2724 + ti,hwmods = "timer9";
2725 + clocks = <&timer9_fck>;
2726 + clock-names = "fck";
2727 + status = "disabled";
2728 + };
2729 +
2730 + timer10: timer@4833f000 {
2731 + compatible = "ti,am4372-timer","ti,am335x-timer";
2732 + reg = <0x4833f000 0x400>;
2733 + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
2734 + ti,hwmods = "timer10";
2735 + clocks = <&timer10_fck>;
2736 + clock-names = "fck";
2737 + status = "disabled";
2738 + };
2739 +
2740 + timer11: timer@48341000 {
2741 + compatible = "ti,am4372-timer","ti,am335x-timer";
2742 + reg = <0x48341000 0x400>;
2743 + interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
2744 + ti,hwmods = "timer11";
2745 + clocks = <&timer11_fck>;
2746 + clock-names = "fck";
2747 + status = "disabled";
2748 };
2749
2750 counter32k: counter@44e86000 {
2751 compatible = "ti,am4372-counter32k","ti,omap-counter32k";
2752 reg = <0x44e86000 0x40>;
2753 + ti,hwmods = "counter_32k";
2754 + clocks = <&synctimer_32kclk>;
2755 + clock-names = "fck";
2756 + };
2757 +
2758 + rtc: rtc@44e3e000 {
2759 + compatible = "ti,am4372-rtc","ti,da830-rtc";
2760 + reg = <0x44e3e000 0x1000>;
2761 + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH
2762 + GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
2763 + ti,hwmods = "rtc";
2764 + clocks = <&clk_32768_ck>;
2765 + clock-names = "fck";
2766 + status = "disabled";
2767 + };
2768 +
2769 + wdt@44e35000 {
2770 + compatible = "ti,am4372-wdt","ti,omap3-wdt";
2771 + reg = <0x44e35000 0x1000>;
2772 + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
2773 + ti,hwmods = "wd_timer2";
2774 + clocks = <&wdt1_fck>;
2775 + clock-names = "fck";
2776 + };
2777 +
2778 + gpio0: gpio@44e07000 {
2779 + compatible = "ti,am4372-gpio","ti,omap4-gpio";
2780 + reg = <0x44e07000 0x1000>;
2781 + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
2782 + gpio-controller;
2783 + #gpio-cells = <2>;
2784 + interrupt-controller;
2785 + #interrupt-cells = <2>;
2786 + ti,hwmods = "gpio1";
2787 + clocks = <&sys_clkin_ck>, <&gpio0_dbclk>;
2788 + clock-names = "fck", "dbclk";
2789 + status = "disabled";
2790 + };
2791 +
2792 + gpio1: gpio@4804c000 {
2793 + compatible = "ti,am4372-gpio","ti,omap4-gpio";
2794 + reg = <0x4804c000 0x1000>;
2795 + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
2796 + gpio-controller;
2797 + #gpio-cells = <2>;
2798 + interrupt-controller;
2799 + #interrupt-cells = <2>;
2800 + ti,hwmods = "gpio2";
2801 + clocks = <&l4ls_gclk>, <&gpio1_dbclk>;
2802 + clock-names = "fck", "dbclk";
2803 + status = "disabled";
2804 + };
2805 +
2806 + gpio2: gpio@481ac000 {
2807 + compatible = "ti,am4372-gpio","ti,omap4-gpio";
2808 + reg = <0x481ac000 0x1000>;
2809 + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
2810 + gpio-controller;
2811 + #gpio-cells = <2>;
2812 + interrupt-controller;
2813 + #interrupt-cells = <2>;
2814 + ti,hwmods = "gpio3";
2815 + clocks = <&l4ls_gclk>, <&gpio2_dbclk>;
2816 + clock-names = "fck", "dbclk";
2817 + status = "disabled";
2818 + };
2819 +
2820 + gpio3: gpio@481ae000 {
2821 + compatible = "ti,am4372-gpio","ti,omap4-gpio";
2822 + reg = <0x481ae000 0x1000>;
2823 + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
2824 + gpio-controller;
2825 + #gpio-cells = <2>;
2826 + interrupt-controller;
2827 + #interrupt-cells = <2>;
2828 + ti,hwmods = "gpio4";
2829 + clocks = <&l4ls_gclk>, <&gpio3_dbclk>;
2830 + clock-names = "fck", "dbclk";
2831 + status = "disabled";
2832 + };
2833 +
2834 + gpio4: gpio@48320000 {
2835 + compatible = "ti,am4372-gpio","ti,omap4-gpio";
2836 + reg = <0x48320000 0x1000>;
2837 + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
2838 + gpio-controller;
2839 + #gpio-cells = <2>;
2840 + interrupt-controller;
2841 + #interrupt-cells = <2>;
2842 + ti,hwmods = "gpio5";
2843 + clocks = <&l4ls_gclk>, <&gpio4_dbclk>;
2844 + clock-names = "fck", "dbclk";
2845 + status = "disabled";
2846 + };
2847 +
2848 + gpio5: gpio@48322000 {
2849 + compatible = "ti,am4372-gpio","ti,omap4-gpio";
2850 + reg = <0x48322000 0x1000>;
2851 + interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2852 + gpio-controller;
2853 + #gpio-cells = <2>;
2854 + interrupt-controller;
2855 + #interrupt-cells = <2>;
2856 + ti,hwmods = "gpio6";
2857 + clocks = <&l4ls_gclk>, <&gpio5_dbclk>;
2858 + clock-names = "fck", "dbclk";
2859 + status = "disabled";
2860 + };
2861 +
2862 + i2c0: i2c@44e0b000 {
2863 + compatible = "ti,am4372-i2c","ti,omap4-i2c";
2864 + reg = <0x44e0b000 0x1000>;
2865 + interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
2866 + ti,hwmods = "i2c1";
2867 + clocks = <&dpll_per_m2_div4_wkupdm_ck>;
2868 + clock-names = "fck";
2869 + #address-cells = <1>;
2870 + #size-cells = <0>;
2871 + status = "disabled";
2872 +
2873 + tps: tps@24 {
2874 + reg = <0x24>;
2875 + };
2876 + };
2877 +
2878 + i2c1: i2c@4802a000 {
2879 + compatible = "ti,am4372-i2c","ti,omap4-i2c";
2880 + reg = <0x4802a000 0x1000>;
2881 + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
2882 + ti,hwmods = "i2c2";
2883 + clocks = <&dpll_per_m2_div4_ck>;
2884 + clock-names = "fck";
2885 + #address-cells = <1>;
2886 + #size-cells = <0>;
2887 + status = "disabled";
2888 + };
2889 +
2890 + i2c2: i2c@4819c000 {
2891 + compatible = "ti,am4372-i2c","ti,omap4-i2c";
2892 + reg = <0x4819c000 0x1000>;
2893 + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
2894 + ti,hwmods = "i2c3";
2895 + clocks = <&dpll_per_m2_div4_ck>;
2896 + clock-names = "fck";
2897 + #address-cells = <1>;
2898 + #size-cells = <0>;
2899 + status = "disabled";
2900 + };
2901 +
2902 + spi0: spi@48030000 {
2903 + compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
2904 + reg = <0x48030000 0x400>;
2905 + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
2906 + ti,hwmods = "spi0";
2907 + clocks = <&dpll_per_m2_div4_ck>;
2908 + clock-names = "fck";
2909 + #address-cells = <1>;
2910 + #size-cells = <0>;
2911 + status = "disabled";
2912 };
2913 +
2914 + mmc1: mmc@48060000 {
2915 + compatible = "ti,omap4-hsmmc";
2916 + reg = <0x48060000 0x1000>;
2917 + ti,hwmods = "mmc1";
2918 + clocks = <&mmc_clk>, <&clkdiv32k_ick>;
2919 + clock-names = "fck", "mmchsdb_fck";
2920 + ti,dual-volt;
2921 + ti,needs-special-reset;
2922 + dmas = <&edma 24
2923 + &edma 25>;
2924 + dma-names = "tx", "rx";
2925 + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
2926 + status = "disabled";
2927 + };
2928 +
2929 + mmc2: mmc@481d8000 {
2930 + compatible = "ti,omap4-hsmmc";
2931 + reg = <0x481d8000 0x1000>;
2932 + ti,hwmods = "mmc2";
2933 + clocks = <&mmc_clk>, <&clkdiv32k_ick>;
2934 + clock-names = "fck", "mmchsdb_fck";
2935 + ti,needs-special-reset;
2936 + dmas = <&edma 2
2937 + &edma 3>;
2938 + dma-names = "tx", "rx";
2939 + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
2940 + status = "disabled";
2941 + };
2942 +
2943 + mmc3: mmc@47810000 {
2944 + compatible = "ti,omap4-hsmmc";
2945 + reg = <0x47810000 0x1000>;
2946 + ti,hwmods = "mmc3";
2947 + clocks = <&mmc_clk>, <&clkdiv32k_ick>;
2948 + clock-names = "fck", "mmchsdb_fck";
2949 + ti,needs-special-reset;
2950 + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
2951 + status = "disabled";
2952 + };
2953 +
2954 + spi1: spi@481a0000 {
2955 + compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
2956 + reg = <0x481a0000 0x400>;
2957 + interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
2958 + ti,hwmods = "spi1";
2959 + clocks = <&dpll_per_m2_div4_ck>;
2960 + clock-names = "fck";
2961 + #address-cells = <1>;
2962 + #size-cells = <0>;
2963 + status = "disabled";
2964 + };
2965 +
2966 + spi2: spi@481a2000 {
2967 + compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
2968 + reg = <0x481a2000 0x400>;
2969 + interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
2970 + ti,hwmods = "spi2";
2971 + clocks = <&dpll_per_m2_div4_ck>;
2972 + clock-names = "fck";
2973 + #address-cells = <1>;
2974 + #size-cells = <0>;
2975 + status = "disabled";
2976 + };
2977 +
2978 + spi3: spi@481a4000 {
2979 + compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
2980 + reg = <0x481a4000 0x400>;
2981 + interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
2982 + ti,hwmods = "spi3";
2983 + clocks = <&dpll_per_m2_div4_ck>;
2984 + clock-names = "fck";
2985 + #address-cells = <1>;
2986 + #size-cells = <0>;
2987 + status = "disabled";
2988 + };
2989 +
2990 + spi4: spi@48345000 {
2991 + compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
2992 + reg = <0x48345000 0x400>;
2993 + interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
2994 + ti,hwmods = "spi4";
2995 + clocks = <&dpll_per_m2_div4_ck>;
2996 + clock-names = "fck";
2997 + #address-cells = <1>;
2998 + #size-cells = <0>;
2999 + status = "disabled";
3000 + };
3001 +
3002 + mac: ethernet@4a100000 {
3003 + compatible = "ti,am4372-cpsw","ti,cpsw";
3004 + reg = <0x4a100000 0x800
3005 + 0x4a101200 0x100>;
3006 + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH
3007 + GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH
3008 + GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH
3009 + GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
3010 + #address-cells = <1>;
3011 + #size-cells = <1>;
3012 + ti,hwmods = "cpgmac0";
3013 + clocks = <&cpsw_125mhz_gclk>;
3014 + clock-names = "fck";
3015 + cpdma_channels = <8>;
3016 + ale_entries = <1024>;
3017 + bd_ram_size = <0x2000>;
3018 + no_bd_ram = <0>;
3019 + rx_descs = <64>;
3020 + mac_control = <0x20>;
3021 + slaves = <2>;
3022 + active_slave = <0>;
3023 + cpts_clock_mult = <0x80000000>;
3024 + cpts_clock_shift = <29>;
3025 + ranges;
3026 + status = "disabled";
3027 +
3028 + davinci_mdio: mdio@4a101000 {
3029 + compatible = "ti,am4372-mdio","ti,davinci_mdio";
3030 + reg = <0x4a101000 0x100>;
3031 + #address-cells = <1>;
3032 + #size-cells = <0>;
3033 + ti,hwmods = "davinci_mdio";
3034 + clocks = <&cpsw_125mhz_gclk>;
3035 + clock-names = "fck";
3036 + bus_freq = <1000000>;
3037 + status = "disabled";
3038 + };
3039 +
3040 + cpsw_emac0: slave@4a100200 {
3041 + /* Filled in by U-Boot */
3042 + mac-address = [ 00 00 00 00 00 00 ];
3043 + };
3044 +
3045 + cpsw_emac1: slave@4a100300 {
3046 + /* Filled in by U-Boot */
3047 + mac-address = [ 00 00 00 00 00 00 ];
3048 + };
3049 +
3050 + phy_sel: cpsw-phy-sel@44e10650 {
3051 + compatible = "ti,am3352-cpsw-phy-sel";
3052 + reg= <0x44e10650 0x4>;
3053 + reg-names = "gmii-sel";
3054 + };
3055 + };
3056 +
3057 + epwmss0: epwmss@48300000 {
3058 + compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
3059 + reg = <0x48300000 0x10>;
3060 + #address-cells = <1>;
3061 + #size-cells = <1>;
3062 + ranges;
3063 + ti,hwmods = "epwmss0";
3064 + clocks = <&l4ls_gclk>;
3065 + clock-names = "fck";
3066 + status = "disabled";
3067 +
3068 + ecap0: ecap@48300100 {
3069 + compatible = "ti,am4372-ecap","ti,am33xx-ecap";
3070 + reg = <0x48300100 0x80>;
3071 + ti,hwmods = "ecap0";
3072 + clocks = <&l4ls_gclk>;
3073 + clock-names = "fck";
3074 + status = "disabled";
3075 + };
3076 +
3077 + ehrpwm0: ehrpwm@48300200 {
3078 + compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
3079 + reg = <0x48300200 0x80>;
3080 + ti,hwmods = "ehrpwm0";
3081 + clocks = <&l4ls_gclk>;
3082 + clock-names = "fck";
3083 + status = "disabled";
3084 + };
3085 + };
3086 +
3087 + epwmss1: epwmss@48302000 {
3088 + compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
3089 + reg = <0x48302000 0x10>;
3090 + #address-cells = <1>;
3091 + #size-cells = <1>;
3092 + ranges;
3093 + ti,hwmods = "epwmss1";
3094 + clocks = <&l4ls_gclk>;
3095 + clock-names = "fck";
3096 + status = "disabled";
3097 +
3098 + ecap1: ecap@48302100 {
3099 + compatible = "ti,am4372-ecap","ti,am33xx-ecap";
3100 + reg = <0x48302100 0x80>;
3101 + ti,hwmods = "ecap1";
3102 + clocks = <&l4ls_gclk>;
3103 + clock-names = "fck";
3104 + status = "disabled";
3105 + };
3106 +
3107 + ehrpwm1: ehrpwm@48302200 {
3108 + compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
3109 + reg = <0x48302200 0x80>;
3110 + ti,hwmods = "ehrpwm1";
3111 + clocks = <&l4ls_gclk>;
3112 + clock-names = "fck";
3113 + status = "disabled";
3114 + };
3115 + };
3116 +
3117 + epwmss2: epwmss@48304000 {
3118 + compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
3119 + reg = <0x48304000 0x10>;
3120 + #address-cells = <1>;
3121 + #size-cells = <1>;
3122 + ranges;
3123 + ti,hwmods = "epwmss2";
3124 + clocks = <&l4ls_gclk>;
3125 + clock-names = "fck";
3126 + status = "disabled";
3127 +
3128 + ecap2: ecap@48304100 {
3129 + compatible = "ti,am4372-ecap","ti,am33xx-ecap";
3130 + reg = <0x48304100 0x80>;
3131 + ti,hwmods = "ecap2";
3132 + clocks = <&l4ls_gclk>;
3133 + clock-names = "fck";
3134 + status = "disabled";
3135 + };
3136 +
3137 + ehrpwm2: ehrpwm@48304200 {
3138 + compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
3139 + reg = <0x48304200 0x80>;
3140 + ti,hwmods = "ehrpwm2";
3141 + clocks = <&l4ls_gclk>;
3142 + clock-names = "fck";
3143 + status = "disabled";
3144 + };
3145 + };
3146 +
3147 + epwmss3: epwmss@48306000 {
3148 + compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
3149 + reg = <0x48306000 0x10>;
3150 + #address-cells = <1>;
3151 + #size-cells = <1>;
3152 + ranges;
3153 + ti,hwmods = "epwmss3";
3154 + clocks = <&l4ls_gclk>;
3155 + clock-names = "fck";
3156 + status = "disabled";
3157 +
3158 + ehrpwm3: ehrpwm@48306200 {
3159 + compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
3160 + reg = <0x48306200 0x80>;
3161 + ti,hwmods = "ehrpwm3";
3162 + clocks = <&l4ls_gclk>;
3163 + clock-names = "fck";
3164 + status = "disabled";
3165 + };
3166 + };
3167 +
3168 + epwmss4: epwmss@48308000 {
3169 + compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
3170 + reg = <0x48308000 0x10>;
3171 + #address-cells = <1>;
3172 + #size-cells = <1>;
3173 + ranges;
3174 + ti,hwmods = "epwmss4";
3175 + clocks = <&l4ls_gclk>;
3176 + clock-names = "fck";
3177 + status = "disabled";
3178 +
3179 + ehrpwm4: ehrpwm@48308200 {
3180 + compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
3181 + reg = <0x48308200 0x80>;
3182 + ti,hwmods = "ehrpwm4";
3183 + clocks = <&l4ls_gclk>;
3184 + clock-names = "fck";
3185 + status = "disabled";
3186 + };
3187 + };
3188 +
3189 + epwmss5: epwmss@4830a000 {
3190 + compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
3191 + reg = <0x4830a000 0x10>;
3192 + #address-cells = <1>;
3193 + #size-cells = <1>;
3194 + ranges;
3195 + ti,hwmods = "epwmss5";
3196 + clocks = <&l4ls_gclk>;
3197 + clock-names = "fck";
3198 + status = "disabled";
3199 +
3200 + ehrpwm5: ehrpwm@4830a200 {
3201 + compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
3202 + reg = <0x4830a200 0x80>;
3203 + ti,hwmods = "ehrpwm5";
3204 + clocks = <&l4ls_gclk>;
3205 + clock-names = "fck";
3206 + status = "disabled";
3207 + };
3208 + };
3209 +
3210 + wkup_m3: wkup_m3@44d00000 {
3211 + compatible = "ti,am4372-wkup-m3","ti,am3353-wkup-m3";
3212 + reg = <0x44d00000 0x4000 /* M3 UMEM */
3213 + 0x44d80000 0x2000>; /* M3 DMEM */
3214 + ti,hwmods = "wkup_m3";
3215 + clocks = <&sys_clkin_ck>;
3216 + clock-names = "fck";
3217 + status = "disabled";
3218 + };
3219 +
3220 + tscadc: tscadc@44e0d000 {
3221 + compatible = "ti,am4372-tscadc","ti,am3359-tscadc";
3222 + reg = <0x44e0d000 0x1000>;
3223 + ti,hwmods = "adc_tsc";
3224 + clocks = <&adc_tsc_fck>;
3225 + clock-names = "fck";
3226 + status = "disabled";
3227 + };
3228 +
3229 + ocmcram: ocmcram@40300000 {
3230 + compatible = "ti,am4372-ocmcram","ti,am3352-ocmcram";
3231 + reg = <0x40300000 0x40000>;
3232 + ti,hwmods = "ocmcram";
3233 + clocks = <&l3_gclk>;
3234 + clock-names = "fck";
3235 + status = "disabled";
3236 + };
3237 +
3238 + dcan0: d_can@481cc000 {
3239 + compatible = "bosch,d_can";
3240 + ti,hwmods = "d_can0";
3241 + clocks = <&dcan0_fck>;
3242 + clock-names = "fck";
3243 + reg = <0x481cc000 0x2000
3244 + 0x44e10644 0x4>;
3245 + status = "disabled";
3246 + };
3247 +
3248 + dcan1: d_can@481d0000 {
3249 + compatible = "bosch,d_can";
3250 + ti,hwmods = "d_can1";
3251 + clocks = <&dcan1_fck>;
3252 + clock-names = "fck";
3253 + reg = <0x481d0000 0x2000
3254 + 0x44e10644 0x4>;
3255 + status = "disabled";
3256 + };
3257 +
3258 + elm: elm@48080000 {
3259 + compatible = "ti,am4372-elm","ti,am3352-elm";
3260 + reg = <0x48080000 0x2000>;
3261 + ti,hwmods = "elm";
3262 + clocks = <&l4ls_gclk>;
3263 + clock-names = "fck";
3264 + status = "disabled";
3265 + };
3266 +
3267 + gpmc: gpmc@50000000 {
3268 + compatible = "ti,am4372-gpmc","ti,am3352-gpmc";
3269 + ti,hwmods = "gpmc";
3270 + clocks = <&l3s_gclk>;
3271 + clock-names = "fck";
3272 + reg = <0x50000000 0x2000>;
3273 + status = "disabled";
3274 + };
3275 +
3276 + prcm: prcm@44df0000 {
3277 + compatible = "ti,am4372-prcm";
3278 + reg = <0x44df0000 0xa000>;
3279 + #reset-cells = <1>;
3280 + };
3281 +
3282 + rng: rng@48310000 {
3283 + compatible = "ti,omap4-rng";
3284 + ti,hwmods = "rng";
3285 + reg = <0x48310000 0x2000>;
3286 + interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
3287 + clocks = <&rng_fck>;
3288 + clock-names = "fck";
3289 + };
3290 +
3291 + sham: sham@53100000 {
3292 + compatible = "ti,omap5-sham";
3293 + ti,hwmods = "sham";
3294 + reg = <0x53100000 0x300>;
3295 + dmas = <&edma 36>;
3296 + dma-names = "rx";
3297 + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
3298 + clocks = <&l3_gclk>;
3299 + clock-names = "fck";
3300 + };
3301 +
3302 + aes: aes@53501000 {
3303 + compatible = "ti,omap4-aes";
3304 + ti,hwmods = "aes";
3305 + reg = <0x53501000 0xa0>;
3306 + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
3307 + dmas = <&edma 6
3308 + &edma 5>;
3309 + dma-names = "tx", "rx";
3310 + clocks = <&aes0_fck>;
3311 + clock-names = "fck";
3312 + };
3313 +
3314 + des: des@53701000 {
3315 + compatible = "ti,omap4-des";
3316 + ti,hwmods = "des";
3317 + reg = <0x53701000 0xa0>;
3318 + interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
3319 + dmas = <&edma 34
3320 + &edma 33>;
3321 + dma-names = "tx", "rx";
3322 + clocks = <&l3_gclk>;
3323 + clock-names = "fck";
3324 + };
3325 +
3326 + am43xx_control_usb2phy1: control-phy@44e10620 {
3327 + compatible = "ti,control-phy-am437usb2";
3328 + reg = <0x44e10620 0x4>;
3329 + reg-names = "power";
3330 + };
3331 +
3332 + am43xx_control_usb2phy2: control-phy@0x44e10628 {
3333 + compatible = "ti,control-phy-am437usb2";
3334 + reg = <0x44e10628 0x4>;
3335 + reg-names = "power";
3336 + };
3337 +
3338 + ocp2scp0: ocp2scp@483a8000 {
3339 + compatible = "ti,omap-ocp2scp";
3340 + #address-cells = <1>;
3341 + #size-cells = <1>;
3342 + ranges;
3343 + ti,hwmods = "ocp2scp0";
3344 +
3345 + usb2_phy1: usb2phy1@483a8000 {
3346 + compatible = "ti,am437x-usb2";
3347 + reg = <0x483a8000 0x8000>;
3348 + ctrl-module = <&am43xx_control_usb2phy1>;
3349 + clocks = <&clk_32768_ck>,
3350 + <&usb_otg_ss0_refclk960m>;
3351 + clock-names = "wkupclk",
3352 + "refclk";
3353 + #phy-cells = <0>;
3354 + };
3355 +
3356 + };
3357 +
3358 + ocp2scp1: ocp2scp@483e8000 {
3359 + compatible = "ti,omap-ocp2scp";
3360 + #address-cells = <1>;
3361 + #size-cells = <1>;
3362 + ranges;
3363 + ti,hwmods = "ocp2scp1";
3364 +
3365 + usb2_phy2: usb2phy2@483e8000 {
3366 + compatible = "ti,am437x-usb2";
3367 + reg = <0x483e8000 0x8000>;
3368 + ctrl-module = <&am43xx_control_usb2phy2>;
3369 + clocks = <&clk_32768_ck>,
3370 + <&usb_otg_ss1_refclk960m>;
3371 + clock-names = "wkupclk",
3372 + "refclk";
3373 + #phy-cells = <0>;
3374 + };
3375 +
3376 + };
3377 +
3378 + dwc3_1: omap_dwc3_1@48380000 {
3379 + compatible = "ti,am437x-dwc3";
3380 + ti,hwmods = "usb_otg_ss0";
3381 + reg = <0x48380000 0x10000>;
3382 + interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
3383 + #address-cells = <1>;
3384 + #size-cells = <1>;
3385 + utmi-mode = <1>;
3386 + ranges;
3387 + usb1: usb@48390000 {
3388 + compatible = "synopsys,dwc3";
3389 + reg = <0x48390000 0x17000>;
3390 + interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
3391 + phys = <&usb2_phy1>;
3392 + phy-names = "usb2-phy";
3393 + maximum-speed = "high-speed";
3394 + dr_mode = "peripheral";
3395 + };
3396 + };
3397 +
3398 + dwc3_2: omap_dwc3_2@483c0000 {
3399 + compatible = "ti,am437x-dwc3";
3400 + ti,hwmods = "usb_otg_ss1";
3401 + reg = <0x483c0000 0x10000>;
3402 + interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
3403 + #address-cells = <1>;
3404 + #size-cells = <1>;
3405 + utmi-mode = <1>;
3406 + ranges;
3407 + usb2: usb@483d0000 {
3408 + compatible = "synopsys,dwc3";
3409 + reg = <0x483d0000 0x17000>;
3410 + interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
3411 + phys = <&usb2_phy2>;
3412 + phy-names = "usb2-phy";
3413 + maximum-speed = "high-speed";
3414 + dr_mode = "host";
3415 + };
3416 + };
3417 +
3418 + dss: dss@4832A000 {
3419 + compatible = "ti,omap3-dss", "simple-bus";
3420 + reg = <0x4832A000 0x200>;
3421 + ti,hwmods = "dss_core";
3422 + #address-cells = <1>;
3423 + #size-cells = <1>;
3424 + ranges;
3425 +
3426 + dispc@4832A400 {
3427 + compatible = "ti,omap3-dispc";
3428 + reg = <0x4832A400 0x400>;
3429 + interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
3430 + ti,hwmods = "dss_dispc";
3431 + };
3432 +
3433 + dpi: encoder@0 {
3434 + compatible = "ti,omap3-dpi";
3435 + };
3436 +
3437 + rfbi: rfbi@4832A800 {
3438 + compatible = "ti,omap3-rfbi";
3439 + reg = <0x4832A800 0x100>;
3440 + ti,hwmods = "dss_rfbi";
3441 + };
3442 +
3443 + };
3444 +
3445 };
3446 +
3447 + clocks {
3448 + #address-cells = <1>;
3449 + #size-cells = <1>;
3450 + ranges;
3451 + /include/ "am43xx-clocks.dtsi"
3452 + };
3453 +
3454 };
3455 +
3456 +/include/ "tps65218.dtsi"
3457 --- /dev/null
3458 +++ b/arch/arm/boot/dts/am437x-gp-evm.dts
3459 @@ -0,0 +1,238 @@
3460 +/*
3461 + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
3462 + *
3463 + * This program is free software; you can redistribute it and/or modify
3464 + * it under the terms of the GNU General Public License version 2 as
3465 + * published by the Free Software Foundation.
3466 + */
3467 +
3468 +/* AM437x GP EVM */
3469 +
3470 +/dts-v1/;
3471 +
3472 +#include "am43x-common-evm.dtsi"
3473 +#include <dt-bindings/pinctrl/am43xx.h>
3474 +
3475 +/ {
3476 + model = "TI AM437x gp EVM";
3477 + compatible = "ti,am437x-gp-evm","ti,am4372","ti,am43";
3478 +
3479 + vmmcsd_fixed: fixedregulator-sd {
3480 + compatible = "regulator-fixed";
3481 + regulator-name = "vmmcsd_fixed";
3482 + regulator-min-microvolt = <3300000>;
3483 + regulator-max-microvolt = <3300000>;
3484 + enable-active-high;
3485 + };
3486 +
3487 + aliases {
3488 + display0 = &lcd0;
3489 + display1 = &hdmi0;
3490 + };
3491 +
3492 + lcd0: display@0 {
3493 + compatible = "osddisplays,osd057T0559-34ts", "panel-dpi";
3494 + video-source = <&dpi>;
3495 + data-lines = <24>;
3496 + gpios = <0 /* No Enable GPIO */
3497 + &gpio0 7 GPIO_ACTIVE_LOW>; /* LCD backlight GPIO */
3498 + activelow_backlight; /* LCD backlight is Active low */
3499 + panel-timing {
3500 + clock-frequency = <33000000>;
3501 + hactive = <800>;
3502 + vactive = <480>;
3503 + hfront-porch = <210>;
3504 + hback-porch = <16>;
3505 + hsync-len = <30>;
3506 + vback-porch = <10>;
3507 + vfront-porch = <22>;
3508 + vsync-len = <13>;
3509 + hsync-active = <0>;
3510 + vsync-active = <0>;
3511 + de-active = <1>;
3512 + pixelclk-active = <1>;
3513 + };
3514 + };
3515 +
3516 + hdmi0: connector@1 {
3517 + compatible = "ti,hdmi_connector";
3518 + video-source = <&sii9022>;
3519 + };
3520 +};
3521 +
3522 +&am43xx_pinmux {
3523 + pinctrl-names = "default";
3524 + pinctrl-0 = <&dss_pinctrl>;
3525 + cpsw_default: cpsw_default {
3526 + pinctrl-single,pins = <
3527 + /* Slave 1 */
3528 + 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_txen */
3529 + 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rxctl */
3530 + 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd3 */
3531 + 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd2 */
3532 + 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd1 */
3533 + 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd0 */
3534 + 0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rmii1_tclk */
3535 + 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */
3536 + 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd3 */
3537 + 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd2 */
3538 + 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd1 */
3539 + 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd0 */
3540 + >;
3541 + };
3542 +
3543 + cpsw_sleep: cpsw_sleep {
3544 + pinctrl-single,pins = <
3545 + /* Slave 1 reset value */
3546 + 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE7)
3547 + 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
3548 + 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
3549 + 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
3550 + 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
3551 + 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
3552 + 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
3553 + 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
3554 + 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
3555 + 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
3556 + 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
3557 + 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
3558 + 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
3559 + >;
3560 + };
3561 +
3562 + davinci_mdio_default: davinci_mdio_default {
3563 + pinctrl-single,pins = <
3564 + /* MDIO */
3565 + 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
3566 + 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
3567 + >;
3568 + };
3569 +
3570 + davinci_mdio_sleep: davinci_mdio_sleep {
3571 + pinctrl-single,pins = <
3572 + /* MDIO reset value */
3573 + 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
3574 + 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
3575 + >;
3576 + };
3577 +
3578 + mmc1_pins: pinmux_mmc1_pins {
3579 + pinctrl-single,pins = <
3580 + 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
3581 + >;
3582 + };
3583 +
3584 + i2c0_pins: pinmux_i2c0_pins {
3585 + pinctrl-single,pins = <
3586 + 0x188 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */
3587 + 0x18c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */
3588 + >;
3589 + };
3590 +
3591 + i2c1_pins: i2c1_pins {
3592 + pinctrl-single,pins = <
3593 + 0x15c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_cs0.i2c1_scl */
3594 + 0x158 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_d1.i2c1_sda */
3595 + >;
3596 + };
3597 +
3598 + dss_pinctrl: dss_pinctrl {
3599 + pinctrl-single,pins = <
3600 + 0x020 (PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */
3601 + 0x024 (PIN_OUTPUT_PULLUP | MUX_MODE1)
3602 + 0x028 (PIN_OUTPUT_PULLUP | MUX_MODE1)
3603 + 0x02C (PIN_OUTPUT_PULLUP | MUX_MODE1)
3604 + 0x030 (PIN_OUTPUT_PULLUP | MUX_MODE1)
3605 + 0x034 (PIN_OUTPUT_PULLUP | MUX_MODE1)
3606 + 0x038 (PIN_OUTPUT_PULLUP | MUX_MODE1)
3607 + 0x03C (PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 15 -> DSS DATA 16 */
3608 + 0x0A0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */
3609 + 0x0A4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
3610 + 0x0A8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
3611 + 0x0AC (PIN_OUTPUT_PULLUP | MUX_MODE0)
3612 + 0x0B0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
3613 + 0x0B4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
3614 + 0x0B8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
3615 + 0x0BC (PIN_OUTPUT_PULLUP | MUX_MODE0)
3616 + 0x0C0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
3617 + 0x0C4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
3618 + 0x0C8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
3619 + 0x0CC (PIN_OUTPUT_PULLUP | MUX_MODE0)
3620 + 0x0D0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
3621 + 0x0D4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
3622 + 0x0D8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
3623 + 0x0DC (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */
3624 + 0x0E0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */
3625 + 0x0E4 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */
3626 + 0x0E8 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */
3627 + 0x0EC (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */
3628 + 0x238 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* GPIO 5_8 to select LCD / HDMI */
3629 + 0x164 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* ECAP0_IN_PWM0_OUT -> GPIO 0_7 BACKLIGHT */
3630 + >;
3631 + };
3632 +};
3633 +
3634 +&rtc {
3635 + status = "okay";
3636 +};
3637 +
3638 +&gpio0 {
3639 + status = "okay";
3640 +};
3641 +
3642 +&gpio5 {
3643 + status = "okay";
3644 +};
3645 +
3646 +&mac {
3647 + pinctrl-names = "default", "sleep";
3648 + pinctrl-0 = <&cpsw_default>;
3649 + pinctrl-1 = <&cpsw_sleep>;
3650 + status = "okay";
3651 +};
3652 +
3653 +&davinci_mdio {
3654 + pinctrl-names = "default", "sleep";
3655 + pinctrl-0 = <&davinci_mdio_default>;
3656 + pinctrl-1 = <&davinci_mdio_sleep>;
3657 + status = "okay";
3658 +};
3659 +
3660 +&cpsw_emac0 {
3661 + phy_id = <&davinci_mdio>, <0>;
3662 + phy-mode = "rgmii";
3663 +};
3664 +
3665 +&cpsw_emac1 {
3666 + phy_id = <&davinci_mdio>, <1>;
3667 + phy-mode = "rgmii";
3668 +};
3669 +
3670 +&mmc1 {
3671 + status = "okay";
3672 + vmmc-supply = <&vmmcsd_fixed>;
3673 + bus-width = <4>;
3674 + pinctrl-names = "default";
3675 + pinctrl-0 = <&mmc1_pins>;
3676 + cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
3677 +};
3678 +
3679 +&i2c0 {
3680 + status = "okay";
3681 + pinctrl-names = "default";
3682 + pinctrl-0 = <&i2c0_pins>;
3683 +};
3684 +
3685 +&i2c1 {
3686 + status = "okay";
3687 + pinctrl-names = "default";
3688 + pinctrl-0 = <&i2c1_pins>;
3689 +
3690 + sii9022: sii9022@3b {
3691 + compatible = "sii,sii9022";
3692 + reg = <0x3b>;
3693 + reset-gpio = <&gpio5 8 GPIO_ACTIVE_LOW>;/* 'SelLCDorHDMI' Gpio, LOW to select HDMI */
3694 + video-source = <&dpi>;
3695 + data-lines = <24>;
3696 + };
3697 +};
3698 --- /dev/null
3699 +++ b/arch/arm/boot/dts/am43x-common-evm.dtsi
3700 @@ -0,0 +1,9 @@
3701 +/*
3702 + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
3703 + *
3704 + * This program is free software; you can redistribute it and/or modify
3705 + * it under the terms of the GNU General Public License version 2 as
3706 + * published by the Free Software Foundation.
3707 + */
3708 +
3709 +#include "am4372.dtsi"
3710 --- a/arch/arm/boot/dts/am43x-epos-evm.dts
3711 +++ b/arch/arm/boot/dts/am43x-epos-evm.dts
3712 @@ -10,9 +10,289 @@
3713
3714 /dts-v1/;
3715
3716 -#include "am4372.dtsi"
3717 +#include "am43x-common-evm.dtsi"
3718 +#include <dt-bindings/pinctrl/am43xx.h>
3719
3720 / {
3721 model = "TI AM43x EPOS EVM";
3722 compatible = "ti,am43x-epos-evm","ti,am4372","ti,am43";
3723 +
3724 + vmmcsd_fixed: fixedregulator-sd {
3725 + compatible = "regulator-fixed";
3726 + regulator-name = "vmmcsd_fixed";
3727 + regulator-min-microvolt = <3300000>;
3728 + regulator-max-microvolt = <3300000>;
3729 + enable-active-high;
3730 + };
3731 +
3732 + aliases {
3733 + display0 = &lcd0;
3734 + display1 = &hdmi0;
3735 + };
3736 +
3737 + lcd0: display@0 {
3738 + compatible = "osddisplays,osd057T0559-34ts", "panel-dpi";
3739 + video-source = <&dpi>;
3740 + data-lines = <24>;
3741 + gpios = <0 /* No Enable GPIO */
3742 + &gpio0 7 GPIO_ACTIVE_LOW>; /* LCD backlight GPIO */
3743 + panel-timing {
3744 + clock-frequency = <33000000>;
3745 + hactive = <800>;
3746 + vactive = <480>;
3747 + hfront-porch = <210>;
3748 + hback-porch = <16>;
3749 + hsync-len = <30>;
3750 + vback-porch = <10>;
3751 + vfront-porch = <22>;
3752 + vsync-len = <13>;
3753 + hsync-active = <0>;
3754 + vsync-active = <0>;
3755 + de-active = <1>;
3756 + pixelclk-active = <1>;
3757 + };
3758 + };
3759 +
3760 + hdmi0: connector@1 {
3761 + compatible = "ti,hdmi_connector";
3762 + video-source = <&sii9022>;
3763 + };
3764 +};
3765 +
3766 +&am43xx_pinmux {
3767 + pinctrl-names = "default";
3768 + pinctrl-0 = <&dss_pinctrl>;
3769 + cpsw_default: cpsw_default {
3770 + pinctrl-single,pins = <
3771 + /* Slave 1 */
3772 + 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs */
3773 + 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */
3774 + 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txen.rmii1_txen */
3775 + 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxdv.rmii1_rxdv */
3776 + 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */
3777 + 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */
3778 + 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */
3779 + 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */
3780 + 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_refclk.rmii1_refclk */
3781 + >;
3782 + };
3783 +
3784 + cpsw_sleep: cpsw_sleep {
3785 + pinctrl-single,pins = <
3786 + /* Slave 1 reset value */
3787 + 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE7)
3788 + 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7)
3789 + 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
3790 + 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
3791 + 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
3792 + 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
3793 + 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
3794 + 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
3795 + 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE7)
3796 + >;
3797 + };
3798 +
3799 + davinci_mdio_default: davinci_mdio_default {
3800 + pinctrl-single,pins = <
3801 + /* MDIO */
3802 + 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
3803 + 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
3804 + >;
3805 + };
3806 +
3807 + davinci_mdio_sleep: davinci_mdio_sleep {
3808 + pinctrl-single,pins = <
3809 + /* MDIO reset value */
3810 + 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
3811 + 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
3812 + >;
3813 + };
3814 +
3815 + mmc1_pins: pinmux_mmc1_pins {
3816 + pinctrl-single,pins = <
3817 + 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
3818 + >;
3819 + };
3820 +
3821 + i2c0_pins: pinmux_i2c0_pins {
3822 + pinctrl-single,pins = <
3823 + 0x188 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */
3824 + 0x18c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */
3825 + >;
3826 + };
3827 +
3828 + i2c2_pins: pinmux_i2c2_pins {
3829 + pinctrl-single,pins = <
3830 + 0x1c0 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c2_sda.i2c2_sda */
3831 + 0x1c4 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c2_scl.i2c2_scl */
3832 + >;
3833 + };
3834 +
3835 + spi0_pins: pinmux_spi0_pins {
3836 + pinctrl-single,pins = <
3837 + 0x150 (PIN_INPUT | MUX_MODE0) /* spi0_clk.spi0_clk */
3838 + 0x154 (PIN_OUTPUT | MUX_MODE0) /* spi0_d0.spi0_d0 */
3839 + 0x158 (PIN_INPUT | MUX_MODE0) /* spi0_d1.spi0_d1 */
3840 + 0x15c (PIN_OUTPUT | MUX_MODE0) /* spi0_cs0.spi0_cs0 */
3841 + >;
3842 + };
3843 +
3844 + spi1_pins: pinmux_spi1_pins {
3845 + pinctrl-single,pins = <
3846 + 0x190 (PIN_INPUT | MUX_MODE3) /* mcasp0_aclkx.spi1_clk */
3847 + 0x194 (PIN_OUTPUT | MUX_MODE3) /* mcasp0_fsx.spi1_d0 */
3848 + 0x198 (PIN_INPUT | MUX_MODE3) /* mcasp0_axr0.spi1_d1 */
3849 + 0x19c (PIN_OUTPUT | MUX_MODE3) /* mcasp0_ahclkr.spi1_cs0 */
3850 + >;
3851 + };
3852 +
3853 + pixcir_ts_pins: pixcir_ts_pins {
3854 + pinctrl-single,pins = <
3855 + 0x48 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_a1.gpio1_17 */
3856 + >;
3857 + };
3858 +
3859 + dss_pinctrl: dss_pinctrl {
3860 + pinctrl-single,pins = <
3861 + 0x020 (PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */
3862 + 0x024 (PIN_OUTPUT_PULLUP | MUX_MODE1)
3863 + 0x028 (PIN_OUTPUT_PULLUP | MUX_MODE1)
3864 + 0x02C (PIN_OUTPUT_PULLUP | MUX_MODE1)
3865 + 0x030 (PIN_OUTPUT_PULLUP | MUX_MODE1)
3866 + 0x034 (PIN_OUTPUT_PULLUP | MUX_MODE1)
3867 + 0x038 (PIN_OUTPUT_PULLUP | MUX_MODE1)
3868 + 0x03C (PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 15 -> DSS DATA 16 */
3869 + 0x0A0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */
3870 + 0x0A4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
3871 + 0x0A8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
3872 + 0x0AC (PIN_OUTPUT_PULLUP | MUX_MODE0)
3873 + 0x0B0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
3874 + 0x0B4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
3875 + 0x0B8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
3876 + 0x0BC (PIN_OUTPUT_PULLUP | MUX_MODE0)
3877 + 0x0C0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
3878 + 0x0C4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
3879 + 0x0C8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
3880 + 0x0CC (PIN_OUTPUT_PULLUP | MUX_MODE0)
3881 + 0x0D0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
3882 + 0x0D4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
3883 + 0x0D8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
3884 + 0x0DC (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */
3885 + 0x0E0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */
3886 + 0x0E4 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */
3887 + 0x0E8 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */
3888 + 0x0EC (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */
3889 + 0x08C (PIN_OUTPUT_PULLUP | MUX_MODE7) /* GPMC CLK -> GPIO 2_1 to select LCD / HDMI */
3890 + 0x164 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* ECAP0_IN_PWM0_OUT -> GPIO 0_7 BACKLIGHT */
3891 + >;
3892 + };
3893 +};
3894 +
3895 +&gpio0 {
3896 + status = "okay";
3897 +};
3898 +
3899 +&gpio1 {
3900 + status = "okay";
3901 +};
3902 +
3903 +&gpio2 {
3904 + status = "okay";
3905 +};
3906 +
3907 +&qspi {
3908 + spi-max-frequency = <48000000>;
3909 + m25p80@0 {
3910 + compatible = "mx66l51235l";
3911 + spi-max-frequency = <48000000>;
3912 + reg = <0>;
3913 + spi-cpol;
3914 + spi-cpha;
3915 + tx-nbits = <1>;
3916 + rx-nbits = <4>;
3917 + };
3918 +};
3919 +
3920 +&mac {
3921 + pinctrl-names = "default", "sleep";
3922 + pinctrl-0 = <&cpsw_default>;
3923 + pinctrl-1 = <&cpsw_sleep>;
3924 + status = "okay";
3925 +};
3926 +
3927 +&davinci_mdio {
3928 + pinctrl-names = "default", "sleep";
3929 + pinctrl-0 = <&davinci_mdio_default>;
3930 + pinctrl-1 = <&davinci_mdio_sleep>;
3931 + status = "okay";
3932 +};
3933 +
3934 +&cpsw_emac0 {
3935 + phy_id = <&davinci_mdio>, <16>;
3936 + phy-mode = "rmii";
3937 +};
3938 +
3939 +&cpsw_emac1 {
3940 + phy_id = <&davinci_mdio>, <1>;
3941 + phy-mode = "rmii";
3942 +};
3943 +
3944 +&phy_sel {
3945 + rmii-clock-ext;
3946 +};
3947 +
3948 +&mmc1 {
3949 + status = "okay";
3950 + vmmc-supply = <&vmmcsd_fixed>;
3951 + bus-width = <4>;
3952 + pinctrl-names = "default";
3953 + pinctrl-0 = <&mmc1_pins>;
3954 + cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
3955 +};
3956 +
3957 +&i2c0 {
3958 + pinctrl-names = "default";
3959 + pinctrl-0 = <&i2c0_pins>;
3960 + status = "okay";
3961 + clock-frequency = <400000>;
3962 +
3963 + pixcir_ts@5c {
3964 + compatible = "pixcir,pixcir_tangoc";
3965 + pinctrl-names = "default";
3966 + pinctrl-0 = <&pixcir_ts_pins>;
3967 + reg = <0x5c>;
3968 + interrupt-parent = <&gpio1>;
3969 + interrupts = <17 0>;
3970 +
3971 + attb-gpio = <&gpio1 17 GPIO_ACTIVE_HIGH>;
3972 +
3973 + x-size = <1024>;
3974 + y-size = <600>;
3975 + };
3976 +};
3977 +
3978 +&i2c2 {
3979 + pinctrl-names = "default";
3980 + pinctrl-0 = <&i2c2_pins>;
3981 + status = "okay";
3982 +
3983 + sii9022: sii9022@3b {
3984 + compatible = "sii,sii9022";
3985 + reg = <0x3b>;
3986 + reset-gpio = <&gpio2 1 GPIO_ACTIVE_LOW>;/* 65'SelLCDorHDMI' Gpio, LOW to select HDMI */
3987 + video-source = <&dpi>;
3988 + data-lines = <24>;
3989 + };
3990 +};
3991 +
3992 +&spi0 {
3993 + pinctrl-names = "default";
3994 + pinctrl-0 = <&spi0_pins>;
3995 + status = "okay";
3996 +};
3997 +
3998 +&spi1 {
3999 + pinctrl-names = "default";
4000 + pinctrl-0 = <&spi1_pins>;
4001 + status = "okay";
4002 };
4003 --- /dev/null
4004 +++ b/arch/arm/boot/dts/am43xx-clocks.dtsi
4005 @@ -0,0 +1,735 @@
4006 +/*
4007 + * Device Tree Source for AM43xx clock data
4008 + *
4009 + * Copyright (C) 2013 Texas Instruments, Inc.
4010 + *
4011 + * This program is free software; you can redistribute it and/or modify
4012 + * it under the terms of the GNU General Public License version 2 as
4013 + * published by the Free Software Foundation.
4014 + */
4015 +
4016 +clk_32768_ck: clk_32768_ck {
4017 + #clock-cells = <0>;
4018 + compatible = "fixed-clock";
4019 + clock-frequency = <32768>;
4020 +};
4021 +
4022 +clk_rc32k_ck: clk_rc32k_ck {
4023 + #clock-cells = <0>;
4024 + compatible = "fixed-clock";
4025 + clock-frequency = <32768>;
4026 +};
4027 +
4028 +virt_19200000_ck: virt_19200000_ck {
4029 + #clock-cells = <0>;
4030 + compatible = "fixed-clock";
4031 + clock-frequency = <19200000>;
4032 +};
4033 +
4034 +virt_24000000_ck: virt_24000000_ck {
4035 + #clock-cells = <0>;
4036 + compatible = "fixed-clock";
4037 + clock-frequency = <24000000>;
4038 +};
4039 +
4040 +virt_25000000_ck: virt_25000000_ck {
4041 + #clock-cells = <0>;
4042 + compatible = "fixed-clock";
4043 + clock-frequency = <25000000>;
4044 +};
4045 +
4046 +virt_26000000_ck: virt_26000000_ck {
4047 + #clock-cells = <0>;
4048 + compatible = "fixed-clock";
4049 + clock-frequency = <26000000>;
4050 +};
4051 +
4052 +crystal_freq_sel_ck: crystal_freq_sel_ck@44e10040 {
4053 + #clock-cells = <0>;
4054 + compatible = "mux-clock";
4055 + clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
4056 + bit-shift = <29>;
4057 + reg = <0x44e10040 0x4>;
4058 + bit-mask = <0x3>;
4059 +};
4060 +
4061 +sysboot_freq_sel_ck: sysboot_freq_sel_ck@44e10040 {
4062 + #clock-cells = <0>;
4063 + compatible = "mux-clock";
4064 + clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
4065 + bit-shift = <22>;
4066 + reg = <0x44e10040 0x4>;
4067 + bit-mask = <0x3>;
4068 +};
4069 +
4070 +sys_clkin_ck: sys_clkin_ck@44e10040 {
4071 + #clock-cells = <0>;
4072 + compatible = "mux-clock";
4073 + clocks = <&sysboot_freq_sel_ck>, <&crystal_freq_sel_ck>;
4074 + bit-shift = <31>;
4075 + reg = <0x44e10040 0x4>;
4076 + bit-mask = <0x1>;
4077 +};
4078 +
4079 +tclkin_ck: tclkin_ck {
4080 + #clock-cells = <0>;
4081 + compatible = "fixed-clock";
4082 + clock-frequency = <26000000>;
4083 +};
4084 +
4085 +dpll_core_ck: dpll_core_ck@44df2d20 {
4086 + #clock-cells = <0>;
4087 + compatible = "ti,omap4-dpll-core-clock";
4088 + clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
4089 + reg = <0x44df2d20 0x4>, <0x44df2d24 0x4>, <0x44df2d2c 0x4>;
4090 + reg-names = "control", "idlest", "mult-div1";
4091 +};
4092 +
4093 +dpll_core_x2_ck: dpll_core_x2_ck {
4094 + #clock-cells = <0>;
4095 + compatible = "ti,omap4-dpll-x2-clock";
4096 + clocks = <&dpll_core_ck>;
4097 +};
4098 +
4099 +dpll_core_m4_ck: dpll_core_m4_ck@44df2d38 {
4100 + #clock-cells = <0>;
4101 + compatible = "ti,divider-clock";
4102 + clocks = <&dpll_core_x2_ck>;
4103 + ti,autoidle-shift = <8>;
4104 + reg = <0x44df2d38 0x4>;
4105 + bit-mask = <0x1f>;
4106 + index-starts-at-one;
4107 + ti,autoidle-low;
4108 +};
4109 +
4110 +dpll_core_m5_ck: dpll_core_m5_ck@44df2d3c {
4111 + #clock-cells = <0>;
4112 + compatible = "ti,divider-clock";
4113 + clocks = <&dpll_core_x2_ck>;
4114 + ti,autoidle-shift = <8>;
4115 + reg = <0x44df2d3c 0x4>;
4116 + bit-mask = <0x1f>;
4117 + index-starts-at-one;
4118 + ti,autoidle-low;
4119 +};
4120 +
4121 +dpll_core_m6_ck: dpll_core_m6_ck@44df2d40 {
4122 + #clock-cells = <0>;
4123 + compatible = "ti,divider-clock";
4124 + clocks = <&dpll_core_x2_ck>;
4125 + ti,autoidle-shift = <8>;
4126 + reg = <0x44df2d40 0x4>;
4127 + bit-mask = <0x1f>;
4128 + index-starts-at-one;
4129 + ti,autoidle-low;
4130 +};
4131 +
4132 +dpll_mpu_ck: dpll_mpu_ck@44df2d60 {
4133 + #clock-cells = <0>;
4134 + compatible = "ti,omap4-dpll-clock";
4135 + clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
4136 + reg = <0x44df2d60 0x4>, <0x44df2d64 0x4>, <0x44df2d6c 0x4>;
4137 + reg-names = "control", "idlest", "mult-div1";
4138 +};
4139 +
4140 +dpll_mpu_m2_ck: dpll_mpu_m2_ck@44df2d70 {
4141 + #clock-cells = <0>;
4142 + compatible = "ti,divider-clock";
4143 + clocks = <&dpll_mpu_ck>;
4144 + ti,autoidle-shift = <8>;
4145 + reg = <0x44df2d70 0x4>;
4146 + bit-mask = <0x1f>;
4147 + index-starts-at-one;
4148 + ti,autoidle-low;
4149 +};
4150 +
4151 +dpll_ddr_ck: dpll_ddr_ck@44df2da0 {
4152 + #clock-cells = <0>;
4153 + compatible = "ti,omap4-dpll-clock";
4154 + clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
4155 + reg = <0x44df2da0 0x4>, <0x44df2da4 0x4>, <0x44df2dac 0x4>;
4156 + reg-names = "control", "idlest", "mult-div1";
4157 +};
4158 +
4159 +dpll_ddr_m2_ck: dpll_ddr_m2_ck@44df2db0 {
4160 + #clock-cells = <0>;
4161 + compatible = "ti,divider-clock";
4162 + clocks = <&dpll_ddr_ck>;
4163 + ti,autoidle-shift = <8>;
4164 + reg = <0x44df2db0 0x4>;
4165 + bit-mask = <0x1f>;
4166 + index-starts-at-one;
4167 + ti,autoidle-low;
4168 +};
4169 +
4170 +dpll_disp_ck: dpll_disp_ck@44df2e20 {
4171 + #clock-cells = <0>;
4172 + compatible = "ti,omap4-dpll-clock";
4173 + clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
4174 + reg = <0x44df2e20 0x4>, <0x44df2e24 0x4>, <0x44df2e2c 0x4>;
4175 + reg-names = "control", "idlest", "mult-div1";
4176 +};
4177 +
4178 +dpll_disp_m2_ck: dpll_disp_m2_ck@44df2e30 {
4179 + #clock-cells = <0>;
4180 + compatible = "ti,divider-clock";
4181 + clocks = <&dpll_disp_ck>;
4182 + ti,autoidle-shift = <8>;
4183 + reg = <0x44df2e30 0x4>;
4184 + bit-mask = <0x1f>;
4185 + index-starts-at-one;
4186 + ti,autoidle-low;
4187 +};
4188 +
4189 +dpll_per_ck: dpll_per_ck@44df2de0 {
4190 + #clock-cells = <0>;
4191 + compatible = "ti,omap4-dpll-j-type-clock";
4192 + clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
4193 + reg = <0x44df2de0 0x4>, <0x44df2de4 0x4>, <0x44df2dec 0x4>;
4194 + reg-names = "control", "idlest", "mult-div1";
4195 +};
4196 +
4197 +dpll_per_m2_ck: dpll_per_m2_ck@44df2df0 {
4198 + #clock-cells = <0>;
4199 + compatible = "ti,divider-clock";
4200 + clocks = <&dpll_per_ck>;
4201 + ti,autoidle-shift = <8>;
4202 + reg = <0x44df2df0 0x4>;
4203 + bit-mask = <0x7f>;
4204 + index-starts-at-one;
4205 + ti,autoidle-low;
4206 +};
4207 +
4208 +dpll_per_m2_div4_wkupdm_ck: dpll_per_m2_div4_wkupdm_ck {
4209 + #clock-cells = <0>;
4210 + compatible = "fixed-factor-clock";
4211 + clocks = <&dpll_per_m2_ck>;
4212 + clock-mult = <1>;
4213 + clock-div = <4>;
4214 +};
4215 +
4216 +dpll_per_m2_div4_ck: dpll_per_m2_div4_ck {
4217 + #clock-cells = <0>;
4218 + compatible = "fixed-factor-clock";
4219 + clocks = <&dpll_per_m2_ck>;
4220 + clock-mult = <1>;
4221 + clock-div = <4>;
4222 +};
4223 +
4224 +adc_tsc_fck: adc_tsc_fck {
4225 + #clock-cells = <0>;
4226 + compatible = "fixed-factor-clock";
4227 + clocks = <&sys_clkin_ck>;
4228 + clock-mult = <1>;
4229 + clock-div = <1>;
4230 +};
4231 +
4232 +clk_24mhz: clk_24mhz {
4233 + #clock-cells = <0>;
4234 + compatible = "fixed-factor-clock";
4235 + clocks = <&dpll_per_m2_ck>;
4236 + clock-mult = <1>;
4237 + clock-div = <8>;
4238 +};
4239 +
4240 +clkdiv32k_ck: clkdiv32k_ck {
4241 + #clock-cells = <0>;
4242 + compatible = "fixed-factor-clock";
4243 + clocks = <&clk_24mhz>;
4244 + clock-mult = <1>;
4245 + clock-div = <732>;
4246 +};
4247 +
4248 +clkdiv32k_ick: clkdiv32k_ick@44df2a38 {
4249 + #clock-cells = <0>;
4250 + compatible = "gate-clock";
4251 + clocks = <&clkdiv32k_ck>;
4252 + bit-shift = <8>;
4253 + reg = <0x44df2a38 0x4>;
4254 +};
4255 +
4256 +dcan0_fck: dcan0_fck {
4257 + #clock-cells = <0>;
4258 + compatible = "fixed-factor-clock";
4259 + clocks = <&sys_clkin_ck>;
4260 + clock-mult = <1>;
4261 + clock-div = <1>;
4262 +};
4263 +
4264 +dcan1_fck: dcan1_fck {
4265 + #clock-cells = <0>;
4266 + compatible = "fixed-factor-clock";
4267 + clocks = <&sys_clkin_ck>;
4268 + clock-mult = <1>;
4269 + clock-div = <1>;
4270 +};
4271 +
4272 +sysclk_div: sysclk_div {
4273 + #clock-cells = <0>;
4274 + compatible = "fixed-factor-clock";
4275 + clocks = <&dpll_core_m4_ck>;
4276 + clock-mult = <1>;
4277 + clock-div = <1>;
4278 +};
4279 +
4280 +pruss_ocp_gclk: pruss_ocp_gclk@44df4248 {
4281 + #clock-cells = <0>;
4282 + compatible = "mux-clock";
4283 + clocks = <&sysclk_div>, <&dpll_disp_m2_ck>;
4284 + reg = <0x44df4248 0x4>;
4285 + bit-mask = <0x1>;
4286 +};
4287 +
4288 +mcasp0_fck: mcasp0_fck {
4289 + #clock-cells = <0>;
4290 + compatible = "fixed-factor-clock";
4291 + clocks = <&sys_clkin_ck>;
4292 + clock-mult = <1>;
4293 + clock-div = <1>;
4294 +};
4295 +
4296 +mcasp1_fck: mcasp1_fck {
4297 + #clock-cells = <0>;
4298 + compatible = "fixed-factor-clock";
4299 + clocks = <&sys_clkin_ck>;
4300 + clock-mult = <1>;
4301 + clock-div = <1>;
4302 +};
4303 +
4304 +smartreflex0_fck: smartreflex0_fck {
4305 + #clock-cells = <0>;
4306 + compatible = "fixed-factor-clock";
4307 + clocks = <&sys_clkin_ck>;
4308 + clock-mult = <1>;
4309 + clock-div = <1>;
4310 +};
4311 +
4312 +smartreflex1_fck: smartreflex1_fck {
4313 + #clock-cells = <0>;
4314 + compatible = "fixed-factor-clock";
4315 + clocks = <&sys_clkin_ck>;
4316 + clock-mult = <1>;
4317 + clock-div = <1>;
4318 +};
4319 +
4320 +sha0_fck: sha0_fck {
4321 + #clock-cells = <0>;
4322 + compatible = "fixed-factor-clock";
4323 + clocks = <&sys_clkin_ck>;
4324 + clock-mult = <1>;
4325 + clock-div = <1>;
4326 +};
4327 +
4328 +rng_fck: rng_fck {
4329 + #clock-cells = <0>;
4330 + compatible = "fixed-factor-clock";
4331 + clocks = <&sys_clkin_ck>;
4332 + clock-mult = <1>;
4333 + clock-div = <1>;
4334 +};
4335 +
4336 +aes0_fck: aes0_fck {
4337 + #clock-cells = <0>;
4338 + compatible = "fixed-factor-clock";
4339 + clocks = <&sys_clkin_ck>;
4340 + clock-mult = <1>;
4341 + clock-div = <1>;
4342 +};
4343 +
4344 +clk_32k_tpm_ck: clk_32k_tpm_ck {
4345 + #clock-cells = <0>;
4346 + compatible = "fixed-clock";
4347 + clock-frequency = <32768>;
4348 +};
4349 +
4350 +timer1_fck: timer1_fck@44df4200 {
4351 + #clock-cells = <0>;
4352 + compatible = "mux-clock";
4353 + clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>, <&clk_32k_tpm_ck>;
4354 + reg = <0x44df4200 0x4>;
4355 + bit-mask = <0x7>;
4356 +};
4357 +
4358 +timer2_fck: timer2_fck@44df4204 {
4359 + #clock-cells = <0>;
4360 + compatible = "mux-clock";
4361 + clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
4362 + reg = <0x44df4204 0x4>;
4363 + bit-mask = <0x3>;
4364 +};
4365 +
4366 +timer3_fck: timer3_fck@44df4208 {
4367 + #clock-cells = <0>;
4368 + compatible = "mux-clock";
4369 + clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
4370 + reg = <0x44df4208 0x4>;
4371 + bit-mask = <0x3>;
4372 +};
4373 +
4374 +timer4_fck: timer4_fck@44df420c {
4375 + #clock-cells = <0>;
4376 + compatible = "mux-clock";
4377 + clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
4378 + reg = <0x44df420c 0x4>;
4379 + bit-mask = <0x3>;
4380 +};
4381 +
4382 +timer5_fck: timer5_fck@44df4210 {
4383 + #clock-cells = <0>;
4384 + compatible = "mux-clock";
4385 + clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
4386 + reg = <0x44df4210 0x4>;
4387 + bit-mask = <0x3>;
4388 +};
4389 +
4390 +timer6_fck: timer6_fck@44df4214 {
4391 + #clock-cells = <0>;
4392 + compatible = "mux-clock";
4393 + clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
4394 + reg = <0x44df4214 0x4>;
4395 + bit-mask = <0x3>;
4396 +};
4397 +
4398 +timer7_fck: timer7_fck@44df4218 {
4399 + #clock-cells = <0>;
4400 + compatible = "mux-clock";
4401 + clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
4402 + reg = <0x44df4218 0x4>;
4403 + bit-mask = <0x3>;
4404 +};
4405 +
4406 +wdt1_fck: wdt1_fck@44df422c {
4407 + #clock-cells = <0>;
4408 + compatible = "mux-clock";
4409 + clocks = <&clk_rc32k_ck>, <&clkdiv32k_ick>;
4410 + reg = <0x44df422c 0x4>;
4411 + bit-mask = <0x1>;
4412 +};
4413 +
4414 +l3_gclk: l3_gclk {
4415 + #clock-cells = <0>;
4416 + compatible = "fixed-factor-clock";
4417 + clocks = <&dpll_core_m4_ck>;
4418 + clock-mult = <1>;
4419 + clock-div = <1>;
4420 +};
4421 +
4422 +dpll_core_m4_div2_ck: dpll_core_m4_div2_ck {
4423 + #clock-cells = <0>;
4424 + compatible = "fixed-factor-clock";
4425 + clocks = <&sysclk_div>;
4426 + clock-mult = <1>;
4427 + clock-div = <2>;
4428 +};
4429 +
4430 +l4hs_gclk: l4hs_gclk {
4431 + #clock-cells = <0>;
4432 + compatible = "fixed-factor-clock";
4433 + clocks = <&dpll_core_m4_ck>;
4434 + clock-mult = <1>;
4435 + clock-div = <1>;
4436 +};
4437 +
4438 +l3s_gclk: l3s_gclk {
4439 + #clock-cells = <0>;
4440 + compatible = "fixed-factor-clock";
4441 + clocks = <&dpll_core_m4_div2_ck>;
4442 + clock-mult = <1>;
4443 + clock-div = <1>;
4444 +};
4445 +
4446 +l4ls_gclk: l4ls_gclk {
4447 + #clock-cells = <0>;
4448 + compatible = "fixed-factor-clock";
4449 + clocks = <&dpll_core_m4_div2_ck>;
4450 + clock-mult = <1>;
4451 + clock-div = <1>;
4452 +};
4453 +
4454 +cpsw_125mhz_gclk: cpsw_125mhz_gclk {
4455 + #clock-cells = <0>;
4456 + compatible = "fixed-factor-clock";
4457 + clocks = <&dpll_core_m5_ck>;
4458 + clock-mult = <1>;
4459 + clock-div = <2>;
4460 +};
4461 +
4462 +cpsw_cpts_rft_clk: cpsw_cpts_rft_clk@44df4238 {
4463 + #clock-cells = <0>;
4464 + compatible = "mux-clock";
4465 + clocks = <&sysclk_div>, <&dpll_core_m5_ck>, <&dpll_disp_m2_ck>;
4466 + reg = <0x44df4238 0x4>;
4467 + bit-mask = <0x3>;
4468 +};
4469 +
4470 +clk_32k_mosc_ck: clk_32k_mosc_ck {
4471 + #clock-cells = <0>;
4472 + compatible = "fixed-clock";
4473 + clock-frequency = <32768>;
4474 +};
4475 +
4476 +gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck@44df4240 {
4477 + #clock-cells = <0>;
4478 + compatible = "mux-clock";
4479 + clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clkdiv32k_ick>, <&clk_32k_mosc_ck>, <&clk_32k_tpm_ck>;
4480 + reg = <0x44df4240 0x4>;
4481 + bit-mask = <0x7>;
4482 +};
4483 +
4484 +gpio0_dbclk: gpio0_dbclk@44df2b68 {
4485 + #clock-cells = <0>;
4486 + compatible = "gate-clock";
4487 + clocks = <&gpio0_dbclk_mux_ck>;
4488 + bit-shift = <8>;
4489 + reg = <0x44df2b68 0x4>;
4490 +};
4491 +
4492 +gpio1_dbclk: gpio1_dbclk@44df8c78 {
4493 + #clock-cells = <0>;
4494 + compatible = "gate-clock";
4495 + clocks = <&clkdiv32k_ick>;
4496 + bit-shift = <8>;
4497 + reg = <0x44df8c78 0x4>;
4498 +};
4499 +
4500 +gpio2_dbclk: gpio2_dbclk@44df8c80 {
4501 + #clock-cells = <0>;
4502 + compatible = "gate-clock";
4503 + clocks = <&clkdiv32k_ick>;
4504 + bit-shift = <8>;
4505 + reg = <0x44df8c80 0x4>;
4506 +};
4507 +
4508 +gpio3_dbclk: gpio3_dbclk@44df8c88 {
4509 + #clock-cells = <0>;
4510 + compatible = "gate-clock";
4511 + clocks = <&clkdiv32k_ick>;
4512 + bit-shift = <8>;
4513 + reg = <0x44df8c88 0x4>;
4514 +};
4515 +
4516 +gpio4_dbclk: gpio4_dbclk@44df8c90 {
4517 + #clock-cells = <0>;
4518 + compatible = "gate-clock";
4519 + clocks = <&clkdiv32k_ick>;
4520 + bit-shift = <8>;
4521 + reg = <0x44df8c90 0x4>;
4522 +};
4523 +
4524 +gpio5_dbclk: gpio5_dbclk@44df8c98 {
4525 + #clock-cells = <0>;
4526 + compatible = "gate-clock";
4527 + clocks = <&clkdiv32k_ick>;
4528 + bit-shift = <8>;
4529 + reg = <0x44df8c98 0x4>;
4530 +};
4531 +
4532 +mmc_clk: mmc_clk {
4533 + #clock-cells = <0>;
4534 + compatible = "fixed-factor-clock";
4535 + clocks = <&dpll_per_m2_ck>;
4536 + clock-mult = <1>;
4537 + clock-div = <2>;
4538 +};
4539 +
4540 +gfx_fclk_clksel_ck: gfx_fclk_clksel_ck@44df423c {
4541 + #clock-cells = <0>;
4542 + compatible = "mux-clock";
4543 + clocks = <&sysclk_div>, <&dpll_per_m2_ck>;
4544 + bit-shift = <1>;
4545 + reg = <0x44df423c 0x4>;
4546 + bit-mask = <0x1>;
4547 +};
4548 +
4549 +gfx_fck_div_ck: gfx_fck_div_ck@44df423c {
4550 + #clock-cells = <0>;
4551 + compatible = "divider-clock";
4552 + clocks = <&gfx_fclk_clksel_ck>;
4553 + reg = <0x44df423c 0x4>;
4554 + bit-mask = <0x1>;
4555 +};
4556 +
4557 +disp_clk: disp_clk@44df4244 {
4558 + #clock-cells = <0>;
4559 + compatible = "mux-clock";
4560 + clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>;
4561 + reg = <0x44df4244 0x4>;
4562 + bit-mask = <0x3>;
4563 +};
4564 +
4565 +dpll_extdev_ck: dpll_extdev_ck@44df2e60 {
4566 + #clock-cells = <0>;
4567 + compatible = "ti,omap4-dpll-clock";
4568 + clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
4569 + reg = <0x44df2e60 0x4>, <0x44df2e64 0x4>, <0x44df2e6c 0x4>;
4570 + reg-names = "control", "idlest", "mult-div1";
4571 +};
4572 +
4573 +dpll_extdev_m2_ck: dpll_extdev_m2_ck@44df2e70 {
4574 + #clock-cells = <0>;
4575 + compatible = "ti,divider-clock";
4576 + clocks = <&dpll_extdev_ck>;
4577 + ti,autoidle-shift = <8>;
4578 + reg = <0x44df2e70 0x4>;
4579 + bit-mask = <0x7f>;
4580 + index-starts-at-one;
4581 + ti,autoidle-low;
4582 +};
4583 +
4584 +mux_synctimer32k_ck: mux_synctimer32k_ck@44df4230 {
4585 + #clock-cells = <0>;
4586 + compatible = "mux-clock";
4587 + clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>, <&clkdiv32k_ick>;
4588 + reg = <0x44df4230 0x4>;
4589 + bit-mask = <0x3>;
4590 +};
4591 +
4592 +synctimer_32kclk: synctimer_32kclk@44df2a30 {
4593 + #clock-cells = <0>;
4594 + compatible = "gate-clock";
4595 + clocks = <&mux_synctimer32k_ck>;
4596 + bit-shift = <8>;
4597 + reg = <0x44df2a30 0x4>;
4598 +};
4599 +
4600 +timer8_fck: timer8_fck@44df421c {
4601 + #clock-cells = <0>;
4602 + compatible = "mux-clock";
4603 + clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
4604 + reg = <0x44df421c 0x4>;
4605 + bit-mask = <0x3>;
4606 +};
4607 +
4608 +timer9_fck: timer9_fck@44df4220 {
4609 + #clock-cells = <0>;
4610 + compatible = "mux-clock";
4611 + clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
4612 + reg = <0x44df4220 0x4>;
4613 + bit-mask = <0x3>;
4614 +};
4615 +
4616 +timer10_fck: timer10_fck@44df4224 {
4617 + #clock-cells = <0>;
4618 + compatible = "mux-clock";
4619 + clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
4620 + reg = <0x44df4224 0x4>;
4621 + bit-mask = <0x3>;
4622 +};
4623 +
4624 +timer11_fck: timer11_fck@44df4228 {
4625 + #clock-cells = <0>;
4626 + compatible = "mux-clock";
4627 + clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
4628 + reg = <0x44df4228 0x4>;
4629 + bit-mask = <0x3>;
4630 +};
4631 +
4632 +cpsw_50m_clkdiv: cpsw_50m_clkdiv {
4633 + #clock-cells = <0>;
4634 + compatible = "fixed-factor-clock";
4635 + clocks = <&dpll_core_m5_ck>;
4636 + clock-mult = <1>;
4637 + clock-div = <1>;
4638 +};
4639 +
4640 +cpsw_5m_clkdiv: cpsw_5m_clkdiv {
4641 + #clock-cells = <0>;
4642 + compatible = "fixed-factor-clock";
4643 + clocks = <&cpsw_50m_clkdiv>;
4644 + clock-mult = <1>;
4645 + clock-div = <10>;
4646 +};
4647 +
4648 +dpll_ddr_x2_ck: dpll_ddr_x2_ck {
4649 + #clock-cells = <0>;
4650 + compatible = "ti,omap4-dpll-x2-clock";
4651 + clocks = <&dpll_ddr_ck>;
4652 +};
4653 +
4654 +dpll_ddr_m4_ck: dpll_ddr_m4_ck@44df2db8 {
4655 + #clock-cells = <0>;
4656 + compatible = "ti,divider-clock";
4657 + clocks = <&dpll_ddr_x2_ck>;
4658 + ti,autoidle-shift = <8>;
4659 + reg = <0x44df2db8 0x4>;
4660 + bit-mask = <0x1f>;
4661 + index-starts-at-one;
4662 + ti,autoidle-low;
4663 +};
4664 +
4665 +dpll_per_clkdcoldo: dpll_per_clkdcoldo {
4666 + #clock-cells = <0>;
4667 + compatible = "fixed-factor-clock";
4668 + clocks = <&dpll_per_ck>;
4669 + clock-mult = <1>;
4670 + clock-div = <1>;
4671 +};
4672 +
4673 +dll_aging_clk_div: dll_aging_clk_div@44df4250 {
4674 + #clock-cells = <0>;
4675 + compatible = "divider-clock";
4676 + clocks = <&sys_clkin_ck>;
4677 + reg = <0x44df4250 0x4>;
4678 + table = < 8 0 >, < 16 1 >, < 32 2 >;
4679 + bit-mask = <0x3>;
4680 +};
4681 +
4682 +div_core_25m_ck: div_core_25m_ck {
4683 + #clock-cells = <0>;
4684 + compatible = "fixed-factor-clock";
4685 + clocks = <&sysclk_div>;
4686 + clock-mult = <1>;
4687 + clock-div = <8>;
4688 +};
4689 +
4690 +func_12m_clk: func_12m_clk {
4691 + #clock-cells = <0>;
4692 + compatible = "fixed-factor-clock";
4693 + clocks = <&dpll_per_m2_ck>;
4694 + clock-mult = <1>;
4695 + clock-div = <16>;
4696 +};
4697 +
4698 +vtp_clk_div: vtp_clk_div {
4699 + #clock-cells = <0>;
4700 + compatible = "fixed-factor-clock";
4701 + clocks = <&sys_clkin_ck>;
4702 + clock-mult = <1>;
4703 + clock-div = <2>;
4704 +};
4705 +
4706 +usbphy_32khz_clkmux: usbphy_32khz_clkmux@44df4260 {
4707 + #clock-cells = <0>;
4708 + compatible = "mux-clock";
4709 + clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>;
4710 + reg = <0x44df4260 0x4>;
4711 + bit-mask = <0x1>;
4712 +};
4713 +
4714 +usb_otg_ss0_refclk960m: usb_otg_ss0_refclk960m@44df8a60 {
4715 + #clock-cells = <0>;
4716 + compatible = "gate-clock";
4717 + clocks = <&dpll_per_clkdcoldo>;
4718 + bit-shift = <8>;
4719 + reg = <0x44df8a60 0x4>;
4720 +};
4721 +
4722 +usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m@44df8a68 {
4723 + #clock-cells = <0>;
4724 + compatible = "gate-clock";
4725 + clocks = <&dpll_per_clkdcoldo>;
4726 + bit-shift = <8>;
4727 + reg = <0x44df8a68 0x4>;
4728 +};
4729 +
4730 +usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k {
4731 + #clock-cells = <0>;
4732 + compatible = "fixed-clock";
4733 + clocks = <&clk_32768_ck>;
4734 +};
4735 +
4736 +usb_phy2_always_on_clk32k: usb_phy2_always_on_clk32k {
4737 + #clock-cells = <0>;
4738 + compatible = "fixed-clock";
4739 + clocks = <&clk_32768_ck>;
4740 +};
4741 --- /dev/null
4742 +++ b/arch/arm/boot/dts/dra7.dtsi
4743 @@ -0,0 +1,1278 @@
4744 +/*
4745 + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
4746 + *
4747 + * This program is free software; you can redistribute it and/or modify
4748 + * it under the terms of the GNU General Public License version 2 as
4749 + * published by the Free Software Foundation.
4750 + * Based on "omap4.dtsi"
4751 + */
4752 +
4753 +#include <dt-bindings/interrupt-controller/arm-gic.h>
4754 +
4755 +#include "skeleton.dtsi"
4756 +
4757 +/ {
4758 + compatible = "ti,dra7xx";
4759 + interrupt-parent = <&gic>;
4760 +
4761 + aliases {
4762 + i2c0 = &i2c1;
4763 + i2c1 = &i2c2;
4764 + i2c2 = &i2c3;
4765 + i2c3 = &i2c4;
4766 + i2c4 = &i2c5;
4767 + serial0 = &uart1;
4768 + serial1 = &uart2;
4769 + serial2 = &uart3;
4770 + serial3 = &uart4;
4771 + serial4 = &uart5;
4772 + serial5 = &uart6;
4773 + ethernet0 = &cpsw_emac0;
4774 + ethernet1 = &cpsw_emac1;
4775 + };
4776 +
4777 + cpus {
4778 + #address-cells = <1>;
4779 + #size-cells = <0>;
4780 +
4781 + cpu0: cpu@0 {
4782 + device_type = "cpu";
4783 + compatible = "arm,cortex-a15";
4784 + reg = <0>;
4785 +
4786 + operating-points = <
4787 + /* kHz uV */
4788 + 1000000 1090000
4789 + 1176000 1210000
4790 + >;
4791 +
4792 + clocks = <&dpll_mpu_ck>;
4793 + clock-names = "cpu";
4794 +
4795 + clock-latency = <300000>; /* From omap-cpufreq driver */
4796 + };
4797 + cpu@1 {
4798 + device_type = "cpu";
4799 + compatible = "arm,cortex-a15";
4800 + reg = <1>;
4801 + };
4802 + };
4803 +
4804 + timer {
4805 + compatible = "arm,armv7-timer";
4806 + /* PPI secure/nonsecure IRQ */
4807 + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
4808 + <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
4809 + <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
4810 + <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
4811 + clock-frequency = <6144000>;
4812 + };
4813 +
4814 + gic: interrupt-controller@48211000 {
4815 + compatible = "arm,cortex-a15-gic";
4816 + interrupt-controller;
4817 + #interrupt-cells = <3>;
4818 + reg = <0x48211000 0x1000>,
4819 + <0x48212000 0x1000>,
4820 + <0x48214000 0x2000>,
4821 + <0x48216000 0x2000>;
4822 + };
4823 +
4824 + /*
4825 + * The soc node represents the soc top level view. It is uses for IPs
4826 + * that are not memory mapped in the MPU view or for the MPU itself.
4827 + */
4828 + soc {
4829 + compatible = "ti,omap-infra";
4830 + mpu {
4831 + compatible = "ti,omap5-mpu";
4832 + ti,hwmods = "mpu";
4833 + };
4834 + };
4835 +
4836 + /*
4837 + * XXX: Use a flat representation of the SOC interconnect.
4838 + * The real OMAP interconnect network is quite complex.
4839 + * Since that will not bring real advantage to represent that in DT for
4840 + * the moment, just use a fake OCP bus entry to represent the whole bus
4841 + * hierarchy.
4842 + */
4843 + ocp {
4844 + compatible = "ti,omap4-l3-noc", "simple-bus";
4845 + #address-cells = <1>;
4846 + #size-cells = <1>;
4847 + ranges;
4848 + ti,hwmods = "l3_main_1", "l3_main_2";
4849 +
4850 + crossbar_mpu: mpuirq@4a002a48 {
4851 + compatible = "crossbar";
4852 + crossbar-name = "mpu-irq";
4853 + reg = <0x4a002a48 0x0130>;
4854 + reg-width = <16>;
4855 + crossbar-lines = "mpu-irq", "rtc-ss-alarm", <0x9f 0xd9 0x12e>,
4856 + "mpu-irq", "mcasp3-arevt", <0x9e 0x96 0x12c>,
4857 + "mpu-irq", "mcasp3-axevt", <0x9d 0x97 0x12a>,
4858 + "mpu-irq", "mailbox5", <0x88 0xfb 0x100>,
4859 + "mpu-irq", "mailbox6", <0x8d 0xff 0x10a>,
4860 + "mpu-irq", "qspi", <0x7c 0x157 0x0ec>,
4861 + "mpu-irq", "vpe", <0x9c 0x162 0x128>,
4862 + "mpu-irq", "cpsw-rx-thresh", <0x32 0x14e 0x58>,
4863 + "mpu-irq", "cpsw-rx", <0x33 0x14f 0x5a>,
4864 + "mpu-irq", "cpsw-tx", <0x34 0x150 0x5c>,
4865 + "mpu-irq", "cpsw-misc", <0x35 0x151 0x5e>;
4866 + };
4867 +
4868 + crossbar_dma: dmareq@4a002b78 {
4869 + compatible = "crossbar";
4870 + crossbar-name = "dma-req";
4871 + reg = <0x4a002b78 0x0100>;
4872 + reg-width = <16>;
4873 + crossbar-lines = "dma-req", "mcasp3-rx", <0x7e 0x84 0xfc>,
4874 + "dma-req", "mcasp3-tx", <0x7d 0x85 0xfa>;
4875 + };
4876 +
4877 + prcm: prcm@4ae06000 {
4878 + compatible = "ti,dra7-prcm";
4879 + reg = <0x4ae06000 0x1f00>;
4880 + #reset-cells = <1>;
4881 + };
4882 +
4883 + counter32k: counter@4ae04000 {
4884 + compatible = "ti,omap-counter32k";
4885 + reg = <0x4ae04000 0x40>;
4886 + ti,hwmods = "counter_32k";
4887 + clocks = <&wkupaon_iclk_mux>;
4888 + clock-names = "fck";
4889 + };
4890 +
4891 + avs_mpu: regulator-avs@0x4A003B18 {
4892 + compatible = "ti,avsclass0";
4893 + reg = <0x4A003B18 20>;
4894 + efuse-settings = <1090000 8
4895 + 1210000 12
4896 + 1280000 16>;
4897 + };
4898 +
4899 + avs_core: regulator-avs@0x4A0025EC {
4900 + compatible = "ti,avsclass0";
4901 + reg = <0x4A0025EC 20>;
4902 + efuse-settings = <1030000 8>;
4903 + };
4904 +
4905 + avs_gpu: regulator-avs@0x4A003B00 {
4906 + compatible = "ti,avsclass0";
4907 + reg = <0x4A003B00 20>;
4908 + efuse-settings = <1090000 8
4909 + 1210000 12
4910 + 1280000 16>;
4911 + };
4912 +
4913 + avs_dspeve: regulator-avs@0x4A0025D8 {
4914 + compatible = "ti,avsclass0";
4915 + reg = <0x4A0025D8 20>;
4916 + efuse-settings = <1055000 8
4917 + 1150000 12
4918 + 1250000 16>;
4919 + };
4920 +
4921 + avs_iva: regulator-avs@0x4A0025C4 {
4922 + compatible = "ti,avsclass0";
4923 + reg = <0x4A0025C4 20>;
4924 + efuse-settings = <1055000 8
4925 + 1150000 12
4926 + 1250000 16>;
4927 + };
4928 +
4929 + dra7_pmx_core: pinmux@4a003400 {
4930 + compatible = "pinctrl-single";
4931 + reg = <0x4a003400 0x0464>;
4932 + #address-cells = <1>;
4933 + #size-cells = <0>;
4934 + pinctrl-single,register-width = <32>;
4935 + pinctrl-single,function-mask = <0x3fffffff>;
4936 + };
4937 +
4938 + sdma: dma-controller@4a056000 {
4939 + compatible = "ti,omap4430-sdma";
4940 + reg = <0x4a056000 0x1000>;
4941 + interrupts = <0 12 0x4>,
4942 + <0 13 0x4>,
4943 + <0 14 0x4>,
4944 + <0 15 0x4>;
4945 + #dma-cells = <1>;
4946 + #dma-channels = <32>;
4947 + #dma-requests = <127>;
4948 + clocks = <&l3_iclk_div>;
4949 + clock-names = "fck";
4950 + };
4951 +
4952 + gpio1: gpio@4ae10000 {
4953 + compatible = "ti,omap4-gpio";
4954 + reg = <0x4ae10000 0x200>;
4955 + interrupts = <0 29 0x4>;
4956 + ti,hwmods = "gpio1";
4957 + clocks = <&wkupaon_iclk_mux>, <&gpio1_dbclk>;
4958 + clock-names = "fck", "dbclk";
4959 + gpio-controller;
4960 + #gpio-cells = <2>;
4961 + interrupt-controller;
4962 + #interrupt-cells = <1>;
4963 + };
4964 +
4965 + gpio2: gpio@48055000 {
4966 + compatible = "ti,omap4-gpio";
4967 + reg = <0x48055000 0x200>;
4968 + interrupts = <0 30 0x4>;
4969 + ti,hwmods = "gpio2";
4970 + clocks = <&l3_iclk_div>, <&gpio2_dbclk>;
4971 + clock-names = "fck", "dbclk";
4972 + gpio-controller;
4973 + #gpio-cells = <2>;
4974 + interrupt-controller;
4975 + #interrupt-cells = <1>;
4976 + };
4977 +
4978 + gpio3: gpio@48057000 {
4979 + compatible = "ti,omap4-gpio";
4980 + reg = <0x48057000 0x200>;
4981 + interrupts = <0 31 0x4>;
4982 + ti,hwmods = "gpio3";
4983 + clocks = <&l3_iclk_div>, <&gpio3_dbclk>;
4984 + clock-names = "fck", "dbclk";
4985 + gpio-controller;
4986 + #gpio-cells = <2>;
4987 + interrupt-controller;
4988 + #interrupt-cells = <1>;
4989 + };
4990 +
4991 + gpio4: gpio@48059000 {
4992 + compatible = "ti,omap4-gpio";
4993 + reg = <0x48059000 0x200>;
4994 + interrupts = <0 32 0x4>;
4995 + ti,hwmods = "gpio4";
4996 + clocks = <&l3_iclk_div>, <&gpio4_dbclk>;
4997 + clock-names = "fck", "dbclk";
4998 + gpio-controller;
4999 + #gpio-cells = <2>;
5000 + interrupt-controller;
5001 + #interrupt-cells = <1>;
5002 + };
5003 +
5004 + gpio5: gpio@4805b000 {
5005 + compatible = "ti,omap4-gpio";
5006 + reg = <0x4805b000 0x200>;
5007 + interrupts = <0 33 0x4>;
5008 + ti,hwmods = "gpio5";
5009 + clocks = <&l3_iclk_div>, <&gpio5_dbclk>;
5010 + clock-names = "fck", "dbclk";
5011 + gpio-controller;
5012 + #gpio-cells = <2>;
5013 + interrupt-controller;
5014 + #interrupt-cells = <1>;
5015 + };
5016 +
5017 + gpio6: gpio@4805d000 {
5018 + compatible = "ti,omap4-gpio";
5019 + reg = <0x4805d000 0x200>;
5020 + interrupts = <0 34 0x4>;
5021 + ti,hwmods = "gpio6";
5022 + clocks = <&l3_iclk_div>, <&gpio6_dbclk>;
5023 + clock-names = "fck", "dbclk";
5024 + gpio-controller;
5025 + #gpio-cells = <2>;
5026 + interrupt-controller;
5027 + #interrupt-cells = <1>;
5028 + };
5029 +
5030 + gpio7: gpio@48051000 {
5031 + compatible = "ti,omap4-gpio";
5032 + reg = <0x48051000 0x200>;
5033 + interrupts = <0 35 0x4>;
5034 + ti,hwmods = "gpio7";
5035 + clocks = <&l3_iclk_div>, <&gpio7_dbclk>;
5036 + clock-names = "fck", "dbclk";
5037 + gpio-controller;
5038 + #gpio-cells = <2>;
5039 + interrupt-controller;
5040 + #interrupt-cells = <1>;
5041 + };
5042 +
5043 + gpio8: gpio@48053000 {
5044 + compatible = "ti,omap4-gpio";
5045 + reg = <0x48053000 0x200>;
5046 + interrupts = <0 121 0x4>;
5047 + ti,hwmods = "gpio8";
5048 + clocks = <&l3_iclk_div>, <&gpio8_dbclk>;
5049 + clock-names = "fck", "dbclk";
5050 + gpio-controller;
5051 + #gpio-cells = <2>;
5052 + interrupt-controller;
5053 + #interrupt-cells = <1>;
5054 + };
5055 +
5056 + uart1: serial@4806a000 {
5057 + compatible = "ti,omap4-uart";
5058 + reg = <0x4806a000 0x100>;
5059 + interrupts = <0 72 0x4>;
5060 + ti,hwmods = "uart1";
5061 + clocks = <&uart1_gfclk_mux>;
5062 + clock-names = "fck";
5063 + clock-frequency = <48000000>;
5064 + status = "disabled";
5065 + };
5066 +
5067 + uart2: serial@4806c000 {
5068 + compatible = "ti,omap4-uart";
5069 + reg = <0x4806c000 0x100>;
5070 + interrupts = <0 73 0x4>;
5071 + ti,hwmods = "uart2";
5072 + clocks = <&uart2_gfclk_mux>;
5073 + clock-names = "fck";
5074 + clock-frequency = <48000000>;
5075 + status = "disabled";
5076 + };
5077 +
5078 + uart3: serial@48020000 {
5079 + compatible = "ti,omap4-uart";
5080 + reg = <0x48020000 0x100>;
5081 + interrupts = <0 74 0x4>;
5082 + ti,hwmods = "uart3";
5083 + clocks = <&uart3_gfclk_mux>;
5084 + clock-names = "fck";
5085 + clock-frequency = <48000000>;
5086 + status = "disabled";
5087 + };
5088 +
5089 + uart4: serial@4806e000 {
5090 + compatible = "ti,omap4-uart";
5091 + reg = <0x4806e000 0x100>;
5092 + interrupts = <0 70 0x4>;
5093 + ti,hwmods = "uart4";
5094 + clocks = <&uart4_gfclk_mux>;
5095 + clock-names = "fck";
5096 + clock-frequency = <48000000>;
5097 + status = "disabled";
5098 + };
5099 +
5100 + uart5: serial@48066000 {
5101 + compatible = "ti,omap4-uart";
5102 + reg = <0x48066000 0x100>;
5103 + interrupts = <0 105 0x4>;
5104 + ti,hwmods = "uart5";
5105 + clocks = <&uart5_gfclk_mux>;
5106 + clock-names = "fck";
5107 + clock-frequency = <48000000>;
5108 + status = "disabled";
5109 + };
5110 +
5111 + uart6: serial@48068000 {
5112 + compatible = "ti,omap4-uart";
5113 + reg = <0x48068000 0x100>;
5114 + interrupts = <0 106 0x4>;
5115 + ti,hwmods = "uart6";
5116 + clocks = <&uart6_gfclk_mux>;
5117 + clock-names = "fck";
5118 + clock-frequency = <48000000>;
5119 + status = "disabled";
5120 + };
5121 +
5122 + uart7: serial@48420000 {
5123 + compatible = "ti,omap4-uart";
5124 + reg = <0x48420000 0x100>;
5125 + ti,hwmods = "uart7";
5126 + clock-frequency = <48000000>;
5127 + status = "disabled";
5128 + };
5129 +
5130 + uart8: serial@48422000 {
5131 + compatible = "ti,omap4-uart";
5132 + reg = <0x48422000 0x100>;
5133 + ti,hwmods = "uart8";
5134 + clock-frequency = <48000000>;
5135 + status = "disabled";
5136 + };
5137 +
5138 + uart9: serial@48424000 {
5139 + compatible = "ti,omap4-uart";
5140 + reg = <0x48424000 0x100>;
5141 + ti,hwmods = "uart9";
5142 + clock-frequency = <48000000>;
5143 + status = "disabled";
5144 + };
5145 +
5146 + uart10: serial@4ae2b000 {
5147 + compatible = "ti,omap4-uart";
5148 + reg = <0x4ae2b000 0x100>;
5149 + ti,hwmods = "uart10";
5150 + clock-frequency = <48000000>;
5151 + status = "disabled";
5152 + };
5153 +
5154 + mailbox1: mailbox@4a0f4000 {
5155 + compatible = "ti,omap4-mailbox";
5156 + reg = <0x4a0f4000 0x200>;
5157 + interrupts = <0 26 0x4>;
5158 + ti,hwmods = "mailbox1";
5159 + ti,mbox-num-users = <3>;
5160 + ti,mbox-num-fifos = <8>;
5161 + #ti,mbox-data-cells = <4>;
5162 + ti,mbox-names = "mbox1-1", "mbox1-2";
5163 + ti,mbox-data = <0 1 0 0>, <3 2 0 0>;
5164 + };
5165 +
5166 + mailbox2: mailbox@4883a000 {
5167 + compatible = "ti,omap4-mailbox";
5168 + reg = <0x4883a000 0x200>;
5169 + ti,hwmods = "mailbox2";
5170 + ti,mbox-num-users = <4>;
5171 + ti,mbox-num-fifos = <12>;
5172 + #ti,mbox-data-cells = <4>;
5173 + status = "disabled";
5174 + };
5175 +
5176 + mailbox3: mailbox@4883c000 {
5177 + compatible = "ti,omap4-mailbox";
5178 + reg = <0x4883c000 0x200>;
5179 + ti,hwmods = "mailbox3";
5180 + ti,mbox-num-users = <4>;
5181 + ti,mbox-num-fifos = <12>;
5182 + #ti,mbox-data-cells = <4>;
5183 + status = "disabled";
5184 + };
5185 +
5186 + mailbox4: mailbox@4883e000 {
5187 + compatible = "ti,omap4-mailbox";
5188 + reg = <0x4883e000 0x200>;
5189 + ti,hwmods = "mailbox4";
5190 + ti,mbox-num-users = <4>;
5191 + ti,mbox-num-fifos = <12>;
5192 + #ti,mbox-data-cells = <4>;
5193 + status = "disabled";
5194 + };
5195 +
5196 + mailbox5: mailbox@48840000 {
5197 + compatible = "ti,omap4-mailbox";
5198 + reg = <0x48840000 0x200>;
5199 + interrupts = <0 136 0x4>;
5200 + ti,hwmods = "mailbox5";
5201 + ti,mbox-num-users = <4>;
5202 + ti,mbox-num-fifos = <12>;
5203 + #ti,mbox-data-cells = <4>;
5204 + ti,mbox-names = "mbox-ipu1", "mbox-dsp1";
5205 + ti,mbox-data = <6 4 0 2>, <5 1 0 2>;
5206 + };
5207 +
5208 + mailbox6: mailbox@48842000 {
5209 + compatible = "ti,omap4-mailbox";
5210 + reg = <0x48842000 0x200>;
5211 + interrupts = <0 141 0x4>;
5212 + ti,hwmods = "mailbox6";
5213 + ti,mbox-num-users = <4>;
5214 + ti,mbox-num-fifos = <12>;
5215 + #ti,mbox-data-cells = <4>;
5216 + ti,mbox-names = "mbox-ipu2", "mbox-dsp2";
5217 + ti,mbox-data = <6 4 0 2>, <5 1 0 2>;
5218 + };
5219 +
5220 + mailbox7: mailbox@48844000 {
5221 + compatible = "ti,omap4-mailbox";
5222 + reg = <0x48844000 0x200>;
5223 + ti,hwmods = "mailbox7";
5224 + ti,mbox-num-users = <4>;
5225 + ti,mbox-num-fifos = <12>;
5226 + #ti,mbox-data-cells = <4>;
5227 + status = "disabled";
5228 + };
5229 +
5230 + mailbox8: mailbox@48846000 {
5231 + compatible = "ti,omap4-mailbox";
5232 + reg = <0x48846000 0x200>;
5233 + ti,hwmods = "mailbox8";
5234 + ti,mbox-num-users = <4>;
5235 + ti,mbox-num-fifos = <12>;
5236 + #ti,mbox-data-cells = <4>;
5237 + status = "disabled";
5238 + };
5239 +
5240 + mailbox9: mailbox@4885e000 {
5241 + compatible = "ti,omap4-mailbox";
5242 + reg = <0x4885e000 0x200>;
5243 + ti,hwmods = "mailbox9";
5244 + ti,mbox-num-users = <4>;
5245 + ti,mbox-num-fifos = <12>;
5246 + #ti,mbox-data-cells = <4>;
5247 + status = "disabled";
5248 + };
5249 +
5250 + mailbox10: mailbox@48860000 {
5251 + compatible = "ti,omap4-mailbox";
5252 + reg = <0x48860000 0x200>;
5253 + ti,hwmods = "mailbox10";
5254 + ti,mbox-num-users = <4>;
5255 + ti,mbox-num-fifos = <12>;
5256 + #ti,mbox-data-cells = <4>;
5257 + status = "disabled";
5258 + };
5259 +
5260 + mailbox11: mailbox@48862000 {
5261 + compatible = "ti,omap4-mailbox";
5262 + reg = <0x48862000 0x200>;
5263 + ti,hwmods = "mailbox11";
5264 + ti,mbox-num-users = <4>;
5265 + ti,mbox-num-fifos = <12>;
5266 + #ti,mbox-data-cells = <4>;
5267 + status = "disabled";
5268 + };
5269 +
5270 + mailbox12: mailbox@48864000 {
5271 + compatible = "ti,omap4-mailbox";
5272 + reg = <0x48864000 0x200>;
5273 + ti,hwmods = "mailbox12";
5274 + ti,mbox-num-users = <4>;
5275 + ti,mbox-num-fifos = <12>;
5276 + #ti,mbox-data-cells = <4>;
5277 + status = "disabled";
5278 + };
5279 +
5280 + mailbox13: mailbox@48802000 {
5281 + compatible = "ti,omap4-mailbox";
5282 + reg = <0x48802000 0x200>;
5283 + ti,hwmods = "mailbox13";
5284 + ti,mbox-num-users = <4>;
5285 + ti,mbox-num-fifos = <12>;
5286 + #ti,mbox-data-cells = <4>;
5287 + status = "disabled";
5288 + };
5289 +
5290 + timer1: timer@4ae18000 {
5291 + compatible = "ti,omap5430-timer";
5292 + reg = <0x4ae18000 0x80>;
5293 + interrupts = <0 37 0x4>;
5294 + ti,hwmods = "timer1";
5295 + clocks = <&timer1_gfclk_mux>;
5296 + clock-names = "fck";
5297 + ti,timer-alwon;
5298 + };
5299 +
5300 + timer2: timer@48032000 {
5301 + compatible = "ti,omap5430-timer";
5302 + reg = <0x48032000 0x80>;
5303 + interrupts = <0 38 0x4>;
5304 + ti,hwmods = "timer2";
5305 + clocks = <&timer2_gfclk_mux>;
5306 + clock-names = "fck";
5307 + };
5308 +
5309 + timer3: timer@48034000 {
5310 + compatible = "ti,omap5430-timer";
5311 + reg = <0x48034000 0x80>;
5312 + interrupts = <0 39 0x4>;
5313 + ti,hwmods = "timer3";
5314 + clocks = <&timer3_gfclk_mux>;
5315 + clock-names = "fck";
5316 + };
5317 +
5318 + timer4: timer@48036000 {
5319 + compatible = "ti,omap5430-timer";
5320 + reg = <0x48036000 0x80>;
5321 + interrupts = <0 40 0x4>;
5322 + ti,hwmods = "timer4";
5323 + clocks = <&timer4_gfclk_mux>;
5324 + clock-names = "fck";
5325 + };
5326 +
5327 + timer5: timer@48820000 {
5328 + compatible = "ti,omap5430-timer";
5329 + reg = <0x48820000 0x80>;
5330 + interrupts = <0 41 0x4>;
5331 + ti,hwmods = "timer5";
5332 + clocks = <&timer5_gfclk_mux>;
5333 + clock-names = "fck";
5334 + ti,timer-dsp;
5335 + };
5336 +
5337 + timer6: timer@48822000 {
5338 + compatible = "ti,omap5430-timer";
5339 + reg = <0x48822000 0x80>;
5340 + interrupts = <0 42 0x4>;
5341 + ti,hwmods = "timer6";
5342 + clocks = <&timer6_gfclk_mux>;
5343 + clock-names = "fck";
5344 + ti,timer-dsp;
5345 + ti,timer-pwm;
5346 + };
5347 +
5348 + timer7: timer@48824000 {
5349 + compatible = "ti,omap5430-timer";
5350 + reg = <0x48824000 0x80>;
5351 + interrupts = <0 43 0x4>;
5352 + ti,hwmods = "timer7";
5353 + clocks = <&timer7_gfclk_mux>;
5354 + clock-names = "fck";
5355 + ti,timer-dsp;
5356 + };
5357 +
5358 + timer8: timer@48826000 {
5359 + compatible = "ti,omap5430-timer";
5360 + reg = <0x48826000 0x80>;
5361 + interrupts = <0 44 0x4>;
5362 + ti,hwmods = "timer8";
5363 + clocks = <&timer8_gfclk_mux>;
5364 + clock-names = "fck";
5365 + ti,timer-dsp;
5366 + ti,timer-pwm;
5367 + };
5368 +
5369 + timer9: timer@4803e000 {
5370 + compatible = "ti,omap5430-timer";
5371 + reg = <0x4803e000 0x80>;
5372 + interrupts = <0 45 0x4>;
5373 + ti,hwmods = "timer9";
5374 + clocks = <&timer9_gfclk_mux>;
5375 + clock-names = "fck";
5376 + };
5377 +
5378 + timer10: timer@48086000 {
5379 + compatible = "ti,omap5430-timer";
5380 + reg = <0x48086000 0x80>;
5381 + interrupts = <0 46 0x4>;
5382 + ti,hwmods = "timer10";
5383 + clocks = <&timer10_gfclk_mux>;
5384 + clock-names = "fck";
5385 + };
5386 +
5387 + timer11: timer@48088000 {
5388 + compatible = "ti,omap5430-timer";
5389 + reg = <0x48088000 0x80>;
5390 + interrupts = <0 47 0x4>;
5391 + ti,hwmods = "timer11";
5392 + clocks = <&timer11_gfclk_mux>;
5393 + clock-names = "fck";
5394 + ti,timer-pwm;
5395 + };
5396 +
5397 + timer13: timer@48828000 {
5398 + compatible = "ti,omap5430-timer";
5399 + reg = <0x48828000 0x80>;
5400 + ti,hwmods = "timer13";
5401 + status = "disabled";
5402 + };
5403 +
5404 + timer14: timer@4882a000 {
5405 + compatible = "ti,omap5430-timer";
5406 + reg = <0x4882a000 0x80>;
5407 + ti,hwmods = "timer14";
5408 + status = "disabled";
5409 + };
5410 +
5411 + timer15: timer@4882c000 {
5412 + compatible = "ti,omap5430-timer";
5413 + reg = <0x4882c000 0x80>;
5414 + ti,hwmods = "timer15";
5415 + status = "disabled";
5416 + };
5417 +
5418 + timer16: timer@4882e000 {
5419 + compatible = "ti,omap5430-timer";
5420 + reg = <0x4882e000 0x80>;
5421 + ti,hwmods = "timer16";
5422 + status = "disabled";
5423 + };
5424 +
5425 + wdt2: wdt@4ae14000 {
5426 + compatible = "ti,omap4-wdt";
5427 + reg = <0x4ae14000 0x80>;
5428 + interrupts = <0 80 0x4>;
5429 + ti,hwmods = "wd_timer2";
5430 + clocks = <&sys_32k_ck>;
5431 + clock-names = "fck";
5432 + };
5433 +
5434 + i2c1: i2c@48070000 {
5435 + compatible = "ti,omap4-i2c";
5436 + reg = <0x48070000 0x100>;
5437 + interrupts = <0 56 0x4>;
5438 + #address-cells = <1>;
5439 + #size-cells = <0>;
5440 + ti,hwmods = "i2c1";
5441 + clocks = <&func_96m_fclk>;
5442 + clock-names = "fck";
5443 + status = "disabled";
5444 + };
5445 +
5446 + i2c2: i2c@48072000 {
5447 + compatible = "ti,omap4-i2c";
5448 + reg = <0x48072000 0x100>;
5449 + interrupts = <0 57 0x4>;
5450 + #address-cells = <1>;
5451 + #size-cells = <0>;
5452 + ti,hwmods = "i2c2";
5453 + clocks = <&func_96m_fclk>;
5454 + clock-names = "fck";
5455 + status = "disabled";
5456 + };
5457 +
5458 + i2c3: i2c@48060000 {
5459 + compatible = "ti,omap4-i2c";
5460 + reg = <0x48060000 0x100>;
5461 + interrupts = <0 61 0x4>;
5462 + #address-cells = <1>;
5463 + #size-cells = <0>;
5464 + ti,hwmods = "i2c3";
5465 + clocks = <&func_96m_fclk>;
5466 + clock-names = "fck";
5467 + status = "disabled";
5468 + };
5469 +
5470 + i2c4: i2c@4807a000 {
5471 + compatible = "ti,omap4-i2c";
5472 + reg = <0x4807a000 0x100>;
5473 + interrupts = <0 62 0x4>;
5474 + #address-cells = <1>;
5475 + #size-cells = <0>;
5476 + ti,hwmods = "i2c4";
5477 + clocks = <&func_96m_fclk>;
5478 + clock-names = "fck";
5479 + status = "disabled";
5480 + };
5481 +
5482 + i2c5: i2c@4807c000 {
5483 + compatible = "ti,omap4-i2c";
5484 + reg = <0x4807c000 0x100>;
5485 + interrupts = <0 60 0x4>;
5486 + #address-cells = <1>;
5487 + #size-cells = <0>;
5488 + ti,hwmods = "i2c5";
5489 + clocks = <&func_96m_fclk>;
5490 + clock-names = "fck";
5491 + status = "disabled";
5492 + };
5493 +
5494 + mmc1: mmc@4809c000 {
5495 + compatible = "ti,omap4-hsmmc";
5496 + reg = <0x4809c000 0x400>;
5497 + interrupts = <0 83 0x4>;
5498 + ti,hwmods = "mmc1";
5499 + clocks = <&mmc1_fclk_div>, <&mmc1_clk32k>;
5500 + clock-names = "fck", "clk32k";
5501 + ti,dual-volt;
5502 + ti,needs-special-reset;
5503 + dmas = <&sdma 61>, <&sdma 62>;
5504 + dma-names = "tx", "rx";
5505 + status = "disabled";
5506 + };
5507 +
5508 + mmc2: mmc@480b4000 {
5509 + compatible = "ti,omap4-hsmmc";
5510 + reg = <0x480b4000 0x400>;
5511 + interrupts = <0 86 0x4>;
5512 + ti,hwmods = "mmc2";
5513 + clocks = <&mmc2_fclk_div>, <&mmc2_clk32k>;
5514 + clock-names = "fck", "clk32k";
5515 + ti,needs-special-reset;
5516 + dmas = <&sdma 47>, <&sdma 48>;
5517 + dma-names = "tx", "rx";
5518 + status = "disabled";
5519 + };
5520 +
5521 + mmc3: mmc@480ad000 {
5522 + compatible = "ti,omap4-hsmmc";
5523 + reg = <0x480ad000 0x400>;
5524 + interrupts = <0 94 0x4>;
5525 + ti,hwmods = "mmc3";
5526 + clocks = <&mmc3_gfclk_div>, <&mmc3_clk32k>;
5527 + clock-names = "fck", "clk32k";
5528 + ti,needs-special-reset;
5529 + dmas = <&sdma 77>, <&sdma 78>;
5530 + dma-names = "tx", "rx";
5531 + status = "disabled";
5532 + };
5533 +
5534 + mmc4: mmc@480d1000 {
5535 + compatible = "ti,omap4-hsmmc";
5536 + reg = <0x480d1000 0x400>;
5537 + interrupts = <0 96 0x4>;
5538 + ti,hwmods = "mmc4";
5539 + clocks = <&mmc4_gfclk_div>, <&mmc4_clk32k>;
5540 + clock-names = "fck", "clk32k";
5541 + ti,needs-special-reset;
5542 + dmas = <&sdma 57>, <&sdma 58>;
5543 + dma-names = "tx", "rx";
5544 + status = "disabled";
5545 + };
5546 +
5547 + qspi: qspi@4b300000 {
5548 + compatible = "ti,dra7xxx-qspi";
5549 + reg = <0x4b300000 0x100>, <0x4a002558 0x4>,
5550 + <0x5c000000 0x3ffffff>;
5551 + reg-names = "qspi_base",
5552 + "qspi_ctrlmod",
5553 + "qspi_mmap";
5554 + #address-cells = <1>;
5555 + #size-cells = <0>;
5556 + ti,hwmods = "qspi";
5557 + ti,spi-num-cs = <4>;
5558 + interrupts = <0 124 0x4>;
5559 + mmap_read;
5560 + };
5561 +
5562 + omap_control_sata: control-phy@4a002374 {
5563 + compatible = "ti,control-phy-pipe3";
5564 + reg = <0x4a002374 0x4>;
5565 + reg-names = "power";
5566 + clocks = <&sys_clkin1>;
5567 + clock-names = "sysclk";
5568 + };
5569 +
5570 + ocp2scp@4a090000 {
5571 + compatible = "ti,omap-ocp2scp";
5572 + #address-cells = <1>;
5573 + #size-cells = <1>;
5574 + ranges;
5575 + ti,hwmods = "ocp2scp3";
5576 + reg = <0x4a090000 0x400>; /* ocp2scp3 */
5577 + sata_phy: sata-phy@4A096000 {
5578 + compatible = "ti,phy-pipe3-sata";
5579 + reg = <0x4A096000 0x80>, /* phy_rx */
5580 + <0x4A096400 0x64>, /* phy_tx */
5581 + <0x4A096800 0x40>; /* pll_ctrl */
5582 + reg-names = "phy_rx", "phy_tx", "pll_ctrl";
5583 + ctrl-module = <&omap_control_sata>;
5584 + clocks = <&sata_ref_clk>;
5585 + clock-names = "refclk";
5586 + #phy-cells = <0>;
5587 + };
5588 + };
5589 +
5590 + sata@4a141100 {
5591 + compatible = "ti,sata";
5592 + ti,hwmods = "sata";
5593 + reg = <0x4a141100 0x100>;
5594 + #address-cells = <1>;
5595 + #size-cells = <1>;
5596 + ranges;
5597 + sata@4a140000 {
5598 + compatible = "snps,dwc-ahci";
5599 + reg = <0x4a140000 0x1100>;
5600 + interrupts = <0 54 0x4>;
5601 + phys = <&sata_phy>;
5602 + phy-names = "sata-phy";
5603 + };
5604 + };
5605 +
5606 +
5607 + mcspi1: spi@48098000 {
5608 + compatible = "ti,omap4-mcspi";
5609 + reg = <0x48098000 0x200>;
5610 + interrupts = <0 65 0x4>;
5611 + #address-cells = <1>;
5612 + #size-cells = <0>;
5613 + ti,hwmods = "mcspi1";
5614 + clocks = <&func_48m_fclk>;
5615 + clock-names = "fck";
5616 + ti,spi-num-cs = <4>;
5617 + dmas = <&sdma 35>,
5618 + <&sdma 36>,
5619 + <&sdma 37>,
5620 + <&sdma 38>,
5621 + <&sdma 39>,
5622 + <&sdma 40>,
5623 + <&sdma 41>,
5624 + <&sdma 42>;
5625 + dma-names = "tx0", "rx0", "tx1", "rx1",
5626 + "tx2", "rx2", "tx3", "rx3";
5627 + status = "disabled";
5628 + };
5629 +
5630 + mcspi2: spi@4809a000 {
5631 + compatible = "ti,omap4-mcspi";
5632 + reg = <0x4809a000 0x200>;
5633 + interrupts = <0 66 0x4>;
5634 + #address-cells = <1>;
5635 + #size-cells = <0>;
5636 + ti,hwmods = "mcspi2";
5637 + clocks = <&func_48m_fclk>;
5638 + clock-names = "fck";
5639 + ti,spi-num-cs = <2>;
5640 + dmas = <&sdma 43>,
5641 + <&sdma 44>,
5642 + <&sdma 45>,
5643 + <&sdma 46>;
5644 + dma-names = "tx0", "rx0", "tx1", "rx1";
5645 + status = "disabled";
5646 + };
5647 +
5648 + mcspi3: spi@480b8000 {
5649 + compatible = "ti,omap4-mcspi";
5650 + reg = <0x480b8000 0x200>;
5651 + interrupts = <0 91 0x4>;
5652 + #address-cells = <1>;
5653 + #size-cells = <0>;
5654 + ti,hwmods = "mcspi3";
5655 + clocks = <&func_48m_fclk>;
5656 + clock-names = "fck";
5657 + ti,spi-num-cs = <2>;
5658 + dmas = <&sdma 15>, <&sdma 16>;
5659 + dma-names = "tx0", "rx0";
5660 + status = "disabled";
5661 + };
5662 +
5663 + mcspi4: spi@480ba000 {
5664 + compatible = "ti,omap4-mcspi";
5665 + reg = <0x480ba000 0x200>;
5666 + interrupts = <0 48 0x4>;
5667 + #address-cells = <1>;
5668 + #size-cells = <0>;
5669 + ti,hwmods = "mcspi4";
5670 + clocks = <&func_48m_fclk>;
5671 + clock-names = "fck";
5672 + ti,spi-num-cs = <1>;
5673 + dmas = <&sdma 70>, <&sdma 71>;
5674 + dma-names = "tx0", "rx0";
5675 + status = "disabled";
5676 + };
5677 +
5678 + rtcss@48838000 {
5679 + compatible = "ti,da830-rtc";
5680 + reg = <0x48838000 0x100>;
5681 + interrupts = <0 159 0x4>,
5682 + <0 159 0x4>;
5683 + ti,hwmods = "rtcss";
5684 + clocks = <&sys_32k_ck>;
5685 + clock-names = "fck";
5686 + };
5687 +
5688 + omap_control_usb2phy1: control-phy@4a002300 {
5689 + compatible = "ti,control-phy-usb2";
5690 + reg = <0x4a002300 0x4>;
5691 + reg-names = "power";
5692 + };
5693 +
5694 + omap_control_usb3phy1: control-phy@4a002370 {
5695 + compatible = "ti,control-phy-pipe3";
5696 + reg = <0x4a002370 0x4>;
5697 + reg-names = "power";
5698 + };
5699 +
5700 + omap_control_usb2phy2: control-phy@0x4a002e74 {
5701 + compatible = "ti,control-phy-dra7usb2";
5702 + reg = <0x4a002e74 0x4>;
5703 + reg-names = "power";
5704 + };
5705 +
5706 + ocp2scp@4a080000 {
5707 + compatible = "ti,omap-ocp2scp";
5708 + #address-cells = <1>;
5709 + #size-cells = <1>;
5710 + ranges;
5711 + ti,hwmods = "ocp2scp1";
5712 + reg = <0x4a080000 0x400>; /* ocp2scp1 */
5713 +
5714 + usb2_phy1: usb2phy1@4a084000 {
5715 + compatible = "ti,omap-usb2";
5716 + reg = <0x4a084000 0x400>;
5717 + ctrl-module = <&omap_control_usb2phy1>;
5718 + clocks = <&usb_phy1_always_on_clk32k>,
5719 + <&usb_otg_ss1_refclk960m>;
5720 + clock-names = "wkupclk",
5721 + "refclk";
5722 + #phy-cells = <0>;
5723 + };
5724 +
5725 + usb2_phy2: usb2phy2@4a085000 {
5726 + compatible = "ti,omap-usb2";
5727 + reg = <0x4a085000 0x400>;
5728 + ctrl-module = <&omap_control_usb2phy2>;
5729 + clocks = <&usb_phy2_always_on_clk32k>,
5730 + <&usb_otg_ss2_refclk960m>;
5731 + clock-names = "wkupclk",
5732 + "refclk";
5733 + #phy-cells = <0>;
5734 + };
5735 +
5736 + usb3_phy1: usb3phy@4a084400 {
5737 + compatible = "ti,phy-pipe3-usb3";
5738 + reg = <0x4a084400 0x80>,
5739 + <0x4a084800 0x64>,
5740 + <0x4a084c00 0x40>;
5741 + reg-names = "phy_rx", "phy_tx", "pll_ctrl";
5742 + ctrl-module = <&omap_control_usb3phy1>;
5743 + clocks = <&usb_phy1_always_on_clk32k>,
5744 + <&usb_otg_ss1_refclk960m>,
5745 + <&dpll_core_h13x2_ck>;
5746 + clock-names = "wkupclk",
5747 + "refclk",
5748 + "refclk2";
5749 + #phy-cells = <0>;
5750 + };
5751 + };
5752 +
5753 + dwc3_1: omap_dwc3_1@48880000 {
5754 + compatible = "ti,dwc3";
5755 + ti,hwmods = "usb_otg_ss1";
5756 + reg = <0x48880000 0x10000>;
5757 + interrupts = <0 77 4>;
5758 + #address-cells = <1>;
5759 + #size-cells = <1>;
5760 + utmi-mode = <2>;
5761 + ranges;
5762 + usb1: usb@48890000 {
5763 + compatible = "synopsys,dwc3";
5764 + reg = <0x48890000 0x17000>;
5765 + interrupts = <0 76 4>;
5766 + phys = <&usb2_phy1>, <&usb3_phy1>;
5767 + phy-names = "usb2-phy", "usb3-phy";
5768 + tx-fifo-resize;
5769 + maximum-speed = "super-speed";
5770 + dr_mode = "otg";
5771 + };
5772 + };
5773 +
5774 + dwc3_2: omap_dwc3_2@488c0000 {
5775 + compatible = "ti,dwc3";
5776 + ti,hwmods = "usb_otg_ss2";
5777 + reg = <0x488c0000 0x10000>;
5778 + interrupts = <0 92 4>;
5779 + #address-cells = <1>;
5780 + #size-cells = <1>;
5781 + utmi-mode = <2>;
5782 + ranges;
5783 + usb2: usb@488d0000 {
5784 + compatible = "synopsys,dwc3";
5785 + reg = <0x488d0000 0x17000>;
5786 + interrupts = <0 78 4>;
5787 + phys = <&usb2_phy2>;
5788 + phy-names = "usb2-phy";
5789 + tx-fifo-resize;
5790 + maximum-speed = "high-speed";
5791 + dr_mode = "otg";
5792 + };
5793 + };
5794 +
5795 + /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */
5796 + dwc3_3: omap_dwc3_3@48900000 {
5797 + compatible = "ti,dwc3";
5798 + ti,hwmods = "usb_otg_ss3";
5799 + reg = <0x48900000 0x10000>;
5800 + /* interrupts = <0 TBD 4>; */
5801 + #address-cells = <1>;
5802 + #size-cells = <1>;
5803 + utmi-mode = <2>;
5804 + ranges;
5805 + status = "disabled";
5806 + usb3: usb@48910000 {
5807 + compatible = "synopsys,dwc3";
5808 + reg = <0x48910000 0x17000>;
5809 + /* interrupts = <0 93 4>; */
5810 + tx-fifo-resize;
5811 + maximum-speed = "high-speed";
5812 + dr_mode = "otg";
5813 + };
5814 + };
5815 +
5816 + dwc3_4: omap_dwc3_4@48940000 {
5817 + compatible = "ti,dwc3";
5818 + ti,hwmods = "usb_otg_ss4";
5819 + reg = <0x48940000 0x10000>;
5820 + /* interrupts = <0 TBD 4>; */
5821 + #address-cells = <1>;
5822 + #size-cells = <1>;
5823 + utmi-mode = <2>;
5824 + ranges;
5825 + status = "disabled";
5826 + usb4: usb@48950000 {
5827 + compatible = "synopsys,dwc3";
5828 + reg = <0x48950000 0x17000>;
5829 + /* interrupts = <0 TBD 4>; */
5830 + tx-fifo-resize;
5831 + maximum-speed = "high-speed";
5832 + dr_mode = "otg";
5833 + };
5834 + };
5835 +
5836 + dmm: dmm@4e000000 {
5837 + compatible = "ti,omap5-dmm";
5838 + reg = <0x4e000000 0x800>;
5839 + interrupts = <0 113 0x4>;
5840 + ti,hwmods = "dmm";
5841 + };
5842 +
5843 + dss: dss@58000000 {
5844 + compatible = "ti,omap4-dss", "simple-bus";
5845 + reg = <0x58000000 0x80>,
5846 + <0x58004000 0x340>,
5847 + <0x58009000 0x340>;
5848 + ti,hwmods = "dss_core";
5849 + #address-cells = <1>;
5850 + #size-cells = <1>;
5851 + ranges;
5852 +
5853 + dispc@58001000 {
5854 + compatible = "ti,omap4-dispc";
5855 + reg = <0x58001000 0x1000>;
5856 + interrupts = <0 25 0x4>;
5857 + ti,hwmods = "dss_dispc";
5858 + };
5859 +
5860 + dpi1: encoder@0 {
5861 + compatible = "ti,dra7xx-dpi";
5862 + id = <0>;
5863 + channel = <0>;
5864 + };
5865 +
5866 + dpi2: encoder@1 {
5867 + compatible = "ti,dra7xx-dpi";
5868 + id = <1>;
5869 + };
5870 +
5871 + dpi3: encoder@2 {
5872 + compatible = "ti,dra7xx-dpi";
5873 + id = <2>;
5874 + };
5875 +
5876 + hdmi: encoder@58040000 {
5877 + compatible = "ti,omap5-hdmi";
5878 + reg = <0x58040000 0x100>,
5879 + <0x58040200 0x40>,
5880 + <0x58040300 0x40>,
5881 + <0x58060000 0x19000>;
5882 + reg-names = "hdmi_wp", "hdmi_pllctrl",
5883 + "hdmi_txphy", "hdmi_core";
5884 + interrupts = <0 101 0x4>;
5885 + ti,hwmods = "dss_hdmi";
5886 + };
5887 + };
5888 +
5889 + vpe {
5890 + compatible = "ti,vpe";
5891 + ti,hwmods = "vpe";
5892 + reg = <0x489d0000 0x120>,
5893 + <0x489d0300 0x20>,
5894 + <0x489d0400 0x20>,
5895 + <0x489d0500 0x20>,
5896 + <0x489d0600 0x3c>,
5897 + <0x489d0700 0x80>,
5898 + <0x489d5700 0x18>,
5899 + <0x489dd000 0x400>;
5900 + reg-names = "vpe_top",
5901 + "vpe_chr_us0",
5902 + "vpe_chr_us1",
5903 + "vpe_chr_us2",
5904 + "vpe_dei",
5905 + "vpe_sc",
5906 + "vpe_csc",
5907 + "vpdma";
5908 + interrupts = <0 0x9c 0x4>;
5909 + #address-cells = <1>;
5910 + #size-cells = <0>;
5911 + };
5912 +
5913 + mac: ethernet@4a100000 {
5914 + compatible = "ti,cpsw";
5915 + ti,hwmods = "gmac";
5916 + cpdma_channels = <8>;
5917 + ale_entries = <1024>;
5918 + bd_ram_size = <0x2000>;
5919 + no_bd_ram = <0>;
5920 + rx_descs = <64>;
5921 + mac_control = <0x20>;
5922 + slaves = <2>;
5923 + active_slave = <0>;
5924 + cpts_clock_mult = <0x80000000>;
5925 + cpts_clock_shift = <29>;
5926 + reg = <0x48484000 0x800
5927 + 0x48485200 0x100>;
5928 + #address-cells = <1>;
5929 + #size-cells = <1>;
5930 + /*
5931 + * rx_thresh_pend
5932 + * rx_pend
5933 + * tx_pend
5934 + * misc_pend
5935 + */
5936 + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
5937 + <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
5938 + <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
5939 + <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
5940 + ranges;
5941 + status = "disabled";
5942 +
5943 + davinci_mdio: mdio@4a101000 {
5944 + compatible = "ti,davinci_mdio";
5945 + #address-cells = <1>;
5946 + #size-cells = <0>;
5947 + ti,hwmods = "davinci_mdio";
5948 + bus_freq = <1000000>;
5949 + reg = <0x48485000 0x100>;
5950 + };
5951 +
5952 + cpsw_emac0: slave@4a100200 {
5953 + /* Filled in by U-Boot */
5954 + mac-address = [ 00 00 00 00 00 00 ];
5955 + };
5956 +
5957 + cpsw_emac1: slave@4a100300 {
5958 + /* Filled in by U-Boot */
5959 + mac-address = [ 00 00 00 00 00 00 ];
5960 + };
5961 + };
5962 +
5963 + elm: elm@48078000 {
5964 + compatible = "ti,am3352-elm";
5965 + /* compatible = "ti,elm"; */
5966 + reg = <0x48078000 0x2000>;
5967 + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
5968 + ti,hwmods = "elm";
5969 + status = "disabled";
5970 + };
5971 +
5972 + gpmc: gpmc@50000000 {
5973 + compatible = "ti,am3352-gpmc";
5974 + /* compatible = "ti,gpmc"; */
5975 + ti,hwmods = "gpmc";
5976 + reg = <0x50000000 0x2000>;
5977 + interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
5978 + gpmc,num-cs = <8>;
5979 + gpmc,num-waitpins = <2>;
5980 + #address-cells = <2>;
5981 + #size-cells = <1>;
5982 + status = "disabled";
5983 + };
5984 +
5985 + aes: aes@4b500000 {
5986 + compatible = "ti,omap4-aes";
5987 + ti,hwmods = "aes";
5988 + reg = <0x4b500000 0xa0>;
5989 + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
5990 + dmas = <&sdma 111>, <&sdma 110>;
5991 + dma-names = "tx", "rx";
5992 + clocks = <&l3_iclk_div>;
5993 + clock-names = "fck";
5994 + };
5995 +
5996 + des: des@480a5000 {
5997 + compatible = "ti,omap4-des";
5998 + ti,hwmods = "des";
5999 + reg = <0x480a5000 0xa0>;
6000 + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
6001 + dmas = <&sdma 117>, <&sdma 116>;
6002 + dma-names = "tx", "rx";
6003 + clocks = <&l3_iclk_div>;
6004 + clock-names = "fck";
6005 + };
6006 + };
6007 +
6008 + clocks {
6009 + #address-cells = <1>;
6010 + #size-cells = <1>;
6011 + ranges;
6012 + /include/ "dra7xx-clocks.dtsi"
6013 + };
6014 +
6015 + clockdomains {
6016 + coreaon_clkdm: coreaon_clkdm {
6017 + compatible = "ti,clockdomain";
6018 + clocks = <&dpll_usb_ck>;
6019 + };
6020 + };
6021 +};
6022 --- /dev/null
6023 +++ b/arch/arm/boot/dts/dra7-evm.dts
6024 @@ -0,0 +1,761 @@
6025 +/*
6026 + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
6027 + *
6028 + * This program is free software; you can redistribute it and/or modify
6029 + * it under the terms of the GNU General Public License version 2 as
6030 + * published by the Free Software Foundation.
6031 + */
6032 +/dts-v1/;
6033 +
6034 +#include "dra7.dtsi"
6035 +#include <dt-bindings/pinctrl/dra7xx.h>
6036 +
6037 +/ {
6038 + model = "TI DRA7";
6039 + compatible = "ti,dra7-evm", "ti,dra752", "ti,dra7";
6040 +
6041 + memory {
6042 + device_type = "memory";
6043 + reg = <0x80000000 0x60000000>; /* 1536 MB */
6044 + };
6045 +
6046 + extcon1: gpio_usbvid_extcon1 {
6047 + compatible = "ti,gpio-usb-id";
6048 + gpios = <&gpio21 1 0>;
6049 + };
6050 +
6051 + extcon2: gpio_usbvid_extcon2 {
6052 + compatible = "ti,gpio-usb-id";
6053 + gpios = <&gpio21 2 0>;
6054 + };
6055 +
6056 + mmc2_3v3: fixedregulator-mmc2 {
6057 + compatible = "regulator-fixed";
6058 + regulator-name = "mmc2_3v3";
6059 + regulator-min-microvolt = <3300000>;
6060 + regulator-max-microvolt = <3300000>;
6061 + };
6062 +};
6063 +
6064 +&dra7_pmx_core {
6065 + pinctrl-names = "default";
6066 + pinctrl-0 = <
6067 + &vout1_pins
6068 + &irq_pins
6069 + >;
6070 +
6071 + i2c1_pins: pinmux_i2c1_pins {
6072 + pinctrl-single,pins = <
6073 + 0x400 0x60000 /* i2c1_sda */
6074 + 0x404 0x60000 /* i2c1_scl */
6075 + >;
6076 + };
6077 +
6078 + i2c2_pins: pinmux_i2c2_pins {
6079 + pinctrl-single,pins = <
6080 + 0x408 0x60000 /* i2c2_sda */
6081 + 0x40c 0x60000 /* i2c2_scl */
6082 + >;
6083 + };
6084 +
6085 + i2c3_pins: pinmux_i2c3_pins {
6086 + pinctrl-single,pins = <
6087 + 0x410 0x60000 /* i2c3_sda */
6088 + 0x414 0x60000 /* i2c3_scl */
6089 + >;
6090 + };
6091 +
6092 + irq_pins: pinmux_irq_pins {
6093 + pinctrl-single,pins = <
6094 + 0x420 0x1 /* Wakeup2 INPUT | MODE1 */
6095 + >;
6096 + };
6097 +
6098 + mmc1_pins: pinmux_mmc1_pins {
6099 + pinctrl-single,pins = <
6100 + 0x36c 0x4000e /* mmc1sdcd.gpio INPUT | MODE15 */
6101 + >;
6102 + };
6103 +
6104 + mcspi1_pins: pinmux_mcspi1_pins {
6105 + pinctrl-single,pins = <
6106 + 0x3a4 0x40000 /* spi2_clk */
6107 + 0x3a8 0x40000 /* spi2_d1 */
6108 + 0x3ac 0x40000 /* spi2_d0 */
6109 + 0x3b0 0xc0000 /* spi2_cs0 */
6110 + 0x3b4 0xc0000 /* spi2_cs1 */
6111 + 0x3b8 0xe0006 /* spi2_cs2 */
6112 + 0x3bc 0xe0006 /* spi2_cs3 */
6113 + >;
6114 + };
6115 +
6116 + mcspi2_pins: pinmux_mcspi2_pins {
6117 + pinctrl-single,pins = <
6118 + 0x3c0 0x40000 /* spi2_sclk */
6119 + 0x3c4 0xc0000 /* spi2_d1 */
6120 + 0x3c8 0xc0000 /* spi2_d1 */
6121 + 0x3cc 0xe0000 /* spi2_cs0 */
6122 + >;
6123 + };
6124 +
6125 + uart1_pins: pinmux_uart1_pins {
6126 + pinctrl-single,pins = <
6127 + 0x3e0 0xe0000 /* uart1_rxd */
6128 + 0x3e4 0xe0000 /* uart1_txd */
6129 + 0x3e8 0x60003 /* uart1_ctsn */
6130 + 0x3ec 0x60003 /* uart1_rtsn */
6131 + >;
6132 + };
6133 +
6134 + uart2_pins: pinmux_uart2_pins {
6135 + pinctrl-single,pins = <
6136 + 0x3f0 0x60000 /* uart2_rxd */
6137 + 0x3f4 0x60000 /* uart2_txd */
6138 + 0x3f8 0x60000 /* uart2_ctsn */
6139 + 0x3fc 0x60000 /* uart2_rtsn */
6140 + >;
6141 + };
6142 +
6143 + uart3_pins: pinmux_uart3_pins {
6144 + pinctrl-single,pins = <
6145 + 0x248 0xc0000 /* uart3_rxd */
6146 + 0x24c 0xc0000 /* uart3_txd */
6147 + >;
6148 + };
6149 +
6150 + qspi1_pins: pinmux_qspi1_pins {
6151 + pinctrl-single,pins = <
6152 + 0x4c 0x40001 /* gpmc_a3.qspi1_cs2 */
6153 + 0x50 0x40001 /* gpmc_a4.qspi1_cs3 */
6154 + 0x74 0x40001 /* gpmc_a13.qspi1_rtclk */
6155 + 0x78 0x40001 /* gpmc_a14.qspi1_d3 */
6156 + 0x7c 0x40001 /* gpmc_a15.qspi1_d2 */
6157 + 0x80 0x40001 /* gpmc_a16.qspi1_d1 */
6158 + 0x84 0x40001 /* gpmc_a17.qspi1_d0 */
6159 + 0x88 0x40001 /* qpmc_a18.qspi1_sclk */
6160 + 0xb8 0x60001 /* gpmc_cs2.qspi1_cs0 */
6161 + 0xbc 0x60001 /* gpmc_cs3.qspi1_cs1 */
6162 + >;
6163 + };
6164 +
6165 + usb1_pins: pinmux_usb1_pins {
6166 + pinctrl-single,pins = <
6167 + 0x280 0xc0000 /* usb1_drvvbus, SLOW_SLEW | PULLUPEN | MODE0 */
6168 + >;
6169 + };
6170 +
6171 + usb2_pins: pinmux_usb2_pins {
6172 + pinctrl-single,pins = <
6173 + 0x284 0xc0000 /* usb2_drvvbus, SLOW_SLEW | PULLUPEN | MODE0 */
6174 + >;
6175 + };
6176 +
6177 + vout1_pins: pinmux_vout1_pins {
6178 + pinctrl-single,pins = <
6179 + 0x1C8 0x0 /* vout1_clk OUTPUT | MODE0 */
6180 + 0x1CC 0x0 /* vout1_de OUTPUT | MODE0 */
6181 + 0x1D0 0x0 /* vout1_fld OUTPUT | MODE0 */
6182 + 0x1D4 0x0 /* vout1_hsync OUTPUT | MODE0 */
6183 + 0x1D8 0x0 /* vout1_vsync OUTPUT | MODE0 */
6184 + 0x1DC 0x0 /* vout1_d0 OUTPUT | MODE0 */
6185 + 0x1E0 0x0 /* vout1_d1 OUTPUT | MODE0 */
6186 + 0x1E4 0x0 /* vout1_d2 OUTPUT | MODE0 */
6187 + 0x1E8 0x0 /* vout1_d3 OUTPUT | MODE0 */
6188 + 0x1EC 0x0 /* vout1_d4 OUTPUT | MODE0 */
6189 + 0x1F0 0x0 /* vout1_d5 OUTPUT | MODE0 */
6190 + 0x1F4 0x0 /* vout1_d6 OUTPUT | MODE0 */
6191 + 0x1F8 0x0 /* vout1_d7 OUTPUT | MODE0 */
6192 + 0x1FC 0x0 /* vout1_d8 OUTPUT | MODE0 */
6193 + 0x200 0x0 /* vout1_d9 OUTPUT | MODE0 */
6194 + 0x204 0x0 /* vout1_d10 OUTPUT | MODE0 */
6195 + 0x208 0x0 /* vout1_d11 OUTPUT | MODE0 */
6196 + 0x20C 0x0 /* vout1_d12 OUTPUT | MODE0 */
6197 + 0x210 0x0 /* vout1_d13 OUTPUT | MODE0 */
6198 + 0x214 0x0 /* vout1_d14 OUTPUT | MODE0 */
6199 + 0x218 0x0 /* vout1_d15 OUTPUT | MODE0 */
6200 + 0x21C 0x0 /* vout1_d16 OUTPUT | MODE0 */
6201 + 0x220 0x0 /* vout1_d17 OUTPUT | MODE0 */
6202 + 0x224 0x0 /* vout1_d18 OUTPUT | MODE0 */
6203 + 0x228 0x0 /* vout1_d19 OUTPUT | MODE0 */
6204 + 0x22C 0x0 /* vout1_d20 OUTPUT | MODE0 */
6205 + 0x230 0x0 /* vout1_d21 OUTPUT | MODE0 */
6206 + 0x234 0x0 /* vout1_d22 OUTPUT | MODE0 */
6207 + 0x238 0x0 /* vout1_d23 OUTPUT | MODE0 */
6208 + >;
6209 + };
6210 +
6211 + cpsw_default: cpsw_default {
6212 + pinctrl-single,pins = <
6213 + /* Slave 1 */
6214 + 0x250 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_tclk */
6215 + 0x254 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_tctl */
6216 + 0x258 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_td3 */
6217 + 0x25c (PIN_OUTPUT | MUX_MODE0) /* rgmii1_td2 */
6218 + 0x260 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_td1 */
6219 + 0x264 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_td0 */
6220 + 0x268 (PIN_INPUT | MUX_MODE0) /* rgmii1_rclk */
6221 + 0x26c (PIN_INPUT | MUX_MODE0) /* rgmii1_rctl */
6222 + 0x270 (PIN_INPUT | MUX_MODE0) /* rgmii1_rd3 */
6223 + 0x274 (PIN_INPUT | MUX_MODE0) /* rgmii1_rd2 */
6224 + 0x278 (PIN_INPUT | MUX_MODE0) /* rgmii1_rd1 */
6225 + 0x27c (PIN_INPUT | MUX_MODE0) /* rgmii1_rd0 */
6226 +
6227 + /* Slave 2 */
6228 + 0x198 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_tclk */
6229 + 0x19c (PIN_OUTPUT | MUX_MODE3) /* rgmii2_tctl */
6230 + 0x1a0 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td3 */
6231 + 0x1a4 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td2 */
6232 + 0x1a8 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td1 */
6233 + 0x1ac (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td0 */
6234 + 0x1b0 (PIN_INPUT | MUX_MODE3) /* rgmii2_rclk */
6235 + 0x1b4 (PIN_INPUT | MUX_MODE3) /* rgmii2_rctl */
6236 + 0x1b8 (PIN_INPUT | MUX_MODE3) /* rgmii2_rd3 */
6237 + 0x1bc (PIN_INPUT | MUX_MODE3) /* rgmii2_rd2 */
6238 + 0x1c0 (PIN_INPUT | MUX_MODE3) /* rgmii2_rd1 */
6239 + 0x1c4 (PIN_INPUT | MUX_MODE3) /* rgmii2_rd0 */
6240 + >;
6241 +
6242 + };
6243 + cpsw_sleep: cpsw_sleep {
6244 + pinctrl-single,pins = <
6245 + /* Slave 1 */
6246 + 0x250 (PIN_OFF_NONE)
6247 + 0x254 (PIN_OFF_NONE)
6248 + 0x258 (PIN_OFF_NONE)
6249 + 0x25c (PIN_OFF_NONE)
6250 + 0x260 (PIN_OFF_NONE)
6251 + 0x264 (PIN_OFF_NONE)
6252 + 0x268 (PIN_OFF_NONE)
6253 + 0x26c (PIN_OFF_NONE)
6254 + 0x270 (PIN_OFF_NONE)
6255 + 0x274 (PIN_OFF_NONE)
6256 + 0x278 (PIN_OFF_NONE)
6257 + 0x27c (PIN_OFF_NONE)
6258 +
6259 + /* Slave 1 */
6260 + 0x198 (PIN_OFF_NONE)
6261 + 0x19c (PIN_OFF_NONE)
6262 + 0x1a0 (PIN_OFF_NONE)
6263 + 0x1a4 (PIN_OFF_NONE)
6264 + 0x1a8 (PIN_OFF_NONE)
6265 + 0x1ac (PIN_OFF_NONE)
6266 + 0x1b0 (PIN_OFF_NONE)
6267 + 0x1b4 (PIN_OFF_NONE)
6268 + 0x1b8 (PIN_OFF_NONE)
6269 + 0x1bc (PIN_OFF_NONE)
6270 + 0x1c0 (PIN_OFF_NONE)
6271 + 0x1c4 (PIN_OFF_NONE)
6272 + >;
6273 + };
6274 +
6275 + davinci_mdio_default: davinci_mdio_default {
6276 + pinctrl-single,pins = <
6277 + /* MDIO */
6278 + 0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_data */
6279 + 0x240 (PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk */
6280 + >;
6281 + };
6282 +
6283 + davinci_mdio_sleep: davinci_mdio_sleep {
6284 + pinctrl-single,pins = <
6285 + 0x23c (PIN_OFF_NONE)
6286 + 0x240 (PIN_OFF_NONE)
6287 + >;
6288 + };
6289 +
6290 + nand_flash_x16: nand_flash_x16 {
6291 + /* On DRA7 EVM, GPMC_WPN and NAND_BOOTn comes from DIP switch
6292 + * So NAND flash requires following switch settings:
6293 + * SW5.9 (GPMC_WPN) = LOW
6294 + * SW5.1 (NAND_BOOTn) = HIGH */
6295 + pinctrl-single,pins = <
6296 + 0x0 0x70000 /* (PIN_INPUT | MUX_MODE0) gpmc_ad0 */
6297 + 0x4 0x70000 /* (PIN_INPUT | MUX_MODE0) gpmc_ad1 */
6298 + 0x8 0x70000 /* (PIN_INPUT | MUX_MODE0) gpmc_ad2 */
6299 + 0xc 0x70000 /* (PIN_INPUT | MUX_MODE0) gpmc_ad3 */
6300 + 0x10 0x70000 /* (PIN_INPUT | MUX_MODE0) gpmc_ad4 */
6301 + 0x14 0x70000 /* (PIN_INPUT | MUX_MODE0) gpmc_ad5 */
6302 + 0x18 0x70000 /* (PIN_INPUT | MUX_MODE0) gpmc_ad6 */
6303 + 0x1c 0x70000 /* (PIN_INPUT | MUX_MODE0) gpmc_ad7 */
6304 + 0x20 0x70000 /* (PIN_INPUT | MUX_MODE0) gpmc_ad8 */
6305 + 0x24 0x70000 /* (PIN_INPUT | MUX_MODE0) gpmc_ad9 */
6306 + 0x28 0x70000 /* (PIN_INPUT | MUX_MODE0) gpmc_ad10 */
6307 + 0x2c 0x70000 /* (PIN_INPUT | MUX_MODE0) gpmc_ad11 */
6308 + 0x30 0x70000 /* (PIN_INPUT | MUX_MODE0) gpmc_ad12 */
6309 + 0x34 0x70000 /* (PIN_INPUT | MUX_MODE0) gpmc_ad13 */
6310 + 0x38 0x70000 /* (PIN_INPUT | MUX_MODE0) gpmc_ad14 */
6311 + 0x3c 0x70000 /* (PIN_INPUT | MUX_MODE0) gpmc_ad15 */
6312 + 0xD8 0x70000 /* (PIN_INPUT | MUX_MODE0) gpmc_wait0 */
6313 + 0xCC 0x0 /* (PIN_OUTPUT | MUX_MODE0) gpmc_wen */
6314 + 0xB4 0x0 /* (PIN_OUTPUT | MUX_MODE0) gpmc_csn0 */
6315 + 0xC4 0x0 /* (PIN_OUTPUT | MUX_MODE0) gpmc_advn_ale */
6316 + 0xC8 0x0 /* (PIN_OUTPUT | MUX_MODE0) gpmc_oen_ren */
6317 + 0xD0 0x0 /* (PIN_OUTPUT | MUX_MODE0) gpmc_be0n_cle */
6318 + >;
6319 + };
6320 +};
6321 +
6322 +&i2c1 {
6323 + status = "okay";
6324 + pinctrl-names = "default";
6325 + pinctrl-0 = <&i2c1_pins>;
6326 + clock-frequency = <400000>;
6327 +
6328 + tps659038: tps659038@58 {
6329 + compatible = "ti,tps659038";
6330 + reg = <0x58>;
6331 +
6332 + tps659038_pmic {
6333 + compatible = "ti,tps659038-pmic";
6334 +
6335 + regulators {
6336 + smps123_reg: smps123 {
6337 + /* VDD_MPU */
6338 + regulator-name = "smps123";
6339 + regulator-min-microvolt = < 850000>;
6340 + regulator-max-microvolt = <1250000>;
6341 + regulator-always-on;
6342 + regulator-boot-on;
6343 + };
6344 +
6345 + smps45_reg: smps45 {
6346 + /* VDD_DSPEVE */
6347 + regulator-name = "smps45";
6348 + regulator-min-microvolt = < 850000>;
6349 + regulator-max-microvolt = <1150000>;
6350 + regulator-boot-on;
6351 + };
6352 +
6353 + smps6_reg: smps6 {
6354 + /* VDD_GPU - over VDD_SMPS6 */
6355 + regulator-name = "smps6";
6356 + regulator-min-microvolt = <850000>;
6357 + regulator-max-microvolt = <12500000>;
6358 + regulator-boot-on;
6359 + };
6360 +
6361 + smps7_reg: smps7 {
6362 + /* CORE_VDD */
6363 + regulator-name = "smps7";
6364 + regulator-min-microvolt = <850000>;
6365 + regulator-max-microvolt = <1030000>;
6366 + regulator-always-on;
6367 + regulator-boot-on;
6368 + };
6369 +
6370 + smps8_reg: smps8 {
6371 + /* VDD_IVAHD */
6372 + regulator-name = "smps8";
6373 + regulator-min-microvolt = < 850000>;
6374 + regulator-max-microvolt = <1250000>;
6375 + regulator-boot-on;
6376 + };
6377 +
6378 + smps9_reg: smps9 {
6379 + /* VDDS1V8 */
6380 + regulator-name = "smps9";
6381 + regulator-min-microvolt = <1800000>;
6382 + regulator-max-microvolt = <1800000>;
6383 + regulator-always-on;
6384 + regulator-boot-on;
6385 + };
6386 +
6387 + ldo1_reg: ldo1 {
6388 + /* LDO1_OUT --> SDIO */
6389 + regulator-name = "ldo1";
6390 + regulator-min-microvolt = <1800000>;
6391 + regulator-max-microvolt = <3300000>;
6392 + regulator-boot-on;
6393 + };
6394 +
6395 + ldo2_reg: ldo2 {
6396 + /* VDD_RTCIO */
6397 + /* LDO2 -> VDDSHV5, LDO2 also goes to CAN_PHY_3V3 */
6398 + regulator-name = "ldo2";
6399 + regulator-min-microvolt = <3300000>;
6400 + regulator-max-microvolt = <3300000>;
6401 + regulator-boot-on;
6402 + };
6403 +
6404 + ldo3_reg: ldo3 {
6405 + /* VDDA_1V8_PHY */
6406 + regulator-name = "ldo3";
6407 + regulator-min-microvolt = <1800000>;
6408 + regulator-max-microvolt = <1800000>;
6409 + regulator-boot-on;
6410 + };
6411 +
6412 + ldo9_reg: ldo9 {
6413 + /* VDD_RTC */
6414 + regulator-name = "ldo9";
6415 + regulator-min-microvolt = <1050000>;
6416 + regulator-max-microvolt = <1050000>;
6417 + regulator-boot-on;
6418 + };
6419 +
6420 + ldoln_reg: ldoln {
6421 + /* VDDA_1V8_PLL */
6422 + regulator-name = "ldoln";
6423 + regulator-min-microvolt = <1800000>;
6424 + regulator-max-microvolt = <1800000>;
6425 + regulator-always-on;
6426 + regulator-boot-on;
6427 + };
6428 +
6429 + ldousb_reg: ldousb {
6430 + /* VDDA_3V_USB: VDDA_USBHS33 */
6431 + regulator-name = "ldousb";
6432 + regulator-min-microvolt = <3300000>;
6433 + regulator-max-microvolt = <3300000>;
6434 + regulator-boot-on;
6435 + };
6436 +
6437 + };
6438 + };
6439 + };
6440 +
6441 + pcf_gpio_20: gpio@20 {
6442 + compatible = "ti,pcf8575";
6443 + reg = <0x20>;
6444 + lines-initial-states = <0x4000>;
6445 + gpio-controller;
6446 + #gpio-cells = <2>;
6447 + interrupt-parent = <&gpio6>;
6448 + interrupts = <11 2>;
6449 + interrupt-controller;
6450 + #interrupt-cells = <2>;
6451 + };
6452 +
6453 + gpio21: gpio@21 {
6454 + compatible = "ti,pcf8575";
6455 + reg = <0x21>;
6456 + lines-initial-states = <0x1408>;
6457 + gpio-controller;
6458 + #gpio-cells = <2>;
6459 + interrupt-parent = <&pcf_gpio_20>;
6460 + interrupts = <14 2>;
6461 + interrupt-controller;
6462 + #interrupt-cells = <2>;
6463 + };
6464 +
6465 + /* TLC chip for LCD panel power and backlight */
6466 + tlc59108: tlc59108@40 {
6467 + compatible = "ti,tlc59108";
6468 + reg = <0x40>;
6469 + gpios = <&pcf_gpio_20 13 0>; /* P15, CON_LCD_PWR_DN */
6470 + video-source = <&dpi1>;
6471 + data-lines = <24>;
6472 + };
6473 +
6474 + mxt244: touchscreen@4a {
6475 + compatible = "atmel,mXT244";
6476 + status = "okay";
6477 + reg = <0x4a>;
6478 + interrupts = <0 119 0x4>;
6479 +
6480 + atmel,config = <
6481 + /* MXT244_GEN_COMMAND(6) */
6482 + 0x00 0x00 0x00 0x00 0x00 0x00
6483 + /* MXT244_GEN_POWER(7) */
6484 + 0x20 0xff 0x32
6485 + /* MXT244_GEN_ACQUIRE(8) */
6486 + 0x0a 0x00 0x05 0x00 0x00 0x00 0x09 0x23
6487 + /* MXT244_TOUCH_MULTI(9) */
6488 + 0x00 0x00 0x00 0x13 0x0b 0x00 0x00 0x00 0x02 0x00
6489 + 0x00 0x01 0x01 0x0e 0x0a 0x0a 0x0a 0x0a 0x00 0x00
6490 + 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
6491 + 0x00
6492 + /* MXT244_TOUCH_KEYARRAY(15) */
6493 + 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
6494 + 0x00
6495 + /* MXT244_COMMSCONFIG_T18(2) */
6496 + 0x00 0x00
6497 + /* MXT244_SPT_GPIOPWM(19) */
6498 + 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
6499 + 0x00 0x00 0x00 0x00 0x00 0x00
6500 + /* MXT244_PROCI_GRIPFACE(20) */
6501 + 0x07 0x00 0x00 0x00 0x00 0x00 0x00 0x50 0x28 0x04
6502 + 0x0f 0x0a
6503 + /* MXT244_PROCG_NOISE(22) */
6504 + 0x05 0x00 0x00 0x00 0x00 0x00 0x00 0x03 0x23 0x00
6505 + 0x00 0x05 0x0f 0x19 0x23 0x2d 0x03
6506 + /* MXT244_TOUCH_PROXIMITY(23) */
6507 + 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
6508 + 0x00 0x00 0x00 0x00 0x00
6509 + /* MXT244_PROCI_ONETOUCH(24) */
6510 + 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
6511 + 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
6512 + /* MXT244_SPT_SELFTEST(25) */
6513 + 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
6514 + 0x00 0x00 0x00 0x00
6515 + /* MXT244_PROCI_TWOTOUCH(27) */
6516 + 0x00 0x00 0x00 0x00 0x00 0x00 0x00
6517 + /* MXT244_SPT_CTECONFIG(28) */
6518 + 0x00 0x00 0x02 0x08 0x10 0x00
6519 + >;
6520 +
6521 + atmel,x_line = <18>;
6522 + atmel,y_line = <12>;
6523 + atmel,x_size = <800>;
6524 + atmel,y_size = <480>;
6525 + atmel,blen = <0x01>;
6526 + atmel,threshold = <30>;
6527 + atmel,voltage = <2800000>;
6528 + atmel,orient = <0x4>;
6529 + };
6530 +};
6531 +
6532 +&i2c2 {
6533 + status = "okay";
6534 + pinctrl-names = "default";
6535 + pinctrl-0 = <&i2c2_pins>;
6536 + clock-frequency = <400000>;
6537 +
6538 + pcf_hdmi: gpio@26 {
6539 + compatible = "nxp,pcf8575";
6540 + reg = <0x26>;
6541 + gpio-controller;
6542 + #gpio-cells = <2>;
6543 + };
6544 +};
6545 +
6546 +&i2c3 {
6547 + status = "okay";
6548 + pinctrl-names = "default";
6549 + pinctrl-0 = <&i2c3_pins>;
6550 + clock-frequency = <3400000>;
6551 +};
6552 +
6553 +&mcspi1 {
6554 + status = "okay";
6555 + pinctrl-names = "default";
6556 + pinctrl-0 = <&mcspi1_pins>;
6557 +};
6558 +
6559 +&mcspi2 {
6560 + status = "okay";
6561 + pinctrl-names = "default";
6562 + pinctrl-0 = <&mcspi2_pins>;
6563 +};
6564 +
6565 +&uart1 {
6566 + status = "okay";
6567 + pinctrl-names = "default";
6568 + pinctrl-0 = <&uart1_pins>;
6569 +};
6570 +
6571 +&uart2 {
6572 + status = "okay";
6573 + pinctrl-names = "default";
6574 + pinctrl-0 = <&uart2_pins>;
6575 +};
6576 +
6577 +&uart3 {
6578 + status = "okay";
6579 + pinctrl-names = "default";
6580 + pinctrl-0 = <&uart3_pins>;
6581 +};
6582 +
6583 +&qspi {
6584 + status = "okay";
6585 + pinctrl-names = "default";
6586 + pinctrl-0 = <&qspi1_pins>;
6587 +
6588 + spi-max-frequency = <48000000>;
6589 + m25p80@0 {
6590 + compatible = "s25fl256s1";
6591 + spi-max-frequency = <48000000>;
6592 + reg = <0>;
6593 + spi-tx-bus-width = <1>;
6594 + spi-rx-bus-width = <4>;
6595 + spi-cpol;
6596 + spi-cpha;
6597 + };
6598 +};
6599 +
6600 +&usb1 {
6601 + dr_mode = "peripheral";
6602 + pinctrl-names = "default";
6603 + pinctrl-0 = <&usb1_pins>;
6604 +};
6605 +
6606 +&usb2 {
6607 + dr_mode = "host";
6608 + pinctrl-names = "default";
6609 + pinctrl-0 = <&usb2_pins>;
6610 +};
6611 +
6612 +&dwc3_1 {
6613 + extcon = <&extcon1>;
6614 +};
6615 +
6616 +&dwc3_2 {
6617 + extcon = <&extcon2>;
6618 +};
6619 +
6620 +&mmc1 {
6621 + status = "okay";
6622 + vmmc-supply = <&ldo1_reg>;
6623 + bus-width = <4>;
6624 + pinctrl-names = "default";
6625 + pinctrl-0 = <&mmc1_pins>;
6626 + cd-gpios = <&gpio6 27 0>; /* gpio 187 */
6627 +};
6628 +
6629 +&mmc2 {
6630 + status = "okay";
6631 + vmmc-supply = <&mmc2_3v3>;
6632 + bus-width = <8>;
6633 + ti,non-removable;
6634 +};
6635 +
6636 +&dss {
6637 + vdda_video-supply = <&ldoln_reg>;
6638 +};
6639 +
6640 +&hdmi {
6641 + vdda_hdmi_dac-supply = <&ldo3_reg>;
6642 +};
6643 +
6644 +&avs_mpu {
6645 + avs-supply = <&smps123_reg>;
6646 +};
6647 +
6648 +&avs_core {
6649 + avs-supply = <&smps7_reg>;
6650 +};
6651 +
6652 +&avs_gpu {
6653 + avs-supply = <&smps6_reg>;
6654 +};
6655 +
6656 +&avs_dspeve {
6657 + avs-supply = <&smps45_reg>;
6658 +};
6659 +
6660 +&avs_iva {
6661 + avs-supply = <&smps8_reg>;
6662 +};
6663 +
6664 +&cpu0 {
6665 + cpu0-supply = <&avs_mpu>;
6666 +};
6667 +
6668 +/ {
6669 + aliases {
6670 + display0 = &tlc59108;
6671 + display1 = &hdmi0;
6672 + };
6673 +
6674 + tpd12s015: encoder@0 {
6675 + compatible = "ti,draevm-tpd12s015";
6676 +
6677 + video-source = <&hdmi>;
6678 +
6679 + gpios = <&pcf_hdmi 4 0>, /* P4, CT CP HPD */
6680 + <&pcf_hdmi 5 0>, /* P5, LS OE */
6681 + <&gpio7 12 0>; /* gpio7_12/sp1_cs2, HPD */
6682 + };
6683 +
6684 + hdmi0: connector@0 {
6685 + compatible = "ti,hdmi_connector";
6686 +
6687 + video-source = <&tpd12s015>;
6688 + };
6689 +};
6690 +
6691 +&mac {
6692 + status = "okay";
6693 + pinctrl-names = "default", "sleep";
6694 + pinctrl-0 = <&cpsw_default>;
6695 + pinctrl-1 = <&cpsw_sleep>;
6696 +};
6697 +
6698 +&cpsw_emac0 {
6699 + phy_id = <&davinci_mdio>, <2>;
6700 +};
6701 +
6702 +&cpsw_emac1 {
6703 + phy_id = <&davinci_mdio>, <3>;
6704 +};
6705 +
6706 +&davinci_mdio {
6707 + pinctrl-names = "default", "sleep";
6708 + pinctrl-0 = <&davinci_mdio_default>;
6709 + pinctrl-1 = <&davinci_mdio_sleep>;
6710 +};
6711 +
6712 +&elm {
6713 + status = "okay";
6714 +};
6715 +
6716 +&gpmc {
6717 + status = "okay";
6718 + pinctrl-names = "default";
6719 + pinctrl-0 = <&nand_flash_x16>;
6720 + ranges = <0 0 0x08000000 0x10000000>;
6721 + nand@0,0 {
6722 + reg = <0 0 0>;
6723 + nand-bus-width = <16>;
6724 + ti,nand-ecc-opt = "bch8";
6725 + gpmc,device-width = <2>;
6726 + gpmc,sync-clk-ps = <0>;
6727 + gpmc,cs-on-ns = <0>;
6728 + gpmc,cs-rd-off-ns = <55>;
6729 + gpmc,cs-wr-off-ns = <55>;
6730 + gpmc,adv-on-ns = <0>;
6731 + gpmc,adv-rd-off-ns = <55>;
6732 + gpmc,adv-wr-off-ns = <55>;
6733 + gpmc,we-on-ns = <5>;
6734 + gpmc,we-off-ns = <40>;
6735 + gpmc,oe-on-ns = <2>;
6736 + gpmc,oe-off-ns = <45>;
6737 + gpmc,access-ns = <40>;
6738 + gpmc,wr-access-ns = <37>;
6739 + gpmc,rd-cycle-ns = <55>;
6740 + gpmc,wr-cycle-ns = <55>;
6741 + gpmc,wait-on-read = "true";
6742 + gpmc,wait-on-write = "true";
6743 + gpmc,bus-turnaround-ns = <0>;
6744 + gpmc,cycle2cycle-delay-ns = <0>;
6745 + gpmc,clk-activation-ns = <0>;
6746 + gpmc,wait-monitoring-ns = <0>;
6747 + gpmc,wr-data-mux-bus-ns = <0>;
6748 + #address-cells = <1>;
6749 + #size-cells = <1>;
6750 + ti,elm-id = <&elm>;
6751 + /* MTD partition table */
6752 + partition@0 {
6753 + label = "SPL1";
6754 + reg = <0x00000000 0x000020000>;
6755 + };
6756 + partition@1 {
6757 + label = "SPL2";
6758 + reg = <0x00020000 0x00020000>;
6759 + };
6760 + partition@2 {
6761 + label = "SPL3";
6762 + reg = <0x00040000 0x00020000>;
6763 + };
6764 + partition@3 {
6765 + label = "SPL4";
6766 + reg = <0x00060000 0x00020000>;
6767 + };
6768 + partition@4 {
6769 + label = "U-boot";
6770 + reg = <0x00080000 0x001e0000>;
6771 + };
6772 + partition@5 {
6773 + label = "environment";
6774 + reg = <0x00260000 0x00020000>;
6775 + };
6776 + partition@6 {
6777 + label = "Kernel";
6778 + reg = <0x00280000 0x00500000>;
6779 + };
6780 + partition@7 {
6781 + label = "File-System";
6782 + reg = <0x00780000 0x0F880000>;
6783 + };
6784 + };
6785 +};
6786 --- /dev/null
6787 +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
6788 @@ -0,0 +1,2103 @@
6789 +/*
6790 + * Device Tree Source for DRA7xx clock data
6791 + *
6792 + * Copyright (C) 2013 Texas Instruments, Inc.
6793 + *
6794 + * This program is free software; you can redistribute it and/or modify
6795 + * it under the terms of the GNU General Public License version 2 as
6796 + * published by the Free Software Foundation.
6797 + */
6798 +
6799 +atl_clkin0_ck: atl_clkin0_ck {
6800 + #clock-cells = <0>;
6801 + compatible = "fixed-clock";
6802 + clock-frequency = <0>;
6803 +};
6804 +
6805 +atl_clkin1_ck: atl_clkin1_ck {
6806 + #clock-cells = <0>;
6807 + compatible = "fixed-clock";
6808 + clock-frequency = <0>;
6809 +};
6810 +
6811 +atl_clkin2_ck: atl_clkin2_ck {
6812 + #clock-cells = <0>;
6813 + compatible = "fixed-clock";
6814 + clock-frequency = <0>;
6815 +};
6816 +
6817 +atlclkin3_ck: atlclkin3_ck {
6818 + #clock-cells = <0>;
6819 + compatible = "fixed-clock";
6820 + clock-frequency = <0>;
6821 +};
6822 +
6823 +hdmi_clkin_ck: hdmi_clkin_ck {
6824 + #clock-cells = <0>;
6825 + compatible = "fixed-clock";
6826 + clock-frequency = <0>;
6827 +};
6828 +
6829 +mlb_clkin_ck: mlb_clkin_ck {
6830 + #clock-cells = <0>;
6831 + compatible = "fixed-clock";
6832 + clock-frequency = <0>;
6833 +};
6834 +
6835 +mlbp_clkin_ck: mlbp_clkin_ck {
6836 + #clock-cells = <0>;
6837 + compatible = "fixed-clock";
6838 + clock-frequency = <0>;
6839 +};
6840 +
6841 +pciesref_acs_clk_ck: pciesref_acs_clk_ck {
6842 + #clock-cells = <0>;
6843 + compatible = "fixed-clock";
6844 + clock-frequency = <100000000>;
6845 +};
6846 +
6847 +ref_clkin0_ck: ref_clkin0_ck {
6848 + #clock-cells = <0>;
6849 + compatible = "fixed-clock";
6850 + clock-frequency = <0>;
6851 +};
6852 +
6853 +ref_clkin1_ck: ref_clkin1_ck {
6854 + #clock-cells = <0>;
6855 + compatible = "fixed-clock";
6856 + clock-frequency = <0>;
6857 +};
6858 +
6859 +ref_clkin2_ck: ref_clkin2_ck {
6860 + #clock-cells = <0>;
6861 + compatible = "fixed-clock";
6862 + clock-frequency = <0>;
6863 +};
6864 +
6865 +ref_clkin3_ck: ref_clkin3_ck {
6866 + #clock-cells = <0>;
6867 + compatible = "fixed-clock";
6868 + clock-frequency = <0>;
6869 +};
6870 +
6871 +rmii_clk_ck: rmii_clk_ck {
6872 + #clock-cells = <0>;
6873 + compatible = "fixed-clock";
6874 + clock-frequency = <0>;
6875 +};
6876 +
6877 +sdvenc_clkin_ck: sdvenc_clkin_ck {
6878 + #clock-cells = <0>;
6879 + compatible = "fixed-clock";
6880 + clock-frequency = <0>;
6881 +};
6882 +
6883 +secure_32k_clk_src_ck: secure_32k_clk_src_ck {
6884 + #clock-cells = <0>;
6885 + compatible = "fixed-clock";
6886 + clock-frequency = <32768>;
6887 +};
6888 +
6889 +sys_32k_ck: sys_32k_ck {
6890 + #clock-cells = <0>;
6891 + compatible = "fixed-clock";
6892 + clock-frequency = <32768>;
6893 +};
6894 +
6895 +virt_12000000_ck: virt_12000000_ck {
6896 + #clock-cells = <0>;
6897 + compatible = "fixed-clock";
6898 + clock-frequency = <12000000>;
6899 +};
6900 +
6901 +virt_13000000_ck: virt_13000000_ck {
6902 + #clock-cells = <0>;
6903 + compatible = "fixed-clock";
6904 + clock-frequency = <13000000>;
6905 +};
6906 +
6907 +virt_16800000_ck: virt_16800000_ck {
6908 + #clock-cells = <0>;
6909 + compatible = "fixed-clock";
6910 + clock-frequency = <16800000>;
6911 +};
6912 +
6913 +virt_19200000_ck: virt_19200000_ck {
6914 + #clock-cells = <0>;
6915 + compatible = "fixed-clock";
6916 + clock-frequency = <19200000>;
6917 +};
6918 +
6919 +virt_20000000_ck: virt_20000000_ck {
6920 + #clock-cells = <0>;
6921 + compatible = "fixed-clock";
6922 + clock-frequency = <20000000>;
6923 +};
6924 +
6925 +virt_26000000_ck: virt_26000000_ck {
6926 + #clock-cells = <0>;
6927 + compatible = "fixed-clock";
6928 + clock-frequency = <26000000>;
6929 +};
6930 +
6931 +virt_27000000_ck: virt_27000000_ck {
6932 + #clock-cells = <0>;
6933 + compatible = "fixed-clock";
6934 + clock-frequency = <27000000>;
6935 +};
6936 +
6937 +virt_38400000_ck: virt_38400000_ck {
6938 + #clock-cells = <0>;
6939 + compatible = "fixed-clock";
6940 + clock-frequency = <38400000>;
6941 +};
6942 +
6943 +sys_clkin1: sys_clkin1@4ae06110 {
6944 + #clock-cells = <0>;
6945 + compatible = "mux-clock";
6946 + clocks = <&virt_12000000_ck>, <&virt_20000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
6947 + reg = <0x4ae06110 0x4>;
6948 + bit-mask = <0x7>;
6949 + index-starts-at-one;
6950 +};
6951 +
6952 +sys_clkin2: sys_clkin2 {
6953 + #clock-cells = <0>;
6954 + compatible = "fixed-clock";
6955 + clock-frequency = <22579200>;
6956 +};
6957 +
6958 +usb_otg_clkin_ck: usb_otg_clkin_ck {
6959 + #clock-cells = <0>;
6960 + compatible = "fixed-clock";
6961 + clock-frequency = <0>;
6962 +};
6963 +
6964 +video1_clkin_ck: video1_clkin_ck {
6965 + #clock-cells = <0>;
6966 + compatible = "fixed-clock";
6967 + clock-frequency = <0>;
6968 +};
6969 +
6970 +video1_m2_clkin_ck: video1_m2_clkin_ck {
6971 + #clock-cells = <0>;
6972 + compatible = "fixed-clock";
6973 + clock-frequency = <0>;
6974 +};
6975 +
6976 +video2_clkin_ck: video2_clkin_ck {
6977 + #clock-cells = <0>;
6978 + compatible = "fixed-clock";
6979 + clock-frequency = <0>;
6980 +};
6981 +
6982 +video2_m2_clkin_ck: video2_m2_clkin_ck {
6983 + #clock-cells = <0>;
6984 + compatible = "fixed-clock";
6985 + clock-frequency = <0>;
6986 +};
6987 +
6988 +abe_dpll_sys_clk_mux: abe_dpll_sys_clk_mux@4ae06118 {
6989 + #clock-cells = <0>;
6990 + compatible = "mux-clock";
6991 + clocks = <&sys_clkin1>, <&sys_clkin2>;
6992 + reg = <0x4ae06118 0x4>;
6993 + bit-mask = <0x1>;
6994 +};
6995 +
6996 +abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux@4ae06114 {
6997 + #clock-cells = <0>;
6998 + compatible = "mux-clock";
6999 + clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;
7000 + reg = <0x4ae06114 0x4>;
7001 + bit-mask = <0x1>;
7002 +};
7003 +
7004 +abe_dpll_clk_mux: abe_dpll_clk_mux@4ae0610c {
7005 + #clock-cells = <0>;
7006 + compatible = "mux-clock";
7007 + clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;
7008 + reg = <0x4ae0610c 0x4>;
7009 + bit-mask = <0x1>;
7010 +};
7011 +
7012 +dpll_abe_ck: dpll_abe_ck@4a0051e0 {
7013 + #clock-cells = <0>;
7014 + compatible = "ti,omap4-dpll-m4xen-clock";
7015 + clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;
7016 + reg = <0x4a0051e0 0x4>, <0x4a0051e4 0x4>, <0x4a0051e8 0x4>, <0x4a0051ec 0x4>;
7017 + reg-names = "control", "idlest", "autoidle", "mult-div1";
7018 +};
7019 +
7020 +dpll_abe_x2_ck: dpll_abe_x2_ck {
7021 + #clock-cells = <0>;
7022 + compatible = "ti,omap4-dpll-x2-clock";
7023 + clocks = <&dpll_abe_ck>;
7024 +};
7025 +
7026 +dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@4a0051f0 {
7027 + #clock-cells = <0>;
7028 + compatible = "ti,divider-clock";
7029 + clocks = <&dpll_abe_x2_ck>;
7030 + ti,autoidle-shift = <8>;
7031 + reg = <0x4a0051f0 0x4>;
7032 + bit-mask = <0x1f>;
7033 + index-starts-at-one;
7034 + ti,autoidle-low;
7035 +};
7036 +
7037 +abe_24m_fclk: abe_24m_fclk@4ae0611c {
7038 + #clock-cells = <0>;
7039 + compatible = "divider-clock";
7040 + clocks = <&dpll_abe_m2x2_ck>;
7041 + reg = <0x4ae0611c 0x4>;
7042 + table = < 8 0 >, < 16 1 >;
7043 + bit-mask = <0x1>;
7044 +};
7045 +
7046 +abe_clk: abe_clk@4a005108 {
7047 + #clock-cells = <0>;
7048 + compatible = "divider-clock";
7049 + clocks = <&dpll_abe_m2x2_ck>;
7050 + reg = <0x4a005108 0x4>;
7051 + bit-mask = <0x3>;
7052 + index-power-of-two;
7053 +};
7054 +
7055 +aess_fclk: aess_fclk@4ae06178 {
7056 + #clock-cells = <0>;
7057 + compatible = "divider-clock";
7058 + clocks = <&abe_clk>;
7059 + reg = <0x4ae06178 0x4>;
7060 + bit-mask = <0x1>;
7061 +};
7062 +
7063 +abe_giclk_div: abe_giclk_div@4ae06174 {
7064 + #clock-cells = <0>;
7065 + compatible = "divider-clock";
7066 + clocks = <&aess_fclk>;
7067 + reg = <0x4ae06174 0x4>;
7068 + bit-mask = <0x1>;
7069 +};
7070 +
7071 +abe_lp_clk_div: abe_lp_clk_div@4ae061d8 {
7072 + #clock-cells = <0>;
7073 + compatible = "divider-clock";
7074 + clocks = <&dpll_abe_m2x2_ck>;
7075 + reg = <0x4ae061d8 0x4>;
7076 + table = < 16 0 >, < 32 1 >;
7077 + bit-mask = <0x1>;
7078 +};
7079 +
7080 +abe_sys_clk_div: abe_sys_clk_div@4ae06120 {
7081 + #clock-cells = <0>;
7082 + compatible = "divider-clock";
7083 + clocks = <&sys_clkin1>;
7084 + reg = <0x4ae06120 0x4>;
7085 + bit-mask = <0x1>;
7086 +};
7087 +
7088 +adc_gfclk_mux: adc_gfclk_mux@4ae061dc {
7089 + #clock-cells = <0>;
7090 + compatible = "mux-clock";
7091 + clocks = <&sys_clkin1>, <&sys_clkin2>, <&sys_32k_ck>;
7092 + reg = <0x4ae061dc 0x4>;
7093 + bit-mask = <0x7>;
7094 +};
7095 +
7096 +dpll_pcie_ref_ck: dpll_pcie_ref_ck@4a008200 {
7097 + #clock-cells = <0>;
7098 + compatible = "ti,omap4-dpll-clock";
7099 + clocks = <&sys_clkin1>, <&sys_clkin1>;
7100 + reg = <0x4a008200 0x4>, <0x4a008204 0x4>, <0x4a008208 0x4>, <0x4a00820c 0x4>;
7101 + reg-names = "control", "idlest", "autoidle", "mult-div1";
7102 +};
7103 +
7104 +dpll_pcie_ref_m2ldo_ck: dpll_pcie_ref_m2ldo_ck@4a008210 {
7105 + #clock-cells = <0>;
7106 + compatible = "ti,divider-clock";
7107 + clocks = <&dpll_pcie_ref_ck>;
7108 + ti,autoidle-shift = <8>;
7109 + reg = <0x4a008210 0x4>;
7110 + bit-mask = <0x1f>;
7111 + index-starts-at-one;
7112 + ti,autoidle-low;
7113 +};
7114 +
7115 +apll_pcie_in_clk_mux: apll_pcie_in_clk_mux@4ae06118 {
7116 + compatible = "mux-clock";
7117 + clocks = <&dpll_pcie_ref_ck>, <&pciesref_acs_clk_ck>;
7118 + #clock-cells = <0>;
7119 + reg = <0x4a00821c 0x4>;
7120 + bit-mask = <0x80>;
7121 +};
7122 +
7123 +apll_pcie_ck: apll_pcie_ck@4a008200 {
7124 + #clock-cells = <0>;
7125 + compatible = "ti,dra7-apll-clock";
7126 + clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>;
7127 + reg = <0x4a00821c 0x4>, <0x4a008220 0x4>;
7128 + reg-names = "control", "idlest";
7129 +};
7130 +
7131 +apll_pcie_clkvcoldo: apll_pcie_clkvcoldo {
7132 + #clock-cells = <0>;
7133 + compatible = "fixed-factor-clock";
7134 + clocks = <&apll_pcie_ck>;
7135 + clock-mult = <1>;
7136 + clock-div = <1>;
7137 +};
7138 +
7139 +apll_pcie_clkvcoldo_div: apll_pcie_clkvcoldo_div {
7140 + #clock-cells = <0>;
7141 + compatible = "fixed-factor-clock";
7142 + clocks = <&apll_pcie_ck>;
7143 + clock-mult = <1>;
7144 + clock-div = <1>;
7145 +};
7146 +
7147 +apll_pcie_m2_ck: apll_pcie_m2_ck@4a008224 {
7148 + #clock-cells = <0>;
7149 + compatible = "fixed-factor-clock";
7150 + clocks = <&apll_pcie_ck>;
7151 + clock-mult = <1>;
7152 + clock-div = <1>;
7153 +};
7154 +
7155 +sys_clk1_dclk_div: sys_clk1_dclk_div@4ae061c8 {
7156 + #clock-cells = <0>;
7157 + compatible = "divider-clock";
7158 + clocks = <&sys_clkin1>;
7159 + reg = <0x4ae061c8 0x4>;
7160 + bit-mask = <0x7>;
7161 + index-power-of-two;
7162 +};
7163 +
7164 +sys_clk2_dclk_div: sys_clk2_dclk_div@4ae061cc {
7165 + #clock-cells = <0>;
7166 + compatible = "divider-clock";
7167 + clocks = <&sys_clkin2>;
7168 + reg = <0x4ae061cc 0x4>;
7169 + bit-mask = <0x7>;
7170 + index-power-of-two;
7171 +};
7172 +
7173 +dpll_abe_m2_ck: dpll_abe_m2_ck@4a0051f0 {
7174 + #clock-cells = <0>;
7175 + compatible = "ti,divider-clock";
7176 + clocks = <&dpll_abe_ck>;
7177 + ti,autoidle-shift = <8>;
7178 + reg = <0x4a0051f0 0x4>;
7179 + bit-mask = <0x1f>;
7180 + index-starts-at-one;
7181 + ti,autoidle-low;
7182 +};
7183 +
7184 +per_abe_x1_dclk_div: per_abe_x1_dclk_div@4ae061bc {
7185 + #clock-cells = <0>;
7186 + compatible = "divider-clock";
7187 + clocks = <&dpll_abe_m2_ck>;
7188 + reg = <0x4ae061bc 0x4>;
7189 + bit-mask = <0x7>;
7190 + index-power-of-two;
7191 +};
7192 +
7193 +dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@4a0051f4 {
7194 + #clock-cells = <0>;
7195 + compatible = "ti,divider-clock";
7196 + clocks = <&dpll_abe_x2_ck>;
7197 + ti,autoidle-shift = <8>;
7198 + reg = <0x4a0051f4 0x4>;
7199 + bit-mask = <0x1f>;
7200 + index-starts-at-one;
7201 + ti,autoidle-low;
7202 +};
7203 +
7204 +dpll_core_ck: dpll_core_ck@4a005120 {
7205 + #clock-cells = <0>;
7206 + compatible = "ti,omap4-dpll-core-clock";
7207 + clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
7208 + reg = <0x4a005120 0x4>, <0x4a005124 0x4>, <0x4a005128 0x4>, <0x4a00512c 0x4>;
7209 + reg-names = "control", "idlest", "autoidle", "mult-div1";
7210 +};
7211 +
7212 +dpll_core_x2_ck: dpll_core_x2_ck {
7213 + #clock-cells = <0>;
7214 + compatible = "ti,omap4-dpll-x2-clock";
7215 + clocks = <&dpll_core_ck>;
7216 +};
7217 +
7218 +dpll_core_h12x2_ck: dpll_core_h12x2_ck@4a00513c {
7219 + #clock-cells = <0>;
7220 + compatible = "ti,divider-clock";
7221 + clocks = <&dpll_core_x2_ck>;
7222 + ti,autoidle-shift = <8>;
7223 + reg = <0x4a00513c 0x4>;
7224 + bit-mask = <0x3f>;
7225 + index-starts-at-one;
7226 + ti,autoidle-low;
7227 +};
7228 +
7229 +mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div {
7230 + #clock-cells = <0>;
7231 + compatible = "fixed-factor-clock";
7232 + clocks = <&dpll_core_h12x2_ck>;
7233 + clock-mult = <1>;
7234 + clock-div = <1>;
7235 +};
7236 +
7237 +dpll_mpu_ck: dpll_mpu_ck@4a005160 {
7238 + #clock-cells = <0>;
7239 + compatible = "ti,omap4-dpll-clock";
7240 + clocks = <&sys_clkin1>, <&mpu_dpll_hs_clk_div>;
7241 + reg = <0x4a005160 0x4>, <0x4a005164 0x4>, <0x4a005168 0x4>, <0x4a00516c 0x4>;
7242 + reg-names = "control", "idlest", "autoidle", "mult-div1";
7243 +};
7244 +
7245 +dpll_mpu_m2_ck: dpll_mpu_m2_ck@4a005170 {
7246 + #clock-cells = <0>;
7247 + compatible = "ti,divider-clock";
7248 + clocks = <&dpll_mpu_ck>;
7249 + ti,autoidle-shift = <8>;
7250 + reg = <0x4a005170 0x4>;
7251 + bit-mask = <0x1f>;
7252 + index-starts-at-one;
7253 + ti,autoidle-low;
7254 +};
7255 +
7256 +mpu_dclk_div: mpu_dclk_div {
7257 + #clock-cells = <0>;
7258 + compatible = "fixed-factor-clock";
7259 + clocks = <&dpll_mpu_m2_ck>;
7260 + clock-mult = <1>;
7261 + clock-div = <1>;
7262 +};
7263 +
7264 +dsp_dpll_hs_clk_div: dsp_dpll_hs_clk_div {
7265 + #clock-cells = <0>;
7266 + compatible = "fixed-factor-clock";
7267 + clocks = <&dpll_core_h12x2_ck>;
7268 + clock-mult = <1>;
7269 + clock-div = <1>;
7270 +};
7271 +
7272 +dpll_dsp_ck: dpll_dsp_ck@4a005234 {
7273 + #clock-cells = <0>;
7274 + compatible = "ti,omap4-dpll-clock";
7275 + clocks = <&sys_clkin1>, <&dsp_dpll_hs_clk_div>;
7276 + reg = <0x4a005234 0x4>, <0x4a005238 0x4>, <0x4a00523c 0x4>, <0x4a005240 0x4>;
7277 + reg-names = "control", "idlest", "autoidle", "mult-div1";
7278 +};
7279 +
7280 +dpll_dsp_m2_ck: dpll_dsp_m2_ck@4a005244 {
7281 + #clock-cells = <0>;
7282 + compatible = "ti,divider-clock";
7283 + clocks = <&dpll_dsp_ck>;
7284 + ti,autoidle-shift = <8>;
7285 + reg = <0x4a005244 0x4>;
7286 + bit-mask = <0x1f>;
7287 + index-starts-at-one;
7288 + ti,autoidle-low;
7289 +};
7290 +
7291 +dsp_gclk_div: dsp_gclk_div@4ae0618c {
7292 + #clock-cells = <0>;
7293 + compatible = "divider-clock";
7294 + clocks = <&dpll_dsp_m2_ck>;
7295 + reg = <0x4ae0618c 0x4>;
7296 + bit-mask = <0x7>;
7297 + index-power-of-two;
7298 +};
7299 +
7300 +iva_dpll_hs_clk_div: iva_dpll_hs_clk_div {
7301 + #clock-cells = <0>;
7302 + compatible = "fixed-factor-clock";
7303 + clocks = <&dpll_core_h12x2_ck>;
7304 + clock-mult = <1>;
7305 + clock-div = <1>;
7306 +};
7307 +
7308 +dpll_iva_ck: dpll_iva_ck@4a0051a0 {
7309 + #clock-cells = <0>;
7310 + compatible = "ti,omap4-dpll-clock";
7311 + clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>;
7312 + reg = <0x4a0051a0 0x4>, <0x4a0051a4 0x4>, <0x4a0051a8 0x4>, <0x4a0051ac 0x4>;
7313 + reg-names = "control", "idlest", "autoidle", "mult-div1";
7314 +};
7315 +
7316 +dpll_iva_m2_ck: dpll_iva_m2_ck@4a0051b0 {
7317 + #clock-cells = <0>;
7318 + compatible = "ti,divider-clock";
7319 + clocks = <&dpll_iva_ck>;
7320 + ti,autoidle-shift = <8>;
7321 + reg = <0x4a0051b0 0x4>;
7322 + bit-mask = <0x1f>;
7323 + index-starts-at-one;
7324 + ti,autoidle-low;
7325 +};
7326 +
7327 +iva_dclk: iva_dclk {
7328 + #clock-cells = <0>;
7329 + compatible = "fixed-factor-clock";
7330 + clocks = <&dpll_iva_m2_ck>;
7331 + clock-mult = <1>;
7332 + clock-div = <1>;
7333 +};
7334 +
7335 +dpll_gpu_ck: dpll_gpu_ck@4a0052d8 {
7336 + #clock-cells = <0>;
7337 + compatible = "ti,omap4-dpll-clock";
7338 + clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
7339 + reg = <0x4a0052d8 0x4>, <0x4a0052dc 0x4>, <0x4a0052e0 0x4>, <0x4a0052e4 0x4>;
7340 + reg-names = "control", "idlest", "autoidle", "mult-div1";
7341 +};
7342 +
7343 +dpll_gpu_m2_ck: dpll_gpu_m2_ck@4a0052e8 {
7344 + #clock-cells = <0>;
7345 + compatible = "ti,divider-clock";
7346 + clocks = <&dpll_gpu_ck>;
7347 + ti,autoidle-shift = <8>;
7348 + reg = <0x4a0052e8 0x4>;
7349 + bit-mask = <0x1f>;
7350 + index-starts-at-one;
7351 + ti,autoidle-low;
7352 +};
7353 +
7354 +gpu_dclk: gpu_dclk@4ae061a0 {
7355 + #clock-cells = <0>;
7356 + compatible = "divider-clock";
7357 + clocks = <&dpll_gpu_m2_ck>;
7358 + reg = <0x4ae061a0 0x4>;
7359 + bit-mask = <0x7>;
7360 + index-power-of-two;
7361 +};
7362 +
7363 +dpll_core_m2_ck: dpll_core_m2_ck@4a005130 {
7364 + #clock-cells = <0>;
7365 + compatible = "ti,divider-clock";
7366 + clocks = <&dpll_core_ck>;
7367 + ti,autoidle-shift = <8>;
7368 + reg = <0x4a005130 0x4>;
7369 + bit-mask = <0x1f>;
7370 + index-starts-at-one;
7371 + ti,autoidle-low;
7372 +};
7373 +
7374 +core_dpll_out_dclk_div: core_dpll_out_dclk_div {
7375 + #clock-cells = <0>;
7376 + compatible = "fixed-factor-clock";
7377 + clocks = <&dpll_core_m2_ck>;
7378 + clock-mult = <1>;
7379 + clock-div = <1>;
7380 +};
7381 +
7382 +dpll_ddr_ck: dpll_ddr_ck@4a005210 {
7383 + #clock-cells = <0>;
7384 + compatible = "ti,omap4-dpll-clock";
7385 + clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
7386 + reg = <0x4a005210 0x4>, <0x4a005214 0x4>, <0x4a005218 0x4>, <0x4a00521c 0x4>;
7387 + reg-names = "control", "idlest", "autoidle", "mult-div1";
7388 +};
7389 +
7390 +dpll_ddr_m2_ck: dpll_ddr_m2_ck@4a005220 {
7391 + #clock-cells = <0>;
7392 + compatible = "ti,divider-clock";
7393 + clocks = <&dpll_ddr_ck>;
7394 + ti,autoidle-shift = <8>;
7395 + reg = <0x4a005220 0x4>;
7396 + bit-mask = <0x1f>;
7397 + index-starts-at-one;
7398 + ti,autoidle-low;
7399 +};
7400 +
7401 +emif_phy_dclk_div: emif_phy_dclk_div@4ae06190 {
7402 + #clock-cells = <0>;
7403 + compatible = "divider-clock";
7404 + clocks = <&dpll_ddr_m2_ck>;
7405 + reg = <0x4ae06190 0x4>;
7406 + bit-mask = <0x7>;
7407 + index-power-of-two;
7408 +};
7409 +
7410 +dpll_gmac_ck: dpll_gmac_ck@4a0052a8 {
7411 + #clock-cells = <0>;
7412 + compatible = "ti,omap4-dpll-clock";
7413 + clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
7414 + reg = <0x4a0052a8 0x4>, <0x4a0052ac 0x4>, <0x4a0052b0 0x4>, <0x4a0052b4 0x4>;
7415 + reg-names = "control", "idlest", "autoidle", "mult-div1";
7416 +};
7417 +
7418 +dpll_gmac_m2_ck: dpll_gmac_m2_ck@4a0052b8 {
7419 + #clock-cells = <0>;
7420 + compatible = "ti,divider-clock";
7421 + clocks = <&dpll_gmac_ck>;
7422 + ti,autoidle-shift = <8>;
7423 + reg = <0x4a0052b8 0x4>;
7424 + bit-mask = <0x1f>;
7425 + index-starts-at-one;
7426 + ti,autoidle-low;
7427 +};
7428 +
7429 +gmac_250m_dclk_div: gmac_250m_dclk_div@4ae0619c {
7430 + #clock-cells = <0>;
7431 + compatible = "divider-clock";
7432 + clocks = <&dpll_gmac_m2_ck>;
7433 + reg = <0x4ae0619c 0x4>;
7434 + bit-mask = <0x7>;
7435 + index-power-of-two;
7436 +};
7437 +
7438 +video2_dclk_div: video2_dclk_div {
7439 + #clock-cells = <0>;
7440 + compatible = "fixed-factor-clock";
7441 + clocks = <&video2_m2_clkin_ck>;
7442 + clock-mult = <1>;
7443 + clock-div = <1>;
7444 +};
7445 +
7446 +video1_dclk_div: video1_dclk_div {
7447 + #clock-cells = <0>;
7448 + compatible = "fixed-factor-clock";
7449 + clocks = <&video1_m2_clkin_ck>;
7450 + clock-mult = <1>;
7451 + clock-div = <1>;
7452 +};
7453 +
7454 +hdmi_dclk_div: hdmi_dclk_div {
7455 + #clock-cells = <0>;
7456 + compatible = "fixed-factor-clock";
7457 + clocks = <&hdmi_clkin_ck>;
7458 + clock-mult = <1>;
7459 + clock-div = <1>;
7460 +};
7461 +
7462 +per_dpll_hs_clk_div: per_dpll_hs_clk_div {
7463 + #clock-cells = <0>;
7464 + compatible = "fixed-factor-clock";
7465 + clocks = <&dpll_abe_m3x2_ck>;
7466 + clock-mult = <1>;
7467 + clock-div = <2>;
7468 +};
7469 +
7470 +dpll_per_ck: dpll_per_ck@4a008140 {
7471 + #clock-cells = <0>;
7472 + compatible = "ti,omap4-dpll-clock";
7473 + clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>;
7474 + reg = <0x4a008140 0x4>, <0x4a008144 0x4>, <0x4a008148 0x4>, <0x4a00814c 0x4>;
7475 + reg-names = "control", "idlest", "autoidle", "mult-div1";
7476 +};
7477 +
7478 +dpll_per_m2_ck: dpll_per_m2_ck@4a008150 {
7479 + #clock-cells = <0>;
7480 + compatible = "ti,divider-clock";
7481 + clocks = <&dpll_per_ck>;
7482 + ti,autoidle-shift = <8>;
7483 + reg = <0x4a008150 0x4>;
7484 + bit-mask = <0x1f>;
7485 + index-starts-at-one;
7486 + ti,autoidle-low;
7487 +};
7488 +
7489 +func_96m_aon_dclk_div: func_96m_aon_dclk_div {
7490 + #clock-cells = <0>;
7491 + compatible = "fixed-factor-clock";
7492 + clocks = <&dpll_per_m2_ck>;
7493 + clock-mult = <1>;
7494 + clock-div = <1>;
7495 +};
7496 +
7497 +usb_dpll_hs_clk_div: usb_dpll_hs_clk_div {
7498 + #clock-cells = <0>;
7499 + compatible = "fixed-factor-clock";
7500 + clocks = <&dpll_abe_m3x2_ck>;
7501 + clock-mult = <1>;
7502 + clock-div = <3>;
7503 +};
7504 +
7505 +dpll_usb_ck: dpll_usb_ck@4a008180 {
7506 + #clock-cells = <0>;
7507 + compatible = "ti,omap4-dpll-j-type-clock";
7508 + clocks = <&sys_clkin1>, <&usb_dpll_hs_clk_div>;
7509 + reg = <0x4a008180 0x4>, <0x4a008184 0x4>, <0x4a008188 0x4>, <0x4a00818c 0x4>;
7510 + reg-names = "control", "idlest", "autoidle", "mult-div1";
7511 +};
7512 +
7513 +dpll_usb_m2_ck: dpll_usb_m2_ck@4a008190 {
7514 + #clock-cells = <0>;
7515 + compatible = "ti,divider-clock";
7516 + clocks = <&dpll_usb_ck>;
7517 + ti,autoidle-shift = <8>;
7518 + reg = <0x4a008190 0x4>;
7519 + bit-mask = <0x7f>;
7520 + index-starts-at-one;
7521 + ti,autoidle-low;
7522 +};
7523 +
7524 +l3init_480m_dclk_div: l3init_480m_dclk_div@4ae061ac {
7525 + #clock-cells = <0>;
7526 + compatible = "divider-clock";
7527 + clocks = <&dpll_usb_m2_ck>;
7528 + reg = <0x4ae061ac 0x4>;
7529 + bit-mask = <0x7>;
7530 + index-power-of-two;
7531 +};
7532 +
7533 +usb_otg_dclk_div: usb_otg_dclk_div@4ae06184 {
7534 + #clock-cells = <0>;
7535 + compatible = "divider-clock";
7536 + clocks = <&usb_otg_clkin_ck>;
7537 + reg = <0x4ae06184 0x4>;
7538 + bit-mask = <0x7>;
7539 + index-power-of-two;
7540 +};
7541 +
7542 +sata_dclk_div: sata_dclk_div@4ae061c0 {
7543 + #clock-cells = <0>;
7544 + compatible = "divider-clock";
7545 + clocks = <&sys_clkin1>;
7546 + reg = <0x4ae061c0 0x4>;
7547 + bit-mask = <0x7>;
7548 + index-power-of-two;
7549 +};
7550 +
7551 +dpll_pcie_ref_m2_ck: dpll_pcie_ref_m2_ck@4a008210 {
7552 + #clock-cells = <0>;
7553 + compatible = "ti,divider-clock";
7554 + clocks = <&dpll_pcie_ref_ck>;
7555 + ti,autoidle-shift = <8>;
7556 + reg = <0x4a008210 0x4>;
7557 + bit-mask = <0x7f>;
7558 + index-starts-at-one;
7559 + ti,autoidle-low;
7560 +};
7561 +
7562 +pcie2_dclk_div: pcie2_dclk_div@4ae061b8 {
7563 + #clock-cells = <0>;
7564 + compatible = "divider-clock";
7565 + clocks = <&dpll_pcie_ref_m2_ck>;
7566 + reg = <0x4ae061b8 0x4>;
7567 + bit-mask = <0x7>;
7568 + index-power-of-two;
7569 +};
7570 +
7571 +pcie_dclk_div: pcie_dclk_div@4ae061b4 {
7572 + #clock-cells = <0>;
7573 + compatible = "divider-clock";
7574 + clocks = <&apll_pcie_m2_ck>;
7575 + reg = <0x4ae061b4 0x4>;
7576 + bit-mask = <0x7>;
7577 + index-power-of-two;
7578 +};
7579 +
7580 +emu_dclk_div: emu_dclk_div@4ae06194 {
7581 + #clock-cells = <0>;
7582 + compatible = "divider-clock";
7583 + clocks = <&sys_clkin1>;
7584 + reg = <0x4ae06194 0x4>;
7585 + bit-mask = <0x7>;
7586 + index-power-of-two;
7587 +};
7588 +
7589 +secure_32k_dclk_div: secure_32k_dclk_div@4ae061c4 {
7590 + #clock-cells = <0>;
7591 + compatible = "divider-clock";
7592 + clocks = <&secure_32k_clk_src_ck>;
7593 + reg = <0x4ae061c4 0x4>;
7594 + bit-mask = <0x7>;
7595 + index-power-of-two;
7596 +};
7597 +
7598 +eve_dpll_hs_clk_div: eve_dpll_hs_clk_div {
7599 + #clock-cells = <0>;
7600 + compatible = "fixed-factor-clock";
7601 + clocks = <&dpll_core_h12x2_ck>;
7602 + clock-mult = <1>;
7603 + clock-div = <1>;
7604 +};
7605 +
7606 +dpll_eve_ck: dpll_eve_ck@4a005284 {
7607 + #clock-cells = <0>;
7608 + compatible = "ti,omap4-dpll-clock";
7609 + clocks = <&sys_clkin1>, <&eve_dpll_hs_clk_div>;
7610 + reg = <0x4a005284 0x4>, <0x4a005288 0x4>, <0x4a00528c 0x4>, <0x4a005290 0x4>;
7611 + reg-names = "control", "idlest", "autoidle", "mult-div1";
7612 +};
7613 +
7614 +dpll_eve_m2_ck: dpll_eve_m2_ck@4a005294 {
7615 + #clock-cells = <0>;
7616 + compatible = "ti,divider-clock";
7617 + clocks = <&dpll_eve_ck>;
7618 + ti,autoidle-shift = <8>;
7619 + reg = <0x4a005294 0x4>;
7620 + bit-mask = <0x1f>;
7621 + index-starts-at-one;
7622 + ti,autoidle-low;
7623 +};
7624 +
7625 +eve_dclk_div: eve_dclk_div {
7626 + #clock-cells = <0>;
7627 + compatible = "fixed-factor-clock";
7628 + clocks = <&dpll_eve_m2_ck>;
7629 + clock-mult = <1>;
7630 + clock-div = <1>;
7631 +};
7632 +
7633 +clkoutmux0_clk_mux: clkoutmux0_clk_mux@4ae06158 {
7634 + #clock-cells = <0>;
7635 + compatible = "mux-clock";
7636 + clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
7637 + reg = <0x4ae06158 0x4>;
7638 + bit-mask = <0x1f>;
7639 +};
7640 +
7641 +clkoutmux1_clk_mux: clkoutmux1_clk_mux@4ae0615c {
7642 + #clock-cells = <0>;
7643 + compatible = "mux-clock";
7644 + clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
7645 + reg = <0x4ae0615c 0x4>;
7646 + bit-mask = <0x1f>;
7647 +};
7648 +
7649 +clkoutmux2_clk_mux: clkoutmux2_clk_mux@4ae06160 {
7650 + #clock-cells = <0>;
7651 + compatible = "mux-clock";
7652 + clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
7653 + reg = <0x4ae06160 0x4>;
7654 + bit-mask = <0x1f>;
7655 +};
7656 +
7657 +custefuse_sys_gfclk_div: custefuse_sys_gfclk_div {
7658 + #clock-cells = <0>;
7659 + compatible = "fixed-factor-clock";
7660 + clocks = <&sys_clkin1>;
7661 + clock-mult = <1>;
7662 + clock-div = <2>;
7663 +};
7664 +
7665 +dpll_core_h13x2_ck: dpll_core_h13x2_ck@4a005140 {
7666 + #clock-cells = <0>;
7667 + compatible = "ti,divider-clock";
7668 + clocks = <&dpll_core_x2_ck>;
7669 + ti,autoidle-shift = <8>;
7670 + reg = <0x4a005140 0x4>;
7671 + bit-mask = <0x3f>;
7672 + index-starts-at-one;
7673 + ti,autoidle-low;
7674 +};
7675 +
7676 +dpll_core_h14x2_ck: dpll_core_h14x2_ck@4a005144 {
7677 + #clock-cells = <0>;
7678 + compatible = "ti,divider-clock";
7679 + clocks = <&dpll_core_x2_ck>;
7680 + ti,autoidle-shift = <8>;
7681 + reg = <0x4a005144 0x4>;
7682 + bit-mask = <0x3f>;
7683 + index-starts-at-one;
7684 + ti,autoidle-low;
7685 +};
7686 +
7687 +dpll_core_h22x2_ck: dpll_core_h22x2_ck@4a005154 {
7688 + #clock-cells = <0>;
7689 + compatible = "ti,divider-clock";
7690 + clocks = <&dpll_core_x2_ck>;
7691 + ti,autoidle-shift = <8>;
7692 + reg = <0x4a005154 0x4>;
7693 + bit-mask = <0x3f>;
7694 + index-starts-at-one;
7695 + ti,autoidle-low;
7696 +};
7697 +
7698 +dpll_core_h23x2_ck: dpll_core_h23x2_ck@4a005158 {
7699 + #clock-cells = <0>;
7700 + compatible = "ti,divider-clock";
7701 + clocks = <&dpll_core_x2_ck>;
7702 + ti,autoidle-shift = <8>;
7703 + reg = <0x4a005158 0x4>;
7704 + bit-mask = <0x3f>;
7705 + index-starts-at-one;
7706 + ti,autoidle-low;
7707 +};
7708 +
7709 +dpll_core_h24x2_ck: dpll_core_h24x2_ck@4a00515c {
7710 + #clock-cells = <0>;
7711 + compatible = "ti,divider-clock";
7712 + clocks = <&dpll_core_x2_ck>;
7713 + ti,autoidle-shift = <8>;
7714 + reg = <0x4a00515c 0x4>;
7715 + bit-mask = <0x3f>;
7716 + index-starts-at-one;
7717 + ti,autoidle-low;
7718 +};
7719 +
7720 +dpll_ddr_x2_ck: dpll_ddr_x2_ck {
7721 + #clock-cells = <0>;
7722 + compatible = "ti,omap4-dpll-x2-clock";
7723 + clocks = <&dpll_ddr_ck>;
7724 +};
7725 +
7726 +dpll_ddr_h11x2_ck: dpll_ddr_h11x2_ck@4a005228 {
7727 + #clock-cells = <0>;
7728 + compatible = "ti,divider-clock";
7729 + clocks = <&dpll_ddr_x2_ck>;
7730 + ti,autoidle-shift = <8>;
7731 + reg = <0x4a005228 0x4>;
7732 + bit-mask = <0x3f>;
7733 + index-starts-at-one;
7734 + ti,autoidle-low;
7735 +};
7736 +
7737 +dpll_dsp_x2_ck: dpll_dsp_x2_ck {
7738 + #clock-cells = <0>;
7739 + compatible = "ti,omap4-dpll-x2-clock";
7740 + clocks = <&dpll_dsp_ck>;
7741 +};
7742 +
7743 +dpll_dsp_m3x2_ck: dpll_dsp_m3x2_ck@4a005248 {
7744 + #clock-cells = <0>;
7745 + compatible = "ti,divider-clock";
7746 + clocks = <&dpll_dsp_x2_ck>;
7747 + ti,autoidle-shift = <8>;
7748 + reg = <0x4a005248 0x4>;
7749 + bit-mask = <0x1f>;
7750 + index-starts-at-one;
7751 + ti,autoidle-low;
7752 +};
7753 +
7754 +dpll_gmac_x2_ck: dpll_gmac_x2_ck {
7755 + #clock-cells = <0>;
7756 + compatible = "ti,omap4-dpll-x2-clock";
7757 + clocks = <&dpll_gmac_ck>;
7758 +};
7759 +
7760 +dpll_gmac_h11x2_ck: dpll_gmac_h11x2_ck@4a0052c0 {
7761 + #clock-cells = <0>;
7762 + compatible = "ti,divider-clock";
7763 + clocks = <&dpll_gmac_x2_ck>;
7764 + ti,autoidle-shift = <8>;
7765 + reg = <0x4a0052c0 0x4>;
7766 + bit-mask = <0x3f>;
7767 + index-starts-at-one;
7768 + ti,autoidle-low;
7769 +};
7770 +
7771 +dpll_gmac_h12x2_ck: dpll_gmac_h12x2_ck@4a0052c4 {
7772 + #clock-cells = <0>;
7773 + compatible = "ti,divider-clock";
7774 + clocks = <&dpll_gmac_x2_ck>;
7775 + ti,autoidle-shift = <8>;
7776 + reg = <0x4a0052c4 0x4>;
7777 + bit-mask = <0x3f>;
7778 + index-starts-at-one;
7779 + ti,autoidle-low;
7780 +};
7781 +
7782 +dpll_gmac_h13x2_ck: dpll_gmac_h13x2_ck@4a0052c8 {
7783 + #clock-cells = <0>;
7784 + compatible = "ti,divider-clock";
7785 + clocks = <&dpll_gmac_x2_ck>;
7786 + ti,autoidle-shift = <8>;
7787 + reg = <0x4a0052c8 0x4>;
7788 + bit-mask = <0x3f>;
7789 + index-starts-at-one;
7790 + ti,autoidle-low;
7791 +};
7792 +
7793 +dpll_gmac_m3x2_ck: dpll_gmac_m3x2_ck@4a0052bc {
7794 + #clock-cells = <0>;
7795 + compatible = "ti,divider-clock";
7796 + clocks = <&dpll_gmac_x2_ck>;
7797 + ti,autoidle-shift = <8>;
7798 + reg = <0x4a0052bc 0x4>;
7799 + bit-mask = <0x1f>;
7800 + index-starts-at-one;
7801 + ti,autoidle-low;
7802 +};
7803 +
7804 +dpll_per_x2_ck: dpll_per_x2_ck {
7805 + #clock-cells = <0>;
7806 + compatible = "ti,omap4-dpll-x2-clock";
7807 + clocks = <&dpll_per_ck>;
7808 +};
7809 +
7810 +dpll_per_h11x2_ck: dpll_per_h11x2_ck@4a008158 {
7811 + #clock-cells = <0>;
7812 + compatible = "ti,divider-clock";
7813 + clocks = <&dpll_per_x2_ck>;
7814 + ti,autoidle-shift = <8>;
7815 + reg = <0x4a008158 0x4>;
7816 + bit-mask = <0x3f>;
7817 + index-starts-at-one;
7818 + ti,autoidle-low;
7819 +};
7820 +
7821 +dpll_per_h12x2_ck: dpll_per_h12x2_ck@4a00815c {
7822 + #clock-cells = <0>;
7823 + compatible = "ti,divider-clock";
7824 + clocks = <&dpll_per_x2_ck>;
7825 + ti,autoidle-shift = <8>;
7826 + reg = <0x4a00815c 0x4>;
7827 + bit-mask = <0x3f>;
7828 + index-starts-at-one;
7829 + ti,autoidle-low;
7830 +};
7831 +
7832 +dpll_per_h13x2_ck: dpll_per_h13x2_ck@4a008160 {
7833 + #clock-cells = <0>;
7834 + compatible = "ti,divider-clock";
7835 + clocks = <&dpll_per_x2_ck>;
7836 + ti,autoidle-shift = <8>;
7837 + reg = <0x4a008160 0x4>;
7838 + bit-mask = <0x3f>;
7839 + index-starts-at-one;
7840 + ti,autoidle-low;
7841 +};
7842 +
7843 +dpll_per_h14x2_ck: dpll_per_h14x2_ck@4a008164 {
7844 + #clock-cells = <0>;
7845 + compatible = "ti,divider-clock";
7846 + clocks = <&dpll_per_x2_ck>;
7847 + ti,autoidle-shift = <8>;
7848 + reg = <0x4a008164 0x4>;
7849 + bit-mask = <0x3f>;
7850 + index-starts-at-one;
7851 + ti,autoidle-low;
7852 +};
7853 +
7854 +dpll_per_m2x2_ck: dpll_per_m2x2_ck@4a008150 {
7855 + #clock-cells = <0>;
7856 + compatible = "ti,divider-clock";
7857 + clocks = <&dpll_per_x2_ck>;
7858 + ti,autoidle-shift = <8>;
7859 + reg = <0x4a008150 0x4>;
7860 + bit-mask = <0x1f>;
7861 + index-starts-at-one;
7862 + ti,autoidle-low;
7863 +};
7864 +
7865 +dpll_usb_clkdcoldo: dpll_usb_clkdcoldo {
7866 + #clock-cells = <0>;
7867 + compatible = "fixed-factor-clock";
7868 + clocks = <&dpll_usb_ck>;
7869 + clock-mult = <1>;
7870 + clock-div = <1>;
7871 +};
7872 +
7873 +eve_clk: eve_clk@4ae06180 {
7874 + #clock-cells = <0>;
7875 + compatible = "mux-clock";
7876 + clocks = <&dpll_eve_m2_ck>, <&dpll_dsp_m3x2_ck>;
7877 + reg = <0x4ae06180 0x4>;
7878 + bit-mask = <0x1>;
7879 +};
7880 +
7881 +func_128m_clk: func_128m_clk {
7882 + #clock-cells = <0>;
7883 + compatible = "fixed-factor-clock";
7884 + clocks = <&dpll_per_h11x2_ck>;
7885 + clock-mult = <1>;
7886 + clock-div = <2>;
7887 +};
7888 +
7889 +func_12m_fclk: func_12m_fclk {
7890 + #clock-cells = <0>;
7891 + compatible = "fixed-factor-clock";
7892 + clocks = <&dpll_per_m2x2_ck>;
7893 + clock-mult = <1>;
7894 + clock-div = <16>;
7895 +};
7896 +
7897 +func_24m_clk: func_24m_clk {
7898 + #clock-cells = <0>;
7899 + compatible = "fixed-factor-clock";
7900 + clocks = <&dpll_per_m2_ck>;
7901 + clock-mult = <1>;
7902 + clock-div = <4>;
7903 +};
7904 +
7905 +func_48m_fclk: func_48m_fclk {
7906 + #clock-cells = <0>;
7907 + compatible = "fixed-factor-clock";
7908 + clocks = <&dpll_per_m2x2_ck>;
7909 + clock-mult = <1>;
7910 + clock-div = <4>;
7911 +};
7912 +
7913 +func_96m_fclk: func_96m_fclk {
7914 + #clock-cells = <0>;
7915 + compatible = "fixed-factor-clock";
7916 + clocks = <&dpll_per_m2x2_ck>;
7917 + clock-mult = <1>;
7918 + clock-div = <2>;
7919 +};
7920 +
7921 +gmii_m_clk_div: gmii_m_clk_div {
7922 + #clock-cells = <0>;
7923 + compatible = "fixed-factor-clock";
7924 + clocks = <&dpll_gmac_h11x2_ck>;
7925 + clock-mult = <1>;
7926 + clock-div = <2>;
7927 +};
7928 +
7929 +hdmi_clk2_div: hdmi_clk2_div {
7930 + #clock-cells = <0>;
7931 + compatible = "fixed-factor-clock";
7932 + clocks = <&hdmi_clkin_ck>;
7933 + clock-mult = <1>;
7934 + clock-div = <1>;
7935 +};
7936 +
7937 +hdmi_div_clk: hdmi_div_clk {
7938 + #clock-cells = <0>;
7939 + compatible = "fixed-factor-clock";
7940 + clocks = <&hdmi_clkin_ck>;
7941 + clock-mult = <1>;
7942 + clock-div = <1>;
7943 +};
7944 +
7945 +hdmi_dpll_clk_mux: hdmi_dpll_clk_mux@4ae061a4 {
7946 + #clock-cells = <0>;
7947 + compatible = "mux-clock";
7948 + clocks = <&sys_clkin1>, <&sys_clkin2>;
7949 + reg = <0x4ae061a4 0x4>;
7950 + bit-mask = <0x7>;
7951 +};
7952 +
7953 +l3_iclk_div: l3_iclk_div {
7954 + #clock-cells = <0>;
7955 + compatible = "fixed-factor-clock";
7956 + clocks = <&dpll_core_h12x2_ck>;
7957 + clock-mult = <1>;
7958 + clock-div = <1>;
7959 +};
7960 +
7961 +l3init_60m_fclk: l3init_60m_fclk@4a008104 {
7962 + #clock-cells = <0>;
7963 + compatible = "divider-clock";
7964 + clocks = <&dpll_usb_m2_ck>;
7965 + reg = <0x4a008104 0x4>;
7966 + table = < 1 0 >, < 8 1 >;
7967 + bit-mask = <0x1>;
7968 +};
7969 +
7970 +l3init_960m_gfclk: l3init_960m_gfclk@4a0086c0 {
7971 + #clock-cells = <0>;
7972 + compatible = "gate-clock";
7973 + clocks = <&dpll_usb_clkdcoldo>;
7974 + bit-shift = <8>;
7975 + reg = <0x4a0086c0 0x4>;
7976 +};
7977 +
7978 +l4_root_clk_div: l4_root_clk_div {
7979 + #clock-cells = <0>;
7980 + compatible = "fixed-factor-clock";
7981 + clocks = <&l3_iclk_div>;
7982 + clock-mult = <1>;
7983 + clock-div = <1>;
7984 +};
7985 +
7986 +mlb_clk: mlb_clk@4ae06134 {
7987 + #clock-cells = <0>;
7988 + compatible = "divider-clock";
7989 + clocks = <&mlb_clkin_ck>;
7990 + reg = <0x4ae06134 0x4>;
7991 + bit-mask = <0x7>;
7992 + index-power-of-two;
7993 +};
7994 +
7995 +mlbp_clk: mlbp_clk@4ae06130 {
7996 + #clock-cells = <0>;
7997 + compatible = "divider-clock";
7998 + clocks = <&mlbp_clkin_ck>;
7999 + reg = <0x4ae06130 0x4>;
8000 + bit-mask = <0x7>;
8001 + index-power-of-two;
8002 +};
8003 +
8004 +per_abe_x1_gfclk2_div: per_abe_x1_gfclk2_div@4ae06138 {
8005 + #clock-cells = <0>;
8006 + compatible = "divider-clock";
8007 + clocks = <&dpll_abe_m2_ck>;
8008 + reg = <0x4ae06138 0x4>;
8009 + bit-mask = <0x7>;
8010 + index-power-of-two;
8011 +};
8012 +
8013 +timer_sys_clk_div: timer_sys_clk_div@4ae06144 {
8014 + #clock-cells = <0>;
8015 + compatible = "divider-clock";
8016 + clocks = <&sys_clkin1>;
8017 + reg = <0x4ae06144 0x4>;
8018 + bit-mask = <0x1>;
8019 +};
8020 +
8021 +video1_clk2_div: video1_clk2_div {
8022 + #clock-cells = <0>;
8023 + compatible = "fixed-factor-clock";
8024 + clocks = <&video1_clkin_ck>;
8025 + clock-mult = <1>;
8026 + clock-div = <1>;
8027 +};
8028 +
8029 +video1_div_clk: video1_div_clk {
8030 + #clock-cells = <0>;
8031 + compatible = "fixed-factor-clock";
8032 + clocks = <&video1_clkin_ck>;
8033 + clock-mult = <1>;
8034 + clock-div = <1>;
8035 +};
8036 +
8037 +video1_dpll_clk_mux: video1_dpll_clk_mux@4ae061d0 {
8038 + #clock-cells = <0>;
8039 + compatible = "mux-clock";
8040 + clocks = <&sys_clkin1>, <&sys_clkin2>;
8041 + reg = <0x4ae061d0 0x4>;
8042 + bit-mask = <0x7>;
8043 +};
8044 +
8045 +video2_clk2_div: video2_clk2_div {
8046 + #clock-cells = <0>;
8047 + compatible = "fixed-factor-clock";
8048 + clocks = <&video2_clkin_ck>;
8049 + clock-mult = <1>;
8050 + clock-div = <1>;
8051 +};
8052 +
8053 +video2_div_clk: video2_div_clk {
8054 + #clock-cells = <0>;
8055 + compatible = "fixed-factor-clock";
8056 + clocks = <&video2_clkin_ck>;
8057 + clock-mult = <1>;
8058 + clock-div = <1>;
8059 +};
8060 +
8061 +video2_dpll_clk_mux: video2_dpll_clk_mux@4ae061d4 {
8062 + #clock-cells = <0>;
8063 + compatible = "mux-clock";
8064 + clocks = <&sys_clkin1>, <&sys_clkin2>;
8065 + reg = <0x4ae061d4 0x4>;
8066 + bit-mask = <0x7>;
8067 +};
8068 +
8069 +wkupaon_iclk_mux: wkupaon_iclk_mux@4ae06108 {
8070 + #clock-cells = <0>;
8071 + compatible = "mux-clock";
8072 + clocks = <&sys_clkin1>, <&abe_lp_clk_div>;
8073 + reg = <0x4ae06108 0x4>;
8074 + bit-mask = <0x1>;
8075 +};
8076 +
8077 +dss_32khz_clk: dss_32khz_clk@4a009120 {
8078 + #clock-cells = <0>;
8079 + compatible = "gate-clock";
8080 + clocks = <&sys_32k_ck>;
8081 + bit-shift = <11>;
8082 + reg = <0x4a009120 0x4>;
8083 +};
8084 +
8085 +dss_48mhz_clk: dss_48mhz_clk@4a009120 {
8086 + #clock-cells = <0>;
8087 + compatible = "gate-clock";
8088 + clocks = <&func_48m_fclk>;
8089 + bit-shift = <9>;
8090 + reg = <0x4a009120 0x4>;
8091 +};
8092 +
8093 +dss_dss_clk: dss_dss_clk@4a009120 {
8094 + #clock-cells = <0>;
8095 + compatible = "gate-clock";
8096 + clocks = <&dpll_per_h12x2_ck>;
8097 + bit-shift = <8>;
8098 + reg = <0x4a009120 0x4>;
8099 +};
8100 +
8101 +dss_hdmi_clk: dss_hdmi_clk@4a009120 {
8102 + #clock-cells = <0>;
8103 + compatible = "gate-clock";
8104 + clocks = <&hdmi_dpll_clk_mux>;
8105 + bit-shift = <10>;
8106 + reg = <0x4a009120 0x4>;
8107 +};
8108 +
8109 +dss_video1_clk: dss_video1_clk@4a009120 {
8110 + #clock-cells = <0>;
8111 + compatible = "gate-clock";
8112 + clocks = <&video1_dpll_clk_mux>;
8113 + bit-shift = <12>;
8114 + reg = <0x4a009120 0x4>;
8115 +};
8116 +
8117 +dss_video2_clk: dss_video2_clk@4a009120 {
8118 + #clock-cells = <0>;
8119 + compatible = "gate-clock";
8120 + clocks = <&video2_dpll_clk_mux>;
8121 + bit-shift = <13>;
8122 + reg = <0x4a009120 0x4>;
8123 +};
8124 +
8125 +dss_deshdcp_clk: dss_deshdcp_clk@4a002558 {
8126 + compatible = "gate-clock";
8127 + clocks = <&l3_iclk_div>;
8128 + #clock-cells = <0>;
8129 + reg = <0x4a002558 0x1>;
8130 + bit-shift = <0>;
8131 +};
8132 +
8133 +gpio1_dbclk: gpio1_dbclk@4ae07838 {
8134 + #clock-cells = <0>;
8135 + compatible = "gate-clock";
8136 + clocks = <&sys_32k_ck>;
8137 + bit-shift = <8>;
8138 + reg = <0x4ae07838 0x4>;
8139 +};
8140 +
8141 +gpio2_dbclk: gpio2_dbclk@4a009760 {
8142 + #clock-cells = <0>;
8143 + compatible = "gate-clock";
8144 + clocks = <&sys_32k_ck>;
8145 + bit-shift = <8>;
8146 + reg = <0x4a009760 0x4>;
8147 +};
8148 +
8149 +gpio3_dbclk: gpio3_dbclk@4a009768 {
8150 + #clock-cells = <0>;
8151 + compatible = "gate-clock";
8152 + clocks = <&sys_32k_ck>;
8153 + bit-shift = <8>;
8154 + reg = <0x4a009768 0x4>;
8155 +};
8156 +
8157 +gpio4_dbclk: gpio4_dbclk@4a009770 {
8158 + #clock-cells = <0>;
8159 + compatible = "gate-clock";
8160 + clocks = <&sys_32k_ck>;
8161 + bit-shift = <8>;
8162 + reg = <0x4a009770 0x4>;
8163 +};
8164 +
8165 +gpio5_dbclk: gpio5_dbclk@4a009778 {
8166 + #clock-cells = <0>;
8167 + compatible = "gate-clock";
8168 + clocks = <&sys_32k_ck>;
8169 + bit-shift = <8>;
8170 + reg = <0x4a009778 0x4>;
8171 +};
8172 +
8173 +gpio6_dbclk: gpio6_dbclk@4a009780 {
8174 + #clock-cells = <0>;
8175 + compatible = "gate-clock";
8176 + clocks = <&sys_32k_ck>;
8177 + bit-shift = <8>;
8178 + reg = <0x4a009780 0x4>;
8179 +};
8180 +
8181 +gpio7_dbclk: gpio7_dbclk@4a009810 {
8182 + #clock-cells = <0>;
8183 + compatible = "gate-clock";
8184 + clocks = <&sys_32k_ck>;
8185 + bit-shift = <8>;
8186 + reg = <0x4a009810 0x4>;
8187 +};
8188 +
8189 +gpio8_dbclk: gpio8_dbclk@4a009818 {
8190 + #clock-cells = <0>;
8191 + compatible = "gate-clock";
8192 + clocks = <&sys_32k_ck>;
8193 + bit-shift = <8>;
8194 + reg = <0x4a009818 0x4>;
8195 +};
8196 +
8197 +mmc1_clk32k: mmc1_clk32k@4a009328 {
8198 + #clock-cells = <0>;
8199 + compatible = "gate-clock";
8200 + clocks = <&sys_32k_ck>;
8201 + bit-shift = <8>;
8202 + reg = <0x4a009328 0x4>;
8203 +};
8204 +
8205 +mmc2_clk32k: mmc2_clk32k@4a009330 {
8206 + #clock-cells = <0>;
8207 + compatible = "gate-clock";
8208 + clocks = <&sys_32k_ck>;
8209 + bit-shift = <8>;
8210 + reg = <0x4a009330 0x4>;
8211 +};
8212 +
8213 +mmc3_clk32k: mmc3_clk32k@4a009820 {
8214 + #clock-cells = <0>;
8215 + compatible = "gate-clock";
8216 + clocks = <&sys_32k_ck>;
8217 + bit-shift = <8>;
8218 + reg = <0x4a009820 0x4>;
8219 +};
8220 +
8221 +mmc4_clk32k: mmc4_clk32k@4a009828 {
8222 + #clock-cells = <0>;
8223 + compatible = "gate-clock";
8224 + clocks = <&sys_32k_ck>;
8225 + bit-shift = <8>;
8226 + reg = <0x4a009828 0x4>;
8227 +};
8228 +
8229 +sata_ref_clk: sata_ref_clk@4a009388 {
8230 + #clock-cells = <0>;
8231 + compatible = "gate-clock";
8232 + clocks = <&sys_clkin1>;
8233 + bit-shift = <8>;
8234 + reg = <0x4a009388 0x4>;
8235 +};
8236 +
8237 +usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m@4a0093f0 {
8238 + #clock-cells = <0>;
8239 + compatible = "gate-clock";
8240 + clocks = <&l3init_960m_gfclk>;
8241 + bit-shift = <8>;
8242 + reg = <0x4a0093f0 0x4>;
8243 +};
8244 +
8245 +usb_otg_ss2_refclk960m: usb_otg_ss2_refclk960m@4a009340 {
8246 + #clock-cells = <0>;
8247 + compatible = "gate-clock";
8248 + clocks = <&l3init_960m_gfclk>;
8249 + bit-shift = <8>;
8250 + reg = <0x4a009340 0x4>;
8251 +};
8252 +
8253 +usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k@4a008640 {
8254 + #clock-cells = <0>;
8255 + compatible = "gate-clock";
8256 + clocks = <&sys_32k_ck>;
8257 + bit-shift = <8>;
8258 + reg = <0x4a008640 0x4>;
8259 +};
8260 +
8261 +usb_phy2_always_on_clk32k: usb_phy2_always_on_clk32k@4a008688 {
8262 + #clock-cells = <0>;
8263 + compatible = "gate-clock";
8264 + clocks = <&sys_32k_ck>;
8265 + bit-shift = <8>;
8266 + reg = <0x4a008688 0x4>;
8267 +};
8268 +
8269 +usb_phy3_always_on_clk32k: usb_phy3_always_on_clk32k@4a008698 {
8270 + #clock-cells = <0>;
8271 + compatible = "gate-clock";
8272 + clocks = <&sys_32k_ck>;
8273 + bit-shift = <8>;
8274 + reg = <0x4a008698 0x4>;
8275 +};
8276 +
8277 +atl_dpll_clk_mux: atl_dpll_clk_mux@4a008c00 {
8278 + #clock-cells = <0>;
8279 + compatible = "mux-clock";
8280 + clocks = <&sys_32k_ck>, <&video1_clkin_ck>, <&video2_clkin_ck>, <&hdmi_clkin_ck>;
8281 + bit-shift = <24>;
8282 + reg = <0x4a008c00 0x4>;
8283 + bit-mask = <0x3>;
8284 +};
8285 +
8286 +atl_gfclk_mux: atl_gfclk_mux@4a008c00 {
8287 + #clock-cells = <0>;
8288 + compatible = "mux-clock";
8289 + clocks = <&l3_iclk_div>, <&dpll_abe_m2_ck>, <&atl_dpll_clk_mux>;
8290 + bit-shift = <26>;
8291 + reg = <0x4a008c00 0x4>;
8292 + bit-mask = <0x3>;
8293 +};
8294 +
8295 +dcan1_sys_clk_mux: dcan1_sys_clk_mux@4ae07888 {
8296 + #clock-cells = <0>;
8297 + compatible = "mux-clock";
8298 + clocks = <&sys_clkin1>, <&sys_clkin2>;
8299 + bit-shift = <24>;
8300 + reg = <0x4ae07888 0x4>;
8301 + bit-mask = <0x1>;
8302 +};
8303 +
8304 +gmac_gmii_ref_clk_div: gmac_gmii_ref_clk_div@4a0093d0 {
8305 + #clock-cells = <0>;
8306 + compatible = "divider-clock";
8307 + clocks = <&dpll_gmac_m2_ck>;
8308 + bit-shift = <24>;
8309 + reg = <0x4a0093d0 0x4>;
8310 + table = < 2 0 >;
8311 + bit-mask = <0x1>;
8312 +};
8313 +
8314 +gmac_rft_clk_mux: gmac_rft_clk_mux@4a0093d0 {
8315 + #clock-cells = <0>;
8316 + compatible = "mux-clock";
8317 + clocks = <&video1_clkin_ck>, <&video2_clkin_ck>, <&dpll_abe_m2_ck>, <&hdmi_clkin_ck>, <&l3_iclk_div>;
8318 + bit-shift = <25>;
8319 + reg = <0x4a0093d0 0x4>;
8320 + bit-mask = <0x7>;
8321 +};
8322 +
8323 +gpu_core_gclk_mux: gpu_core_gclk_mux@4a009220 {
8324 + #clock-cells = <0>;
8325 + compatible = "mux-clock";
8326 + clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
8327 + bit-shift = <24>;
8328 + reg = <0x4a009220 0x4>;
8329 + bit-mask = <0x3>;
8330 +};
8331 +
8332 +gpu_hyd_gclk_mux: gpu_hyd_gclk_mux@4a009220 {
8333 + #clock-cells = <0>;
8334 + compatible = "mux-clock";
8335 + clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
8336 + bit-shift = <26>;
8337 + reg = <0x4a009220 0x4>;
8338 + bit-mask = <0x3>;
8339 +};
8340 +
8341 +ipu1_gfclk_mux: ipu1_gfclk_mux@4a005520 {
8342 + #clock-cells = <0>;
8343 + compatible = "mux-clock";
8344 + clocks = <&dpll_abe_m2x2_ck>, <&dpll_core_h22x2_ck>;
8345 + bit-shift = <24>;
8346 + reg = <0x4a005520 0x4>;
8347 + bit-mask = <0x1>;
8348 +};
8349 +
8350 +l3instr_ts_gclk_div: l3instr_ts_gclk_div@4a008e50 {
8351 + #clock-cells = <0>;
8352 + compatible = "divider-clock";
8353 + clocks = <&wkupaon_iclk_mux>;
8354 + bit-shift = <24>;
8355 + reg = <0x4a008e50 0x4>;
8356 + table = < 8 0 >, < 16 1 >, < 32 2 >;
8357 + bit-mask = <0x3>;
8358 +};
8359 +
8360 +mcasp1_ahclkr_mux: mcasp1_ahclkr_mux@4a005550 {
8361 + #clock-cells = <0>;
8362 + compatible = "mux-clock";
8363 + clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
8364 + bit-shift = <28>;
8365 + reg = <0x4a005550 0x4>;
8366 + bit-mask = <0xf>;
8367 +};
8368 +
8369 +mcasp1_ahclkx_mux: mcasp1_ahclkx_mux@4a005550 {
8370 + #clock-cells = <0>;
8371 + compatible = "mux-clock";
8372 + clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
8373 + bit-shift = <24>;
8374 + reg = <0x4a005550 0x4>;
8375 + bit-mask = <0xf>;
8376 +};
8377 +
8378 +mcasp1_aux_gfclk_mux: mcasp1_aux_gfclk_mux@4a005550 {
8379 + #clock-cells = <0>;
8380 + compatible = "mux-clock";
8381 + clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
8382 + bit-shift = <22>;
8383 + reg = <0x4a005550 0x4>;
8384 + bit-mask = <0x3>;
8385 +};
8386 +
8387 +mcasp2_ahclkr_mux: mcasp2_ahclkr_mux@4a009860 {
8388 + #clock-cells = <0>;
8389 + compatible = "mux-clock";
8390 + clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
8391 + bit-shift = <28>;
8392 + reg = <0x4a009860 0x4>;
8393 + bit-mask = <0xf>;
8394 +};
8395 +
8396 +mcasp2_ahclkx_mux: mcasp2_ahclkx_mux@4a009860 {
8397 + #clock-cells = <0>;
8398 + compatible = "mux-clock";
8399 + clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
8400 + bit-shift = <28>;
8401 + reg = <0x4a009860 0x4>;
8402 + bit-mask = <0xf>;
8403 +};
8404 +
8405 +mcasp2_aux_gfclk_mux: mcasp2_aux_gfclk_mux@4a009860 {
8406 + #clock-cells = <0>;
8407 + compatible = "mux-clock";
8408 + clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
8409 + bit-shift = <22>;
8410 + reg = <0x4a009860 0x4>;
8411 + bit-mask = <0x3>;
8412 +};
8413 +
8414 +mcasp3_ahclkx_mux: mcasp3_ahclkx_mux@4a009868 {
8415 + #clock-cells = <0>;
8416 + compatible = "mux-clock";
8417 + clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
8418 + bit-shift = <24>;
8419 + reg = <0x4a009868 0x4>;
8420 + bit-mask = <0xf>;
8421 +};
8422 +
8423 +mcasp3_aux_gfclk_mux: mcasp3_aux_gfclk_mux@4a009868 {
8424 + #clock-cells = <0>;
8425 + compatible = "mux-clock";
8426 + clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
8427 + bit-shift = <22>;
8428 + reg = <0x4a009868 0x4>;
8429 + bit-mask = <0x3>;
8430 +};
8431 +
8432 +mcasp4_ahclkx_mux: mcasp4_ahclkx_mux@4a009898 {
8433 + #clock-cells = <0>;
8434 + compatible = "mux-clock";
8435 + clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
8436 + bit-shift = <24>;
8437 + reg = <0x4a009898 0x4>;
8438 + bit-mask = <0xf>;
8439 +};
8440 +
8441 +mcasp4_aux_gfclk_mux: mcasp4_aux_gfclk_mux@4a009898 {
8442 + #clock-cells = <0>;
8443 + compatible = "mux-clock";
8444 + clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
8445 + bit-shift = <22>;
8446 + reg = <0x4a009898 0x4>;
8447 + bit-mask = <0x3>;
8448 +};
8449 +
8450 +mcasp5_ahclkx_mux: mcasp5_ahclkx_mux@4a009878 {
8451 + #clock-cells = <0>;
8452 + compatible = "mux-clock";
8453 + clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
8454 + bit-shift = <24>;
8455 + reg = <0x4a009878 0x4>;
8456 + bit-mask = <0xf>;
8457 +};
8458 +
8459 +mcasp5_aux_gfclk_mux: mcasp5_aux_gfclk_mux@4a009878 {
8460 + #clock-cells = <0>;
8461 + compatible = "mux-clock";
8462 + clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
8463 + bit-shift = <22>;
8464 + reg = <0x4a009878 0x4>;
8465 + bit-mask = <0x3>;
8466 +};
8467 +
8468 +mcasp6_ahclkx_mux: mcasp6_ahclkx_mux@4a009904 {
8469 + #clock-cells = <0>;
8470 + compatible = "mux-clock";
8471 + clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
8472 + bit-shift = <24>;
8473 + reg = <0x4a009904 0x4>;
8474 + bit-mask = <0xf>;
8475 +};
8476 +
8477 +mcasp6_aux_gfclk_mux: mcasp6_aux_gfclk_mux@4a009904 {
8478 + #clock-cells = <0>;
8479 + compatible = "mux-clock";
8480 + clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
8481 + bit-shift = <22>;
8482 + reg = <0x4a009904 0x4>;
8483 + bit-mask = <0x3>;
8484 +};
8485 +
8486 +mcasp7_ahclkx_mux: mcasp7_ahclkx_mux@4a009908 {
8487 + #clock-cells = <0>;
8488 + compatible = "mux-clock";
8489 + clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
8490 + bit-shift = <24>;
8491 + reg = <0x4a009908 0x4>;
8492 + bit-mask = <0xf>;
8493 +};
8494 +
8495 +mcasp7_aux_gfclk_mux: mcasp7_aux_gfclk_mux@4a009908 {
8496 + #clock-cells = <0>;
8497 + compatible = "mux-clock";
8498 + clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
8499 + bit-shift = <22>;
8500 + reg = <0x4a009908 0x4>;
8501 + bit-mask = <0x3>;
8502 +};
8503 +
8504 +mcasp8_ahclk_mux: mcasp8_ahclk_mux@4a009890 {
8505 + #clock-cells = <0>;
8506 + compatible = "mux-clock";
8507 + clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
8508 + bit-shift = <22>;
8509 + reg = <0x4a009890 0x4>;
8510 + bit-mask = <0x3>;
8511 +};
8512 +
8513 +mcasp8_aux_gfclk_mux: mcasp8_aux_gfclk_mux@4a009890 {
8514 + #clock-cells = <0>;
8515 + compatible = "mux-clock";
8516 + clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
8517 + bit-shift = <24>;
8518 + reg = <0x4a009890 0x4>;
8519 + bit-mask = <0xf>;
8520 +};
8521 +
8522 +mmc1_fclk_mux: mmc1_fclk_mux@4a009328 {
8523 + #clock-cells = <0>;
8524 + compatible = "mux-clock";
8525 + clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
8526 + bit-shift = <24>;
8527 + reg = <0x4a009328 0x4>;
8528 + bit-mask = <0x1>;
8529 +};
8530 +
8531 +mmc1_fclk_div: mmc1_fclk_div@4a009328 {
8532 + #clock-cells = <0>;
8533 + compatible = "divider-clock";
8534 + clocks = <&mmc1_fclk_mux>;
8535 + bit-shift = <25>;
8536 + reg = <0x4a009328 0x4>;
8537 + bit-mask = <0x3>;
8538 + index-power-of-two;
8539 +};
8540 +
8541 +mmc2_fclk_mux: mmc2_fclk_mux@4a009330 {
8542 + #clock-cells = <0>;
8543 + compatible = "mux-clock";
8544 + clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
8545 + bit-shift = <24>;
8546 + reg = <0x4a009330 0x4>;
8547 + bit-mask = <0x1>;
8548 +};
8549 +
8550 +mmc2_fclk_div: mmc2_fclk_div@4a009330 {
8551 + #clock-cells = <0>;
8552 + compatible = "divider-clock";
8553 + clocks = <&mmc2_fclk_mux>;
8554 + bit-shift = <25>;
8555 + reg = <0x4a009330 0x4>;
8556 + bit-mask = <0x3>;
8557 + index-power-of-two;
8558 +};
8559 +
8560 +mmc3_gfclk_mux: mmc3_gfclk_mux@4a009820 {
8561 + #clock-cells = <0>;
8562 + compatible = "mux-clock";
8563 + clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
8564 + bit-shift = <24>;
8565 + reg = <0x4a009820 0x4>;
8566 + bit-mask = <0x1>;
8567 +};
8568 +
8569 +mmc3_gfclk_div: mmc3_gfclk_div@4a009820 {
8570 + #clock-cells = <0>;
8571 + compatible = "divider-clock";
8572 + clocks = <&mmc3_gfclk_mux>;
8573 + bit-shift = <25>;
8574 + reg = <0x4a009820 0x4>;
8575 + bit-mask = <0x3>;
8576 + index-power-of-two;
8577 +};
8578 +
8579 +mmc4_gfclk_mux: mmc4_gfclk_mux@4a009828 {
8580 + #clock-cells = <0>;
8581 + compatible = "mux-clock";
8582 + clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
8583 + bit-shift = <24>;
8584 + reg = <0x4a009828 0x4>;
8585 + bit-mask = <0x1>;
8586 +};
8587 +
8588 +mmc4_gfclk_div: mmc4_gfclk_div@4a009828 {
8589 + #clock-cells = <0>;
8590 + compatible = "divider-clock";
8591 + clocks = <&mmc4_gfclk_mux>;
8592 + bit-shift = <25>;
8593 + reg = <0x4a009828 0x4>;
8594 + bit-mask = <0x3>;
8595 + index-power-of-two;
8596 +};
8597 +
8598 +qspi_gfclk_mux: qspi_gfclk_mux@4a009838 {
8599 + #clock-cells = <0>;
8600 + compatible = "mux-clock";
8601 + clocks = <&func_128m_clk>, <&dpll_per_h13x2_ck>;
8602 + bit-shift = <24>;
8603 + reg = <0x4a009838 0x4>;
8604 + bit-mask = <0x1>;
8605 +};
8606 +
8607 +qspi_gfclk_div: qspi_gfclk_div@4a009838 {
8608 + #clock-cells = <0>;
8609 + compatible = "divider-clock";
8610 + clocks = <&qspi_gfclk_mux>;
8611 + bit-shift = <25>;
8612 + reg = <0x4a009838 0x4>;
8613 + bit-mask = <0x3>;
8614 + index-power-of-two;
8615 +};
8616 +
8617 +timer10_gfclk_mux: timer10_gfclk_mux@4a009728 {
8618 + #clock-cells = <0>;
8619 + compatible = "mux-clock";
8620 + clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
8621 + bit-shift = <24>;
8622 + reg = <0x4a009728 0x4>;
8623 + bit-mask = <0xf>;
8624 +};
8625 +
8626 +timer11_gfclk_mux: timer11_gfclk_mux@4a009730 {
8627 + #clock-cells = <0>;
8628 + compatible = "mux-clock";
8629 + clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
8630 + bit-shift = <24>;
8631 + reg = <0x4a009730 0x4>;
8632 + bit-mask = <0xf>;
8633 +};
8634 +
8635 +timer13_gfclk_mux: timer13_gfclk_mux@4a0097c8 {
8636 + #clock-cells = <0>;
8637 + compatible = "mux-clock";
8638 + clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
8639 + bit-shift = <24>;
8640 + reg = <0x4a0097c8 0x4>;
8641 + bit-mask = <0xf>;
8642 +};
8643 +
8644 +timer14_gfclk_mux: timer14_gfclk_mux@4a0097d0 {
8645 + #clock-cells = <0>;
8646 + compatible = "mux-clock";
8647 + clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
8648 + bit-shift = <24>;
8649 + reg = <0x4a0097d0 0x4>;
8650 + bit-mask = <0xf>;
8651 +};
8652 +
8653 +timer15_gfclk_mux: timer15_gfclk_mux@4a0097d8 {
8654 + #clock-cells = <0>;
8655 + compatible = "mux-clock";
8656 + clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
8657 + bit-shift = <24>;
8658 + reg = <0x4a0097d8 0x4>;
8659 + bit-mask = <0xf>;
8660 +};
8661 +
8662 +timer16_gfclk_mux: timer16_gfclk_mux@4a009830 {
8663 + #clock-cells = <0>;
8664 + compatible = "mux-clock";
8665 + clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
8666 + bit-shift = <24>;
8667 + reg = <0x4a009830 0x4>;
8668 + bit-mask = <0xf>;
8669 +};
8670 +
8671 +timer1_gfclk_mux: timer1_gfclk_mux@4ae07840 {
8672 + #clock-cells = <0>;
8673 + compatible = "mux-clock";
8674 + clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
8675 + bit-shift = <24>;
8676 + reg = <0x4ae07840 0x4>;
8677 + bit-mask = <0xf>;
8678 +};
8679 +
8680 +timer2_gfclk_mux: timer2_gfclk_mux@4a009738 {
8681 + #clock-cells = <0>;
8682 + compatible = "mux-clock";
8683 + clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
8684 + bit-shift = <24>;
8685 + reg = <0x4a009738 0x4>;
8686 + bit-mask = <0xf>;
8687 +};
8688 +
8689 +timer3_gfclk_mux: timer3_gfclk_mux@4a009740 {
8690 + #clock-cells = <0>;
8691 + compatible = "mux-clock";
8692 + clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
8693 + bit-shift = <24>;
8694 + reg = <0x4a009740 0x4>;
8695 + bit-mask = <0xf>;
8696 +};
8697 +
8698 +timer4_gfclk_mux: timer4_gfclk_mux@4a009748 {
8699 + #clock-cells = <0>;
8700 + compatible = "mux-clock";
8701 + clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
8702 + bit-shift = <24>;
8703 + reg = <0x4a009748 0x4>;
8704 + bit-mask = <0xf>;
8705 +};
8706 +
8707 +timer5_gfclk_mux: timer5_gfclk_mux@4a005558 {
8708 + #clock-cells = <0>;
8709 + compatible = "mux-clock";
8710 + clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
8711 + bit-shift = <24>;
8712 + reg = <0x4a005558 0x4>;
8713 + bit-mask = <0xf>;
8714 +};
8715 +
8716 +timer6_gfclk_mux: timer6_gfclk_mux@4a005560 {
8717 + #clock-cells = <0>;
8718 + compatible = "mux-clock";
8719 + clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
8720 + bit-shift = <24>;
8721 + reg = <0x4a005560 0x4>;
8722 + bit-mask = <0xf>;
8723 +};
8724 +
8725 +timer7_gfclk_mux: timer7_gfclk_mux@4a005568 {
8726 + #clock-cells = <0>;
8727 + compatible = "mux-clock";
8728 + clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
8729 + bit-shift = <24>;
8730 + reg = <0x4a005568 0x4>;
8731 + bit-mask = <0xf>;
8732 +};
8733 +
8734 +timer8_gfclk_mux: timer8_gfclk_mux@4a005570 {
8735 + #clock-cells = <0>;
8736 + compatible = "mux-clock";
8737 + clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
8738 + bit-shift = <24>;
8739 + reg = <0x4a005570 0x4>;
8740 + bit-mask = <0xf>;
8741 +};
8742 +
8743 +timer9_gfclk_mux: timer9_gfclk_mux@4a009750 {
8744 + #clock-cells = <0>;
8745 + compatible = "mux-clock";
8746 + clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
8747 + bit-shift = <24>;
8748 + reg = <0x4a009750 0x4>;
8749 + bit-mask = <0xf>;
8750 +};
8751 +
8752 +uart10_gfclk_mux: uart10_gfclk_mux@4ae07880 {
8753 + #clock-cells = <0>;
8754 + compatible = "mux-clock";
8755 + clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
8756 + bit-shift = <24>;
8757 + reg = <0x4ae07880 0x4>;
8758 + bit-mask = <0x1>;
8759 +};
8760 +
8761 +uart1_gfclk_mux: uart1_gfclk_mux@4a009840 {
8762 + #clock-cells = <0>;
8763 + compatible = "mux-clock";
8764 + clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
8765 + bit-shift = <24>;
8766 + reg = <0x4a009840 0x4>;
8767 + bit-mask = <0x1>;
8768 +};
8769 +
8770 +uart2_gfclk_mux: uart2_gfclk_mux@4a009848 {
8771 + #clock-cells = <0>;
8772 + compatible = "mux-clock";
8773 + clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
8774 + bit-shift = <24>;
8775 + reg = <0x4a009848 0x4>;
8776 + bit-mask = <0x1>;
8777 +};
8778 +
8779 +uart3_gfclk_mux: uart3_gfclk_mux@4a009850 {
8780 + #clock-cells = <0>;
8781 + compatible = "mux-clock";
8782 + clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
8783 + bit-shift = <24>;
8784 + reg = <0x4a009850 0x4>;
8785 + bit-mask = <0x1>;
8786 +};
8787 +
8788 +uart4_gfclk_mux: uart4_gfclk_mux@4a009858 {
8789 + #clock-cells = <0>;
8790 + compatible = "mux-clock";
8791 + clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
8792 + bit-shift = <24>;
8793 + reg = <0x4a009858 0x4>;
8794 + bit-mask = <0x1>;
8795 +};
8796 +
8797 +uart5_gfclk_mux: uart5_gfclk_mux@4a009870 {
8798 + #clock-cells = <0>;
8799 + compatible = "mux-clock";
8800 + clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
8801 + bit-shift = <24>;
8802 + reg = <0x4a009870 0x4>;
8803 + bit-mask = <0x1>;
8804 +};
8805 +
8806 +uart6_gfclk_mux: uart6_gfclk_mux@4a005580 {
8807 + #clock-cells = <0>;
8808 + compatible = "mux-clock";
8809 + clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
8810 + bit-shift = <24>;
8811 + reg = <0x4a005580 0x4>;
8812 + bit-mask = <0x1>;
8813 +};
8814 +
8815 +uart7_gfclk_mux: uart7_gfclk_mux@4a0098d0 {
8816 + #clock-cells = <0>;
8817 + compatible = "mux-clock";
8818 + clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
8819 + bit-shift = <24>;
8820 + reg = <0x4a0098d0 0x4>;
8821 + bit-mask = <0x1>;
8822 +};
8823 +
8824 +uart8_gfclk_mux: uart8_gfclk_mux@4a0098e0 {
8825 + #clock-cells = <0>;
8826 + compatible = "mux-clock";
8827 + clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
8828 + bit-shift = <24>;
8829 + reg = <0x4a0098e0 0x4>;
8830 + bit-mask = <0x1>;
8831 +};
8832 +
8833 +uart9_gfclk_mux: uart9_gfclk_mux@4a0098e8 {
8834 + #clock-cells = <0>;
8835 + compatible = "mux-clock";
8836 + clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
8837 + bit-shift = <24>;
8838 + reg = <0x4a0098e8 0x4>;
8839 + bit-mask = <0x1>;
8840 +};
8841 +
8842 +vip1_gclk_mux: vip1_gclk_mux@4a009020 {
8843 + #clock-cells = <0>;
8844 + compatible = "mux-clock";
8845 + clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
8846 + bit-shift = <24>;
8847 + reg = <0x4a009020 0x4>;
8848 + bit-mask = <0x1>;
8849 +};
8850 +
8851 +vip2_gclk_mux: vip2_gclk_mux@4a009028 {
8852 + #clock-cells = <0>;
8853 + compatible = "mux-clock";
8854 + clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
8855 + bit-shift = <24>;
8856 + reg = <0x4a009028 0x4>;
8857 + bit-mask = <0x1>;
8858 +};
8859 +
8860 +vip3_gclk_mux: vip3_gclk_mux@4a009030 {
8861 + #clock-cells = <0>;
8862 + compatible = "mux-clock";
8863 + clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
8864 + bit-shift = <24>;
8865 + reg = <0x4a009030 0x4>;
8866 + bit-mask = <0x1>;
8867 +};
8868 +
8869 +optfclk_pciephy_div: optfclk_pciephy_div@4a00821c {
8870 + compatible = "divider-clock";
8871 + clocks = <&apll_pcie_ck>;
8872 + #clock-cells = <0>;
8873 + reg = <0x4a00821c 0x4>;
8874 + bit-mask = <0x100>;
8875 +};
8876 +
8877 +optfclk_pciephy_clk: optfclk_pciephy_clk@4a0093b0 {
8878 + compatible = "gate-clock";
8879 + clocks = <&apll_pcie_ck>;
8880 + #clock-cells = <0>;
8881 + reg = <0x4a0093b0 0x4>;
8882 + bit-shift = <9>;
8883 +};
8884 +
8885 +optfclk_pciephy_div_clk: optfclk_pciephy_div_clk@4a0093b0 {
8886 + compatible = "gate-clock";
8887 + clocks = <&optfclk_pciephy_div>;
8888 + #clock-cells = <0>;
8889 + reg = <0x4a0093b0 0x4>;
8890 + bit-shift = <10>;
8891 +};
8892 --- a/arch/arm/boot/dts/Makefile
8893 +++ b/arch/arm/boot/dts/Makefile
8894 @@ -186,9 +186,12 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420
8895 am335x-evmsk.dtb \
8896 am335x-bone.dtb \
8897 am335x-boneblack.dtb \
8898 + am335x-evm-profile2.dtb \
8899 am3517-evm.dtb \
8900 am3517_mt_ventoux.dtb \
8901 - am43x-epos-evm.dtb
8902 + am43x-epos-evm.dtb \
8903 + am437x-gp-evm.dtb \
8904 + dra7-evm.dtb
8905 dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-ethernet-disk-mini-v2.dtb
8906 dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb
8907 dtb-$(CONFIG_ARCH_U8500) += ste-snowball.dtb \
8908 --- a/arch/arm/boot/dts/omap2420.dtsi
8909 +++ b/arch/arm/boot/dts/omap2420.dtsi
8910 @@ -114,6 +114,18 @@
8911 dma-names = "tx", "rx";
8912 };
8913
8914 + mailbox: mailbox@48094000 {
8915 + compatible = "ti,omap2-mailbox";
8916 + reg = <0x48094000 0x200>;
8917 + interrupts = <26>, /* DSP Interrupt */
8918 + <34>; /* IVA Interrupt */
8919 + ti,hwmods = "mailbox";
8920 + ti,mbox-num-users = <4>;
8921 + ti,mbox-num-fifos = <6>;
8922 + ti,mbox-names = "dsp", "iva";
8923 + ti,mbox-data = <0 1 0 0>, <2 3 1 3>;
8924 + };
8925 +
8926 timer1: timer@48028000 {
8927 compatible = "ti,omap2420-timer";
8928 reg = <0x48028000 0x400>;
8929 --- a/arch/arm/boot/dts/omap2430.dtsi
8930 +++ b/arch/arm/boot/dts/omap2430.dtsi
8931 @@ -175,6 +175,17 @@
8932 dma-names = "tx", "rx";
8933 };
8934
8935 + mailbox: mailbox@48094000 {
8936 + compatible = "ti,omap2-mailbox";
8937 + reg = <0x48094000 0x200>;
8938 + interrupts = <26>;
8939 + ti,hwmods = "mailbox";
8940 + ti,mbox-num-users = <4>;
8941 + ti,mbox-num-fifos = <6>;
8942 + ti,mbox-names = "dsp";
8943 + ti,mbox-data = <0 1 0 0>;
8944 + };
8945 +
8946 timer1: timer@49018000 {
8947 compatible = "ti,omap2420-timer";
8948 reg = <0x49018000 0x400>;
8949 --- /dev/null
8950 +++ b/arch/arm/boot/dts/omap3430es1-clocks.dtsi
8951 @@ -0,0 +1,158 @@
8952 +/*
8953 + * Device Tree Source for OMAP3430 ES1 clock data
8954 + *
8955 + * Copyright (C) 2013 Texas Instruments, Inc.
8956 + *
8957 + * This program is free software; you can redistribute it and/or modify
8958 + * it under the terms of the GNU General Public License version 2 as
8959 + * published by the Free Software Foundation.
8960 + */
8961 +
8962 +gfx_l3_ck: gfx_l3_ck@48004b10 {
8963 + #clock-cells = <0>;
8964 + compatible = "ti,gate-clock";
8965 + clocks = <&l3_ick>;
8966 + reg = <0x48004b10 0x4>;
8967 + ti,enable-bit = <0>;
8968 +};
8969 +
8970 +gfx_l3_fck: gfx_l3_fck@48004b40 {
8971 + #clock-cells = <0>;
8972 + compatible = "divider-clock";
8973 + clocks = <&l3_ick>;
8974 + reg = <0x48004b40 0x4>;
8975 + bit-mask = <0x7>;
8976 + index-starts-at-one;
8977 +};
8978 +
8979 +gfx_l3_ick: gfx_l3_ick {
8980 + #clock-cells = <0>;
8981 + compatible = "fixed-factor-clock";
8982 + clocks = <&gfx_l3_ck>;
8983 + clock-mult = <1>;
8984 + clock-div = <1>;
8985 +};
8986 +
8987 +gfx_cg1_ck: gfx_cg1_ck@48004b00 {
8988 + #clock-cells = <0>;
8989 + compatible = "ti,gate-clock";
8990 + clocks = <&gfx_l3_fck>;
8991 + reg = <0x48004b00 0x4>;
8992 + ti,enable-bit = <1>;
8993 +};
8994 +
8995 +gfx_cg2_ck: gfx_cg2_ck@48004b00 {
8996 + #clock-cells = <0>;
8997 + compatible = "ti,gate-clock";
8998 + clocks = <&gfx_l3_fck>;
8999 + reg = <0x48004b00 0x4>;
9000 + ti,enable-bit = <2>;
9001 +};
9002 +
9003 +d2d_26m_fck: d2d_26m_fck@48004a00 {
9004 + #clock-cells = <0>;
9005 + compatible = "ti,gate-clock";
9006 + clocks = <&sys_ck>;
9007 + reg = <0x48004a00 0x4>;
9008 + ti,enable-bit = <3>;
9009 +};
9010 +
9011 +fshostusb_fck: fshostusb_fck@48004a00 {
9012 + #clock-cells = <0>;
9013 + compatible = "ti,gate-clock";
9014 + clocks = <&core_48m_fck>;
9015 + reg = <0x48004a00 0x4>;
9016 + ti,enable-bit = <5>;
9017 +};
9018 +
9019 +ssi_ssr_div_fck_3430es1: ssi_ssr_div_fck_3430es1@48004a40 {
9020 + #clock-cells = <0>;
9021 + compatible = "divider-clock";
9022 + clocks = <&corex2_fck>;
9023 + bit-shift = <8>;
9024 + reg = <0x48004a40 0x4>;
9025 + table = < 1 1 >, < 2 2 >, < 3 3 >, < 4 4 >, < 6 6 >, < 8 8 >;
9026 + bit-mask = <0xf>;
9027 +};
9028 +
9029 +ssi_ssr_fck_3430es1: ssi_ssr_fck_3430es1@48004a00 {
9030 + #clock-cells = <0>;
9031 + compatible = "gate-clock";
9032 + clocks = <&ssi_ssr_div_fck_3430es1>;
9033 + bit-shift = <0>;
9034 + reg = <0x48004a00 0x4>;
9035 +};
9036 +
9037 +ssi_sst_fck_3430es1: ssi_sst_fck_3430es1 {
9038 + #clock-cells = <0>;
9039 + compatible = "fixed-factor-clock";
9040 + clocks = <&ssi_ssr_fck_3430es1>;
9041 + clock-mult = <1>;
9042 + clock-div = <2>;
9043 +};
9044 +
9045 +hsotgusb_ick: hsotgusb_ick@48004a10 {
9046 + #clock-cells = <0>;
9047 + compatible = "ti,omap3-no-wait-interface-clock";
9048 + clocks = <&core_l3_ick>;
9049 + reg = <0x48004a10 0x4>;
9050 + ti,enable-bit = <4>;
9051 +};
9052 +
9053 +fac_ick: fac_ick@48004a10 {
9054 + #clock-cells = <0>;
9055 + compatible = "ti,omap3-interface-clock";
9056 + clocks = <&core_l4_ick>;
9057 + reg = <0x48004a10 0x4>;
9058 + ti,enable-bit = <8>;
9059 +};
9060 +
9061 +ssi_l4_ick: ssi_l4_ick {
9062 + #clock-cells = <0>;
9063 + compatible = "fixed-factor-clock";
9064 + clocks = <&l4_ick>;
9065 + clock-mult = <1>;
9066 + clock-div = <1>;
9067 +};
9068 +
9069 +ssi_ick_3430es1: ssi_ick_3430es1@48004a10 {
9070 + #clock-cells = <0>;
9071 + compatible = "ti,omap3-no-wait-interface-clock";
9072 + clocks = <&ssi_l4_ick>;
9073 + reg = <0x48004a10 0x4>;
9074 + ti,enable-bit = <0>;
9075 +};
9076 +
9077 +usb_l4_div_ick: usb_l4_div_ick@48004a40 {
9078 + #clock-cells = <0>;
9079 + compatible = "divider-clock";
9080 + clocks = <&l4_ick>;
9081 + bit-shift = <4>;
9082 + reg = <0x48004a40 0x4>;
9083 + bit-mask = <0x3>;
9084 + index-starts-at-one;
9085 +};
9086 +
9087 +usb_l4_ick: usb_l4_ick@48004a10 {
9088 + #clock-cells = <0>;
9089 + compatible = "gate-clock";
9090 + clocks = <&usb_l4_div_ick>;
9091 + bit-shift = <5>;
9092 + reg = <0x48004a10 0x4>;
9093 +};
9094 +
9095 +dss1_alwon_fck_3430es1: dss1_alwon_fck_3430es1@48004e00 {
9096 + #clock-cells = <0>;
9097 + compatible = "gate-clock";
9098 + clocks = <&dpll4_m4x2_ck>;
9099 + reg = <0x48004e00 0x4>;
9100 + bit-shift = <0>;
9101 +};
9102 +
9103 +dss_ick_3430es1: dss_ick_3430es1@48004e10 {
9104 + #clock-cells = <0>;
9105 + compatible = "ti,omap3-no-wait-interface-clock";
9106 + clocks = <&l4_ick>;
9107 + reg = <0x48004e10 0x4>;
9108 + ti,enable-bit = <0>;
9109 +};
9110 --- a/arch/arm/boot/dts/omap34xx.dtsi
9111 +++ b/arch/arm/boot/dts/omap34xx.dtsi
9112 @@ -25,4 +25,113 @@
9113 clock-latency = <300000>; /* From legacy driver */
9114 };
9115 };
9116 -};
9117 +
9118 + clocks {
9119 + #address-cells = <1>;
9120 + #size-cells = <1>;
9121 + ranges;
9122 + /include/ "omap34xx-omap36xx-clocks.dtsi"
9123 + /include/ "omap36xx-omap3430es2plus-clocks.dtsi"
9124 + /include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
9125 + };
9126 +
9127 + clockdomains {
9128 + usbhost_clkdm: usbhost_clkdm {
9129 + compatible = "ti,clockdomain";
9130 + clocks = <&usbhost_48m_fck>, <&usbhost_ick>;
9131 + };
9132 +
9133 + wkup_clkdm: wkup_clkdm {
9134 + compatible = "ti,clockdomain";
9135 + clocks = <&wdt1_ick>, <&gpt12_ick>, <&gpio1_ick>,
9136 + <&gpt1_ick>, <&omap_32ksync_ick>, <&wdt2_ick>,
9137 + <&wdt2_fck>;
9138 + };
9139 +
9140 + cam_clkdm: cam_clkdm {
9141 + compatible = "ti,clockdomain";
9142 + clocks = <&cam_ick>;
9143 + };
9144 +
9145 + dpll4_clkdm: dpll4_clkdm {
9146 + compatible = "ti,clockdomain";
9147 + clocks = <&dpll4_ck>;
9148 + };
9149 +
9150 + sgx_clkdm: sgx_clkdm {
9151 + compatible = "ti,clockdomain";
9152 + clocks = <&sgx_ick>;
9153 + };
9154 +
9155 + dpll3_clkdm: dpll3_clkdm {
9156 + compatible = "ti,clockdomain";
9157 + clocks = <&dpll3_ck>;
9158 + };
9159 +
9160 + iva2_clkdm: iva2_clkdm {
9161 + compatible = "ti,clockdomain";
9162 + clocks = <&iva2_ck>;
9163 + };
9164 +
9165 + dpll1_clkdm: dpll1_clkdm {
9166 + compatible = "ti,clockdomain";
9167 + clocks = <&dpll1_ck>;
9168 + };
9169 +
9170 + dpll2_clkdm: dpll2_clkdm {
9171 + compatible = "ti,clockdomain";
9172 + clocks = <&dpll2_ck>;
9173 + };
9174 +
9175 + dpll5_clkdm: dpll5_clkdm {
9176 + compatible = "ti,clockdomain";
9177 + clocks = <&dpll5_ck>;
9178 + };
9179 +
9180 + dss_clkdm: dss_clkdm {
9181 + compatible = "ti,clockdomain";
9182 + clocks = <&dss1_alwon_fck_3430es2>, <&dss_ick_3430es2>;
9183 + };
9184 +
9185 + core_l4_clkdm: core_l4_clkdm {
9186 + compatible = "ti,clockdomain";
9187 + clocks = <&mmchs1_ick>, <&mmchs2_ick>, <&hdq_fck>,
9188 + <&uart1_ick>, <&mcspi4_fck>, <&i2c3_fck>,
9189 + <&mcspi2_ick>, <&uart2_ick>, <&mcspi3_ick>,
9190 + <&i2c1_fck>, <&hdq_ick>, <&sha12_ick>,
9191 + <&mcbsp5_ick>, <&mcspi3_fck>, <&aes2_ick>,
9192 + <&mcspi1_ick>, <&uart2_fck>, <&mmchs2_fck>,
9193 + <&mmchs1_fck>, <&i2c3_ick>, <&mcspi1_fck>,
9194 + <&mcspi4_ick>, <&omapctrl_ick>, <&mcbsp1_ick>,
9195 + <&mcspi2_fck>, <&gpt10_ick>, <&i2c2_fck>,
9196 + <&i2c2_ick>, <&gpt11_ick>, <&i2c1_ick>,
9197 + <&uart1_fck>;
9198 + };
9199 +
9200 + core_l3_clkdm: core_l3_clkdm {
9201 + compatible = "ti,clockdomain";
9202 + clocks = <&sdrc_ick>;
9203 + };
9204 +
9205 + per_clkdm: per_clkdm {
9206 + compatible = "ti,clockdomain";
9207 + clocks = <&gpt2_ick>, <&uart3_fck>, <&gpio3_ick>,
9208 + <&mcbsp2_ick>, <&gpt6_ick>, <&mcbsp4_ick>,
9209 + <&gpt4_ick>, <&mcbsp3_ick>, <&gpt8_ick>,
9210 + <&uart3_ick>, <&gpt5_ick>, <&gpt7_ick>,
9211 + <&gpio2_ick>, <&gpio6_ick>, <&gpt9_ick>,
9212 + <&gpt3_ick>, <&gpio5_ick>, <&wdt3_ick>,
9213 + <&gpio4_ick>, <&wdt3_fck>, <&uart4_ick>;
9214 + };
9215 +
9216 + emu_clkdm: emu_clkdm {
9217 + compatible = "ti,clockdomain";
9218 + clocks = <&emu_src_ck>;
9219 + };
9220 +
9221 + d2d_clkdm: d2d_clkdm {
9222 + compatible = "ti,clockdomain";
9223 + clocks = <&mad2d_ick>, <&sad2d_ick>, <&modem_fck>;
9224 + };
9225 + };
9226 +};
9227 \ No newline at end of file
9228 --- /dev/null
9229 +++ b/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi
9230 @@ -0,0 +1,222 @@
9231 +/*
9232 + * Device Tree Source for OMAP34xx/OMAP36xx clock data
9233 + *
9234 + * Copyright (C) 2013 Texas Instruments, Inc.
9235 + *
9236 + * This program is free software; you can redistribute it and/or modify
9237 + * it under the terms of the GNU General Public License version 2 as
9238 + * published by the Free Software Foundation.
9239 + */
9240 +
9241 +security_l4_ick2: security_l4_ick2 {
9242 + #clock-cells = <0>;
9243 + compatible = "fixed-factor-clock";
9244 + clocks = <&l4_ick>;
9245 + clock-mult = <1>;
9246 + clock-div = <1>;
9247 +};
9248 +
9249 +aes1_ick: aes1_ick@48004a14 {
9250 + #clock-cells = <0>;
9251 + compatible = "ti,omap3-interface-clock";
9252 + clocks = <&security_l4_ick2>;
9253 + reg = <0x48004a14 0x4>;
9254 + ti,enable-bit = <3>;
9255 +};
9256 +
9257 +rng_ick: rng_ick@48004a14 {
9258 + #clock-cells = <0>;
9259 + compatible = "ti,omap3-interface-clock";
9260 + clocks = <&security_l4_ick2>;
9261 + reg = <0x48004a14 0x4>;
9262 + ti,enable-bit = <2>;
9263 +};
9264 +
9265 +sha11_ick: sha11_ick@48004a14 {
9266 + #clock-cells = <0>;
9267 + compatible = "ti,omap3-interface-clock";
9268 + clocks = <&security_l4_ick2>;
9269 + reg = <0x48004a14 0x4>;
9270 + ti,enable-bit = <1>;
9271 +};
9272 +
9273 +des1_ick: des1_ick@48004a14 {
9274 + #clock-cells = <0>;
9275 + compatible = "ti,omap3-interface-clock";
9276 + clocks = <&security_l4_ick2>;
9277 + reg = <0x48004a14 0x4>;
9278 + ti,enable-bit = <0>;
9279 +};
9280 +
9281 +cam_mclk: cam_mclk@48004f00 {
9282 + #clock-cells = <0>;
9283 + compatible = "gate-clock";
9284 + clocks = <&dpll4_m5x2_ck>;
9285 + bit-shift = <0>;
9286 + reg = <0x48004f00 0x4>;
9287 + set-rate-parent;
9288 +};
9289 +
9290 +cam_ick: cam_ick@48004f10 {
9291 + #clock-cells = <0>;
9292 + compatible = "ti,omap3-no-wait-interface-clock";
9293 + clocks = <&l4_ick>;
9294 + reg = <0x48004f10 0x4>;
9295 + ti,enable-bit = <0>;
9296 +};
9297 +
9298 +csi2_96m_fck: csi2_96m_fck@48004f00 {
9299 + #clock-cells = <0>;
9300 + compatible = "gate-clock";
9301 + clocks = <&core_96m_fck>;
9302 + reg = <0x48004f00 0x4>;
9303 + bit-shift = <1>;
9304 +};
9305 +
9306 +security_l3_ick: security_l3_ick {
9307 + #clock-cells = <0>;
9308 + compatible = "fixed-factor-clock";
9309 + clocks = <&l3_ick>;
9310 + clock-mult = <1>;
9311 + clock-div = <1>;
9312 +};
9313 +
9314 +pka_ick: pka_ick@48004a14 {
9315 + #clock-cells = <0>;
9316 + compatible = "ti,omap3-interface-clock";
9317 + clocks = <&security_l3_ick>;
9318 + reg = <0x48004a14 0x4>;
9319 + ti,enable-bit = <4>;
9320 +};
9321 +
9322 +icr_ick: icr_ick@48004a10 {
9323 + #clock-cells = <0>;
9324 + compatible = "ti,omap3-interface-clock";
9325 + clocks = <&core_l4_ick>;
9326 + reg = <0x48004a10 0x4>;
9327 + ti,enable-bit = <29>;
9328 +};
9329 +
9330 +des2_ick: des2_ick@48004a10 {
9331 + #clock-cells = <0>;
9332 + compatible = "ti,omap3-interface-clock";
9333 + clocks = <&core_l4_ick>;
9334 + reg = <0x48004a10 0x4>;
9335 + ti,enable-bit = <26>;
9336 +};
9337 +
9338 +mspro_ick: mspro_ick@48004a10 {
9339 + #clock-cells = <0>;
9340 + compatible = "ti,omap3-interface-clock";
9341 + clocks = <&core_l4_ick>;
9342 + reg = <0x48004a10 0x4>;
9343 + ti,enable-bit = <23>;
9344 +};
9345 +
9346 +mailboxes_ick: mailboxes_ick@48004a10 {
9347 + #clock-cells = <0>;
9348 + compatible = "ti,omap3-interface-clock";
9349 + clocks = <&core_l4_ick>;
9350 + reg = <0x48004a10 0x4>;
9351 + ti,enable-bit = <7>;
9352 +};
9353 +
9354 +ssi_l4_ick: ssi_l4_ick {
9355 + #clock-cells = <0>;
9356 + compatible = "fixed-factor-clock";
9357 + clocks = <&l4_ick>;
9358 + clock-mult = <1>;
9359 + clock-div = <1>;
9360 +};
9361 +
9362 +sr1_fck: sr1_fck@48004c00 {
9363 + #clock-cells = <0>;
9364 + compatible = "ti,gate-clock";
9365 + clocks = <&sys_ck>;
9366 + reg = <0x48004c00 0x4>;
9367 + ti,enable-bit = <6>;
9368 +};
9369 +
9370 +sr2_fck: sr2_fck@48004c00 {
9371 + #clock-cells = <0>;
9372 + compatible = "ti,gate-clock";
9373 + clocks = <&sys_ck>;
9374 + reg = <0x48004c00 0x4>;
9375 + ti,enable-bit = <7>;
9376 +};
9377 +
9378 +sr_l4_ick: sr_l4_ick {
9379 + #clock-cells = <0>;
9380 + compatible = "fixed-factor-clock";
9381 + clocks = <&l4_ick>;
9382 + clock-mult = <1>;
9383 + clock-div = <1>;
9384 +};
9385 +
9386 +dpll2_fck: dpll2_fck@48004040 {
9387 + #clock-cells = <0>;
9388 + compatible = "divider-clock";
9389 + clocks = <&core_ck>;
9390 + bit-shift = <19>;
9391 + reg = <0x48004040 0x4>;
9392 + bit-mask = <0x7>;
9393 + index-starts-at-one;
9394 +};
9395 +
9396 +dpll2_ck: dpll2_ck@48004004 {
9397 + #clock-cells = <0>;
9398 + compatible = "ti,omap3-dpll-clock";
9399 + clocks = <&sys_ck>, <&dpll2_fck>;
9400 + ti,modes = <0xa2>;
9401 + reg-names = "control", "idlest", "autoidle", "mult-div1";
9402 + reg = <0x48004004 0x4>, <0x48004024 0x4>, <0x48004034 0x4>, <0x48004040 0x4>;
9403 +};
9404 +
9405 +dpll2_m2_ck: dpll2_m2_ck@48004044 {
9406 + #clock-cells = <0>;
9407 + compatible = "divider-clock";
9408 + clocks = <&dpll2_ck>;
9409 + reg = <0x48004044 0x4>;
9410 + bit-mask = <0x1f>;
9411 + index-starts-at-one;
9412 +};
9413 +
9414 +iva2_ck: iva2_ck@48004000 {
9415 + #clock-cells = <0>;
9416 + compatible = "ti,gate-clock";
9417 + clocks = <&dpll2_m2_ck>;
9418 + reg = <0x48004000 0x4>;
9419 + ti,enable-bit = <0>;
9420 +};
9421 +
9422 +modem_fck: modem_fck@48004a00 {
9423 + #clock-cells = <0>;
9424 + compatible = "ti,omap3-interface-clock";
9425 + clocks = <&sys_ck>;
9426 + reg = <0x48004a00 0x4>;
9427 + ti,enable-bit = <31>;
9428 +};
9429 +
9430 +sad2d_ick: sad2d_ick@48004a10 {
9431 + #clock-cells = <0>;
9432 + compatible = "ti,omap3-interface-clock";
9433 + clocks = <&l3_ick>;
9434 + reg = <0x48004a10 0x4>;
9435 + ti,enable-bit = <3>;
9436 +};
9437 +
9438 +mad2d_ick: mad2d_ick@48004a18 {
9439 + #clock-cells = <0>;
9440 + compatible = "ti,omap3-interface-clock";
9441 + clocks = <&l3_ick>;
9442 + reg = <0x48004a18 0x4>;
9443 + ti,enable-bit = <3>;
9444 +};
9445 +
9446 +mspro_fck: mspro_fck@48004a00 {
9447 + #clock-cells = <0>;
9448 + compatible = "ti,gate-clock";
9449 + clocks = <&core_96m_fck>;
9450 + reg = <0x48004a00 0x4>;
9451 + ti,enable-bit = <23>;
9452 +};
9453 --- /dev/null
9454 +++ b/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi
9455 @@ -0,0 +1,196 @@
9456 +/*
9457 + * Device Tree Source for OMAP36xx/AM35xx/OMAP34xx clock data
9458 + *
9459 + * Copyright (C) 2013 Texas Instruments, Inc.
9460 + *
9461 + * This program is free software; you can redistribute it and/or modify
9462 + * it under the terms of the GNU General Public License version 2 as
9463 + * published by the Free Software Foundation.
9464 + */
9465 +
9466 +dpll5_ck: dpll5_ck@48004d04 {
9467 + #clock-cells = <0>;
9468 + compatible = "ti,omap3-dpll-clock";
9469 + clocks = <&sys_ck>, <&sys_ck>;
9470 + ti,modes = <0x82>;
9471 + reg-names = "control", "idlest", "autoidle", "mult-div1";
9472 + reg = <0x48004d04 0x4>, <0x48004d24 0x4>, <0x48004d34 0x4>, <0x48004d4c 0x4>;
9473 +};
9474 +
9475 +dpll5_m2_ck: dpll5_m2_ck@48004d50 {
9476 + #clock-cells = <0>;
9477 + compatible = "divider-clock";
9478 + clocks = <&dpll5_ck>;
9479 + reg = <0x48004d50 0x4>;
9480 + bit-mask = <0x1f>;
9481 + index-starts-at-one;
9482 +};
9483 +
9484 +core_d3_ck: core_d3_ck {
9485 + #clock-cells = <0>;
9486 + compatible = "fixed-factor-clock";
9487 + clocks = <&core_ck>;
9488 + clock-mult = <1>;
9489 + clock-div = <3>;
9490 +};
9491 +
9492 +core_d4_ck: core_d4_ck {
9493 + #clock-cells = <0>;
9494 + compatible = "fixed-factor-clock";
9495 + clocks = <&core_ck>;
9496 + clock-mult = <1>;
9497 + clock-div = <4>;
9498 +};
9499 +
9500 +core_d6_ck: core_d6_ck {
9501 + #clock-cells = <0>;
9502 + compatible = "fixed-factor-clock";
9503 + clocks = <&core_ck>;
9504 + clock-mult = <1>;
9505 + clock-div = <6>;
9506 +};
9507 +
9508 +omap_192m_alwon_fck: omap_192m_alwon_fck {
9509 + #clock-cells = <0>;
9510 + compatible = "fixed-factor-clock";
9511 + clocks = <&dpll4_m2x2_ck>;
9512 + clock-mult = <1>;
9513 + clock-div = <1>;
9514 +};
9515 +
9516 +core_d2_ck: core_d2_ck {
9517 + #clock-cells = <0>;
9518 + compatible = "fixed-factor-clock";
9519 + clocks = <&core_ck>;
9520 + clock-mult = <1>;
9521 + clock-div = <2>;
9522 +};
9523 +
9524 +corex2_d3_fck: corex2_d3_fck {
9525 + #clock-cells = <0>;
9526 + compatible = "fixed-factor-clock";
9527 + clocks = <&corex2_fck>;
9528 + clock-mult = <1>;
9529 + clock-div = <3>;
9530 +};
9531 +
9532 +corex2_d5_fck: corex2_d5_fck {
9533 + #clock-cells = <0>;
9534 + compatible = "fixed-factor-clock";
9535 + clocks = <&corex2_fck>;
9536 + clock-mult = <1>;
9537 + clock-div = <5>;
9538 +};
9539 +
9540 +sgx_mux_fck: sgx_mux_fck@48004b40 {
9541 + #clock-cells = <0>;
9542 + compatible = "mux-clock";
9543 + clocks = <&core_d3_ck>, <&core_d4_ck>, <&core_d6_ck>, <&cm_96m_fck>, <&omap_192m_alwon_fck>, <&core_d2_ck>, <&corex2_d3_fck>, <&corex2_d5_fck>;
9544 + reg = <0x48004b40 0x4>;
9545 + table = <&core_d3_ck 0>, <&core_d4_ck 1>, <&core_d6_ck 2>, <&cm_96m_fck 3>, <&omap_192m_alwon_fck 4>, <&core_d2_ck 5>, <&corex2_d3_fck 6>, <&corex2_d5_fck 7>;
9546 + bit-mask = <0x7>;
9547 +};
9548 +
9549 +sgx_fck: sgx_fck@48004b00 {
9550 + #clock-cells = <0>;
9551 + compatible = "gate-clock";
9552 + clocks = <&sgx_mux_fck>;
9553 + bit-shift = <1>;
9554 + reg = <0x48004b00 0x4>;
9555 +};
9556 +
9557 +sgx_ick: sgx_ick@48004b10 {
9558 + #clock-cells = <0>;
9559 + compatible = "ti,gate-clock";
9560 + clocks = <&l3_ick>;
9561 + reg = <0x48004b10 0x4>;
9562 + ti,enable-bit = <0>;
9563 +};
9564 +
9565 +cpefuse_fck: cpefuse_fck@48004a08 {
9566 + #clock-cells = <0>;
9567 + compatible = "gate-clock";
9568 + clocks = <&sys_ck>;
9569 + reg = <0x48004a08 0x4>;
9570 + bit-shift = <0>;
9571 +};
9572 +
9573 +ts_fck: ts_fck@48004a08 {
9574 + #clock-cells = <0>;
9575 + compatible = "gate-clock";
9576 + clocks = <&omap_32k_fck>;
9577 + reg = <0x48004a08 0x4>;
9578 + bit-shift = <1>;
9579 +};
9580 +
9581 +usbtll_fck: usbtll_fck@48004a08 {
9582 + #clock-cells = <0>;
9583 + compatible = "ti,gate-clock";
9584 + clocks = <&dpll5_m2_ck>;
9585 + reg = <0x48004a08 0x4>;
9586 + ti,enable-bit = <2>;
9587 +};
9588 +
9589 +usbtll_ick: usbtll_ick@48004a18 {
9590 + #clock-cells = <0>;
9591 + compatible = "ti,omap3-interface-clock";
9592 + clocks = <&core_l4_ick>;
9593 + reg = <0x48004a18 0x4>;
9594 + ti,enable-bit = <2>;
9595 +};
9596 +
9597 +mmchs3_ick: mmchs3_ick@48004a10 {
9598 + #clock-cells = <0>;
9599 + compatible = "ti,omap3-interface-clock";
9600 + clocks = <&core_l4_ick>;
9601 + reg = <0x48004a10 0x4>;
9602 + ti,enable-bit = <30>;
9603 +};
9604 +
9605 +mmchs3_fck: mmchs3_fck@48004a00 {
9606 + #clock-cells = <0>;
9607 + compatible = "ti,gate-clock";
9608 + clocks = <&core_96m_fck>;
9609 + reg = <0x48004a00 0x4>;
9610 + ti,enable-bit = <30>;
9611 +};
9612 +
9613 +dss1_alwon_fck_3430es2: dss1_alwon_fck_3430es2@48004e00 {
9614 + #clock-cells = <0>;
9615 + compatible = "ti,dss-gate-clock";
9616 + clocks = <&dpll4_m4x2_ck>;
9617 + reg = <0x48004e00 0x4>;
9618 + ti,enable-bit = <0>;
9619 +};
9620 +
9621 +dss_ick_3430es2: dss_ick_3430es2@48004e10 {
9622 + #clock-cells = <0>;
9623 + compatible = "ti,omap3-dss-interface-clock";
9624 + clocks = <&l4_ick>;
9625 + reg = <0x48004e10 0x4>;
9626 + ti,enable-bit = <0>;
9627 +};
9628 +
9629 +usbhost_120m_fck: usbhost_120m_fck@48005400 {
9630 + #clock-cells = <0>;
9631 + compatible = "gate-clock";
9632 + clocks = <&dpll5_m2_ck>;
9633 + reg = <0x48005400 0x4>;
9634 + bit-shift = <1>;
9635 +};
9636 +
9637 +usbhost_48m_fck: usbhost_48m_fck@48005400 {
9638 + #clock-cells = <0>;
9639 + compatible = "ti,dss-gate-clock";
9640 + clocks = <&omap_48m_fck>;
9641 + reg = <0x48005400 0x4>;
9642 + ti,enable-bit = <0>;
9643 +};
9644 +
9645 +usbhost_ick: usbhost_ick@48005410 {
9646 + #clock-cells = <0>;
9647 + compatible = "ti,omap3-dss-interface-clock";
9648 + clocks = <&l4_ick>;
9649 + reg = <0x48005410 0x4>;
9650 + ti,enable-bit = <0>;
9651 +};
9652 --- /dev/null
9653 +++ b/arch/arm/boot/dts/omap36xx-clocks.dtsi
9654 @@ -0,0 +1,80 @@
9655 +/*
9656 + * Device Tree Source for OMAP36xx clock data
9657 + *
9658 + * Copyright (C) 2013 Texas Instruments, Inc.
9659 + *
9660 + * This program is free software; you can redistribute it and/or modify
9661 + * it under the terms of the GNU General Public License version 2 as
9662 + * published by the Free Software Foundation.
9663 + */
9664 +
9665 +dpll4_ck: dpll4_ck@48004d00 {
9666 + #clock-cells = <0>;
9667 + compatible = "ti,omap3-dpll-per-j-type-clock";
9668 + clocks = <&sys_ck>, <&sys_ck>;
9669 + ti,modes = <0x82>;
9670 + reg-names = "control", "idlest", "autoidle", "mult-div1";
9671 + reg = <0x48004d00 0x4>, <0x48004d20 0x4>, <0x48004d30 0x4>, <0x48004d44 0x4>;
9672 +};
9673 +
9674 +dpll4_m2x2_ck: dpll4_m2x2_ck@48004d00 {
9675 + #clock-cells = <0>;
9676 + compatible = "ti,hsdiv-gate-clock";
9677 + clocks = <&dpll4_m2x2_mul_ck>;
9678 + reg = <0x48004d00 0x4>;
9679 + ti,enable-bit = <0x1b>;
9680 + ti,set-bit-to-disable;
9681 +};
9682 +
9683 +dpll3_m3x2_ck: dpll3_m3x2_ck@48004d00 {
9684 + #clock-cells = <0>;
9685 + compatible = "ti,hsdiv-gate-clock";
9686 + clocks = <&dpll3_m3x2_mul_ck>;
9687 + reg = <0x48004d00 0x4>;
9688 + ti,enable-bit = <0xc>;
9689 + ti,set-bit-to-disable;
9690 +};
9691 +
9692 +dpll4_m3x2_ck: dpll4_m3x2_ck@48004d00 {
9693 + #clock-cells = <0>;
9694 + compatible = "ti,hsdiv-gate-clock";
9695 + clocks = <&dpll4_m3x2_mul_ck>;
9696 + reg = <0x48004d00 0x4>;
9697 + ti,enable-bit = <0x1c>;
9698 + ti,set-bit-to-disable;
9699 +};
9700 +
9701 +dpll4_m5x2_ck: dpll4_m5x2_ck@48004d00 {
9702 + #clock-cells = <0>;
9703 + compatible = "ti,hsdiv-gate-clock";
9704 + clocks = <&dpll4_m5x2_mul_ck>;
9705 + reg = <0x48004d00 0x4>;
9706 + ti,enable-bit = <0x1e>;
9707 + ti,set-rate-parent;
9708 + ti,set-bit-to-disable;
9709 +};
9710 +
9711 +dpll4_m6x2_ck: dpll4_m6x2_ck@48004d00 {
9712 + #clock-cells = <0>;
9713 + compatible = "ti,hsdiv-gate-clock";
9714 + clocks = <&dpll4_m6x2_mul_ck>;
9715 + reg = <0x48004d00 0x4>;
9716 + ti,enable-bit = <0x1f>;
9717 + ti,set-bit-to-disable;
9718 +};
9719 +
9720 +omap_192m_alwon_fck: omap_192m_alwon_fck {
9721 + #clock-cells = <0>;
9722 + compatible = "fixed-factor-clock";
9723 + clocks = <&dpll4_m2x2_ck>;
9724 + clock-mult = <1>;
9725 + clock-div = <1>;
9726 +};
9727 +
9728 +uart4_fck: uart4_fck@48005000 {
9729 + #clock-cells = <0>;
9730 + compatible = "ti,gate-clock";
9731 + clocks = <&per_48m_fck>;
9732 + reg = <0x48005000 0x4>;
9733 + ti,enable-bit = <18>;
9734 +};
9735 --- a/arch/arm/boot/dts/omap36xx.dtsi
9736 +++ b/arch/arm/boot/dts/omap36xx.dtsi
9737 @@ -35,4 +35,114 @@
9738 clock-frequency = <48000000>;
9739 };
9740 };
9741 -};
9742 +
9743 + clocks {
9744 + #address-cells = <1>;
9745 + #size-cells = <1>;
9746 + ranges;
9747 + /include/ "omap36xx-clocks.dtsi"
9748 + /include/ "omap34xx-omap36xx-clocks.dtsi"
9749 + /include/ "omap36xx-omap3430es2plus-clocks.dtsi"
9750 + /include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
9751 + };
9752 +
9753 + clockdomains {
9754 + usbhost_clkdm: usbhost_clkdm {
9755 + compatible = "ti,clockdomain";
9756 + clocks = <&usbhost_48m_fck>, <&usbhost_ick>;
9757 + };
9758 +
9759 + wkup_clkdm: wkup_clkdm {
9760 + compatible = "ti,clockdomain";
9761 + clocks = <&wdt1_ick>, <&gpt12_ick>, <&gpio1_ick>,
9762 + <&gpt1_ick>, <&omap_32ksync_ick>, <&wdt2_ick>,
9763 + <&wdt2_fck>;
9764 + };
9765 +
9766 + cam_clkdm: cam_clkdm {
9767 + compatible = "ti,clockdomain";
9768 + clocks = <&cam_ick>;
9769 + };
9770 +
9771 + dpll4_clkdm: dpll4_clkdm {
9772 + compatible = "ti,clockdomain";
9773 + clocks = <&dpll4_ck>;
9774 + };
9775 +
9776 + sgx_clkdm: sgx_clkdm {
9777 + compatible = "ti,clockdomain";
9778 + clocks = <&sgx_ick>;
9779 + };
9780 +
9781 + dpll3_clkdm: dpll3_clkdm {
9782 + compatible = "ti,clockdomain";
9783 + clocks = <&dpll3_ck>;
9784 + };
9785 +
9786 + iva2_clkdm: iva2_clkdm {
9787 + compatible = "ti,clockdomain";
9788 + clocks = <&iva2_ck>;
9789 + };
9790 +
9791 + dpll1_clkdm: dpll1_clkdm {
9792 + compatible = "ti,clockdomain";
9793 + clocks = <&dpll1_ck>;
9794 + };
9795 +
9796 + dpll5_clkdm: dpll5_clkdm {
9797 + compatible = "ti,clockdomain";
9798 + clocks = <&dpll5_ck>;
9799 + };
9800 +
9801 + dpll2_clkdm: dpll2_clkdm {
9802 + compatible = "ti,clockdomain";
9803 + clocks = <&dpll2_ck>;
9804 + };
9805 +
9806 + dss_clkdm: dss_clkdm {
9807 + compatible = "ti,clockdomain";
9808 + clocks = <&dss1_alwon_fck_3430es2>, <&dss_ick_3430es2>;
9809 + };
9810 +
9811 + core_l4_clkdm: core_l4_clkdm {
9812 + compatible = "ti,clockdomain";
9813 + clocks = <&mmchs1_ick>, <&mmchs2_ick>, <&hdq_fck>,
9814 + <&uart1_ick>, <&mcspi4_fck>, <&i2c3_fck>,
9815 + <&mcspi2_ick>, <&uart2_ick>, <&mcspi3_ick>,
9816 + <&i2c1_fck>, <&hdq_ick>, <&sha12_ick>,
9817 + <&mcbsp5_ick>, <&mcspi3_fck>, <&aes2_ick>,
9818 + <&mcspi1_ick>, <&uart2_fck>, <&mmchs2_fck>,
9819 + <&mmchs1_fck>, <&i2c3_ick>, <&mcspi1_fck>,
9820 + <&mcspi4_ick>, <&omapctrl_ick>, <&mcbsp1_ick>,
9821 + <&mcspi2_fck>, <&gpt10_ick>, <&i2c2_fck>,
9822 + <&i2c2_ick>, <&gpt11_ick>, <&i2c1_ick>,
9823 + <&uart1_fck>;
9824 + };
9825 +
9826 + core_l3_clkdm: core_l3_clkdm {
9827 + compatible = "ti,clockdomain";
9828 + clocks = <&sdrc_ick>;
9829 + };
9830 +
9831 + per_clkdm: per_clkdm {
9832 + compatible = "ti,clockdomain";
9833 + clocks = <&gpt2_ick>, <&uart3_fck>, <&gpio3_ick>,
9834 + <&mcbsp2_ick>, <&gpt6_ick>, <&mcbsp4_ick>,
9835 + <&gpt4_ick>, <&mcbsp3_ick>, <&gpt8_ick>,
9836 + <&uart3_ick>, <&gpt5_ick>, <&gpt7_ick>,
9837 + <&gpio2_ick>, <&gpio6_ick>, <&gpt9_ick>,
9838 + <&gpt3_ick>, <&gpio5_ick>, <&wdt3_ick>,
9839 + <&gpio4_ick>, <&wdt3_fck>, <&uart4_ick>;
9840 + };
9841 +
9842 + emu_clkdm: emu_clkdm {
9843 + compatible = "ti,clockdomain";
9844 + clocks = <&emu_src_ck>;
9845 + };
9846 +
9847 + d2d_clkdm: d2d_clkdm {
9848 + compatible = "ti,clockdomain";
9849 + clocks = <&mad2d_ick>, <&sad2d_ick>, <&modem_fck>;
9850 + };
9851 + };
9852 +};
9853 \ No newline at end of file
9854 --- /dev/null
9855 +++ b/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi
9856 @@ -0,0 +1,175 @@
9857 +/*
9858 + * Device Tree Source for OMAP34xx/OMAP36xx clock data
9859 + *
9860 + * Copyright (C) 2013 Texas Instruments, Inc.
9861 + *
9862 + * This program is free software; you can redistribute it and/or modify
9863 + * it under the terms of the GNU General Public License version 2 as
9864 + * published by the Free Software Foundation.
9865 + */
9866 +
9867 +ssi_ssr_div_fck_3430es2: ssi_ssr_div_fck_3430es2@48004a40 {
9868 + #clock-cells = <0>;
9869 + compatible = "divider-clock";
9870 + clocks = <&corex2_fck>;
9871 + bit-shift = <8>;
9872 + reg = <0x48004a40 0x4>;
9873 + table = < 1 1 >, < 2 2 >, < 3 3 >, < 4 4 >, < 6 6 >, < 8 8 >;
9874 + bit-mask = <0xf>;
9875 +};
9876 +
9877 +ssi_ssr_fck_3430es2: ssi_ssr_fck_3430es2@48004a00 {
9878 + #clock-cells = <0>;
9879 + compatible = "gate-clock";
9880 + clocks = <&ssi_ssr_div_fck_3430es2>;
9881 + bit-shift = <0>;
9882 + reg = <0x48004a00 0x4>;
9883 +};
9884 +
9885 +ssi_sst_fck_3430es2: ssi_sst_fck_3430es2 {
9886 + #clock-cells = <0>;
9887 + compatible = "fixed-factor-clock";
9888 + clocks = <&ssi_ssr_fck_3430es2>;
9889 + clock-mult = <1>;
9890 + clock-div = <2>;
9891 +};
9892 +
9893 +hsotgusb_ick: hsotgusb_ick@48004a10 {
9894 + #clock-cells = <0>;
9895 + compatible = "ti,omap3-hsotgusb-interface-clock";
9896 + clocks = <&core_l3_ick>;
9897 + reg = <0x48004a10 0x4>;
9898 + ti,enable-bit = <4>;
9899 +};
9900 +
9901 +ssi_l4_ick: ssi_l4_ick {
9902 + #clock-cells = <0>;
9903 + compatible = "fixed-factor-clock";
9904 + clocks = <&l4_ick>;
9905 + clock-mult = <1>;
9906 + clock-div = <1>;
9907 +};
9908 +
9909 +ssi_ick_3430es2: ssi_ick_3430es2@48004a10 {
9910 + #clock-cells = <0>;
9911 + compatible = "ti,omap3-ssi-interface-clock";
9912 + clocks = <&ssi_l4_ick>;
9913 + reg = <0x48004a10 0x4>;
9914 + ti,enable-bit = <0>;
9915 +};
9916 +
9917 +dpll5_ck: dpll5_ck@48004d04 {
9918 + #clock-cells = <0>;
9919 + compatible = "ti,omap3-dpll-clock";
9920 + clocks = <&sys_ck>, <&sys_ck>;
9921 + ti,modes = <0x82>;
9922 + reg-names = "control", "idlest", "autoidle", "mult-div1";
9923 + reg = <0x48004d04 0x4>, <0x48004d24 0x4>, <0x48004d34 0x4>, <0x48004d4c 0x4>;
9924 +};
9925 +
9926 +dpll5_m2_ck: dpll5_m2_ck@48004d50 {
9927 + #clock-cells = <0>;
9928 + compatible = "divider-clock";
9929 + clocks = <&dpll5_ck>;
9930 + reg = <0x48004d50 0x4>;
9931 + bit-mask = <0x1f>;
9932 + index-starts-at-one;
9933 +};
9934 +
9935 +dpll5_m2_d20_ck: dpll5_m2_d20_ck {
9936 + #clock-cells = <0>;
9937 + compatible = "fixed-factor-clock";
9938 + clocks = <&dpll5_m2_ck>;
9939 + clock-mult = <1>;
9940 + clock-div = <20>;
9941 +};
9942 +
9943 +sys_d2_ck: sys_d2_ck {
9944 + #clock-cells = <0>;
9945 + compatible = "fixed-factor-clock";
9946 + clocks = <&sys_ck>;
9947 + clock-mult = <1>;
9948 + clock-div = <2>;
9949 +};
9950 +
9951 +omap_96m_d2_fck: omap_96m_d2_fck {
9952 + #clock-cells = <0>;
9953 + compatible = "fixed-factor-clock";
9954 + clocks = <&omap_96m_fck>;
9955 + clock-mult = <1>;
9956 + clock-div = <2>;
9957 +};
9958 +
9959 +omap_96m_d4_fck: omap_96m_d4_fck {
9960 + #clock-cells = <0>;
9961 + compatible = "fixed-factor-clock";
9962 + clocks = <&omap_96m_fck>;
9963 + clock-mult = <1>;
9964 + clock-div = <4>;
9965 +};
9966 +
9967 +omap_96m_d8_fck: omap_96m_d8_fck {
9968 + #clock-cells = <0>;
9969 + compatible = "fixed-factor-clock";
9970 + clocks = <&omap_96m_fck>;
9971 + clock-mult = <1>;
9972 + clock-div = <8>;
9973 +};
9974 +
9975 +omap_96m_d10_fck: omap_96m_d10_fck {
9976 + #clock-cells = <0>;
9977 + compatible = "fixed-factor-clock";
9978 + clocks = <&omap_96m_fck>;
9979 + clock-mult = <1>;
9980 + clock-div = <10>;
9981 +};
9982 +
9983 +dpll5_m2_d4_ck: dpll5_m2_d4_ck {
9984 + #clock-cells = <0>;
9985 + compatible = "fixed-factor-clock";
9986 + clocks = <&dpll5_m2_ck>;
9987 + clock-mult = <1>;
9988 + clock-div = <4>;
9989 +};
9990 +
9991 +dpll5_m2_d8_ck: dpll5_m2_d8_ck {
9992 + #clock-cells = <0>;
9993 + compatible = "fixed-factor-clock";
9994 + clocks = <&dpll5_m2_ck>;
9995 + clock-mult = <1>;
9996 + clock-div = <8>;
9997 +};
9998 +
9999 +dpll5_m2_d16_ck: dpll5_m2_d16_ck {
10000 + #clock-cells = <0>;
10001 + compatible = "fixed-factor-clock";
10002 + clocks = <&dpll5_m2_ck>;
10003 + clock-mult = <1>;
10004 + clock-div = <16>;
10005 +};
10006 +
10007 +usim_mux_fck: usim_mux_fck@48004c40 {
10008 + #clock-cells = <0>;
10009 + compatible = "mux-clock";
10010 + clocks = <&sys_ck>, <&dpll5_m2_d20_ck>, <&sys_d2_ck>, <&omap_96m_d2_fck>, <&omap_96m_d4_fck>, <&omap_96m_d8_fck>, <&omap_96m_d10_fck>, <&dpll5_m2_d4_ck>, <&dpll5_m2_d8_ck>, <&dpll5_m2_d16_ck>;
10011 + bit-shift = <3>;
10012 + reg = <0x48004c40 0x4>;
10013 + table = <&sys_ck 1>, <&dpll5_m2_d20_ck 10>, <&sys_d2_ck 2>, <&omap_96m_d2_fck 3>, <&omap_96m_d4_fck 4>, <&omap_96m_d8_fck 5>, <&omap_96m_d10_fck 6>, <&dpll5_m2_d4_ck 7>, <&dpll5_m2_d8_ck 8>, <&dpll5_m2_d16_ck 9>;
10014 + bit-mask = <0xf>;
10015 +};
10016 +
10017 +usim_fck: usim_fck@48004c00 {
10018 + #clock-cells = <0>;
10019 + compatible = "gate-clock";
10020 + clocks = <&usim_mux_fck>;
10021 + bit-shift = <9>;
10022 + reg = <0x48004c00 0x4>;
10023 +};
10024 +
10025 +usim_ick: usim_ick@48004c10 {
10026 + #clock-cells = <0>;
10027 + compatible = "ti,omap3-interface-clock";
10028 + clocks = <&wkup_l4_ick>;
10029 + reg = <0x48004c10 0x4>;
10030 + ti,enable-bit = <9>;
10031 +};
10032 --- a/arch/arm/boot/dts/omap3-beagle.dts
10033 +++ b/arch/arm/boot/dts/omap3-beagle.dts
10034 @@ -44,17 +44,6 @@
10035 };
10036 };
10037
10038 - /* HS USB Port 2 RESET */
10039 - hsusb2_reset: hsusb2_reset_reg {
10040 - compatible = "regulator-fixed";
10041 - regulator-name = "hsusb2_reset";
10042 - regulator-min-microvolt = <3300000>;
10043 - regulator-max-microvolt = <3300000>;
10044 - gpio = <&gpio5 19 0>; /* gpio_147 */
10045 - startup-delay-us = <70000>;
10046 - enable-active-high;
10047 - };
10048 -
10049 /* HS USB Port 2 Power */
10050 hsusb2_power: hsusb2_power_reg {
10051 compatible = "regulator-fixed";
10052 @@ -68,7 +57,7 @@
10053 /* HS USB Host PHY on PORT 2 */
10054 hsusb2_phy: hsusb2_phy {
10055 compatible = "usb-nop-xceiv";
10056 - reset-supply = <&hsusb2_reset>;
10057 + reset-gpios = <&gpio5 19 GPIO_ACTIVE_LOW>; /* gpio_147 */
10058 vcc-supply = <&hsusb2_power>;
10059 };
10060
10061 @@ -101,18 +90,18 @@
10062
10063 hsusbb2_pins: pinmux_hsusbb2_pins {
10064 pinctrl-single,pins = <
10065 - 0x5c0 (PIN_OUTPUT | MUX_MODE3) /* usbb2_ulpitll_clk.usbb1_ulpiphy_clk */
10066 - 0x5c2 (PIN_OUTPUT | MUX_MODE3) /* usbb2_ulpitll_clk.usbb1_ulpiphy_stp */
10067 - 0x5c4 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* usbb2_ulpitll_clk.usbb1_ulpiphy_dir */
10068 - 0x5c6 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* usbb2_ulpitll_clk.usbb1_ulpiphy_nxt */
10069 - 0x5c8 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* usbb2_ulpitll_clk.usbb1_ulpiphy_dat0 */
10070 - 0x5cA (PIN_INPUT_PULLDOWN | MUX_MODE3) /* usbb2_ulpitll_clk.usbb1_ulpiphy_dat1 */
10071 - 0x1a4 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* usbb2_ulpitll_clk.usbb1_ulpiphy_dat2 */
10072 - 0x1a6 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* usbb2_ulpitll_clk.usbb1_ulpiphy_dat3 */
10073 - 0x1a8 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* usbb2_ulpitll_clk.usbb1_ulpiphy_dat4 */
10074 - 0x1aa (PIN_INPUT_PULLDOWN | MUX_MODE3) /* usbb2_ulpitll_clk.usbb1_ulpiphy_dat5 */
10075 - 0x1ac (PIN_INPUT_PULLDOWN | MUX_MODE3) /* usbb2_ulpitll_clk.usbb1_ulpiphy_dat6 */
10076 - 0x1ae (PIN_INPUT_PULLDOWN | MUX_MODE3) /* usbb2_ulpitll_clk.usbb1_ulpiphy_dat7 */
10077 + 0x5c0 (PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */
10078 + 0x5c2 (PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */
10079 + 0x5c4 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */
10080 + 0x5c6 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */
10081 + 0x5c8 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */
10082 + 0x5cA (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */
10083 + 0x1a4 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */
10084 + 0x1a6 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */
10085 + 0x1a8 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */
10086 + 0x1aa (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */
10087 + 0x1ac (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */
10088 + 0x1ae (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */
10089 >;
10090 };
10091
10092 @@ -180,3 +169,39 @@
10093 pinctrl-names = "default";
10094 pinctrl-0 = <&gpio1_pins>;
10095 };
10096 +
10097 +&usb_otg_hs {
10098 + interface-type = <0>;
10099 + usb-phy = <&usb2_phy>;
10100 + mode = <3>;
10101 + power = <50>;
10102 +};
10103 +
10104 +&dpi {
10105 + vdds_dsi-supply = <&vpll2>;
10106 +};
10107 +
10108 +/ {
10109 + aliases {
10110 + display0 = &dvi0;
10111 + display1 = &tv0;
10112 + };
10113 +
10114 + tfp410: encoder@0 {
10115 + compatible = "ti,tfp410";
10116 + video-source = <&dpi>;
10117 + data-lines = <24>;
10118 + gpios = <&gpio5 10 0>; /* 170, power-down */
10119 + };
10120 +
10121 + dvi0: connector@0 {
10122 + compatible = "ti,dvi_connector";
10123 + video-source = <&tfp410>;
10124 + i2c-bus = <&i2c3>;
10125 + };
10126 +
10127 + tv0: connector@1 {
10128 + compatible = "ti,svideo_connector";
10129 + video-source = <&venc>;
10130 + };
10131 +};
10132 --- a/arch/arm/boot/dts/omap3-beagle-xm.dts
10133 +++ b/arch/arm/boot/dts/omap3-beagle-xm.dts
10134 @@ -69,6 +69,23 @@
10135 };
10136
10137 };
10138 +
10139 + /* HS USB Port 2 Power */
10140 + hsusb2_power: hsusb2_power_reg {
10141 + compatible = "regulator-fixed";
10142 + regulator-name = "hsusb2_vbus";
10143 + regulator-min-microvolt = <3300000>;
10144 + regulator-max-microvolt = <3300000>;
10145 + gpio = <&twl_gpio 18 0>; /* GPIO LEDA */
10146 + startup-delay-us = <70000>;
10147 + };
10148 +
10149 + /* HS USB Host PHY on PORT 2 */
10150 + hsusb2_phy: hsusb2_phy {
10151 + compatible = "usb-nop-xceiv";
10152 + reset-gpios = <&gpio5 19 GPIO_ACTIVE_LOW>; /* gpio_147 */
10153 + vcc-supply = <&hsusb2_power>;
10154 + };
10155 };
10156
10157 &omap3_pmx_wkup {
10158 @@ -79,6 +96,37 @@
10159 };
10160 };
10161
10162 +&omap3_pmx_core {
10163 + pinctrl-names = "default";
10164 + pinctrl-0 = <
10165 + &hsusbb2_pins
10166 + >;
10167 +
10168 + uart3_pins: pinmux_uart3_pins {
10169 + pinctrl-single,pins = <
10170 + 0x16e (PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */
10171 + 0x170 (PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx OUTPUT | MODE0 */
10172 + >;
10173 + };
10174 +
10175 + hsusbb2_pins: pinmux_hsusbb2_pins {
10176 + pinctrl-single,pins = <
10177 + 0x5c0 (PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */
10178 + 0x5c2 (PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */
10179 + 0x5c4 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */
10180 + 0x5c6 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */
10181 + 0x5c8 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */
10182 + 0x5cA (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */
10183 + 0x1a4 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */
10184 + 0x1a6 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */
10185 + 0x1a8 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */
10186 + 0x1aa (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */
10187 + 0x1ac (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */
10188 + 0x1ae (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */
10189 + >;
10190 + };
10191 +};
10192 +
10193 &i2c1 {
10194 clock-frequency = <2600000>;
10195
10196 @@ -144,19 +192,12 @@
10197 &usb_otg_hs {
10198 interface-type = <0>;
10199 usb-phy = <&usb2_phy>;
10200 + phys = <&usb2_phy>;
10201 + phy-names = "usb2-phy";
10202 mode = <3>;
10203 power = <50>;
10204 };
10205
10206 -&omap3_pmx_core {
10207 - uart3_pins: pinmux_uart3_pins {
10208 - pinctrl-single,pins = <
10209 - 0x16e (PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */
10210 - 0x170 (PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx OUTPUT | MODE0 */
10211 - >;
10212 - };
10213 -};
10214 -
10215 &uart3 {
10216 pinctrl-names = "default";
10217 pinctrl-0 = <&uart3_pins>;
10218 @@ -166,3 +207,11 @@
10219 pinctrl-names = "default";
10220 pinctrl-0 = <&gpio1_pins>;
10221 };
10222 +
10223 +&usbhshost {
10224 + port2-mode = "ehci-phy";
10225 +};
10226 +
10227 +&usbhsehci {
10228 + phys = <0 &hsusb2_phy>;
10229 +};
10230 --- a/arch/arm/boot/dts/omap3.dtsi
10231 +++ b/arch/arm/boot/dts/omap3.dtsi
10232 @@ -19,6 +19,9 @@
10233 interrupt-parent = <&intc>;
10234
10235 aliases {
10236 + i2c0 = &i2c1;
10237 + i2c1 = &i2c2;
10238 + i2c2 = &i2c3;
10239 serial0 = &uart1;
10240 serial1 = &uart2;
10241 serial2 = &uart3;
10242 @@ -32,6 +35,11 @@
10243 compatible = "arm,cortex-a8";
10244 device_type = "cpu";
10245 reg = <0x0>;
10246 +
10247 + clocks = <&dpll1_ck>;
10248 + clock-names = "cpu";
10249 +
10250 + clock-latency = <300000>; /* From omap-cpufreq driver */
10251 };
10252 };
10253
10254 @@ -80,6 +88,8 @@
10255 compatible = "ti,omap-counter32k";
10256 reg = <0x48320000 0x20>;
10257 ti,hwmods = "counter_32k";
10258 + clocks = <&wkup_32k_fck>;
10259 + clock-names = "fck";
10260 };
10261
10262 intc: interrupt-controller@48200000 {
10263 @@ -100,6 +110,8 @@
10264 #dma-cells = <1>;
10265 #dma-channels = <32>;
10266 #dma-requests = <96>;
10267 + clocks = <&core_l3_ick>;
10268 + clock-names = "fck";
10269 };
10270
10271 omap3_pmx_core: pinmux@48002030 {
10272 @@ -125,6 +137,8 @@
10273 reg = <0x48310000 0x200>;
10274 interrupts = <29>;
10275 ti,hwmods = "gpio1";
10276 + clocks = <&gpio1_ick>, <&gpio1_dbck>;
10277 + clock-names = "fck", "dbclk";
10278 ti,gpio-always-on;
10279 gpio-controller;
10280 #gpio-cells = <2>;
10281 @@ -137,6 +151,8 @@
10282 reg = <0x49050000 0x200>;
10283 interrupts = <30>;
10284 ti,hwmods = "gpio2";
10285 + clocks = <&gpio2_ick>, <&gpio2_dbck>;
10286 + clock-names = "fck", "dbclk";
10287 gpio-controller;
10288 #gpio-cells = <2>;
10289 interrupt-controller;
10290 @@ -148,6 +164,8 @@
10291 reg = <0x49052000 0x200>;
10292 interrupts = <31>;
10293 ti,hwmods = "gpio3";
10294 + clocks = <&gpio3_ick>, <&gpio3_dbck>;
10295 + clock-names = "fck", "dbclk";
10296 gpio-controller;
10297 #gpio-cells = <2>;
10298 interrupt-controller;
10299 @@ -159,6 +177,8 @@
10300 reg = <0x49054000 0x200>;
10301 interrupts = <32>;
10302 ti,hwmods = "gpio4";
10303 + clocks = <&gpio4_ick>, <&gpio4_dbck>;
10304 + clock-names = "fck", "dbclk";
10305 gpio-controller;
10306 #gpio-cells = <2>;
10307 interrupt-controller;
10308 @@ -170,6 +190,8 @@
10309 reg = <0x49056000 0x200>;
10310 interrupts = <33>;
10311 ti,hwmods = "gpio5";
10312 + clocks = <&gpio5_ick>, <&gpio5_dbck>;
10313 + clock-names = "fck", "dbclk";
10314 gpio-controller;
10315 #gpio-cells = <2>;
10316 interrupt-controller;
10317 @@ -181,6 +203,8 @@
10318 reg = <0x49058000 0x200>;
10319 interrupts = <34>;
10320 ti,hwmods = "gpio6";
10321 + clocks = <&gpio6_ick>, <&gpio6_dbck>;
10322 + clock-names = "fck", "dbclk";
10323 gpio-controller;
10324 #gpio-cells = <2>;
10325 interrupt-controller;
10326 @@ -190,18 +214,24 @@
10327 uart1: serial@4806a000 {
10328 compatible = "ti,omap3-uart";
10329 ti,hwmods = "uart1";
10330 + clocks = <&uart1_fck>;
10331 + clock-names = "fck";
10332 clock-frequency = <48000000>;
10333 };
10334
10335 uart2: serial@4806c000 {
10336 compatible = "ti,omap3-uart";
10337 ti,hwmods = "uart2";
10338 + clocks = <&uart2_fck>;
10339 + clock-names = "fck";
10340 clock-frequency = <48000000>;
10341 };
10342
10343 uart3: serial@49020000 {
10344 compatible = "ti,omap3-uart";
10345 ti,hwmods = "uart3";
10346 + clocks = <&uart3_fck>;
10347 + clock-names = "fck";
10348 clock-frequency = <48000000>;
10349 };
10350
10351 @@ -210,6 +240,8 @@
10352 #address-cells = <1>;
10353 #size-cells = <0>;
10354 ti,hwmods = "i2c1";
10355 + clocks = <&i2c1_fck>;
10356 + clock-names = "fck";
10357 };
10358
10359 i2c2: i2c@48072000 {
10360 @@ -217,6 +249,8 @@
10361 #address-cells = <1>;
10362 #size-cells = <0>;
10363 ti,hwmods = "i2c2";
10364 + clocks = <&i2c2_fck>;
10365 + clock-names = "fck";
10366 };
10367
10368 i2c3: i2c@48060000 {
10369 @@ -224,6 +258,8 @@
10370 #address-cells = <1>;
10371 #size-cells = <0>;
10372 ti,hwmods = "i2c3";
10373 + clocks = <&i2c3_fck>;
10374 + clock-names = "fck";
10375 };
10376
10377 mcspi1: spi@48098000 {
10378 @@ -231,6 +267,8 @@
10379 #address-cells = <1>;
10380 #size-cells = <0>;
10381 ti,hwmods = "mcspi1";
10382 + clocks = <&mcspi1_fck>;
10383 + clock-names = "fck";
10384 ti,spi-num-cs = <4>;
10385 dmas = <&sdma 35>,
10386 <&sdma 36>,
10387 @@ -249,6 +287,8 @@
10388 #address-cells = <1>;
10389 #size-cells = <0>;
10390 ti,hwmods = "mcspi2";
10391 + clocks = <&mcspi2_fck>;
10392 + clock-names = "fck";
10393 ti,spi-num-cs = <2>;
10394 dmas = <&sdma 43>,
10395 <&sdma 44>,
10396 @@ -262,6 +302,8 @@
10397 #address-cells = <1>;
10398 #size-cells = <0>;
10399 ti,hwmods = "mcspi3";
10400 + clocks = <&mcspi3_fck>;
10401 + clock-names = "fck";
10402 ti,spi-num-cs = <2>;
10403 dmas = <&sdma 15>,
10404 <&sdma 16>,
10405 @@ -275,6 +317,8 @@
10406 #address-cells = <1>;
10407 #size-cells = <0>;
10408 ti,hwmods = "mcspi4";
10409 + clocks = <&mcspi4_fck>;
10410 + clock-names = "fck";
10411 ti,spi-num-cs = <1>;
10412 dmas = <&sdma 70>, <&sdma 71>;
10413 dma-names = "tx0", "rx0";
10414 @@ -283,6 +327,8 @@
10415 mmc1: mmc@4809c000 {
10416 compatible = "ti,omap3-hsmmc";
10417 ti,hwmods = "mmc1";
10418 + clocks = <&mmchs1_fck>, <&omap_32k_fck>;
10419 + clock-names = "fck", "dbck";
10420 ti,dual-volt;
10421 dmas = <&sdma 61>, <&sdma 62>;
10422 dma-names = "tx", "rx";
10423 @@ -291,6 +337,8 @@
10424 mmc2: mmc@480b4000 {
10425 compatible = "ti,omap3-hsmmc";
10426 ti,hwmods = "mmc2";
10427 + clocks = <&mmchs2_fck>, <&omap_32k_fck>;
10428 + clock-names = "fck", "dbck";
10429 dmas = <&sdma 47>, <&sdma 48>;
10430 dma-names = "tx", "rx";
10431 };
10432 @@ -298,6 +346,8 @@
10433 mmc3: mmc@480ad000 {
10434 compatible = "ti,omap3-hsmmc";
10435 ti,hwmods = "mmc3";
10436 + clocks = <&mmchs3_fck>, <&omap_32k_fck>;
10437 + clock-names = "fck", "dbck";
10438 dmas = <&sdma 77>, <&sdma 78>;
10439 dma-names = "tx", "rx";
10440 };
10441 @@ -305,6 +355,8 @@
10442 wdt2: wdt@48314000 {
10443 compatible = "ti,omap3-wdt";
10444 ti,hwmods = "wd_timer2";
10445 + clocks = <&wdt2_fck>;
10446 + clock-names = "fck";
10447 };
10448
10449 mcbsp1: mcbsp@48074000 {
10450 @@ -317,6 +369,8 @@
10451 interrupt-names = "common", "tx", "rx";
10452 ti,buffer-size = <128>;
10453 ti,hwmods = "mcbsp1";
10454 + clocks = <&mcbsp1_fck>, <&mcbsp_clks>, <&core_96m_fck>;
10455 + clock-names = "fck", "pad_fck", "prcm_fck";
10456 dmas = <&sdma 31>,
10457 <&sdma 32>;
10458 dma-names = "tx", "rx";
10459 @@ -366,6 +420,8 @@
10460 interrupt-names = "common", "tx", "rx";
10461 ti,buffer-size = <128>;
10462 ti,hwmods = "mcbsp4";
10463 + clocks = <&mcbsp4_fck>, <&mcbsp_clks>, <&per_96m_fck>;
10464 + clock-names = "fck", "pad_fck", "prcm_fck";
10465 dmas = <&sdma 19>,
10466 <&sdma 20>;
10467 dma-names = "tx", "rx";
10468 @@ -381,16 +437,31 @@
10469 interrupt-names = "common", "tx", "rx";
10470 ti,buffer-size = <128>;
10471 ti,hwmods = "mcbsp5";
10472 + clocks = <&mcbsp5_fck>, <&mcbsp_clks>, <&core_96m_fck>;
10473 + clock-names = "fck", "pad_fck", "prcm_fck";
10474 dmas = <&sdma 21>,
10475 <&sdma 22>;
10476 dma-names = "tx", "rx";
10477 };
10478
10479 + mailbox: mailbox@48094000 {
10480 + compatible = "ti,omap2-mailbox";
10481 + reg = <0x48094000 0x200>;
10482 + interrupts = <26>;
10483 + ti,hwmods = "mailbox";
10484 + ti,mbox-num-users = <2>;
10485 + ti,mbox-num-fifos = <2>;
10486 + ti,mbox-names = "dsp";
10487 + ti,mbox-data = <0 1 0 0>;
10488 + };
10489 +
10490 timer1: timer@48318000 {
10491 compatible = "ti,omap3430-timer";
10492 reg = <0x48318000 0x400>;
10493 interrupts = <37>;
10494 ti,hwmods = "timer1";
10495 + clocks = <&gpt1_fck>;
10496 + clock-names = "fck";
10497 ti,timer-alwon;
10498 };
10499
10500 @@ -399,6 +470,8 @@
10501 reg = <0x49032000 0x400>;
10502 interrupts = <38>;
10503 ti,hwmods = "timer2";
10504 + clocks = <&gpt2_fck>;
10505 + clock-names = "fck";
10506 };
10507
10508 timer3: timer@49034000 {
10509 @@ -406,6 +479,8 @@
10510 reg = <0x49034000 0x400>;
10511 interrupts = <39>;
10512 ti,hwmods = "timer3";
10513 + clocks = <&gpt3_fck>;
10514 + clock-names = "fck";
10515 };
10516
10517 timer4: timer@49036000 {
10518 @@ -413,6 +488,8 @@
10519 reg = <0x49036000 0x400>;
10520 interrupts = <40>;
10521 ti,hwmods = "timer4";
10522 + clocks = <&gpt4_fck>;
10523 + clock-names = "fck";
10524 };
10525
10526 timer5: timer@49038000 {
10527 @@ -420,6 +497,8 @@
10528 reg = <0x49038000 0x400>;
10529 interrupts = <41>;
10530 ti,hwmods = "timer5";
10531 + clocks = <&gpt5_fck>;
10532 + clock-names = "fck";
10533 ti,timer-dsp;
10534 };
10535
10536 @@ -428,6 +507,8 @@
10537 reg = <0x4903a000 0x400>;
10538 interrupts = <42>;
10539 ti,hwmods = "timer6";
10540 + clocks = <&gpt6_fck>;
10541 + clock-names = "fck";
10542 ti,timer-dsp;
10543 };
10544
10545 @@ -436,6 +517,8 @@
10546 reg = <0x4903c000 0x400>;
10547 interrupts = <43>;
10548 ti,hwmods = "timer7";
10549 + clocks = <&gpt7_fck>;
10550 + clock-names = "fck";
10551 ti,timer-dsp;
10552 };
10553
10554 @@ -444,6 +527,8 @@
10555 reg = <0x4903e000 0x400>;
10556 interrupts = <44>;
10557 ti,hwmods = "timer8";
10558 + clocks = <&gpt8_fck>;
10559 + clock-names = "fck";
10560 ti,timer-pwm;
10561 ti,timer-dsp;
10562 };
10563 @@ -453,6 +538,8 @@
10564 reg = <0x49040000 0x400>;
10565 interrupts = <45>;
10566 ti,hwmods = "timer9";
10567 + clocks = <&gpt9_fck>;
10568 + clock-names = "fck";
10569 ti,timer-pwm;
10570 };
10571
10572 @@ -461,6 +548,8 @@
10573 reg = <0x48086000 0x400>;
10574 interrupts = <46>;
10575 ti,hwmods = "timer10";
10576 + clocks = <&gpt10_fck>;
10577 + clock-names = "fck";
10578 ti,timer-pwm;
10579 };
10580
10581 @@ -469,6 +558,8 @@
10582 reg = <0x48088000 0x400>;
10583 interrupts = <47>;
10584 ti,hwmods = "timer11";
10585 + clocks = <&gpt11_fck>;
10586 + clock-names = "fck";
10587 ti,timer-pwm;
10588 };
10589
10590 @@ -477,6 +568,8 @@
10591 reg = <0x48304000 0x400>;
10592 interrupts = <95>;
10593 ti,hwmods = "timer12";
10594 + clocks = <&gpt12_fck>;
10595 + clock-names = "fck";
10596 ti,timer-alwon;
10597 ti,timer-secure;
10598 };
10599 @@ -486,12 +579,16 @@
10600 reg = <0x48062000 0x1000>;
10601 interrupts = <78>;
10602 ti,hwmods = "usb_tll_hs";
10603 + clocks = <&usbtll_fck>;
10604 + clock-names = "fck";
10605 };
10606
10607 usbhshost: usbhshost@48064000 {
10608 compatible = "ti,usbhs-host";
10609 reg = <0x48064000 0x400>;
10610 ti,hwmods = "usb_host_hs";
10611 + clocks = <&usbhost_48m_fck>, <&usbhost_120m_fck>;
10612 + clock-names = "fck", "ehci_logic_fck";
10613 #address-cells = <1>;
10614 #size-cells = <1>;
10615 ranges;
10616 @@ -514,6 +611,8 @@
10617 gpmc: gpmc@6e000000 {
10618 compatible = "ti,omap3430-gpmc";
10619 ti,hwmods = "gpmc";
10620 + clocks = <&gpmc_fck>;
10621 + clock-names = "fck";
10622 reg = <0x6e000000 0x02d0>;
10623 interrupts = <20>;
10624 gpmc,num-cs = <8>;
10625 @@ -528,9 +627,61 @@
10626 interrupts = <92>, <93>;
10627 interrupt-names = "mc", "dma";
10628 ti,hwmods = "usb_otg_hs";
10629 + clocks = <&hsotgusb_ick>;
10630 + clock-names = "fck";
10631 multipoint = <1>;
10632 num-eps = <16>;
10633 ram-bits = <12>;
10634 };
10635 +
10636 + dss@48050000 {
10637 + compatible = "ti,omap3-dss", "simple-bus";
10638 + reg = <0x48050000 0x200>;
10639 + ti,hwmods = "dss_core";
10640 + #address-cells = <1>;
10641 + #size-cells = <1>;
10642 + ranges;
10643 +
10644 + dispc@48050400 {
10645 + compatible = "ti,omap3-dispc";
10646 + reg = <0x48050400 0x400>;
10647 + interrupts = <25>;
10648 + ti,hwmods = "dss_dispc";
10649 + };
10650 +
10651 + dpi: encoder@0 {
10652 + compatible = "ti,omap3-dpi";
10653 + };
10654 +
10655 + sdi: encoder@1 {
10656 + compatible = "ti,omap3-sdi";
10657 + };
10658 +
10659 + dsi: encoder@4804fc00 {
10660 + compatible = "ti,omap3-dsi";
10661 + reg = <0x4804fc00 0x400>;
10662 + interrupts = <25>;
10663 + ti,hwmods = "dss_dsi1";
10664 + };
10665 +
10666 + rfbi: encoder@48050800 {
10667 + compatible = "ti,omap3-rfbi";
10668 + reg = <0x48050800 0x100>;
10669 + ti,hwmods = "dss_rfbi";
10670 + };
10671 +
10672 + venc: encoder@48050c00 {
10673 + compatible = "ti,omap3-venc";
10674 + reg = <0x48050c00 0x100>;
10675 + ti,hwmods = "dss_venc";
10676 + };
10677 + };
10678 + };
10679 +
10680 + clocks {
10681 + #address-cells = <1>;
10682 + #size-cells = <1>;
10683 + ranges;
10684 + /include/ "omap3xxx-clocks.dtsi"
10685 };
10686 };
10687 --- a/arch/arm/boot/dts/omap3-evm.dts
10688 +++ b/arch/arm/boot/dts/omap3-evm.dts
10689 @@ -70,6 +70,8 @@
10690 &usb_otg_hs {
10691 interface-type = <0>;
10692 usb-phy = <&usb2_phy>;
10693 + phys = <&usb2_phy>;
10694 + phy-names = "usb2-phy";
10695 mode = <3>;
10696 power = <50>;
10697 };
10698 --- a/arch/arm/boot/dts/omap3-overo.dtsi
10699 +++ b/arch/arm/boot/dts/omap3-overo.dtsi
10700 @@ -76,6 +76,8 @@
10701 &usb_otg_hs {
10702 interface-type = <0>;
10703 usb-phy = <&usb2_phy>;
10704 + phys = <&usb2_phy>;
10705 + phy-names = "usb2-phy";
10706 mode = <3>;
10707 power = <50>;
10708 };
10709 --- a/arch/arm/boot/dts/omap3-tobi.dts
10710 +++ b/arch/arm/boot/dts/omap3-tobi.dts
10711 @@ -81,3 +81,36 @@
10712 &mmc3 {
10713 status = "disabled";
10714 };
10715 +
10716 +&dpi {
10717 + vdds_dsi-supply = <&vpll2>;
10718 +};
10719 +
10720 +/ {
10721 + aliases {
10722 + display0 = &lcd0;
10723 + };
10724 +
10725 + lcd0: display@0 {
10726 + compatible = "samsung,lte430wq-f0c", "panel-dpi";
10727 + video-source = <&dpi>;
10728 + data-lines = <24>;
10729 +
10730 + panel-timing {
10731 + clock-frequency = <9200000>;
10732 + hactive = <480>;
10733 + vactive = <272>;
10734 + hfront-porch = <8>;
10735 + hback-porch = <4>;
10736 + hsync-len = <41>;
10737 + vback-porch = <2>;
10738 + vfront-porch = <4>;
10739 + vsync-len = <10>;
10740 +
10741 + hsync-active = <0>;
10742 + vsync-active = <0>;
10743 + de-active = <1>;
10744 + pixelclk-active = <1>;
10745 + };
10746 + };
10747 +};
10748 --- /dev/null
10749 +++ b/arch/arm/boot/dts/omap3xxx-clocks.dtsi
10750 @@ -0,0 +1,1513 @@
10751 +/*
10752 + * Device Tree Source for OMAP3 clock data
10753 + *
10754 + * Copyright (C) 2013 Texas Instruments, Inc.
10755 + *
10756 + * This program is free software; you can redistribute it and/or modify
10757 + * it under the terms of the GNU General Public License version 2 as
10758 + * published by the Free Software Foundation.
10759 + */
10760 +
10761 +dummy_apb_pclk: dummy_apb_pclk {
10762 + #clock-cells = <0>;
10763 + compatible = "fixed-clock";
10764 + clock-frequency = <0x0>;
10765 +};
10766 +
10767 +omap_32k_fck: omap_32k_fck {
10768 + #clock-cells = <0>;
10769 + compatible = "fixed-clock";
10770 + clock-frequency = <32768>;
10771 +};
10772 +
10773 +virt_12m_ck: virt_12m_ck {
10774 + #clock-cells = <0>;
10775 + compatible = "fixed-clock";
10776 + clock-frequency = <12000000>;
10777 +};
10778 +
10779 +virt_13m_ck: virt_13m_ck {
10780 + #clock-cells = <0>;
10781 + compatible = "fixed-clock";
10782 + clock-frequency = <13000000>;
10783 +};
10784 +
10785 +virt_19200000_ck: virt_19200000_ck {
10786 + #clock-cells = <0>;
10787 + compatible = "fixed-clock";
10788 + clock-frequency = <19200000>;
10789 +};
10790 +
10791 +virt_26000000_ck: virt_26000000_ck {
10792 + #clock-cells = <0>;
10793 + compatible = "fixed-clock";
10794 + clock-frequency = <26000000>;
10795 +};
10796 +
10797 +virt_38_4m_ck: virt_38_4m_ck {
10798 + #clock-cells = <0>;
10799 + compatible = "fixed-clock";
10800 + clock-frequency = <38400000>;
10801 +};
10802 +
10803 +virt_16_8m_ck: virt_16_8m_ck {
10804 + #clock-cells = <0>;
10805 + compatible = "fixed-clock";
10806 + clock-frequency = <16800000>;
10807 +};
10808 +
10809 +osc_sys_ck: osc_sys_ck@48306d40 {
10810 + #clock-cells = <0>;
10811 + compatible = "mux-clock";
10812 + clocks = <&virt_12m_ck>, <&virt_13m_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_38_4m_ck>, <&virt_16_8m_ck>;
10813 + reg = <0x48306d40 0x4>;
10814 + bit-mask = <0x7>;
10815 +};
10816 +
10817 +sys_ck: sys_ck@48307270 {
10818 + #clock-cells = <0>;
10819 + compatible = "divider-clock";
10820 + clocks = <&osc_sys_ck>;
10821 + bit-shift = <6>;
10822 + reg = <0x48307270 0x4>;
10823 + bit-mask = <0x3>;
10824 + index-starts-at-one;
10825 +};
10826 +
10827 +dpll4_ck: dpll4_ck@48004d00 {
10828 + #clock-cells = <0>;
10829 + compatible = "ti,omap3-dpll-per-clock";
10830 + clocks = <&sys_ck>, <&sys_ck>;
10831 + ti,modes = <0x82>;
10832 + reg-names = "control", "idlest", "autoidle", "mult-div1";
10833 + reg = <0x48004d00 0x4>, <0x48004d20 0x4>, <0x48004d30 0x4>, <0x48004d44 0x4>;
10834 +};
10835 +
10836 +dpll4_m2_ck: dpll4_m2_ck@48004d48 {
10837 + #clock-cells = <0>;
10838 + compatible = "divider-clock";
10839 + clocks = <&dpll4_ck>;
10840 + reg = <0x48004d48 0x4>;
10841 + bit-mask = <0x3f>;
10842 + index-starts-at-one;
10843 +};
10844 +
10845 +dpll4_m2x2_mul_ck: dpll4_m2x2_mul_ck {
10846 + #clock-cells = <0>;
10847 + compatible = "fixed-factor-clock";
10848 + clocks = <&dpll4_m2_ck>;
10849 + clock-mult = <2>;
10850 + clock-div = <1>;
10851 +};
10852 +
10853 +dpll4_m2x2_ck: dpll4_m2x2_ck@48004d00 {
10854 + #clock-cells = <0>;
10855 + compatible = "gate-clock";
10856 + clocks = <&dpll4_m2x2_mul_ck>;
10857 + bit-shift = <0x1b>;
10858 + reg = <0x48004d00 0x4>;
10859 + set-bit-to-disable;
10860 +};
10861 +
10862 +omap_96m_alwon_fck: omap_96m_alwon_fck {
10863 + #clock-cells = <0>;
10864 + compatible = "fixed-factor-clock";
10865 + clocks = <&dpll4_m2x2_ck>;
10866 + clock-mult = <1>;
10867 + clock-div = <1>;
10868 +};
10869 +
10870 +dpll3_ck: dpll3_ck@48004d00 {
10871 + #clock-cells = <0>;
10872 + compatible = "ti,omap3-dpll-core-clock";
10873 + clocks = <&sys_ck>, <&sys_ck>;
10874 + reg-names = "control", "idlest", "autoidle", "mult-div1";
10875 + reg = <0x48004d00 0x4>, <0x48004d20 0x4>, <0x48004d30 0x4>, <0x48004d40 0x4>;
10876 +};
10877 +
10878 +dpll3_m3_ck: dpll3_m3_ck@48005140 {
10879 + #clock-cells = <0>;
10880 + compatible = "divider-clock";
10881 + clocks = <&dpll3_ck>;
10882 + bit-shift = <16>;
10883 + reg = <0x48005140 0x4>;
10884 + bit-mask = <0x1f>;
10885 + index-starts-at-one;
10886 +};
10887 +
10888 +dpll3_m3x2_mul_ck: dpll3_m3x2_mul_ck {
10889 + #clock-cells = <0>;
10890 + compatible = "fixed-factor-clock";
10891 + clocks = <&dpll3_m3_ck>;
10892 + clock-mult = <2>;
10893 + clock-div = <1>;
10894 +};
10895 +
10896 +dpll3_m3x2_ck: dpll3_m3x2_ck@48004d00 {
10897 + #clock-cells = <0>;
10898 + compatible = "gate-clock";
10899 + clocks = <&dpll3_m3x2_mul_ck>;
10900 + bit-shift = <0xc>;
10901 + reg = <0x48004d00 0x4>;
10902 + set-bit-to-disable;
10903 +};
10904 +
10905 +emu_core_alwon_ck: emu_core_alwon_ck {
10906 + #clock-cells = <0>;
10907 + compatible = "fixed-factor-clock";
10908 + clocks = <&dpll3_m3x2_ck>;
10909 + clock-mult = <1>;
10910 + clock-div = <1>;
10911 +};
10912 +
10913 +sys_altclk: sys_altclk {
10914 + #clock-cells = <0>;
10915 + compatible = "fixed-clock";
10916 + clock-frequency = <0x0>;
10917 +};
10918 +
10919 +mcbsp_clks: mcbsp_clks {
10920 + #clock-cells = <0>;
10921 + compatible = "fixed-clock";
10922 + clock-frequency = <0x0>;
10923 +};
10924 +
10925 +sys_clkout1: sys_clkout1@48306d70 {
10926 + #clock-cells = <0>;
10927 + compatible = "gate-clock";
10928 + clocks = <&osc_sys_ck>;
10929 + reg = <0x48306d70 0x4>;
10930 + bit-shift = <7>;
10931 +};
10932 +
10933 +dpll3_m2_ck: dpll3_m2_ck@48004d40 {
10934 + #clock-cells = <0>;
10935 + compatible = "divider-clock";
10936 + clocks = <&dpll3_ck>;
10937 + bit-shift = <27>;
10938 + reg = <0x48004d40 0x4>;
10939 + bit-mask = <0x1f>;
10940 + index-starts-at-one;
10941 +};
10942 +
10943 +core_ck: core_ck {
10944 + #clock-cells = <0>;
10945 + compatible = "fixed-factor-clock";
10946 + clocks = <&dpll3_m2_ck>;
10947 + clock-mult = <1>;
10948 + clock-div = <1>;
10949 +};
10950 +
10951 +dpll1_fck: dpll1_fck@48004940 {
10952 + #clock-cells = <0>;
10953 + compatible = "divider-clock";
10954 + clocks = <&core_ck>;
10955 + bit-shift = <19>;
10956 + reg = <0x48004940 0x4>;
10957 + bit-mask = <0x7>;
10958 + index-starts-at-one;
10959 +};
10960 +
10961 +dpll1_ck: dpll1_ck@48004904 {
10962 + #clock-cells = <0>;
10963 + compatible = "ti,omap3-dpll-clock";
10964 + clocks = <&sys_ck>, <&dpll1_fck>;
10965 + reg-names = "control", "idlest", "autoidle", "mult-div1";
10966 + reg = <0x48004904 0x4>, <0x48004924 0x4>, <0x48004934 0x4>, <0x48004940 0x4>;
10967 +};
10968 +
10969 +dpll1_x2_ck: dpll1_x2_ck {
10970 + #clock-cells = <0>;
10971 + compatible = "fixed-factor-clock";
10972 + clocks = <&dpll1_ck>;
10973 + clock-mult = <2>;
10974 + clock-div = <1>;
10975 +};
10976 +
10977 +dpll1_x2m2_ck: dpll1_x2m2_ck@48004944 {
10978 + #clock-cells = <0>;
10979 + compatible = "divider-clock";
10980 + clocks = <&dpll1_x2_ck>;
10981 + reg = <0x48004944 0x4>;
10982 + bit-mask = <0x1f>;
10983 + index-starts-at-one;
10984 +};
10985 +
10986 +dpll3_x2_ck: dpll3_x2_ck {
10987 + #clock-cells = <0>;
10988 + compatible = "fixed-factor-clock";
10989 + clocks = <&dpll3_ck>;
10990 + clock-mult = <2>;
10991 + clock-div = <1>;
10992 +};
10993 +
10994 +dpll3_m2x2_ck: dpll3_m2x2_ck {
10995 + #clock-cells = <0>;
10996 + compatible = "fixed-factor-clock";
10997 + clocks = <&dpll3_m2_ck>;
10998 + clock-mult = <2>;
10999 + clock-div = <1>;
11000 +};
11001 +
11002 +dpll4_x2_ck: dpll4_x2_ck {
11003 + #clock-cells = <0>;
11004 + compatible = "fixed-factor-clock";
11005 + clocks = <&dpll4_ck>;
11006 + clock-mult = <2>;
11007 + clock-div = <1>;
11008 +};
11009 +
11010 +cm_96m_fck: cm_96m_fck {
11011 + #clock-cells = <0>;
11012 + compatible = "fixed-factor-clock";
11013 + clocks = <&omap_96m_alwon_fck>;
11014 + clock-mult = <1>;
11015 + clock-div = <1>;
11016 +};
11017 +
11018 +omap_96m_fck: omap_96m_fck@48004d40 {
11019 + #clock-cells = <0>;
11020 + compatible = "mux-clock";
11021 + clocks = <&cm_96m_fck>, <&sys_ck>;
11022 + bit-shift = <6>;
11023 + reg = <0x48004d40 0x4>;
11024 + bit-mask = <0x1>;
11025 +};
11026 +
11027 +dpll4_m3_ck: dpll4_m3_ck@48004e40 {
11028 + #clock-cells = <0>;
11029 + compatible = "divider-clock";
11030 + clocks = <&dpll4_ck>;
11031 + bit-shift = <8>;
11032 + reg = <0x48004e40 0x4>;
11033 + bit-mask = <0x3f>;
11034 + index-starts-at-one;
11035 +};
11036 +
11037 +dpll4_m3x2_mul_ck: dpll4_m3x2_mul_ck {
11038 + #clock-cells = <0>;
11039 + compatible = "fixed-factor-clock";
11040 + clocks = <&dpll4_m3_ck>;
11041 + clock-mult = <2>;
11042 + clock-div = <1>;
11043 +};
11044 +
11045 +dpll4_m3x2_ck: dpll4_m3x2_ck@48004d00 {
11046 + #clock-cells = <0>;
11047 + compatible = "gate-clock";
11048 + clocks = <&dpll4_m3x2_mul_ck>;
11049 + bit-shift = <0x1c>;
11050 + reg = <0x48004d00 0x4>;
11051 + set-bit-to-disable;
11052 +};
11053 +
11054 +omap_54m_fck: omap_54m_fck@48004d40 {
11055 + #clock-cells = <0>;
11056 + compatible = "mux-clock";
11057 + clocks = <&dpll4_m3x2_ck>, <&sys_altclk>;
11058 + bit-shift = <5>;
11059 + reg = <0x48004d40 0x4>;
11060 + bit-mask = <0x1>;
11061 +};
11062 +
11063 +cm_96m_d2_fck: cm_96m_d2_fck {
11064 + #clock-cells = <0>;
11065 + compatible = "fixed-factor-clock";
11066 + clocks = <&cm_96m_fck>;
11067 + clock-mult = <1>;
11068 + clock-div = <2>;
11069 +};
11070 +
11071 +omap_48m_fck: omap_48m_fck@48004d40 {
11072 + #clock-cells = <0>;
11073 + compatible = "mux-clock";
11074 + clocks = <&cm_96m_d2_fck>, <&sys_altclk>;
11075 + bit-shift = <3>;
11076 + reg = <0x48004d40 0x4>;
11077 + table = <&cm_96m_d2_fck 0>, <&sys_altclk 1>;
11078 + bit-mask = <0x1>;
11079 +};
11080 +
11081 +omap_12m_fck: omap_12m_fck {
11082 + #clock-cells = <0>;
11083 + compatible = "fixed-factor-clock";
11084 + clocks = <&omap_48m_fck>;
11085 + clock-mult = <1>;
11086 + clock-div = <4>;
11087 +};
11088 +
11089 +dpll4_m4_ck: dpll4_m4_ck@48004e40 {
11090 + #clock-cells = <0>;
11091 + compatible = "divider-clock";
11092 + clocks = <&dpll4_ck>;
11093 + reg = <0x48004e40 0x4>;
11094 + bit-mask = <0x3f>;
11095 + index-starts-at-one;
11096 +};
11097 +
11098 +dpll4_m4x2_mul_ck: dpll4_m4x2_mul_ck {
11099 + #clock-cells = <0>;
11100 + compatible = "fixed-factor-clock";
11101 + clocks = <&dpll4_m4_ck>;
11102 + clock-mult = <2>;
11103 + clock-div = <1>;
11104 +};
11105 +
11106 +dpll4_m4x2_ck: dpll4_m4x2_ck@48004d00 {
11107 + #clock-cells = <0>;
11108 + compatible = "gate-clock";
11109 + clocks = <&dpll4_m4x2_mul_ck>;
11110 + bit-shift = <0x1d>;
11111 + reg = <0x48004d00 0x4>;
11112 + set-bit-to-disable;
11113 +};
11114 +
11115 +dpll4_m5_ck: dpll4_m5_ck@48004f40 {
11116 + #clock-cells = <0>;
11117 + compatible = "divider-clock";
11118 + clocks = <&dpll4_ck>;
11119 + reg = <0x48004f40 0x4>;
11120 + bit-mask = <0x3f>;
11121 + index-starts-at-one;
11122 +};
11123 +
11124 +dpll4_m5x2_mul_ck: dpll4_m5x2_mul_ck {
11125 + #clock-cells = <0>;
11126 + compatible = "fixed-factor-clock";
11127 + clocks = <&dpll4_m5_ck>;
11128 + clock-mult = <2>;
11129 + clock-div = <1>;
11130 +};
11131 +
11132 +dpll4_m5x2_ck: dpll4_m5x2_ck@48004d00 {
11133 + #clock-cells = <0>;
11134 + compatible = "gate-clock";
11135 + clocks = <&dpll4_m5x2_mul_ck>;
11136 + bit-shift = <0x1e>;
11137 + reg = <0x48004d00 0x4>;
11138 + set-bit-to-disable;
11139 +};
11140 +
11141 +dpll4_m6_ck: dpll4_m6_ck@48005140 {
11142 + #clock-cells = <0>;
11143 + compatible = "divider-clock";
11144 + clocks = <&dpll4_ck>;
11145 + bit-shift = <24>;
11146 + reg = <0x48005140 0x4>;
11147 + bit-mask = <0x3f>;
11148 + index-starts-at-one;
11149 +};
11150 +
11151 +dpll4_m6x2_mul_ck: dpll4_m6x2_mul_ck {
11152 + #clock-cells = <0>;
11153 + compatible = "fixed-factor-clock";
11154 + clocks = <&dpll4_m6_ck>;
11155 + clock-mult = <2>;
11156 + clock-div = <1>;
11157 +};
11158 +
11159 +dpll4_m6x2_ck: dpll4_m6x2_ck@48004d00 {
11160 + #clock-cells = <0>;
11161 + compatible = "gate-clock";
11162 + clocks = <&dpll4_m6x2_mul_ck>;
11163 + bit-shift = <0x1f>;
11164 + reg = <0x48004d00 0x4>;
11165 + set-bit-to-disable;
11166 +};
11167 +
11168 +emu_per_alwon_ck: emu_per_alwon_ck {
11169 + #clock-cells = <0>;
11170 + compatible = "fixed-factor-clock";
11171 + clocks = <&dpll4_m6x2_ck>;
11172 + clock-mult = <1>;
11173 + clock-div = <1>;
11174 +};
11175 +
11176 +clkout2_src_mux_ck: clkout2_src_mux_ck@48004d70 {
11177 + #clock-cells = <0>;
11178 + compatible = "mux-clock";
11179 + clocks = <&core_ck>, <&sys_ck>, <&cm_96m_fck>, <&omap_54m_fck>;
11180 + reg = <0x48004d70 0x4>;
11181 + bit-mask = <0x3>;
11182 +};
11183 +
11184 +clkout2_src_ck: clkout2_src_ck@48004d70 {
11185 + #clock-cells = <0>;
11186 + compatible = "gate-clock";
11187 + clocks = <&clkout2_src_mux_ck>;
11188 + bit-shift = <7>;
11189 + reg = <0x48004d70 0x4>;
11190 +};
11191 +
11192 +sys_clkout2: sys_clkout2@48004d70 {
11193 + #clock-cells = <0>;
11194 + compatible = "divider-clock";
11195 + clocks = <&clkout2_src_ck>;
11196 + bit-shift = <3>;
11197 + reg = <0x48004d70 0x4>;
11198 + bit-mask = <0x7>;
11199 + index-power-of-two;
11200 +};
11201 +
11202 +corex2_fck: corex2_fck {
11203 + #clock-cells = <0>;
11204 + compatible = "fixed-factor-clock";
11205 + clocks = <&dpll3_m2x2_ck>;
11206 + clock-mult = <1>;
11207 + clock-div = <1>;
11208 +};
11209 +
11210 +mpu_ck: mpu_ck {
11211 + #clock-cells = <0>;
11212 + compatible = "fixed-factor-clock";
11213 + clocks = <&dpll1_x2m2_ck>;
11214 + clock-mult = <1>;
11215 + clock-div = <1>;
11216 +};
11217 +
11218 +arm_fck: arm_fck@48004924 {
11219 + #clock-cells = <0>;
11220 + compatible = "divider-clock";
11221 + clocks = <&mpu_ck>;
11222 + reg = <0x48004924 0x4>;
11223 + bit-mask = <0x1>;
11224 +};
11225 +
11226 +emu_mpu_alwon_ck: emu_mpu_alwon_ck {
11227 + #clock-cells = <0>;
11228 + compatible = "fixed-factor-clock";
11229 + clocks = <&mpu_ck>;
11230 + clock-mult = <1>;
11231 + clock-div = <1>;
11232 +};
11233 +
11234 +l3_ick: l3_ick@48004a40 {
11235 + #clock-cells = <0>;
11236 + compatible = "divider-clock";
11237 + clocks = <&core_ck>;
11238 + reg = <0x48004a40 0x4>;
11239 + bit-mask = <0x3>;
11240 + index-starts-at-one;
11241 +};
11242 +
11243 +l4_ick: l4_ick@48004a40 {
11244 + #clock-cells = <0>;
11245 + compatible = "divider-clock";
11246 + clocks = <&l3_ick>;
11247 + bit-shift = <2>;
11248 + reg = <0x48004a40 0x4>;
11249 + bit-mask = <0x3>;
11250 + index-starts-at-one;
11251 +};
11252 +
11253 +rm_ick: rm_ick@48004c40 {
11254 + #clock-cells = <0>;
11255 + compatible = "divider-clock";
11256 + clocks = <&l4_ick>;
11257 + bit-shift = <1>;
11258 + reg = <0x48004c40 0x4>;
11259 + bit-mask = <0x3>;
11260 + index-starts-at-one;
11261 +};
11262 +
11263 +gpt10_mux_fck: gpt10_mux_fck@48004a40 {
11264 + #clock-cells = <0>;
11265 + compatible = "mux-clock";
11266 + clocks = <&omap_32k_fck>, <&sys_ck>;
11267 + bit-shift = <6>;
11268 + reg = <0x48004a40 0x4>;
11269 + bit-mask = <0x1>;
11270 +};
11271 +
11272 +gpt10_fck: gpt10_fck@48004a00 {
11273 + #clock-cells = <0>;
11274 + compatible = "gate-clock";
11275 + clocks = <&gpt10_mux_fck>;
11276 + bit-shift = <11>;
11277 + reg = <0x48004a00 0x4>;
11278 +};
11279 +
11280 +gpt11_mux_fck: gpt11_mux_fck@48004a40 {
11281 + #clock-cells = <0>;
11282 + compatible = "mux-clock";
11283 + clocks = <&omap_32k_fck>, <&sys_ck>;
11284 + bit-shift = <7>;
11285 + reg = <0x48004a40 0x4>;
11286 + bit-mask = <0x1>;
11287 +};
11288 +
11289 +gpt11_fck: gpt11_fck@48004a00 {
11290 + #clock-cells = <0>;
11291 + compatible = "gate-clock";
11292 + clocks = <&gpt11_mux_fck>;
11293 + bit-shift = <12>;
11294 + reg = <0x48004a00 0x4>;
11295 +};
11296 +
11297 +core_96m_fck: core_96m_fck {
11298 + #clock-cells = <0>;
11299 + compatible = "fixed-factor-clock";
11300 + clocks = <&omap_96m_fck>;
11301 + clock-mult = <1>;
11302 + clock-div = <1>;
11303 +};
11304 +
11305 +mmchs2_fck: mmchs2_fck@48004a00 {
11306 + #clock-cells = <0>;
11307 + compatible = "ti,gate-clock";
11308 + clocks = <&core_96m_fck>;
11309 + reg = <0x48004a00 0x4>;
11310 + ti,enable-bit = <25>;
11311 +};
11312 +
11313 +mmchs1_fck: mmchs1_fck@48004a00 {
11314 + #clock-cells = <0>;
11315 + compatible = "ti,gate-clock";
11316 + clocks = <&core_96m_fck>;
11317 + reg = <0x48004a00 0x4>;
11318 + ti,enable-bit = <24>;
11319 +};
11320 +
11321 +i2c3_fck: i2c3_fck@48004a00 {
11322 + #clock-cells = <0>;
11323 + compatible = "ti,gate-clock";
11324 + clocks = <&core_96m_fck>;
11325 + reg = <0x48004a00 0x4>;
11326 + ti,enable-bit = <17>;
11327 +};
11328 +
11329 +i2c2_fck: i2c2_fck@48004a00 {
11330 + #clock-cells = <0>;
11331 + compatible = "ti,gate-clock";
11332 + clocks = <&core_96m_fck>;
11333 + reg = <0x48004a00 0x4>;
11334 + ti,enable-bit = <16>;
11335 +};
11336 +
11337 +i2c1_fck: i2c1_fck@48004a00 {
11338 + #clock-cells = <0>;
11339 + compatible = "ti,gate-clock";
11340 + clocks = <&core_96m_fck>;
11341 + reg = <0x48004a00 0x4>;
11342 + ti,enable-bit = <15>;
11343 +};
11344 +
11345 +mcbsp5_mux_fck: mcbsp5_mux_fck@480022d8 {
11346 + #clock-cells = <0>;
11347 + compatible = "mux-clock";
11348 + clocks = <&core_96m_fck>, <&mcbsp_clks>;
11349 + bit-shift = <4>;
11350 + reg = <0x480022d8 0x4>;
11351 + bit-mask = <0x1>;
11352 +};
11353 +
11354 +mcbsp5_fck: mcbsp5_fck@48004a00 {
11355 + #clock-cells = <0>;
11356 + compatible = "gate-clock";
11357 + clocks = <&mcbsp5_mux_fck>;
11358 + bit-shift = <10>;
11359 + reg = <0x48004a00 0x4>;
11360 +};
11361 +
11362 +mcbsp1_mux_fck: mcbsp1_mux_fck@48002274 {
11363 + #clock-cells = <0>;
11364 + compatible = "mux-clock";
11365 + clocks = <&core_96m_fck>, <&mcbsp_clks>;
11366 + bit-shift = <2>;
11367 + reg = <0x48002274 0x4>;
11368 + bit-mask = <0x1>;
11369 +};
11370 +
11371 +mcbsp1_fck: mcbsp1_fck@48004a00 {
11372 + #clock-cells = <0>;
11373 + compatible = "gate-clock";
11374 + clocks = <&mcbsp1_mux_fck>;
11375 + bit-shift = <9>;
11376 + reg = <0x48004a00 0x4>;
11377 +};
11378 +
11379 +core_48m_fck: core_48m_fck {
11380 + #clock-cells = <0>;
11381 + compatible = "fixed-factor-clock";
11382 + clocks = <&omap_48m_fck>;
11383 + clock-mult = <1>;
11384 + clock-div = <1>;
11385 +};
11386 +
11387 +mcspi4_fck: mcspi4_fck@48004a00 {
11388 + #clock-cells = <0>;
11389 + compatible = "ti,gate-clock";
11390 + clocks = <&core_48m_fck>;
11391 + reg = <0x48004a00 0x4>;
11392 + ti,enable-bit = <21>;
11393 +};
11394 +
11395 +mcspi3_fck: mcspi3_fck@48004a00 {
11396 + #clock-cells = <0>;
11397 + compatible = "ti,gate-clock";
11398 + clocks = <&core_48m_fck>;
11399 + reg = <0x48004a00 0x4>;
11400 + ti,enable-bit = <20>;
11401 +};
11402 +
11403 +mcspi2_fck: mcspi2_fck@48004a00 {
11404 + #clock-cells = <0>;
11405 + compatible = "ti,gate-clock";
11406 + clocks = <&core_48m_fck>;
11407 + reg = <0x48004a00 0x4>;
11408 + ti,enable-bit = <19>;
11409 +};
11410 +
11411 +mcspi1_fck: mcspi1_fck@48004a00 {
11412 + #clock-cells = <0>;
11413 + compatible = "ti,gate-clock";
11414 + clocks = <&core_48m_fck>;
11415 + reg = <0x48004a00 0x4>;
11416 + ti,enable-bit = <18>;
11417 +};
11418 +
11419 +uart2_fck: uart2_fck@48004a00 {
11420 + #clock-cells = <0>;
11421 + compatible = "ti,gate-clock";
11422 + clocks = <&core_48m_fck>;
11423 + reg = <0x48004a00 0x4>;
11424 + ti,enable-bit = <14>;
11425 +};
11426 +
11427 +uart1_fck: uart1_fck@48004a00 {
11428 + #clock-cells = <0>;
11429 + compatible = "ti,gate-clock";
11430 + clocks = <&core_48m_fck>;
11431 + reg = <0x48004a00 0x4>;
11432 + ti,enable-bit = <13>;
11433 +};
11434 +
11435 +core_12m_fck: core_12m_fck {
11436 + #clock-cells = <0>;
11437 + compatible = "fixed-factor-clock";
11438 + clocks = <&omap_12m_fck>;
11439 + clock-mult = <1>;
11440 + clock-div = <1>;
11441 +};
11442 +
11443 +hdq_fck: hdq_fck@48004a00 {
11444 + #clock-cells = <0>;
11445 + compatible = "ti,gate-clock";
11446 + clocks = <&core_12m_fck>;
11447 + reg = <0x48004a00 0x4>;
11448 + ti,enable-bit = <22>;
11449 +};
11450 +
11451 +core_l3_ick: core_l3_ick {
11452 + #clock-cells = <0>;
11453 + compatible = "fixed-factor-clock";
11454 + clocks = <&l3_ick>;
11455 + clock-mult = <1>;
11456 + clock-div = <1>;
11457 +};
11458 +
11459 +sdrc_ick: sdrc_ick@48004a10 {
11460 + #clock-cells = <0>;
11461 + compatible = "ti,gate-clock";
11462 + clocks = <&core_l3_ick>;
11463 + reg = <0x48004a10 0x4>;
11464 + ti,enable-bit = <1>;
11465 +};
11466 +
11467 +gpmc_fck: gpmc_fck {
11468 + #clock-cells = <0>;
11469 + compatible = "fixed-factor-clock";
11470 + clocks = <&core_l3_ick>;
11471 + clock-mult = <1>;
11472 + clock-div = <1>;
11473 +};
11474 +
11475 +core_l4_ick: core_l4_ick {
11476 + #clock-cells = <0>;
11477 + compatible = "fixed-factor-clock";
11478 + clocks = <&l4_ick>;
11479 + clock-mult = <1>;
11480 + clock-div = <1>;
11481 +};
11482 +
11483 +mmchs2_ick: mmchs2_ick@48004a10 {
11484 + #clock-cells = <0>;
11485 + compatible = "ti,omap3-interface-clock";
11486 + clocks = <&core_l4_ick>;
11487 + reg = <0x48004a10 0x4>;
11488 + ti,enable-bit = <25>;
11489 +};
11490 +
11491 +mmchs1_ick: mmchs1_ick@48004a10 {
11492 + #clock-cells = <0>;
11493 + compatible = "ti,omap3-interface-clock";
11494 + clocks = <&core_l4_ick>;
11495 + reg = <0x48004a10 0x4>;
11496 + ti,enable-bit = <24>;
11497 +};
11498 +
11499 +hdq_ick: hdq_ick@48004a10 {
11500 + #clock-cells = <0>;
11501 + compatible = "ti,omap3-interface-clock";
11502 + clocks = <&core_l4_ick>;
11503 + reg = <0x48004a10 0x4>;
11504 + ti,enable-bit = <22>;
11505 +};
11506 +
11507 +mcspi4_ick: mcspi4_ick@48004a10 {
11508 + #clock-cells = <0>;
11509 + compatible = "ti,omap3-interface-clock";
11510 + clocks = <&core_l4_ick>;
11511 + reg = <0x48004a10 0x4>;
11512 + ti,enable-bit = <21>;
11513 +};
11514 +
11515 +mcspi3_ick: mcspi3_ick@48004a10 {
11516 + #clock-cells = <0>;
11517 + compatible = "ti,omap3-interface-clock";
11518 + clocks = <&core_l4_ick>;
11519 + reg = <0x48004a10 0x4>;
11520 + ti,enable-bit = <20>;
11521 +};
11522 +
11523 +mcspi2_ick: mcspi2_ick@48004a10 {
11524 + #clock-cells = <0>;
11525 + compatible = "ti,omap3-interface-clock";
11526 + clocks = <&core_l4_ick>;
11527 + reg = <0x48004a10 0x4>;
11528 + ti,enable-bit = <19>;
11529 +};
11530 +
11531 +mcspi1_ick: mcspi1_ick@48004a10 {
11532 + #clock-cells = <0>;
11533 + compatible = "ti,omap3-interface-clock";
11534 + clocks = <&core_l4_ick>;
11535 + reg = <0x48004a10 0x4>;
11536 + ti,enable-bit = <18>;
11537 +};
11538 +
11539 +i2c3_ick: i2c3_ick@48004a10 {
11540 + #clock-cells = <0>;
11541 + compatible = "ti,omap3-interface-clock";
11542 + clocks = <&core_l4_ick>;
11543 + reg = <0x48004a10 0x4>;
11544 + ti,enable-bit = <17>;
11545 +};
11546 +
11547 +i2c2_ick: i2c2_ick@48004a10 {
11548 + #clock-cells = <0>;
11549 + compatible = "ti,omap3-interface-clock";
11550 + clocks = <&core_l4_ick>;
11551 + reg = <0x48004a10 0x4>;
11552 + ti,enable-bit = <16>;
11553 +};
11554 +
11555 +i2c1_ick: i2c1_ick@48004a10 {
11556 + #clock-cells = <0>;
11557 + compatible = "ti,omap3-interface-clock";
11558 + clocks = <&core_l4_ick>;
11559 + reg = <0x48004a10 0x4>;
11560 + ti,enable-bit = <15>;
11561 +};
11562 +
11563 +uart2_ick: uart2_ick@48004a10 {
11564 + #clock-cells = <0>;
11565 + compatible = "ti,omap3-interface-clock";
11566 + clocks = <&core_l4_ick>;
11567 + reg = <0x48004a10 0x4>;
11568 + ti,enable-bit = <14>;
11569 +};
11570 +
11571 +uart1_ick: uart1_ick@48004a10 {
11572 + #clock-cells = <0>;
11573 + compatible = "ti,omap3-interface-clock";
11574 + clocks = <&core_l4_ick>;
11575 + reg = <0x48004a10 0x4>;
11576 + ti,enable-bit = <13>;
11577 +};
11578 +
11579 +gpt11_ick: gpt11_ick@48004a10 {
11580 + #clock-cells = <0>;
11581 + compatible = "ti,omap3-interface-clock";
11582 + clocks = <&core_l4_ick>;
11583 + reg = <0x48004a10 0x4>;
11584 + ti,enable-bit = <12>;
11585 +};
11586 +
11587 +gpt10_ick: gpt10_ick@48004a10 {
11588 + #clock-cells = <0>;
11589 + compatible = "ti,omap3-interface-clock";
11590 + clocks = <&core_l4_ick>;
11591 + reg = <0x48004a10 0x4>;
11592 + ti,enable-bit = <11>;
11593 +};
11594 +
11595 +mcbsp5_ick: mcbsp5_ick@48004a10 {
11596 + #clock-cells = <0>;
11597 + compatible = "ti,omap3-interface-clock";
11598 + clocks = <&core_l4_ick>;
11599 + reg = <0x48004a10 0x4>;
11600 + ti,enable-bit = <10>;
11601 +};
11602 +
11603 +mcbsp1_ick: mcbsp1_ick@48004a10 {
11604 + #clock-cells = <0>;
11605 + compatible = "ti,omap3-interface-clock";
11606 + clocks = <&core_l4_ick>;
11607 + reg = <0x48004a10 0x4>;
11608 + ti,enable-bit = <9>;
11609 +};
11610 +
11611 +omapctrl_ick: omapctrl_ick@48004a10 {
11612 + #clock-cells = <0>;
11613 + compatible = "ti,omap3-interface-clock";
11614 + clocks = <&core_l4_ick>;
11615 + reg = <0x48004a10 0x4>;
11616 + ti,enable-bit = <6>;
11617 +};
11618 +
11619 +dss_tv_fck: dss_tv_fck@48004e00 {
11620 + #clock-cells = <0>;
11621 + compatible = "gate-clock";
11622 + clocks = <&omap_54m_fck>;
11623 + reg = <0x48004e00 0x4>;
11624 + bit-shift = <2>;
11625 +};
11626 +
11627 +dss_96m_fck: dss_96m_fck@48004e00 {
11628 + #clock-cells = <0>;
11629 + compatible = "gate-clock";
11630 + clocks = <&omap_96m_fck>;
11631 + reg = <0x48004e00 0x4>;
11632 + bit-shift = <2>;
11633 +};
11634 +
11635 +dss2_alwon_fck: dss2_alwon_fck@48004e00 {
11636 + #clock-cells = <0>;
11637 + compatible = "gate-clock";
11638 + clocks = <&sys_ck>;
11639 + reg = <0x48004e00 0x4>;
11640 + bit-shift = <1>;
11641 +};
11642 +
11643 +gpt1_mux_fck: gpt1_mux_fck@48004c40 {
11644 + #clock-cells = <0>;
11645 + compatible = "mux-clock";
11646 + clocks = <&omap_32k_fck>, <&sys_ck>;
11647 + reg = <0x48004c40 0x4>;
11648 + bit-mask = <0x1>;
11649 +};
11650 +
11651 +gpt1_fck: gpt1_fck@48004c00 {
11652 + #clock-cells = <0>;
11653 + compatible = "gate-clock";
11654 + clocks = <&gpt1_mux_fck>;
11655 + bit-shift = <0>;
11656 + reg = <0x48004c00 0x4>;
11657 +};
11658 +
11659 +aes2_ick: aes2_ick@48004a10 {
11660 + #clock-cells = <0>;
11661 + compatible = "ti,omap3-interface-clock";
11662 + clocks = <&core_l4_ick>;
11663 + reg = <0x48004a10 0x4>;
11664 + ti,enable-bit = <28>;
11665 +};
11666 +
11667 +wkup_32k_fck: wkup_32k_fck {
11668 + #clock-cells = <0>;
11669 + compatible = "fixed-factor-clock";
11670 + clocks = <&omap_32k_fck>;
11671 + clock-mult = <1>;
11672 + clock-div = <1>;
11673 +};
11674 +
11675 +gpio1_dbck: gpio1_dbck@48004c00 {
11676 + #clock-cells = <0>;
11677 + compatible = "gate-clock";
11678 + clocks = <&wkup_32k_fck>;
11679 + reg = <0x48004c00 0x4>;
11680 + bit-shift = <3>;
11681 +};
11682 +
11683 +sha12_ick: sha12_ick@48004a10 {
11684 + #clock-cells = <0>;
11685 + compatible = "ti,omap3-interface-clock";
11686 + clocks = <&core_l4_ick>;
11687 + reg = <0x48004a10 0x4>;
11688 + ti,enable-bit = <27>;
11689 +};
11690 +
11691 +wdt2_fck: wdt2_fck@48004c00 {
11692 + #clock-cells = <0>;
11693 + compatible = "ti,gate-clock";
11694 + clocks = <&wkup_32k_fck>;
11695 + reg = <0x48004c00 0x4>;
11696 + ti,enable-bit = <5>;
11697 +};
11698 +
11699 +wkup_l4_ick: wkup_l4_ick {
11700 + #clock-cells = <0>;
11701 + compatible = "fixed-factor-clock";
11702 + clocks = <&sys_ck>;
11703 + clock-mult = <1>;
11704 + clock-div = <1>;
11705 +};
11706 +
11707 +wdt2_ick: wdt2_ick@48004c10 {
11708 + #clock-cells = <0>;
11709 + compatible = "ti,omap3-interface-clock";
11710 + clocks = <&wkup_l4_ick>;
11711 + reg = <0x48004c10 0x4>;
11712 + ti,enable-bit = <5>;
11713 +};
11714 +
11715 +wdt1_ick: wdt1_ick@48004c10 {
11716 + #clock-cells = <0>;
11717 + compatible = "ti,omap3-interface-clock";
11718 + clocks = <&wkup_l4_ick>;
11719 + reg = <0x48004c10 0x4>;
11720 + ti,enable-bit = <4>;
11721 +};
11722 +
11723 +gpio1_ick: gpio1_ick@48004c10 {
11724 + #clock-cells = <0>;
11725 + compatible = "ti,omap3-interface-clock";
11726 + clocks = <&wkup_l4_ick>;
11727 + reg = <0x48004c10 0x4>;
11728 + ti,enable-bit = <3>;
11729 +};
11730 +
11731 +omap_32ksync_ick: omap_32ksync_ick@48004c10 {
11732 + #clock-cells = <0>;
11733 + compatible = "ti,omap3-interface-clock";
11734 + clocks = <&wkup_l4_ick>;
11735 + reg = <0x48004c10 0x4>;
11736 + ti,enable-bit = <2>;
11737 +};
11738 +
11739 +gpt12_ick: gpt12_ick@48004c10 {
11740 + #clock-cells = <0>;
11741 + compatible = "ti,omap3-interface-clock";
11742 + clocks = <&wkup_l4_ick>;
11743 + reg = <0x48004c10 0x4>;
11744 + ti,enable-bit = <1>;
11745 +};
11746 +
11747 +gpt1_ick: gpt1_ick@48004c10 {
11748 + #clock-cells = <0>;
11749 + compatible = "ti,omap3-interface-clock";
11750 + clocks = <&wkup_l4_ick>;
11751 + reg = <0x48004c10 0x4>;
11752 + ti,enable-bit = <0>;
11753 +};
11754 +
11755 +per_96m_fck: per_96m_fck {
11756 + #clock-cells = <0>;
11757 + compatible = "fixed-factor-clock";
11758 + clocks = <&omap_96m_alwon_fck>;
11759 + clock-mult = <1>;
11760 + clock-div = <1>;
11761 +};
11762 +
11763 +per_48m_fck: per_48m_fck {
11764 + #clock-cells = <0>;
11765 + compatible = "fixed-factor-clock";
11766 + clocks = <&omap_48m_fck>;
11767 + clock-mult = <1>;
11768 + clock-div = <1>;
11769 +};
11770 +
11771 +uart3_fck: uart3_fck@48005000 {
11772 + #clock-cells = <0>;
11773 + compatible = "ti,gate-clock";
11774 + clocks = <&per_48m_fck>;
11775 + reg = <0x48005000 0x4>;
11776 + ti,enable-bit = <11>;
11777 +};
11778 +
11779 +gpt2_mux_fck: gpt2_mux_fck@48005040 {
11780 + #clock-cells = <0>;
11781 + compatible = "mux-clock";
11782 + clocks = <&omap_32k_fck>, <&sys_ck>;
11783 + reg = <0x48005040 0x4>;
11784 + bit-mask = <0x1>;
11785 +};
11786 +
11787 +gpt2_fck: gpt2_fck@48005000 {
11788 + #clock-cells = <0>;
11789 + compatible = "gate-clock";
11790 + clocks = <&gpt2_mux_fck>;
11791 + bit-shift = <3>;
11792 + reg = <0x48005000 0x4>;
11793 +};
11794 +
11795 +gpt3_mux_fck: gpt3_mux_fck@48005040 {
11796 + #clock-cells = <0>;
11797 + compatible = "mux-clock";
11798 + clocks = <&omap_32k_fck>, <&sys_ck>;
11799 + bit-shift = <1>;
11800 + reg = <0x48005040 0x4>;
11801 + bit-mask = <0x1>;
11802 +};
11803 +
11804 +gpt3_fck: gpt3_fck@48005000 {
11805 + #clock-cells = <0>;
11806 + compatible = "gate-clock";
11807 + clocks = <&gpt3_mux_fck>;
11808 + bit-shift = <4>;
11809 + reg = <0x48005000 0x4>;
11810 +};
11811 +
11812 +gpt4_mux_fck: gpt4_mux_fck@48005040 {
11813 + #clock-cells = <0>;
11814 + compatible = "mux-clock";
11815 + clocks = <&omap_32k_fck>, <&sys_ck>;
11816 + bit-shift = <2>;
11817 + reg = <0x48005040 0x4>;
11818 + bit-mask = <0x1>;
11819 +};
11820 +
11821 +gpt4_fck: gpt4_fck@48005000 {
11822 + #clock-cells = <0>;
11823 + compatible = "gate-clock";
11824 + clocks = <&gpt4_mux_fck>;
11825 + bit-shift = <5>;
11826 + reg = <0x48005000 0x4>;
11827 +};
11828 +
11829 +gpt5_mux_fck: gpt5_mux_fck@48005040 {
11830 + #clock-cells = <0>;
11831 + compatible = "mux-clock";
11832 + clocks = <&omap_32k_fck>, <&sys_ck>;
11833 + bit-shift = <3>;
11834 + reg = <0x48005040 0x4>;
11835 + bit-mask = <0x1>;
11836 +};
11837 +
11838 +gpt5_fck: gpt5_fck@48005000 {
11839 + #clock-cells = <0>;
11840 + compatible = "gate-clock";
11841 + clocks = <&gpt5_mux_fck>;
11842 + bit-shift = <6>;
11843 + reg = <0x48005000 0x4>;
11844 +};
11845 +
11846 +gpt6_mux_fck: gpt6_mux_fck@48005040 {
11847 + #clock-cells = <0>;
11848 + compatible = "mux-clock";
11849 + clocks = <&omap_32k_fck>, <&sys_ck>;
11850 + bit-shift = <4>;
11851 + reg = <0x48005040 0x4>;
11852 + bit-mask = <0x1>;
11853 +};
11854 +
11855 +gpt6_fck: gpt6_fck@48005000 {
11856 + #clock-cells = <0>;
11857 + compatible = "gate-clock";
11858 + clocks = <&gpt6_mux_fck>;
11859 + bit-shift = <7>;
11860 + reg = <0x48005000 0x4>;
11861 +};
11862 +
11863 +gpt7_mux_fck: gpt7_mux_fck@48005040 {
11864 + #clock-cells = <0>;
11865 + compatible = "mux-clock";
11866 + clocks = <&omap_32k_fck>, <&sys_ck>;
11867 + bit-shift = <5>;
11868 + reg = <0x48005040 0x4>;
11869 + bit-mask = <0x1>;
11870 +};
11871 +
11872 +gpt7_fck: gpt7_fck@48005000 {
11873 + #clock-cells = <0>;
11874 + compatible = "gate-clock";
11875 + clocks = <&gpt7_mux_fck>;
11876 + bit-shift = <8>;
11877 + reg = <0x48005000 0x4>;
11878 +};
11879 +
11880 +gpt8_mux_fck: gpt8_mux_fck@48005040 {
11881 + #clock-cells = <0>;
11882 + compatible = "mux-clock";
11883 + clocks = <&omap_32k_fck>, <&sys_ck>;
11884 + bit-shift = <6>;
11885 + reg = <0x48005040 0x4>;
11886 + bit-mask = <0x1>;
11887 +};
11888 +
11889 +gpt8_fck: gpt8_fck@48005000 {
11890 + #clock-cells = <0>;
11891 + compatible = "gate-clock";
11892 + clocks = <&gpt8_mux_fck>;
11893 + bit-shift = <9>;
11894 + reg = <0x48005000 0x4>;
11895 +};
11896 +
11897 +gpt9_mux_fck: gpt9_mux_fck@48005040 {
11898 + #clock-cells = <0>;
11899 + compatible = "mux-clock";
11900 + clocks = <&omap_32k_fck>, <&sys_ck>;
11901 + bit-shift = <7>;
11902 + reg = <0x48005040 0x4>;
11903 + bit-mask = <0x1>;
11904 +};
11905 +
11906 +gpt9_fck: gpt9_fck@48005000 {
11907 + #clock-cells = <0>;
11908 + compatible = "gate-clock";
11909 + clocks = <&gpt9_mux_fck>;
11910 + bit-shift = <10>;
11911 + reg = <0x48005000 0x4>;
11912 +};
11913 +
11914 +per_32k_alwon_fck: per_32k_alwon_fck {
11915 + #clock-cells = <0>;
11916 + compatible = "fixed-factor-clock";
11917 + clocks = <&omap_32k_fck>;
11918 + clock-mult = <1>;
11919 + clock-div = <1>;
11920 +};
11921 +
11922 +gpio6_dbck: gpio6_dbck@48005000 {
11923 + #clock-cells = <0>;
11924 + compatible = "gate-clock";
11925 + clocks = <&per_32k_alwon_fck>;
11926 + reg = <0x48005000 0x4>;
11927 + bit-shift = <17>;
11928 +};
11929 +
11930 +gpio5_dbck: gpio5_dbck@48005000 {
11931 + #clock-cells = <0>;
11932 + compatible = "gate-clock";
11933 + clocks = <&per_32k_alwon_fck>;
11934 + reg = <0x48005000 0x4>;
11935 + bit-shift = <16>;
11936 +};
11937 +
11938 +gpio4_dbck: gpio4_dbck@48005000 {
11939 + #clock-cells = <0>;
11940 + compatible = "gate-clock";
11941 + clocks = <&per_32k_alwon_fck>;
11942 + reg = <0x48005000 0x4>;
11943 + bit-shift = <15>;
11944 +};
11945 +
11946 +gpio3_dbck: gpio3_dbck@48005000 {
11947 + #clock-cells = <0>;
11948 + compatible = "gate-clock";
11949 + clocks = <&per_32k_alwon_fck>;
11950 + reg = <0x48005000 0x4>;
11951 + bit-shift = <14>;
11952 +};
11953 +
11954 +gpio2_dbck: gpio2_dbck@48005000 {
11955 + #clock-cells = <0>;
11956 + compatible = "gate-clock";
11957 + clocks = <&per_32k_alwon_fck>;
11958 + reg = <0x48005000 0x4>;
11959 + bit-shift = <13>;
11960 +};
11961 +
11962 +wdt3_fck: wdt3_fck@48005000 {
11963 + #clock-cells = <0>;
11964 + compatible = "ti,gate-clock";
11965 + clocks = <&per_32k_alwon_fck>;
11966 + reg = <0x48005000 0x4>;
11967 + ti,enable-bit = <12>;
11968 +};
11969 +
11970 +per_l4_ick: per_l4_ick {
11971 + #clock-cells = <0>;
11972 + compatible = "fixed-factor-clock";
11973 + clocks = <&l4_ick>;
11974 + clock-mult = <1>;
11975 + clock-div = <1>;
11976 +};
11977 +
11978 +gpio6_ick: gpio6_ick@48005010 {
11979 + #clock-cells = <0>;
11980 + compatible = "ti,omap3-interface-clock";
11981 + clocks = <&per_l4_ick>;
11982 + reg = <0x48005010 0x4>;
11983 + ti,enable-bit = <17>;
11984 +};
11985 +
11986 +gpio5_ick: gpio5_ick@48005010 {
11987 + #clock-cells = <0>;
11988 + compatible = "ti,omap3-interface-clock";
11989 + clocks = <&per_l4_ick>;
11990 + reg = <0x48005010 0x4>;
11991 + ti,enable-bit = <16>;
11992 +};
11993 +
11994 +gpio4_ick: gpio4_ick@48005010 {
11995 + #clock-cells = <0>;
11996 + compatible = "ti,omap3-interface-clock";
11997 + clocks = <&per_l4_ick>;
11998 + reg = <0x48005010 0x4>;
11999 + ti,enable-bit = <15>;
12000 +};
12001 +
12002 +gpio3_ick: gpio3_ick@48005010 {
12003 + #clock-cells = <0>;
12004 + compatible = "ti,omap3-interface-clock";
12005 + clocks = <&per_l4_ick>;
12006 + reg = <0x48005010 0x4>;
12007 + ti,enable-bit = <14>;
12008 +};
12009 +
12010 +gpio2_ick: gpio2_ick@48005010 {
12011 + #clock-cells = <0>;
12012 + compatible = "ti,omap3-interface-clock";
12013 + clocks = <&per_l4_ick>;
12014 + reg = <0x48005010 0x4>;
12015 + ti,enable-bit = <13>;
12016 +};
12017 +
12018 +wdt3_ick: wdt3_ick@48005010 {
12019 + #clock-cells = <0>;
12020 + compatible = "ti,omap3-interface-clock";
12021 + clocks = <&per_l4_ick>;
12022 + reg = <0x48005010 0x4>;
12023 + ti,enable-bit = <12>;
12024 +};
12025 +
12026 +uart3_ick: uart3_ick@48005010 {
12027 + #clock-cells = <0>;
12028 + compatible = "ti,omap3-interface-clock";
12029 + clocks = <&per_l4_ick>;
12030 + reg = <0x48005010 0x4>;
12031 + ti,enable-bit = <11>;
12032 +};
12033 +
12034 +uart4_ick: uart4_ick@48005010 {
12035 + #clock-cells = <0>;
12036 + compatible = "ti,omap3-interface-clock";
12037 + clocks = <&per_l4_ick>;
12038 + reg = <0x48005010 0x4>;
12039 + ti,enable-bit = <18>;
12040 +};
12041 +
12042 +gpt9_ick: gpt9_ick@48005010 {
12043 + #clock-cells = <0>;
12044 + compatible = "ti,omap3-interface-clock";
12045 + clocks = <&per_l4_ick>;
12046 + reg = <0x48005010 0x4>;
12047 + ti,enable-bit = <10>;
12048 +};
12049 +
12050 +gpt8_ick: gpt8_ick@48005010 {
12051 + #clock-cells = <0>;
12052 + compatible = "ti,omap3-interface-clock";
12053 + clocks = <&per_l4_ick>;
12054 + reg = <0x48005010 0x4>;
12055 + ti,enable-bit = <9>;
12056 +};
12057 +
12058 +gpt7_ick: gpt7_ick@48005010 {
12059 + #clock-cells = <0>;
12060 + compatible = "ti,omap3-interface-clock";
12061 + clocks = <&per_l4_ick>;
12062 + reg = <0x48005010 0x4>;
12063 + ti,enable-bit = <8>;
12064 +};
12065 +
12066 +gpt6_ick: gpt6_ick@48005010 {
12067 + #clock-cells = <0>;
12068 + compatible = "ti,omap3-interface-clock";
12069 + clocks = <&per_l4_ick>;
12070 + reg = <0x48005010 0x4>;
12071 + ti,enable-bit = <7>;
12072 +};
12073 +
12074 +gpt5_ick: gpt5_ick@48005010 {
12075 + #clock-cells = <0>;
12076 + compatible = "ti,omap3-interface-clock";
12077 + clocks = <&per_l4_ick>;
12078 + reg = <0x48005010 0x4>;
12079 + ti,enable-bit = <6>;
12080 +};
12081 +
12082 +gpt4_ick: gpt4_ick@48005010 {
12083 + #clock-cells = <0>;
12084 + compatible = "ti,omap3-interface-clock";
12085 + clocks = <&per_l4_ick>;
12086 + reg = <0x48005010 0x4>;
12087 + ti,enable-bit = <5>;
12088 +};
12089 +
12090 +gpt3_ick: gpt3_ick@48005010 {
12091 + #clock-cells = <0>;
12092 + compatible = "ti,omap3-interface-clock";
12093 + clocks = <&per_l4_ick>;
12094 + reg = <0x48005010 0x4>;
12095 + ti,enable-bit = <4>;
12096 +};
12097 +
12098 +gpt2_ick: gpt2_ick@48005010 {
12099 + #clock-cells = <0>;
12100 + compatible = "ti,omap3-interface-clock";
12101 + clocks = <&per_l4_ick>;
12102 + reg = <0x48005010 0x4>;
12103 + ti,enable-bit = <3>;
12104 +};
12105 +
12106 +mcbsp2_ick: mcbsp2_ick@48005010 {
12107 + #clock-cells = <0>;
12108 + compatible = "ti,omap3-interface-clock";
12109 + clocks = <&per_l4_ick>;
12110 + reg = <0x48005010 0x4>;
12111 + ti,enable-bit = <0>;
12112 +};
12113 +
12114 +mcbsp3_ick: mcbsp3_ick@48005010 {
12115 + #clock-cells = <0>;
12116 + compatible = "ti,omap3-interface-clock";
12117 + clocks = <&per_l4_ick>;
12118 + reg = <0x48005010 0x4>;
12119 + ti,enable-bit = <1>;
12120 +};
12121 +
12122 +mcbsp4_ick: mcbsp4_ick@48005010 {
12123 + #clock-cells = <0>;
12124 + compatible = "ti,omap3-interface-clock";
12125 + clocks = <&per_l4_ick>;
12126 + reg = <0x48005010 0x4>;
12127 + ti,enable-bit = <2>;
12128 +};
12129 +
12130 +mcbsp2_mux_fck: mcbsp2_mux_fck@48002274 {
12131 + #clock-cells = <0>;
12132 + compatible = "mux-clock";
12133 + clocks = <&per_96m_fck>, <&mcbsp_clks>;
12134 + bit-shift = <6>;
12135 + reg = <0x48002274 0x4>;
12136 + bit-mask = <0x1>;
12137 +};
12138 +
12139 +mcbsp2_fck: mcbsp2_fck@48005000 {
12140 + #clock-cells = <0>;
12141 + compatible = "gate-clock";
12142 + clocks = <&mcbsp2_mux_fck>;
12143 + bit-shift = <0>;
12144 + reg = <0x48005000 0x4>;
12145 +};
12146 +
12147 +mcbsp3_mux_fck: mcbsp3_mux_fck@480022d8 {
12148 + #clock-cells = <0>;
12149 + compatible = "mux-clock";
12150 + clocks = <&per_96m_fck>, <&mcbsp_clks>;
12151 + reg = <0x480022d8 0x4>;
12152 + bit-mask = <0x1>;
12153 +};
12154 +
12155 +mcbsp3_fck: mcbsp3_fck@48005000 {
12156 + #clock-cells = <0>;
12157 + compatible = "gate-clock";
12158 + clocks = <&mcbsp3_mux_fck>;
12159 + bit-shift = <1>;
12160 + reg = <0x48005000 0x4>;
12161 +};
12162 +
12163 +mcbsp4_mux_fck: mcbsp4_mux_fck@480022d8 {
12164 + #clock-cells = <0>;
12165 + compatible = "mux-clock";
12166 + clocks = <&per_96m_fck>, <&mcbsp_clks>;
12167 + bit-shift = <2>;
12168 + reg = <0x480022d8 0x4>;
12169 + bit-mask = <0x1>;
12170 +};
12171 +
12172 +mcbsp4_fck: mcbsp4_fck@48005000 {
12173 + #clock-cells = <0>;
12174 + compatible = "gate-clock";
12175 + clocks = <&mcbsp4_mux_fck>;
12176 + bit-shift = <2>;
12177 + reg = <0x48005000 0x4>;
12178 +};
12179 +
12180 +emu_src_mux_ck: emu_src_mux_ck@48005140 {
12181 + #clock-cells = <0>;
12182 + compatible = "mux-clock";
12183 + clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>;
12184 + reg = <0x48005140 0x4>;
12185 + bit-mask = <0x3>;
12186 +};
12187 +
12188 +emu_src_ck: emu_src_ck {
12189 + #clock-cells = <0>;
12190 + compatible = "ti,clkdm-gate-clock";
12191 + clocks = <&emu_src_mux_ck>;
12192 +};
12193 +
12194 +pclk_fck: pclk_fck@48005140 {
12195 + #clock-cells = <0>;
12196 + compatible = "divider-clock";
12197 + clocks = <&emu_src_ck>;
12198 + bit-shift = <8>;
12199 + reg = <0x48005140 0x4>;
12200 + bit-mask = <0x7>;
12201 + index-starts-at-one;
12202 +};
12203 +
12204 +pclkx2_fck: pclkx2_fck@48005140 {
12205 + #clock-cells = <0>;
12206 + compatible = "divider-clock";
12207 + clocks = <&emu_src_ck>;
12208 + bit-shift = <6>;
12209 + reg = <0x48005140 0x4>;
12210 + bit-mask = <0x3>;
12211 + index-starts-at-one;
12212 +};
12213 +
12214 +atclk_fck: atclk_fck@48005140 {
12215 + #clock-cells = <0>;
12216 + compatible = "divider-clock";
12217 + clocks = <&emu_src_ck>;
12218 + bit-shift = <4>;
12219 + reg = <0x48005140 0x4>;
12220 + bit-mask = <0x3>;
12221 + index-starts-at-one;
12222 +};
12223 +
12224 +traceclk_src_fck: traceclk_src_fck@48005140 {
12225 + #clock-cells = <0>;
12226 + compatible = "mux-clock";
12227 + clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>;
12228 + bit-shift = <2>;
12229 + reg = <0x48005140 0x4>;
12230 + bit-mask = <0x3>;
12231 +};
12232 +
12233 +traceclk_fck: traceclk_fck@48005140 {
12234 + #clock-cells = <0>;
12235 + compatible = "divider-clock";
12236 + clocks = <&traceclk_src_fck>;
12237 + bit-shift = <11>;
12238 + reg = <0x48005140 0x4>;
12239 + bit-mask = <0x7>;
12240 + index-starts-at-one;
12241 +};
12242 +
12243 +secure_32k_fck: secure_32k_fck {
12244 + #clock-cells = <0>;
12245 + compatible = "fixed-clock";
12246 + clock-frequency = <32768>;
12247 +};
12248 +
12249 +gpt12_fck: gpt12_fck {
12250 + #clock-cells = <0>;
12251 + compatible = "fixed-factor-clock";
12252 + clocks = <&secure_32k_fck>;
12253 + clock-mult = <1>;
12254 + clock-div = <1>;
12255 +};
12256 +
12257 +wdt1_fck: wdt1_fck {
12258 + #clock-cells = <0>;
12259 + compatible = "fixed-factor-clock";
12260 + clocks = <&secure_32k_fck>;
12261 + clock-mult = <1>;
12262 + clock-div = <1>;
12263 +};
12264 --- /dev/null
12265 +++ b/arch/arm/boot/dts/omap443x-clocks.dtsi
12266 @@ -0,0 +1,17 @@
12267 +/*
12268 + * Device Tree Source for OMAP443x clock data
12269 + *
12270 + * Copyright (C) 2013 Texas Instruments, Inc.
12271 + *
12272 + * This program is free software; you can redistribute it and/or modify
12273 + * it under the terms of the GNU General Public License version 2 as
12274 + * published by the Free Software Foundation.
12275 + */
12276 +
12277 +bandgap_fclk: bandgap_fclk@4a307888 {
12278 + #clock-cells = <0>;
12279 + compatible = "gate-clock";
12280 + clocks = <&sys_32k_ck>;
12281 + bit-shift = <8>;
12282 + reg = <0x4a307888 0x4>;
12283 +};
12284 --- a/arch/arm/boot/dts/omap443x.dtsi
12285 +++ b/arch/arm/boot/dts/omap443x.dtsi
12286 @@ -30,4 +30,24 @@
12287 0x4a00232C 0x4>;
12288 compatible = "ti,omap4430-bandgap";
12289 };
12290 +
12291 + clocks {
12292 + #address-cells = <1>;
12293 + #size-cells = <1>;
12294 + ranges;
12295 + /include/ "omap44xx-clocks.dtsi"
12296 + /include/ "omap443x-clocks.dtsi"
12297 + };
12298 +
12299 + clockdomains {
12300 + l3_init_clkdm: l3_init_clkdm {
12301 + compatible = "ti,clockdomain";
12302 + clocks = <&dpll_usb_ck>;
12303 + };
12304 +
12305 + emu_sys_clkdm: emu_sys_clkdm {
12306 + compatible = "ti,clockdomain";
12307 + clocks = <&trace_clk_div_ck>;
12308 + };
12309 + };
12310 };
12311 --- a/arch/arm/boot/dts/omap4460.dtsi
12312 +++ b/arch/arm/boot/dts/omap4460.dtsi
12313 @@ -38,4 +38,24 @@
12314 interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>; /* talert */
12315 gpios = <&gpio3 22 0>; /* tshut */
12316 };
12317 +
12318 + clocks {
12319 + #address-cells = <1>;
12320 + #size-cells = <1>;
12321 + ranges;
12322 + /include/ "omap44xx-clocks.dtsi"
12323 + /include/ "omap446x-clocks.dtsi"
12324 + };
12325 +
12326 + clockdomains {
12327 + l3_init_clkdm: l3_init_clkdm {
12328 + compatible = "ti,clockdomain";
12329 + clocks = <&dpll_usb_ck>;
12330 + };
12331 +
12332 + emu_sys_clkdm: emu_sys_clkdm {
12333 + compatible = "ti,clockdomain";
12334 + clocks = <&trace_clk_div_ck>;
12335 + };
12336 + };
12337 };
12338 --- /dev/null
12339 +++ b/arch/arm/boot/dts/omap446x-clocks.dtsi
12340 @@ -0,0 +1,27 @@
12341 +/*
12342 + * Device Tree Source for OMAP446x clock data
12343 + *
12344 + * Copyright (C) 2013 Texas Instruments, Inc.
12345 + *
12346 + * This program is free software; you can redistribute it and/or modify
12347 + * it under the terms of the GNU General Public License version 2 as
12348 + * published by the Free Software Foundation.
12349 + */
12350 +
12351 +div_ts_ck: div_ts_ck@4a307888 {
12352 + #clock-cells = <0>;
12353 + compatible = "divider-clock";
12354 + clocks = <&l4_wkup_clk_mux_ck>;
12355 + bit-shift = <24>;
12356 + reg = <0x4a307888 0x4>;
12357 + table = < 8 0 >, < 16 1 >, < 32 2 >;
12358 + bit-mask = <0x3>;
12359 +};
12360 +
12361 +bandgap_ts_fclk: bandgap_ts_fclk@4a307888 {
12362 + #clock-cells = <0>;
12363 + compatible = "gate-clock";
12364 + clocks = <&div_ts_ck>;
12365 + bit-shift = <8>;
12366 + reg = <0x4a307888 0x4>;
12367 +};
12368 --- /dev/null
12369 +++ b/arch/arm/boot/dts/omap44xx-clocks.dtsi
12370 @@ -0,0 +1,1639 @@
12371 +/*
12372 + * Device Tree Source for OMAP4 clock data
12373 + *
12374 + * Copyright (C) 2013 Texas Instruments, Inc.
12375 + *
12376 + * This program is free software; you can redistribute it and/or modify
12377 + * it under the terms of the GNU General Public License version 2 as
12378 + * published by the Free Software Foundation.
12379 + */
12380 +
12381 +extalt_clkin_ck: extalt_clkin_ck {
12382 + #clock-cells = <0>;
12383 + compatible = "fixed-clock";
12384 + clock-frequency = <59000000>;
12385 +};
12386 +
12387 +pad_clks_src_ck: pad_clks_src_ck {
12388 + #clock-cells = <0>;
12389 + compatible = "fixed-clock";
12390 + clock-frequency = <12000000>;
12391 +};
12392 +
12393 +pad_clks_ck: pad_clks_ck@4a004108 {
12394 + #clock-cells = <0>;
12395 + compatible = "gate-clock";
12396 + clocks = <&pad_clks_src_ck>;
12397 + bit-shift = <8>;
12398 + reg = <0x4a004108 0x4>;
12399 +};
12400 +
12401 +pad_slimbus_core_clks_ck: pad_slimbus_core_clks_ck {
12402 + #clock-cells = <0>;
12403 + compatible = "fixed-clock";
12404 + clock-frequency = <12000000>;
12405 +};
12406 +
12407 +secure_32k_clk_src_ck: secure_32k_clk_src_ck {
12408 + #clock-cells = <0>;
12409 + compatible = "fixed-clock";
12410 + clock-frequency = <32768>;
12411 +};
12412 +
12413 +slimbus_src_clk: slimbus_src_clk {
12414 + #clock-cells = <0>;
12415 + compatible = "fixed-clock";
12416 + clock-frequency = <12000000>;
12417 +};
12418 +
12419 +slimbus_clk: slimbus_clk@4a004108 {
12420 + #clock-cells = <0>;
12421 + compatible = "gate-clock";
12422 + clocks = <&slimbus_src_clk>;
12423 + bit-shift = <10>;
12424 + reg = <0x4a004108 0x4>;
12425 +};
12426 +
12427 +sys_32k_ck: sys_32k_ck {
12428 + #clock-cells = <0>;
12429 + compatible = "fixed-clock";
12430 + clock-frequency = <32768>;
12431 +};
12432 +
12433 +virt_12000000_ck: virt_12000000_ck {
12434 + #clock-cells = <0>;
12435 + compatible = "fixed-clock";
12436 + clock-frequency = <12000000>;
12437 +};
12438 +
12439 +virt_13000000_ck: virt_13000000_ck {
12440 + #clock-cells = <0>;
12441 + compatible = "fixed-clock";
12442 + clock-frequency = <13000000>;
12443 +};
12444 +
12445 +virt_16800000_ck: virt_16800000_ck {
12446 + #clock-cells = <0>;
12447 + compatible = "fixed-clock";
12448 + clock-frequency = <16800000>;
12449 +};
12450 +
12451 +virt_19200000_ck: virt_19200000_ck {
12452 + #clock-cells = <0>;
12453 + compatible = "fixed-clock";
12454 + clock-frequency = <19200000>;
12455 +};
12456 +
12457 +virt_26000000_ck: virt_26000000_ck {
12458 + #clock-cells = <0>;
12459 + compatible = "fixed-clock";
12460 + clock-frequency = <26000000>;
12461 +};
12462 +
12463 +virt_27000000_ck: virt_27000000_ck {
12464 + #clock-cells = <0>;
12465 + compatible = "fixed-clock";
12466 + clock-frequency = <27000000>;
12467 +};
12468 +
12469 +virt_38400000_ck: virt_38400000_ck {
12470 + #clock-cells = <0>;
12471 + compatible = "fixed-clock";
12472 + clock-frequency = <38400000>;
12473 +};
12474 +
12475 +sys_clkin_ck: sys_clkin_ck@4a306110 {
12476 + #clock-cells = <0>;
12477 + compatible = "mux-clock";
12478 + clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
12479 + reg = <0x4a306110 0x4>;
12480 + bit-mask = <0x7>;
12481 + index-starts-at-one;
12482 +};
12483 +
12484 +tie_low_clock_ck: tie_low_clock_ck {
12485 + #clock-cells = <0>;
12486 + compatible = "fixed-clock";
12487 + clock-frequency = <0>;
12488 +};
12489 +
12490 +utmi_phy_clkout_ck: utmi_phy_clkout_ck {
12491 + #clock-cells = <0>;
12492 + compatible = "fixed-clock";
12493 + clock-frequency = <60000000>;
12494 +};
12495 +
12496 +xclk60mhsp1_ck: xclk60mhsp1_ck {
12497 + #clock-cells = <0>;
12498 + compatible = "fixed-clock";
12499 + clock-frequency = <60000000>;
12500 +};
12501 +
12502 +xclk60mhsp2_ck: xclk60mhsp2_ck {
12503 + #clock-cells = <0>;
12504 + compatible = "fixed-clock";
12505 + clock-frequency = <60000000>;
12506 +};
12507 +
12508 +xclk60motg_ck: xclk60motg_ck {
12509 + #clock-cells = <0>;
12510 + compatible = "fixed-clock";
12511 + clock-frequency = <60000000>;
12512 +};
12513 +
12514 +abe_dpll_bypass_clk_mux_ck: abe_dpll_bypass_clk_mux_ck@4a306108 {
12515 + #clock-cells = <0>;
12516 + compatible = "mux-clock";
12517 + clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
12518 + bit-shift = <24>;
12519 + reg = <0x4a306108 0x4>;
12520 + bit-mask = <0x1>;
12521 +};
12522 +
12523 +abe_dpll_refclk_mux_ck: abe_dpll_refclk_mux_ck@4a30610c {
12524 + #clock-cells = <0>;
12525 + compatible = "mux-clock";
12526 + clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
12527 + reg = <0x4a30610c 0x4>;
12528 + bit-mask = <0x1>;
12529 +};
12530 +
12531 +dpll_abe_ck: dpll_abe_ck@4a0041e0 {
12532 + #clock-cells = <0>;
12533 + compatible = "ti,omap4-dpll-m4xen-clock";
12534 + clocks = <&abe_dpll_refclk_mux_ck>, <&abe_dpll_bypass_clk_mux_ck>;
12535 + reg = <0x4a0041e0 0x4>, <0x4a0041e4 0x4>, <0x4a0041e8 0x4>, <0x4a0041ec 0x4>;
12536 + reg-names = "control", "idlest", "autoidle", "mult-div1";
12537 +};
12538 +
12539 +dpll_abe_x2_ck: dpll_abe_x2_ck@4a0041f0 {
12540 + #clock-cells = <0>;
12541 + compatible = "ti,omap4-dpll-x2-clock";
12542 + clocks = <&dpll_abe_ck>;
12543 + reg = <0x4a0041f0 0x4>;
12544 +};
12545 +
12546 +dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@4a0041f0 {
12547 + #clock-cells = <0>;
12548 + compatible = "ti,divider-clock";
12549 + clocks = <&dpll_abe_x2_ck>;
12550 + ti,autoidle-shift = <8>;
12551 + reg = <0x4a0041f0 0x4>;
12552 + bit-mask = <0x1f>;
12553 + index-starts-at-one;
12554 + ti,autoidle-low;
12555 +};
12556 +
12557 +abe_24m_fclk: abe_24m_fclk {
12558 + #clock-cells = <0>;
12559 + compatible = "fixed-factor-clock";
12560 + clocks = <&dpll_abe_m2x2_ck>;
12561 + clock-mult = <1>;
12562 + clock-div = <8>;
12563 +};
12564 +
12565 +abe_clk: abe_clk@4a004108 {
12566 + #clock-cells = <0>;
12567 + compatible = "divider-clock";
12568 + clocks = <&dpll_abe_m2x2_ck>;
12569 + reg = <0x4a004108 0x4>;
12570 + bit-mask = <0x3>;
12571 + index-power-of-two;
12572 +};
12573 +
12574 +aess_fclk: aess_fclk@4a004528 {
12575 + #clock-cells = <0>;
12576 + compatible = "divider-clock";
12577 + clocks = <&abe_clk>;
12578 + bit-shift = <24>;
12579 + reg = <0x4a004528 0x4>;
12580 + bit-mask = <0x1>;
12581 +};
12582 +
12583 +dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@4a0041f4 {
12584 + #clock-cells = <0>;
12585 + compatible = "ti,divider-clock";
12586 + clocks = <&dpll_abe_x2_ck>;
12587 + ti,autoidle-shift = <8>;
12588 + reg = <0x4a0041f4 0x4>;
12589 + bit-mask = <0x1f>;
12590 + index-starts-at-one;
12591 + ti,autoidle-low;
12592 +};
12593 +
12594 +core_hsd_byp_clk_mux_ck: core_hsd_byp_clk_mux_ck@4a00412c {
12595 + #clock-cells = <0>;
12596 + compatible = "mux-clock";
12597 + clocks = <&sys_clkin_ck>, <&dpll_abe_m3x2_ck>;
12598 + bit-shift = <23>;
12599 + reg = <0x4a00412c 0x4>;
12600 + bit-mask = <0x1>;
12601 +};
12602 +
12603 +dpll_core_ck: dpll_core_ck@4a004120 {
12604 + #clock-cells = <0>;
12605 + compatible = "ti,omap4-dpll-core-clock";
12606 + clocks = <&sys_clkin_ck>, <&core_hsd_byp_clk_mux_ck>;
12607 + reg = <0x4a004120 0x4>, <0x4a004124 0x4>, <0x4a004128 0x4>, <0x4a00412c 0x4>;
12608 + reg-names = "control", "idlest", "autoidle", "mult-div1";
12609 +};
12610 +
12611 +dpll_core_x2_ck: dpll_core_x2_ck {
12612 + #clock-cells = <0>;
12613 + compatible = "ti,omap4-dpll-x2-clock";
12614 + clocks = <&dpll_core_ck>;
12615 +};
12616 +
12617 +dpll_core_m6x2_ck: dpll_core_m6x2_ck@4a004140 {
12618 + #clock-cells = <0>;
12619 + compatible = "ti,divider-clock";
12620 + clocks = <&dpll_core_x2_ck>;
12621 + ti,autoidle-shift = <8>;
12622 + reg = <0x4a004140 0x4>;
12623 + bit-mask = <0x1f>;
12624 + index-starts-at-one;
12625 + ti,autoidle-low;
12626 +};
12627 +
12628 +dbgclk_mux_ck: dbgclk_mux_ck {
12629 + #clock-cells = <0>;
12630 + compatible = "fixed-factor-clock";
12631 + clocks = <&sys_clkin_ck>;
12632 + clock-mult = <1>;
12633 + clock-div = <1>;
12634 +};
12635 +
12636 +dpll_core_m2_ck: dpll_core_m2_ck@4a004130 {
12637 + #clock-cells = <0>;
12638 + compatible = "ti,divider-clock";
12639 + clocks = <&dpll_core_ck>;
12640 + ti,autoidle-shift = <8>;
12641 + reg = <0x4a004130 0x4>;
12642 + bit-mask = <0x1f>;
12643 + index-starts-at-one;
12644 + ti,autoidle-low;
12645 +};
12646 +
12647 +ddrphy_ck: ddrphy_ck {
12648 + #clock-cells = <0>;
12649 + compatible = "fixed-factor-clock";
12650 + clocks = <&dpll_core_m2_ck>;
12651 + clock-mult = <1>;
12652 + clock-div = <2>;
12653 +};
12654 +
12655 +dpll_core_m5x2_ck: dpll_core_m5x2_ck@4a00413c {
12656 + #clock-cells = <0>;
12657 + compatible = "ti,divider-clock";
12658 + clocks = <&dpll_core_x2_ck>;
12659 + ti,autoidle-shift = <8>;
12660 + reg = <0x4a00413c 0x4>;
12661 + bit-mask = <0x1f>;
12662 + index-starts-at-one;
12663 + ti,autoidle-low;
12664 +};
12665 +
12666 +div_core_ck: div_core_ck@4a004100 {
12667 + #clock-cells = <0>;
12668 + compatible = "divider-clock";
12669 + clocks = <&dpll_core_m5x2_ck>;
12670 + reg = <0x4a004100 0x4>;
12671 + bit-mask = <0x1>;
12672 +};
12673 +
12674 +div_iva_hs_clk: div_iva_hs_clk@4a0041dc {
12675 + #clock-cells = <0>;
12676 + compatible = "divider-clock";
12677 + clocks = <&dpll_core_m5x2_ck>;
12678 + reg = <0x4a0041dc 0x4>;
12679 + bit-mask = <0x3>;
12680 + index-power-of-two;
12681 +};
12682 +
12683 +div_mpu_hs_clk: div_mpu_hs_clk@4a00419c {
12684 + #clock-cells = <0>;
12685 + compatible = "divider-clock";
12686 + clocks = <&dpll_core_m5x2_ck>;
12687 + reg = <0x4a00419c 0x4>;
12688 + bit-mask = <0x3>;
12689 + index-power-of-two;
12690 +};
12691 +
12692 +dpll_core_m4x2_ck: dpll_core_m4x2_ck@4a004138 {
12693 + #clock-cells = <0>;
12694 + compatible = "ti,divider-clock";
12695 + clocks = <&dpll_core_x2_ck>;
12696 + ti,autoidle-shift = <8>;
12697 + reg = <0x4a004138 0x4>;
12698 + bit-mask = <0x1f>;
12699 + index-starts-at-one;
12700 + ti,autoidle-low;
12701 +};
12702 +
12703 +dll_clk_div_ck: dll_clk_div_ck {
12704 + #clock-cells = <0>;
12705 + compatible = "fixed-factor-clock";
12706 + clocks = <&dpll_core_m4x2_ck>;
12707 + clock-mult = <1>;
12708 + clock-div = <2>;
12709 +};
12710 +
12711 +dpll_abe_m2_ck: dpll_abe_m2_ck@4a0041f0 {
12712 + #clock-cells = <0>;
12713 + compatible = "divider-clock";
12714 + clocks = <&dpll_abe_ck>;
12715 + reg = <0x4a0041f0 0x4>;
12716 + bit-mask = <0x1f>;
12717 + index-starts-at-one;
12718 +};
12719 +
12720 +dpll_core_m3x2_div_ck: dpll_core_m3x2_div_ck@4a004134 {
12721 + #clock-cells = <0>;
12722 + compatible = "divider-clock";
12723 + clocks = <&dpll_core_x2_ck>;
12724 + reg = <0x4a004134 0x4>;
12725 + bit-mask = <0x1f>;
12726 + index-starts-at-one;
12727 +};
12728 +
12729 +dpll_core_m3x2_ck: dpll_core_m3x2_ck@4a004134 {
12730 + #clock-cells = <0>;
12731 + compatible = "gate-clock";
12732 + clocks = <&dpll_core_m3x2_div_ck>;
12733 + bit-shift = <8>;
12734 + reg = <0x4a004134 0x4>;
12735 +};
12736 +
12737 +dpll_core_m7x2_ck: dpll_core_m7x2_ck@4a004144 {
12738 + #clock-cells = <0>;
12739 + compatible = "ti,divider-clock";
12740 + clocks = <&dpll_core_x2_ck>;
12741 + ti,autoidle-shift = <8>;
12742 + reg = <0x4a004144 0x4>;
12743 + bit-mask = <0x1f>;
12744 + index-starts-at-one;
12745 + ti,autoidle-low;
12746 +};
12747 +
12748 +iva_hsd_byp_clk_mux_ck: iva_hsd_byp_clk_mux_ck@4a0041ac {
12749 + #clock-cells = <0>;
12750 + compatible = "mux-clock";
12751 + clocks = <&sys_clkin_ck>, <&div_iva_hs_clk>;
12752 + bit-shift = <23>;
12753 + reg = <0x4a0041ac 0x4>;
12754 + bit-mask = <0x1>;
12755 +};
12756 +
12757 +dpll_iva_ck: dpll_iva_ck@4a0041a0 {
12758 + #clock-cells = <0>;
12759 + compatible = "ti,omap4-dpll-clock";
12760 + clocks = <&sys_clkin_ck>, <&iva_hsd_byp_clk_mux_ck>;
12761 + reg = <0x4a0041a0 0x4>, <0x4a0041a4 0x4>, <0x4a0041a8 0x4>, <0x4a0041ac 0x4>;
12762 + reg-names = "control", "idlest", "autoidle", "mult-div1";
12763 +};
12764 +
12765 +dpll_iva_x2_ck: dpll_iva_x2_ck {
12766 + #clock-cells = <0>;
12767 + compatible = "ti,omap4-dpll-x2-clock";
12768 + clocks = <&dpll_iva_ck>;
12769 +};
12770 +
12771 +dpll_iva_m4x2_ck: dpll_iva_m4x2_ck@4a0041b8 {
12772 + #clock-cells = <0>;
12773 + compatible = "ti,divider-clock";
12774 + clocks = <&dpll_iva_x2_ck>;
12775 + ti,autoidle-shift = <8>;
12776 + reg = <0x4a0041b8 0x4>;
12777 + bit-mask = <0x1f>;
12778 + index-starts-at-one;
12779 + ti,autoidle-low;
12780 +};
12781 +
12782 +dpll_iva_m5x2_ck: dpll_iva_m5x2_ck@4a0041bc {
12783 + #clock-cells = <0>;
12784 + compatible = "ti,divider-clock";
12785 + clocks = <&dpll_iva_x2_ck>;
12786 + ti,autoidle-shift = <8>;
12787 + reg = <0x4a0041bc 0x4>;
12788 + bit-mask = <0x1f>;
12789 + index-starts-at-one;
12790 + ti,autoidle-low;
12791 +};
12792 +
12793 +dpll_mpu_ck: dpll_mpu_ck@4a004160 {
12794 + #clock-cells = <0>;
12795 + compatible = "ti,omap4-dpll-clock";
12796 + clocks = <&sys_clkin_ck>, <&div_mpu_hs_clk>;
12797 + reg = <0x4a004160 0x4>, <0x4a004164 0x4>, <0x4a004168 0x4>, <0x4a00416c 0x4>;
12798 + reg-names = "control", "idlest", "autoidle", "mult-div1";
12799 +};
12800 +
12801 +dpll_mpu_m2_ck: dpll_mpu_m2_ck@4a004170 {
12802 + #clock-cells = <0>;
12803 + compatible = "ti,divider-clock";
12804 + clocks = <&dpll_mpu_ck>;
12805 + ti,autoidle-shift = <8>;
12806 + reg = <0x4a004170 0x4>;
12807 + bit-mask = <0x1f>;
12808 + index-starts-at-one;
12809 + ti,autoidle-low;
12810 +};
12811 +
12812 +per_hs_clk_div_ck: per_hs_clk_div_ck {
12813 + #clock-cells = <0>;
12814 + compatible = "fixed-factor-clock";
12815 + clocks = <&dpll_abe_m3x2_ck>;
12816 + clock-mult = <1>;
12817 + clock-div = <2>;
12818 +};
12819 +
12820 +per_hsd_byp_clk_mux_ck: per_hsd_byp_clk_mux_ck@4a00814c {
12821 + #clock-cells = <0>;
12822 + compatible = "mux-clock";
12823 + clocks = <&sys_clkin_ck>, <&per_hs_clk_div_ck>;
12824 + bit-shift = <23>;
12825 + reg = <0x4a00814c 0x4>;
12826 + bit-mask = <0x1>;
12827 +};
12828 +
12829 +dpll_per_ck: dpll_per_ck@4a008140 {
12830 + #clock-cells = <0>;
12831 + compatible = "ti,omap4-dpll-clock";
12832 + clocks = <&sys_clkin_ck>, <&per_hsd_byp_clk_mux_ck>;
12833 + reg = <0x4a008140 0x4>, <0x4a008144 0x4>, <0x4a008148 0x4>, <0x4a00814c 0x4>;
12834 + reg-names = "control", "idlest", "autoidle", "mult-div1";
12835 +};
12836 +
12837 +dpll_per_m2_ck: dpll_per_m2_ck@4a008150 {
12838 + #clock-cells = <0>;
12839 + compatible = "divider-clock";
12840 + clocks = <&dpll_per_ck>;
12841 + reg = <0x4a008150 0x4>;
12842 + bit-mask = <0x1f>;
12843 + index-starts-at-one;
12844 +};
12845 +
12846 +dpll_per_x2_ck: dpll_per_x2_ck@4a008150 {
12847 + #clock-cells = <0>;
12848 + compatible = "ti,omap4-dpll-x2-clock";
12849 + clocks = <&dpll_per_ck>;
12850 + reg = <0x4a008150 0x4>;
12851 +};
12852 +
12853 +dpll_per_m2x2_ck: dpll_per_m2x2_ck@4a008150 {
12854 + #clock-cells = <0>;
12855 + compatible = "ti,divider-clock";
12856 + clocks = <&dpll_per_x2_ck>;
12857 + ti,autoidle-shift = <8>;
12858 + reg = <0x4a008150 0x4>;
12859 + bit-mask = <0x1f>;
12860 + index-starts-at-one;
12861 + ti,autoidle-low;
12862 +};
12863 +
12864 +dpll_per_m3x2_div_ck: dpll_per_m3x2_div_ck@4a008154 {
12865 + #clock-cells = <0>;
12866 + compatible = "divider-clock";
12867 + clocks = <&dpll_per_x2_ck>;
12868 + reg = <0x4a008154 0x4>;
12869 + bit-mask = <0x1f>;
12870 + index-starts-at-one;
12871 +};
12872 +
12873 +dpll_per_m3x2_ck: dpll_per_m3x2_ck@4a008154 {
12874 + #clock-cells = <0>;
12875 + compatible = "gate-clock";
12876 + clocks = <&dpll_per_m3x2_div_ck>;
12877 + bit-shift = <8>;
12878 + reg = <0x4a008154 0x4>;
12879 +};
12880 +
12881 +dpll_per_m4x2_ck: dpll_per_m4x2_ck@4a008158 {
12882 + #clock-cells = <0>;
12883 + compatible = "ti,divider-clock";
12884 + clocks = <&dpll_per_x2_ck>;
12885 + ti,autoidle-shift = <8>;
12886 + reg = <0x4a008158 0x4>;
12887 + bit-mask = <0x1f>;
12888 + index-starts-at-one;
12889 + ti,autoidle-low;
12890 +};
12891 +
12892 +dpll_per_m5x2_ck: dpll_per_m5x2_ck@4a00815c {
12893 + #clock-cells = <0>;
12894 + compatible = "ti,divider-clock";
12895 + clocks = <&dpll_per_x2_ck>;
12896 + ti,autoidle-shift = <8>;
12897 + reg = <0x4a00815c 0x4>;
12898 + bit-mask = <0x1f>;
12899 + index-starts-at-one;
12900 + ti,autoidle-low;
12901 +};
12902 +
12903 +dpll_per_m6x2_ck: dpll_per_m6x2_ck@4a008160 {
12904 + #clock-cells = <0>;
12905 + compatible = "ti,divider-clock";
12906 + clocks = <&dpll_per_x2_ck>;
12907 + ti,autoidle-shift = <8>;
12908 + reg = <0x4a008160 0x4>;
12909 + bit-mask = <0x1f>;
12910 + index-starts-at-one;
12911 + ti,autoidle-low;
12912 +};
12913 +
12914 +dpll_per_m7x2_ck: dpll_per_m7x2_ck@4a008164 {
12915 + #clock-cells = <0>;
12916 + compatible = "ti,divider-clock";
12917 + clocks = <&dpll_per_x2_ck>;
12918 + ti,autoidle-shift = <8>;
12919 + reg = <0x4a008164 0x4>;
12920 + bit-mask = <0x1f>;
12921 + index-starts-at-one;
12922 + ti,autoidle-low;
12923 +};
12924 +
12925 +usb_hs_clk_div_ck: usb_hs_clk_div_ck {
12926 + #clock-cells = <0>;
12927 + compatible = "fixed-factor-clock";
12928 + clocks = <&dpll_abe_m3x2_ck>;
12929 + clock-mult = <1>;
12930 + clock-div = <3>;
12931 +};
12932 +
12933 +dpll_usb_ck: dpll_usb_ck@4a008180 {
12934 + #clock-cells = <0>;
12935 + compatible = "ti,omap4-dpll-j-type-clock";
12936 + clocks = <&sys_clkin_ck>, <&usb_hs_clk_div_ck>;
12937 + reg = <0x4a008180 0x4>, <0x4a008184 0x4>, <0x4a008188 0x4>, <0x4a00818c 0x4>;
12938 + reg-names = "control", "idlest", "autoidle", "mult-div1";
12939 +};
12940 +
12941 +dpll_usb_clkdcoldo_ck: dpll_usb_clkdcoldo_ck@4a0081b4 {
12942 + #clock-cells = <0>;
12943 + compatible = "ti,fixed-factor-clock";
12944 + clocks = <&dpll_usb_ck>;
12945 + ti,autoidle-shift = <8>;
12946 + clock-div = <1>;
12947 + reg = <0x4a0081b4 0x4>;
12948 + clock-mult = <1>;
12949 + ti,autoidle-low;
12950 +};
12951 +
12952 +dpll_usb_m2_ck: dpll_usb_m2_ck@4a008190 {
12953 + #clock-cells = <0>;
12954 + compatible = "ti,divider-clock";
12955 + clocks = <&dpll_usb_ck>;
12956 + ti,autoidle-shift = <8>;
12957 + reg = <0x4a008190 0x4>;
12958 + bit-mask = <0x7f>;
12959 + index-starts-at-one;
12960 + ti,autoidle-low;
12961 +};
12962 +
12963 +ducati_clk_mux_ck: ducati_clk_mux_ck@4a008100 {
12964 + #clock-cells = <0>;
12965 + compatible = "mux-clock";
12966 + clocks = <&div_core_ck>, <&dpll_per_m6x2_ck>;
12967 + reg = <0x4a008100 0x4>;
12968 + bit-mask = <0x1>;
12969 +};
12970 +
12971 +func_12m_fclk: func_12m_fclk {
12972 + #clock-cells = <0>;
12973 + compatible = "fixed-factor-clock";
12974 + clocks = <&dpll_per_m2x2_ck>;
12975 + clock-mult = <1>;
12976 + clock-div = <16>;
12977 +};
12978 +
12979 +func_24m_clk: func_24m_clk {
12980 + #clock-cells = <0>;
12981 + compatible = "fixed-factor-clock";
12982 + clocks = <&dpll_per_m2_ck>;
12983 + clock-mult = <1>;
12984 + clock-div = <4>;
12985 +};
12986 +
12987 +func_24mc_fclk: func_24mc_fclk {
12988 + #clock-cells = <0>;
12989 + compatible = "fixed-factor-clock";
12990 + clocks = <&dpll_per_m2x2_ck>;
12991 + clock-mult = <1>;
12992 + clock-div = <8>;
12993 +};
12994 +
12995 +func_48m_fclk: func_48m_fclk@4a008108 {
12996 + #clock-cells = <0>;
12997 + compatible = "divider-clock";
12998 + clocks = <&dpll_per_m2x2_ck>;
12999 + reg = <0x4a008108 0x4>;
13000 + table = < 4 0 >, < 8 1 >;
13001 + bit-mask = <0x1>;
13002 +};
13003 +
13004 +func_48mc_fclk: func_48mc_fclk {
13005 + #clock-cells = <0>;
13006 + compatible = "fixed-factor-clock";
13007 + clocks = <&dpll_per_m2x2_ck>;
13008 + clock-mult = <1>;
13009 + clock-div = <4>;
13010 +};
13011 +
13012 +func_64m_fclk: func_64m_fclk@4a008108 {
13013 + #clock-cells = <0>;
13014 + compatible = "divider-clock";
13015 + clocks = <&dpll_per_m4x2_ck>;
13016 + reg = <0x4a008108 0x4>;
13017 + table = < 2 0 >, < 4 1 >;
13018 + bit-mask = <0x1>;
13019 +};
13020 +
13021 +func_96m_fclk: func_96m_fclk@4a008108 {
13022 + #clock-cells = <0>;
13023 + compatible = "divider-clock";
13024 + clocks = <&dpll_per_m2x2_ck>;
13025 + reg = <0x4a008108 0x4>;
13026 + table = < 2 0 >, < 4 1 >;
13027 + bit-mask = <0x1>;
13028 +};
13029 +
13030 +init_60m_fclk: init_60m_fclk@4a008104 {
13031 + #clock-cells = <0>;
13032 + compatible = "divider-clock";
13033 + clocks = <&dpll_usb_m2_ck>;
13034 + reg = <0x4a008104 0x4>;
13035 + table = < 1 0 >, < 8 1 >;
13036 + bit-mask = <0x1>;
13037 +};
13038 +
13039 +l3_div_ck: l3_div_ck@4a004100 {
13040 + #clock-cells = <0>;
13041 + compatible = "divider-clock";
13042 + clocks = <&div_core_ck>;
13043 + bit-shift = <4>;
13044 + reg = <0x4a004100 0x4>;
13045 + bit-mask = <0x1>;
13046 +};
13047 +
13048 +l4_div_ck: l4_div_ck@4a004100 {
13049 + #clock-cells = <0>;
13050 + compatible = "divider-clock";
13051 + clocks = <&l3_div_ck>;
13052 + bit-shift = <8>;
13053 + reg = <0x4a004100 0x4>;
13054 + bit-mask = <0x1>;
13055 +};
13056 +
13057 +lp_clk_div_ck: lp_clk_div_ck {
13058 + #clock-cells = <0>;
13059 + compatible = "fixed-factor-clock";
13060 + clocks = <&dpll_abe_m2x2_ck>;
13061 + clock-mult = <1>;
13062 + clock-div = <16>;
13063 +};
13064 +
13065 +l4_wkup_clk_mux_ck: l4_wkup_clk_mux_ck@4a306108 {
13066 + #clock-cells = <0>;
13067 + compatible = "mux-clock";
13068 + clocks = <&sys_clkin_ck>, <&lp_clk_div_ck>;
13069 + reg = <0x4a306108 0x4>;
13070 + bit-mask = <0x1>;
13071 +};
13072 +
13073 +mpu_periphclk: mpu_periphclk {
13074 + #clock-cells = <0>;
13075 + compatible = "fixed-factor-clock";
13076 + clocks = <&dpll_mpu_ck>;
13077 + clock-mult = <1>;
13078 + clock-div = <2>;
13079 +};
13080 +
13081 +ocp_abe_iclk: ocp_abe_iclk@4a004528 {
13082 + #clock-cells = <0>;
13083 + compatible = "divider-clock";
13084 + clocks = <&aess_fclk>;
13085 + bit-shift = <24>;
13086 + reg = <0x4a004528 0x4>;
13087 + table = < 2 0 >, < 1 1 >;
13088 + bit-mask = <0x1>;
13089 +};
13090 +
13091 +per_abe_24m_fclk: per_abe_24m_fclk {
13092 + #clock-cells = <0>;
13093 + compatible = "fixed-factor-clock";
13094 + clocks = <&dpll_abe_m2_ck>;
13095 + clock-mult = <1>;
13096 + clock-div = <4>;
13097 +};
13098 +
13099 +per_abe_nc_fclk: per_abe_nc_fclk@4a008108 {
13100 + #clock-cells = <0>;
13101 + compatible = "divider-clock";
13102 + clocks = <&dpll_abe_m2_ck>;
13103 + reg = <0x4a008108 0x4>;
13104 + bit-mask = <0x1>;
13105 +};
13106 +
13107 +syc_clk_div_ck: syc_clk_div_ck@4a306100 {
13108 + #clock-cells = <0>;
13109 + compatible = "divider-clock";
13110 + clocks = <&sys_clkin_ck>;
13111 + reg = <0x4a306100 0x4>;
13112 + bit-mask = <0x1>;
13113 +};
13114 +
13115 +aes1_fck: aes1_fck@4a0095a0 {
13116 + #clock-cells = <0>;
13117 + compatible = "gate-clock";
13118 + clocks = <&l3_div_ck>;
13119 + bit-shift = <1>;
13120 + reg = <0x4a0095a0 0x4>;
13121 +};
13122 +
13123 +aes2_fck: aes2_fck@4a0095a8 {
13124 + #clock-cells = <0>;
13125 + compatible = "gate-clock";
13126 + clocks = <&l3_div_ck>;
13127 + bit-shift = <1>;
13128 + reg = <0x4a0095a8 0x4>;
13129 +};
13130 +
13131 +dmic_sync_mux_ck: dmic_sync_mux_ck@4a004538 {
13132 + #clock-cells = <0>;
13133 + compatible = "mux-clock";
13134 + clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>;
13135 + bit-shift = <25>;
13136 + reg = <0x4a004538 0x4>;
13137 + bit-mask = <0x1>;
13138 +};
13139 +
13140 +func_dmic_abe_gfclk: func_dmic_abe_gfclk@4a004538 {
13141 + #clock-cells = <0>;
13142 + compatible = "mux-clock";
13143 + clocks = <&dmic_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
13144 + bit-shift = <24>;
13145 + reg = <0x4a004538 0x4>;
13146 + bit-mask = <0x3>;
13147 +};
13148 +
13149 +dss_sys_clk: dss_sys_clk@4a009120 {
13150 + #clock-cells = <0>;
13151 + compatible = "gate-clock";
13152 + clocks = <&syc_clk_div_ck>;
13153 + bit-shift = <10>;
13154 + reg = <0x4a009120 0x4>;
13155 +};
13156 +
13157 +dss_tv_clk: dss_tv_clk@4a009120 {
13158 + #clock-cells = <0>;
13159 + compatible = "gate-clock";
13160 + clocks = <&extalt_clkin_ck>;
13161 + bit-shift = <11>;
13162 + reg = <0x4a009120 0x4>;
13163 +};
13164 +
13165 +dss_dss_clk: dss_dss_clk@4a009120 {
13166 + #clock-cells = <0>;
13167 + compatible = "gate-clock";
13168 + clocks = <&dpll_per_m5x2_ck>;
13169 + bit-shift = <8>;
13170 + reg = <0x4a009120 0x4>;
13171 +};
13172 +
13173 +dss_48mhz_clk: dss_48mhz_clk@4a009120 {
13174 + #clock-cells = <0>;
13175 + compatible = "gate-clock";
13176 + clocks = <&func_48mc_fclk>;
13177 + bit-shift = <9>;
13178 + reg = <0x4a009120 0x4>;
13179 +};
13180 +
13181 +dss_fck: dss_fck@4a009120 {
13182 + #clock-cells = <0>;
13183 + compatible = "gate-clock";
13184 + clocks = <&l3_div_ck>;
13185 + bit-shift = <1>;
13186 + reg = <0x4a009120 0x4>;
13187 +};
13188 +
13189 +fdif_fck: fdif_fck@4a009028 {
13190 + #clock-cells = <0>;
13191 + compatible = "divider-clock";
13192 + clocks = <&dpll_per_m4x2_ck>;
13193 + bit-shift = <24>;
13194 + reg = <0x4a009028 0x4>;
13195 + bit-mask = <0x3>;
13196 + index-power-of-two;
13197 +};
13198 +
13199 +gpio1_dbclk: gpio1_dbclk@4a307838 {
13200 + #clock-cells = <0>;
13201 + compatible = "gate-clock";
13202 + clocks = <&sys_32k_ck>;
13203 + bit-shift = <8>;
13204 + reg = <0x4a307838 0x4>;
13205 +};
13206 +
13207 +gpio2_dbclk: gpio2_dbclk@4a009460 {
13208 + #clock-cells = <0>;
13209 + compatible = "gate-clock";
13210 + clocks = <&sys_32k_ck>;
13211 + bit-shift = <8>;
13212 + reg = <0x4a009460 0x4>;
13213 +};
13214 +
13215 +gpio3_dbclk: gpio3_dbclk@4a009468 {
13216 + #clock-cells = <0>;
13217 + compatible = "gate-clock";
13218 + clocks = <&sys_32k_ck>;
13219 + bit-shift = <8>;
13220 + reg = <0x4a009468 0x4>;
13221 +};
13222 +
13223 +gpio4_dbclk: gpio4_dbclk@4a009470 {
13224 + #clock-cells = <0>;
13225 + compatible = "gate-clock";
13226 + clocks = <&sys_32k_ck>;
13227 + bit-shift = <8>;
13228 + reg = <0x4a009470 0x4>;
13229 +};
13230 +
13231 +gpio5_dbclk: gpio5_dbclk@4a009478 {
13232 + #clock-cells = <0>;
13233 + compatible = "gate-clock";
13234 + clocks = <&sys_32k_ck>;
13235 + bit-shift = <8>;
13236 + reg = <0x4a009478 0x4>;
13237 +};
13238 +
13239 +gpio6_dbclk: gpio6_dbclk@4a009480 {
13240 + #clock-cells = <0>;
13241 + compatible = "gate-clock";
13242 + clocks = <&sys_32k_ck>;
13243 + bit-shift = <8>;
13244 + reg = <0x4a009480 0x4>;
13245 +};
13246 +
13247 +sgx_clk_mux: sgx_clk_mux@4a009220 {
13248 + #clock-cells = <0>;
13249 + compatible = "mux-clock";
13250 + clocks = <&dpll_core_m7x2_ck>, <&dpll_per_m7x2_ck>;
13251 + bit-shift = <24>;
13252 + reg = <0x4a009220 0x4>;
13253 + bit-mask = <0x1>;
13254 +};
13255 +
13256 +hsi_fck: hsi_fck@4a009338 {
13257 + #clock-cells = <0>;
13258 + compatible = "divider-clock";
13259 + clocks = <&dpll_per_m2x2_ck>;
13260 + bit-shift = <24>;
13261 + reg = <0x4a009338 0x4>;
13262 + bit-mask = <0x3>;
13263 + index-power-of-two;
13264 +};
13265 +
13266 +iss_ctrlclk: iss_ctrlclk@4a009020 {
13267 + #clock-cells = <0>;
13268 + compatible = "gate-clock";
13269 + clocks = <&func_96m_fclk>;
13270 + bit-shift = <8>;
13271 + reg = <0x4a009020 0x4>;
13272 +};
13273 +
13274 +mcasp_sync_mux_ck: mcasp_sync_mux_ck@4a004540 {
13275 + #clock-cells = <0>;
13276 + compatible = "mux-clock";
13277 + clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>;
13278 + bit-shift = <25>;
13279 + reg = <0x4a004540 0x4>;
13280 + bit-mask = <0x1>;
13281 +};
13282 +
13283 +func_mcasp_abe_gfclk: func_mcasp_abe_gfclk@4a004540 {
13284 + #clock-cells = <0>;
13285 + compatible = "mux-clock";
13286 + clocks = <&mcasp_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
13287 + bit-shift = <24>;
13288 + reg = <0x4a004540 0x4>;
13289 + bit-mask = <0x3>;
13290 +};
13291 +
13292 +mcbsp1_sync_mux_ck: mcbsp1_sync_mux_ck@4a004548 {
13293 + #clock-cells = <0>;
13294 + compatible = "mux-clock";
13295 + clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>;
13296 + bit-shift = <25>;
13297 + reg = <0x4a004548 0x4>;
13298 + bit-mask = <0x1>;
13299 +};
13300 +
13301 +func_mcbsp1_gfclk: func_mcbsp1_gfclk@4a004548 {
13302 + #clock-cells = <0>;
13303 + compatible = "mux-clock";
13304 + clocks = <&mcbsp1_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
13305 + bit-shift = <24>;
13306 + reg = <0x4a004548 0x4>;
13307 + bit-mask = <0x3>;
13308 +};
13309 +
13310 +mcbsp2_sync_mux_ck: mcbsp2_sync_mux_ck@4a004550 {
13311 + #clock-cells = <0>;
13312 + compatible = "mux-clock";
13313 + clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>;
13314 + bit-shift = <25>;
13315 + reg = <0x4a004550 0x4>;
13316 + bit-mask = <0x1>;
13317 +};
13318 +
13319 +func_mcbsp2_gfclk: func_mcbsp2_gfclk@4a004550 {
13320 + #clock-cells = <0>;
13321 + compatible = "mux-clock";
13322 + clocks = <&mcbsp2_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
13323 + bit-shift = <24>;
13324 + reg = <0x4a004550 0x4>;
13325 + bit-mask = <0x3>;
13326 +};
13327 +
13328 +mcbsp3_sync_mux_ck: mcbsp3_sync_mux_ck@4a004558 {
13329 + #clock-cells = <0>;
13330 + compatible = "mux-clock";
13331 + clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>;
13332 + bit-shift = <25>;
13333 + reg = <0x4a004558 0x4>;
13334 + bit-mask = <0x1>;
13335 +};
13336 +
13337 +func_mcbsp3_gfclk: func_mcbsp3_gfclk@4a004558 {
13338 + #clock-cells = <0>;
13339 + compatible = "mux-clock";
13340 + clocks = <&mcbsp3_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
13341 + bit-shift = <24>;
13342 + reg = <0x4a004558 0x4>;
13343 + bit-mask = <0x3>;
13344 +};
13345 +
13346 +mcbsp4_sync_mux_ck: mcbsp4_sync_mux_ck@4a0094e0 {
13347 + #clock-cells = <0>;
13348 + compatible = "mux-clock";
13349 + clocks = <&func_96m_fclk>, <&per_abe_nc_fclk>;
13350 + bit-shift = <25>;
13351 + reg = <0x4a0094e0 0x4>;
13352 + bit-mask = <0x1>;
13353 +};
13354 +
13355 +per_mcbsp4_gfclk: per_mcbsp4_gfclk@4a0094e0 {
13356 + #clock-cells = <0>;
13357 + compatible = "mux-clock";
13358 + clocks = <&mcbsp4_sync_mux_ck>, <&pad_clks_ck>;
13359 + bit-shift = <24>;
13360 + reg = <0x4a0094e0 0x4>;
13361 + bit-mask = <0x1>;
13362 +};
13363 +
13364 +hsmmc1_fclk: hsmmc1_fclk@4a009328 {
13365 + #clock-cells = <0>;
13366 + compatible = "mux-clock";
13367 + clocks = <&func_64m_fclk>, <&func_96m_fclk>;
13368 + bit-shift = <24>;
13369 + reg = <0x4a009328 0x4>;
13370 + bit-mask = <0x1>;
13371 +};
13372 +
13373 +hsmmc2_fclk: hsmmc2_fclk@4a009330 {
13374 + #clock-cells = <0>;
13375 + compatible = "mux-clock";
13376 + clocks = <&func_64m_fclk>, <&func_96m_fclk>;
13377 + bit-shift = <24>;
13378 + reg = <0x4a009330 0x4>;
13379 + bit-mask = <0x1>;
13380 +};
13381 +
13382 +ocp2scp_usb_phy_phy_48m: ocp2scp_usb_phy_phy_48m@4a0093e0 {
13383 + #clock-cells = <0>;
13384 + compatible = "gate-clock";
13385 + clocks = <&func_48m_fclk>;
13386 + bit-shift = <8>;
13387 + reg = <0x4a0093e0 0x4>;
13388 +};
13389 +
13390 +sha2md5_fck: sha2md5_fck@4a0095c8 {
13391 + #clock-cells = <0>;
13392 + compatible = "gate-clock";
13393 + clocks = <&l3_div_ck>;
13394 + bit-shift = <1>;
13395 + reg = <0x4a0095c8 0x4>;
13396 +};
13397 +
13398 +slimbus1_fclk_1: slimbus1_fclk_1@4a004560 {
13399 + #clock-cells = <0>;
13400 + compatible = "gate-clock";
13401 + clocks = <&func_24m_clk>;
13402 + bit-shift = <9>;
13403 + reg = <0x4a004560 0x4>;
13404 +};
13405 +
13406 +slimbus1_fclk_0: slimbus1_fclk_0@4a004560 {
13407 + #clock-cells = <0>;
13408 + compatible = "gate-clock";
13409 + clocks = <&abe_24m_fclk>;
13410 + bit-shift = <8>;
13411 + reg = <0x4a004560 0x4>;
13412 +};
13413 +
13414 +slimbus1_fclk_2: slimbus1_fclk_2@4a004560 {
13415 + #clock-cells = <0>;
13416 + compatible = "gate-clock";
13417 + clocks = <&pad_clks_ck>;
13418 + bit-shift = <10>;
13419 + reg = <0x4a004560 0x4>;
13420 +};
13421 +
13422 +slimbus1_slimbus_clk: slimbus1_slimbus_clk@4a004560 {
13423 + #clock-cells = <0>;
13424 + compatible = "gate-clock";
13425 + clocks = <&slimbus_clk>;
13426 + bit-shift = <11>;
13427 + reg = <0x4a004560 0x4>;
13428 +};
13429 +
13430 +slimbus2_fclk_1: slimbus2_fclk_1@4a009538 {
13431 + #clock-cells = <0>;
13432 + compatible = "gate-clock";
13433 + clocks = <&per_abe_24m_fclk>;
13434 + bit-shift = <9>;
13435 + reg = <0x4a009538 0x4>;
13436 +};
13437 +
13438 +slimbus2_fclk_0: slimbus2_fclk_0@4a009538 {
13439 + #clock-cells = <0>;
13440 + compatible = "gate-clock";
13441 + clocks = <&func_24mc_fclk>;
13442 + bit-shift = <8>;
13443 + reg = <0x4a009538 0x4>;
13444 +};
13445 +
13446 +slimbus2_slimbus_clk: slimbus2_slimbus_clk@4a009538 {
13447 + #clock-cells = <0>;
13448 + compatible = "gate-clock";
13449 + clocks = <&pad_slimbus_core_clks_ck>;
13450 + bit-shift = <10>;
13451 + reg = <0x4a009538 0x4>;
13452 +};
13453 +
13454 +smartreflex_core_fck: smartreflex_core_fck@4a008638 {
13455 + #clock-cells = <0>;
13456 + compatible = "gate-clock";
13457 + clocks = <&l4_wkup_clk_mux_ck>;
13458 + bit-shift = <1>;
13459 + reg = <0x4a008638 0x4>;
13460 +};
13461 +
13462 +smartreflex_iva_fck: smartreflex_iva_fck@4a008630 {
13463 + #clock-cells = <0>;
13464 + compatible = "gate-clock";
13465 + clocks = <&l4_wkup_clk_mux_ck>;
13466 + bit-shift = <1>;
13467 + reg = <0x4a008630 0x4>;
13468 +};
13469 +
13470 +smartreflex_mpu_fck: smartreflex_mpu_fck@4a008628 {
13471 + #clock-cells = <0>;
13472 + compatible = "gate-clock";
13473 + clocks = <&l4_wkup_clk_mux_ck>;
13474 + bit-shift = <1>;
13475 + reg = <0x4a008628 0x4>;
13476 +};
13477 +
13478 +dmt1_clk_mux: dmt1_clk_mux@4a307840 {
13479 + #clock-cells = <0>;
13480 + compatible = "mux-clock";
13481 + clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
13482 + bit-shift = <24>;
13483 + reg = <0x4a307840 0x4>;
13484 + bit-mask = <0x1>;
13485 +};
13486 +
13487 +cm2_dm10_mux: cm2_dm10_mux@4a009428 {
13488 + #clock-cells = <0>;
13489 + compatible = "mux-clock";
13490 + clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
13491 + bit-shift = <24>;
13492 + reg = <0x4a009428 0x4>;
13493 + bit-mask = <0x1>;
13494 +};
13495 +
13496 +cm2_dm11_mux: cm2_dm11_mux@4a009430 {
13497 + #clock-cells = <0>;
13498 + compatible = "mux-clock";
13499 + clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
13500 + bit-shift = <24>;
13501 + reg = <0x4a009430 0x4>;
13502 + bit-mask = <0x1>;
13503 +};
13504 +
13505 +cm2_dm2_mux: cm2_dm2_mux@4a009438 {
13506 + #clock-cells = <0>;
13507 + compatible = "mux-clock";
13508 + clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
13509 + bit-shift = <24>;
13510 + reg = <0x4a009438 0x4>;
13511 + bit-mask = <0x1>;
13512 +};
13513 +
13514 +cm2_dm3_mux: cm2_dm3_mux@4a009440 {
13515 + #clock-cells = <0>;
13516 + compatible = "mux-clock";
13517 + clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
13518 + bit-shift = <24>;
13519 + reg = <0x4a009440 0x4>;
13520 + bit-mask = <0x1>;
13521 +};
13522 +
13523 +cm2_dm4_mux: cm2_dm4_mux@4a009448 {
13524 + #clock-cells = <0>;
13525 + compatible = "mux-clock";
13526 + clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
13527 + bit-shift = <24>;
13528 + reg = <0x4a009448 0x4>;
13529 + bit-mask = <0x1>;
13530 +};
13531 +
13532 +timer5_sync_mux: timer5_sync_mux@4a004568 {
13533 + #clock-cells = <0>;
13534 + compatible = "mux-clock";
13535 + clocks = <&syc_clk_div_ck>, <&sys_32k_ck>;
13536 + bit-shift = <24>;
13537 + reg = <0x4a004568 0x4>;
13538 + bit-mask = <0x1>;
13539 +};
13540 +
13541 +timer6_sync_mux: timer6_sync_mux@4a004570 {
13542 + #clock-cells = <0>;
13543 + compatible = "mux-clock";
13544 + clocks = <&syc_clk_div_ck>, <&sys_32k_ck>;
13545 + bit-shift = <24>;
13546 + reg = <0x4a004570 0x4>;
13547 + bit-mask = <0x1>;
13548 +};
13549 +
13550 +timer7_sync_mux: timer7_sync_mux@4a004578 {
13551 + #clock-cells = <0>;
13552 + compatible = "mux-clock";
13553 + clocks = <&syc_clk_div_ck>, <&sys_32k_ck>;
13554 + bit-shift = <24>;
13555 + reg = <0x4a004578 0x4>;
13556 + bit-mask = <0x1>;
13557 +};
13558 +
13559 +timer8_sync_mux: timer8_sync_mux@4a004580 {
13560 + #clock-cells = <0>;
13561 + compatible = "mux-clock";
13562 + clocks = <&syc_clk_div_ck>, <&sys_32k_ck>;
13563 + bit-shift = <24>;
13564 + reg = <0x4a004580 0x4>;
13565 + bit-mask = <0x1>;
13566 +};
13567 +
13568 +cm2_dm9_mux: cm2_dm9_mux@4a009450 {
13569 + #clock-cells = <0>;
13570 + compatible = "mux-clock";
13571 + clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
13572 + bit-shift = <24>;
13573 + reg = <0x4a009450 0x4>;
13574 + bit-mask = <0x1>;
13575 +};
13576 +
13577 +usb_host_fs_fck: usb_host_fs_fck@4a0093d0 {
13578 + #clock-cells = <0>;
13579 + compatible = "gate-clock";
13580 + clocks = <&func_48mc_fclk>;
13581 + reg = <0x4a0093d0 0x4>;
13582 + bit-shift = <1>;
13583 +};
13584 +
13585 +utmi_p1_gfclk: utmi_p1_gfclk@4a009358 {
13586 + #clock-cells = <0>;
13587 + compatible = "mux-clock";
13588 + clocks = <&init_60m_fclk>, <&xclk60mhsp1_ck>;
13589 + bit-shift = <24>;
13590 + reg = <0x4a009358 0x4>;
13591 + bit-mask = <0x1>;
13592 +};
13593 +
13594 +usb_host_hs_utmi_p1_clk: usb_host_hs_utmi_p1_clk@4a009358 {
13595 + #clock-cells = <0>;
13596 + compatible = "gate-clock";
13597 + clocks = <&utmi_p1_gfclk>;
13598 + bit-shift = <8>;
13599 + reg = <0x4a009358 0x4>;
13600 +};
13601 +
13602 +utmi_p2_gfclk: utmi_p2_gfclk@4a009358 {
13603 + #clock-cells = <0>;
13604 + compatible = "mux-clock";
13605 + clocks = <&init_60m_fclk>, <&xclk60mhsp2_ck>;
13606 + bit-shift = <25>;
13607 + reg = <0x4a009358 0x4>;
13608 + bit-mask = <0x1>;
13609 +};
13610 +
13611 +usb_host_hs_utmi_p2_clk: usb_host_hs_utmi_p2_clk@4a009358 {
13612 + #clock-cells = <0>;
13613 + compatible = "gate-clock";
13614 + clocks = <&utmi_p2_gfclk>;
13615 + bit-shift = <9>;
13616 + reg = <0x4a009358 0x4>;
13617 +};
13618 +
13619 +usb_host_hs_utmi_p3_clk: usb_host_hs_utmi_p3_clk@4a009358 {
13620 + #clock-cells = <0>;
13621 + compatible = "gate-clock";
13622 + clocks = <&init_60m_fclk>;
13623 + bit-shift = <10>;
13624 + reg = <0x4a009358 0x4>;
13625 +};
13626 +
13627 +usb_host_hs_hsic480m_p1_clk: usb_host_hs_hsic480m_p1_clk@4a009358 {
13628 + #clock-cells = <0>;
13629 + compatible = "gate-clock";
13630 + clocks = <&dpll_usb_m2_ck>;
13631 + bit-shift = <13>;
13632 + reg = <0x4a009358 0x4>;
13633 +};
13634 +
13635 +usb_host_hs_hsic60m_p1_clk: usb_host_hs_hsic60m_p1_clk@4a009358 {
13636 + #clock-cells = <0>;
13637 + compatible = "gate-clock";
13638 + clocks = <&init_60m_fclk>;
13639 + bit-shift = <11>;
13640 + reg = <0x4a009358 0x4>;
13641 +};
13642 +
13643 +usb_host_hs_hsic60m_p2_clk: usb_host_hs_hsic60m_p2_clk@4a009358 {
13644 + #clock-cells = <0>;
13645 + compatible = "gate-clock";
13646 + clocks = <&init_60m_fclk>;
13647 + bit-shift = <12>;
13648 + reg = <0x4a009358 0x4>;
13649 +};
13650 +
13651 +usb_host_hs_hsic480m_p2_clk: usb_host_hs_hsic480m_p2_clk@4a009358 {
13652 + #clock-cells = <0>;
13653 + compatible = "gate-clock";
13654 + clocks = <&dpll_usb_m2_ck>;
13655 + bit-shift = <14>;
13656 + reg = <0x4a009358 0x4>;
13657 +};
13658 +
13659 +usb_host_hs_func48mclk: usb_host_hs_func48mclk@4a009358 {
13660 + #clock-cells = <0>;
13661 + compatible = "gate-clock";
13662 + clocks = <&func_48mc_fclk>;
13663 + bit-shift = <15>;
13664 + reg = <0x4a009358 0x4>;
13665 +};
13666 +
13667 +usb_host_hs_fck: usb_host_hs_fck@4a009358 {
13668 + #clock-cells = <0>;
13669 + compatible = "gate-clock";
13670 + clocks = <&init_60m_fclk>;
13671 + bit-shift = <1>;
13672 + reg = <0x4a009358 0x4>;
13673 +};
13674 +
13675 +otg_60m_gfclk: otg_60m_gfclk@4a009360 {
13676 + #clock-cells = <0>;
13677 + compatible = "mux-clock";
13678 + clocks = <&utmi_phy_clkout_ck>, <&xclk60motg_ck>;
13679 + bit-shift = <24>;
13680 + reg = <0x4a009360 0x4>;
13681 + bit-mask = <0x1>;
13682 +};
13683 +
13684 +usb_otg_hs_xclk: usb_otg_hs_xclk@4a009360 {
13685 + #clock-cells = <0>;
13686 + compatible = "gate-clock";
13687 + clocks = <&otg_60m_gfclk>;
13688 + bit-shift = <8>;
13689 + reg = <0x4a009360 0x4>;
13690 +};
13691 +
13692 +usb_otg_hs_ick: usb_otg_hs_ick@4a009360 {
13693 + #clock-cells = <0>;
13694 + compatible = "gate-clock";
13695 + clocks = <&l3_div_ck>;
13696 + bit-shift = <0>;
13697 + reg = <0x4a009360 0x4>;
13698 +};
13699 +
13700 +usb_phy_cm_clk32k: usb_phy_cm_clk32k@4a008640 {
13701 + #clock-cells = <0>;
13702 + compatible = "gate-clock";
13703 + clocks = <&sys_32k_ck>;
13704 + bit-shift = <8>;
13705 + reg = <0x4a008640 0x4>;
13706 +};
13707 +
13708 +usb_tll_hs_usb_ch2_clk: usb_tll_hs_usb_ch2_clk@4a009368 {
13709 + #clock-cells = <0>;
13710 + compatible = "gate-clock";
13711 + clocks = <&init_60m_fclk>;
13712 + bit-shift = <10>;
13713 + reg = <0x4a009368 0x4>;
13714 +};
13715 +
13716 +usb_tll_hs_usb_ch0_clk: usb_tll_hs_usb_ch0_clk@4a009368 {
13717 + #clock-cells = <0>;
13718 + compatible = "gate-clock";
13719 + clocks = <&init_60m_fclk>;
13720 + bit-shift = <8>;
13721 + reg = <0x4a009368 0x4>;
13722 +};
13723 +
13724 +usb_tll_hs_usb_ch1_clk: usb_tll_hs_usb_ch1_clk@4a009368 {
13725 + #clock-cells = <0>;
13726 + compatible = "gate-clock";
13727 + clocks = <&init_60m_fclk>;
13728 + bit-shift = <9>;
13729 + reg = <0x4a009368 0x4>;
13730 +};
13731 +
13732 +usb_tll_hs_ick: usb_tll_hs_ick@4a009368 {
13733 + #clock-cells = <0>;
13734 + compatible = "gate-clock";
13735 + clocks = <&l4_div_ck>;
13736 + bit-shift = <0>;
13737 + reg = <0x4a009368 0x4>;
13738 +};
13739 +
13740 +usim_ck: usim_ck@4a307858 {
13741 + #clock-cells = <0>;
13742 + compatible = "divider-clock";
13743 + clocks = <&dpll_per_m4x2_ck>;
13744 + bit-shift = <24>;
13745 + reg = <0x4a307858 0x4>;
13746 + table = < 14 0 >, < 18 1 >;
13747 + bit-mask = <0x1>;
13748 +};
13749 +
13750 +usim_fclk: usim_fclk@4a307858 {
13751 + #clock-cells = <0>;
13752 + compatible = "gate-clock";
13753 + clocks = <&usim_ck>;
13754 + bit-shift = <8>;
13755 + reg = <0x4a307858 0x4>;
13756 +};
13757 +
13758 +pmd_stm_clock_mux_ck: pmd_stm_clock_mux_ck@4a307a20 {
13759 + #clock-cells = <0>;
13760 + compatible = "mux-clock";
13761 + clocks = <&sys_clkin_ck>, <&dpll_core_m6x2_ck>, <&tie_low_clock_ck>;
13762 + bit-shift = <20>;
13763 + reg = <0x4a307a20 0x4>;
13764 + bit-mask = <0x3>;
13765 +};
13766 +
13767 +pmd_trace_clk_mux_ck: pmd_trace_clk_mux_ck@4a307a20 {
13768 + #clock-cells = <0>;
13769 + compatible = "mux-clock";
13770 + clocks = <&sys_clkin_ck>, <&dpll_core_m6x2_ck>, <&tie_low_clock_ck>;
13771 + bit-shift = <22>;
13772 + reg = <0x4a307a20 0x4>;
13773 + bit-mask = <0x3>;
13774 +};
13775 +
13776 +stm_clk_div_ck: stm_clk_div_ck@4a307a20 {
13777 + #clock-cells = <0>;
13778 + compatible = "divider-clock";
13779 + clocks = <&pmd_stm_clock_mux_ck>;
13780 + bit-shift = <27>;
13781 + reg = <0x4a307a20 0x4>;
13782 + bit-mask = <0x7>;
13783 + index-power-of-two;
13784 +};
13785 +
13786 +trace_clk_div_div_ck: trace_clk_div_div_ck@4a307a20 {
13787 + #clock-cells = <0>;
13788 + compatible = "divider-clock";
13789 + bit-shift = <24>;
13790 + reg = <0x4a307a20 0x4>;
13791 + bit-mask = <0x7>;
13792 + index-power-of-two;
13793 +};
13794 +
13795 +trace_clk_div_ck: trace_clk_div_ck {
13796 + #clock-cells = <0>;
13797 + compatible = "ti,clkdm-gate-clock";
13798 + clocks = <&trace_clk_div_div_ck>;
13799 +};
13800 +
13801 +auxclk0_src_mux_ck: auxclk0_src_mux_ck@4a30a310 {
13802 + #clock-cells = <0>;
13803 + compatible = "mux-clock";
13804 + clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
13805 + bit-shift = <1>;
13806 + reg = <0x4a30a310 0x4>;
13807 + bit-mask = <0x3>;
13808 +};
13809 +
13810 +auxclk0_src_ck: auxclk0_src_ck@4a30a310 {
13811 + #clock-cells = <0>;
13812 + compatible = "gate-clock";
13813 + clocks = <&auxclk0_src_mux_ck>;
13814 + bit-shift = <8>;
13815 + reg = <0x4a30a310 0x4>;
13816 +};
13817 +
13818 +auxclk0_ck: auxclk0_ck@4a30a310 {
13819 + #clock-cells = <0>;
13820 + compatible = "divider-clock";
13821 + clocks = <&auxclk0_src_ck>;
13822 + bit-shift = <16>;
13823 + reg = <0x4a30a310 0x4>;
13824 + bit-mask = <0xf>;
13825 +};
13826 +
13827 +auxclk1_src_mux_ck: auxclk1_src_mux_ck@4a30a314 {
13828 + #clock-cells = <0>;
13829 + compatible = "mux-clock";
13830 + clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
13831 + bit-shift = <1>;
13832 + reg = <0x4a30a314 0x4>;
13833 + bit-mask = <0x3>;
13834 +};
13835 +
13836 +auxclk1_src_ck: auxclk1_src_ck@4a30a314 {
13837 + #clock-cells = <0>;
13838 + compatible = "gate-clock";
13839 + clocks = <&auxclk1_src_mux_ck>;
13840 + bit-shift = <8>;
13841 + reg = <0x4a30a314 0x4>;
13842 +};
13843 +
13844 +auxclk1_ck: auxclk1_ck@4a30a314 {
13845 + #clock-cells = <0>;
13846 + compatible = "divider-clock";
13847 + clocks = <&auxclk1_src_ck>;
13848 + bit-shift = <16>;
13849 + reg = <0x4a30a314 0x4>;
13850 + bit-mask = <0xf>;
13851 +};
13852 +
13853 +auxclk2_src_mux_ck: auxclk2_src_mux_ck@4a30a318 {
13854 + #clock-cells = <0>;
13855 + compatible = "mux-clock";
13856 + clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
13857 + bit-shift = <1>;
13858 + reg = <0x4a30a318 0x4>;
13859 + bit-mask = <0x3>;
13860 +};
13861 +
13862 +auxclk2_src_ck: auxclk2_src_ck@4a30a318 {
13863 + #clock-cells = <0>;
13864 + compatible = "gate-clock";
13865 + clocks = <&auxclk2_src_mux_ck>;
13866 + bit-shift = <8>;
13867 + reg = <0x4a30a318 0x4>;
13868 +};
13869 +
13870 +auxclk2_ck: auxclk2_ck@4a30a318 {
13871 + #clock-cells = <0>;
13872 + compatible = "divider-clock";
13873 + clocks = <&auxclk2_src_ck>;
13874 + bit-shift = <16>;
13875 + reg = <0x4a30a318 0x4>;
13876 + bit-mask = <0xf>;
13877 +};
13878 +
13879 +auxclk3_src_mux_ck: auxclk3_src_mux_ck@4a30a31c {
13880 + #clock-cells = <0>;
13881 + compatible = "mux-clock";
13882 + clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
13883 + bit-shift = <1>;
13884 + reg = <0x4a30a31c 0x4>;
13885 + bit-mask = <0x3>;
13886 +};
13887 +
13888 +auxclk3_src_ck: auxclk3_src_ck@4a30a31c {
13889 + #clock-cells = <0>;
13890 + compatible = "gate-clock";
13891 + clocks = <&auxclk3_src_mux_ck>;
13892 + bit-shift = <8>;
13893 + reg = <0x4a30a31c 0x4>;
13894 +};
13895 +
13896 +auxclk3_ck: auxclk3_ck@4a30a31c {
13897 + #clock-cells = <0>;
13898 + compatible = "divider-clock";
13899 + clocks = <&auxclk3_src_ck>;
13900 + bit-shift = <16>;
13901 + reg = <0x4a30a31c 0x4>;
13902 + bit-mask = <0xf>;
13903 +};
13904 +
13905 +auxclk4_src_mux_ck: auxclk4_src_mux_ck@4a30a320 {
13906 + #clock-cells = <0>;
13907 + compatible = "mux-clock";
13908 + clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
13909 + bit-shift = <1>;
13910 + reg = <0x4a30a320 0x4>;
13911 + bit-mask = <0x3>;
13912 +};
13913 +
13914 +auxclk4_src_ck: auxclk4_src_ck@4a30a320 {
13915 + #clock-cells = <0>;
13916 + compatible = "gate-clock";
13917 + clocks = <&auxclk4_src_mux_ck>;
13918 + bit-shift = <8>;
13919 + reg = <0x4a30a320 0x4>;
13920 +};
13921 +
13922 +auxclk4_ck: auxclk4_ck@4a30a320 {
13923 + #clock-cells = <0>;
13924 + compatible = "divider-clock";
13925 + clocks = <&auxclk4_src_ck>;
13926 + bit-shift = <16>;
13927 + reg = <0x4a30a320 0x4>;
13928 + bit-mask = <0xf>;
13929 +};
13930 +
13931 +auxclk5_src_mux_ck: auxclk5_src_mux_ck@4a30a324 {
13932 + #clock-cells = <0>;
13933 + compatible = "mux-clock";
13934 + clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
13935 + bit-shift = <1>;
13936 + reg = <0x4a30a324 0x4>;
13937 + bit-mask = <0x3>;
13938 +};
13939 +
13940 +auxclk5_src_ck: auxclk5_src_ck@4a30a324 {
13941 + #clock-cells = <0>;
13942 + compatible = "gate-clock";
13943 + clocks = <&auxclk5_src_mux_ck>;
13944 + bit-shift = <8>;
13945 + reg = <0x4a30a324 0x4>;
13946 +};
13947 +
13948 +auxclk5_ck: auxclk5_ck@4a30a324 {
13949 + #clock-cells = <0>;
13950 + compatible = "divider-clock";
13951 + clocks = <&auxclk5_src_ck>;
13952 + bit-shift = <16>;
13953 + reg = <0x4a30a324 0x4>;
13954 + bit-mask = <0xf>;
13955 +};
13956 +
13957 +auxclkreq0_ck: auxclkreq0_ck@4a30a210 {
13958 + #clock-cells = <0>;
13959 + compatible = "mux-clock";
13960 + clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
13961 + bit-shift = <2>;
13962 + reg = <0x4a30a210 0x4>;
13963 + bit-mask = <0x7>;
13964 +};
13965 +
13966 +auxclkreq1_ck: auxclkreq1_ck@4a30a214 {
13967 + #clock-cells = <0>;
13968 + compatible = "mux-clock";
13969 + clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
13970 + bit-shift = <2>;
13971 + reg = <0x4a30a214 0x4>;
13972 + bit-mask = <0x7>;
13973 +};
13974 +
13975 +auxclkreq2_ck: auxclkreq2_ck@4a30a218 {
13976 + #clock-cells = <0>;
13977 + compatible = "mux-clock";
13978 + clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
13979 + bit-shift = <2>;
13980 + reg = <0x4a30a218 0x4>;
13981 + bit-mask = <0x7>;
13982 +};
13983 +
13984 +auxclkreq3_ck: auxclkreq3_ck@4a30a21c {
13985 + #clock-cells = <0>;
13986 + compatible = "mux-clock";
13987 + clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
13988 + bit-shift = <2>;
13989 + reg = <0x4a30a21c 0x4>;
13990 + bit-mask = <0x7>;
13991 +};
13992 +
13993 +auxclkreq4_ck: auxclkreq4_ck@4a30a220 {
13994 + #clock-cells = <0>;
13995 + compatible = "mux-clock";
13996 + clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
13997 + bit-shift = <2>;
13998 + reg = <0x4a30a220 0x4>;
13999 + bit-mask = <0x7>;
14000 +};
14001 +
14002 +auxclkreq5_ck: auxclkreq5_ck@4a30a224 {
14003 + #clock-cells = <0>;
14004 + compatible = "mux-clock";
14005 + clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
14006 + bit-shift = <2>;
14007 + reg = <0x4a30a224 0x4>;
14008 + bit-mask = <0x7>;
14009 +};
14010 --- a/arch/arm/boot/dts/omap4.dtsi
14011 +++ b/arch/arm/boot/dts/omap4.dtsi
14012 @@ -17,6 +17,10 @@
14013 interrupt-parent = <&gic>;
14014
14015 aliases {
14016 + i2c0 = &i2c1;
14017 + i2c1 = &i2c2;
14018 + i2c2 = &i2c3;
14019 + i2c3 = &i2c4;
14020 serial0 = &uart1;
14021 serial1 = &uart2;
14022 serial2 = &uart3;
14023 @@ -32,6 +36,11 @@
14024 device_type = "cpu";
14025 next-level-cache = <&L2>;
14026 reg = <0x0>;
14027 +
14028 + clocks = <&dpll_mpu_ck>;
14029 + clock-names = "cpu";
14030 +
14031 + clock-latency = <300000>; /* From omap-cpufreq driver */
14032 };
14033 cpu@1 {
14034 compatible = "arm,cortex-a9";
14035 @@ -107,6 +116,8 @@
14036 compatible = "ti,omap-counter32k";
14037 reg = <0x4a304000 0x20>;
14038 ti,hwmods = "counter_32k";
14039 + clocks = <&sys_32k_ck>;
14040 + clock-names = "fck";
14041 };
14042
14043 omap4_pmx_core: pinmux@4a100040 {
14044 @@ -136,6 +147,8 @@
14045 #dma-cells = <1>;
14046 #dma-channels = <32>;
14047 #dma-requests = <127>;
14048 + clocks = <&l3_div_ck>;
14049 + clock-names = "fck";
14050 };
14051
14052 gpio1: gpio@4a310000 {
14053 @@ -143,6 +156,8 @@
14054 reg = <0x4a310000 0x200>;
14055 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
14056 ti,hwmods = "gpio1";
14057 + clocks = <&l4_wkup_clk_mux_ck>, <&gpio1_dbclk>;
14058 + clock-names = "fck", "dbclk";
14059 ti,gpio-always-on;
14060 gpio-controller;
14061 #gpio-cells = <2>;
14062 @@ -155,6 +170,8 @@
14063 reg = <0x48055000 0x200>;
14064 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
14065 ti,hwmods = "gpio2";
14066 + clocks = <&l4_div_ck>, <&gpio2_dbclk>;
14067 + clock-names = "fck", "dbclk";
14068 gpio-controller;
14069 #gpio-cells = <2>;
14070 interrupt-controller;
14071 @@ -166,6 +183,8 @@
14072 reg = <0x48057000 0x200>;
14073 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
14074 ti,hwmods = "gpio3";
14075 + clocks = <&l4_div_ck>, <&gpio3_dbclk>;
14076 + clock-names = "fck", "dbclk";
14077 gpio-controller;
14078 #gpio-cells = <2>;
14079 interrupt-controller;
14080 @@ -177,6 +196,8 @@
14081 reg = <0x48059000 0x200>;
14082 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
14083 ti,hwmods = "gpio4";
14084 + clocks = <&l4_div_ck>, <&gpio4_dbclk>;
14085 + clock-names = "fck", "dbclk";
14086 gpio-controller;
14087 #gpio-cells = <2>;
14088 interrupt-controller;
14089 @@ -188,6 +209,8 @@
14090 reg = <0x4805b000 0x200>;
14091 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
14092 ti,hwmods = "gpio5";
14093 + clocks = <&l4_div_ck>, <&gpio5_dbclk>;
14094 + clock-names = "fck", "dbclk";
14095 gpio-controller;
14096 #gpio-cells = <2>;
14097 interrupt-controller;
14098 @@ -199,6 +222,8 @@
14099 reg = <0x4805d000 0x200>;
14100 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
14101 ti,hwmods = "gpio6";
14102 + clocks = <&l4_div_ck>, <&gpio6_dbclk>;
14103 + clock-names = "fck", "dbclk";
14104 gpio-controller;
14105 #gpio-cells = <2>;
14106 interrupt-controller;
14107 @@ -214,6 +239,7 @@
14108 gpmc,num-cs = <8>;
14109 gpmc,num-waitpins = <4>;
14110 ti,hwmods = "gpmc";
14111 + ti,no-idle;
14112 };
14113
14114 uart1: serial@4806a000 {
14115 @@ -221,6 +247,8 @@
14116 reg = <0x4806a000 0x100>;
14117 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
14118 ti,hwmods = "uart1";
14119 + clocks = <&func_48m_fclk>;
14120 + clock-names = "fck";
14121 clock-frequency = <48000000>;
14122 };
14123
14124 @@ -229,6 +257,8 @@
14125 reg = <0x4806c000 0x100>;
14126 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
14127 ti,hwmods = "uart2";
14128 + clocks = <&func_48m_fclk>;
14129 + clock-names = "fck";
14130 clock-frequency = <48000000>;
14131 };
14132
14133 @@ -237,6 +267,8 @@
14134 reg = <0x48020000 0x100>;
14135 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
14136 ti,hwmods = "uart3";
14137 + clocks = <&func_48m_fclk>;
14138 + clock-names = "fck";
14139 clock-frequency = <48000000>;
14140 };
14141
14142 @@ -245,6 +277,8 @@
14143 reg = <0x4806e000 0x100>;
14144 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
14145 ti,hwmods = "uart4";
14146 + clocks = <&func_48m_fclk>;
14147 + clock-names = "fck";
14148 clock-frequency = <48000000>;
14149 };
14150
14151 @@ -255,6 +289,8 @@
14152 #address-cells = <1>;
14153 #size-cells = <0>;
14154 ti,hwmods = "i2c1";
14155 + clocks = <&func_96m_fclk>;
14156 + clock-names = "fck";
14157 };
14158
14159 i2c2: i2c@48072000 {
14160 @@ -264,6 +300,8 @@
14161 #address-cells = <1>;
14162 #size-cells = <0>;
14163 ti,hwmods = "i2c2";
14164 + clocks = <&func_96m_fclk>;
14165 + clock-names = "fck";
14166 };
14167
14168 i2c3: i2c@48060000 {
14169 @@ -273,6 +311,8 @@
14170 #address-cells = <1>;
14171 #size-cells = <0>;
14172 ti,hwmods = "i2c3";
14173 + clocks = <&func_96m_fclk>;
14174 + clock-names = "fck";
14175 };
14176
14177 i2c4: i2c@48350000 {
14178 @@ -282,6 +322,8 @@
14179 #address-cells = <1>;
14180 #size-cells = <0>;
14181 ti,hwmods = "i2c4";
14182 + clocks = <&func_96m_fclk>;
14183 + clock-names = "fck";
14184 };
14185
14186 mcspi1: spi@48098000 {
14187 @@ -291,6 +333,8 @@
14188 #address-cells = <1>;
14189 #size-cells = <0>;
14190 ti,hwmods = "mcspi1";
14191 + clocks = <&func_48m_fclk>;
14192 + clock-names = "fck";
14193 ti,spi-num-cs = <4>;
14194 dmas = <&sdma 35>,
14195 <&sdma 36>,
14196 @@ -311,6 +355,8 @@
14197 #address-cells = <1>;
14198 #size-cells = <0>;
14199 ti,hwmods = "mcspi2";
14200 + clocks = <&func_48m_fclk>;
14201 + clock-names = "fck";
14202 ti,spi-num-cs = <2>;
14203 dmas = <&sdma 43>,
14204 <&sdma 44>,
14205 @@ -326,6 +372,8 @@
14206 #address-cells = <1>;
14207 #size-cells = <0>;
14208 ti,hwmods = "mcspi3";
14209 + clocks = <&func_48m_fclk>;
14210 + clock-names = "fck";
14211 ti,spi-num-cs = <2>;
14212 dmas = <&sdma 15>, <&sdma 16>;
14213 dma-names = "tx0", "rx0";
14214 @@ -338,6 +386,8 @@
14215 #address-cells = <1>;
14216 #size-cells = <0>;
14217 ti,hwmods = "mcspi4";
14218 + clocks = <&func_48m_fclk>;
14219 + clock-names = "fck";
14220 ti,spi-num-cs = <1>;
14221 dmas = <&sdma 70>, <&sdma 71>;
14222 dma-names = "tx0", "rx0";
14223 @@ -348,6 +398,8 @@
14224 reg = <0x4809c000 0x400>;
14225 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
14226 ti,hwmods = "mmc1";
14227 + clocks = <&hsmmc1_fclk>;
14228 + clock-names = "fck";
14229 ti,dual-volt;
14230 ti,needs-special-reset;
14231 dmas = <&sdma 61>, <&sdma 62>;
14232 @@ -359,6 +411,8 @@
14233 reg = <0x480b4000 0x400>;
14234 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
14235 ti,hwmods = "mmc2";
14236 + clocks = <&hsmmc2_fclk>;
14237 + clock-names = "fck";
14238 ti,needs-special-reset;
14239 dmas = <&sdma 47>, <&sdma 48>;
14240 dma-names = "tx", "rx";
14241 @@ -369,6 +423,8 @@
14242 reg = <0x480ad000 0x400>;
14243 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
14244 ti,hwmods = "mmc3";
14245 + clocks = <&func_48m_fclk>;
14246 + clock-names = "fck";
14247 ti,needs-special-reset;
14248 dmas = <&sdma 77>, <&sdma 78>;
14249 dma-names = "tx", "rx";
14250 @@ -379,6 +435,8 @@
14251 reg = <0x480d1000 0x400>;
14252 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
14253 ti,hwmods = "mmc4";
14254 + clocks = <&func_48m_fclk>;
14255 + clock-names = "fck";
14256 ti,needs-special-reset;
14257 dmas = <&sdma 57>, <&sdma 58>;
14258 dma-names = "tx", "rx";
14259 @@ -389,16 +447,20 @@
14260 reg = <0x480d5000 0x400>;
14261 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
14262 ti,hwmods = "mmc5";
14263 + clocks = <&func_48m_fclk>;
14264 + clock-names = "fck";
14265 ti,needs-special-reset;
14266 dmas = <&sdma 59>, <&sdma 60>;
14267 dma-names = "tx", "rx";
14268 };
14269
14270 wdt2: wdt@4a314000 {
14271 - compatible = "ti,omap4-wdt", "ti,omap3-wdt";
14272 + compatible = "ti,omap4-wdt";
14273 reg = <0x4a314000 0x80>;
14274 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
14275 ti,hwmods = "wd_timer2";
14276 + clocks = <&sys_32k_ck>;
14277 + clock-names = "fck";
14278 };
14279
14280 mcpdm: mcpdm@40132000 {
14281 @@ -408,6 +470,8 @@
14282 reg-names = "mpu", "dma";
14283 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
14284 ti,hwmods = "mcpdm";
14285 + clocks = <&pad_clks_ck>;
14286 + clock-names = "fck";
14287 dmas = <&sdma 65>,
14288 <&sdma 66>;
14289 dma-names = "up_link", "dn_link";
14290 @@ -420,6 +484,8 @@
14291 reg-names = "mpu", "dma";
14292 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
14293 ti,hwmods = "dmic";
14294 + clocks = <&func_dmic_abe_gfclk>;
14295 + clock-names = "fck";
14296 dmas = <&sdma 67>;
14297 dma-names = "up_link";
14298 };
14299 @@ -433,6 +499,8 @@
14300 interrupt-names = "common";
14301 ti,buffer-size = <128>;
14302 ti,hwmods = "mcbsp1";
14303 + clocks = <&func_mcbsp1_gfclk>, <&pad_clks_ck>, <&mcbsp1_sync_mux_ck>;
14304 + clock-names = "fck", "pad_fck", "prcm_fck";
14305 dmas = <&sdma 33>,
14306 <&sdma 34>;
14307 dma-names = "tx", "rx";
14308 @@ -447,6 +515,8 @@
14309 interrupt-names = "common";
14310 ti,buffer-size = <128>;
14311 ti,hwmods = "mcbsp2";
14312 + clocks = <&func_mcbsp2_gfclk>, <&pad_clks_ck>, <&mcbsp2_sync_mux_ck>;
14313 + clock-names = "fck", "pad_fck", "prcm_fck";
14314 dmas = <&sdma 17>,
14315 <&sdma 18>;
14316 dma-names = "tx", "rx";
14317 @@ -461,6 +531,8 @@
14318 interrupt-names = "common";
14319 ti,buffer-size = <128>;
14320 ti,hwmods = "mcbsp3";
14321 + clocks = <&func_mcbsp3_gfclk>, <&pad_clks_ck>, <&mcbsp3_sync_mux_ck>;
14322 + clock-names = "fck", "pad_fck", "prcm_fck";
14323 dmas = <&sdma 19>,
14324 <&sdma 20>;
14325 dma-names = "tx", "rx";
14326 @@ -474,6 +546,8 @@
14327 interrupt-names = "common";
14328 ti,buffer-size = <128>;
14329 ti,hwmods = "mcbsp4";
14330 + clocks = <&per_mcbsp4_gfclk>, <&pad_clks_ck>, <&mcbsp4_sync_mux_ck>;
14331 + clock-names = "fck", "pad_fck", "prcm_fck";
14332 dmas = <&sdma 31>,
14333 <&sdma 32>;
14334 dma-names = "tx", "rx";
14335 @@ -485,6 +559,15 @@
14336 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
14337 reg-names = "mpu";
14338 ti,hwmods = "kbd";
14339 + clocks = <&sys_32k_ck>;
14340 + clock-names = "fck";
14341 + };
14342 +
14343 + dmm: dmm@4e000000 {
14344 + compatible = "ti,omap4-dmm";
14345 + reg = <0x4e000000 0x800>;
14346 + interrupts = <0 113 0x4>;
14347 + ti,hwmods = "dmm";
14348 };
14349
14350 emif1: emif@4c000000 {
14351 @@ -492,6 +575,9 @@
14352 reg = <0x4c000000 0x100>;
14353 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
14354 ti,hwmods = "emif1";
14355 + ti,no-idle;
14356 + clocks = <&ddrphy_ck>;
14357 + clock-names = "fck";
14358 phy-type = <1>;
14359 hw-caps-read-idle-ctrl;
14360 hw-caps-ll-interface;
14361 @@ -503,6 +589,9 @@
14362 reg = <0x4d000000 0x100>;
14363 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
14364 ti,hwmods = "emif2";
14365 + ti,no-idle;
14366 + clocks = <&ddrphy_ck>;
14367 + clock-names = "fck";
14368 phy-type = <1>;
14369 hw-caps-read-idle-ctrl;
14370 hw-caps-ll-interface;
14371 @@ -516,18 +605,36 @@
14372 #size-cells = <1>;
14373 ranges;
14374 ti,hwmods = "ocp2scp_usb_phy";
14375 + clocks = <&ocp2scp_usb_phy_phy_48m>;
14376 + clock-names = "fck";
14377 usb2_phy: usb2phy@4a0ad080 {
14378 compatible = "ti,omap-usb2";
14379 reg = <0x4a0ad080 0x58>;
14380 - ctrl-module = <&omap_control_usb>;
14381 + ctrl-module = <&omap_control_usb2phy>;
14382 + clocks = <&usb_phy_cm_clk32k>, <&ocp2scp_usb_phy_phy_48m>;
14383 + clock-names = "wkupclk", "refclk";
14384 + #phy-cells = <0>;
14385 };
14386 };
14387
14388 + mailbox: mailbox@4a0f4000 {
14389 + compatible = "ti,omap4-mailbox";
14390 + reg = <0x4a0f4000 0x200>;
14391 + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
14392 + ti,hwmods = "mailbox";
14393 + ti,mbox-num-users = <3>;
14394 + ti,mbox-num-fifos = <8>;
14395 + ti,mbox-names = "mbox-ipu", "mbox-dsp";
14396 + ti,mbox-data = <0 1 0 0>, <3 2 0 0>;
14397 + };
14398 +
14399 timer1: timer@4a318000 {
14400 compatible = "ti,omap3430-timer";
14401 reg = <0x4a318000 0x80>;
14402 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
14403 ti,hwmods = "timer1";
14404 + clocks = <&dmt1_clk_mux>;
14405 + clock-names = "fck";
14406 ti,timer-alwon;
14407 };
14408
14409 @@ -536,6 +643,8 @@
14410 reg = <0x48032000 0x80>;
14411 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
14412 ti,hwmods = "timer2";
14413 + clocks = <&cm2_dm2_mux>;
14414 + clock-names = "fck";
14415 };
14416
14417 timer3: timer@48034000 {
14418 @@ -543,6 +652,8 @@
14419 reg = <0x48034000 0x80>;
14420 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
14421 ti,hwmods = "timer3";
14422 + clocks = <&cm2_dm3_mux>;
14423 + clock-names = "fck";
14424 };
14425
14426 timer4: timer@48036000 {
14427 @@ -550,6 +661,8 @@
14428 reg = <0x48036000 0x80>;
14429 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
14430 ti,hwmods = "timer4";
14431 + clocks = <&cm2_dm4_mux>;
14432 + clock-names = "fck";
14433 };
14434
14435 timer5: timer@40138000 {
14436 @@ -558,6 +671,8 @@
14437 <0x49038000 0x80>;
14438 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
14439 ti,hwmods = "timer5";
14440 + clocks = <&timer5_sync_mux>;
14441 + clock-names = "fck";
14442 ti,timer-dsp;
14443 };
14444
14445 @@ -567,6 +682,8 @@
14446 <0x4903a000 0x80>;
14447 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
14448 ti,hwmods = "timer6";
14449 + clocks = <&timer6_sync_mux>;
14450 + clock-names = "fck";
14451 ti,timer-dsp;
14452 };
14453
14454 @@ -576,6 +693,8 @@
14455 <0x4903c000 0x80>;
14456 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
14457 ti,hwmods = "timer7";
14458 + clocks = <&timer7_sync_mux>;
14459 + clock-names = "fck";
14460 ti,timer-dsp;
14461 };
14462
14463 @@ -585,6 +704,8 @@
14464 <0x4903e000 0x80>;
14465 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
14466 ti,hwmods = "timer8";
14467 + clocks = <&timer8_sync_mux>;
14468 + clock-names = "fck";
14469 ti,timer-pwm;
14470 ti,timer-dsp;
14471 };
14472 @@ -594,6 +715,8 @@
14473 reg = <0x4803e000 0x80>;
14474 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
14475 ti,hwmods = "timer9";
14476 + clocks = <&cm2_dm9_mux>;
14477 + clock-names = "fck";
14478 ti,timer-pwm;
14479 };
14480
14481 @@ -602,6 +725,8 @@
14482 reg = <0x48086000 0x80>;
14483 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
14484 ti,hwmods = "timer10";
14485 + clocks = <&cm2_dm10_mux>;
14486 + clock-names = "fck";
14487 ti,timer-pwm;
14488 };
14489
14490 @@ -610,6 +735,8 @@
14491 reg = <0x48088000 0x80>;
14492 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
14493 ti,hwmods = "timer11";
14494 + clocks = <&cm2_dm11_mux>;
14495 + clock-names = "fck";
14496 ti,timer-pwm;
14497 };
14498
14499 @@ -618,12 +745,16 @@
14500 reg = <0x4a062000 0x1000>;
14501 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
14502 ti,hwmods = "usb_tll_hs";
14503 + clocks = <&usb_tll_hs_ick>;
14504 + clock-names = "fck";
14505 };
14506
14507 usbhshost: usbhshost@4a064000 {
14508 compatible = "ti,usbhs-host";
14509 reg = <0x4a064000 0x800>;
14510 ti,hwmods = "usb_host_hs";
14511 + clocks = <&usb_host_hs_fck>;
14512 + clock-names = "fck";
14513 #address-cells = <1>;
14514 #size-cells = <1>;
14515 ranges;
14516 @@ -643,12 +774,16 @@
14517 };
14518 };
14519
14520 - omap_control_usb: omap-control-usb@4a002300 {
14521 - compatible = "ti,omap-control-usb";
14522 - reg = <0x4a002300 0x4>,
14523 - <0x4a00233c 0x4>;
14524 - reg-names = "control_dev_conf", "otghs_control";
14525 - ti,type = <1>;
14526 + omap_control_usb2phy: control-phy@4a002300 {
14527 + compatible = "ti,control-phy-usb2";
14528 + reg = <0x4a002300 0x4>;
14529 + reg-names = "power";
14530 + };
14531 +
14532 + omap_control_usbotg: control-phy@4a00233c {
14533 + compatible = "ti,control-phy-otghs";
14534 + reg = <0x4a00233c 0x4>;
14535 + reg-names = "otghs_control";
14536 };
14537
14538 usb_otg_hs: usb_otg_hs@4a0ab000 {
14539 @@ -657,11 +792,98 @@
14540 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
14541 interrupt-names = "mc", "dma";
14542 ti,hwmods = "usb_otg_hs";
14543 + clocks = <&usb_otg_hs_ick>, <&usb_otg_hs_xclk>;
14544 + clock-names = "fck", "xclk";
14545 usb-phy = <&usb2_phy>;
14546 + phys = <&usb2_phy>;
14547 + phy-names = "usb2-phy";
14548 multipoint = <1>;
14549 num-eps = <16>;
14550 ram-bits = <12>;
14551 - ti,has-mailbox;
14552 + ctrl-module = <&omap_control_usbotg>;
14553 + dr_mode = "peripheral";
14554 + };
14555 +
14556 + dss@58000000 {
14557 + compatible = "ti,omap4-dss", "simple-bus";
14558 + reg = <0x58000000 0x80>;
14559 + ti,hwmods = "dss_core";
14560 + #address-cells = <1>;
14561 + #size-cells = <1>;
14562 + ranges;
14563 +
14564 + dispc@58001000 {
14565 + compatible = "ti,omap4-dispc";
14566 + reg = <0x58001000 0x1000>;
14567 + interrupts = <0 25 0x4>;
14568 + ti,hwmods = "dss_dispc";
14569 + };
14570 +
14571 + dpi: encoder@0 {
14572 + compatible = "ti,omap4-dpi";
14573 + };
14574 +
14575 + rfbi: encoder@58002000 {
14576 + compatible = "ti,omap4-rfbi";
14577 + reg = <0x58002000 0x1000>;
14578 + ti,hwmods = "dss_rfbi";
14579 + };
14580 +
14581 + /*
14582 + * Accessing venc registers cause a crash on omap4, so
14583 + * this is disabled for now.
14584 + */
14585 + /*
14586 + venc: encoder@58003000 {
14587 + compatible = "ti,omap4-venc";
14588 + reg = <0x58003000 0x1000>;
14589 + ti,hwmods = "dss_venc";
14590 + };
14591 + */
14592 +
14593 + dsi1: encoder@58004000 {
14594 + compatible = "ti,omap4-dsi";
14595 + reg = <0x58004000 0x200>;
14596 + interrupts = <0 53 0x4>;
14597 + ti,hwmods = "dss_dsi1";
14598 + };
14599 +
14600 + dsi2: encoder@58005000 {
14601 + compatible = "ti,omap4-dsi";
14602 + reg = <0x58005000 0x200>;
14603 + interrupts = <0 84 0x4>;
14604 + ti,hwmods = "dss_dsi2";
14605 + };
14606 +
14607 + hdmi: encoder@58006000 {
14608 + compatible = "ti,omap4-hdmi";
14609 + reg = <0x58006000 0x200>,
14610 + <0x58006200 0x100>,
14611 + <0x58006300 0x100>,
14612 + <0x58006400 0x1000>;
14613 + reg-names = "hdmi_wp", "hdmi_pllctrl",
14614 + "hdmi_txphy", "hdmi_core";
14615 + interrupts = <0 101 0x4>;
14616 + ti,hwmods = "dss_hdmi";
14617 + };
14618 + };
14619 +
14620 + aes: aes@4b501000 {
14621 + compatible = "ti,omap4-aes";
14622 + ti,hwmods = "aes";
14623 + reg = <0x4b501000 0xa0>;
14624 + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
14625 + dmas = <&sdma 111>, <&sdma 110>;
14626 + dma-names = "tx", "rx";
14627 + };
14628 +
14629 + des: des@480a5000 {
14630 + compatible = "ti,omap4-des";
14631 + ti,hwmods = "des";
14632 + reg = <0x480a5000 0xa0>;
14633 + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
14634 + dmas = <&sdma 117>, <&sdma 116>;
14635 + dma-names = "tx", "rx";
14636 };
14637 };
14638 };
14639 --- a/arch/arm/boot/dts/omap4-panda-common.dtsi
14640 +++ b/arch/arm/boot/dts/omap4-panda-common.dtsi
14641 @@ -60,22 +60,6 @@
14642 "AFMR", "Line In";
14643 };
14644
14645 - /*
14646 - * Temp hack: Need to be replaced with the proper gpio-controlled
14647 - * reset driver as soon it will be merged.
14648 - * http://thread.gmane.org/gmane.linux.drivers.devicetree/36830
14649 - */
14650 - /* HS USB Port 1 RESET */
14651 - hsusb1_reset: hsusb1_reset_reg {
14652 - compatible = "regulator-fixed";
14653 - regulator-name = "hsusb1_reset";
14654 - regulator-min-microvolt = <3300000>;
14655 - regulator-max-microvolt = <3300000>;
14656 - gpio = <&gpio2 30 0>; /* gpio_62 */
14657 - startup-delay-us = <70000>;
14658 - enable-active-high;
14659 - };
14660 -
14661 /* HS USB Port 1 Power */
14662 hsusb1_power: hsusb1_power_reg {
14663 compatible = "regulator-fixed";
14664 @@ -97,14 +81,10 @@
14665 /* HS USB Host PHY on PORT 1 */
14666 hsusb1_phy: hsusb1_phy {
14667 compatible = "usb-nop-xceiv";
14668 - reset-supply = <&hsusb1_reset>;
14669 + reset-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>; /* gpio_62 */
14670 vcc-supply = <&hsusb1_power>;
14671 - /**
14672 - * FIXME:
14673 - * put the right clock phandle here when available
14674 - * clocks = <&auxclk3>;
14675 - * clock-names = "main_clk";
14676 - */
14677 + clocks = <&auxclk3_ck>;
14678 + clock-names = "main_clk";
14679 clock-frequency = <19200000>;
14680 };
14681
14682 @@ -401,3 +381,51 @@
14683 &usbhsehci {
14684 phys = <&hsusb1_phy>;
14685 };
14686 +
14687 +&dsi1 {
14688 + vdds_dsi-supply = <&vcxio>;
14689 +};
14690 +
14691 +&dsi2 {
14692 + vdds_dsi-supply = <&vcxio>;
14693 +};
14694 +
14695 +&hdmi {
14696 + vdda_hdmi_dac-supply = <&vdac>;
14697 +};
14698 +
14699 +/ {
14700 + aliases {
14701 + display0 = &dvi0;
14702 + display1 = &hdmi0;
14703 + };
14704 +
14705 + tfp410: encoder@0 {
14706 + compatible = "ti,tfp410";
14707 + video-source = <&dpi>;
14708 + data-lines = <24>;
14709 + gpios = <&gpio1 0 0>; /* 0, power-down */
14710 + };
14711 +
14712 + dvi0: connector@0 {
14713 + compatible = "ti,dvi_connector";
14714 + video-source = <&tfp410>;
14715 + i2c-bus = <&i2c3>;
14716 + };
14717 +
14718 + tpd12s015: encoder@1 {
14719 + compatible = "ti,tpd12s015";
14720 +
14721 + video-source = <&hdmi>;
14722 +
14723 + gpios = <&gpio2 28 0>, /* 60, CT CP HPD */
14724 + <&gpio2 9 0>, /* 41, LS OE */
14725 + <&gpio2 31 0>; /* 63, HPD */
14726 + };
14727 +
14728 + hdmi0: connector@1 {
14729 + compatible = "ti,hdmi_connector";
14730 +
14731 + video-source = <&tpd12s015>;
14732 + };
14733 +};
14734 --- a/arch/arm/boot/dts/omap4-sdp.dts
14735 +++ b/arch/arm/boot/dts/omap4-sdp.dts
14736 @@ -569,3 +569,73 @@
14737 mode = <3>;
14738 power = <50>;
14739 };
14740 +
14741 +&dsi1 {
14742 + vdds_dsi-supply = <&vcxio>;
14743 +};
14744 +
14745 +&dsi2 {
14746 + vdds_dsi-supply = <&vcxio>;
14747 +};
14748 +
14749 +&hdmi {
14750 + vdda_hdmi_dac-supply = <&vdac>;
14751 +};
14752 +
14753 +/ {
14754 + aliases {
14755 + display0 = &lcd0;
14756 + display1 = &lcd1;
14757 + display2 = &hdmi0;
14758 + };
14759 +
14760 + lcd0: display@0 {
14761 + compatible = "tpo,taal", "panel-dsi-cm";
14762 +
14763 + video-source = <&dsi1>;
14764 +
14765 + lanes = <
14766 + 0 /* clk + */
14767 + 1 /* clk - */
14768 + 2 /* data1 + */
14769 + 3 /* data1 - */
14770 + 4 /* data2 + */
14771 + 5 /* data2 - */
14772 + >;
14773 +
14774 + gpios = <&gpio4 6 0>; /* 102, reset */
14775 + };
14776 +
14777 + lcd1: display@1 {
14778 + compatible = "tpo,taal", "panel-dsi-cm";
14779 +
14780 + video-source = <&dsi2>;
14781 +
14782 + lanes = <
14783 + 0 /* clk + */
14784 + 1 /* clk - */
14785 + 2 /* data1 + */
14786 + 3 /* data1 - */
14787 + 4 /* data2 + */
14788 + 5 /* data2 - */
14789 + >;
14790 +
14791 + gpios = <&gpio4 8 0>; /* 104, reset */
14792 + };
14793 +
14794 + tpd12s015: encoder@0 {
14795 + compatible = "ti,tpd12s015";
14796 +
14797 + video-source = <&hdmi>;
14798 +
14799 + gpios = <&gpio2 28 0>, /* 60, CT CP HPD */
14800 + <&gpio2 9 0>, /* 41, LS OE */
14801 + <&gpio2 31 0>; /* 63, HPD */
14802 + };
14803 +
14804 + hdmi0: connector@0 {
14805 + compatible = "ti,hdmi_connector";
14806 +
14807 + video-source = <&tpd12s015>;
14808 + };
14809 +};
14810 --- /dev/null
14811 +++ b/arch/arm/boot/dts/omap54xx-clocks.dtsi
14812 @@ -0,0 +1,1400 @@
14813 +/*
14814 + * Device Tree Source for OMAP5 clock data
14815 + *
14816 + * Copyright (C) 2013 Texas Instruments, Inc.
14817 + *
14818 + * This program is free software; you can redistribute it and/or modify
14819 + * it under the terms of the GNU General Public License version 2 as
14820 + * published by the Free Software Foundation.
14821 + */
14822 +
14823 +pad_clks_src_ck: pad_clks_src_ck {
14824 + #clock-cells = <0>;
14825 + compatible = "fixed-clock";
14826 + clock-frequency = <12000000>;
14827 +};
14828 +
14829 +pad_clks_ck: pad_clks_ck@4a004108 {
14830 + #clock-cells = <0>;
14831 + compatible = "gate-clock";
14832 + clocks = <&pad_clks_src_ck>;
14833 + bit-shift = <8>;
14834 + reg = <0x4a004108 0x4>;
14835 +};
14836 +
14837 +secure_32k_clk_src_ck: secure_32k_clk_src_ck {
14838 + #clock-cells = <0>;
14839 + compatible = "fixed-clock";
14840 + clock-frequency = <32768>;
14841 +};
14842 +
14843 +slimbus_src_clk: slimbus_src_clk {
14844 + #clock-cells = <0>;
14845 + compatible = "fixed-clock";
14846 + clock-frequency = <12000000>;
14847 +};
14848 +
14849 +slimbus_clk: slimbus_clk@4a004108 {
14850 + #clock-cells = <0>;
14851 + compatible = "gate-clock";
14852 + clocks = <&slimbus_src_clk>;
14853 + bit-shift = <10>;
14854 + reg = <0x4a004108 0x4>;
14855 +};
14856 +
14857 +sys_32k_ck: sys_32k_ck {
14858 + #clock-cells = <0>;
14859 + compatible = "fixed-clock";
14860 + clock-frequency = <32768>;
14861 +};
14862 +
14863 +virt_12000000_ck: virt_12000000_ck {
14864 + #clock-cells = <0>;
14865 + compatible = "fixed-clock";
14866 + clock-frequency = <12000000>;
14867 +};
14868 +
14869 +virt_13000000_ck: virt_13000000_ck {
14870 + #clock-cells = <0>;
14871 + compatible = "fixed-clock";
14872 + clock-frequency = <13000000>;
14873 +};
14874 +
14875 +virt_16800000_ck: virt_16800000_ck {
14876 + #clock-cells = <0>;
14877 + compatible = "fixed-clock";
14878 + clock-frequency = <16800000>;
14879 +};
14880 +
14881 +virt_19200000_ck: virt_19200000_ck {
14882 + #clock-cells = <0>;
14883 + compatible = "fixed-clock";
14884 + clock-frequency = <19200000>;
14885 +};
14886 +
14887 +virt_26000000_ck: virt_26000000_ck {
14888 + #clock-cells = <0>;
14889 + compatible = "fixed-clock";
14890 + clock-frequency = <26000000>;
14891 +};
14892 +
14893 +virt_27000000_ck: virt_27000000_ck {
14894 + #clock-cells = <0>;
14895 + compatible = "fixed-clock";
14896 + clock-frequency = <27000000>;
14897 +};
14898 +
14899 +virt_38400000_ck: virt_38400000_ck {
14900 + #clock-cells = <0>;
14901 + compatible = "fixed-clock";
14902 + clock-frequency = <38400000>;
14903 +};
14904 +
14905 +sys_clkin: sys_clkin@4ae06110 {
14906 + #clock-cells = <0>;
14907 + compatible = "mux-clock";
14908 + clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
14909 + reg = <0x4ae06110 0x4>;
14910 + bit-mask = <0x7>;
14911 + index-starts-at-one;
14912 +};
14913 +
14914 +xclk60mhsp1_ck: xclk60mhsp1_ck {
14915 + #clock-cells = <0>;
14916 + compatible = "fixed-clock";
14917 + clock-frequency = <60000000>;
14918 +};
14919 +
14920 +xclk60mhsp2_ck: xclk60mhsp2_ck {
14921 + #clock-cells = <0>;
14922 + compatible = "fixed-clock";
14923 + clock-frequency = <60000000>;
14924 +};
14925 +
14926 +abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux@4ae06108 {
14927 + #clock-cells = <0>;
14928 + compatible = "mux-clock";
14929 + clocks = <&sys_clkin>, <&sys_32k_ck>;
14930 + reg = <0x4ae06108 0x4>;
14931 + bit-mask = <0x1>;
14932 +};
14933 +
14934 +abe_dpll_clk_mux: abe_dpll_clk_mux@4ae0610c {
14935 + #clock-cells = <0>;
14936 + compatible = "mux-clock";
14937 + clocks = <&sys_clkin>, <&sys_32k_ck>;
14938 + reg = <0x4ae0610c 0x4>;
14939 + bit-mask = <0x1>;
14940 +};
14941 +
14942 +dpll_abe_ck: dpll_abe_ck@4a0041e0 {
14943 + #clock-cells = <0>;
14944 + compatible = "ti,omap4-dpll-m4xen-clock";
14945 + clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;
14946 + reg = <0x4a0041e0 0x4>, <0x4a0041e4 0x4>, <0x4a0041e8 0x4>, <0x4a0041ec 0x4>;
14947 + reg-names = "control", "idlest", "autoidle", "mult-div1";
14948 +};
14949 +
14950 +dpll_abe_x2_ck: dpll_abe_x2_ck {
14951 + #clock-cells = <0>;
14952 + compatible = "ti,omap4-dpll-x2-clock";
14953 + clocks = <&dpll_abe_ck>;
14954 +};
14955 +
14956 +dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@4a0041f0 {
14957 + #clock-cells = <0>;
14958 + compatible = "ti,divider-clock";
14959 + clocks = <&dpll_abe_x2_ck>;
14960 + ti,autoidle-shift = <8>;
14961 + reg = <0x4a0041f0 0x4>;
14962 + bit-mask = <0x1f>;
14963 + index-starts-at-one;
14964 + ti,autoidle-low;
14965 +};
14966 +
14967 +abe_24m_fclk: abe_24m_fclk {
14968 + #clock-cells = <0>;
14969 + compatible = "fixed-factor-clock";
14970 + clocks = <&dpll_abe_m2x2_ck>;
14971 + clock-mult = <1>;
14972 + clock-div = <8>;
14973 +};
14974 +
14975 +abe_clk: abe_clk@4a004108 {
14976 + #clock-cells = <0>;
14977 + compatible = "divider-clock";
14978 + clocks = <&dpll_abe_m2x2_ck>;
14979 + reg = <0x4a004108 0x4>;
14980 + bit-mask = <0x3>;
14981 + index-power-of-two;
14982 +};
14983 +
14984 +abe_iclk: abe_iclk {
14985 + #clock-cells = <0>;
14986 + compatible = "fixed-factor-clock";
14987 + clocks = <&abe_clk>;
14988 + clock-mult = <1>;
14989 + clock-div = <2>;
14990 +};
14991 +
14992 +abe_lp_clk_div: abe_lp_clk_div {
14993 + #clock-cells = <0>;
14994 + compatible = "fixed-factor-clock";
14995 + clocks = <&dpll_abe_m2x2_ck>;
14996 + clock-mult = <1>;
14997 + clock-div = <16>;
14998 +};
14999 +
15000 +dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@4a0041f4 {
15001 + #clock-cells = <0>;
15002 + compatible = "ti,divider-clock";
15003 + clocks = <&dpll_abe_x2_ck>;
15004 + ti,autoidle-shift = <8>;
15005 + reg = <0x4a0041f4 0x4>;
15006 + bit-mask = <0x1f>;
15007 + index-starts-at-one;
15008 + ti,autoidle-low;
15009 +};
15010 +
15011 +dpll_core_ck: dpll_core_ck@4a004120 {
15012 + #clock-cells = <0>;
15013 + compatible = "ti,omap4-dpll-core-clock";
15014 + clocks = <&sys_clkin>, <&dpll_abe_m3x2_ck>;
15015 + reg = <0x4a004120 0x4>, <0x4a004124 0x4>, <0x4a004128 0x4>, <0x4a00412c 0x4>;
15016 + reg-names = "control", "idlest", "autoidle", "mult-div1";
15017 +};
15018 +
15019 +dpll_core_x2_ck: dpll_core_x2_ck {
15020 + #clock-cells = <0>;
15021 + compatible = "ti,omap4-dpll-x2-clock";
15022 + clocks = <&dpll_core_ck>;
15023 +};
15024 +
15025 +dpll_core_h21x2_ck: dpll_core_h21x2_ck@4a004150 {
15026 + #clock-cells = <0>;
15027 + compatible = "ti,divider-clock";
15028 + clocks = <&dpll_core_x2_ck>;
15029 + ti,autoidle-shift = <8>;
15030 + reg = <0x4a004150 0x4>;
15031 + bit-mask = <0x3f>;
15032 + index-starts-at-one;
15033 + ti,autoidle-low;
15034 +};
15035 +
15036 +c2c_fclk: c2c_fclk {
15037 + #clock-cells = <0>;
15038 + compatible = "fixed-factor-clock";
15039 + clocks = <&dpll_core_h21x2_ck>;
15040 + clock-mult = <1>;
15041 + clock-div = <1>;
15042 +};
15043 +
15044 +c2c_iclk: c2c_iclk {
15045 + #clock-cells = <0>;
15046 + compatible = "fixed-factor-clock";
15047 + clocks = <&c2c_fclk>;
15048 + clock-mult = <1>;
15049 + clock-div = <2>;
15050 +};
15051 +
15052 +custefuse_sys_gfclk_div: custefuse_sys_gfclk_div {
15053 + #clock-cells = <0>;
15054 + compatible = "fixed-factor-clock";
15055 + clocks = <&sys_clkin>;
15056 + clock-mult = <1>;
15057 + clock-div = <2>;
15058 +};
15059 +
15060 +dpll_core_h11x2_ck: dpll_core_h11x2_ck@4a004138 {
15061 + #clock-cells = <0>;
15062 + compatible = "ti,divider-clock";
15063 + clocks = <&dpll_core_x2_ck>;
15064 + ti,autoidle-shift = <8>;
15065 + reg = <0x4a004138 0x4>;
15066 + bit-mask = <0x3f>;
15067 + index-starts-at-one;
15068 + ti,autoidle-low;
15069 +};
15070 +
15071 +dpll_core_h12x2_ck: dpll_core_h12x2_ck@4a00413c {
15072 + #clock-cells = <0>;
15073 + compatible = "ti,divider-clock";
15074 + clocks = <&dpll_core_x2_ck>;
15075 + ti,autoidle-shift = <8>;
15076 + reg = <0x4a00413c 0x4>;
15077 + bit-mask = <0x3f>;
15078 + index-starts-at-one;
15079 + ti,autoidle-low;
15080 +};
15081 +
15082 +dpll_core_h13x2_ck: dpll_core_h13x2_ck@4a004140 {
15083 + #clock-cells = <0>;
15084 + compatible = "ti,divider-clock";
15085 + clocks = <&dpll_core_x2_ck>;
15086 + ti,autoidle-shift = <8>;
15087 + reg = <0x4a004140 0x4>;
15088 + bit-mask = <0x3f>;
15089 + index-starts-at-one;
15090 + ti,autoidle-low;
15091 +};
15092 +
15093 +dpll_core_h14x2_ck: dpll_core_h14x2_ck@4a004144 {
15094 + #clock-cells = <0>;
15095 + compatible = "ti,divider-clock";
15096 + clocks = <&dpll_core_x2_ck>;
15097 + ti,autoidle-shift = <8>;
15098 + reg = <0x4a004144 0x4>;
15099 + bit-mask = <0x3f>;
15100 + index-starts-at-one;
15101 + ti,autoidle-low;
15102 +};
15103 +
15104 +dpll_core_h22x2_ck: dpll_core_h22x2_ck@4a004154 {
15105 + #clock-cells = <0>;
15106 + compatible = "ti,divider-clock";
15107 + clocks = <&dpll_core_x2_ck>;
15108 + ti,autoidle-shift = <8>;
15109 + reg = <0x4a004154 0x4>;
15110 + bit-mask = <0x3f>;
15111 + index-starts-at-one;
15112 + ti,autoidle-low;
15113 +};
15114 +
15115 +dpll_core_h23x2_ck: dpll_core_h23x2_ck@4a004158 {
15116 + #clock-cells = <0>;
15117 + compatible = "ti,divider-clock";
15118 + clocks = <&dpll_core_x2_ck>;
15119 + ti,autoidle-shift = <8>;
15120 + reg = <0x4a004158 0x4>;
15121 + bit-mask = <0x3f>;
15122 + index-starts-at-one;
15123 + ti,autoidle-low;
15124 +};
15125 +
15126 +dpll_core_h24x2_ck: dpll_core_h24x2_ck@4a00415c {
15127 + #clock-cells = <0>;
15128 + compatible = "ti,divider-clock";
15129 + clocks = <&dpll_core_x2_ck>;
15130 + ti,autoidle-shift = <8>;
15131 + reg = <0x4a00415c 0x4>;
15132 + bit-mask = <0x3f>;
15133 + index-starts-at-one;
15134 + ti,autoidle-low;
15135 +};
15136 +
15137 +dpll_core_m2_ck: dpll_core_m2_ck@4a004130 {
15138 + #clock-cells = <0>;
15139 + compatible = "ti,divider-clock";
15140 + clocks = <&dpll_core_ck>;
15141 + ti,autoidle-shift = <8>;
15142 + reg = <0x4a004130 0x4>;
15143 + bit-mask = <0x1f>;
15144 + index-starts-at-one;
15145 + ti,autoidle-low;
15146 +};
15147 +
15148 +dpll_core_m3x2_ck: dpll_core_m3x2_ck@4a004134 {
15149 + #clock-cells = <0>;
15150 + compatible = "ti,divider-clock";
15151 + clocks = <&dpll_core_x2_ck>;
15152 + ti,autoidle-shift = <8>;
15153 + reg = <0x4a004134 0x4>;
15154 + bit-mask = <0x1f>;
15155 + index-starts-at-one;
15156 + ti,autoidle-low;
15157 +};
15158 +
15159 +iva_dpll_hs_clk_div: iva_dpll_hs_clk_div {
15160 + #clock-cells = <0>;
15161 + compatible = "fixed-factor-clock";
15162 + clocks = <&dpll_core_h12x2_ck>;
15163 + clock-mult = <1>;
15164 + clock-div = <1>;
15165 +};
15166 +
15167 +dpll_iva_ck: dpll_iva_ck@4a0041a0 {
15168 + #clock-cells = <0>;
15169 + compatible = "ti,omap4-dpll-clock";
15170 + clocks = <&sys_clkin>, <&iva_dpll_hs_clk_div>;
15171 + reg = <0x4a0041a0 0x4>, <0x4a0041a4 0x4>, <0x4a0041a8 0x4>, <0x4a0041ac 0x4>;
15172 + reg-names = "control", "idlest", "autoidle", "mult-div1";
15173 +};
15174 +
15175 +dpll_iva_x2_ck: dpll_iva_x2_ck {
15176 + #clock-cells = <0>;
15177 + compatible = "ti,omap4-dpll-x2-clock";
15178 + clocks = <&dpll_iva_ck>;
15179 +};
15180 +
15181 +dpll_iva_h11x2_ck: dpll_iva_h11x2_ck@4a0041b8 {
15182 + #clock-cells = <0>;
15183 + compatible = "ti,divider-clock";
15184 + clocks = <&dpll_iva_x2_ck>;
15185 + ti,autoidle-shift = <8>;
15186 + reg = <0x4a0041b8 0x4>;
15187 + bit-mask = <0x3f>;
15188 + index-starts-at-one;
15189 + ti,autoidle-low;
15190 +};
15191 +
15192 +dpll_iva_h12x2_ck: dpll_iva_h12x2_ck@4a0041bc {
15193 + #clock-cells = <0>;
15194 + compatible = "ti,divider-clock";
15195 + clocks = <&dpll_iva_x2_ck>;
15196 + ti,autoidle-shift = <8>;
15197 + reg = <0x4a0041bc 0x4>;
15198 + bit-mask = <0x3f>;
15199 + index-starts-at-one;
15200 + ti,autoidle-low;
15201 +};
15202 +
15203 +mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div {
15204 + #clock-cells = <0>;
15205 + compatible = "fixed-factor-clock";
15206 + clocks = <&dpll_core_h12x2_ck>;
15207 + clock-mult = <1>;
15208 + clock-div = <1>;
15209 +};
15210 +
15211 +dpll_mpu_ck: dpll_mpu_ck@4a004160 {
15212 + #clock-cells = <0>;
15213 + compatible = "ti,omap4-dpll-clock";
15214 + clocks = <&sys_clkin>, <&mpu_dpll_hs_clk_div>;
15215 + reg = <0x4a004160 0x4>, <0x4a004164 0x4>, <0x4a004168 0x4>, <0x4a00416c 0x4>;
15216 + reg-names = "control", "idlest", "autoidle", "mult-div1";
15217 +};
15218 +
15219 +dpll_mpu_m2_ck: dpll_mpu_m2_ck@4a004170 {
15220 + #clock-cells = <0>;
15221 + compatible = "ti,divider-clock";
15222 + clocks = <&dpll_mpu_ck>;
15223 + ti,autoidle-shift = <8>;
15224 + reg = <0x4a004170 0x4>;
15225 + bit-mask = <0x1f>;
15226 + index-starts-at-one;
15227 + ti,autoidle-low;
15228 +};
15229 +
15230 +per_dpll_hs_clk_div: per_dpll_hs_clk_div {
15231 + #clock-cells = <0>;
15232 + compatible = "fixed-factor-clock";
15233 + clocks = <&dpll_abe_m3x2_ck>;
15234 + clock-mult = <1>;
15235 + clock-div = <2>;
15236 +};
15237 +
15238 +dpll_per_ck: dpll_per_ck@4a008140 {
15239 + #clock-cells = <0>;
15240 + compatible = "ti,omap4-dpll-clock";
15241 + clocks = <&sys_clkin>, <&per_dpll_hs_clk_div>;
15242 + reg = <0x4a008140 0x4>, <0x4a008144 0x4>, <0x4a008148 0x4>, <0x4a00814c 0x4>;
15243 + reg-names = "control", "idlest", "autoidle", "mult-div1";
15244 +};
15245 +
15246 +dpll_per_x2_ck: dpll_per_x2_ck {
15247 + #clock-cells = <0>;
15248 + compatible = "ti,omap4-dpll-x2-clock";
15249 + clocks = <&dpll_per_ck>;
15250 +};
15251 +
15252 +dpll_per_h11x2_ck: dpll_per_h11x2_ck@4a008158 {
15253 + #clock-cells = <0>;
15254 + compatible = "ti,divider-clock";
15255 + clocks = <&dpll_per_x2_ck>;
15256 + ti,autoidle-shift = <8>;
15257 + reg = <0x4a008158 0x4>;
15258 + bit-mask = <0x3f>;
15259 + index-starts-at-one;
15260 + ti,autoidle-low;
15261 +};
15262 +
15263 +dpll_per_h12x2_ck: dpll_per_h12x2_ck@4a00815c {
15264 + #clock-cells = <0>;
15265 + compatible = "ti,divider-clock";
15266 + clocks = <&dpll_per_x2_ck>;
15267 + ti,autoidle-shift = <8>;
15268 + reg = <0x4a00815c 0x4>;
15269 + bit-mask = <0x3f>;
15270 + index-starts-at-one;
15271 + ti,autoidle-low;
15272 +};
15273 +
15274 +dpll_per_h14x2_ck: dpll_per_h14x2_ck@4a008164 {
15275 + #clock-cells = <0>;
15276 + compatible = "ti,divider-clock";
15277 + clocks = <&dpll_per_x2_ck>;
15278 + ti,autoidle-shift = <8>;
15279 + reg = <0x4a008164 0x4>;
15280 + bit-mask = <0x3f>;
15281 + index-starts-at-one;
15282 + ti,autoidle-low;
15283 +};
15284 +
15285 +dpll_per_m2_ck: dpll_per_m2_ck@4a008150 {
15286 + #clock-cells = <0>;
15287 + compatible = "ti,divider-clock";
15288 + clocks = <&dpll_per_ck>;
15289 + ti,autoidle-shift = <8>;
15290 + reg = <0x4a008150 0x4>;
15291 + bit-mask = <0x1f>;
15292 + index-starts-at-one;
15293 + ti,autoidle-low;
15294 +};
15295 +
15296 +dpll_per_m2x2_ck: dpll_per_m2x2_ck@4a008150 {
15297 + #clock-cells = <0>;
15298 + compatible = "ti,divider-clock";
15299 + clocks = <&dpll_per_x2_ck>;
15300 + ti,autoidle-shift = <8>;
15301 + reg = <0x4a008150 0x4>;
15302 + bit-mask = <0x1f>;
15303 + index-starts-at-one;
15304 + ti,autoidle-low;
15305 +};
15306 +
15307 +dpll_per_m3x2_ck: dpll_per_m3x2_ck@4a008154 {
15308 + #clock-cells = <0>;
15309 + compatible = "ti,divider-clock";
15310 + clocks = <&dpll_per_x2_ck>;
15311 + ti,autoidle-shift = <8>;
15312 + reg = <0x4a008154 0x4>;
15313 + bit-mask = <0x1f>;
15314 + index-starts-at-one;
15315 + ti,autoidle-low;
15316 +};
15317 +
15318 +dpll_unipro1_ck: dpll_unipro1_ck@4a008200 {
15319 + #clock-cells = <0>;
15320 + compatible = "ti,omap4-dpll-clock";
15321 + clocks = <&sys_clkin>, <&sys_clkin>;
15322 + reg = <0x4a008200 0x4>, <0x4a008204 0x4>, <0x4a008208 0x4>, <0x4a00820c 0x4>;
15323 + reg-names = "control", "idlest", "autoidle", "mult-div1";
15324 +};
15325 +
15326 +dpll_unipro1_clkdcoldo: dpll_unipro1_clkdcoldo {
15327 + #clock-cells = <0>;
15328 + compatible = "fixed-factor-clock";
15329 + clocks = <&dpll_unipro1_ck>;
15330 + clock-mult = <1>;
15331 + clock-div = <1>;
15332 +};
15333 +
15334 +dpll_unipro1_m2_ck: dpll_unipro1_m2_ck@4a008210 {
15335 + #clock-cells = <0>;
15336 + compatible = "ti,divider-clock";
15337 + clocks = <&dpll_unipro1_ck>;
15338 + ti,autoidle-shift = <8>;
15339 + reg = <0x4a008210 0x4>;
15340 + bit-mask = <0x7f>;
15341 + index-starts-at-one;
15342 + ti,autoidle-low;
15343 +};
15344 +
15345 +dpll_unipro2_ck: dpll_unipro2_ck@4a0081c0 {
15346 + #clock-cells = <0>;
15347 + compatible = "ti,omap4-dpll-clock";
15348 + clocks = <&sys_clkin>, <&sys_clkin>;
15349 + reg = <0x4a0081c0 0x4>, <0x4a0081c4 0x4>, <0x4a0081c8 0x4>, <0x4a0081cc 0x4>;
15350 + reg-names = "control", "idlest", "autoidle", "mult-div1";
15351 +};
15352 +
15353 +dpll_unipro2_clkdcoldo: dpll_unipro2_clkdcoldo {
15354 + #clock-cells = <0>;
15355 + compatible = "fixed-factor-clock";
15356 + clocks = <&dpll_unipro2_ck>;
15357 + clock-mult = <1>;
15358 + clock-div = <1>;
15359 +};
15360 +
15361 +dpll_unipro2_m2_ck: dpll_unipro2_m2_ck@4a0081d0 {
15362 + #clock-cells = <0>;
15363 + compatible = "ti,divider-clock";
15364 + clocks = <&dpll_unipro2_ck>;
15365 + ti,autoidle-shift = <8>;
15366 + reg = <0x4a0081d0 0x4>;
15367 + bit-mask = <0x7f>;
15368 + index-starts-at-one;
15369 + ti,autoidle-low;
15370 +};
15371 +
15372 +usb_dpll_hs_clk_div: usb_dpll_hs_clk_div {
15373 + #clock-cells = <0>;
15374 + compatible = "fixed-factor-clock";
15375 + clocks = <&dpll_abe_m3x2_ck>;
15376 + clock-mult = <1>;
15377 + clock-div = <3>;
15378 +};
15379 +
15380 +dpll_usb_ck: dpll_usb_ck@4a008180 {
15381 + #clock-cells = <0>;
15382 + compatible = "ti,omap4-dpll-j-type-clock";
15383 + clocks = <&sys_clkin>, <&usb_dpll_hs_clk_div>;
15384 + reg = <0x4a008180 0x4>, <0x4a008184 0x4>, <0x4a008188 0x4>, <0x4a00818c 0x4>;
15385 + reg-names = "control", "idlest", "autoidle", "mult-div1";
15386 +};
15387 +
15388 +dpll_usb_clkdcoldo: dpll_usb_clkdcoldo {
15389 + #clock-cells = <0>;
15390 + compatible = "fixed-factor-clock";
15391 + clocks = <&dpll_usb_ck>;
15392 + clock-mult = <1>;
15393 + clock-div = <1>;
15394 +};
15395 +
15396 +dpll_usb_m2_ck: dpll_usb_m2_ck@4a008190 {
15397 + #clock-cells = <0>;
15398 + compatible = "ti,divider-clock";
15399 + clocks = <&dpll_usb_ck>;
15400 + ti,autoidle-shift = <8>;
15401 + reg = <0x4a008190 0x4>;
15402 + bit-mask = <0x7f>;
15403 + index-starts-at-one;
15404 + ti,autoidle-low;
15405 +};
15406 +
15407 +dss_syc_gfclk_div: dss_syc_gfclk_div {
15408 + #clock-cells = <0>;
15409 + compatible = "fixed-factor-clock";
15410 + clocks = <&sys_clkin>;
15411 + clock-mult = <1>;
15412 + clock-div = <1>;
15413 +};
15414 +
15415 +func_128m_clk: func_128m_clk {
15416 + #clock-cells = <0>;
15417 + compatible = "fixed-factor-clock";
15418 + clocks = <&dpll_per_h11x2_ck>;
15419 + clock-mult = <1>;
15420 + clock-div = <2>;
15421 +};
15422 +
15423 +func_12m_fclk: func_12m_fclk {
15424 + #clock-cells = <0>;
15425 + compatible = "fixed-factor-clock";
15426 + clocks = <&dpll_per_m2x2_ck>;
15427 + clock-mult = <1>;
15428 + clock-div = <16>;
15429 +};
15430 +
15431 +func_24m_clk: func_24m_clk {
15432 + #clock-cells = <0>;
15433 + compatible = "fixed-factor-clock";
15434 + clocks = <&dpll_per_m2_ck>;
15435 + clock-mult = <1>;
15436 + clock-div = <4>;
15437 +};
15438 +
15439 +func_48m_fclk: func_48m_fclk {
15440 + #clock-cells = <0>;
15441 + compatible = "fixed-factor-clock";
15442 + clocks = <&dpll_per_m2x2_ck>;
15443 + clock-mult = <1>;
15444 + clock-div = <4>;
15445 +};
15446 +
15447 +func_96m_fclk: func_96m_fclk {
15448 + #clock-cells = <0>;
15449 + compatible = "fixed-factor-clock";
15450 + clocks = <&dpll_per_m2x2_ck>;
15451 + clock-mult = <1>;
15452 + clock-div = <2>;
15453 +};
15454 +
15455 +l3_iclk_div: l3_iclk_div {
15456 + #clock-cells = <0>;
15457 + compatible = "fixed-factor-clock";
15458 + clocks = <&dpll_core_h12x2_ck>;
15459 + clock-mult = <1>;
15460 + clock-div = <1>;
15461 +};
15462 +
15463 +gpu_l3_iclk: gpu_l3_iclk {
15464 + #clock-cells = <0>;
15465 + compatible = "fixed-factor-clock";
15466 + clocks = <&l3_iclk_div>;
15467 + clock-mult = <1>;
15468 + clock-div = <1>;
15469 +};
15470 +
15471 +l3init_60m_fclk: l3init_60m_fclk@4a008104 {
15472 + #clock-cells = <0>;
15473 + compatible = "divider-clock";
15474 + clocks = <&dpll_usb_m2_ck>;
15475 + reg = <0x4a008104 0x4>;
15476 + table = < 1 0 >, < 8 1 >;
15477 + bit-mask = <0x1>;
15478 +};
15479 +
15480 +wkupaon_iclk_mux: wkupaon_iclk_mux@4ae06108 {
15481 + #clock-cells = <0>;
15482 + compatible = "mux-clock";
15483 + clocks = <&sys_clkin>, <&abe_lp_clk_div>;
15484 + reg = <0x4ae06108 0x4>;
15485 + bit-mask = <0x1>;
15486 +};
15487 +
15488 +l3instr_ts_gclk_div: l3instr_ts_gclk_div {
15489 + #clock-cells = <0>;
15490 + compatible = "fixed-factor-clock";
15491 + clocks = <&wkupaon_iclk_mux>;
15492 + clock-mult = <1>;
15493 + clock-div = <1>;
15494 +};
15495 +
15496 +l4_root_clk_div: l4_root_clk_div {
15497 + #clock-cells = <0>;
15498 + compatible = "fixed-factor-clock";
15499 + clocks = <&l3_iclk_div>;
15500 + clock-mult = <1>;
15501 + clock-div = <1>;
15502 +};
15503 +
15504 +dss_32khz_clk: dss_32khz_clk@4a009420 {
15505 + #clock-cells = <0>;
15506 + compatible = "gate-clock";
15507 + clocks = <&sys_32k_ck>;
15508 + bit-shift = <11>;
15509 + reg = <0x4a009420 0x4>;
15510 +};
15511 +
15512 +dss_48mhz_clk: dss_48mhz_clk@4a009420 {
15513 + #clock-cells = <0>;
15514 + compatible = "gate-clock";
15515 + clocks = <&func_48m_fclk>;
15516 + bit-shift = <9>;
15517 + reg = <0x4a009420 0x4>;
15518 +};
15519 +
15520 +dss_dss_clk: dss_dss_clk@4a009420 {
15521 + #clock-cells = <0>;
15522 + compatible = "gate-clock";
15523 + clocks = <&dpll_per_h12x2_ck>;
15524 + bit-shift = <8>;
15525 + reg = <0x4a009420 0x4>;
15526 +};
15527 +
15528 +dss_sys_clk: dss_sys_clk@4a009420 {
15529 + #clock-cells = <0>;
15530 + compatible = "gate-clock";
15531 + clocks = <&dss_syc_gfclk_div>;
15532 + bit-shift = <10>;
15533 + reg = <0x4a009420 0x4>;
15534 +};
15535 +
15536 +gpio1_dbclk: gpio1_dbclk@4ae07938 {
15537 + #clock-cells = <0>;
15538 + compatible = "gate-clock";
15539 + clocks = <&sys_32k_ck>;
15540 + bit-shift = <8>;
15541 + reg = <0x4ae07938 0x4>;
15542 +};
15543 +
15544 +gpio2_dbclk: gpio2_dbclk@4a009060 {
15545 + #clock-cells = <0>;
15546 + compatible = "gate-clock";
15547 + clocks = <&sys_32k_ck>;
15548 + bit-shift = <8>;
15549 + reg = <0x4a009060 0x4>;
15550 +};
15551 +
15552 +gpio3_dbclk: gpio3_dbclk@4a009068 {
15553 + #clock-cells = <0>;
15554 + compatible = "gate-clock";
15555 + clocks = <&sys_32k_ck>;
15556 + bit-shift = <8>;
15557 + reg = <0x4a009068 0x4>;
15558 +};
15559 +
15560 +gpio4_dbclk: gpio4_dbclk@4a009070 {
15561 + #clock-cells = <0>;
15562 + compatible = "gate-clock";
15563 + clocks = <&sys_32k_ck>;
15564 + bit-shift = <8>;
15565 + reg = <0x4a009070 0x4>;
15566 +};
15567 +
15568 +gpio5_dbclk: gpio5_dbclk@4a009078 {
15569 + #clock-cells = <0>;
15570 + compatible = "gate-clock";
15571 + clocks = <&sys_32k_ck>;
15572 + bit-shift = <8>;
15573 + reg = <0x4a009078 0x4>;
15574 +};
15575 +
15576 +gpio6_dbclk: gpio6_dbclk@4a009080 {
15577 + #clock-cells = <0>;
15578 + compatible = "gate-clock";
15579 + clocks = <&sys_32k_ck>;
15580 + bit-shift = <8>;
15581 + reg = <0x4a009080 0x4>;
15582 +};
15583 +
15584 +gpio7_dbclk: gpio7_dbclk@4a009110 {
15585 + #clock-cells = <0>;
15586 + compatible = "gate-clock";
15587 + clocks = <&sys_32k_ck>;
15588 + bit-shift = <8>;
15589 + reg = <0x4a009110 0x4>;
15590 +};
15591 +
15592 +gpio8_dbclk: gpio8_dbclk@4a009118 {
15593 + #clock-cells = <0>;
15594 + compatible = "gate-clock";
15595 + clocks = <&sys_32k_ck>;
15596 + bit-shift = <8>;
15597 + reg = <0x4a009118 0x4>;
15598 +};
15599 +
15600 +iss_ctrlclk: iss_ctrlclk@4a009320 {
15601 + #clock-cells = <0>;
15602 + compatible = "gate-clock";
15603 + clocks = <&func_96m_fclk>;
15604 + bit-shift = <8>;
15605 + reg = <0x4a009320 0x4>;
15606 +};
15607 +
15608 +lli_txphy_clk: lli_txphy_clk@4a008f20 {
15609 + #clock-cells = <0>;
15610 + compatible = "gate-clock";
15611 + clocks = <&dpll_unipro1_clkdcoldo>;
15612 + bit-shift = <8>;
15613 + reg = <0x4a008f20 0x4>;
15614 +};
15615 +
15616 +lli_txphy_ls_clk: lli_txphy_ls_clk@4a008f20 {
15617 + #clock-cells = <0>;
15618 + compatible = "gate-clock";
15619 + clocks = <&dpll_unipro1_m2_ck>;
15620 + bit-shift = <9>;
15621 + reg = <0x4a008f20 0x4>;
15622 +};
15623 +
15624 +mmc1_32khz_clk: mmc1_32khz_clk@4a009628 {
15625 + #clock-cells = <0>;
15626 + compatible = "gate-clock";
15627 + clocks = <&sys_32k_ck>;
15628 + bit-shift = <8>;
15629 + reg = <0x4a009628 0x4>;
15630 +};
15631 +
15632 +sata_ref_clk: sata_ref_clk@4a009688 {
15633 + #clock-cells = <0>;
15634 + compatible = "gate-clock";
15635 + clocks = <&sys_clkin>;
15636 + bit-shift = <8>;
15637 + reg = <0x4a009688 0x4>;
15638 +};
15639 +
15640 +slimbus1_slimbus_clk: slimbus1_slimbus_clk@4a004560 {
15641 + #clock-cells = <0>;
15642 + compatible = "gate-clock";
15643 + clocks = <&slimbus_clk>;
15644 + bit-shift = <11>;
15645 + reg = <0x4a004560 0x4>;
15646 +};
15647 +
15648 +usb_host_hs_hsic480m_p1_clk: usb_host_hs_hsic480m_p1_clk@4a009658 {
15649 + #clock-cells = <0>;
15650 + compatible = "gate-clock";
15651 + clocks = <&dpll_usb_m2_ck>;
15652 + bit-shift = <13>;
15653 + reg = <0x4a009658 0x4>;
15654 +};
15655 +
15656 +usb_host_hs_hsic480m_p2_clk: usb_host_hs_hsic480m_p2_clk@4a009658 {
15657 + #clock-cells = <0>;
15658 + compatible = "gate-clock";
15659 + clocks = <&dpll_usb_m2_ck>;
15660 + bit-shift = <14>;
15661 + reg = <0x4a009658 0x4>;
15662 +};
15663 +
15664 +usb_host_hs_hsic480m_p3_clk: usb_host_hs_hsic480m_p3_clk@4a009658 {
15665 + #clock-cells = <0>;
15666 + compatible = "gate-clock";
15667 + clocks = <&dpll_usb_m2_ck>;
15668 + bit-shift = <7>;
15669 + reg = <0x4a009658 0x4>;
15670 +};
15671 +
15672 +usb_host_hs_hsic60m_p1_clk: usb_host_hs_hsic60m_p1_clk@4a009658 {
15673 + #clock-cells = <0>;
15674 + compatible = "gate-clock";
15675 + clocks = <&l3init_60m_fclk>;
15676 + bit-shift = <11>;
15677 + reg = <0x4a009658 0x4>;
15678 +};
15679 +
15680 +usb_host_hs_hsic60m_p2_clk: usb_host_hs_hsic60m_p2_clk@4a009658 {
15681 + #clock-cells = <0>;
15682 + compatible = "gate-clock";
15683 + clocks = <&l3init_60m_fclk>;
15684 + bit-shift = <12>;
15685 + reg = <0x4a009658 0x4>;
15686 +};
15687 +
15688 +usb_host_hs_hsic60m_p3_clk: usb_host_hs_hsic60m_p3_clk@4a009658 {
15689 + #clock-cells = <0>;
15690 + compatible = "gate-clock";
15691 + clocks = <&l3init_60m_fclk>;
15692 + bit-shift = <6>;
15693 + reg = <0x4a009658 0x4>;
15694 +};
15695 +
15696 +utmi_p1_gfclk: utmi_p1_gfclk@4a009658 {
15697 + #clock-cells = <0>;
15698 + compatible = "mux-clock";
15699 + clocks = <&l3init_60m_fclk>, <&xclk60mhsp1_ck>;
15700 + bit-shift = <24>;
15701 + reg = <0x4a009658 0x4>;
15702 + bit-mask = <0x1>;
15703 +};
15704 +
15705 +usb_host_hs_utmi_p1_clk: usb_host_hs_utmi_p1_clk@4a009658 {
15706 + #clock-cells = <0>;
15707 + compatible = "gate-clock";
15708 + clocks = <&utmi_p1_gfclk>;
15709 + bit-shift = <8>;
15710 + reg = <0x4a009658 0x4>;
15711 +};
15712 +
15713 +utmi_p2_gfclk: utmi_p2_gfclk@4a009658 {
15714 + #clock-cells = <0>;
15715 + compatible = "mux-clock";
15716 + clocks = <&l3init_60m_fclk>, <&xclk60mhsp2_ck>;
15717 + bit-shift = <25>;
15718 + reg = <0x4a009658 0x4>;
15719 + bit-mask = <0x1>;
15720 +};
15721 +
15722 +usb_host_hs_utmi_p2_clk: usb_host_hs_utmi_p2_clk@4a009658 {
15723 + #clock-cells = <0>;
15724 + compatible = "gate-clock";
15725 + clocks = <&utmi_p2_gfclk>;
15726 + bit-shift = <9>;
15727 + reg = <0x4a009658 0x4>;
15728 +};
15729 +
15730 +usb_host_hs_utmi_p3_clk: usb_host_hs_utmi_p3_clk@4a009658 {
15731 + #clock-cells = <0>;
15732 + compatible = "gate-clock";
15733 + clocks = <&l3init_60m_fclk>;
15734 + bit-shift = <10>;
15735 + reg = <0x4a009658 0x4>;
15736 +};
15737 +
15738 +usb_otg_ss_refclk960m: usb_otg_ss_refclk960m@4a0096f0 {
15739 + #clock-cells = <0>;
15740 + compatible = "gate-clock";
15741 + clocks = <&dpll_usb_clkdcoldo>;
15742 + bit-shift = <8>;
15743 + reg = <0x4a0096f0 0x4>;
15744 +};
15745 +
15746 +usb_phy_cm_clk32k: usb_phy_cm_clk32k@4a008640 {
15747 + #clock-cells = <0>;
15748 + compatible = "gate-clock";
15749 + clocks = <&sys_32k_ck>;
15750 + bit-shift = <8>;
15751 + reg = <0x4a008640 0x4>;
15752 +};
15753 +
15754 +usb_tll_hs_usb_ch0_clk: usb_tll_hs_usb_ch0_clk@4a009668 {
15755 + #clock-cells = <0>;
15756 + compatible = "gate-clock";
15757 + clocks = <&l3init_60m_fclk>;
15758 + bit-shift = <8>;
15759 + reg = <0x4a009668 0x4>;
15760 +};
15761 +
15762 +usb_tll_hs_usb_ch1_clk: usb_tll_hs_usb_ch1_clk@4a009668 {
15763 + #clock-cells = <0>;
15764 + compatible = "gate-clock";
15765 + clocks = <&l3init_60m_fclk>;
15766 + bit-shift = <9>;
15767 + reg = <0x4a009668 0x4>;
15768 +};
15769 +
15770 +usb_tll_hs_usb_ch2_clk: usb_tll_hs_usb_ch2_clk@4a009668 {
15771 + #clock-cells = <0>;
15772 + compatible = "gate-clock";
15773 + clocks = <&l3init_60m_fclk>;
15774 + bit-shift = <10>;
15775 + reg = <0x4a009668 0x4>;
15776 +};
15777 +
15778 +aess_fclk: aess_fclk@4a004528 {
15779 + #clock-cells = <0>;
15780 + compatible = "divider-clock";
15781 + clocks = <&abe_clk>;
15782 + bit-shift = <24>;
15783 + reg = <0x4a004528 0x4>;
15784 + bit-mask = <0x1>;
15785 +};
15786 +
15787 +dmic_sync_mux_ck: dmic_sync_mux_ck@4a004538 {
15788 + #clock-cells = <0>;
15789 + compatible = "mux-clock";
15790 + clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
15791 + bit-shift = <26>;
15792 + reg = <0x4a004538 0x4>;
15793 + bit-mask = <0x3>;
15794 +};
15795 +
15796 +dmic_gfclk: dmic_gfclk@4a004538 {
15797 + #clock-cells = <0>;
15798 + compatible = "mux-clock";
15799 + clocks = <&dmic_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
15800 + bit-shift = <24>;
15801 + reg = <0x4a004538 0x4>;
15802 + bit-mask = <0x3>;
15803 +};
15804 +
15805 +fdif_fclk: fdif_fclk@4a009328 {
15806 + #clock-cells = <0>;
15807 + compatible = "divider-clock";
15808 + clocks = <&dpll_per_h11x2_ck>;
15809 + bit-shift = <24>;
15810 + reg = <0x4a009328 0x4>;
15811 + bit-mask = <0x1>;
15812 +};
15813 +
15814 +gpu_core_gclk_mux: gpu_core_gclk_mux@4a009520 {
15815 + #clock-cells = <0>;
15816 + compatible = "mux-clock";
15817 + clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>;
15818 + bit-shift = <24>;
15819 + reg = <0x4a009520 0x4>;
15820 + bit-mask = <0x1>;
15821 +};
15822 +
15823 +gpu_hyd_gclk_mux: gpu_hyd_gclk_mux@4a009520 {
15824 + #clock-cells = <0>;
15825 + compatible = "mux-clock";
15826 + clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>;
15827 + bit-shift = <25>;
15828 + reg = <0x4a009520 0x4>;
15829 + bit-mask = <0x1>;
15830 +};
15831 +
15832 +hsi_fclk: hsi_fclk@4a009638 {
15833 + #clock-cells = <0>;
15834 + compatible = "divider-clock";
15835 + clocks = <&dpll_per_m2x2_ck>;
15836 + bit-shift = <24>;
15837 + reg = <0x4a009638 0x4>;
15838 + bit-mask = <0x1>;
15839 +};
15840 +
15841 +mcasp_sync_mux_ck: mcasp_sync_mux_ck@4a004540 {
15842 + #clock-cells = <0>;
15843 + compatible = "mux-clock";
15844 + clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
15845 + bit-shift = <26>;
15846 + reg = <0x4a004540 0x4>;
15847 + bit-mask = <0x3>;
15848 +};
15849 +
15850 +mcasp_gfclk: mcasp_gfclk@4a004540 {
15851 + #clock-cells = <0>;
15852 + compatible = "mux-clock";
15853 + clocks = <&mcasp_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
15854 + bit-shift = <24>;
15855 + reg = <0x4a004540 0x4>;
15856 + bit-mask = <0x3>;
15857 +};
15858 +
15859 +mcbsp1_sync_mux_ck: mcbsp1_sync_mux_ck@4a004548 {
15860 + #clock-cells = <0>;
15861 + compatible = "mux-clock";
15862 + clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
15863 + bit-shift = <26>;
15864 + reg = <0x4a004548 0x4>;
15865 + bit-mask = <0x3>;
15866 +};
15867 +
15868 +mcbsp1_gfclk: mcbsp1_gfclk@4a004548 {
15869 + #clock-cells = <0>;
15870 + compatible = "mux-clock";
15871 + clocks = <&mcbsp1_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
15872 + bit-shift = <24>;
15873 + reg = <0x4a004548 0x4>;
15874 + bit-mask = <0x3>;
15875 +};
15876 +
15877 +mcbsp2_sync_mux_ck: mcbsp2_sync_mux_ck@4a004550 {
15878 + #clock-cells = <0>;
15879 + compatible = "mux-clock";
15880 + clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
15881 + bit-shift = <26>;
15882 + reg = <0x4a004550 0x4>;
15883 + bit-mask = <0x3>;
15884 +};
15885 +
15886 +mcbsp2_gfclk: mcbsp2_gfclk@4a004550 {
15887 + #clock-cells = <0>;
15888 + compatible = "mux-clock";
15889 + clocks = <&mcbsp2_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
15890 + bit-shift = <24>;
15891 + reg = <0x4a004550 0x4>;
15892 + bit-mask = <0x3>;
15893 +};
15894 +
15895 +mcbsp3_sync_mux_ck: mcbsp3_sync_mux_ck@4a004558 {
15896 + #clock-cells = <0>;
15897 + compatible = "mux-clock";
15898 + clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
15899 + bit-shift = <26>;
15900 + reg = <0x4a004558 0x4>;
15901 + bit-mask = <0x3>;
15902 +};
15903 +
15904 +mcbsp3_gfclk: mcbsp3_gfclk@4a004558 {
15905 + #clock-cells = <0>;
15906 + compatible = "mux-clock";
15907 + clocks = <&mcbsp3_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
15908 + bit-shift = <24>;
15909 + reg = <0x4a004558 0x4>;
15910 + bit-mask = <0x3>;
15911 +};
15912 +
15913 +mmc1_fclk_mux: mmc1_fclk_mux@4a009628 {
15914 + #clock-cells = <0>;
15915 + compatible = "mux-clock";
15916 + clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
15917 + bit-shift = <24>;
15918 + reg = <0x4a009628 0x4>;
15919 + bit-mask = <0x1>;
15920 +};
15921 +
15922 +mmc1_fclk: mmc1_fclk@4a009628 {
15923 + #clock-cells = <0>;
15924 + compatible = "divider-clock";
15925 + clocks = <&mmc1_fclk_mux>;
15926 + bit-shift = <25>;
15927 + reg = <0x4a009628 0x4>;
15928 + bit-mask = <0x1>;
15929 +};
15930 +
15931 +mmc2_fclk_mux: mmc2_fclk_mux@4a009630 {
15932 + #clock-cells = <0>;
15933 + compatible = "mux-clock";
15934 + clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
15935 + bit-shift = <24>;
15936 + reg = <0x4a009630 0x4>;
15937 + bit-mask = <0x1>;
15938 +};
15939 +
15940 +mmc2_fclk: mmc2_fclk@4a009630 {
15941 + #clock-cells = <0>;
15942 + compatible = "divider-clock";
15943 + clocks = <&mmc2_fclk_mux>;
15944 + bit-shift = <25>;
15945 + reg = <0x4a009630 0x4>;
15946 + bit-mask = <0x1>;
15947 +};
15948 +
15949 +timer10_gfclk_mux: timer10_gfclk_mux@4a009028 {
15950 + #clock-cells = <0>;
15951 + compatible = "mux-clock";
15952 + clocks = <&sys_clkin>, <&sys_32k_ck>;
15953 + bit-shift = <24>;
15954 + reg = <0x4a009028 0x4>;
15955 + bit-mask = <0x1>;
15956 +};
15957 +
15958 +timer11_gfclk_mux: timer11_gfclk_mux@4a009030 {
15959 + #clock-cells = <0>;
15960 + compatible = "mux-clock";
15961 + clocks = <&sys_clkin>, <&sys_32k_ck>;
15962 + bit-shift = <24>;
15963 + reg = <0x4a009030 0x4>;
15964 + bit-mask = <0x1>;
15965 +};
15966 +
15967 +timer1_gfclk_mux: timer1_gfclk_mux@4ae07940 {
15968 + #clock-cells = <0>;
15969 + compatible = "mux-clock";
15970 + clocks = <&sys_clkin>, <&sys_32k_ck>;
15971 + bit-shift = <24>;
15972 + reg = <0x4ae07940 0x4>;
15973 + bit-mask = <0x1>;
15974 +};
15975 +
15976 +timer2_gfclk_mux: timer2_gfclk_mux@4a009038 {
15977 + #clock-cells = <0>;
15978 + compatible = "mux-clock";
15979 + clocks = <&sys_clkin>, <&sys_32k_ck>;
15980 + bit-shift = <24>;
15981 + reg = <0x4a009038 0x4>;
15982 + bit-mask = <0x1>;
15983 +};
15984 +
15985 +timer3_gfclk_mux: timer3_gfclk_mux@4a009040 {
15986 + #clock-cells = <0>;
15987 + compatible = "mux-clock";
15988 + clocks = <&sys_clkin>, <&sys_32k_ck>;
15989 + bit-shift = <24>;
15990 + reg = <0x4a009040 0x4>;
15991 + bit-mask = <0x1>;
15992 +};
15993 +
15994 +timer4_gfclk_mux: timer4_gfclk_mux@4a009048 {
15995 + #clock-cells = <0>;
15996 + compatible = "mux-clock";
15997 + clocks = <&sys_clkin>, <&sys_32k_ck>;
15998 + bit-shift = <24>;
15999 + reg = <0x4a009048 0x4>;
16000 + bit-mask = <0x1>;
16001 +};
16002 +
16003 +timer5_gfclk_mux: timer5_gfclk_mux@4a004568 {
16004 + #clock-cells = <0>;
16005 + compatible = "mux-clock";
16006 + clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
16007 + bit-shift = <24>;
16008 + reg = <0x4a004568 0x4>;
16009 + bit-mask = <0x1>;
16010 +};
16011 +
16012 +timer6_gfclk_mux: timer6_gfclk_mux@4a004570 {
16013 + #clock-cells = <0>;
16014 + compatible = "mux-clock";
16015 + clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
16016 + bit-shift = <24>;
16017 + reg = <0x4a004570 0x4>;
16018 + bit-mask = <0x1>;
16019 +};
16020 +
16021 +timer7_gfclk_mux: timer7_gfclk_mux@4a004578 {
16022 + #clock-cells = <0>;
16023 + compatible = "mux-clock";
16024 + clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
16025 + bit-shift = <24>;
16026 + reg = <0x4a004578 0x4>;
16027 + bit-mask = <0x1>;
16028 +};
16029 +
16030 +timer8_gfclk_mux: timer8_gfclk_mux@4a004580 {
16031 + #clock-cells = <0>;
16032 + compatible = "mux-clock";
16033 + clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
16034 + bit-shift = <24>;
16035 + reg = <0x4a004580 0x4>;
16036 + bit-mask = <0x1>;
16037 +};
16038 +
16039 +timer9_gfclk_mux: timer9_gfclk_mux@4a009050 {
16040 + #clock-cells = <0>;
16041 + compatible = "mux-clock";
16042 + clocks = <&sys_clkin>, <&sys_32k_ck>;
16043 + bit-shift = <24>;
16044 + reg = <0x4a009050 0x4>;
16045 + bit-mask = <0x1>;
16046 +};
16047 +
16048 +auxclk0_src_mux_ck: auxclk0_src_mux_ck@4ae0a310 {
16049 + #clock-cells = <0>;
16050 + compatible = "mux-clock";
16051 + clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
16052 + bit-shift = <1>;
16053 + reg = <0x4ae0a310 0x4>;
16054 + bit-mask = <0x3>;
16055 +};
16056 +
16057 +auxclk0_src_ck: auxclk0_src_ck@4ae0a310 {
16058 + #clock-cells = <0>;
16059 + compatible = "gate-clock";
16060 + clocks = <&auxclk0_src_mux_ck>;
16061 + bit-shift = <8>;
16062 + reg = <0x4ae0a310 0x4>;
16063 +};
16064 +
16065 +auxclk0_ck: auxclk0_ck@4ae0a310 {
16066 + #clock-cells = <0>;
16067 + compatible = "divider-clock";
16068 + clocks = <&auxclk0_src_ck>;
16069 + bit-shift = <16>;
16070 + reg = <0x4ae0a310 0x4>;
16071 + bit-mask = <0xf>;
16072 +};
16073 +
16074 +auxclk1_src_mux_ck: auxclk1_src_mux_ck@4ae0a314 {
16075 + #clock-cells = <0>;
16076 + compatible = "mux-clock";
16077 + clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
16078 + bit-shift = <1>;
16079 + reg = <0x4ae0a314 0x4>;
16080 + bit-mask = <0x3>;
16081 +};
16082 +
16083 +auxclk1_src_ck: auxclk1_src_ck@4ae0a314 {
16084 + #clock-cells = <0>;
16085 + compatible = "gate-clock";
16086 + clocks = <&auxclk1_src_mux_ck>;
16087 + bit-shift = <8>;
16088 + reg = <0x4ae0a314 0x4>;
16089 +};
16090 +
16091 +auxclk1_ck: auxclk1_ck@4ae0a314 {
16092 + #clock-cells = <0>;
16093 + compatible = "divider-clock";
16094 + clocks = <&auxclk1_src_ck>;
16095 + bit-shift = <16>;
16096 + reg = <0x4ae0a314 0x4>;
16097 + bit-mask = <0xf>;
16098 +};
16099 +
16100 +auxclk2_src_mux_ck: auxclk2_src_mux_ck@4ae0a318 {
16101 + #clock-cells = <0>;
16102 + compatible = "mux-clock";
16103 + clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
16104 + bit-shift = <1>;
16105 + reg = <0x4ae0a318 0x4>;
16106 + bit-mask = <0x3>;
16107 +};
16108 +
16109 +auxclk2_src_ck: auxclk2_src_ck@4ae0a318 {
16110 + #clock-cells = <0>;
16111 + compatible = "gate-clock";
16112 + clocks = <&auxclk2_src_mux_ck>;
16113 + bit-shift = <8>;
16114 + reg = <0x4ae0a318 0x4>;
16115 +};
16116 +
16117 +auxclk2_ck: auxclk2_ck@4ae0a318 {
16118 + #clock-cells = <0>;
16119 + compatible = "divider-clock";
16120 + clocks = <&auxclk2_src_ck>;
16121 + bit-shift = <16>;
16122 + reg = <0x4ae0a318 0x4>;
16123 + bit-mask = <0xf>;
16124 +};
16125 +
16126 +auxclk3_src_mux_ck: auxclk3_src_mux_ck@4ae0a31c {
16127 + #clock-cells = <0>;
16128 + compatible = "mux-clock";
16129 + clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
16130 + bit-shift = <1>;
16131 + reg = <0x4ae0a31c 0x4>;
16132 + bit-mask = <0x3>;
16133 +};
16134 +
16135 +auxclk3_src_ck: auxclk3_src_ck@4ae0a31c {
16136 + #clock-cells = <0>;
16137 + compatible = "gate-clock";
16138 + clocks = <&auxclk3_src_mux_ck>;
16139 + bit-shift = <8>;
16140 + reg = <0x4ae0a31c 0x4>;
16141 +};
16142 +
16143 +auxclk3_ck: auxclk3_ck@4ae0a31c {
16144 + #clock-cells = <0>;
16145 + compatible = "divider-clock";
16146 + clocks = <&auxclk3_src_ck>;
16147 + bit-shift = <16>;
16148 + reg = <0x4ae0a31c 0x4>;
16149 + bit-mask = <0xf>;
16150 +};
16151 +
16152 +auxclk4_src_mux_ck: auxclk4_src_mux_ck@4ae0a320 {
16153 + #clock-cells = <0>;
16154 + compatible = "mux-clock";
16155 + clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
16156 + bit-shift = <1>;
16157 + reg = <0x4ae0a320 0x4>;
16158 + bit-mask = <0x3>;
16159 +};
16160 +
16161 +auxclk4_src_ck: auxclk4_src_ck@4ae0a320 {
16162 + #clock-cells = <0>;
16163 + compatible = "gate-clock";
16164 + clocks = <&auxclk4_src_mux_ck>;
16165 + bit-shift = <8>;
16166 + reg = <0x4ae0a320 0x4>;
16167 +};
16168 +
16169 +auxclk4_ck: auxclk4_ck@4ae0a320 {
16170 + #clock-cells = <0>;
16171 + compatible = "divider-clock";
16172 + clocks = <&auxclk4_src_ck>;
16173 + bit-shift = <16>;
16174 + reg = <0x4ae0a320 0x4>;
16175 + bit-mask = <0xf>;
16176 +};
16177 +
16178 +auxclkreq0_ck: auxclkreq0_ck@4ae0a210 {
16179 + #clock-cells = <0>;
16180 + compatible = "mux-clock";
16181 + clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
16182 + bit-shift = <2>;
16183 + reg = <0x4ae0a210 0x4>;
16184 + bit-mask = <0x7>;
16185 +};
16186 +
16187 +auxclkreq1_ck: auxclkreq1_ck@4ae0a214 {
16188 + #clock-cells = <0>;
16189 + compatible = "mux-clock";
16190 + clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
16191 + bit-shift = <2>;
16192 + reg = <0x4ae0a214 0x4>;
16193 + bit-mask = <0x7>;
16194 +};
16195 +
16196 +auxclkreq2_ck: auxclkreq2_ck@4ae0a218 {
16197 + #clock-cells = <0>;
16198 + compatible = "mux-clock";
16199 + clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
16200 + bit-shift = <2>;
16201 + reg = <0x4ae0a218 0x4>;
16202 + bit-mask = <0x7>;
16203 +};
16204 +
16205 +auxclkreq3_ck: auxclkreq3_ck@4ae0a21c {
16206 + #clock-cells = <0>;
16207 + compatible = "mux-clock";
16208 + clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
16209 + bit-shift = <2>;
16210 + reg = <0x4ae0a21c 0x4>;
16211 + bit-mask = <0x7>;
16212 +};
16213 --- a/arch/arm/boot/dts/omap5.dtsi
16214 +++ b/arch/arm/boot/dts/omap5.dtsi
16215 @@ -21,6 +21,11 @@
16216 interrupt-parent = <&gic>;
16217
16218 aliases {
16219 + i2c0 = &i2c1;
16220 + i2c1 = &i2c2;
16221 + i2c2 = &i2c3;
16222 + i2c3 = &i2c4;
16223 + i2c4 = &i2c5;
16224 serial0 = &uart1;
16225 serial1 = &uart2;
16226 serial2 = &uart3;
16227 @@ -33,10 +38,23 @@
16228 #address-cells = <1>;
16229 #size-cells = <0>;
16230
16231 - cpu@0 {
16232 + cpu0: cpu@0 {
16233 device_type = "cpu";
16234 compatible = "arm,cortex-a15";
16235 reg = <0x0>;
16236 +
16237 + operating-points = <
16238 + /* kHz uV */
16239 + 500000 880000
16240 + 1000000 1060000
16241 + 1500000 1250000
16242 + >;
16243 +
16244 + clocks = <&dpll_mpu_ck>;
16245 + clock-names = "cpu";
16246 +
16247 + clock-latency = <300000>; /* From omap-cpufreq driver */
16248 +
16249 };
16250 cpu@1 {
16251 device_type = "cpu";
16252 @@ -52,7 +70,6 @@
16253 <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
16254 <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
16255 <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
16256 - clock-frequency = <6144000>;
16257 };
16258
16259 gic: interrupt-controller@48211000 {
16260 @@ -100,6 +117,8 @@
16261 compatible = "ti,omap-counter32k";
16262 reg = <0x4ae04000 0x40>;
16263 ti,hwmods = "counter_32k";
16264 + clocks = <&wkupaon_iclk_mux>;
16265 + clock-names = "fck";
16266 };
16267
16268 omap5_pmx_core: pinmux@4a002840 {
16269 @@ -129,6 +148,8 @@
16270 #dma-cells = <1>;
16271 #dma-channels = <32>;
16272 #dma-requests = <127>;
16273 + clocks = <&l3_iclk_div>;
16274 + clock-names = "fck";
16275 };
16276
16277 gpio1: gpio@4ae10000 {
16278 @@ -136,6 +157,8 @@
16279 reg = <0x4ae10000 0x200>;
16280 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
16281 ti,hwmods = "gpio1";
16282 + clocks = <&wkupaon_iclk_mux>, <&gpio1_dbclk>;
16283 + clock-names = "fck", "dbclk";
16284 ti,gpio-always-on;
16285 gpio-controller;
16286 #gpio-cells = <2>;
16287 @@ -148,6 +171,8 @@
16288 reg = <0x48055000 0x200>;
16289 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
16290 ti,hwmods = "gpio2";
16291 + clocks = <&l4_root_clk_div>, <&gpio2_dbclk>;
16292 + clock-names = "fck", "dbclk";
16293 gpio-controller;
16294 #gpio-cells = <2>;
16295 interrupt-controller;
16296 @@ -159,6 +184,8 @@
16297 reg = <0x48057000 0x200>;
16298 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
16299 ti,hwmods = "gpio3";
16300 + clocks = <&l4_root_clk_div>, <&gpio3_dbclk>;
16301 + clock-names = "fck", "dbclk";
16302 gpio-controller;
16303 #gpio-cells = <2>;
16304 interrupt-controller;
16305 @@ -170,6 +197,8 @@
16306 reg = <0x48059000 0x200>;
16307 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
16308 ti,hwmods = "gpio4";
16309 + clocks = <&l4_root_clk_div>, <&gpio4_dbclk>;
16310 + clock-names = "fck", "dbclk";
16311 gpio-controller;
16312 #gpio-cells = <2>;
16313 interrupt-controller;
16314 @@ -181,6 +210,8 @@
16315 reg = <0x4805b000 0x200>;
16316 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
16317 ti,hwmods = "gpio5";
16318 + clocks = <&l4_root_clk_div>, <&gpio5_dbclk>;
16319 + clock-names = "fck", "dbclk";
16320 gpio-controller;
16321 #gpio-cells = <2>;
16322 interrupt-controller;
16323 @@ -192,6 +223,8 @@
16324 reg = <0x4805d000 0x200>;
16325 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
16326 ti,hwmods = "gpio6";
16327 + clocks = <&l4_root_clk_div>, <&gpio6_dbclk>;
16328 + clock-names = "fck", "dbclk";
16329 gpio-controller;
16330 #gpio-cells = <2>;
16331 interrupt-controller;
16332 @@ -203,6 +236,8 @@
16333 reg = <0x48051000 0x200>;
16334 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
16335 ti,hwmods = "gpio7";
16336 + clocks = <&l4_root_clk_div>, <&gpio7_dbclk>;
16337 + clock-names = "fck", "dbclk";
16338 gpio-controller;
16339 #gpio-cells = <2>;
16340 interrupt-controller;
16341 @@ -214,6 +249,8 @@
16342 reg = <0x48053000 0x200>;
16343 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
16344 ti,hwmods = "gpio8";
16345 + clocks = <&l4_root_clk_div>, <&gpio8_dbclk>;
16346 + clock-names = "fck", "dbclk";
16347 gpio-controller;
16348 #gpio-cells = <2>;
16349 interrupt-controller;
16350 @@ -238,6 +275,9 @@
16351 #address-cells = <1>;
16352 #size-cells = <0>;
16353 ti,hwmods = "i2c1";
16354 + clocks = <&func_96m_fclk>;
16355 + clock-names = "fck";
16356 + status = "disabled";
16357 };
16358
16359 i2c2: i2c@48072000 {
16360 @@ -247,6 +287,9 @@
16361 #address-cells = <1>;
16362 #size-cells = <0>;
16363 ti,hwmods = "i2c2";
16364 + clocks = <&func_96m_fclk>;
16365 + clock-names = "fck";
16366 + status = "disabled";
16367 };
16368
16369 i2c3: i2c@48060000 {
16370 @@ -256,6 +299,9 @@
16371 #address-cells = <1>;
16372 #size-cells = <0>;
16373 ti,hwmods = "i2c3";
16374 + clocks = <&func_96m_fclk>;
16375 + clock-names = "fck";
16376 + status = "disabled";
16377 };
16378
16379 i2c4: i2c@4807a000 {
16380 @@ -265,6 +311,9 @@
16381 #address-cells = <1>;
16382 #size-cells = <0>;
16383 ti,hwmods = "i2c4";
16384 + clocks = <&func_96m_fclk>;
16385 + clock-names = "fck";
16386 + status = "disabled";
16387 };
16388
16389 i2c5: i2c@4807c000 {
16390 @@ -274,6 +323,9 @@
16391 #address-cells = <1>;
16392 #size-cells = <0>;
16393 ti,hwmods = "i2c5";
16394 + clocks = <&func_96m_fclk>;
16395 + clock-names = "fck";
16396 + status = "disabled";
16397 };
16398
16399 mcspi1: spi@48098000 {
16400 @@ -283,6 +335,8 @@
16401 #address-cells = <1>;
16402 #size-cells = <0>;
16403 ti,hwmods = "mcspi1";
16404 + clocks = <&func_48m_fclk>;
16405 + clock-names = "fck";
16406 ti,spi-num-cs = <4>;
16407 dmas = <&sdma 35>,
16408 <&sdma 36>,
16409 @@ -294,6 +348,7 @@
16410 <&sdma 42>;
16411 dma-names = "tx0", "rx0", "tx1", "rx1",
16412 "tx2", "rx2", "tx3", "rx3";
16413 + status = "disabled";
16414 };
16415
16416 mcspi2: spi@4809a000 {
16417 @@ -303,12 +358,15 @@
16418 #address-cells = <1>;
16419 #size-cells = <0>;
16420 ti,hwmods = "mcspi2";
16421 + clocks = <&func_48m_fclk>;
16422 + clock-names = "fck";
16423 ti,spi-num-cs = <2>;
16424 dmas = <&sdma 43>,
16425 <&sdma 44>,
16426 <&sdma 45>,
16427 <&sdma 46>;
16428 dma-names = "tx0", "rx0", "tx1", "rx1";
16429 + status = "disabled";
16430 };
16431
16432 mcspi3: spi@480b8000 {
16433 @@ -318,9 +376,12 @@
16434 #address-cells = <1>;
16435 #size-cells = <0>;
16436 ti,hwmods = "mcspi3";
16437 + clocks = <&func_48m_fclk>;
16438 + clock-names = "fck";
16439 ti,spi-num-cs = <2>;
16440 dmas = <&sdma 15>, <&sdma 16>;
16441 dma-names = "tx0", "rx0";
16442 + status = "disabled";
16443 };
16444
16445 mcspi4: spi@480ba000 {
16446 @@ -330,9 +391,12 @@
16447 #address-cells = <1>;
16448 #size-cells = <0>;
16449 ti,hwmods = "mcspi4";
16450 + clocks = <&func_48m_fclk>;
16451 + clock-names = "fck";
16452 ti,spi-num-cs = <1>;
16453 dmas = <&sdma 70>, <&sdma 71>;
16454 dma-names = "tx0", "rx0";
16455 + status = "disabled";
16456 };
16457
16458 uart1: serial@4806a000 {
16459 @@ -340,7 +404,10 @@
16460 reg = <0x4806a000 0x100>;
16461 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
16462 ti,hwmods = "uart1";
16463 + clocks = <&func_48m_fclk>;
16464 + clock-names = "fck";
16465 clock-frequency = <48000000>;
16466 + status = "disabled";
16467 };
16468
16469 uart2: serial@4806c000 {
16470 @@ -348,7 +415,10 @@
16471 reg = <0x4806c000 0x100>;
16472 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
16473 ti,hwmods = "uart2";
16474 + clocks = <&func_48m_fclk>;
16475 + clock-names = "fck";
16476 clock-frequency = <48000000>;
16477 + status = "disabled";
16478 };
16479
16480 uart3: serial@48020000 {
16481 @@ -356,7 +426,10 @@
16482 reg = <0x48020000 0x100>;
16483 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
16484 ti,hwmods = "uart3";
16485 + clocks = <&func_48m_fclk>;
16486 + clock-names = "fck";
16487 clock-frequency = <48000000>;
16488 + status = "disabled";
16489 };
16490
16491 uart4: serial@4806e000 {
16492 @@ -364,7 +437,10 @@
16493 reg = <0x4806e000 0x100>;
16494 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
16495 ti,hwmods = "uart4";
16496 + clocks = <&func_48m_fclk>;
16497 + clock-names = "fck";
16498 clock-frequency = <48000000>;
16499 + status = "disabled";
16500 };
16501
16502 uart5: serial@48066000 {
16503 @@ -372,7 +448,10 @@
16504 reg = <0x48066000 0x100>;
16505 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
16506 ti,hwmods = "uart5";
16507 + clocks = <&func_48m_fclk>;
16508 + clock-names = "fck";
16509 clock-frequency = <48000000>;
16510 + status = "disabled";
16511 };
16512
16513 uart6: serial@48068000 {
16514 @@ -380,7 +459,10 @@
16515 reg = <0x48068000 0x100>;
16516 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
16517 ti,hwmods = "uart6";
16518 + clocks = <&func_48m_fclk>;
16519 + clock-names = "fck";
16520 clock-frequency = <48000000>;
16521 + status = "disabled";
16522 };
16523
16524 mmc1: mmc@4809c000 {
16525 @@ -388,6 +470,8 @@
16526 reg = <0x4809c000 0x400>;
16527 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
16528 ti,hwmods = "mmc1";
16529 + clocks = <&mmc1_fclk>, <&mmc1_32khz_clk>;
16530 + clock-names = "fck", "32khz_clk";
16531 ti,dual-volt;
16532 ti,needs-special-reset;
16533 dmas = <&sdma 61>, <&sdma 62>;
16534 @@ -399,6 +483,8 @@
16535 reg = <0x480b4000 0x400>;
16536 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
16537 ti,hwmods = "mmc2";
16538 + clocks = <&mmc2_fclk>;
16539 + clock-names = "fck";
16540 ti,needs-special-reset;
16541 dmas = <&sdma 47>, <&sdma 48>;
16542 dma-names = "tx", "rx";
16543 @@ -409,6 +495,8 @@
16544 reg = <0x480ad000 0x400>;
16545 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
16546 ti,hwmods = "mmc3";
16547 + clocks = <&func_48m_fclk>;
16548 + clock-names = "fck";
16549 ti,needs-special-reset;
16550 dmas = <&sdma 77>, <&sdma 78>;
16551 dma-names = "tx", "rx";
16552 @@ -419,6 +507,8 @@
16553 reg = <0x480d1000 0x400>;
16554 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
16555 ti,hwmods = "mmc4";
16556 + clocks = <&func_48m_fclk>;
16557 + clock-names = "fck";
16558 ti,needs-special-reset;
16559 dmas = <&sdma 57>, <&sdma 58>;
16560 dma-names = "tx", "rx";
16561 @@ -429,15 +519,63 @@
16562 reg = <0x480d5000 0x400>;
16563 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
16564 ti,hwmods = "mmc5";
16565 + clocks = <&func_96m_fclk>;
16566 + clock-names = "fck";
16567 ti,needs-special-reset;
16568 dmas = <&sdma 59>, <&sdma 60>;
16569 dma-names = "tx", "rx";
16570 };
16571
16572 + omap_control_sata: control-phy@4a002374 {
16573 + compatible = "ti,control-phy-pipe3";
16574 + reg = <0x4a002374 0x4>;
16575 + reg-names = "power";
16576 + clocks = <&sys_clkin>;
16577 + clock-names = "sysclk";
16578 + };
16579 +
16580 + ocp2scp@4a090000 {
16581 + compatible = "ti,omap-ocp2scp";
16582 + #address-cells = <1>;
16583 + #size-cells = <1>;
16584 + ranges;
16585 + ti,hwmods = "ocp2scp3";
16586 + reg = <0x4a090000 0x1c>; /* ocp2scp3 */
16587 + sata_phy: sata-phy@4A096000 {
16588 + compatible = "ti,phy-pipe3-sata";
16589 + reg = <0x4A096000 0x80>, /* phy_rx */
16590 + <0x4A096400 0x64>, /* phy_tx */
16591 + <0x4A096800 0x40>; /* pll_ctrl */
16592 + reg-names = "phy_rx", "phy_tx", "pll_ctrl";
16593 + ctrl-module = <&omap_control_sata>;
16594 + #phy-cells = <0>;
16595 + clocks = <&sata_ref_clk>;
16596 + clock-names = "refclk";
16597 + };
16598 + };
16599 +
16600 + sata@4a141100 {
16601 + compatible = "ti,sata";
16602 + ti,hwmods = "sata";
16603 + reg = <0x4a141100 0x100>;
16604 + #address-cells = <1>;
16605 + #size-cells = <1>;
16606 + ranges;
16607 + sata@4a140000 {
16608 + compatible = "snps,dwc-ahci";
16609 + reg = <0x4a140000 0x1100>;
16610 + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
16611 + phys = <&sata_phy>;
16612 + phy-names = "sata-phy";
16613 + };
16614 + };
16615 +
16616 keypad: keypad@4ae1c000 {
16617 compatible = "ti,omap4-keypad";
16618 reg = <0x4ae1c000 0x400>;
16619 ti,hwmods = "kbd";
16620 + clocks = <&sys_32k_ck>;
16621 + clock-names = "fck";
16622 };
16623
16624 mcpdm: mcpdm@40132000 {
16625 @@ -447,6 +585,8 @@
16626 reg-names = "mpu", "dma";
16627 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
16628 ti,hwmods = "mcpdm";
16629 + clocks = <&pad_clks_ck>;
16630 + clock-names = "fck";
16631 dmas = <&sdma 65>,
16632 <&sdma 66>;
16633 dma-names = "up_link", "dn_link";
16634 @@ -459,6 +599,8 @@
16635 reg-names = "mpu", "dma";
16636 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
16637 ti,hwmods = "dmic";
16638 + clocks = <&dmic_gfclk>;
16639 + clock-names = "fck";
16640 dmas = <&sdma 67>;
16641 dma-names = "up_link";
16642 };
16643 @@ -472,6 +614,8 @@
16644 interrupt-names = "common";
16645 ti,buffer-size = <128>;
16646 ti,hwmods = "mcbsp1";
16647 + clocks = <&mcbsp1_gfclk>, <&pad_clks_ck>, <&mcbsp1_sync_mux_ck>;
16648 + clock-names = "fck", "pad_fck", "prcm_fck";
16649 dmas = <&sdma 33>,
16650 <&sdma 34>;
16651 dma-names = "tx", "rx";
16652 @@ -486,6 +630,8 @@
16653 interrupt-names = "common";
16654 ti,buffer-size = <128>;
16655 ti,hwmods = "mcbsp2";
16656 + clocks = <&mcbsp2_gfclk>, <&pad_clks_ck>, <&mcbsp2_sync_mux_ck>;
16657 + clock-names = "fck", "pad_fck", "prcm_fck";
16658 dmas = <&sdma 17>,
16659 <&sdma 18>;
16660 dma-names = "tx", "rx";
16661 @@ -500,16 +646,31 @@
16662 interrupt-names = "common";
16663 ti,buffer-size = <128>;
16664 ti,hwmods = "mcbsp3";
16665 + clocks = <&mcbsp3_gfclk>, <&pad_clks_ck>, <&mcbsp3_sync_mux_ck>;
16666 + clock-names = "fck", "pad_fck", "prcm_fck";
16667 dmas = <&sdma 19>,
16668 <&sdma 20>;
16669 dma-names = "tx", "rx";
16670 };
16671
16672 + mailbox: mailbox@4a0f4000 {
16673 + compatible = "ti,omap4-mailbox";
16674 + reg = <0x4a0f4000 0x200>;
16675 + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
16676 + ti,hwmods = "mailbox";
16677 + ti,mbox-num-users = <3>;
16678 + ti,mbox-num-fifos = <8>;
16679 + ti,mbox-names = "mbox-ipu", "mbox-dsp";
16680 + ti,mbox-data = <0 1 0 0>, <3 2 0 0>;
16681 + };
16682 +
16683 timer1: timer@4ae18000 {
16684 compatible = "ti,omap5430-timer";
16685 reg = <0x4ae18000 0x80>;
16686 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
16687 ti,hwmods = "timer1";
16688 + clocks = <&timer1_gfclk_mux>;
16689 + clock-names = "fck";
16690 ti,timer-alwon;
16691 };
16692
16693 @@ -518,6 +679,8 @@
16694 reg = <0x48032000 0x80>;
16695 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
16696 ti,hwmods = "timer2";
16697 + clocks = <&timer2_gfclk_mux>;
16698 + clock-names = "fck";
16699 };
16700
16701 timer3: timer@48034000 {
16702 @@ -525,6 +688,8 @@
16703 reg = <0x48034000 0x80>;
16704 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
16705 ti,hwmods = "timer3";
16706 + clocks = <&timer3_gfclk_mux>;
16707 + clock-names = "fck";
16708 };
16709
16710 timer4: timer@48036000 {
16711 @@ -532,6 +697,8 @@
16712 reg = <0x48036000 0x80>;
16713 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
16714 ti,hwmods = "timer4";
16715 + clocks = <&timer4_gfclk_mux>;
16716 + clock-names = "fck";
16717 };
16718
16719 timer5: timer@40138000 {
16720 @@ -540,6 +707,8 @@
16721 <0x49038000 0x80>;
16722 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
16723 ti,hwmods = "timer5";
16724 + clocks = <&timer5_gfclk_mux>;
16725 + clock-names = "fck";
16726 ti,timer-dsp;
16727 ti,timer-pwm;
16728 };
16729 @@ -550,6 +719,8 @@
16730 <0x4903a000 0x80>;
16731 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
16732 ti,hwmods = "timer6";
16733 + clocks = <&timer6_gfclk_mux>;
16734 + clock-names = "fck";
16735 ti,timer-dsp;
16736 ti,timer-pwm;
16737 };
16738 @@ -560,6 +731,8 @@
16739 <0x4903c000 0x80>;
16740 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
16741 ti,hwmods = "timer7";
16742 + clocks = <&timer7_gfclk_mux>;
16743 + clock-names = "fck";
16744 ti,timer-dsp;
16745 };
16746
16747 @@ -569,6 +742,8 @@
16748 <0x4903e000 0x80>;
16749 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
16750 ti,hwmods = "timer8";
16751 + clocks = <&timer8_gfclk_mux>;
16752 + clock-names = "fck";
16753 ti,timer-dsp;
16754 ti,timer-pwm;
16755 };
16756 @@ -578,6 +753,8 @@
16757 reg = <0x4803e000 0x80>;
16758 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
16759 ti,hwmods = "timer9";
16760 + clocks = <&timer9_gfclk_mux>;
16761 + clock-names = "fck";
16762 ti,timer-pwm;
16763 };
16764
16765 @@ -586,6 +763,8 @@
16766 reg = <0x48086000 0x80>;
16767 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
16768 ti,hwmods = "timer10";
16769 + clocks = <&timer10_gfclk_mux>;
16770 + clock-names = "fck";
16771 ti,timer-pwm;
16772 };
16773
16774 @@ -594,19 +773,33 @@
16775 reg = <0x48088000 0x80>;
16776 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
16777 ti,hwmods = "timer11";
16778 + clocks = <&timer11_gfclk_mux>;
16779 + clock-names = "fck";
16780 ti,timer-pwm;
16781 };
16782
16783 wdt2: wdt@4ae14000 {
16784 - compatible = "ti,omap5-wdt", "ti,omap3-wdt";
16785 + compatible = "ti,omap5-wdt", "ti,omap4-wdt";
16786 reg = <0x4ae14000 0x80>;
16787 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
16788 ti,hwmods = "wd_timer2";
16789 + clocks = <&sys_32k_ck>;
16790 + clock-names = "fck";
16791 + };
16792 +
16793 + dmm: dmm@4e000000 {
16794 + compatible = "ti,omap5-dmm";
16795 + reg = <0x4e000000 0x800>;
16796 + interrupts = <0 113 0x4>;
16797 + ti,hwmods = "dmm";
16798 };
16799
16800 emif1: emif@0x4c000000 {
16801 compatible = "ti,emif-4d5";
16802 ti,hwmods = "emif1";
16803 + ti,no-idle;
16804 + clocks = <&dpll_core_h11x2_ck>;
16805 + clock-names = "fck";
16806 phy-type = <2>; /* DDR PHY type: Intelli PHY */
16807 reg = <0x4c000000 0x400>;
16808 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
16809 @@ -618,6 +811,9 @@
16810 emif2: emif@0x4d000000 {
16811 compatible = "ti,emif-4d5";
16812 ti,hwmods = "emif2";
16813 + ti,no-idle;
16814 + clocks = <&dpll_core_h11x2_ck>;
16815 + clock-names = "fck";
16816 phy-type = <2>; /* DDR PHY type: Intelli PHY */
16817 reg = <0x4d000000 0x400>;
16818 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
16819 @@ -626,18 +822,25 @@
16820 hw-caps-temp-alert;
16821 };
16822
16823 - omap_control_usb: omap-control-usb@4a002300 {
16824 - compatible = "ti,omap-control-usb";
16825 - reg = <0x4a002300 0x4>,
16826 - <0x4a002370 0x4>;
16827 - reg-names = "control_dev_conf", "phy_power_usb";
16828 - ti,type = <2>;
16829 + omap_control_usb2phy: control-phy@4a002300 {
16830 + compatible = "ti,control-phy-usb2";
16831 + reg = <0x4a002300 0x4>;
16832 + reg-names = "power";
16833 + };
16834 +
16835 + omap_control_usb3phy: control-phy@4a002370 {
16836 + compatible = "ti,control-phy-pipe3";
16837 + reg = <0x4a002370 0x4>;
16838 + reg-names = "power";
16839 };
16840
16841 - omap_dwc3@4a020000 {
16842 + usb3: omap_dwc3@4a020000 {
16843 compatible = "ti,dwc3";
16844 ti,hwmods = "usb_otg_ss";
16845 + clocks = <&dpll_core_h13x2_ck>, <&usb_otg_ss_refclk960m>;
16846 + clock-names = "fck", "refclk960m";
16847 reg = <0x4a020000 0x10000>;
16848 +
16849 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
16850 #address-cells = <1>;
16851 #size-cells = <1>;
16852 @@ -647,7 +850,10 @@
16853 compatible = "snps,dwc3";
16854 reg = <0x4a030000 0x10000>;
16855 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
16856 - usb-phy = <&usb2_phy>, <&usb3_phy>;
16857 + phys = <&usb2_phy>, <&usb3_phy>;
16858 + phy-names = "usb2-phy", "usb3-phy";
16859 + maximum-speed = "super-speed";
16860 + dr_mode = "peripheral";
16861 tx-fifo-resize;
16862 };
16863 };
16864 @@ -662,16 +868,26 @@
16865 usb2_phy: usb2phy@4a084000 {
16866 compatible = "ti,omap-usb2";
16867 reg = <0x4a084000 0x7c>;
16868 - ctrl-module = <&omap_control_usb>;
16869 + ctrl-module = <&omap_control_usb2phy>;
16870 + clocks = <&usb_phy_cm_clk32k>, <&usb_otg_ss_refclk960m>;
16871 + clock-names = "wkupclk", "refclk";
16872 + #phy-cells = <0>;
16873 };
16874
16875 usb3_phy: usb3phy@4a084400 {
16876 - compatible = "ti,omap-usb3";
16877 + compatible = "ti,phy-pipe3-usb3";
16878 reg = <0x4a084400 0x80>,
16879 <0x4a084800 0x64>,
16880 <0x4a084c00 0x40>;
16881 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
16882 - ctrl-module = <&omap_control_usb>;
16883 + ctrl-module = <&omap_control_usb3phy>;
16884 + clocks = <&usb_phy_cm_clk32k>,
16885 + <&usb_otg_ss_refclk960m>,
16886 + <&dpll_core_h13x2_ck>;
16887 + clock-names = "wkupclk",
16888 + "refclk",
16889 + "refclk2";
16890 + #phy-cells = <0>;
16891 };
16892 };
16893
16894 @@ -689,6 +905,8 @@
16895 #address-cells = <1>;
16896 #size-cells = <1>;
16897 ranges;
16898 + clocks = <&l3init_60m_fclk>;
16899 + clock-names = "init_60m_fclk";
16900
16901 usbhsohci: ohci@4a064800 {
16902 compatible = "ti,ohci-omap3", "usb-ohci";
16903 @@ -713,5 +931,71 @@
16904 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
16905 compatible = "ti,omap5430-bandgap";
16906 };
16907 +
16908 + dss@58000000 {
16909 + compatible = "ti,omap4-dss", "simple-bus";
16910 + reg = <0x58000000 0x80>;
16911 + ti,hwmods = "dss_core";
16912 + #address-cells = <1>;
16913 + #size-cells = <1>;
16914 + ranges;
16915 +
16916 + dispc@58001000 {
16917 + compatible = "ti,omap4-dispc";
16918 + reg = <0x58001000 0x1000>;
16919 + interrupts = <0 25 0x4>;
16920 + ti,hwmods = "dss_dispc";
16921 + };
16922 +
16923 + dpi: encoder@0 {
16924 + compatible = "ti,omap4-dpi";
16925 + };
16926 +
16927 + rfbi: encoder@58002000 {
16928 + compatible = "ti,omap4-rfbi";
16929 + reg = <0x58002000 0x1000>;
16930 + ti,hwmods = "dss_rfbi";
16931 + };
16932 +
16933 + dsi1: encoder@58004000 {
16934 + compatible = "ti,omap4-dsi";
16935 + reg = <0x58004000 0x200>;
16936 + interrupts = <0 53 0x4>;
16937 + ti,hwmods = "dss_dsi1";
16938 + };
16939 +
16940 + dsi2: encoder@58005000 {
16941 + compatible = "ti,omap4-dsi";
16942 + reg = <0x58005000 0x200>;
16943 + interrupts = <0 84 0x4>;
16944 + ti,hwmods = "dss_dsi2";
16945 + };
16946 +
16947 + hdmi: encoder@58060000 {
16948 + compatible = "ti,omap5-hdmi";
16949 + reg = <0x58040000 0x200>,
16950 + <0x58040200 0x100>,
16951 + <0x58040300 0x100>,
16952 + <0x58060000 0x19000>;
16953 + reg-names = "hdmi_wp", "hdmi_pllctrl",
16954 + "hdmi_txphy", "hdmi_core";
16955 + interrupts = <0 101 0x4>;
16956 + ti,hwmods = "dss_hdmi";
16957 + };
16958 + };
16959 + };
16960 +
16961 + clocks {
16962 + #address-cells = <1>;
16963 + #size-cells = <1>;
16964 + ranges;
16965 + /include/ "omap54xx-clocks.dtsi"
16966 + };
16967 +
16968 + clockdomains {
16969 + l3init_clkdm: l3init_clkdm {
16970 + compatible = "ti,clockdomain";
16971 + clocks = <&dpll_usb_ck>;
16972 + };
16973 };
16974 };
16975 --- a/arch/arm/boot/dts/omap5-uevm.dts
16976 +++ b/arch/arm/boot/dts/omap5-uevm.dts
16977 @@ -27,45 +27,19 @@
16978 regulator-max-microvolt = <3000000>;
16979 };
16980
16981 - /* HS USB Port 2 RESET */
16982 - hsusb2_reset: hsusb2_reset_reg {
16983 - compatible = "regulator-fixed";
16984 - regulator-name = "hsusb2_reset";
16985 - regulator-min-microvolt = <3300000>;
16986 - regulator-max-microvolt = <3300000>;
16987 - gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>; /* gpio3_80 HUB_NRESET */
16988 - startup-delay-us = <70000>;
16989 - enable-active-high;
16990 - };
16991 -
16992 /* HS USB Host PHY on PORT 2 */
16993 hsusb2_phy: hsusb2_phy {
16994 compatible = "usb-nop-xceiv";
16995 - reset-supply = <&hsusb2_reset>;
16996 - /**
16997 - * FIXME
16998 - * Put the right clock phandle here when available
16999 - * clocks = <&auxclk1>;
17000 - * clock-names = "main_clk";
17001 - */
17002 + reset-gpios = <&gpio3 16 GPIO_ACTIVE_LOW>; /* gpio3_80 HUB_NRESET */
17003 + clocks = <&auxclk1_ck>;
17004 + clock-names = "main_clk";
17005 clock-frequency = <19200000>;
17006 };
17007
17008 - /* HS USB Port 3 RESET */
17009 - hsusb3_reset: hsusb3_reset_reg {
17010 - compatible = "regulator-fixed";
17011 - regulator-name = "hsusb3_reset";
17012 - regulator-min-microvolt = <3300000>;
17013 - regulator-max-microvolt = <3300000>;
17014 - gpio = <&gpio3 15 GPIO_ACTIVE_HIGH>; /* gpio3_79 ETH_NRESET */
17015 - startup-delay-us = <70000>;
17016 - enable-active-high;
17017 - };
17018 -
17019 /* HS USB Host PHY on PORT 3 */
17020 hsusb3_phy: hsusb3_phy {
17021 compatible = "usb-nop-xceiv";
17022 - reset-supply = <&hsusb3_reset>;
17023 + reset-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>; /* gpio3_79 ETH_NRESET */
17024 };
17025
17026 leds {
17027 @@ -77,6 +51,28 @@
17028 default-state = "off";
17029 };
17030 };
17031 +
17032 + sound: sound {
17033 + compatible = "ti,abe-twl6040";
17034 + ti,model = "omap5-uevm";
17035 +
17036 + ti,mclk-freq = <19200000>;
17037 +
17038 + ti,mcpdm = <&mcpdm>;
17039 +
17040 + ti,twl6040 = <&twl6040>;
17041 +
17042 + /* Audio routing */
17043 + ti,audio-routing =
17044 + "Headset Stereophone", "HSOL",
17045 + "Headset Stereophone", "HSOR",
17046 + "Line Out", "AUXL",
17047 + "Line Out", "AUXR",
17048 + "HSMIC", "Headset Mic",
17049 + "Headset Mic", "Headset Mic Bias",
17050 + "AFML", "Line In",
17051 + "AFMR", "Line In";
17052 + };
17053 };
17054
17055 &omap5_pmx_core {
17056 @@ -84,16 +80,18 @@
17057 pinctrl-0 = <
17058 &twl6040_pins
17059 &mcpdm_pins
17060 - &dmic_pins
17061 &mcbsp1_pins
17062 &mcbsp2_pins
17063 &usbhost_pins
17064 &led_gpio_pins
17065 + &dss_hdmi_pins
17066 + &tpd12s015_pins
17067 + &palmas_pins
17068 >;
17069
17070 twl6040_pins: pinmux_twl6040_pins {
17071 pinctrl-single,pins = <
17072 - 0x18a (PIN_OUTPUT | MUX_MODE6) /* perslimbus2_clock.gpio5_145 */
17073 + 0x17e (PIN_OUTPUT | MUX_MODE6) /* mcspi1_somi.gpio5_141 */
17074 >;
17075 };
17076
17077 @@ -107,15 +105,6 @@
17078 >;
17079 };
17080
17081 - dmic_pins: pinmux_dmic_pins {
17082 - pinctrl-single,pins = <
17083 - 0x144 (PIN_INPUT | MUX_MODE0) /* abedmic_din1.abedmic_din1 */
17084 - 0x146 (PIN_INPUT | MUX_MODE0) /* abedmic_din2.abedmic_din2 */
17085 - 0x148 (PIN_INPUT | MUX_MODE0) /* abedmic_din3.abedmic_din3 */
17086 - 0x14a (PIN_OUTPUT | MUX_MODE0) /* abedmic_clk1.abedmic_clk1 */
17087 - >;
17088 - };
17089 -
17090 mcbsp1_pins: pinmux_mcbsp1_pins {
17091 pinctrl-single,pins = <
17092 0x14c (PIN_INPUT | MUX_MODE1) /* abedmic_clk2.abemcbsp1_fsx */
17093 @@ -143,8 +132,14 @@
17094
17095 i2c5_pins: pinmux_i2c5_pins {
17096 pinctrl-single,pins = <
17097 - 0x184 (PIN_INPUT | MUX_MODE0) /* i2c5_scl */
17098 - 0x186 (PIN_INPUT | MUX_MODE0) /* i2c5_sda */
17099 + 0x186 (PIN_INPUT | MUX_MODE0) /* i2c5_scl */
17100 + 0x188 (PIN_INPUT | MUX_MODE0) /* i2c5_sda */
17101 + >;
17102 + };
17103 +
17104 + mmc1_pins: pinmux_mmc1_pins {
17105 + pinctrl-single,pins = <
17106 + 0x194 (PIN_INPUT | MUX_MODE6) /* gpio5_152 */
17107 >;
17108 };
17109
17110 @@ -153,25 +148,25 @@
17111 0xbc (PIN_INPUT | MUX_MODE0) /* mcspi2_clk */
17112 0xbe (PIN_INPUT | MUX_MODE0) /* mcspi2_simo */
17113 0xc0 (PIN_INPUT_PULLUP | MUX_MODE0) /* mcspi2_somi */
17114 - 0xc2 (PIN_OUTPUT | MUX_MODE0) /* mcspi2_cs */
17115 + 0xc2 (PIN_OUTPUT | MUX_MODE0) /* mcspi2_cs0 */
17116 >;
17117 };
17118
17119 mcspi3_pins: pinmux_mcspi3_pins {
17120 pinctrl-single,pins = <
17121 - 0x78 (PIN_INPUT | MUX_MODE1) /* mcspi2_somi */
17122 - 0x7a (PIN_INPUT | MUX_MODE1) /* mcspi2_cs */
17123 - 0x7c (PIN_INPUT | MUX_MODE1) /* mcspi2_simo */
17124 - 0x7e (PIN_INPUT | MUX_MODE1) /* mcspi2_clk */
17125 + 0x78 (PIN_INPUT | MUX_MODE1) /* mcspi3_somi */
17126 + 0x7a (PIN_INPUT | MUX_MODE1) /* mcspi3_cs0 */
17127 + 0x7c (PIN_INPUT | MUX_MODE1) /* mcspi3_simo */
17128 + 0x7e (PIN_INPUT | MUX_MODE1) /* mcspi3_clk */
17129 >;
17130 };
17131
17132 mcspi4_pins: pinmux_mcspi4_pins {
17133 pinctrl-single,pins = <
17134 - 0x164 (PIN_INPUT | MUX_MODE1) /* mcspi2_clk */
17135 - 0x168 (PIN_INPUT | MUX_MODE1) /* mcspi2_simo */
17136 - 0x16a (PIN_INPUT | MUX_MODE1) /* mcspi2_somi */
17137 - 0x16c (PIN_INPUT | MUX_MODE1) /* mcspi2_cs */
17138 + 0x164 (PIN_INPUT | MUX_MODE1) /* mcspi4_clk */
17139 + 0x168 (PIN_INPUT | MUX_MODE1) /* mcspi4_simo */
17140 + 0x16a (PIN_INPUT | MUX_MODE1) /* mcspi4_somi */
17141 + 0x16c (PIN_INPUT | MUX_MODE1) /* mcspi4_cs0 */
17142 >;
17143 };
17144
17145 @@ -219,6 +214,25 @@
17146 >;
17147 };
17148
17149 + dss_hdmi_pins: pinmux_dss_hdmi_pins {
17150 + pinctrl-single,pins = <
17151 + 0x0fc (PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_cec.hdmi_cec */
17152 + 0x100 (PIN_INPUT | MUX_MODE0) /* DDC-SCL */
17153 + 0x102 (PIN_INPUT | MUX_MODE0) /* DDC-SDA */
17154 + >;
17155 + };
17156 +
17157 + tpd12s015_pins: pinmux_tpd12s015_pins {
17158 + pinctrl-single,pins = <
17159 + 0x0fe (PIN_INPUT_PULLDOWN | MUX_MODE6) /* hdmi_hpd.gpio7_193 */
17160 + >;
17161 + };
17162 +
17163 + palmas_pins: pinmux_palmas_pins {
17164 + pinctrl-single,pins = <
17165 + 0x140 (PIN_INPUT_PULLUP | MUX_MODE1) /* MSECURE */
17166 + >;
17167 + };
17168 };
17169
17170 &omap5_pmx_wkup {
17171 @@ -235,8 +249,11 @@
17172 };
17173
17174 &mmc1 {
17175 + pinctrl-names = "default";
17176 + pinctrl-0 = <&mmc1_pins>;
17177 vmmc-supply = <&ldo9_reg>;
17178 bus-width = <4>;
17179 + cd-gpios = <&gpio5 24 0>; /* gpio 152 */
17180 };
17181
17182 &mmc2 {
17183 @@ -259,6 +276,7 @@
17184 };
17185
17186 &i2c1 {
17187 + status = "okay";
17188 pinctrl-names = "default";
17189 pinctrl-0 = <&i2c1_pins>;
17190
17191 @@ -272,6 +290,30 @@
17192 interrupt-controller;
17193 #interrupt-cells = <2>;
17194
17195 + extcon_usb3: palmas_usb {
17196 + compatible = "ti,palmas-usb-vid";
17197 + ti,enable-vbus-detection;
17198 + ti,enable-id-detection;
17199 + ti,wakeup;
17200 + };
17201 +
17202 + palmas_rtc: rtc {
17203 + compatible = "ti,palmas-rtc";
17204 + interrupt-parent = <&palmas>;
17205 + interrupts = <8 IRQ_TYPE_NONE>;
17206 + ti,backup-battery-chargeable;
17207 + };
17208 +
17209 + clk32kg: palmas_clk32k@0 {
17210 + compatible = "ti,palmas-clk32kg";
17211 + #clock-cells = <0>;
17212 + };
17213 +
17214 + clk32kgaudio: palmas_clk32k@1 {
17215 + compatible = "ti,palmas-clk32kgaudio";
17216 + #clock-cells = <0>;
17217 + };
17218 +
17219 palmas_pmic {
17220 compatible = "ti,palmas-pmic";
17221 interrupt-parent = <&palmas>;
17222 @@ -334,15 +376,22 @@
17223 ti,smps-range = <0x80>;
17224 };
17225
17226 - smps10_reg: smps10 {
17227 + smps10_out2_reg: smps10_out2 {
17228 /* VBUS_5V_OTG */
17229 - regulator-name = "smps10";
17230 + regulator-name = "smps10_out2";
17231 regulator-min-microvolt = <5000000>;
17232 regulator-max-microvolt = <5000000>;
17233 regulator-always-on;
17234 regulator-boot-on;
17235 };
17236
17237 + smps10_out1_reg: smps10_out1 {
17238 + /* VBUS_5V_OTG */
17239 + regulator-name = "smps10_out1";
17240 + regulator-min-microvolt = <5000000>;
17241 + regulator-max-microvolt = <5000000>;
17242 + };
17243 +
17244 ldo1_reg: ldo1 {
17245 /* VDDAPHY_CAM: vdda_csiport */
17246 regulator-name = "ldo1";
17247 @@ -448,13 +497,37 @@
17248 };
17249 };
17250 };
17251 +
17252 + twl6040: twl@4b {
17253 + compatible = "ti,twl6040";
17254 + reg = <0x4b>;
17255 +
17256 + interrupts = <GIC_SPI 119 IRQ_TYPE_NONE>; /* IRQ_SYS_2N cascaded to gic */
17257 + interrupt-parent = <&gic>;
17258 + ti,audpwron-gpio = <&gpio5 13 0>; /* gpio line 141 */
17259 +
17260 + vio-supply = <&smps7_reg>;
17261 + v2v1-supply = <&smps9_reg>;
17262 + enable-active-high;
17263 +
17264 + clocks = <&clk32kgaudio>;
17265 + clock-names = "clk32k";
17266 + };
17267 };
17268
17269 &i2c5 {
17270 + status = "okay";
17271 pinctrl-names = "default";
17272 pinctrl-0 = <&i2c5_pins>;
17273
17274 clock-frequency = <400000>;
17275 +
17276 + tca6424a: tca6424a@22 {
17277 + compatible = "ti,tca6424";
17278 + reg = <0x22>;
17279 + gpio-controller;
17280 + #gpio-cells = <2>;
17281 + };
17282 };
17283
17284 &mcbsp3 {
17285 @@ -470,36 +543,91 @@
17286 phys = <0 &hsusb2_phy &hsusb3_phy>;
17287 };
17288
17289 -&mcspi1 {
17290 +&usb3 {
17291 + extcon = <&extcon_usb3>;
17292 + vbus-supply = <&smps10_out1_reg>;
17293 +};
17294
17295 +&mcspi1 {
17296 + status = "okay";
17297 };
17298
17299 &mcspi2 {
17300 + status = "okay";
17301 pinctrl-names = "default";
17302 pinctrl-0 = <&mcspi2_pins>;
17303 };
17304
17305 &mcspi3 {
17306 + status = "okay";
17307 pinctrl-names = "default";
17308 pinctrl-0 = <&mcspi3_pins>;
17309 };
17310
17311 &mcspi4 {
17312 + status = "okay";
17313 pinctrl-names = "default";
17314 pinctrl-0 = <&mcspi4_pins>;
17315 };
17316
17317 &uart1 {
17318 + status = "okay";
17319 pinctrl-names = "default";
17320 pinctrl-0 = <&uart1_pins>;
17321 };
17322
17323 &uart3 {
17324 + status = "okay";
17325 pinctrl-names = "default";
17326 pinctrl-0 = <&uart3_pins>;
17327 };
17328
17329 &uart5 {
17330 + status = "okay";
17331 pinctrl-names = "default";
17332 pinctrl-0 = <&uart5_pins>;
17333 };
17334 +
17335 +&hdmi {
17336 + vdda_hdmi_dac-supply = <&ldo4_reg>;
17337 +};
17338 +
17339 +&dsi1 {
17340 + vdds_dsi-supply = <&ldo4_reg>;
17341 +};
17342 +
17343 +&dsi2 {
17344 + vdds_dsi-supply = <&ldo4_reg>;
17345 +};
17346 +
17347 +&cpu0 {
17348 + cpu0-supply = <&smps123_reg>;
17349 +};
17350 +
17351 +/ {
17352 + aliases {
17353 + display0 = &hdmi0;
17354 + ethernet0 = &smsc0;
17355 + };
17356 +
17357 + tpd12s015: encoder@0 {
17358 + compatible = "ti,tpd12s015";
17359 +
17360 + video-source = <&hdmi>;
17361 +
17362 + gpios = <&tca6424a 0 0>, /* TCA6424A P01, CT CP HPD */
17363 + <&tca6424a 1 0>, /* TCA6424A P00, LS OE */
17364 + <&gpio7 1 0>; /* GPIO 193, HPD */
17365 + };
17366 +
17367 + hdmi0: connector@0 {
17368 + compatible = "ti,hdmi_connector";
17369 +
17370 + video-source = <&tpd12s015>;
17371 + };
17372 +
17373 + smsc0: smsc95xx@0 {
17374 + /* Filled in by U-Boot */
17375 + mac-address = [ 00 00 00 00 00 00 ];
17376 + };
17377 +};
17378 --- /dev/null
17379 +++ b/arch/arm/boot/dts/tps65218.dtsi
17380 @@ -0,0 +1,41 @@
17381 +/*
17382 + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
17383 + *
17384 + * This program is free software; you can redistribute it and/or modify
17385 + * it under the terms of the GNU General Public License version 2 as
17386 + * published by the Free Software Foundation.
17387 + */
17388 +
17389 +&tps {
17390 + compatible = "ti,tps65218";
17391 + interrupt-controller;
17392 + #interrupt-cells = <2>;
17393 +
17394 + dcdc1: regulator-dcdc1 {
17395 + compatible = "ti,tps65218-dcdc1";
17396 + };
17397 +
17398 + dcdc2: regulator-dcdc2 {
17399 + compatible = "ti,tps65218-dcdc2";
17400 + };
17401 +
17402 + dcdc3: regulator-dcdc3 {
17403 + compatible = "ti,tps65218-dcdc3";
17404 + };
17405 +
17406 + dcdc4: regulator-dcdc4 {
17407 + compatible = "ti,tps65218-dcdc4";
17408 + };
17409 +
17410 + dcdc5: regulator-dcdc5 {
17411 + compatible = "ti,tps65218-dcdc5";
17412 + };
17413 +
17414 + dcdc6: regulator-dcdc6 {
17415 + compatible = "ti,tps65218-dcdc6";
17416 + };
17417 +
17418 + ldo1: regulator-ldo1 {
17419 + compatible = "ti,tps65218-ldo1";
17420 + };
17421 +};
17422 --- a/arch/arm/boot/dts/twl4030.dtsi
17423 +++ b/arch/arm/boot/dts/twl4030.dtsi
17424 @@ -86,6 +86,7 @@
17425 usb1v8-supply = <&vusb1v8>;
17426 usb3v1-supply = <&vusb3v1>;
17427 usb_mode = <1>;
17428 + #phy-cells = <0>;
17429 };
17430
17431 twl_pwm: pwm {
17432 --- a/arch/arm/boot/Makefile
17433 +++ b/arch/arm/boot/Makefile
17434 @@ -55,6 +55,9 @@ $(obj)/zImage: $(obj)/compressed/vmlinux
17435 $(call if_changed,objcopy)
17436 @$(kecho) ' Kernel: $@ is ready'
17437
17438 +$(obj)/zImage-dtb.%: $(obj)/dts/%.dtb $(obj)/zImage
17439 + cat $(obj)/zImage $< > $@
17440 +
17441 endif
17442
17443 ifneq ($(LOADADDR),)
17444 @@ -80,6 +83,10 @@ $(obj)/uImage: $(obj)/zImage FORCE
17445 $(call if_changed,uimage)
17446 @$(kecho) ' Image $@ is ready'
17447
17448 +$(obj)/uImage.%: $(obj)/zImage-dtb.% FORCE
17449 + $(call if_changed,uimage)
17450 + @echo ' Image $@ is ready'
17451 +
17452 $(obj)/bootp/bootp: $(obj)/zImage initrd FORCE
17453 $(Q)$(MAKE) $(build)=$(obj)/bootp $@
17454 @:
17455 --- a/arch/arm/configs/omap2plus_defconfig
17456 +++ b/arch/arm/configs/omap2plus_defconfig
17457 @@ -26,11 +26,13 @@ CONFIG_ARCH_OMAP2=y
17458 CONFIG_ARCH_OMAP3=y
17459 CONFIG_ARCH_OMAP4=y
17460 CONFIG_SOC_AM33XX=y
17461 +CONFIG_SOC_AM43XX=y
17462 CONFIG_OMAP_RESET_CLOCKS=y
17463 CONFIG_OMAP_MUX_DEBUG=y
17464 CONFIG_ARCH_VEXPRESS_CA9X4=y
17465 CONFIG_ARM_THUMBEE=y
17466 CONFIG_ARM_ERRATA_411920=y
17467 +CONFIG_OMAP4_ERRATA_I688=y
17468 CONFIG_NO_HZ=y
17469 CONFIG_HIGH_RES_TIMERS=y
17470 CONFIG_SMP=y
17471 @@ -42,6 +44,14 @@ CONFIG_ARM_APPENDED_DTB=y
17472 CONFIG_ARM_ATAG_DTB_COMPAT=y
17473 CONFIG_CMDLINE="root=/dev/mmcblk0p2 rootwait console=ttyO2,115200"
17474 CONFIG_KEXEC=y
17475 +CONFIG_CPU_FREQ=y
17476 +CONFIG_CPU_FREQ_STAT_DETAILS=y
17477 +CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
17478 +CONFIG_CPU_FREQ_GOV_POWERSAVE=y
17479 +CONFIG_CPU_FREQ_GOV_USERSPACE=y
17480 +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
17481 +CONFIG_GENERIC_CPUFREQ_CPU0=y
17482 +# CONFIG_ARM_OMAP2PLUS_CPUFREQ is not set
17483 CONFIG_FPE_NWFPE=y
17484 CONFIG_BINFMT_MISC=y
17485 CONFIG_PM_DEBUG=y
17486 @@ -60,6 +70,7 @@ CONFIG_IP_PNP_RARP=y
17487 # CONFIG_INET_LRO is not set
17488 # CONFIG_IPV6 is not set
17489 CONFIG_NETFILTER=y
17490 +CONFIG_VLAN_8021Q=y
17491 CONFIG_CAN=m
17492 CONFIG_CAN_RAW=m
17493 CONFIG_CAN_BCM=m
17494 @@ -82,6 +93,7 @@ CONFIG_DMA_CMA=y
17495 CONFIG_CONNECTOR=y
17496 CONFIG_DEVTMPFS=y
17497 CONFIG_DEVTMPFS_MOUNT=y
17498 +CONFIG_OMAP_OCP2SCP=y
17499 CONFIG_MTD=y
17500 CONFIG_MTD_CMDLINE_PARTS=y
17501 CONFIG_MTD_CHAR=y
17502 @@ -89,8 +101,11 @@ CONFIG_MTD_BLOCK=y
17503 CONFIG_MTD_OOPS=y
17504 CONFIG_MTD_CFI=y
17505 CONFIG_MTD_CFI_INTELEXT=y
17506 +CONFIG_MTD_M25P80=y
17507 +# CONFIG_M25PXX_USE_FAST_READ is not set
17508 CONFIG_MTD_NAND=y
17509 CONFIG_MTD_NAND_OMAP2=y
17510 +CONFIG_MTD_NAND_OMAP_BCH=y
17511 CONFIG_MTD_ONENAND=y
17512 CONFIG_MTD_ONENAND_VERIFY_WRITE=y
17513 CONFIG_MTD_ONENAND_OMAP2=y
17514 @@ -106,6 +121,9 @@ CONFIG_SCSI=y
17515 CONFIG_BLK_DEV_SD=y
17516 CONFIG_SCSI_MULTI_LUN=y
17517 CONFIG_SCSI_SCAN_ASYNC=y
17518 +CONFIG_ATA=y
17519 +CONFIG_SATA_AHCI_PLATFORM=y
17520 +CONFIG_SATA_TI=y
17521 CONFIG_MD=y
17522 CONFIG_NETDEVICES=y
17523 CONFIG_SMSC_PHY=y
17524 @@ -131,6 +149,9 @@ CONFIG_KEYBOARD_MATRIX=m
17525 CONFIG_KEYBOARD_TWL4030=y
17526 CONFIG_INPUT_TOUCHSCREEN=y
17527 CONFIG_TOUCHSCREEN_ADS7846=y
17528 +CONFIG_TOUCHSCREEN_ATMEL_MXT=y
17529 +CONFIG_TOUCHSCREEN_TI_AM335X_TSC=y
17530 +CONFIG_TOUCHSCREEN_PIXCIR=m
17531 CONFIG_INPUT_MISC=y
17532 CONFIG_INPUT_TWL4030_PWRBUTTON=y
17533 CONFIG_VT_HW_CONSOLE_BINDING=y
17534 @@ -151,10 +172,14 @@ CONFIG_HW_RANDOM=y
17535 CONFIG_I2C_CHARDEV=y
17536 CONFIG_SPI=y
17537 CONFIG_SPI_OMAP24XX=y
17538 +CONFIG_SPI_TI_QSPI=y
17539 CONFIG_PINCTRL_SINGLE=y
17540 CONFIG_DEBUG_GPIO=y
17541 CONFIG_GPIO_SYSFS=y
17542 CONFIG_GPIO_TWL4030=y
17543 +CONFIG_GPIOLIB=y
17544 +CONFIG_I2C=y
17545 +CONFIG_GPIO_PCF857X=y
17546 CONFIG_W1=y
17547 CONFIG_POWER_SUPPLY=y
17548 CONFIG_SENSORS_LM75=m
17549 @@ -168,31 +193,52 @@ CONFIG_THERMAL_GOV_USER_SPACE=y
17550 CONFIG_CPU_THERMAL=y
17551 CONFIG_OMAP_WATCHDOG=y
17552 CONFIG_TWL4030_WATCHDOG=y
17553 +CONFIG_MFD_TI_AM335X_TSCADC=y
17554 +CONFIG_MFD_PALMAS=y
17555 CONFIG_MFD_TPS65217=y
17556 CONFIG_MFD_TPS65910=y
17557 CONFIG_TWL6040_CORE=y
17558 CONFIG_REGULATOR_TWL4030=y
17559 +CONFIG_REGULATOR_TIAVSCLASS0=y
17560 CONFIG_REGULATOR_TPS65023=y
17561 CONFIG_REGULATOR_TPS6507X=y
17562 CONFIG_REGULATOR_TPS65217=y
17563 CONFIG_REGULATOR_TPS65910=y
17564 +CONFIG_REGULATOR_PALMAS=y
17565 +CONFIG_MEDIA_SUPPORT=m
17566 +CONFIG_MEDIA_CAMERA_SUPPORT=y
17567 +CONFIG_VIDEO_DEV=m
17568 +CONFIG_VIDEO_V4L2=m
17569 +CONFIG_VIDEOBUF2_CORE=m
17570 +CONFIG_VIDEOBUF2_MEMOPS=m
17571 +CONFIG_VIDEOBUF2_VMALLOC=m
17572 +CONFIG_MEDIA_USB_SUPPORT=y
17573 +CONFIG_USB_VIDEO_CLASS=m
17574 +CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
17575 +CONFIG_USB_GSPCA=m
17576 CONFIG_FB=y
17577 CONFIG_FIRMWARE_EDID=y
17578 CONFIG_FB_MODE_HELPERS=y
17579 CONFIG_FB_TILEBLITTING=y
17580 CONFIG_FB_OMAP_LCD_VGA=y
17581 -CONFIG_OMAP2_DSS=m
17582 +CONFIG_FB_DA8XX=y
17583 +CONFIG_FB_DA8XX_TDA998X=y
17584 +CONFIG_OMAP2_DSS=y
17585 CONFIG_OMAP2_DSS_RFBI=y
17586 CONFIG_OMAP2_DSS_SDI=y
17587 CONFIG_OMAP2_DSS_DSI=y
17588 -CONFIG_FB_OMAP2=m
17589 -CONFIG_DISPLAY_ENCODER_TFP410=m
17590 -CONFIG_DISPLAY_ENCODER_TPD12S015=m
17591 -CONFIG_DISPLAY_CONNECTOR_DVI=m
17592 -CONFIG_DISPLAY_CONNECTOR_HDMI=m
17593 -CONFIG_DISPLAY_PANEL_DPI=m
17594 +CONFIG_FB_OMAP2=y
17595 +CONFIG_DISPLAY_ENCODER_TFP410=y
17596 +CONFIG_DISPLAY_ENCODER_TPD12S015=y
17597 +CONFIG_DISPLAY_DRA_EVM_ENCODER_TPD12S015=y
17598 +CONFIG_DISPLAY_CONNECTOR_DVI=y
17599 +CONFIG_DISPLAY_CONNECTOR_HDMI=y
17600 +CONFIG_DISPLAY_PANEL_DPI=y
17601 +CONFIG_DISPLAY_PANEL_TFCS9700=y
17602 CONFIG_BACKLIGHT_LCD_SUPPORT=y
17603 CONFIG_LCD_CLASS_DEVICE=y
17604 +CONFIG_BACKLIGHT_CLASS_DEVICE=y
17605 +CONFIG_BACKLIGHT_PWM=y
17606 CONFIG_LCD_PLATFORM=y
17607 CONFIG_DISPLAY_SUPPORT=y
17608 CONFIG_FRAMEBUFFER_CONSOLE=y
17609 @@ -210,25 +256,57 @@ CONFIG_SND_DEBUG=y
17610 CONFIG_SND_USB_AUDIO=m
17611 CONFIG_SND_SOC=m
17612 CONFIG_SND_OMAP_SOC=m
17613 +CONFIG_SND_AM33XX_SOC_EVM=m
17614 +CONFIG_SND_DAVINCI_SOC=m
17615 CONFIG_SND_OMAP_SOC_OMAP_TWL4030=m
17616 CONFIG_SND_OMAP_SOC_OMAP_ABE_TWL6040=m
17617 CONFIG_SND_OMAP_SOC_OMAP3_PANDORA=m
17618 CONFIG_USB=y
17619 -CONFIG_USB_DEBUG=y
17620 CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
17621 CONFIG_USB_DEVICEFS=y
17622 CONFIG_USB_MON=y
17623 +CONFIG_USB_XHCI_HCD=y
17624 +CONFIG_USB_XHCI_PLATFORM=y
17625 +CONFIG_USB_EHCI_HCD=y
17626 +CONFIG_USB_MUSB_HDRC=y
17627 +CONFIG_USB_MUSB_OMAP2PLUS=m
17628 +CONFIG_USB_MUSB_DSPS=m
17629 CONFIG_USB_WDM=y
17630 CONFIG_USB_STORAGE=y
17631 CONFIG_USB_LIBUSUAL=y
17632 CONFIG_USB_TEST=y
17633 +CONFIG_AM335X_PHY_USB=y
17634 +CONFIG_TWL6030_USB=y
17635 CONFIG_USB_PHY=y
17636 CONFIG_NOP_USB_XCEIV=y
17637 +
17638 +CONFIG_USB_DWC3=y
17639 +CONFIG_USB_DWC3_OMAP=y
17640 +
17641 CONFIG_USB_GADGET=y
17642 CONFIG_USB_GADGET_DEBUG=y
17643 CONFIG_USB_GADGET_DEBUG_FILES=y
17644 CONFIG_USB_GADGET_DEBUG_FS=y
17645 CONFIG_USB_ZERO=m
17646 +CONFIG_USB_AUDIO=m
17647 +CONFIG_USB_ETH=m
17648 +CONFIG_USB_G_NCM=m
17649 +CONFIG_USB_GADGETFS=m
17650 +CONFIG_USB_FUNCTIONFS=m
17651 +CONFIG_USB_FUNCTIONFS_ETH=y
17652 +CONFIG_USB_FUNCTIONFS_RNDIS=y
17653 +CONFIG_USB_FUNCTIONFS_GENERIC=y
17654 +CONFIG_USB_MASS_STORAGE=m
17655 +CONFIG_USB_G_SERIAL=m
17656 +CONFIG_USB_MIDI_GADGET=m
17657 +CONFIG_USB_G_PRINTER=m
17658 +CONFIG_USB_CDC_COMPOSITE=m
17659 +CONFIG_USB_G_ACM_MS=m
17660 +CONFIG_USB_G_MULTI=m
17661 +CONFIG_USB_G_MULTI_CDC=y
17662 +CONFIG_USB_G_HID=m
17663 +CONFIG_USB_G_DBGP=m
17664 +CONFIG_USB_G_WEBCAM=m
17665 CONFIG_MMC=y
17666 CONFIG_MMC_UNSAFE_RESUME=y
17667 CONFIG_SDIO_UART=y
17668 @@ -249,14 +327,35 @@ CONFIG_RTC_CLASS=y
17669 CONFIG_RTC_DRV_TWL92330=y
17670 CONFIG_RTC_DRV_TWL4030=y
17671 CONFIG_RTC_DRV_OMAP=y
17672 +CONFIG_RTC_DRV_PALMAS=y
17673 CONFIG_DMADEVICES=y
17674 CONFIG_TI_EDMA=y
17675 CONFIG_DMA_OMAP=y
17676 +CONFIG_PWM=y
17677 +CONFIG_COMMON_CLK_DEBUG=y
17678 +CONFIG_PWM_TIECAP=m
17679 +CONFIG_PWM_TIEHRPWM=m
17680 CONFIG_TI_SOC_THERMAL=y
17681 CONFIG_TI_THERMAL=y
17682 CONFIG_OMAP4_THERMAL=y
17683 CONFIG_OMAP5_THERMAL=y
17684 CONFIG_DRA752_THERMAL=y
17685 +
17686 +CONFIG_EXTCON=y
17687 +CONFIG_EXTCON_PALMAS=y
17688 +CONFIG_EXTCON_GPIO_USBVID=y
17689 +
17690 +CONFIG_GENERIC_PHY=y
17691 +CONFIG_OMAP_CONTROL_PHY=y
17692 +CONFIG_IIO=m
17693 +CONFIG_IIO_BUFFER=y
17694 +CONFIG_IIO_BUFFER_CB=y
17695 +CONFIG_IIO_KFIFO_BUF=m
17696 +CONFIG_TI_AM335X_ADC=m
17697 +CONFIG_OMAP_USB2=y
17698 +CONFIG_OMAP_PIPE3=y
17699 +CONFIG_TWL4030_USB=y
17700 +
17701 CONFIG_EXT2_FS=y
17702 CONFIG_EXT3_FS=y
17703 # CONFIG_EXT3_FS_XATTR is not set
17704 @@ -295,6 +394,10 @@ CONFIG_DEBUG_INFO=y
17705 CONFIG_SECURITY=y
17706 CONFIG_CRYPTO_MICHAEL_MIC=y
17707 # CONFIG_CRYPTO_ANSI_CPRNG is not set
17708 +CONFIG_CRYPTO_DEV_OMAP_SHAM=y
17709 +CONFIG_CRYPTO_DEV_OMAP_AES=y
17710 +CONFIG_CRYPTO_DEV_OMAP_DES=y
17711 +CONFIG_CRYPTO_TEST=m
17712 CONFIG_CRC_CCITT=y
17713 CONFIG_CRC_T10DIF=y
17714 CONFIG_CRC_ITU_T=y
17715 @@ -306,3 +409,4 @@ CONFIG_TI_DAVINCI_CPDMA=y
17716 CONFIG_TI_CPSW=y
17717 CONFIG_AT803X_PHY=y
17718 CONFIG_SOC_DRA7XX=y
17719 +CONFIG_GPIO_PCA953X=y
17720 --- a/arch/arm/Kconfig
17721 +++ b/arch/arm/Kconfig
17722 @@ -873,10 +873,33 @@ config ARCH_OMAP1
17723 help
17724 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
17725
17726 +config ARCH_OMAP2PLUS
17727 + bool "TI OMAP2+"
17728 + depends on MMU
17729 + select ARCH_HAS_BANDGAP
17730 + select ARCH_HAS_CPUFREQ
17731 + select ARCH_HAS_HOLES_MEMORYMODEL
17732 + select ARCH_OMAP
17733 + select ARCH_REQUIRE_GPIOLIB
17734 + select CLKDEV_LOOKUP
17735 + select CLKSRC_MMIO
17736 + select GENERIC_CLOCKEVENTS
17737 + select GENERIC_IRQ_CHIP
17738 + select HAVE_CLK
17739 + select OMAP_DM_TIMER
17740 + select PINCTRL
17741 + select PROC_DEVICETREE if PROC_FS
17742 + select SOC_BUS
17743 + select SPARSE_IRQ
17744 + select TI_PRIV_EDMA
17745 + select USE_OF
17746 + select AUTO_ZRELADDR
17747 + help
17748 + SUpport for OMAP2, OMAP3, OMAP4 and OMAP5
17749 +
17750 endchoice
17751
17752 menu "Multiple platform selection"
17753 - depends on ARCH_MULTIPLATFORM
17754
17755 comment "CPU Core family selection"
17756
17757 @@ -1606,6 +1629,7 @@ config ARCH_NR_GPIO
17758 default 352 if ARCH_VT8500
17759 default 288 if ARCH_SUNXI
17760 default 264 if MACH_H4700
17761 + default 192 if SOC_AM43XX
17762 default 0
17763 help
17764 Maximum number of GPIOs in the system.
17765 --- a/arch/arm/Kconfig.debug
17766 +++ b/arch/arm/Kconfig.debug
17767 @@ -1077,7 +1077,7 @@ config DEBUG_UNCOMPRESS
17768
17769 config UNCOMPRESS_INCLUDE
17770 string
17771 - default "debug/uncompress.h" if ARCH_MULTIPLATFORM || ARCH_MSM
17772 + default "debug/uncompress.h" if ARCH_MULTIPLATFORM || ARCH_MSM || ARCH_OMAP
17773 default "mach/uncompress.h"
17774
17775 config EARLY_PRINTK
17776 --- a/arch/arm/kernel/head.S
17777 +++ b/arch/arm/kernel/head.S
17778 @@ -534,7 +534,8 @@ smp_on_up:
17779 __do_fixup_smp_on_up:
17780 cmp r4, r5
17781 movhs pc, lr
17782 - ldmia r4!, {r0, r6}
17783 + ldmia r4!, {r0}
17784 + ldmia r4!, {r6}
17785 ARM( str r6, [r0, r3] )
17786 THUMB( add r0, r0, r3 )
17787 #ifdef __ARMEB__
17788 --- a/arch/arm/mach-omap2/am33xx-restart.c
17789 +++ b/arch/arm/mach-omap2/am33xx-restart.c
17790 @@ -9,6 +9,7 @@
17791 #include <linux/reboot.h>
17792
17793 #include "common.h"
17794 +#include "prcm43xx.h"
17795 #include "prm-regbits-33xx.h"
17796 #include "prm33xx.h"
17797
17798 @@ -33,3 +34,25 @@ void am33xx_restart(enum reboot_mode mod
17799 (void)am33xx_prm_read_reg(AM33XX_PRM_DEVICE_MOD,
17800 AM33XX_PRM_RSTCTRL_OFFSET);
17801 }
17802 +
17803 +/**
17804 + * am43xx_restart - trigger a software restart of the SoC
17805 + * @mode: the "reboot mode", see arch/arm/kernel/{setup,process}.c
17806 + * @cmd: passed fr-om the userspace program rebooting the system (if provided)
17807 + *
17808 + * Resets the SoC. For @cmd, see the 'reboot' syscall in
17809 + * kernel/sys.c. No return value.
17810 + */
17811 +void am43xx_restart(enum reboot_mode mode, const char *cmd)
17812 +{
17813 + /* TODO: Handle mode and cmd if necessary */
17814 +
17815 + am33xx_prm_rmw_reg_bits(AM33XX_RST_GLOBAL_WARM_SW_MASK,
17816 + AM33XX_RST_GLOBAL_WARM_SW_MASK,
17817 + AM43XX_PRM_DEVICE_INST,
17818 + AM33XX_PRM_RSTCTRL_OFFSET);
17819 +
17820 + /* OCP barrier */
17821 + (void)am33xx_prm_read_reg(AM43XX_PRM_DEVICE_INST,
17822 + AM33XX_PRM_RSTCTRL_OFFSET);
17823 +}
17824 --- a/arch/arm/mach-omap2/board-2430sdp.c
17825 +++ b/arch/arm/mach-omap2/board-2430sdp.c
17826 @@ -246,7 +246,7 @@ static void __init omap_2430sdp_init(voi
17827 omap_hsmmc_init(mmc);
17828
17829 omap_mux_init_signal("usb0hs_stp", OMAP_PULL_ENA | OMAP_PULL_UP);
17830 - usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
17831 + usb_bind_phy("musb-hdrc.0", 0, "twl4030_usb");
17832 usb_musb_init(NULL);
17833
17834 board_smc91x_init();
17835 --- a/arch/arm/mach-omap2/board-3430sdp.c
17836 +++ b/arch/arm/mach-omap2/board-3430sdp.c
17837 @@ -607,7 +607,7 @@ static void __init omap_3430sdp_init(voi
17838 omap_ads7846_init(1, gpio_pendown, 310, NULL);
17839 omap_serial_init();
17840 omap_sdrc_init(hyb18m512160af6_sdrc_params, NULL);
17841 - usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
17842 + usb_bind_phy("musb-hdrc.0", 0, "twl4030_usb");
17843 usb_musb_init(NULL);
17844 board_smc91x_init();
17845 board_flash_init(sdp_flash_partitions, chip_sel_3430, 0);
17846 --- a/arch/arm/mach-omap2/board-cm-t35.c
17847 +++ b/arch/arm/mach-omap2/board-cm-t35.c
17848 @@ -725,7 +725,7 @@ static void __init cm_t3x_common_init(vo
17849 cm_t35_init_display();
17850 omap_twl4030_audio_init("cm-t3x", NULL);
17851
17852 - usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
17853 + usb_bind_phy("musb-hdrc.0", 0, "twl4030_usb");
17854 usb_musb_init(NULL);
17855 cm_t35_init_usbh();
17856 cm_t35_init_camera();
17857 --- a/arch/arm/mach-omap2/board-devkit8000.c
17858 +++ b/arch/arm/mach-omap2/board-devkit8000.c
17859 @@ -628,7 +628,7 @@ static void __init devkit8000_init(void)
17860
17861 omap_ads7846_init(2, OMAP3_DEVKIT_TS_GPIO, 0, NULL);
17862
17863 - usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
17864 + usb_bind_phy("musb-hdrc.0", 0, "twl4030_usb");
17865 usb_musb_init(NULL);
17866 usbhs_init(&usbhs_bdata);
17867 board_nand_init(devkit8000_nand_partitions,
17868 --- a/arch/arm/mach-omap2/board-flash.c
17869 +++ b/arch/arm/mach-omap2/board-flash.c
17870 @@ -142,7 +142,7 @@ __init board_nand_init(struct mtd_partit
17871 board_nand_data.nr_parts = nr_parts;
17872 board_nand_data.devsize = nand_type;
17873
17874 - board_nand_data.ecc_opt = OMAP_ECC_HAMMING_CODE_DEFAULT;
17875 + board_nand_data.ecc_opt = OMAP_ECC_BCH8_CODE_HW;
17876 gpmc_nand_init(&board_nand_data, gpmc_t);
17877 }
17878 #endif /* CONFIG_MTD_NAND_OMAP2 || CONFIG_MTD_NAND_OMAP2_MODULE */
17879 --- a/arch/arm/mach-omap2/board-generic.c
17880 +++ b/arch/arm/mach-omap2/board-generic.c
17881 @@ -15,13 +15,11 @@
17882 #include <linux/of_irq.h>
17883 #include <linux/of_platform.h>
17884 #include <linux/irqdomain.h>
17885 -#include <linux/clk.h>
17886
17887 #include <asm/mach/arch.h>
17888
17889 #include "common.h"
17890 #include "common-board-devices.h"
17891 -#include "dss-common.h"
17892
17893 #if !(defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3))
17894 #define intc_of_init NULL
17895 @@ -36,40 +34,13 @@ static struct of_device_id omap_dt_match
17896 { }
17897 };
17898
17899 -/*
17900 - * Create alias for USB host PHY clock.
17901 - * Remove this when clock phandle can be provided via DT
17902 - */
17903 -static void __init legacy_init_ehci_clk(char *clkname)
17904 -{
17905 - int ret;
17906 -
17907 - ret = clk_add_alias("main_clk", NULL, clkname, NULL);
17908 - if (ret) {
17909 - pr_err("%s:Failed to add main_clk alias to %s :%d\n",
17910 - __func__, clkname, ret);
17911 - }
17912 -}
17913 -
17914 static void __init omap_generic_init(void)
17915 {
17916 omap_sdrc_init(NULL, NULL);
17917
17918 of_platform_populate(NULL, omap_dt_match_table, NULL, NULL);
17919
17920 - /*
17921 - * HACK: call display setup code for selected boards to enable omapdss.
17922 - * This will be removed when omapdss supports DT.
17923 - */
17924 - if (of_machine_is_compatible("ti,omap4-panda")) {
17925 - omap4_panda_display_init_of();
17926 - legacy_init_ehci_clk("auxclk3_ck");
17927 -
17928 - }
17929 - else if (of_machine_is_compatible("ti,omap4-sdp"))
17930 - omap_4430sdp_display_init_of();
17931 - else if (of_machine_is_compatible("ti,omap5-uevm"))
17932 - legacy_init_ehci_clk("auxclk1_ck");
17933 + omapdss_init_of();
17934 }
17935
17936 #ifdef CONFIG_SOC_OMAP2420
17937 @@ -165,6 +136,24 @@ DT_MACHINE_START(OMAP3_GP_DT, "Generic O
17938 .dt_compat = omap3_gp_boards_compat,
17939 .restart = omap3xxx_restart,
17940 MACHINE_END
17941 +
17942 +static const char *omap3630_gp_boards_compat[] __initdata = {
17943 + "ti,omap3-beagle-xm",
17944 + NULL,
17945 +};
17946 +
17947 +DT_MACHINE_START(OMAP3630_GP_DT, "Generic OMAP3630-GP (Flattened Device Tree)")
17948 + .reserve = omap_reserve,
17949 + .map_io = omap3_map_io,
17950 + .init_early = omap3630_init_early,
17951 + .init_irq = omap_intc_of_init,
17952 + .handle_irq = omap3_intc_handle_irq,
17953 + .init_machine = omap_generic_init,
17954 + .init_late = omap3_init_late,
17955 + .init_time = omap3_secure_sync32k_timer_init,
17956 + .dt_compat = omap3630_gp_boards_compat,
17957 + .restart = omap3xxx_restart,
17958 +MACHINE_END
17959 #endif
17960
17961 #ifdef CONFIG_SOC_AM33XX
17962 @@ -174,12 +163,14 @@ static const char *am33xx_boards_compat[
17963 };
17964
17965 DT_MACHINE_START(AM33XX_DT, "Generic AM33XX (Flattened Device Tree)")
17966 - .reserve = omap_reserve,
17967 + .reserve = am33xx_reserve,
17968 .map_io = am33xx_map_io,
17969 .init_early = am33xx_init_early,
17970 + .init_late = am33xx_init_late,
17971 .init_irq = omap_intc_of_init,
17972 .handle_irq = omap3_intc_handle_irq,
17973 .init_machine = omap_generic_init,
17974 + .init_late = am33xx_init_late,
17975 .init_time = omap3_gptimer_timer_init,
17976 .dt_compat = am33xx_boards_compat,
17977 .restart = am33xx_restart,
17978 @@ -219,6 +210,7 @@ DT_MACHINE_START(OMAP5_DT, "Generic OMAP
17979 .init_early = omap5_init_early,
17980 .init_irq = omap_gic_of_init,
17981 .init_machine = omap_generic_init,
17982 + .init_late = omap5_init_late,
17983 .init_time = omap5_realtime_timer_init,
17984 .dt_compat = omap5_boards_compat,
17985 .restart = omap44xx_restart,
17986 @@ -232,12 +224,14 @@ static const char *am43_boards_compat[]
17987 };
17988
17989 DT_MACHINE_START(AM43_DT, "Generic AM43 (Flattened Device Tree)")
17990 + .reserve = am33xx_reserve,
17991 .map_io = am33xx_map_io,
17992 .init_early = am43xx_init_early,
17993 .init_irq = omap_gic_of_init,
17994 .init_machine = omap_generic_init,
17995 .init_time = omap3_sync32k_timer_init,
17996 .dt_compat = am43_boards_compat,
17997 + .restart = am43xx_restart,
17998 MACHINE_END
17999 #endif
18000
18001 @@ -254,6 +248,7 @@ DT_MACHINE_START(DRA7XX_DT, "Generic DRA
18002 .init_early = dra7xx_init_early,
18003 .init_irq = omap_gic_of_init,
18004 .init_machine = omap_generic_init,
18005 + .init_late = dra7xx_init_late,
18006 .init_time = omap5_realtime_timer_init,
18007 .dt_compat = dra7xx_boards_compat,
18008 .restart = omap44xx_restart,
18009 --- a/arch/arm/mach-omap2/board-igep0020.c
18010 +++ b/arch/arm/mach-omap2/board-igep0020.c
18011 @@ -667,7 +667,7 @@ static void __init igep_init(void)
18012 omap_serial_init();
18013 omap_sdrc_init(m65kxxxxam_sdrc_params,
18014 m65kxxxxam_sdrc_params);
18015 - usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
18016 + usb_bind_phy("musb-hdrc.0", 0, "twl4030_usb");
18017 usb_musb_init(NULL);
18018
18019 igep_flash_init();
18020 --- a/arch/arm/mach-omap2/board-ldp.c
18021 +++ b/arch/arm/mach-omap2/board-ldp.c
18022 @@ -403,7 +403,7 @@ static void __init omap_ldp_init(void)
18023 omap_ads7846_init(1, 54, 310, NULL);
18024 omap_serial_init();
18025 omap_sdrc_init(NULL, NULL);
18026 - usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
18027 + usb_bind_phy("musb-hdrc.0", 0, "twl4030_usb");
18028 usb_musb_init(NULL);
18029 board_nand_init(ldp_nand_partitions, ARRAY_SIZE(ldp_nand_partitions),
18030 ZOOM_NAND_CS, 0, nand_default_timings);
18031 --- a/arch/arm/mach-omap2/board-omap3beagle.c
18032 +++ b/arch/arm/mach-omap2/board-omap3beagle.c
18033 @@ -289,18 +289,12 @@ static struct regulator_consumer_supply
18034
18035 static struct gpio_led gpio_leds[];
18036
18037 -/* PHY's VCC regulator might be added later, so flag that we need it */
18038 -static struct usb_phy_gen_xceiv_platform_data hsusb2_phy_data = {
18039 - .needs_vcc = true,
18040 -};
18041 -
18042 static struct usbhs_phy_data phy_data[] = {
18043 {
18044 .port = 2,
18045 .reset_gpio = 147,
18046 .vcc_gpio = -1, /* updated in beagle_twl_gpio_setup */
18047 .vcc_polarity = 1, /* updated in beagle_twl_gpio_setup */
18048 - .platform_data = &hsusb2_phy_data,
18049 },
18050 };
18051
18052 @@ -567,7 +561,7 @@ static void __init omap3_beagle_init(voi
18053 omap_sdrc_init(mt46h32m32lf6_sdrc_params,
18054 mt46h32m32lf6_sdrc_params);
18055
18056 - usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
18057 + usb_bind_phy("musb-hdrc.0", 0, "twl4030_usb");
18058 usb_musb_init(NULL);
18059
18060 usbhs_init(&usbhs_bdata);
18061 --- a/arch/arm/mach-omap2/board-omap3evm.c
18062 +++ b/arch/arm/mach-omap2/board-omap3evm.c
18063 @@ -723,7 +723,7 @@ static void __init omap3_evm_init(void)
18064 omap_mux_init_gpio(135, OMAP_PIN_OUTPUT);
18065 phy_data[0].reset_gpio = 135;
18066 }
18067 - usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
18068 + usb_bind_phy("musb-hdrc.0", 0, "twl4030_usb");
18069 usb_musb_init(&musb_board_data);
18070
18071 usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
18072 --- a/arch/arm/mach-omap2/board-omap3logic.c
18073 +++ b/arch/arm/mach-omap2/board-omap3logic.c
18074 @@ -216,7 +216,7 @@ static void __init omap3logic_init(void)
18075 board_mmc_init();
18076 board_smsc911x_init();
18077
18078 - usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
18079 + usb_bind_phy("musb-hdrc.0", 0, "twl4030_usb");
18080 usb_musb_init(NULL);
18081
18082 /* Ensure SDRC pins are mux'd for self-refresh */
18083 --- a/arch/arm/mach-omap2/board-omap3pandora.c
18084 +++ b/arch/arm/mach-omap2/board-omap3pandora.c
18085 @@ -607,7 +607,7 @@ static void __init omap3pandora_init(voi
18086 usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
18087 usbhs_init(&usbhs_bdata);
18088
18089 - usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
18090 + usb_bind_phy("musb-hdrc.0", 0, "twl4030_usb");
18091 usb_musb_init(NULL);
18092 gpmc_nand_init(&pandora_nand_data, NULL);
18093
18094 --- a/arch/arm/mach-omap2/board-omap3stalker.c
18095 +++ b/arch/arm/mach-omap2/board-omap3stalker.c
18096 @@ -407,7 +407,7 @@ static void __init omap3_stalker_init(vo
18097
18098 omap_serial_init();
18099 omap_sdrc_init(mt46h32m32lf6_sdrc_params, NULL);
18100 - usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
18101 + usb_bind_phy("musb-hdrc.0", 0, "twl4030_usb");
18102 usb_musb_init(NULL);
18103
18104 usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
18105 --- a/arch/arm/mach-omap2/board-omap3touchbook.c
18106 +++ b/arch/arm/mach-omap2/board-omap3touchbook.c
18107 @@ -367,7 +367,7 @@ static void __init omap3_touchbook_init(
18108
18109 /* Touchscreen and accelerometer */
18110 omap_ads7846_init(4, OMAP3_TS_GPIO, 310, &ads7846_pdata);
18111 - usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
18112 + usb_bind_phy("musb-hdrc.0", 0, "twl4030_usb");
18113 usb_musb_init(NULL);
18114
18115 usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
18116 --- a/arch/arm/mach-omap2/board-overo.c
18117 +++ b/arch/arm/mach-omap2/board-overo.c
18118 @@ -511,7 +511,7 @@ static void __init overo_init(void)
18119 mt46h32m32lf6_sdrc_params);
18120 board_nand_init(overo_nand_partitions,
18121 ARRAY_SIZE(overo_nand_partitions), NAND_CS, 0, NULL);
18122 - usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
18123 + usb_bind_phy("musb-hdrc.0", 0, "twl4030_usb");
18124 usb_musb_init(NULL);
18125
18126 usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
18127 --- a/arch/arm/mach-omap2/board-rm680.c
18128 +++ b/arch/arm/mach-omap2/board-rm680.c
18129 @@ -135,7 +135,7 @@ static void __init rm680_init(void)
18130 sdrc_params = nokia_get_sdram_timings();
18131 omap_sdrc_init(sdrc_params, sdrc_params);
18132
18133 - usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
18134 + usb_bind_phy("musb-hdrc.0", 0, "twl4030_usb");
18135 usb_musb_init(NULL);
18136 rm680_peripherals_init();
18137 }
18138 --- a/arch/arm/mach-omap2/board-rx51.c
18139 +++ b/arch/arm/mach-omap2/board-rx51.c
18140 @@ -99,7 +99,7 @@ static void __init rx51_init(void)
18141 sdrc_params = nokia_get_sdram_timings();
18142 omap_sdrc_init(sdrc_params, sdrc_params);
18143
18144 - usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
18145 + usb_bind_phy("musb-hdrc.0", 0, "twl4030_usb");
18146 usb_musb_init(&musb_board_data);
18147 rx51_peripherals_init();
18148
18149 --- a/arch/arm/mach-omap2/board-zoom-peripherals.c
18150 +++ b/arch/arm/mach-omap2/board-zoom-peripherals.c
18151 @@ -353,7 +353,7 @@ void __init zoom_peripherals_init(void)
18152 omap_i2c_init();
18153 pwm_add_table(zoom_pwm_lookup, ARRAY_SIZE(zoom_pwm_lookup));
18154 platform_add_devices(zoom_devices, ARRAY_SIZE(zoom_devices));
18155 - usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
18156 + usb_bind_phy("musb-hdrc.0", 0, "twl4030_usb");
18157 usb_musb_init(NULL);
18158 enable_board_wakeup_source();
18159 omap_serial_init();
18160 --- a/arch/arm/mach-omap2/cclock33xx_data.c
18161 +++ /dev/null
18162 @@ -1,1064 +0,0 @@
18163 -/*
18164 - * AM33XX Clock data
18165 - *
18166 - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
18167 - * Vaibhav Hiremath <hvaibhav@ti.com>
18168 - *
18169 - * This program is free software; you can redistribute it and/or
18170 - * modify it under the terms of the GNU General Public License as
18171 - * published by the Free Software Foundation version 2.
18172 - *
18173 - * This program is distributed "as is" WITHOUT ANY WARRANTY of any
18174 - * kind, whether express or implied; without even the implied warranty
18175 - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18176 - * GNU General Public License for more details.
18177 - */
18178 -
18179 -#include <linux/kernel.h>
18180 -#include <linux/list.h>
18181 -#include <linux/clk-private.h>
18182 -#include <linux/clkdev.h>
18183 -#include <linux/io.h>
18184 -
18185 -#include "am33xx.h"
18186 -#include "soc.h"
18187 -#include "iomap.h"
18188 -#include "clock.h"
18189 -#include "control.h"
18190 -#include "cm.h"
18191 -#include "cm33xx.h"
18192 -#include "cm-regbits-33xx.h"
18193 -#include "prm.h"
18194 -
18195 -/* Modulemode control */
18196 -#define AM33XX_MODULEMODE_HWCTRL_SHIFT 0
18197 -#define AM33XX_MODULEMODE_SWCTRL_SHIFT 1
18198 -
18199 -/*LIST_HEAD(clocks);*/
18200 -
18201 -/* Root clocks */
18202 -
18203 -/* RTC 32k */
18204 -DEFINE_CLK_FIXED_RATE(clk_32768_ck, CLK_IS_ROOT, 32768, 0x0);
18205 -
18206 -/* On-Chip 32KHz RC OSC */
18207 -DEFINE_CLK_FIXED_RATE(clk_rc32k_ck, CLK_IS_ROOT, 32000, 0x0);
18208 -
18209 -/* Crystal input clks */
18210 -DEFINE_CLK_FIXED_RATE(virt_19200000_ck, CLK_IS_ROOT, 19200000, 0x0);
18211 -
18212 -DEFINE_CLK_FIXED_RATE(virt_24000000_ck, CLK_IS_ROOT, 24000000, 0x0);
18213 -
18214 -DEFINE_CLK_FIXED_RATE(virt_25000000_ck, CLK_IS_ROOT, 25000000, 0x0);
18215 -
18216 -DEFINE_CLK_FIXED_RATE(virt_26000000_ck, CLK_IS_ROOT, 26000000, 0x0);
18217 -
18218 -/* Oscillator clock */
18219 -/* 19.2, 24, 25 or 26 MHz */
18220 -static const char *sys_clkin_ck_parents[] = {
18221 - "virt_19200000_ck", "virt_24000000_ck", "virt_25000000_ck",
18222 - "virt_26000000_ck",
18223 -};
18224 -
18225 -/*
18226 - * sys_clk in: input to the dpll and also used as funtional clock for,
18227 - * adc_tsc, smartreflex0-1, timer1-7, mcasp0-1, dcan0-1, cefuse
18228 - *
18229 - */
18230 -DEFINE_CLK_MUX(sys_clkin_ck, sys_clkin_ck_parents, NULL, 0x0,
18231 - AM33XX_CTRL_REGADDR(AM33XX_CONTROL_STATUS),
18232 - AM33XX_CONTROL_STATUS_SYSBOOT1_SHIFT,
18233 - AM33XX_CONTROL_STATUS_SYSBOOT1_WIDTH,
18234 - 0, NULL);
18235 -
18236 -/* External clock - 12 MHz */
18237 -DEFINE_CLK_FIXED_RATE(tclkin_ck, CLK_IS_ROOT, 12000000, 0x0);
18238 -
18239 -/* Module clocks and DPLL outputs */
18240 -
18241 -/* DPLL_CORE */
18242 -static struct dpll_data dpll_core_dd = {
18243 - .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_CORE,
18244 - .clk_bypass = &sys_clkin_ck,
18245 - .clk_ref = &sys_clkin_ck,
18246 - .control_reg = AM33XX_CM_CLKMODE_DPLL_CORE,
18247 - .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
18248 - .idlest_reg = AM33XX_CM_IDLEST_DPLL_CORE,
18249 - .mult_mask = AM33XX_DPLL_MULT_MASK,
18250 - .div1_mask = AM33XX_DPLL_DIV_MASK,
18251 - .enable_mask = AM33XX_DPLL_EN_MASK,
18252 - .idlest_mask = AM33XX_ST_DPLL_CLK_MASK,
18253 - .max_multiplier = 2047,
18254 - .max_divider = 128,
18255 - .min_divider = 1,
18256 -};
18257 -
18258 -/* CLKDCOLDO output */
18259 -static const char *dpll_core_ck_parents[] = {
18260 - "sys_clkin_ck",
18261 -};
18262 -
18263 -static struct clk dpll_core_ck;
18264 -
18265 -static const struct clk_ops dpll_core_ck_ops = {
18266 - .recalc_rate = &omap3_dpll_recalc,
18267 - .get_parent = &omap2_init_dpll_parent,
18268 -};
18269 -
18270 -static struct clk_hw_omap dpll_core_ck_hw = {
18271 - .hw = {
18272 - .clk = &dpll_core_ck,
18273 - },
18274 - .dpll_data = &dpll_core_dd,
18275 - .ops = &clkhwops_omap3_dpll,
18276 -};
18277 -
18278 -DEFINE_STRUCT_CLK(dpll_core_ck, dpll_core_ck_parents, dpll_core_ck_ops);
18279 -
18280 -static const char *dpll_core_x2_ck_parents[] = {
18281 - "dpll_core_ck",
18282 -};
18283 -
18284 -static struct clk dpll_core_x2_ck;
18285 -
18286 -static const struct clk_ops dpll_x2_ck_ops = {
18287 - .recalc_rate = &omap3_clkoutx2_recalc,
18288 -};
18289 -
18290 -static struct clk_hw_omap dpll_core_x2_ck_hw = {
18291 - .hw = {
18292 - .clk = &dpll_core_x2_ck,
18293 - },
18294 - .flags = CLOCK_CLKOUTX2,
18295 -};
18296 -
18297 -DEFINE_STRUCT_CLK(dpll_core_x2_ck, dpll_core_x2_ck_parents, dpll_x2_ck_ops);
18298 -
18299 -DEFINE_CLK_DIVIDER(dpll_core_m4_ck, "dpll_core_x2_ck", &dpll_core_x2_ck,
18300 - 0x0, AM33XX_CM_DIV_M4_DPLL_CORE,
18301 - AM33XX_HSDIVIDER_CLKOUT1_DIV_SHIFT,
18302 - AM33XX_HSDIVIDER_CLKOUT1_DIV_WIDTH, CLK_DIVIDER_ONE_BASED,
18303 - NULL);
18304 -
18305 -DEFINE_CLK_DIVIDER(dpll_core_m5_ck, "dpll_core_x2_ck", &dpll_core_x2_ck,
18306 - 0x0, AM33XX_CM_DIV_M5_DPLL_CORE,
18307 - AM33XX_HSDIVIDER_CLKOUT2_DIV_SHIFT,
18308 - AM33XX_HSDIVIDER_CLKOUT2_DIV_WIDTH,
18309 - CLK_DIVIDER_ONE_BASED, NULL);
18310 -
18311 -DEFINE_CLK_DIVIDER(dpll_core_m6_ck, "dpll_core_x2_ck", &dpll_core_x2_ck,
18312 - 0x0, AM33XX_CM_DIV_M6_DPLL_CORE,
18313 - AM33XX_HSDIVIDER_CLKOUT3_DIV_SHIFT,
18314 - AM33XX_HSDIVIDER_CLKOUT3_DIV_WIDTH,
18315 - CLK_DIVIDER_ONE_BASED, NULL);
18316 -
18317 -
18318 -/* DPLL_MPU */
18319 -static struct dpll_data dpll_mpu_dd = {
18320 - .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_MPU,
18321 - .clk_bypass = &sys_clkin_ck,
18322 - .clk_ref = &sys_clkin_ck,
18323 - .control_reg = AM33XX_CM_CLKMODE_DPLL_MPU,
18324 - .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
18325 - .idlest_reg = AM33XX_CM_IDLEST_DPLL_MPU,
18326 - .mult_mask = AM33XX_DPLL_MULT_MASK,
18327 - .div1_mask = AM33XX_DPLL_DIV_MASK,
18328 - .enable_mask = AM33XX_DPLL_EN_MASK,
18329 - .idlest_mask = AM33XX_ST_DPLL_CLK_MASK,
18330 - .max_multiplier = 2047,
18331 - .max_divider = 128,
18332 - .min_divider = 1,
18333 -};
18334 -
18335 -/* CLKOUT: fdpll/M2 */
18336 -static struct clk dpll_mpu_ck;
18337 -
18338 -static const struct clk_ops dpll_mpu_ck_ops = {
18339 - .enable = &omap3_noncore_dpll_enable,
18340 - .disable = &omap3_noncore_dpll_disable,
18341 - .recalc_rate = &omap3_dpll_recalc,
18342 - .round_rate = &omap2_dpll_round_rate,
18343 - .set_rate = &omap3_noncore_dpll_set_rate,
18344 - .get_parent = &omap2_init_dpll_parent,
18345 -};
18346 -
18347 -static struct clk_hw_omap dpll_mpu_ck_hw = {
18348 - .hw = {
18349 - .clk = &dpll_mpu_ck,
18350 - },
18351 - .dpll_data = &dpll_mpu_dd,
18352 - .ops = &clkhwops_omap3_dpll,
18353 -};
18354 -
18355 -DEFINE_STRUCT_CLK(dpll_mpu_ck, dpll_core_ck_parents, dpll_mpu_ck_ops);
18356 -
18357 -/*
18358 - * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2
18359 - * and ALT_CLK1/2)
18360 - */
18361 -DEFINE_CLK_DIVIDER(dpll_mpu_m2_ck, "dpll_mpu_ck", &dpll_mpu_ck,
18362 - 0x0, AM33XX_CM_DIV_M2_DPLL_MPU, AM33XX_DPLL_CLKOUT_DIV_SHIFT,
18363 - AM33XX_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
18364 -
18365 -/* DPLL_DDR */
18366 -static struct dpll_data dpll_ddr_dd = {
18367 - .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_DDR,
18368 - .clk_bypass = &sys_clkin_ck,
18369 - .clk_ref = &sys_clkin_ck,
18370 - .control_reg = AM33XX_CM_CLKMODE_DPLL_DDR,
18371 - .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
18372 - .idlest_reg = AM33XX_CM_IDLEST_DPLL_DDR,
18373 - .mult_mask = AM33XX_DPLL_MULT_MASK,
18374 - .div1_mask = AM33XX_DPLL_DIV_MASK,
18375 - .enable_mask = AM33XX_DPLL_EN_MASK,
18376 - .idlest_mask = AM33XX_ST_DPLL_CLK_MASK,
18377 - .max_multiplier = 2047,
18378 - .max_divider = 128,
18379 - .min_divider = 1,
18380 -};
18381 -
18382 -/* CLKOUT: fdpll/M2 */
18383 -static struct clk dpll_ddr_ck;
18384 -
18385 -static const struct clk_ops dpll_ddr_ck_ops = {
18386 - .recalc_rate = &omap3_dpll_recalc,
18387 - .get_parent = &omap2_init_dpll_parent,
18388 - .round_rate = &omap2_dpll_round_rate,
18389 - .set_rate = &omap3_noncore_dpll_set_rate,
18390 -};
18391 -
18392 -static struct clk_hw_omap dpll_ddr_ck_hw = {
18393 - .hw = {
18394 - .clk = &dpll_ddr_ck,
18395 - },
18396 - .dpll_data = &dpll_ddr_dd,
18397 - .ops = &clkhwops_omap3_dpll,
18398 -};
18399 -
18400 -DEFINE_STRUCT_CLK(dpll_ddr_ck, dpll_core_ck_parents, dpll_ddr_ck_ops);
18401 -
18402 -/*
18403 - * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2
18404 - * and ALT_CLK1/2)
18405 - */
18406 -DEFINE_CLK_DIVIDER(dpll_ddr_m2_ck, "dpll_ddr_ck", &dpll_ddr_ck,
18407 - 0x0, AM33XX_CM_DIV_M2_DPLL_DDR,
18408 - AM33XX_DPLL_CLKOUT_DIV_SHIFT, AM33XX_DPLL_CLKOUT_DIV_WIDTH,
18409 - CLK_DIVIDER_ONE_BASED, NULL);
18410 -
18411 -/* emif_fck functional clock */
18412 -DEFINE_CLK_FIXED_FACTOR(dpll_ddr_m2_div2_ck, "dpll_ddr_m2_ck", &dpll_ddr_m2_ck,
18413 - 0x0, 1, 2);
18414 -
18415 -/* DPLL_DISP */
18416 -static struct dpll_data dpll_disp_dd = {
18417 - .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_DISP,
18418 - .clk_bypass = &sys_clkin_ck,
18419 - .clk_ref = &sys_clkin_ck,
18420 - .control_reg = AM33XX_CM_CLKMODE_DPLL_DISP,
18421 - .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
18422 - .idlest_reg = AM33XX_CM_IDLEST_DPLL_DISP,
18423 - .mult_mask = AM33XX_DPLL_MULT_MASK,
18424 - .div1_mask = AM33XX_DPLL_DIV_MASK,
18425 - .enable_mask = AM33XX_DPLL_EN_MASK,
18426 - .idlest_mask = AM33XX_ST_DPLL_CLK_MASK,
18427 - .max_multiplier = 2047,
18428 - .max_divider = 128,
18429 - .min_divider = 1,
18430 -};
18431 -
18432 -/* CLKOUT: fdpll/M2 */
18433 -static struct clk dpll_disp_ck;
18434 -
18435 -static struct clk_hw_omap dpll_disp_ck_hw = {
18436 - .hw = {
18437 - .clk = &dpll_disp_ck,
18438 - },
18439 - .dpll_data = &dpll_disp_dd,
18440 - .ops = &clkhwops_omap3_dpll,
18441 -};
18442 -
18443 -DEFINE_STRUCT_CLK(dpll_disp_ck, dpll_core_ck_parents, dpll_ddr_ck_ops);
18444 -
18445 -/*
18446 - * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2
18447 - * and ALT_CLK1/2)
18448 - */
18449 -DEFINE_CLK_DIVIDER(dpll_disp_m2_ck, "dpll_disp_ck", &dpll_disp_ck,
18450 - CLK_SET_RATE_PARENT, AM33XX_CM_DIV_M2_DPLL_DISP,
18451 - AM33XX_DPLL_CLKOUT_DIV_SHIFT, AM33XX_DPLL_CLKOUT_DIV_WIDTH,
18452 - CLK_DIVIDER_ONE_BASED, NULL);
18453 -
18454 -/* DPLL_PER */
18455 -static struct dpll_data dpll_per_dd = {
18456 - .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_PERIPH,
18457 - .clk_bypass = &sys_clkin_ck,
18458 - .clk_ref = &sys_clkin_ck,
18459 - .control_reg = AM33XX_CM_CLKMODE_DPLL_PER,
18460 - .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
18461 - .idlest_reg = AM33XX_CM_IDLEST_DPLL_PER,
18462 - .mult_mask = AM33XX_DPLL_MULT_PERIPH_MASK,
18463 - .div1_mask = AM33XX_DPLL_PER_DIV_MASK,
18464 - .enable_mask = AM33XX_DPLL_EN_MASK,
18465 - .idlest_mask = AM33XX_ST_DPLL_CLK_MASK,
18466 - .max_multiplier = 2047,
18467 - .max_divider = 128,
18468 - .min_divider = 1,
18469 - .flags = DPLL_J_TYPE,
18470 -};
18471 -
18472 -/* CLKDCOLDO */
18473 -static struct clk dpll_per_ck;
18474 -
18475 -static struct clk_hw_omap dpll_per_ck_hw = {
18476 - .hw = {
18477 - .clk = &dpll_per_ck,
18478 - },
18479 - .dpll_data = &dpll_per_dd,
18480 - .ops = &clkhwops_omap3_dpll,
18481 -};
18482 -
18483 -DEFINE_STRUCT_CLK(dpll_per_ck, dpll_core_ck_parents, dpll_ddr_ck_ops);
18484 -
18485 -/* CLKOUT: fdpll/M2 */
18486 -DEFINE_CLK_DIVIDER(dpll_per_m2_ck, "dpll_per_ck", &dpll_per_ck, 0x0,
18487 - AM33XX_CM_DIV_M2_DPLL_PER, AM33XX_DPLL_CLKOUT_DIV_SHIFT,
18488 - AM33XX_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED,
18489 - NULL);
18490 -
18491 -DEFINE_CLK_FIXED_FACTOR(dpll_per_m2_div4_wkupdm_ck, "dpll_per_m2_ck",
18492 - &dpll_per_m2_ck, 0x0, 1, 4);
18493 -
18494 -DEFINE_CLK_FIXED_FACTOR(dpll_per_m2_div4_ck, "dpll_per_m2_ck",
18495 - &dpll_per_m2_ck, 0x0, 1, 4);
18496 -
18497 -DEFINE_CLK_FIXED_FACTOR(dpll_core_m4_div2_ck, "dpll_core_m4_ck",
18498 - &dpll_core_m4_ck, 0x0, 1, 2);
18499 -
18500 -DEFINE_CLK_FIXED_FACTOR(l4_rtc_gclk, "dpll_core_m4_ck", &dpll_core_m4_ck, 0x0,
18501 - 1, 2);
18502 -
18503 -DEFINE_CLK_FIXED_FACTOR(clk_24mhz, "dpll_per_m2_ck", &dpll_per_m2_ck, 0x0, 1,
18504 - 8);
18505 -
18506 -/*
18507 - * Below clock nodes describes clockdomains derived out
18508 - * of core clock.
18509 - */
18510 -static const struct clk_ops clk_ops_null = {
18511 -};
18512 -
18513 -static const char *l3_gclk_parents[] = {
18514 - "dpll_core_m4_ck"
18515 -};
18516 -
18517 -static struct clk l3_gclk;
18518 -DEFINE_STRUCT_CLK_HW_OMAP(l3_gclk, NULL);
18519 -DEFINE_STRUCT_CLK(l3_gclk, l3_gclk_parents, clk_ops_null);
18520 -
18521 -static struct clk l4hs_gclk;
18522 -DEFINE_STRUCT_CLK_HW_OMAP(l4hs_gclk, NULL);
18523 -DEFINE_STRUCT_CLK(l4hs_gclk, l3_gclk_parents, clk_ops_null);
18524 -
18525 -static const char *l3s_gclk_parents[] = {
18526 - "dpll_core_m4_div2_ck"
18527 -};
18528 -
18529 -static struct clk l3s_gclk;
18530 -DEFINE_STRUCT_CLK_HW_OMAP(l3s_gclk, NULL);
18531 -DEFINE_STRUCT_CLK(l3s_gclk, l3s_gclk_parents, clk_ops_null);
18532 -
18533 -static struct clk l4fw_gclk;
18534 -DEFINE_STRUCT_CLK_HW_OMAP(l4fw_gclk, NULL);
18535 -DEFINE_STRUCT_CLK(l4fw_gclk, l3s_gclk_parents, clk_ops_null);
18536 -
18537 -static struct clk l4ls_gclk;
18538 -DEFINE_STRUCT_CLK_HW_OMAP(l4ls_gclk, NULL);
18539 -DEFINE_STRUCT_CLK(l4ls_gclk, l3s_gclk_parents, clk_ops_null);
18540 -
18541 -static struct clk sysclk_div_ck;
18542 -DEFINE_STRUCT_CLK_HW_OMAP(sysclk_div_ck, NULL);
18543 -DEFINE_STRUCT_CLK(sysclk_div_ck, l3_gclk_parents, clk_ops_null);
18544 -
18545 -/*
18546 - * In order to match the clock domain with hwmod clockdomain entry,
18547 - * separate clock nodes is required for the modules which are
18548 - * directly getting their funtioncal clock from sys_clkin.
18549 - */
18550 -static struct clk adc_tsc_fck;
18551 -DEFINE_STRUCT_CLK_HW_OMAP(adc_tsc_fck, NULL);
18552 -DEFINE_STRUCT_CLK(adc_tsc_fck, dpll_core_ck_parents, clk_ops_null);
18553 -
18554 -static struct clk dcan0_fck;
18555 -DEFINE_STRUCT_CLK_HW_OMAP(dcan0_fck, NULL);
18556 -DEFINE_STRUCT_CLK(dcan0_fck, dpll_core_ck_parents, clk_ops_null);
18557 -
18558 -static struct clk dcan1_fck;
18559 -DEFINE_STRUCT_CLK_HW_OMAP(dcan1_fck, NULL);
18560 -DEFINE_STRUCT_CLK(dcan1_fck, dpll_core_ck_parents, clk_ops_null);
18561 -
18562 -static struct clk mcasp0_fck;
18563 -DEFINE_STRUCT_CLK_HW_OMAP(mcasp0_fck, NULL);
18564 -DEFINE_STRUCT_CLK(mcasp0_fck, dpll_core_ck_parents, clk_ops_null);
18565 -
18566 -static struct clk mcasp1_fck;
18567 -DEFINE_STRUCT_CLK_HW_OMAP(mcasp1_fck, NULL);
18568 -DEFINE_STRUCT_CLK(mcasp1_fck, dpll_core_ck_parents, clk_ops_null);
18569 -
18570 -static struct clk smartreflex0_fck;
18571 -DEFINE_STRUCT_CLK_HW_OMAP(smartreflex0_fck, NULL);
18572 -DEFINE_STRUCT_CLK(smartreflex0_fck, dpll_core_ck_parents, clk_ops_null);
18573 -
18574 -static struct clk smartreflex1_fck;
18575 -DEFINE_STRUCT_CLK_HW_OMAP(smartreflex1_fck, NULL);
18576 -DEFINE_STRUCT_CLK(smartreflex1_fck, dpll_core_ck_parents, clk_ops_null);
18577 -
18578 -static struct clk sha0_fck;
18579 -DEFINE_STRUCT_CLK_HW_OMAP(sha0_fck, NULL);
18580 -DEFINE_STRUCT_CLK(sha0_fck, dpll_core_ck_parents, clk_ops_null);
18581 -
18582 -static struct clk aes0_fck;
18583 -DEFINE_STRUCT_CLK_HW_OMAP(aes0_fck, NULL);
18584 -DEFINE_STRUCT_CLK(aes0_fck, dpll_core_ck_parents, clk_ops_null);
18585 -
18586 -static struct clk rng_fck;
18587 -DEFINE_STRUCT_CLK_HW_OMAP(rng_fck, NULL);
18588 -DEFINE_STRUCT_CLK(rng_fck, dpll_core_ck_parents, clk_ops_null);
18589 -
18590 -/*
18591 - * Modules clock nodes
18592 - *
18593 - * The following clock leaf nodes are added for the moment because:
18594 - *
18595 - * - hwmod data is not present for these modules, either hwmod
18596 - * control is not required or its not populated.
18597 - * - Driver code is not yet migrated to use hwmod/runtime pm
18598 - * - Modules outside kernel access (to disable them by default)
18599 - *
18600 - * - mmu (gfx domain)
18601 - * - cefuse
18602 - * - usbotg_fck (its additional clock and not really a modulemode)
18603 - * - ieee5000
18604 - */
18605 -
18606 -DEFINE_CLK_GATE(mmu_fck, "dpll_core_m4_ck", &dpll_core_m4_ck, 0x0,
18607 - AM33XX_CM_GFX_MMUDATA_CLKCTRL, AM33XX_MODULEMODE_SWCTRL_SHIFT,
18608 - 0x0, NULL);
18609 -
18610 -DEFINE_CLK_GATE(cefuse_fck, "sys_clkin_ck", &sys_clkin_ck, 0x0,
18611 - AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL, AM33XX_MODULEMODE_SWCTRL_SHIFT,
18612 - 0x0, NULL);
18613 -
18614 -/*
18615 - * clkdiv32 is generated from fixed division of 732.4219
18616 - */
18617 -DEFINE_CLK_FIXED_FACTOR(clkdiv32k_ck, "clk_24mhz", &clk_24mhz, 0x0, 1, 732);
18618 -
18619 -static struct clk clkdiv32k_ick;
18620 -
18621 -static const char *clkdiv32k_ick_parent_names[] = {
18622 - "clkdiv32k_ck",
18623 -};
18624 -
18625 -static const struct clk_ops clkdiv32k_ick_ops = {
18626 - .enable = &omap2_dflt_clk_enable,
18627 - .disable = &omap2_dflt_clk_disable,
18628 - .is_enabled = &omap2_dflt_clk_is_enabled,
18629 - .init = &omap2_init_clk_clkdm,
18630 -};
18631 -
18632 -static struct clk_hw_omap clkdiv32k_ick_hw = {
18633 - .hw = {
18634 - .clk = &clkdiv32k_ick,
18635 - },
18636 - .enable_reg = AM33XX_CM_PER_CLKDIV32K_CLKCTRL,
18637 - .enable_bit = AM33XX_MODULEMODE_SWCTRL_SHIFT,
18638 - .clkdm_name = "clk_24mhz_clkdm",
18639 -};
18640 -
18641 -DEFINE_STRUCT_CLK(clkdiv32k_ick, clkdiv32k_ick_parent_names, clkdiv32k_ick_ops);
18642 -
18643 -/* "usbotg_fck" is an additional clock and not really a modulemode */
18644 -DEFINE_CLK_GATE(usbotg_fck, "dpll_per_ck", &dpll_per_ck, 0x0,
18645 - AM33XX_CM_CLKDCOLDO_DPLL_PER, AM33XX_ST_DPLL_CLKDCOLDO_SHIFT,
18646 - 0x0, NULL);
18647 -
18648 -DEFINE_CLK_GATE(ieee5000_fck, "dpll_core_m4_div2_ck", &dpll_core_m4_div2_ck,
18649 - 0x0, AM33XX_CM_PER_IEEE5000_CLKCTRL,
18650 - AM33XX_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
18651 -
18652 -/* Timers */
18653 -static const struct clksel timer1_clkmux_sel[] = {
18654 - { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
18655 - { .parent = &clkdiv32k_ick, .rates = div_1_1_rates },
18656 - { .parent = &tclkin_ck, .rates = div_1_2_rates },
18657 - { .parent = &clk_rc32k_ck, .rates = div_1_3_rates },
18658 - { .parent = &clk_32768_ck, .rates = div_1_4_rates },
18659 - { .parent = NULL },
18660 -};
18661 -
18662 -static const char *timer1_ck_parents[] = {
18663 - "sys_clkin_ck", "clkdiv32k_ick", "tclkin_ck", "clk_rc32k_ck",
18664 - "clk_32768_ck",
18665 -};
18666 -
18667 -static struct clk timer1_fck;
18668 -
18669 -static const struct clk_ops timer1_fck_ops = {
18670 - .recalc_rate = &omap2_clksel_recalc,
18671 - .get_parent = &omap2_clksel_find_parent_index,
18672 - .set_parent = &omap2_clksel_set_parent,
18673 - .init = &omap2_init_clk_clkdm,
18674 -};
18675 -
18676 -static struct clk_hw_omap timer1_fck_hw = {
18677 - .hw = {
18678 - .clk = &timer1_fck,
18679 - },
18680 - .clkdm_name = "l4ls_clkdm",
18681 - .clksel = timer1_clkmux_sel,
18682 - .clksel_reg = AM33XX_CLKSEL_TIMER1MS_CLK,
18683 - .clksel_mask = AM33XX_CLKSEL_0_2_MASK,
18684 -};
18685 -
18686 -DEFINE_STRUCT_CLK(timer1_fck, timer1_ck_parents, timer1_fck_ops);
18687 -
18688 -static const struct clksel timer2_to_7_clk_sel[] = {
18689 - { .parent = &tclkin_ck, .rates = div_1_0_rates },
18690 - { .parent = &sys_clkin_ck, .rates = div_1_1_rates },
18691 - { .parent = &clkdiv32k_ick, .rates = div_1_2_rates },
18692 - { .parent = NULL },
18693 -};
18694 -
18695 -static const char *timer2_to_7_ck_parents[] = {
18696 - "tclkin_ck", "sys_clkin_ck", "clkdiv32k_ick",
18697 -};
18698 -
18699 -static struct clk timer2_fck;
18700 -
18701 -static struct clk_hw_omap timer2_fck_hw = {
18702 - .hw = {
18703 - .clk = &timer2_fck,
18704 - },
18705 - .clkdm_name = "l4ls_clkdm",
18706 - .clksel = timer2_to_7_clk_sel,
18707 - .clksel_reg = AM33XX_CLKSEL_TIMER2_CLK,
18708 - .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
18709 -};
18710 -
18711 -DEFINE_STRUCT_CLK(timer2_fck, timer2_to_7_ck_parents, timer1_fck_ops);
18712 -
18713 -static struct clk timer3_fck;
18714 -
18715 -static struct clk_hw_omap timer3_fck_hw = {
18716 - .hw = {
18717 - .clk = &timer3_fck,
18718 - },
18719 - .clkdm_name = "l4ls_clkdm",
18720 - .clksel = timer2_to_7_clk_sel,
18721 - .clksel_reg = AM33XX_CLKSEL_TIMER3_CLK,
18722 - .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
18723 -};
18724 -
18725 -DEFINE_STRUCT_CLK(timer3_fck, timer2_to_7_ck_parents, timer1_fck_ops);
18726 -
18727 -static struct clk timer4_fck;
18728 -
18729 -static struct clk_hw_omap timer4_fck_hw = {
18730 - .hw = {
18731 - .clk = &timer4_fck,
18732 - },
18733 - .clkdm_name = "l4ls_clkdm",
18734 - .clksel = timer2_to_7_clk_sel,
18735 - .clksel_reg = AM33XX_CLKSEL_TIMER4_CLK,
18736 - .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
18737 -};
18738 -
18739 -DEFINE_STRUCT_CLK(timer4_fck, timer2_to_7_ck_parents, timer1_fck_ops);
18740 -
18741 -static struct clk timer5_fck;
18742 -
18743 -static struct clk_hw_omap timer5_fck_hw = {
18744 - .hw = {
18745 - .clk = &timer5_fck,
18746 - },
18747 - .clkdm_name = "l4ls_clkdm",
18748 - .clksel = timer2_to_7_clk_sel,
18749 - .clksel_reg = AM33XX_CLKSEL_TIMER5_CLK,
18750 - .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
18751 -};
18752 -
18753 -DEFINE_STRUCT_CLK(timer5_fck, timer2_to_7_ck_parents, timer1_fck_ops);
18754 -
18755 -static struct clk timer6_fck;
18756 -
18757 -static struct clk_hw_omap timer6_fck_hw = {
18758 - .hw = {
18759 - .clk = &timer6_fck,
18760 - },
18761 - .clkdm_name = "l4ls_clkdm",
18762 - .clksel = timer2_to_7_clk_sel,
18763 - .clksel_reg = AM33XX_CLKSEL_TIMER6_CLK,
18764 - .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
18765 -};
18766 -
18767 -DEFINE_STRUCT_CLK(timer6_fck, timer2_to_7_ck_parents, timer1_fck_ops);
18768 -
18769 -static struct clk timer7_fck;
18770 -
18771 -static struct clk_hw_omap timer7_fck_hw = {
18772 - .hw = {
18773 - .clk = &timer7_fck,
18774 - },
18775 - .clkdm_name = "l4ls_clkdm",
18776 - .clksel = timer2_to_7_clk_sel,
18777 - .clksel_reg = AM33XX_CLKSEL_TIMER7_CLK,
18778 - .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
18779 -};
18780 -
18781 -DEFINE_STRUCT_CLK(timer7_fck, timer2_to_7_ck_parents, timer1_fck_ops);
18782 -
18783 -DEFINE_CLK_FIXED_FACTOR(cpsw_125mhz_gclk,
18784 - "dpll_core_m5_ck",
18785 - &dpll_core_m5_ck,
18786 - 0x0,
18787 - 1, 2);
18788 -
18789 -static const struct clk_ops cpsw_fck_ops = {
18790 - .recalc_rate = &omap2_clksel_recalc,
18791 - .get_parent = &omap2_clksel_find_parent_index,
18792 - .set_parent = &omap2_clksel_set_parent,
18793 -};
18794 -
18795 -static const struct clksel cpsw_cpts_rft_clkmux_sel[] = {
18796 - { .parent = &dpll_core_m5_ck, .rates = div_1_0_rates },
18797 - { .parent = &dpll_core_m4_ck, .rates = div_1_1_rates },
18798 - { .parent = NULL },
18799 -};
18800 -
18801 -static const char *cpsw_cpts_rft_ck_parents[] = {
18802 - "dpll_core_m5_ck", "dpll_core_m4_ck",
18803 -};
18804 -
18805 -static struct clk cpsw_cpts_rft_clk;
18806 -
18807 -static struct clk_hw_omap cpsw_cpts_rft_clk_hw = {
18808 - .hw = {
18809 - .clk = &cpsw_cpts_rft_clk,
18810 - },
18811 - .clkdm_name = "cpsw_125mhz_clkdm",
18812 - .clksel = cpsw_cpts_rft_clkmux_sel,
18813 - .clksel_reg = AM33XX_CM_CPTS_RFT_CLKSEL,
18814 - .clksel_mask = AM33XX_CLKSEL_0_0_MASK,
18815 -};
18816 -
18817 -DEFINE_STRUCT_CLK(cpsw_cpts_rft_clk, cpsw_cpts_rft_ck_parents, cpsw_fck_ops);
18818 -
18819 -
18820 -/* gpio */
18821 -static const char *gpio0_ck_parents[] = {
18822 - "clk_rc32k_ck", "clk_32768_ck", "clkdiv32k_ick",
18823 -};
18824 -
18825 -static const struct clksel gpio0_dbclk_mux_sel[] = {
18826 - { .parent = &clk_rc32k_ck, .rates = div_1_0_rates },
18827 - { .parent = &clk_32768_ck, .rates = div_1_1_rates },
18828 - { .parent = &clkdiv32k_ick, .rates = div_1_2_rates },
18829 - { .parent = NULL },
18830 -};
18831 -
18832 -static const struct clk_ops gpio_fck_ops = {
18833 - .recalc_rate = &omap2_clksel_recalc,
18834 - .get_parent = &omap2_clksel_find_parent_index,
18835 - .set_parent = &omap2_clksel_set_parent,
18836 - .init = &omap2_init_clk_clkdm,
18837 -};
18838 -
18839 -static struct clk gpio0_dbclk_mux_ck;
18840 -
18841 -static struct clk_hw_omap gpio0_dbclk_mux_ck_hw = {
18842 - .hw = {
18843 - .clk = &gpio0_dbclk_mux_ck,
18844 - },
18845 - .clkdm_name = "l4_wkup_clkdm",
18846 - .clksel = gpio0_dbclk_mux_sel,
18847 - .clksel_reg = AM33XX_CLKSEL_GPIO0_DBCLK,
18848 - .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
18849 -};
18850 -
18851 -DEFINE_STRUCT_CLK(gpio0_dbclk_mux_ck, gpio0_ck_parents, gpio_fck_ops);
18852 -
18853 -DEFINE_CLK_GATE(gpio0_dbclk, "gpio0_dbclk_mux_ck", &gpio0_dbclk_mux_ck, 0x0,
18854 - AM33XX_CM_WKUP_GPIO0_CLKCTRL,
18855 - AM33XX_OPTFCLKEN_GPIO0_GDBCLK_SHIFT, 0x0, NULL);
18856 -
18857 -DEFINE_CLK_GATE(gpio1_dbclk, "clkdiv32k_ick", &clkdiv32k_ick, 0x0,
18858 - AM33XX_CM_PER_GPIO1_CLKCTRL,
18859 - AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT, 0x0, NULL);
18860 -
18861 -DEFINE_CLK_GATE(gpio2_dbclk, "clkdiv32k_ick", &clkdiv32k_ick, 0x0,
18862 - AM33XX_CM_PER_GPIO2_CLKCTRL,
18863 - AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT, 0x0, NULL);
18864 -
18865 -DEFINE_CLK_GATE(gpio3_dbclk, "clkdiv32k_ick", &clkdiv32k_ick, 0x0,
18866 - AM33XX_CM_PER_GPIO3_CLKCTRL,
18867 - AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT, 0x0, NULL);
18868 -
18869 -
18870 -static const char *pruss_ck_parents[] = {
18871 - "l3_gclk", "dpll_disp_m2_ck",
18872 -};
18873 -
18874 -static const struct clksel pruss_ocp_clk_mux_sel[] = {
18875 - { .parent = &l3_gclk, .rates = div_1_0_rates },
18876 - { .parent = &dpll_disp_m2_ck, .rates = div_1_1_rates },
18877 - { .parent = NULL },
18878 -};
18879 -
18880 -static struct clk pruss_ocp_gclk;
18881 -
18882 -static struct clk_hw_omap pruss_ocp_gclk_hw = {
18883 - .hw = {
18884 - .clk = &pruss_ocp_gclk,
18885 - },
18886 - .clkdm_name = "pruss_ocp_clkdm",
18887 - .clksel = pruss_ocp_clk_mux_sel,
18888 - .clksel_reg = AM33XX_CLKSEL_PRUSS_OCP_CLK,
18889 - .clksel_mask = AM33XX_CLKSEL_0_0_MASK,
18890 -};
18891 -
18892 -DEFINE_STRUCT_CLK(pruss_ocp_gclk, pruss_ck_parents, gpio_fck_ops);
18893 -
18894 -static const char *lcd_ck_parents[] = {
18895 - "dpll_disp_m2_ck", "dpll_core_m5_ck", "dpll_per_m2_ck",
18896 -};
18897 -
18898 -static const struct clksel lcd_clk_mux_sel[] = {
18899 - { .parent = &dpll_disp_m2_ck, .rates = div_1_0_rates },
18900 - { .parent = &dpll_core_m5_ck, .rates = div_1_1_rates },
18901 - { .parent = &dpll_per_m2_ck, .rates = div_1_2_rates },
18902 - { .parent = NULL },
18903 -};
18904 -
18905 -static struct clk lcd_gclk;
18906 -
18907 -static struct clk_hw_omap lcd_gclk_hw = {
18908 - .hw = {
18909 - .clk = &lcd_gclk,
18910 - },
18911 - .clkdm_name = "lcdc_clkdm",
18912 - .clksel = lcd_clk_mux_sel,
18913 - .clksel_reg = AM33XX_CLKSEL_LCDC_PIXEL_CLK,
18914 - .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
18915 -};
18916 -
18917 -DEFINE_STRUCT_CLK_FLAGS(lcd_gclk, lcd_ck_parents,
18918 - gpio_fck_ops, CLK_SET_RATE_PARENT);
18919 -
18920 -DEFINE_CLK_FIXED_FACTOR(mmc_clk, "dpll_per_m2_ck", &dpll_per_m2_ck, 0x0, 1, 2);
18921 -
18922 -static const char *gfx_ck_parents[] = {
18923 - "dpll_core_m4_ck", "dpll_per_m2_ck",
18924 -};
18925 -
18926 -static const struct clksel gfx_clksel_sel[] = {
18927 - { .parent = &dpll_core_m4_ck, .rates = div_1_0_rates },
18928 - { .parent = &dpll_per_m2_ck, .rates = div_1_1_rates },
18929 - { .parent = NULL },
18930 -};
18931 -
18932 -static struct clk gfx_fclk_clksel_ck;
18933 -
18934 -static struct clk_hw_omap gfx_fclk_clksel_ck_hw = {
18935 - .hw = {
18936 - .clk = &gfx_fclk_clksel_ck,
18937 - },
18938 - .clksel = gfx_clksel_sel,
18939 - .clksel_reg = AM33XX_CLKSEL_GFX_FCLK,
18940 - .clksel_mask = AM33XX_CLKSEL_GFX_FCLK_MASK,
18941 -};
18942 -
18943 -DEFINE_STRUCT_CLK(gfx_fclk_clksel_ck, gfx_ck_parents, gpio_fck_ops);
18944 -
18945 -static const struct clk_div_table div_1_0_2_1_rates[] = {
18946 - { .div = 1, .val = 0, },
18947 - { .div = 2, .val = 1, },
18948 - { .div = 0 },
18949 -};
18950 -
18951 -DEFINE_CLK_DIVIDER_TABLE(gfx_fck_div_ck, "gfx_fclk_clksel_ck",
18952 - &gfx_fclk_clksel_ck, 0x0, AM33XX_CLKSEL_GFX_FCLK,
18953 - AM33XX_CLKSEL_0_0_SHIFT, AM33XX_CLKSEL_0_0_WIDTH,
18954 - 0x0, div_1_0_2_1_rates, NULL);
18955 -
18956 -static const char *sysclkout_ck_parents[] = {
18957 - "clk_32768_ck", "l3_gclk", "dpll_ddr_m2_ck", "dpll_per_m2_ck",
18958 - "lcd_gclk",
18959 -};
18960 -
18961 -static const struct clksel sysclkout_pre_sel[] = {
18962 - { .parent = &clk_32768_ck, .rates = div_1_0_rates },
18963 - { .parent = &l3_gclk, .rates = div_1_1_rates },
18964 - { .parent = &dpll_ddr_m2_ck, .rates = div_1_2_rates },
18965 - { .parent = &dpll_per_m2_ck, .rates = div_1_3_rates },
18966 - { .parent = &lcd_gclk, .rates = div_1_4_rates },
18967 - { .parent = NULL },
18968 -};
18969 -
18970 -static struct clk sysclkout_pre_ck;
18971 -
18972 -static struct clk_hw_omap sysclkout_pre_ck_hw = {
18973 - .hw = {
18974 - .clk = &sysclkout_pre_ck,
18975 - },
18976 - .clksel = sysclkout_pre_sel,
18977 - .clksel_reg = AM33XX_CM_CLKOUT_CTRL,
18978 - .clksel_mask = AM33XX_CLKOUT2SOURCE_MASK,
18979 -};
18980 -
18981 -DEFINE_STRUCT_CLK(sysclkout_pre_ck, sysclkout_ck_parents, gpio_fck_ops);
18982 -
18983 -/* Divide by 8 clock rates with default clock is 1/1*/
18984 -static const struct clk_div_table div8_rates[] = {
18985 - { .div = 1, .val = 0, },
18986 - { .div = 2, .val = 1, },
18987 - { .div = 3, .val = 2, },
18988 - { .div = 4, .val = 3, },
18989 - { .div = 5, .val = 4, },
18990 - { .div = 6, .val = 5, },
18991 - { .div = 7, .val = 6, },
18992 - { .div = 8, .val = 7, },
18993 - { .div = 0 },
18994 -};
18995 -
18996 -DEFINE_CLK_DIVIDER_TABLE(clkout2_div_ck, "sysclkout_pre_ck", &sysclkout_pre_ck,
18997 - 0x0, AM33XX_CM_CLKOUT_CTRL, AM33XX_CLKOUT2DIV_SHIFT,
18998 - AM33XX_CLKOUT2DIV_WIDTH, 0x0, div8_rates, NULL);
18999 -
19000 -DEFINE_CLK_GATE(clkout2_ck, "clkout2_div_ck", &clkout2_div_ck, 0x0,
19001 - AM33XX_CM_CLKOUT_CTRL, AM33XX_CLKOUT2EN_SHIFT, 0x0, NULL);
19002 -
19003 -static const char *wdt_ck_parents[] = {
19004 - "clk_rc32k_ck", "clkdiv32k_ick",
19005 -};
19006 -
19007 -static const struct clksel wdt_clkmux_sel[] = {
19008 - { .parent = &clk_rc32k_ck, .rates = div_1_0_rates },
19009 - { .parent = &clkdiv32k_ick, .rates = div_1_1_rates },
19010 - { .parent = NULL },
19011 -};
19012 -
19013 -static struct clk wdt1_fck;
19014 -
19015 -static struct clk_hw_omap wdt1_fck_hw = {
19016 - .hw = {
19017 - .clk = &wdt1_fck,
19018 - },
19019 - .clkdm_name = "l4_wkup_clkdm",
19020 - .clksel = wdt_clkmux_sel,
19021 - .clksel_reg = AM33XX_CLKSEL_WDT1_CLK,
19022 - .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
19023 -};
19024 -
19025 -DEFINE_STRUCT_CLK(wdt1_fck, wdt_ck_parents, gpio_fck_ops);
19026 -
19027 -static const char *pwmss_clk_parents[] = {
19028 - "dpll_per_m2_ck",
19029 -};
19030 -
19031 -static const struct clk_ops ehrpwm_tbclk_ops = {
19032 - .enable = &omap2_dflt_clk_enable,
19033 - .disable = &omap2_dflt_clk_disable,
19034 -};
19035 -
19036 -DEFINE_CLK_OMAP_MUX_GATE(ehrpwm0_tbclk, "l4ls_clkdm",
19037 - NULL, NULL, 0,
19038 - AM33XX_CTRL_REGADDR(AM33XX_PWMSS_TBCLK_CLKCTRL),
19039 - AM33XX_PWMSS0_TBCLKEN_SHIFT,
19040 - NULL, pwmss_clk_parents, ehrpwm_tbclk_ops);
19041 -
19042 -DEFINE_CLK_OMAP_MUX_GATE(ehrpwm1_tbclk, "l4ls_clkdm",
19043 - NULL, NULL, 0,
19044 - AM33XX_CTRL_REGADDR(AM33XX_PWMSS_TBCLK_CLKCTRL),
19045 - AM33XX_PWMSS1_TBCLKEN_SHIFT,
19046 - NULL, pwmss_clk_parents, ehrpwm_tbclk_ops);
19047 -
19048 -DEFINE_CLK_OMAP_MUX_GATE(ehrpwm2_tbclk, "l4ls_clkdm",
19049 - NULL, NULL, 0,
19050 - AM33XX_CTRL_REGADDR(AM33XX_PWMSS_TBCLK_CLKCTRL),
19051 - AM33XX_PWMSS2_TBCLKEN_SHIFT,
19052 - NULL, pwmss_clk_parents, ehrpwm_tbclk_ops);
19053 -
19054 -/*
19055 - * debugss optional clocks
19056 - */
19057 -DEFINE_CLK_GATE(dbg_sysclk_ck, "sys_clkin_ck", &sys_clkin_ck,
19058 - 0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
19059 - AM33XX_OPTFCLKEN_DBGSYSCLK_SHIFT, 0x0, NULL);
19060 -
19061 -DEFINE_CLK_GATE(dbg_clka_ck, "dpll_core_m4_ck", &dpll_core_m4_ck,
19062 - 0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
19063 - AM33XX_OPTCLK_DEBUG_CLKA_SHIFT, 0x0, NULL);
19064 -
19065 -static const char *stm_pmd_clock_mux_ck_parents[] = {
19066 - "dbg_sysclk_ck", "dbg_clka_ck",
19067 -};
19068 -
19069 -DEFINE_CLK_MUX(stm_pmd_clock_mux_ck, stm_pmd_clock_mux_ck_parents, NULL, 0x0,
19070 - AM33XX_CM_WKUP_DEBUGSS_CLKCTRL, AM33XX_STM_PMD_CLKSEL_SHIFT,
19071 - AM33XX_STM_PMD_CLKSEL_WIDTH, 0x0, NULL);
19072 -
19073 -DEFINE_CLK_MUX(trace_pmd_clk_mux_ck, stm_pmd_clock_mux_ck_parents, NULL, 0x0,
19074 - AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
19075 - AM33XX_TRC_PMD_CLKSEL_SHIFT,
19076 - AM33XX_TRC_PMD_CLKSEL_WIDTH, 0x0, NULL);
19077 -
19078 -DEFINE_CLK_DIVIDER(stm_clk_div_ck, "stm_pmd_clock_mux_ck",
19079 - &stm_pmd_clock_mux_ck, 0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
19080 - AM33XX_STM_PMD_CLKDIVSEL_SHIFT,
19081 - AM33XX_STM_PMD_CLKDIVSEL_WIDTH, CLK_DIVIDER_POWER_OF_TWO,
19082 - NULL);
19083 -
19084 -DEFINE_CLK_DIVIDER(trace_clk_div_ck, "trace_pmd_clk_mux_ck",
19085 - &trace_pmd_clk_mux_ck, 0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
19086 - AM33XX_TRC_PMD_CLKDIVSEL_SHIFT,
19087 - AM33XX_TRC_PMD_CLKDIVSEL_WIDTH, CLK_DIVIDER_POWER_OF_TWO,
19088 - NULL);
19089 -
19090 -/*
19091 - * clkdev
19092 - */
19093 -static struct omap_clk am33xx_clks[] = {
19094 - CLK(NULL, "clk_32768_ck", &clk_32768_ck),
19095 - CLK(NULL, "clk_rc32k_ck", &clk_rc32k_ck),
19096 - CLK(NULL, "virt_19200000_ck", &virt_19200000_ck),
19097 - CLK(NULL, "virt_24000000_ck", &virt_24000000_ck),
19098 - CLK(NULL, "virt_25000000_ck", &virt_25000000_ck),
19099 - CLK(NULL, "virt_26000000_ck", &virt_26000000_ck),
19100 - CLK(NULL, "sys_clkin_ck", &sys_clkin_ck),
19101 - CLK(NULL, "tclkin_ck", &tclkin_ck),
19102 - CLK(NULL, "dpll_core_ck", &dpll_core_ck),
19103 - CLK(NULL, "dpll_core_x2_ck", &dpll_core_x2_ck),
19104 - CLK(NULL, "dpll_core_m4_ck", &dpll_core_m4_ck),
19105 - CLK(NULL, "dpll_core_m5_ck", &dpll_core_m5_ck),
19106 - CLK(NULL, "dpll_core_m6_ck", &dpll_core_m6_ck),
19107 - CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck),
19108 - CLK("cpu0", NULL, &dpll_mpu_ck),
19109 - CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck),
19110 - CLK(NULL, "dpll_ddr_ck", &dpll_ddr_ck),
19111 - CLK(NULL, "dpll_ddr_m2_ck", &dpll_ddr_m2_ck),
19112 - CLK(NULL, "dpll_ddr_m2_div2_ck", &dpll_ddr_m2_div2_ck),
19113 - CLK(NULL, "dpll_disp_ck", &dpll_disp_ck),
19114 - CLK(NULL, "dpll_disp_m2_ck", &dpll_disp_m2_ck),
19115 - CLK(NULL, "dpll_per_ck", &dpll_per_ck),
19116 - CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck),
19117 - CLK(NULL, "dpll_per_m2_div4_wkupdm_ck", &dpll_per_m2_div4_wkupdm_ck),
19118 - CLK(NULL, "dpll_per_m2_div4_ck", &dpll_per_m2_div4_ck),
19119 - CLK(NULL, "adc_tsc_fck", &adc_tsc_fck),
19120 - CLK(NULL, "cefuse_fck", &cefuse_fck),
19121 - CLK(NULL, "clkdiv32k_ck", &clkdiv32k_ck),
19122 - CLK(NULL, "clkdiv32k_ick", &clkdiv32k_ick),
19123 - CLK(NULL, "dcan0_fck", &dcan0_fck),
19124 - CLK("481cc000.d_can", NULL, &dcan0_fck),
19125 - CLK(NULL, "dcan1_fck", &dcan1_fck),
19126 - CLK("481d0000.d_can", NULL, &dcan1_fck),
19127 - CLK(NULL, "pruss_ocp_gclk", &pruss_ocp_gclk),
19128 - CLK(NULL, "mcasp0_fck", &mcasp0_fck),
19129 - CLK(NULL, "mcasp1_fck", &mcasp1_fck),
19130 - CLK(NULL, "mmu_fck", &mmu_fck),
19131 - CLK(NULL, "smartreflex0_fck", &smartreflex0_fck),
19132 - CLK(NULL, "smartreflex1_fck", &smartreflex1_fck),
19133 - CLK(NULL, "sha0_fck", &sha0_fck),
19134 - CLK(NULL, "aes0_fck", &aes0_fck),
19135 - CLK(NULL, "rng_fck", &rng_fck),
19136 - CLK(NULL, "timer1_fck", &timer1_fck),
19137 - CLK(NULL, "timer2_fck", &timer2_fck),
19138 - CLK(NULL, "timer3_fck", &timer3_fck),
19139 - CLK(NULL, "timer4_fck", &timer4_fck),
19140 - CLK(NULL, "timer5_fck", &timer5_fck),
19141 - CLK(NULL, "timer6_fck", &timer6_fck),
19142 - CLK(NULL, "timer7_fck", &timer7_fck),
19143 - CLK(NULL, "usbotg_fck", &usbotg_fck),
19144 - CLK(NULL, "ieee5000_fck", &ieee5000_fck),
19145 - CLK(NULL, "wdt1_fck", &wdt1_fck),
19146 - CLK(NULL, "l4_rtc_gclk", &l4_rtc_gclk),
19147 - CLK(NULL, "l3_gclk", &l3_gclk),
19148 - CLK(NULL, "dpll_core_m4_div2_ck", &dpll_core_m4_div2_ck),
19149 - CLK(NULL, "l4hs_gclk", &l4hs_gclk),
19150 - CLK(NULL, "l3s_gclk", &l3s_gclk),
19151 - CLK(NULL, "l4fw_gclk", &l4fw_gclk),
19152 - CLK(NULL, "l4ls_gclk", &l4ls_gclk),
19153 - CLK(NULL, "clk_24mhz", &clk_24mhz),
19154 - CLK(NULL, "sysclk_div_ck", &sysclk_div_ck),
19155 - CLK(NULL, "cpsw_125mhz_gclk", &cpsw_125mhz_gclk),
19156 - CLK(NULL, "cpsw_cpts_rft_clk", &cpsw_cpts_rft_clk),
19157 - CLK(NULL, "gpio0_dbclk_mux_ck", &gpio0_dbclk_mux_ck),
19158 - CLK(NULL, "gpio0_dbclk", &gpio0_dbclk),
19159 - CLK(NULL, "gpio1_dbclk", &gpio1_dbclk),
19160 - CLK(NULL, "gpio2_dbclk", &gpio2_dbclk),
19161 - CLK(NULL, "gpio3_dbclk", &gpio3_dbclk),
19162 - CLK(NULL, "lcd_gclk", &lcd_gclk),
19163 - CLK(NULL, "mmc_clk", &mmc_clk),
19164 - CLK(NULL, "gfx_fclk_clksel_ck", &gfx_fclk_clksel_ck),
19165 - CLK(NULL, "gfx_fck_div_ck", &gfx_fck_div_ck),
19166 - CLK(NULL, "sysclkout_pre_ck", &sysclkout_pre_ck),
19167 - CLK(NULL, "clkout2_div_ck", &clkout2_div_ck),
19168 - CLK(NULL, "timer_32k_ck", &clkdiv32k_ick),
19169 - CLK(NULL, "timer_sys_ck", &sys_clkin_ck),
19170 - CLK(NULL, "dbg_sysclk_ck", &dbg_sysclk_ck),
19171 - CLK(NULL, "dbg_clka_ck", &dbg_clka_ck),
19172 - CLK(NULL, "stm_pmd_clock_mux_ck", &stm_pmd_clock_mux_ck),
19173 - CLK(NULL, "trace_pmd_clk_mux_ck", &trace_pmd_clk_mux_ck),
19174 - CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck),
19175 - CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck),
19176 - CLK(NULL, "clkout2_ck", &clkout2_ck),
19177 - CLK("48300200.ehrpwm", "tbclk", &ehrpwm0_tbclk),
19178 - CLK("48302200.ehrpwm", "tbclk", &ehrpwm1_tbclk),
19179 - CLK("48304200.ehrpwm", "tbclk", &ehrpwm2_tbclk),
19180 -};
19181 -
19182 -
19183 -static const char *enable_init_clks[] = {
19184 - "dpll_ddr_m2_ck",
19185 - "dpll_mpu_m2_ck",
19186 - "l3_gclk",
19187 - "l4hs_gclk",
19188 - "l4fw_gclk",
19189 - "l4ls_gclk",
19190 - "clkout2_ck", /* Required for external peripherals like, Audio codecs */
19191 -};
19192 -
19193 -int __init am33xx_clk_init(void)
19194 -{
19195 - if (soc_is_am33xx())
19196 - cpu_mask = RATE_IN_AM33XX;
19197 -
19198 - omap_clocks_register(am33xx_clks, ARRAY_SIZE(am33xx_clks));
19199 -
19200 - omap2_clk_disable_autoidle_all();
19201 -
19202 - omap2_clk_enable_init_clocks(enable_init_clks,
19203 - ARRAY_SIZE(enable_init_clks));
19204 -
19205 - /* TRM ERRATA: Timer 3 & 6 default parent (TCLKIN) may not be always
19206 - * physically present, in such a case HWMOD enabling of
19207 - * clock would be failure with default parent. And timer
19208 - * probe thinks clock is already enabled, this leads to
19209 - * crash upon accessing timer 3 & 6 registers in probe.
19210 - * Fix by setting parent of both these timers to master
19211 - * oscillator clock.
19212 - */
19213 -
19214 - clk_set_parent(&timer3_fck, &sys_clkin_ck);
19215 - clk_set_parent(&timer6_fck, &sys_clkin_ck);
19216 - /*
19217 - * The On-Chip 32K RC Osc clock is not an accurate clock-source as per
19218 - * the design/spec, so as a result, for example, timer which supposed
19219 - * to get expired @60Sec, but will expire somewhere ~@40Sec, which is
19220 - * not expected by any use-case, so change WDT1 clock source to PRCM
19221 - * 32KHz clock.
19222 - */
19223 - clk_set_parent(&wdt1_fck, &clkdiv32k_ick);
19224 -
19225 - return 0;
19226 -}
19227 --- a/arch/arm/mach-omap2/clkt_dpll.c
19228 +++ b/arch/arm/mach-omap2/clkt_dpll.c
19229 @@ -209,7 +209,7 @@ u8 omap2_init_dpll_parent(struct clk_hw
19230 if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
19231 v == OMAP3XXX_EN_DPLL_FRBYPASS)
19232 return 1;
19233 - } else if (soc_is_am33xx() || cpu_is_omap44xx()) {
19234 + } else if (soc_is_am33xx() || cpu_is_omap44xx() || soc_is_am43xx()) {
19235 if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||
19236 v == OMAP4XXX_EN_DPLL_FRBYPASS ||
19237 v == OMAP4XXX_EN_DPLL_MNBYPASS)
19238 @@ -255,7 +255,7 @@ unsigned long omap2_get_dpll_rate(struct
19239 if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
19240 v == OMAP3XXX_EN_DPLL_FRBYPASS)
19241 return __clk_get_rate(dd->clk_bypass);
19242 - } else if (soc_is_am33xx() || cpu_is_omap44xx()) {
19243 + } else if (soc_is_am33xx() || cpu_is_omap44xx() || soc_is_am43xx()) {
19244 if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||
19245 v == OMAP4XXX_EN_DPLL_FRBYPASS ||
19246 v == OMAP4XXX_EN_DPLL_MNBYPASS)
19247 --- a/arch/arm/mach-omap2/clock3xxx.h
19248 +++ b/arch/arm/mach-omap2/clock3xxx.h
19249 @@ -9,11 +9,12 @@
19250 #define __ARCH_ARM_MACH_OMAP2_CLOCK3XXX_H
19251
19252 int omap3xxx_clk_init(void);
19253 -int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate,
19254 - unsigned long parent_rate);
19255 +int omap3430_clk_init(void);
19256 +int omap3630_clk_init(void);
19257 +int ti81xx_clk_init(void);
19258 +int am35xx_clk_init(void);
19259 int omap3_core_dpll_m2_set_rate(struct clk_hw *clk, unsigned long rate,
19260 unsigned long parent_rate);
19261 -void omap3_clk_lock_dpll5(void);
19262
19263 extern struct clk *sdrc_ick_p;
19264 extern struct clk *arm_fck_p;
19265 --- a/arch/arm/mach-omap2/clock.c
19266 +++ b/arch/arm/mach-omap2/clock.c
19267 @@ -520,6 +520,9 @@ int omap2_clk_enable_autoidle_all(void)
19268 list_for_each_entry(c, &clk_hw_omap_clocks, node)
19269 if (c->ops && c->ops->allow_idle)
19270 c->ops->allow_idle(c);
19271 +
19272 + of_omap_clk_allow_autoidle_all();
19273 +
19274 return 0;
19275 }
19276
19277 @@ -539,6 +542,9 @@ int omap2_clk_disable_autoidle_all(void)
19278 list_for_each_entry(c, &clk_hw_omap_clocks, node)
19279 if (c->ops && c->ops->deny_idle)
19280 c->ops->deny_idle(c);
19281 +
19282 + of_omap_clk_deny_autoidle_all();
19283 +
19284 return 0;
19285 }
19286
19287 --- a/arch/arm/mach-omap2/clockdomain.h
19288 +++ b/arch/arm/mach-omap2/clockdomain.h
19289 @@ -132,7 +132,7 @@ struct clockdomain {
19290 u8 _flags;
19291 const u8 dep_bit;
19292 const u8 prcm_partition;
19293 - const s16 cm_inst;
19294 + const u16 cm_inst;
19295 const u16 clkdm_offs;
19296 struct clkdm_dep *wkdep_srcs;
19297 struct clkdm_dep *sleepdep_srcs;
19298 @@ -215,6 +215,7 @@ extern void __init omap242x_clockdomains
19299 extern void __init omap243x_clockdomains_init(void);
19300 extern void __init omap3xxx_clockdomains_init(void);
19301 extern void __init am33xx_clockdomains_init(void);
19302 +extern void am43xx_clockdomains_init(void);
19303 extern void __init omap44xx_clockdomains_init(void);
19304 extern void __init omap54xx_clockdomains_init(void);
19305 extern void __init dra7xx_clockdomains_init(void);
19306 @@ -226,6 +227,7 @@ extern struct clkdm_ops omap2_clkdm_oper
19307 extern struct clkdm_ops omap3_clkdm_operations;
19308 extern struct clkdm_ops omap4_clkdm_operations;
19309 extern struct clkdm_ops am33xx_clkdm_operations;
19310 +extern struct clkdm_ops am43xx_clkdm_operations;
19311
19312 extern struct clkdm_dep gfx_24xx_wkdeps[];
19313 extern struct clkdm_dep dsp_24xx_wkdeps[];
19314 --- /dev/null
19315 +++ b/arch/arm/mach-omap2/clockdomains43xx_data.c
19316 @@ -0,0 +1,199 @@
19317 +/*
19318 + * AM43xx Clock domains framework
19319 + *
19320 + * Copyright (C) 2013 Texas Instruments, Inc.
19321 + *
19322 + * This file is made by modifying the file generated automatically
19323 + * from the OMAP hardware databases.
19324 + *
19325 + * This program is free software; you can redistribute it and/or modify
19326 + * it under the terms of the GNU General Public License version 2 as
19327 + * published by the Free Software Foundation.
19328 + */
19329 +
19330 +#include <linux/kernel.h>
19331 +#include <linux/io.h>
19332 +
19333 +#include "clockdomain.h"
19334 +#include "prcm44xx.h"
19335 +#include "prcm43xx.h"
19336 +
19337 +static struct clockdomain l4_cefuse_43xx_clkdm = {
19338 + .name = "l4_cefuse_clkdm",
19339 + .pwrdm = { .name = "cefuse_pwrdm" },
19340 + .prcm_partition = AM43XX_CM_PARTITION,
19341 + .cm_inst = AM43XX_CM_CEFUSE_INST,
19342 + .clkdm_offs = AM43XX_CM_CEFUSE_CEFUSE_CDOFFS,
19343 + .flags = CLKDM_CAN_SWSUP,
19344 +};
19345 +
19346 +static struct clockdomain mpu_43xx_clkdm = {
19347 + .name = "mpu_clkdm",
19348 + .pwrdm = { .name = "mpu_pwrdm" },
19349 + .prcm_partition = AM43XX_CM_PARTITION,
19350 + .cm_inst = AM43XX_CM_MPU_INST,
19351 + .clkdm_offs = AM43XX_CM_MPU_MPU_CDOFFS,
19352 + .flags = CLKDM_CAN_HWSUP_SWSUP,
19353 +};
19354 +
19355 +static struct clockdomain l4ls_43xx_clkdm = {
19356 + .name = "l4ls_clkdm",
19357 + .pwrdm = { .name = "per_pwrdm" },
19358 + .prcm_partition = AM43XX_CM_PARTITION,
19359 + .cm_inst = AM43XX_CM_PER_INST,
19360 + .clkdm_offs = AM43XX_CM_PER_L4LS_CDOFFS,
19361 + .flags = CLKDM_CAN_SWSUP,
19362 +};
19363 +
19364 +static struct clockdomain tamper_43xx_clkdm = {
19365 + .name = "tamper_clkdm",
19366 + .pwrdm = { .name = "tamper_pwrdm" },
19367 + .prcm_partition = AM43XX_CM_PARTITION,
19368 + .cm_inst = AM43XX_CM_TAMPER_INST,
19369 + .clkdm_offs = AM43XX_CM_TAMPER_TAMPER_CDOFFS,
19370 + .flags = CLKDM_CAN_SWSUP,
19371 +};
19372 +
19373 +static struct clockdomain l4_rtc_43xx_clkdm = {
19374 + .name = "l4_rtc_clkdm",
19375 + .pwrdm = { .name = "rtc_pwrdm" },
19376 + .prcm_partition = AM43XX_CM_PARTITION,
19377 + .cm_inst = AM43XX_CM_RTC_INST,
19378 + .clkdm_offs = AM43XX_CM_RTC_RTC_CDOFFS,
19379 + .flags = CLKDM_CAN_SWSUP,
19380 +};
19381 +
19382 +static struct clockdomain pruss_ocp_43xx_clkdm = {
19383 + .name = "pruss_ocp_clkdm",
19384 + .pwrdm = { .name = "per_pwrdm" },
19385 + .prcm_partition = AM43XX_CM_PARTITION,
19386 + .cm_inst = AM43XX_CM_PER_INST,
19387 + .clkdm_offs = AM43XX_CM_PER_ICSS_CDOFFS,
19388 + .flags = CLKDM_CAN_SWSUP,
19389 +};
19390 +
19391 +static struct clockdomain ocpwp_l3_43xx_clkdm = {
19392 + .name = "ocpwp_l3_clkdm",
19393 + .pwrdm = { .name = "per_pwrdm" },
19394 + .prcm_partition = AM43XX_CM_PARTITION,
19395 + .cm_inst = AM43XX_CM_PER_INST,
19396 + .clkdm_offs = AM43XX_CM_PER_OCPWP_L3_CDOFFS,
19397 + .flags = CLKDM_CAN_SWSUP,
19398 +};
19399 +
19400 +static struct clockdomain l3s_tsc_43xx_clkdm = {
19401 + .name = "l3s_tsc_clkdm",
19402 + .pwrdm = { .name = "wkup_pwrdm" },
19403 + .prcm_partition = AM43XX_CM_PARTITION,
19404 + .cm_inst = AM43XX_CM_WKUP_INST,
19405 + .clkdm_offs = AM43XX_CM_WKUP_L3S_TSC_CDOFFS,
19406 + .flags = CLKDM_CAN_SWSUP,
19407 +};
19408 +
19409 +static struct clockdomain dss_43xx_clkdm = {
19410 + .name = "dss_clkdm",
19411 + .pwrdm = { .name = "per_pwrdm" },
19412 + .prcm_partition = AM43XX_CM_PARTITION,
19413 + .cm_inst = AM43XX_CM_PER_INST,
19414 + .clkdm_offs = AM43XX_CM_PER_DSS_CDOFFS,
19415 + .flags = CLKDM_CAN_SWSUP,
19416 +};
19417 +
19418 +static struct clockdomain l3_aon_43xx_clkdm = {
19419 + .name = "l3_aon_clkdm",
19420 + .pwrdm = { .name = "wkup_pwrdm" },
19421 + .prcm_partition = AM43XX_CM_PARTITION,
19422 + .cm_inst = AM43XX_CM_WKUP_INST,
19423 + .clkdm_offs = AM43XX_CM_WKUP_L3_AON_CDOFFS,
19424 + .flags = CLKDM_CAN_SWSUP,
19425 +};
19426 +
19427 +static struct clockdomain emif_43xx_clkdm = {
19428 + .name = "emif_clkdm",
19429 + .pwrdm = { .name = "per_pwrdm" },
19430 + .prcm_partition = AM43XX_CM_PARTITION,
19431 + .cm_inst = AM43XX_CM_PER_INST,
19432 + .clkdm_offs = AM43XX_CM_PER_EMIF_CDOFFS,
19433 + .flags = CLKDM_CAN_SWSUP,
19434 +};
19435 +
19436 +static struct clockdomain l4_wkup_aon_43xx_clkdm = {
19437 + .name = "l4_wkup_aon_clkdm",
19438 + .pwrdm = { .name = "wkup_pwrdm" },
19439 + .prcm_partition = AM43XX_CM_PARTITION,
19440 + .cm_inst = AM43XX_CM_WKUP_INST,
19441 + .clkdm_offs = AM43XX_CM_WKUP_L4_WKUP_AON_CDOFFS,
19442 +};
19443 +
19444 +static struct clockdomain l3_43xx_clkdm = {
19445 + .name = "l3_clkdm",
19446 + .pwrdm = { .name = "per_pwrdm" },
19447 + .prcm_partition = AM43XX_CM_PARTITION,
19448 + .cm_inst = AM43XX_CM_PER_INST,
19449 + .clkdm_offs = AM43XX_CM_PER_L3_CDOFFS,
19450 + .flags = CLKDM_CAN_SWSUP,
19451 +};
19452 +
19453 +static struct clockdomain l4_wkup_43xx_clkdm = {
19454 + .name = "l4_wkup_clkdm",
19455 + .pwrdm = { .name = "wkup_pwrdm" },
19456 + .prcm_partition = AM43XX_CM_PARTITION,
19457 + .cm_inst = AM43XX_CM_WKUP_INST,
19458 + .clkdm_offs = AM43XX_CM_WKUP_WKUP_CDOFFS,
19459 + .flags = CLKDM_CAN_SWSUP,
19460 +};
19461 +
19462 +static struct clockdomain cpsw_125mhz_43xx_clkdm = {
19463 + .name = "cpsw_125mhz_clkdm",
19464 + .pwrdm = { .name = "per_pwrdm" },
19465 + .prcm_partition = AM43XX_CM_PARTITION,
19466 + .cm_inst = AM43XX_CM_PER_INST,
19467 + .clkdm_offs = AM43XX_CM_PER_CPSW_CDOFFS,
19468 + .flags = CLKDM_CAN_SWSUP,
19469 +};
19470 +
19471 +static struct clockdomain gfx_l3_43xx_clkdm = {
19472 + .name = "gfx_l3_clkdm",
19473 + .pwrdm = { .name = "gfx_pwrdm" },
19474 + .prcm_partition = AM43XX_CM_PARTITION,
19475 + .cm_inst = AM43XX_CM_GFX_INST,
19476 + .clkdm_offs = AM43XX_CM_GFX_GFX_L3_CDOFFS,
19477 + .flags = CLKDM_CAN_SWSUP,
19478 +};
19479 +
19480 +static struct clockdomain l3s_43xx_clkdm = {
19481 + .name = "l3s_clkdm",
19482 + .pwrdm = { .name = "per_pwrdm" },
19483 + .prcm_partition = AM43XX_CM_PARTITION,
19484 + .cm_inst = AM43XX_CM_PER_INST,
19485 + .clkdm_offs = AM43XX_CM_PER_L3S_CDOFFS,
19486 + .flags = CLKDM_CAN_SWSUP,
19487 +};
19488 +
19489 +static struct clockdomain *clockdomains_am43xx[] __initdata = {
19490 + &l4_cefuse_43xx_clkdm,
19491 + &mpu_43xx_clkdm,
19492 + &l4ls_43xx_clkdm,
19493 + &tamper_43xx_clkdm,
19494 + &l4_rtc_43xx_clkdm,
19495 + &pruss_ocp_43xx_clkdm,
19496 + &ocpwp_l3_43xx_clkdm,
19497 + &l3s_tsc_43xx_clkdm,
19498 + &dss_43xx_clkdm,
19499 + &l3_aon_43xx_clkdm,
19500 + &emif_43xx_clkdm,
19501 + &l4_wkup_aon_43xx_clkdm,
19502 + &l3_43xx_clkdm,
19503 + &l4_wkup_43xx_clkdm,
19504 + &cpsw_125mhz_43xx_clkdm,
19505 + &gfx_l3_43xx_clkdm,
19506 + &l3s_43xx_clkdm,
19507 + NULL
19508 +};
19509 +
19510 +void __init am43xx_clockdomains_init(void)
19511 +{
19512 + clkdm_register_platform_funcs(&am43xx_clkdm_operations);
19513 + clkdm_register_clkdms(clockdomains_am43xx);
19514 + clkdm_complete_init();
19515 +}
19516 --- a/arch/arm/mach-omap2/clockdomains7xx_data.c
19517 +++ b/arch/arm/mach-omap2/clockdomains7xx_data.c
19518 @@ -409,7 +409,7 @@ static struct clockdomain l4sec_7xx_clkd
19519 .dep_bit = DRA7XX_L4SEC_STATDEP_SHIFT,
19520 .wkdep_srcs = l4sec_wkup_sleep_deps,
19521 .sleepdep_srcs = l4sec_wkup_sleep_deps,
19522 - .flags = CLKDM_CAN_HWSUP_SWSUP,
19523 + .flags = CLKDM_CAN_SWSUP,
19524 };
19525
19526 static struct clockdomain l3main1_7xx_clkdm = {
19527 @@ -554,7 +554,7 @@ static struct clockdomain dss_7xx_clkdm
19528 .dep_bit = DRA7XX_DSS_STATDEP_SHIFT,
19529 .wkdep_srcs = dss_wkup_sleep_deps,
19530 .sleepdep_srcs = dss_wkup_sleep_deps,
19531 - .flags = CLKDM_CAN_HWSUP_SWSUP,
19532 + .flags = CLKDM_CAN_SWSUP,
19533 };
19534
19535 static struct clockdomain emif_7xx_clkdm = {
19536 --- a/arch/arm/mach-omap2/clock.h
19537 +++ b/arch/arm/mach-omap2/clock.h
19538 @@ -21,6 +21,7 @@
19539
19540 #include <linux/clkdev.h>
19541 #include <linux/clk-provider.h>
19542 +#include <linux/clk/ti.h>
19543
19544 struct omap_clk {
19545 u16 cpu;
19546 @@ -37,7 +38,6 @@ struct omap_clk {
19547 }
19548
19549 struct clockdomain;
19550 -#define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw)
19551
19552 #define DEFINE_STRUCT_CLK(_name, _parent_array_name, _clkops_name) \
19553 static struct clk _name = { \
19554 @@ -178,141 +178,6 @@ struct clksel {
19555 const struct clksel_rate *rates;
19556 };
19557
19558 -/**
19559 - * struct dpll_data - DPLL registers and integration data
19560 - * @mult_div1_reg: register containing the DPLL M and N bitfields
19561 - * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg
19562 - * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg
19563 - * @clk_bypass: struct clk pointer to the clock's bypass clock input
19564 - * @clk_ref: struct clk pointer to the clock's reference clock input
19565 - * @control_reg: register containing the DPLL mode bitfield
19566 - * @enable_mask: mask of the DPLL mode bitfield in @control_reg
19567 - * @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate()
19568 - * @last_rounded_m: cache of the last M result of omap2_dpll_round_rate()
19569 - * @last_rounded_m4xen: cache of the last M4X result of
19570 - * omap4_dpll_regm4xen_round_rate()
19571 - * @last_rounded_lpmode: cache of the last lpmode result of
19572 - * omap4_dpll_lpmode_recalc()
19573 - * @max_multiplier: maximum valid non-bypass multiplier value (actual)
19574 - * @last_rounded_n: cache of the last N result of omap2_dpll_round_rate()
19575 - * @min_divider: minimum valid non-bypass divider value (actual)
19576 - * @max_divider: maximum valid non-bypass divider value (actual)
19577 - * @modes: possible values of @enable_mask
19578 - * @autoidle_reg: register containing the DPLL autoidle mode bitfield
19579 - * @idlest_reg: register containing the DPLL idle status bitfield
19580 - * @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg
19581 - * @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg
19582 - * @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg
19583 - * @lpmode_mask: mask of the DPLL low-power mode bitfield in @control_reg
19584 - * @m4xen_mask: mask of the DPLL M4X multiplier bitfield in @control_reg
19585 - * @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg
19586 - * @recal_en_bit: bitshift of the PRM_IRQENABLE_* bit for recalibration IRQs
19587 - * @recal_st_bit: bitshift of the PRM_IRQSTATUS_* bit for recalibration IRQs
19588 - * @flags: DPLL type/features (see below)
19589 - *
19590 - * Possible values for @flags:
19591 - * DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs)
19592 - *
19593 - * @freqsel_mask is only used on the OMAP34xx family and AM35xx.
19594 - *
19595 - * XXX Some DPLLs have multiple bypass inputs, so it's not technically
19596 - * correct to only have one @clk_bypass pointer.
19597 - *
19598 - * XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m,
19599 - * @last_rounded_n) should be separated from the runtime-fixed fields
19600 - * and placed into a different structure, so that the runtime-fixed data
19601 - * can be placed into read-only space.
19602 - */
19603 -struct dpll_data {
19604 - void __iomem *mult_div1_reg;
19605 - u32 mult_mask;
19606 - u32 div1_mask;
19607 - struct clk *clk_bypass;
19608 - struct clk *clk_ref;
19609 - void __iomem *control_reg;
19610 - u32 enable_mask;
19611 - unsigned long last_rounded_rate;
19612 - u16 last_rounded_m;
19613 - u8 last_rounded_m4xen;
19614 - u8 last_rounded_lpmode;
19615 - u16 max_multiplier;
19616 - u8 last_rounded_n;
19617 - u8 min_divider;
19618 - u16 max_divider;
19619 - u8 modes;
19620 - void __iomem *autoidle_reg;
19621 - void __iomem *idlest_reg;
19622 - u32 autoidle_mask;
19623 - u32 freqsel_mask;
19624 - u32 idlest_mask;
19625 - u32 dco_mask;
19626 - u32 sddiv_mask;
19627 - u32 lpmode_mask;
19628 - u32 m4xen_mask;
19629 - u8 auto_recal_bit;
19630 - u8 recal_en_bit;
19631 - u8 recal_st_bit;
19632 - u8 flags;
19633 -};
19634 -
19635 -/*
19636 - * struct clk.flags possibilities
19637 - *
19638 - * XXX document the rest of the clock flags here
19639 - *
19640 - * CLOCK_CLKOUTX2: (OMAP4 only) DPLL CLKOUT and CLKOUTX2 GATE_CTRL
19641 - * bits share the same register. This flag allows the
19642 - * omap4_dpllmx*() code to determine which GATE_CTRL bit field
19643 - * should be used. This is a temporary solution - a better approach
19644 - * would be to associate clock type-specific data with the clock,
19645 - * similar to the struct dpll_data approach.
19646 - */
19647 -#define ENABLE_REG_32BIT (1 << 0) /* Use 32-bit access */
19648 -#define CLOCK_IDLE_CONTROL (1 << 1)
19649 -#define CLOCK_NO_IDLE_PARENT (1 << 2)
19650 -#define ENABLE_ON_INIT (1 << 3) /* Enable upon framework init */
19651 -#define INVERT_ENABLE (1 << 4) /* 0 enables, 1 disables */
19652 -#define CLOCK_CLKOUTX2 (1 << 5)
19653 -
19654 -/**
19655 - * struct clk_hw_omap - OMAP struct clk
19656 - * @node: list_head connecting this clock into the full clock list
19657 - * @enable_reg: register to write to enable the clock (see @enable_bit)
19658 - * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg)
19659 - * @flags: see "struct clk.flags possibilities" above
19660 - * @clksel_reg: for clksel clks, register va containing src/divisor select
19661 - * @clksel_mask: bitmask in @clksel_reg for the src/divisor selector
19662 - * @clksel: for clksel clks, pointer to struct clksel for this clock
19663 - * @dpll_data: for DPLLs, pointer to struct dpll_data for this clock
19664 - * @clkdm_name: clockdomain name that this clock is contained in
19665 - * @clkdm: pointer to struct clockdomain, resolved from @clkdm_name at runtime
19666 - * @rate_offset: bitshift for rate selection bitfield (OMAP1 only)
19667 - * @src_offset: bitshift for source selection bitfield (OMAP1 only)
19668 - *
19669 - * XXX @rate_offset, @src_offset should probably be removed and OMAP1
19670 - * clock code converted to use clksel.
19671 - *
19672 - */
19673 -
19674 -struct clk_hw_omap_ops;
19675 -
19676 -struct clk_hw_omap {
19677 - struct clk_hw hw;
19678 - struct list_head node;
19679 - unsigned long fixed_rate;
19680 - u8 fixed_div;
19681 - void __iomem *enable_reg;
19682 - u8 enable_bit;
19683 - u8 flags;
19684 - void __iomem *clksel_reg;
19685 - u32 clksel_mask;
19686 - const struct clksel *clksel;
19687 - struct dpll_data *dpll_data;
19688 - const char *clkdm_name;
19689 - struct clockdomain *clkdm;
19690 - const struct clk_hw_omap_ops *ops;
19691 -};
19692 -
19693 struct clk_hw_omap_ops {
19694 void (*find_idlest)(struct clk_hw_omap *oclk,
19695 void __iomem **idlest_reg,
19696 @@ -348,36 +213,13 @@ unsigned long omap_fixed_divisor_recalc(
19697 #define OMAP4XXX_EN_DPLL_FRBYPASS 0x6
19698 #define OMAP4XXX_EN_DPLL_LOCKED 0x7
19699
19700 -/* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
19701 -#define DPLL_LOW_POWER_STOP 0x1
19702 -#define DPLL_LOW_POWER_BYPASS 0x5
19703 -#define DPLL_LOCKED 0x7
19704 -
19705 -/* DPLL Type and DCO Selection Flags */
19706 -#define DPLL_J_TYPE 0x1
19707 -
19708 -long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
19709 - unsigned long *parent_rate);
19710 -unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate);
19711 -int omap3_noncore_dpll_enable(struct clk_hw *hw);
19712 -void omap3_noncore_dpll_disable(struct clk_hw *hw);
19713 -int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
19714 - unsigned long parent_rate);
19715 u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk);
19716 void omap3_dpll_allow_idle(struct clk_hw_omap *clk);
19717 void omap3_dpll_deny_idle(struct clk_hw_omap *clk);
19718 -unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
19719 - unsigned long parent_rate);
19720 int omap4_dpllmx_gatectrl_read(struct clk_hw_omap *clk);
19721 void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk);
19722 void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk);
19723 -unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
19724 - unsigned long parent_rate);
19725 -long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
19726 - unsigned long target_rate,
19727 - unsigned long *parent_rate);
19728
19729 -void omap2_init_clk_clkdm(struct clk_hw *clk);
19730 void __init omap2_clk_disable_clkdm_control(void);
19731
19732 /* clkt_clksel.c public functions */
19733 @@ -396,22 +238,15 @@ int omap2_clksel_set_parent(struct clk_h
19734 extern void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk);
19735 extern void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk);
19736
19737 -u8 omap2_init_dpll_parent(struct clk_hw *hw);
19738 unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk);
19739
19740 -int omap2_dflt_clk_enable(struct clk_hw *hw);
19741 -void omap2_dflt_clk_disable(struct clk_hw *hw);
19742 -int omap2_dflt_clk_is_enabled(struct clk_hw *hw);
19743 void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk,
19744 void __iomem **other_reg,
19745 u8 *other_bit);
19746 void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk,
19747 void __iomem **idlest_reg,
19748 u8 *idlest_bit, u8 *idlest_val);
19749 -void omap2_init_clk_hw_omap_clocks(struct clk *clk);
19750 int omap2_clk_enable_autoidle_all(void);
19751 -int omap2_clk_disable_autoidle_all(void);
19752 -void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks);
19753 int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name);
19754 void omap2_clk_print_new_rates(const char *hfclkin_ck_name,
19755 const char *core_ck_name,
19756 @@ -431,19 +266,8 @@ extern const struct clksel_rate gfx_l3_r
19757 extern const struct clksel_rate dsp_ick_rates[];
19758 extern struct clk dummy_ck;
19759
19760 -extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;
19761 -extern const struct clk_hw_omap_ops clkhwops_iclk_wait;
19762 -extern const struct clk_hw_omap_ops clkhwops_wait;
19763 -extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
19764 -extern const struct clk_hw_omap_ops clkhwops_iclk;
19765 extern const struct clk_hw_omap_ops clkhwops_omap3430es2_ssi_wait;
19766 -extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait;
19767 -extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait;
19768 -extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait;
19769 -extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait;
19770 extern const struct clk_hw_omap_ops clkhwops_omap3430es2_hsotgusb_wait;
19771 -extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait;
19772 -extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait;
19773 extern const struct clk_hw_omap_ops clkhwops_apll54;
19774 extern const struct clk_hw_omap_ops clkhwops_apll96;
19775 extern const struct clk_hw_omap_ops clkhwops_omap2xxx_dpll;
19776 @@ -460,8 +284,5 @@ extern const struct clksel_rate div31_1t
19777
19778 extern int am33xx_clk_init(void);
19779
19780 -extern int omap2_clkops_enable_clkdm(struct clk_hw *hw);
19781 -extern void omap2_clkops_disable_clkdm(struct clk_hw *hw);
19782 -
19783 extern void omap_clocks_register(struct omap_clk *oclks, int cnt);
19784 #endif
19785 --- a/arch/arm/mach-omap2/cm33xx.c
19786 +++ b/arch/arm/mach-omap2/cm33xx.c
19787 @@ -48,13 +48,13 @@
19788 /* Private functions */
19789
19790 /* Read a register in a CM instance */
19791 -static inline u32 am33xx_cm_read_reg(s16 inst, u16 idx)
19792 +static inline u32 am33xx_cm_read_reg(u16 inst, u16 idx)
19793 {
19794 return __raw_readl(cm_base + inst + idx);
19795 }
19796
19797 /* Write into a register in a CM */
19798 -static inline void am33xx_cm_write_reg(u32 val, s16 inst, u16 idx)
19799 +static inline void am33xx_cm_write_reg(u32 val, u16 inst, u16 idx)
19800 {
19801 __raw_writel(val, cm_base + inst + idx);
19802 }
19803 @@ -82,7 +82,7 @@ static inline u32 am33xx_cm_clear_reg_bi
19804 return am33xx_cm_rmw_reg_bits(bits, 0x0, inst, idx);
19805 }
19806
19807 -static inline u32 am33xx_cm_read_reg_bits(u16 inst, s16 idx, u32 mask)
19808 +static inline u32 am33xx_cm_read_reg_bits(u16 inst, u16 idx, u32 mask)
19809 {
19810 u32 v;
19811
19812 @@ -102,7 +102,7 @@ static inline u32 am33xx_cm_read_reg_bit
19813 * Return the IDLEST bitfield of a CM_*_CLKCTRL register, shifted down to
19814 * bit 0.
19815 */
19816 -static u32 _clkctrl_idlest(u16 inst, s16 cdoffs, u16 clkctrl_offs)
19817 +static u32 _clkctrl_idlest(u16 inst, u16 cdoffs, u16 clkctrl_offs)
19818 {
19819 u32 v = am33xx_cm_read_reg(inst, clkctrl_offs);
19820 v &= AM33XX_IDLEST_MASK;
19821 @@ -119,7 +119,7 @@ static u32 _clkctrl_idlest(u16 inst, s16
19822 * Returns true if the module's CM_*_CLKCTRL.IDLEST bitfield is either
19823 * *FUNCTIONAL or *INTERFACE_IDLE; false otherwise.
19824 */
19825 -static bool _is_module_ready(u16 inst, s16 cdoffs, u16 clkctrl_offs)
19826 +static bool _is_module_ready(u16 inst, u16 cdoffs, u16 clkctrl_offs)
19827 {
19828 u32 v;
19829
19830 @@ -138,7 +138,7 @@ static bool _is_module_ready(u16 inst, s
19831 * @c must be the unshifted value for CLKTRCTRL - i.e., this function
19832 * will handle the shift itself.
19833 */
19834 -static void _clktrctrl_write(u8 c, s16 inst, u16 cdoffs)
19835 +static void _clktrctrl_write(u8 c, u16 inst, u16 cdoffs)
19836 {
19837 u32 v;
19838
19839 @@ -158,7 +158,7 @@ static void _clktrctrl_write(u8 c, s16 i
19840 * Returns true if the clockdomain referred to by (@inst, @cdoffs)
19841 * is in hardware-supervised idle mode, or 0 otherwise.
19842 */
19843 -bool am33xx_cm_is_clkdm_in_hwsup(s16 inst, u16 cdoffs)
19844 +bool am33xx_cm_is_clkdm_in_hwsup(u16 inst, u16 cdoffs)
19845 {
19846 u32 v;
19847
19848 @@ -177,7 +177,7 @@ bool am33xx_cm_is_clkdm_in_hwsup(s16 ins
19849 * Put a clockdomain referred to by (@inst, @cdoffs) into
19850 * hardware-supervised idle mode. No return value.
19851 */
19852 -void am33xx_cm_clkdm_enable_hwsup(s16 inst, u16 cdoffs)
19853 +void am33xx_cm_clkdm_enable_hwsup(u16 inst, u16 cdoffs)
19854 {
19855 _clktrctrl_write(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, inst, cdoffs);
19856 }
19857 @@ -191,7 +191,7 @@ void am33xx_cm_clkdm_enable_hwsup(s16 in
19858 * software-supervised idle mode, i.e., controlled manually by the
19859 * Linux OMAP clockdomain code. No return value.
19860 */
19861 -void am33xx_cm_clkdm_disable_hwsup(s16 inst, u16 cdoffs)
19862 +void am33xx_cm_clkdm_disable_hwsup(u16 inst, u16 cdoffs)
19863 {
19864 _clktrctrl_write(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, inst, cdoffs);
19865 }
19866 @@ -204,7 +204,7 @@ void am33xx_cm_clkdm_disable_hwsup(s16 i
19867 * Put a clockdomain referred to by (@inst, @cdoffs) into idle
19868 * No return value.
19869 */
19870 -void am33xx_cm_clkdm_force_sleep(s16 inst, u16 cdoffs)
19871 +void am33xx_cm_clkdm_force_sleep(u16 inst, u16 cdoffs)
19872 {
19873 _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, inst, cdoffs);
19874 }
19875 @@ -217,7 +217,7 @@ void am33xx_cm_clkdm_force_sleep(s16 ins
19876 * Take a clockdomain referred to by (@inst, @cdoffs) out of idle,
19877 * waking it up. No return value.
19878 */
19879 -void am33xx_cm_clkdm_force_wakeup(s16 inst, u16 cdoffs)
19880 +void am33xx_cm_clkdm_force_wakeup(u16 inst, u16 cdoffs)
19881 {
19882 _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, inst, cdoffs);
19883 }
19884 @@ -237,7 +237,7 @@ void am33xx_cm_clkdm_force_wakeup(s16 in
19885 * sysconfig cannot be accessed and will probably lead to an "imprecise
19886 * external abort"
19887 */
19888 -int am33xx_cm_wait_module_ready(u16 inst, s16 cdoffs, u16 clkctrl_offs)
19889 +int am33xx_cm_wait_module_ready(u16 inst, u16 cdoffs, u16 clkctrl_offs)
19890 {
19891 int i = 0;
19892
19893 @@ -258,7 +258,7 @@ int am33xx_cm_wait_module_ready(u16 inst
19894 * like reset assertion or parent clock de-activation must wait the
19895 * module to be fully disabled.
19896 */
19897 -int am33xx_cm_wait_module_idle(u16 inst, s16 cdoffs, u16 clkctrl_offs)
19898 +int am33xx_cm_wait_module_idle(u16 inst, u16 cdoffs, u16 clkctrl_offs)
19899 {
19900 int i = 0;
19901
19902 @@ -281,7 +281,7 @@ int am33xx_cm_wait_module_idle(u16 inst,
19903 *
19904 * No return value.
19905 */
19906 -void am33xx_cm_module_enable(u8 mode, u16 inst, s16 cdoffs, u16 clkctrl_offs)
19907 +void am33xx_cm_module_enable(u8 mode, u16 inst, u16 cdoffs, u16 clkctrl_offs)
19908 {
19909 u32 v;
19910
19911 @@ -299,7 +299,7 @@ void am33xx_cm_module_enable(u8 mode, u1
19912 *
19913 * No return value.
19914 */
19915 -void am33xx_cm_module_disable(u16 inst, s16 cdoffs, u16 clkctrl_offs)
19916 +void am33xx_cm_module_disable(u16 inst, u16 cdoffs, u16 clkctrl_offs)
19917 {
19918 u32 v;
19919
19920 --- a/arch/arm/mach-omap2/cm33xx.h
19921 +++ b/arch/arm/mach-omap2/cm33xx.h
19922 @@ -377,36 +377,36 @@
19923
19924
19925 #ifndef __ASSEMBLER__
19926 -extern bool am33xx_cm_is_clkdm_in_hwsup(s16 inst, u16 cdoffs);
19927 -extern void am33xx_cm_clkdm_enable_hwsup(s16 inst, u16 cdoffs);
19928 -extern void am33xx_cm_clkdm_disable_hwsup(s16 inst, u16 cdoffs);
19929 -extern void am33xx_cm_clkdm_force_sleep(s16 inst, u16 cdoffs);
19930 -extern void am33xx_cm_clkdm_force_wakeup(s16 inst, u16 cdoffs);
19931 +extern bool am33xx_cm_is_clkdm_in_hwsup(u16 inst, u16 cdoffs);
19932 +extern void am33xx_cm_clkdm_enable_hwsup(u16 inst, u16 cdoffs);
19933 +extern void am33xx_cm_clkdm_disable_hwsup(u16 inst, u16 cdoffs);
19934 +extern void am33xx_cm_clkdm_force_sleep(u16 inst, u16 cdoffs);
19935 +extern void am33xx_cm_clkdm_force_wakeup(u16 inst, u16 cdoffs);
19936
19937 -#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
19938 -extern int am33xx_cm_wait_module_idle(u16 inst, s16 cdoffs,
19939 +#ifdef CONFIG_SOC_AM33XX
19940 +extern int am33xx_cm_wait_module_idle(u16 inst, u16 cdoffs,
19941 u16 clkctrl_offs);
19942 -extern void am33xx_cm_module_enable(u8 mode, u16 inst, s16 cdoffs,
19943 +extern void am33xx_cm_module_enable(u8 mode, u16 inst, u16 cdoffs,
19944 u16 clkctrl_offs);
19945 -extern void am33xx_cm_module_disable(u16 inst, s16 cdoffs,
19946 +extern void am33xx_cm_module_disable(u16 inst, u16 cdoffs,
19947 u16 clkctrl_offs);
19948 -extern int am33xx_cm_wait_module_ready(u16 inst, s16 cdoffs,
19949 +extern int am33xx_cm_wait_module_ready(u16 inst, u16 cdoffs,
19950 u16 clkctrl_offs);
19951 #else
19952 -static inline int am33xx_cm_wait_module_idle(u16 inst, s16 cdoffs,
19953 +static inline int am33xx_cm_wait_module_idle(u16 inst, u16 cdoffs,
19954 u16 clkctrl_offs)
19955 {
19956 return 0;
19957 }
19958 -static inline void am33xx_cm_module_enable(u8 mode, u16 inst, s16 cdoffs,
19959 +static inline void am33xx_cm_module_enable(u8 mode, u16 inst, u16 cdoffs,
19960 u16 clkctrl_offs)
19961 {
19962 }
19963 -static inline void am33xx_cm_module_disable(u16 inst, s16 cdoffs,
19964 +static inline void am33xx_cm_module_disable(u16 inst, u16 cdoffs,
19965 u16 clkctrl_offs)
19966 {
19967 }
19968 -static inline int am33xx_cm_wait_module_ready(u16 inst, s16 cdoffs,
19969 +static inline int am33xx_cm_wait_module_ready(u16 inst, u16 cdoffs,
19970 u16 clkctrl_offs)
19971 {
19972 return 0;
19973 --- a/arch/arm/mach-omap2/cminst44xx.c
19974 +++ b/arch/arm/mach-omap2/cminst44xx.c
19975 @@ -80,7 +80,7 @@ void omap_cm_base_init(void)
19976 * Return the IDLEST bitfield of a CM_*_CLKCTRL register, shifted down to
19977 * bit 0.
19978 */
19979 -static u32 _clkctrl_idlest(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs)
19980 +static u32 _clkctrl_idlest(u8 part, u16 inst, u16 cdoffs, u16 clkctrl_offs)
19981 {
19982 u32 v = omap4_cminst_read_inst_reg(part, inst, clkctrl_offs);
19983 v &= OMAP4430_IDLEST_MASK;
19984 @@ -98,7 +98,7 @@ static u32 _clkctrl_idlest(u8 part, u16
19985 * Returns true if the module's CM_*_CLKCTRL.IDLEST bitfield is either
19986 * *FUNCTIONAL or *INTERFACE_IDLE; false otherwise.
19987 */
19988 -static bool _is_module_ready(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs)
19989 +static bool _is_module_ready(u8 part, u16 inst, u16 cdoffs, u16 clkctrl_offs)
19990 {
19991 u32 v;
19992
19993 @@ -111,7 +111,7 @@ static bool _is_module_ready(u8 part, u1
19994 /* Public functions */
19995
19996 /* Read a register in a CM instance */
19997 -u32 omap4_cminst_read_inst_reg(u8 part, s16 inst, u16 idx)
19998 +u32 omap4_cminst_read_inst_reg(u8 part, u16 inst, u16 idx)
19999 {
20000 BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
20001 part == OMAP4430_INVALID_PRCM_PARTITION ||
20002 @@ -120,7 +120,7 @@ u32 omap4_cminst_read_inst_reg(u8 part,
20003 }
20004
20005 /* Write into a register in a CM instance */
20006 -void omap4_cminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx)
20007 +void omap4_cminst_write_inst_reg(u32 val, u8 part, u16 inst, u16 idx)
20008 {
20009 BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
20010 part == OMAP4430_INVALID_PRCM_PARTITION ||
20011 @@ -152,7 +152,7 @@ u32 omap4_cminst_clear_inst_reg_bits(u32
20012 return omap4_cminst_rmw_inst_reg_bits(bits, 0x0, part, inst, idx);
20013 }
20014
20015 -u32 omap4_cminst_read_inst_reg_bits(u8 part, u16 inst, s16 idx, u32 mask)
20016 +u32 omap4_cminst_read_inst_reg_bits(u8 part, u16 inst, u16 idx, u32 mask)
20017 {
20018 u32 v;
20019
20020 @@ -177,7 +177,7 @@ u32 omap4_cminst_read_inst_reg_bits(u8 p
20021 * @c must be the unshifted value for CLKTRCTRL - i.e., this function
20022 * will handle the shift itself.
20023 */
20024 -static void _clktrctrl_write(u8 c, u8 part, s16 inst, u16 cdoffs)
20025 +static void _clktrctrl_write(u8 c, u8 part, u16 inst, u16 cdoffs)
20026 {
20027 u32 v;
20028
20029 @@ -196,7 +196,7 @@ static void _clktrctrl_write(u8 c, u8 pa
20030 * Returns true if the clockdomain referred to by (@part, @inst, @cdoffs)
20031 * is in hardware-supervised idle mode, or 0 otherwise.
20032 */
20033 -bool omap4_cminst_is_clkdm_in_hwsup(u8 part, s16 inst, u16 cdoffs)
20034 +bool omap4_cminst_is_clkdm_in_hwsup(u8 part, u16 inst, u16 cdoffs)
20035 {
20036 u32 v;
20037
20038 @@ -216,7 +216,7 @@ bool omap4_cminst_is_clkdm_in_hwsup(u8 p
20039 * Put a clockdomain referred to by (@part, @inst, @cdoffs) into
20040 * hardware-supervised idle mode. No return value.
20041 */
20042 -void omap4_cminst_clkdm_enable_hwsup(u8 part, s16 inst, u16 cdoffs)
20043 +void omap4_cminst_clkdm_enable_hwsup(u8 part, u16 inst, u16 cdoffs)
20044 {
20045 _clktrctrl_write(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, part, inst, cdoffs);
20046 }
20047 @@ -231,7 +231,7 @@ void omap4_cminst_clkdm_enable_hwsup(u8
20048 * software-supervised idle mode, i.e., controlled manually by the
20049 * Linux OMAP clockdomain code. No return value.
20050 */
20051 -void omap4_cminst_clkdm_disable_hwsup(u8 part, s16 inst, u16 cdoffs)
20052 +void omap4_cminst_clkdm_disable_hwsup(u8 part, u16 inst, u16 cdoffs)
20053 {
20054 _clktrctrl_write(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, part, inst, cdoffs);
20055 }
20056 @@ -245,7 +245,7 @@ void omap4_cminst_clkdm_disable_hwsup(u8
20057 * Take a clockdomain referred to by (@part, @inst, @cdoffs) out of idle,
20058 * waking it up. No return value.
20059 */
20060 -void omap4_cminst_clkdm_force_wakeup(u8 part, s16 inst, u16 cdoffs)
20061 +void omap4_cminst_clkdm_force_wakeup(u8 part, u16 inst, u16 cdoffs)
20062 {
20063 _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, part, inst, cdoffs);
20064 }
20065 @@ -266,7 +266,7 @@ void omap4_cminst_clkdm_force_wakeup(u8
20066 * sysconfig cannot be accessed and will probably lead to an "imprecise
20067 * external abort"
20068 */
20069 -int omap4_cminst_wait_module_ready(u8 part, u16 inst, s16 cdoffs,
20070 +int omap4_cminst_wait_module_ready(u8 part, u16 inst, u16 cdoffs,
20071 u16 clkctrl_offs)
20072 {
20073 int i = 0;
20074 @@ -292,7 +292,8 @@ int omap4_cminst_wait_module_ready(u8 pa
20075 * like reset assertion or parent clock de-activation must wait the
20076 * module to be fully disabled.
20077 */
20078 -int omap4_cminst_wait_module_idle(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs)
20079 +int omap4_cminst_wait_module_idle(u8 part, u16 inst,
20080 + u16 cdoffs, u16 clkctrl_offs)
20081 {
20082 int i = 0;
20083
20084 @@ -316,7 +317,7 @@ int omap4_cminst_wait_module_idle(u8 par
20085 *
20086 * No return value.
20087 */
20088 -void omap4_cminst_module_enable(u8 mode, u8 part, u16 inst, s16 cdoffs,
20089 +void omap4_cminst_module_enable(u8 mode, u8 part, u16 inst, u16 cdoffs,
20090 u16 clkctrl_offs)
20091 {
20092 u32 v;
20093 @@ -336,7 +337,7 @@ void omap4_cminst_module_enable(u8 mode,
20094 *
20095 * No return value.
20096 */
20097 -void omap4_cminst_module_disable(u8 part, u16 inst, s16 cdoffs,
20098 +void omap4_cminst_module_disable(u8 part, u16 inst, u16 cdoffs,
20099 u16 clkctrl_offs)
20100 {
20101 u32 v;
20102 @@ -479,6 +480,15 @@ struct clkdm_ops omap4_clkdm_operations
20103 .clkdm_sleep = omap4_clkdm_sleep,
20104 .clkdm_wakeup = omap4_clkdm_wakeup,
20105 .clkdm_allow_idle = omap4_clkdm_allow_idle,
20106 + .clkdm_deny_idle = omap4_clkdm_deny_idle,
20107 + .clkdm_clk_enable = omap4_clkdm_clk_enable,
20108 + .clkdm_clk_disable = omap4_clkdm_clk_disable,
20109 +};
20110 +
20111 +struct clkdm_ops am43xx_clkdm_operations = {
20112 + .clkdm_sleep = omap4_clkdm_sleep,
20113 + .clkdm_wakeup = omap4_clkdm_wakeup,
20114 + .clkdm_allow_idle = omap4_clkdm_allow_idle,
20115 .clkdm_deny_idle = omap4_clkdm_deny_idle,
20116 .clkdm_clk_enable = omap4_clkdm_clk_enable,
20117 .clkdm_clk_disable = omap4_clkdm_clk_disable,
20118 --- a/arch/arm/mach-omap2/cminst44xx.h
20119 +++ b/arch/arm/mach-omap2/cminst44xx.h
20120 @@ -11,31 +11,32 @@
20121 #ifndef __ARCH_ASM_MACH_OMAP2_CMINST44XX_H
20122 #define __ARCH_ASM_MACH_OMAP2_CMINST44XX_H
20123
20124 -extern bool omap4_cminst_is_clkdm_in_hwsup(u8 part, s16 inst, u16 cdoffs);
20125 -extern void omap4_cminst_clkdm_enable_hwsup(u8 part, s16 inst, u16 cdoffs);
20126 -extern void omap4_cminst_clkdm_disable_hwsup(u8 part, s16 inst, u16 cdoffs);
20127 -extern void omap4_cminst_clkdm_force_sleep(u8 part, s16 inst, u16 cdoffs);
20128 -extern void omap4_cminst_clkdm_force_wakeup(u8 part, s16 inst, u16 cdoffs);
20129 -extern int omap4_cminst_wait_module_ready(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs);
20130 -extern int omap4_cminst_wait_module_idle(u8 part, u16 inst, s16 cdoffs,
20131 +extern bool omap4_cminst_is_clkdm_in_hwsup(u8 part, u16 inst, u16 cdoffs);
20132 +extern void omap4_cminst_clkdm_enable_hwsup(u8 part, u16 inst, u16 cdoffs);
20133 +extern void omap4_cminst_clkdm_disable_hwsup(u8 part, u16 inst, u16 cdoffs);
20134 +extern void omap4_cminst_clkdm_force_sleep(u8 part, u16 inst, u16 cdoffs);
20135 +extern void omap4_cminst_clkdm_force_wakeup(u8 part, u16 inst, u16 cdoffs);
20136 +extern int omap4_cminst_wait_module_ready(u8 part, u16 inst,
20137 + u16 cdoffs, u16 clkctrl_offs);
20138 +extern int omap4_cminst_wait_module_idle(u8 part, u16 inst, u16 cdoffs,
20139 u16 clkctrl_offs);
20140 -extern void omap4_cminst_module_enable(u8 mode, u8 part, u16 inst, s16 cdoffs,
20141 +extern void omap4_cminst_module_enable(u8 mode, u8 part, u16 inst, u16 cdoffs,
20142 u16 clkctrl_offs);
20143 -extern void omap4_cminst_module_disable(u8 part, u16 inst, s16 cdoffs,
20144 +extern void omap4_cminst_module_disable(u8 part, u16 inst, u16 cdoffs,
20145 u16 clkctrl_offs);
20146 /*
20147 * In an ideal world, we would not export these low-level functions,
20148 * but this will probably take some time to fix properly
20149 */
20150 -extern u32 omap4_cminst_read_inst_reg(u8 part, s16 inst, u16 idx);
20151 -extern void omap4_cminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx);
20152 +extern u32 omap4_cminst_read_inst_reg(u8 part, u16 inst, u16 idx);
20153 +extern void omap4_cminst_write_inst_reg(u32 val, u8 part, u16 inst, u16 idx);
20154 extern u32 omap4_cminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part,
20155 s16 inst, s16 idx);
20156 extern u32 omap4_cminst_set_inst_reg_bits(u32 bits, u8 part, s16 inst,
20157 s16 idx);
20158 extern u32 omap4_cminst_clear_inst_reg_bits(u32 bits, u8 part, s16 inst,
20159 s16 idx);
20160 -extern u32 omap4_cminst_read_inst_reg_bits(u8 part, u16 inst, s16 idx,
20161 +extern u32 omap4_cminst_read_inst_reg_bits(u8 part, u16 inst, u16 idx,
20162 u32 mask);
20163
20164 extern void omap_cm_base_init(void);
20165 --- a/arch/arm/mach-omap2/common.c
20166 +++ b/arch/arm/mach-omap2/common.c
20167 @@ -15,10 +15,14 @@
20168 #include <linux/kernel.h>
20169 #include <linux/init.h>
20170 #include <linux/platform_data/dsp-omap.h>
20171 +#include <asm/memblock.h>
20172 +#include <asm/mach/map.h>
20173
20174 #include "common.h"
20175 #include "omap-secure.h"
20176
20177 +#define AM33XX_DRAM_SYNC_VA 0xfe600000
20178 +
20179 /*
20180 * Stub function for OMAP2 so that common files
20181 * continue to build when custom builds are used
20182 @@ -34,3 +38,31 @@ void __init omap_reserve(void)
20183 omap_secure_ram_reserve_memblock();
20184 omap_barrier_reserve_memblock();
20185 }
20186 +
20187 +static phys_addr_t am33xx_paddr;
20188 +static u32 am33xx_size;
20189 +
20190 +/* Steal one page physical memory for uncached read DeepSleep */
20191 +void __init am33xx_reserve(void)
20192 +{
20193 + am33xx_size = ALIGN(PAGE_SIZE, SZ_1M);
20194 + am33xx_paddr = arm_memblock_steal(am33xx_size, SZ_1M);
20195 +
20196 + omap_reserve();
20197 +}
20198 +
20199 +void __iomem *am33xx_dram_sync;
20200 +
20201 +void __init am33xx_dram_sync_init(void)
20202 +{
20203 + struct map_desc dram_io_desc[1];
20204 +
20205 + dram_io_desc[0].virtual = AM33XX_DRAM_SYNC_VA;
20206 + dram_io_desc[0].pfn = __phys_to_pfn(am33xx_paddr);
20207 + dram_io_desc[0].length = am33xx_size;
20208 + dram_io_desc[0].type = MT_MEMORY_SO;
20209 +
20210 + iotable_init(dram_io_desc, ARRAY_SIZE(dram_io_desc));
20211 +
20212 + am33xx_dram_sync = (void __iomem *) dram_io_desc[0].virtual;
20213 +}
20214 --- a/arch/arm/mach-omap2/common.h
20215 +++ b/arch/arm/mach-omap2/common.h
20216 @@ -60,7 +60,7 @@ static inline int omap3_pm_init(void)
20217 }
20218 #endif
20219
20220 -#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP4)
20221 +#if defined(CONFIG_PM) && (defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX))
20222 int omap4_pm_init(void);
20223 #else
20224 static inline int omap4_pm_init(void)
20225 @@ -69,6 +69,15 @@ static inline int omap4_pm_init(void)
20226 }
20227 #endif
20228
20229 +#if defined(CONFIG_PM) && defined(CONFIG_SOC_AM33XX)
20230 +int am33xx_pm_init(void);
20231 +#else
20232 +static inline int am33xx_pm_init(void)
20233 +{
20234 + return 0;
20235 +}
20236 +#endif
20237 +
20238 #ifdef CONFIG_OMAP_MUX
20239 int omap_mux_late_init(void);
20240 #else
20241 @@ -107,10 +116,14 @@ void omap2430_init_late(void);
20242 void omap3430_init_late(void);
20243 void omap35xx_init_late(void);
20244 void omap3630_init_late(void);
20245 +void am33xx_init_late(void);
20246 void am35xx_init_late(void);
20247 void ti81xx_init_late(void);
20248 +void am33xx_init_late(void);
20249 +void omap5_init_late(void);
20250 int omap2_common_pm_late_init(void);
20251 void dra7xx_init_early(void);
20252 +void dra7xx_init_late(void);
20253
20254 #ifdef CONFIG_SOC_BUS
20255 void omap_soc_device_init(void);
20256 @@ -136,6 +149,14 @@ static inline void am33xx_restart(enum r
20257 }
20258 #endif
20259
20260 +#ifdef CONFIG_SOC_AM43XX
20261 +void am43xx_restart(enum reboot_mode mode, const char *cmd);
20262 +#else
20263 +static inline void am43xx_restart(enum reboot_mode mode, const char *cmd)
20264 +{
20265 +}
20266 +#endif
20267 +
20268 #ifdef CONFIG_ARCH_OMAP3
20269 void omap3xxx_restart(enum reboot_mode mode, const char *cmd);
20270 #else
20271 @@ -152,6 +173,14 @@ static inline void omap44xx_restart(enum
20272 }
20273 #endif
20274
20275 +#if defined(CONFIG_SUSPEND)
20276 +void omap2_common_suspend_init(void);
20277 +#else
20278 +inline void omap2_common_suspend_init(void);
20279 +{
20280 +}
20281 +#endif
20282 +
20283 /* This gets called from mach-omap2/io.c, do not call this */
20284 void __init omap2_set_globals_tap(u32 class, void __iomem *tap);
20285
20286 @@ -165,7 +194,6 @@ void __init ti81xx_map_io(void);
20287
20288 /* omap_barriers_init() is OMAP4 only */
20289 void omap_barriers_init(void);
20290 -
20291 /**
20292 * omap_test_timeout - busy-loop, testing a condition
20293 * @cond: condition to test until it evaluates to true
20294 @@ -259,6 +287,8 @@ extern int omap4_enter_lowpower(unsigned
20295 extern int omap4_finish_suspend(unsigned long cpu_state);
20296 extern void omap4_cpu_resume(void);
20297 extern int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state);
20298 +extern int omap5_finish_suspend(unsigned long cpu_state);
20299 +extern void omap5_cpu_resume(void);
20300 #else
20301 static inline int omap4_enter_lowpower(unsigned int cpu,
20302 unsigned int power_state)
20303 @@ -286,6 +316,14 @@ static inline int omap4_finish_suspend(u
20304 static inline void omap4_cpu_resume(void)
20305 {}
20306
20307 +static inline int omap5_finish_suspend(unsigned long cpu_state)
20308 +{
20309 + return 0;
20310 +}
20311 +
20312 +static inline void omap5_cpu_resume(void)
20313 +{}
20314 +
20315 #endif
20316
20317 struct omap_sdrc_params;
20318 @@ -295,11 +333,17 @@ struct omap2_hsmmc_info;
20319 extern int omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers);
20320 extern void omap_reserve(void);
20321
20322 +extern void am33xx_reserve(void);
20323 +extern void am33xx_dram_sync_init(void);
20324 +extern void __iomem *am33xx_dram_sync;
20325 +
20326 struct omap_hwmod;
20327 extern int omap_dss_reset(struct omap_hwmod *);
20328
20329 /* SoC specific clock initializer */
20330 extern int (*omap_clk_init)(void);
20331
20332 +int __init omapdss_init_of(void);
20333 +
20334 #endif /* __ASSEMBLER__ */
20335 #endif /* __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H */
20336 --- a/arch/arm/mach-omap2/devices.c
20337 +++ b/arch/arm/mach-omap2/devices.c
20338 @@ -37,6 +37,7 @@
20339 #include "mux.h"
20340 #include "control.h"
20341 #include "devices.h"
20342 +#include "display.h"
20343
20344 #define L3_MODULES_MAX_LEN 12
20345 #define L3_MODULES 3
20346 @@ -466,13 +467,13 @@ static struct platform_device omap_vout_
20347 .resource = &omap_vout_resource[0],
20348 .id = -1,
20349 };
20350 -static void omap_init_vout(void)
20351 +
20352 +int __init omap_init_vout(void)
20353 {
20354 - if (platform_device_register(&omap_vout_device) < 0)
20355 - printk(KERN_ERR "Unable to register OMAP-VOUT device\n");
20356 + return platform_device_register(&omap_vout_device);
20357 }
20358 #else
20359 -static inline void omap_init_vout(void) {}
20360 +int __init omap_init_vout(void) { return 0; }
20361 #endif
20362
20363 #if IS_ENABLED(CONFIG_WL12XX)
20364 @@ -524,9 +525,9 @@ static int __init omap2_init_devices(voi
20365 omap_init_audio();
20366 omap_init_camera();
20367 omap_init_hdmi_audio();
20368 - omap_init_mbox();
20369 /* If dtb is there, the devices will be created dynamically */
20370 if (!of_have_populated_dt()) {
20371 + omap_init_mbox();
20372 omap_init_mcspi();
20373 omap_init_sham();
20374 omap_init_aes();
20375 @@ -536,7 +537,6 @@ static int __init omap2_init_devices(voi
20376 omap_init_wl12xx_of();
20377 }
20378 omap_init_sti();
20379 - omap_init_vout();
20380
20381 return 0;
20382 }
20383 --- a/arch/arm/mach-omap2/display.c
20384 +++ b/arch/arm/mach-omap2/display.c
20385 @@ -23,6 +23,8 @@
20386 #include <linux/clk.h>
20387 #include <linux/err.h>
20388 #include <linux/delay.h>
20389 +#include <linux/of.h>
20390 +#include <linux/of_platform.h>
20391
20392 #include <video/omapdss.h>
20393 #include "omap_hwmod.h"
20394 @@ -316,6 +318,10 @@ static enum omapdss_version __init omap_
20395 return OMAPDSS_VER_OMAP4;
20396 else if (soc_is_omap54xx())
20397 return OMAPDSS_VER_OMAP5;
20398 + else if (soc_is_dra7xx())
20399 + return OMAPDSS_VER_DRA7xx;
20400 + else if (soc_is_am43xx())
20401 + return OMAPDSS_VER_AM43xx;
20402 else
20403 return OMAPDSS_VER_UNKNOWN;
20404 }
20405 @@ -416,6 +422,34 @@ int __init omap_display_init(struct omap
20406 }
20407 }
20408
20409 + /* create DRM device */
20410 + r = omap_init_drm();
20411 + if (r < 0) {
20412 + pr_err("Unable to register omapdrm device\n");
20413 + return r;
20414 + }
20415 +
20416 + /* create vrfb device */
20417 + r = omap_init_vrfb();
20418 + if (r < 0) {
20419 + pr_err("Unable to register omapvrfb device\n");
20420 + return r;
20421 + }
20422 +
20423 + /* create FB device */
20424 + r = omap_init_fb();
20425 + if (r < 0) {
20426 + pr_err("Unable to register omapfb device\n");
20427 + return r;
20428 + }
20429 +
20430 + /* create V4L2 display device */
20431 + r = omap_init_vout();
20432 + if (r < 0) {
20433 + pr_err("Unable to register omap_vout device\n");
20434 + return r;
20435 + }
20436 +
20437 return 0;
20438 }
20439
20440 @@ -564,3 +598,63 @@ int omap_dss_reset(struct omap_hwmod *oh
20441
20442 return r;
20443 }
20444 +
20445 +int __init omapdss_init_of(void)
20446 +{
20447 + int r;
20448 + enum omapdss_version ver;
20449 +
20450 + static struct omap_dss_board_info board_data = {
20451 + .dsi_enable_pads = omap_dsi_enable_pads,
20452 + .dsi_disable_pads = omap_dsi_disable_pads,
20453 + .get_context_loss_count = omap_pm_get_dev_context_loss_count,
20454 + .set_min_bus_tput = omap_dss_set_min_bus_tput,
20455 + };
20456 +
20457 + ver = omap_display_get_version();
20458 +
20459 + if (ver == OMAPDSS_VER_UNKNOWN) {
20460 + pr_err("DSS not supported on this SoC\n");
20461 + return -ENODEV;
20462 + }
20463 +
20464 + board_data.version = ver;
20465 +
20466 + omap_display_device.dev.platform_data = &board_data;
20467 +
20468 + r = platform_device_register(&omap_display_device);
20469 + if (r < 0) {
20470 + pr_err("Unable to register omapdss device\n");
20471 + return r;
20472 + }
20473 +
20474 + /* create DRM device */
20475 + r = omap_init_drm();
20476 + if (r < 0) {
20477 + pr_err("Unable to register omapdrm device\n");
20478 + return r;
20479 + }
20480 +
20481 + /* create vrfb device */
20482 + r = omap_init_vrfb();
20483 + if (r < 0) {
20484 + pr_err("Unable to register omapvrfb device\n");
20485 + return r;
20486 + }
20487 +
20488 + /* create FB device */
20489 + r = omap_init_fb();
20490 + if (r < 0) {
20491 + pr_err("Unable to register omapfb device\n");
20492 + return r;
20493 + }
20494 +
20495 + /* create V4L2 display device */
20496 + r = omap_init_vout();
20497 + if (r < 0) {
20498 + pr_err("Unable to register omap_vout device\n");
20499 + return r;
20500 + }
20501 +
20502 + return 0;
20503 +}
20504 --- a/arch/arm/mach-omap2/display.h
20505 +++ b/arch/arm/mach-omap2/display.h
20506 @@ -26,4 +26,8 @@ struct omap_dss_dispc_dev_attr {
20507 bool has_framedonetv_irq;
20508 };
20509
20510 +int omap_init_drm(void);
20511 +int omap_init_vrfb(void);
20512 +int omap_init_fb(void);
20513 +int omap_init_vout(void);
20514 #endif
20515 --- a/arch/arm/mach-omap2/drm.c
20516 +++ b/arch/arm/mach-omap2/drm.c
20517 @@ -26,10 +26,9 @@
20518 #include <linux/platform_data/omap_drm.h>
20519
20520 #include "soc.h"
20521 -#include "omap_device.h"
20522 -#include "omap_hwmod.h"
20523 +#include "display.h"
20524
20525 -#if defined(CONFIG_DRM_OMAP) || (CONFIG_DRM_OMAP_MODULE)
20526 +#if defined(CONFIG_DRM_OMAP) || defined(CONFIG_DRM_OMAP_MODULE)
20527
20528 static struct omap_drm_platform_data platform_data;
20529
20530 @@ -42,26 +41,13 @@ static struct platform_device omap_drm_d
20531 .id = 0,
20532 };
20533
20534 -static int __init omap_init_drm(void)
20535 +int __init omap_init_drm(void)
20536 {
20537 - struct omap_hwmod *oh = NULL;
20538 - struct platform_device *pdev;
20539 -
20540 - /* lookup and populate the DMM information, if present - OMAP4+ */
20541 - oh = omap_hwmod_lookup("dmm");
20542 -
20543 - if (oh) {
20544 - pdev = omap_device_build(oh->name, -1, oh, NULL, 0);
20545 - WARN(IS_ERR(pdev), "Could not build omap_device for %s\n",
20546 - oh->name);
20547 - }
20548 -
20549 platform_data.omaprev = GET_OMAP_TYPE;
20550
20551 return platform_device_register(&omap_drm_device);
20552
20553 }
20554 -
20555 -omap_arch_initcall(omap_init_drm);
20556 -
20557 +#else
20558 +int __init omap_init_drm(void) { return 0; }
20559 #endif
20560 --- a/arch/arm/mach-omap2/dss-common.c
20561 +++ /dev/null
20562 @@ -1,215 +0,0 @@
20563 -/*
20564 - * Copyright (C) 2012 Texas Instruments, Inc..
20565 - * Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
20566 - *
20567 - * This program is free software; you can redistribute it and/or
20568 - * modify it under the terms of the GNU General Public License
20569 - * version 2 as published by the Free Software Foundation.
20570 - *
20571 - * This program is distributed in the hope that it will be useful, but
20572 - * WITHOUT ANY WARRANTY; without even the implied warranty of
20573 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20574 - * General Public License for more details.
20575 - *
20576 - * You should have received a copy of the GNU General Public License
20577 - * along with this program; if not, write to the Free Software
20578 - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20579 - * 02110-1301 USA
20580 - *
20581 - */
20582 -
20583 -/*
20584 - * NOTE: this is a transitional file to help with DT adaptation.
20585 - * This file will be removed when DSS supports DT.
20586 - */
20587 -
20588 -#include <linux/kernel.h>
20589 -#include <linux/gpio.h>
20590 -#include <linux/platform_device.h>
20591 -
20592 -#include <video/omapdss.h>
20593 -#include <video/omap-panel-data.h>
20594 -
20595 -#include "soc.h"
20596 -#include "dss-common.h"
20597 -#include "mux.h"
20598 -
20599 -#define HDMI_GPIO_CT_CP_HPD 60 /* HPD mode enable/disable */
20600 -#define HDMI_GPIO_LS_OE 41 /* Level shifter for HDMI */
20601 -#define HDMI_GPIO_HPD 63 /* Hotplug detect */
20602 -
20603 -#define PANDA_DVI_TFP410_POWER_DOWN_GPIO 0
20604 -
20605 -/* DVI Connector */
20606 -static struct connector_dvi_platform_data omap4_panda_dvi_connector_pdata = {
20607 - .name = "dvi",
20608 - .source = "tfp410.0",
20609 - .i2c_bus_num = 2,
20610 -};
20611 -
20612 -static struct platform_device omap4_panda_dvi_connector_device = {
20613 - .name = "connector-dvi",
20614 - .id = 0,
20615 - .dev.platform_data = &omap4_panda_dvi_connector_pdata,
20616 -};
20617 -
20618 -/* TFP410 DPI-to-DVI chip */
20619 -static struct encoder_tfp410_platform_data omap4_panda_tfp410_pdata = {
20620 - .name = "tfp410.0",
20621 - .source = "dpi.0",
20622 - .data_lines = 24,
20623 - .power_down_gpio = PANDA_DVI_TFP410_POWER_DOWN_GPIO,
20624 -};
20625 -
20626 -static struct platform_device omap4_panda_tfp410_device = {
20627 - .name = "tfp410",
20628 - .id = 0,
20629 - .dev.platform_data = &omap4_panda_tfp410_pdata,
20630 -};
20631 -
20632 -/* HDMI Connector */
20633 -static struct connector_hdmi_platform_data omap4_panda_hdmi_connector_pdata = {
20634 - .name = "hdmi",
20635 - .source = "tpd12s015.0",
20636 -};
20637 -
20638 -static struct platform_device omap4_panda_hdmi_connector_device = {
20639 - .name = "connector-hdmi",
20640 - .id = 0,
20641 - .dev.platform_data = &omap4_panda_hdmi_connector_pdata,
20642 -};
20643 -
20644 -/* TPD12S015 HDMI ESD protection & level shifter chip */
20645 -static struct encoder_tpd12s015_platform_data omap4_panda_tpd_pdata = {
20646 - .name = "tpd12s015.0",
20647 - .source = "hdmi.0",
20648 -
20649 - .ct_cp_hpd_gpio = HDMI_GPIO_CT_CP_HPD,
20650 - .ls_oe_gpio = HDMI_GPIO_LS_OE,
20651 - .hpd_gpio = HDMI_GPIO_HPD,
20652 -};
20653 -
20654 -static struct platform_device omap4_panda_tpd_device = {
20655 - .name = "tpd12s015",
20656 - .id = 0,
20657 - .dev.platform_data = &omap4_panda_tpd_pdata,
20658 -};
20659 -
20660 -static struct omap_dss_board_info omap4_panda_dss_data = {
20661 - .default_display_name = "dvi",
20662 -};
20663 -
20664 -void __init omap4_panda_display_init_of(void)
20665 -{
20666 - omap_display_init(&omap4_panda_dss_data);
20667 -
20668 - platform_device_register(&omap4_panda_tfp410_device);
20669 - platform_device_register(&omap4_panda_dvi_connector_device);
20670 -
20671 - platform_device_register(&omap4_panda_tpd_device);
20672 - platform_device_register(&omap4_panda_hdmi_connector_device);
20673 -}
20674 -
20675 -
20676 -/* OMAP4 Blaze display data */
20677 -
20678 -#define DISPLAY_SEL_GPIO 59 /* LCD2/PicoDLP switch */
20679 -#define DLP_POWER_ON_GPIO 40
20680 -
20681 -static struct panel_dsicm_platform_data dsi1_panel = {
20682 - .name = "lcd",
20683 - .source = "dsi.0",
20684 - .reset_gpio = 102,
20685 - .use_ext_te = false,
20686 - .ext_te_gpio = 101,
20687 - .pin_config = {
20688 - .num_pins = 6,
20689 - .pins = { 0, 1, 2, 3, 4, 5 },
20690 - },
20691 -};
20692 -
20693 -static struct platform_device sdp4430_lcd_device = {
20694 - .name = "panel-dsi-cm",
20695 - .id = 0,
20696 - .dev.platform_data = &dsi1_panel,
20697 -};
20698 -
20699 -static struct panel_dsicm_platform_data dsi2_panel = {
20700 - .name = "lcd2",
20701 - .source = "dsi.1",
20702 - .reset_gpio = 104,
20703 - .use_ext_te = false,
20704 - .ext_te_gpio = 103,
20705 - .pin_config = {
20706 - .num_pins = 6,
20707 - .pins = { 0, 1, 2, 3, 4, 5 },
20708 - },
20709 -};
20710 -
20711 -static struct platform_device sdp4430_lcd2_device = {
20712 - .name = "panel-dsi-cm",
20713 - .id = 1,
20714 - .dev.platform_data = &dsi2_panel,
20715 -};
20716 -
20717 -/* HDMI Connector */
20718 -static struct connector_hdmi_platform_data sdp4430_hdmi_connector_pdata = {
20719 - .name = "hdmi",
20720 - .source = "tpd12s015.0",
20721 -};
20722 -
20723 -static struct platform_device sdp4430_hdmi_connector_device = {
20724 - .name = "connector-hdmi",
20725 - .id = 0,
20726 - .dev.platform_data = &sdp4430_hdmi_connector_pdata,
20727 -};
20728 -
20729 -/* TPD12S015 HDMI ESD protection & level shifter chip */
20730 -static struct encoder_tpd12s015_platform_data sdp4430_tpd_pdata = {
20731 - .name = "tpd12s015.0",
20732 - .source = "hdmi.0",
20733 -
20734 - .ct_cp_hpd_gpio = HDMI_GPIO_CT_CP_HPD,
20735 - .ls_oe_gpio = HDMI_GPIO_LS_OE,
20736 - .hpd_gpio = HDMI_GPIO_HPD,
20737 -};
20738 -
20739 -static struct platform_device sdp4430_tpd_device = {
20740 - .name = "tpd12s015",
20741 - .id = 0,
20742 - .dev.platform_data = &sdp4430_tpd_pdata,
20743 -};
20744 -
20745 -
20746 -static struct omap_dss_board_info sdp4430_dss_data = {
20747 - .default_display_name = "lcd",
20748 -};
20749 -
20750 -/*
20751 - * we select LCD2 by default (instead of Pico DLP) by setting DISPLAY_SEL_GPIO.
20752 - * Setting DLP_POWER_ON gpio enables the VDLP_2V5 VDLP_1V8 and VDLP_1V0 rails
20753 - * used by picodlp on the 4430sdp platform. Keep this gpio disabled as LCD2 is
20754 - * selected by default
20755 - */
20756 -void __init omap_4430sdp_display_init_of(void)
20757 -{
20758 - int r;
20759 -
20760 - r = gpio_request_one(DISPLAY_SEL_GPIO, GPIOF_OUT_INIT_HIGH,
20761 - "display_sel");
20762 - if (r)
20763 - pr_err("%s: Could not get display_sel GPIO\n", __func__);
20764 -
20765 - r = gpio_request_one(DLP_POWER_ON_GPIO, GPIOF_OUT_INIT_LOW,
20766 - "DLP POWER ON");
20767 - if (r)
20768 - pr_err("%s: Could not get DLP POWER ON GPIO\n", __func__);
20769 -
20770 - omap_display_init(&sdp4430_dss_data);
20771 -
20772 - platform_device_register(&sdp4430_lcd_device);
20773 - platform_device_register(&sdp4430_lcd2_device);
20774 -
20775 - platform_device_register(&sdp4430_tpd_device);
20776 - platform_device_register(&sdp4430_hdmi_connector_device);
20777 -}
20778 --- a/arch/arm/mach-omap2/dss-common.h
20779 +++ /dev/null
20780 @@ -1,12 +0,0 @@
20781 -#ifndef __OMAP_DSS_COMMON__
20782 -#define __OMAP_DSS_COMMON__
20783 -
20784 -/*
20785 - * NOTE: this is a transitional file to help with DT adaptation.
20786 - * This file will be removed when DSS supports DT.
20787 - */
20788 -
20789 -void __init omap4_panda_display_init_of(void);
20790 -void __init omap_4430sdp_display_init_of(void);
20791 -
20792 -#endif
20793 --- a/arch/arm/mach-omap2/fb.c
20794 +++ b/arch/arm/mach-omap2/fb.c
20795 @@ -32,6 +32,7 @@
20796 #include <asm/mach/map.h>
20797
20798 #include "soc.h"
20799 +#include "display.h"
20800
20801 #ifdef CONFIG_OMAP2_VRFB
20802
20803 @@ -64,7 +65,7 @@ static const struct resource omap3_vrfb_
20804 DEFINE_RES_MEM_NAMED(0xfc000000u, 0x4000000, "vrfb-area-11"),
20805 };
20806
20807 -static int __init omap_init_vrfb(void)
20808 +int __init omap_init_vrfb(void)
20809 {
20810 struct platform_device *pdev;
20811 const struct resource *res;
20812 @@ -85,8 +86,8 @@ static int __init omap_init_vrfb(void)
20813
20814 return PTR_RET(pdev);
20815 }
20816 -
20817 -omap_arch_initcall(omap_init_vrfb);
20818 +#else
20819 +int __init omap_init_vrfb(void) { return 0; }
20820 #endif
20821
20822 #if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE)
20823 @@ -105,11 +106,10 @@ static struct platform_device omap_fb_de
20824 .num_resources = 0,
20825 };
20826
20827 -static int __init omap_init_fb(void)
20828 +int __init omap_init_fb(void)
20829 {
20830 return platform_device_register(&omap_fb_device);
20831 }
20832 -
20833 -omap_arch_initcall(omap_init_fb);
20834 -
20835 +#else
20836 +int __init omap_init_fb(void) { return 0; }
20837 #endif
20838 --- a/arch/arm/mach-omap2/gpmc.c
20839 +++ b/arch/arm/mach-omap2/gpmc.c
20840 @@ -68,6 +68,9 @@
20841 #define GPMC_ECC_BCH_RESULT_1 0x244 /* not available on OMAP2 */
20842 #define GPMC_ECC_BCH_RESULT_2 0x248 /* not available on OMAP2 */
20843 #define GPMC_ECC_BCH_RESULT_3 0x24c /* not available on OMAP2 */
20844 +#define GPMC_ECC_BCH_RESULT_4 0x300 /* not available on OMAP2 */
20845 +#define GPMC_ECC_BCH_RESULT_5 0x304 /* not available on OMAP2 */
20846 +#define GPMC_ECC_BCH_RESULT_6 0x308 /* not available on OMAP2 */
20847
20848 /* GPMC ECC control settings */
20849 #define GPMC_ECC_CTRL_ECCCLEAR 0x100
20850 @@ -659,13 +662,19 @@ void gpmc_update_nand_reg(struct gpmc_na
20851
20852 for (i = 0; i < GPMC_BCH_NUM_REMAINDER; i++) {
20853 reg->gpmc_bch_result0[i] = gpmc_base + GPMC_ECC_BCH_RESULT_0 +
20854 - GPMC_BCH_SIZE * i;
20855 + (GPMC_BCH_SIZE * i);
20856 reg->gpmc_bch_result1[i] = gpmc_base + GPMC_ECC_BCH_RESULT_1 +
20857 - GPMC_BCH_SIZE * i;
20858 + (GPMC_BCH_SIZE * i);
20859 reg->gpmc_bch_result2[i] = gpmc_base + GPMC_ECC_BCH_RESULT_2 +
20860 - GPMC_BCH_SIZE * i;
20861 + (GPMC_BCH_SIZE * i);
20862 reg->gpmc_bch_result3[i] = gpmc_base + GPMC_ECC_BCH_RESULT_3 +
20863 - GPMC_BCH_SIZE * i;
20864 + (GPMC_BCH_SIZE * i);
20865 + reg->gpmc_bch_result4[i] = gpmc_base + GPMC_ECC_BCH_RESULT_4 +
20866 + (GPMC_BCH_SIZE * i);
20867 + reg->gpmc_bch_result5[i] = gpmc_base + GPMC_ECC_BCH_RESULT_5 +
20868 + (GPMC_BCH_SIZE * i);
20869 + reg->gpmc_bch_result6[i] = gpmc_base + GPMC_ECC_BCH_RESULT_6 +
20870 + (GPMC_BCH_SIZE * i);
20871 }
20872 }
20873
20874 @@ -1340,15 +1349,6 @@ static void __maybe_unused gpmc_read_tim
20875 }
20876
20877 #ifdef CONFIG_MTD_NAND
20878 -
20879 -static const char * const nand_ecc_opts[] = {
20880 - [OMAP_ECC_HAMMING_CODE_DEFAULT] = "sw",
20881 - [OMAP_ECC_HAMMING_CODE_HW] = "hw",
20882 - [OMAP_ECC_HAMMING_CODE_HW_ROMCODE] = "hw-romcode",
20883 - [OMAP_ECC_BCH4_CODE_HW] = "bch4",
20884 - [OMAP_ECC_BCH8_CODE_HW] = "bch8",
20885 -};
20886 -
20887 static const char * const nand_xfer_types[] = {
20888 [NAND_OMAP_PREFETCH_POLLED] = "prefetch-polled",
20889 [NAND_OMAP_POLLED] = "polled",
20890 @@ -1377,17 +1377,42 @@ static int gpmc_probe_nand_child(struct
20891
20892 gpmc_nand_data->cs = val;
20893 gpmc_nand_data->of_node = child;
20894 -
20895 - if (!of_property_read_string(child, "ti,nand-ecc-opt", &s))
20896 - for (val = 0; val < ARRAY_SIZE(nand_ecc_opts); val++)
20897 - if (!strcasecmp(s, nand_ecc_opts[val])) {
20898 - gpmc_nand_data->ecc_opt = val;
20899 - break;
20900 - }
20901 + /* Detect availability of ELM module */
20902 + gpmc_nand_data->elm_of_node = of_parse_phandle(child, "ti,elm-id", 0);
20903 + if (gpmc_nand_data->elm_of_node == NULL)
20904 + gpmc_nand_data->elm_of_node =
20905 + of_parse_phandle(child, "elm_id", 0);
20906 + if (gpmc_nand_data->elm_of_node == NULL)
20907 + pr_warn("%s: ti,elm-id property not found\n", __func__);
20908 +
20909 + /* select NAND ecc-scheme */
20910 + if (of_property_read_string(child, "ti,nand-ecc-opt", &s)) {
20911 + pr_err("%s: valid ti,nand-ecc-opt not found\n", __func__);
20912 + return -ENODEV;
20913 + }
20914 + if (!strcmp(s, "ham1") || !strcmp(s, "sw") || !strcmp(s, "hw") ||
20915 + !strcmp(s, "hw-romcode"))
20916 + gpmc_nand_data->ecc_opt = OMAP_ECC_HAMMING_CODE_HW;
20917 + else if (!strcmp(s, "bch4"))
20918 + if (gpmc_nand_data->elm_of_node)
20919 + gpmc_nand_data->ecc_opt = OMAP_ECC_BCH4_CODE_HW;
20920 + else
20921 + gpmc_nand_data->ecc_opt =
20922 + OMAP_ECC_BCH4_CODE_HW_DETECTION_SW;
20923 + else if (!strcmp(s, "bch8"))
20924 + if (gpmc_nand_data->elm_of_node)
20925 + gpmc_nand_data->ecc_opt = OMAP_ECC_BCH8_CODE_HW;
20926 + else
20927 + gpmc_nand_data->ecc_opt =
20928 + OMAP_ECC_BCH8_CODE_HW_DETECTION_SW;
20929 + else if (!strcmp(s, "bch16"))
20930 + gpmc_nand_data->ecc_opt = OMAP_ECC_BCH16_CODE_HW;
20931 + else
20932 + pr_err("%s: ti,nand-ecc-opt: invalid property val\n", __func__);
20933
20934 if (!of_property_read_string(child, "ti,nand-xfer-type", &s))
20935 for (val = 0; val < ARRAY_SIZE(nand_xfer_types); val++)
20936 - if (!strcasecmp(s, nand_xfer_types[val])) {
20937 + if (!strcmp(s, nand_xfer_types[val])) {
20938 gpmc_nand_data->xfer_type = val;
20939 break;
20940 }
20941 --- a/arch/arm/mach-omap2/gpmc-nand.c
20942 +++ b/arch/arm/mach-omap2/gpmc-nand.c
20943 @@ -43,28 +43,6 @@ static struct platform_device gpmc_nand_
20944 .resource = gpmc_nand_resource,
20945 };
20946
20947 -static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt)
20948 -{
20949 - /* support only OMAP3 class */
20950 - if (!cpu_is_omap34xx() && !soc_is_am33xx()) {
20951 - pr_err("BCH ecc is not supported on this CPU\n");
20952 - return 0;
20953 - }
20954 -
20955 - /*
20956 - * For now, assume 4-bit mode is only supported on OMAP3630 ES1.x, x>=1
20957 - * and AM33xx derivates. Other chips may be added if confirmed to work.
20958 - */
20959 - if ((ecc_opt == OMAP_ECC_BCH4_CODE_HW) &&
20960 - (!cpu_is_omap3630() || (GET_OMAP_REVISION() == 0)) &&
20961 - (!soc_is_am33xx())) {
20962 - pr_err("BCH 4-bit mode is not supported on this CPU\n");
20963 - return 0;
20964 - }
20965 -
20966 - return 1;
20967 -}
20968 -
20969 int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data,
20970 struct gpmc_timings *gpmc_t)
20971 {
20972 @@ -127,9 +105,6 @@ int gpmc_nand_init(struct omap_nand_plat
20973
20974 gpmc_update_nand_reg(&gpmc_nand_data->reg, gpmc_nand_data->cs);
20975
20976 - if (!gpmc_hwecc_bch_capable(gpmc_nand_data->ecc_opt))
20977 - return -EINVAL;
20978 -
20979 err = platform_device_register(&gpmc_nand_device);
20980 if (err < 0) {
20981 dev_err(dev, "Unable to register NAND device\n");
20982 --- a/arch/arm/mach-omap2/io.c
20983 +++ b/arch/arm/mach-omap2/io.c
20984 @@ -322,6 +322,7 @@ void __init ti81xx_map_io(void)
20985 void __init am33xx_map_io(void)
20986 {
20987 iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc));
20988 + am33xx_dram_sync_init();
20989 }
20990 #endif
20991
20992 @@ -398,6 +399,7 @@ static void __init __maybe_unused omap_c
20993 {
20994 omap_mux_late_init();
20995 omap2_common_pm_late_init();
20996 + omap2_common_suspend_init();
20997 omap_soc_device_init();
20998 }
20999
21000 @@ -488,21 +490,29 @@ void __init omap3_init_early(void)
21001 void __init omap3430_init_early(void)
21002 {
21003 omap3_init_early();
21004 + if (of_have_populated_dt())
21005 + omap_clk_init = omap3430_clk_init;
21006 }
21007
21008 void __init omap35xx_init_early(void)
21009 {
21010 omap3_init_early();
21011 + if (of_have_populated_dt())
21012 + omap_clk_init = omap3430_clk_init;
21013 }
21014
21015 void __init omap3630_init_early(void)
21016 {
21017 omap3_init_early();
21018 + if (of_have_populated_dt())
21019 + omap_clk_init = omap3630_clk_init;
21020 }
21021
21022 void __init am35xx_init_early(void)
21023 {
21024 omap3_init_early();
21025 + if (of_have_populated_dt())
21026 + omap_clk_init = am35xx_clk_init;
21027 }
21028
21029 void __init ti81xx_init_early(void)
21030 @@ -520,7 +530,10 @@ void __init ti81xx_init_early(void)
21031 omap3xxx_clockdomains_init();
21032 omap3xxx_hwmod_init();
21033 omap_hwmod_init_postsetup();
21034 - omap_clk_init = omap3xxx_clk_init;
21035 + if (of_have_populated_dt())
21036 + omap_clk_init = ti81xx_clk_init;
21037 + else
21038 + omap_clk_init = omap3xxx_clk_init;
21039 }
21040
21041 void __init omap3_init_late(void)
21042 @@ -583,6 +596,13 @@ void __init am33xx_init_early(void)
21043 omap_hwmod_init_postsetup();
21044 omap_clk_init = am33xx_clk_init;
21045 }
21046 +
21047 +void __init am33xx_init_late(void)
21048 +{
21049 + omap_hwmod_force_mstandby_repeated();
21050 + omap2_common_pm_late_init();
21051 + am33xx_pm_init();
21052 +}
21053 #endif
21054
21055 #ifdef CONFIG_SOC_AM43XX
21056 @@ -594,7 +614,15 @@ void __init am43xx_init_early(void)
21057 NULL);
21058 omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM43XX_PRCM_BASE));
21059 omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM43XX_PRCM_BASE), NULL);
21060 + omap_prm_base_init();
21061 + omap_cm_base_init();
21062 omap3xxx_check_revision();
21063 + am33xx_check_features();
21064 + am43xx_powerdomains_init();
21065 + am43xx_clockdomains_init();
21066 + am33xx_hwmod_init();
21067 + omap_hwmod_init_postsetup();
21068 + omap_clk_init = am43xx_clk_init;
21069 }
21070 #endif
21071
21072 @@ -650,6 +678,16 @@ void __init omap5_init_early(void)
21073 omap54xx_clockdomains_init();
21074 omap54xx_hwmod_init();
21075 omap_hwmod_init_postsetup();
21076 + omap_clk_init = omap5xxx_clk_init;
21077 +}
21078 +
21079 +void __init omap5_init_late(void)
21080 +{
21081 + omap_mux_late_init();
21082 + omap2_common_pm_late_init();
21083 + omap2_common_suspend_init();
21084 + omap4_pm_init();
21085 + omap2_clk_enable_autoidle_all();
21086 }
21087 #endif
21088
21089 @@ -670,9 +708,17 @@ void __init dra7xx_init_early(void)
21090 dra7xx_clockdomains_init();
21091 dra7xx_hwmod_init();
21092 omap_hwmod_init_postsetup();
21093 + omap_clk_init = dra7xx_clk_init;
21094 }
21095 -#endif
21096
21097 +void __init dra7xx_init_late(void)
21098 +{
21099 + omap2_common_pm_late_init();
21100 + omap2_common_suspend_init();
21101 + omap4_pm_init();
21102 + omap2_clk_enable_autoidle_all();
21103 +}
21104 +#endif
21105
21106 void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
21107 struct omap_sdrc_params *sdrc_cs1)
21108 --- a/arch/arm/mach-omap2/Kconfig
21109 +++ b/arch/arm/mach-omap2/Kconfig
21110 @@ -66,11 +66,16 @@ config SOC_OMAP5
21111 config SOC_AM33XX
21112 bool "TI AM33XX"
21113 depends on ARCH_MULTI_V7
21114 - select ARCH_OMAP2PLUS
21115 + default y
21116 select ARM_CPU_SUSPEND if PM
21117 + select COMMON_CLK
21118 select CPU_V7
21119 + select MAILBOX if PM
21120 select MULTI_IRQ_HANDLER
21121 - select COMMON_CLK
21122 + select ARCH_HAS_RESET_CONTROLLER
21123 + select OMAP_MBOX_FWK if PM
21124 + select OMAP2PLUS_MBOX if PM
21125 + select RESET_TI
21126
21127 config SOC_AM43XX
21128 bool "TI AM43x"
21129 @@ -81,29 +86,9 @@ config SOC_AM43XX
21130 select ARM_GIC
21131 select COMMON_CLK
21132 select MACH_OMAP_GENERIC
21133 -
21134 -config ARCH_OMAP2PLUS
21135 - bool
21136 - select ARCH_HAS_BANDGAP
21137 - select ARCH_HAS_CPUFREQ
21138 - select ARCH_HAS_HOLES_MEMORYMODEL
21139 - select ARCH_OMAP
21140 - select ARCH_REQUIRE_GPIOLIB
21141 - select CLKDEV_LOOKUP
21142 - select CLKSRC_MMIO
21143 - select GENERIC_CLOCKEVENTS
21144 - select GENERIC_IRQ_CHIP
21145 - select HAVE_CLK
21146 - select OMAP_DM_TIMER
21147 - select PINCTRL
21148 - select PROC_DEVICETREE if PROC_FS
21149 - select SOC_BUS
21150 - select SPARSE_IRQ
21151 - select TI_PRIV_EDMA
21152 - select USE_OF
21153 - help
21154 - Systems based on OMAP2, OMAP3, OMAP4 or OMAP5
21155 -
21156 + select MIGHT_HAVE_CACHE_L2X0
21157 + select ARCH_HAS_RESET_CONTROLLER
21158 + select RESET_TI
21159
21160 if ARCH_OMAP2PLUS
21161
21162 @@ -141,6 +126,9 @@ config SOC_DRA7XX
21163 select ARM_GIC
21164 select HAVE_SMP
21165 select COMMON_CLK
21166 + select CROSSBAR
21167 + select ARCH_HAS_RESET_CONTROLLER
21168 + select RESET_TI
21169
21170 comment "OMAP Core Type"
21171 depends on ARCH_OMAP2
21172 --- a/arch/arm/mach-omap2/Makefile
21173 +++ b/arch/arm/mach-omap2/Makefile
21174 @@ -8,7 +8,7 @@ ccflags-$(CONFIG_ARCH_MULTIPLATFORM) :=
21175 # Common support
21176 obj-y := id.o io.o control.o mux.o devices.o fb.o serial.o gpmc.o timer.o pm.o \
21177 common.o gpio.o dma.o wd_timer.o display.o i2c.o hdq1w.o omap_hwmod.o \
21178 - omap_device.o sram.o
21179 + omap_device.o sram.o drm.o
21180
21181 omap-2-3-common = irq.o
21182 hwmod-common = omap_hwmod.o omap_hwmod_reset.o \
21183 @@ -60,6 +60,7 @@ AFLAGS_sram34xx.o :=-Wa,-march=armv7-a
21184 obj-$(CONFIG_SOC_OMAP2420) += omap2-restart.o
21185 obj-$(CONFIG_SOC_OMAP2430) += omap2-restart.o
21186 obj-$(CONFIG_SOC_AM33XX) += am33xx-restart.o
21187 +obj-$(CONFIG_SOC_AM43XX) += am33xx-restart.o
21188 obj-$(CONFIG_ARCH_OMAP3) += omap3-restart.o
21189 obj-$(CONFIG_ARCH_OMAP4) += omap4-restart.o
21190 obj-$(CONFIG_SOC_OMAP5) += omap4-restart.o
21191 @@ -91,6 +92,7 @@ obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sl
21192 obj-$(CONFIG_ARCH_OMAP4) += pm44xx.o omap-mpuss-lowpower.o
21193 obj-$(CONFIG_SOC_OMAP5) += omap-mpuss-lowpower.o
21194 obj-$(CONFIG_SOC_DRA7XX) += omap-mpuss-lowpower.o
21195 +obj-$(CONFIG_SOC_AM33XX) += pm33xx.o sleep33xx.o wkup_m3.o
21196 obj-$(CONFIG_PM_DEBUG) += pm-debug.o
21197
21198 obj-$(CONFIG_POWER_AVS_OMAP) += sr_device.o
21199 @@ -98,6 +100,7 @@ obj-$(CONFIG_POWER_AVS_OMAP_CLASS3) +
21200
21201 AFLAGS_sleep24xx.o :=-Wa,-march=armv6
21202 AFLAGS_sleep34xx.o :=-Wa,-march=armv7-a$(plus_sec)
21203 +AFLAGS_sleep33xx.o :=-Wa,-march=armv7-a$(plus_sec)
21204
21205 endif
21206
21207 @@ -112,13 +115,13 @@ obj-$(CONFIG_ARCH_OMAP2) += prm2xxx_3xx
21208 obj-$(CONFIG_ARCH_OMAP3) += prm2xxx_3xxx.o prm3xxx.o cm3xxx.o
21209 obj-$(CONFIG_ARCH_OMAP3) += vc3xxx_data.o vp3xxx_data.o
21210 obj-$(CONFIG_SOC_AM33XX) += prm33xx.o cm33xx.o
21211 -obj-$(CONFIG_SOC_AM43XX) += prm33xx.o cm33xx.o
21212 omap-prcm-4-5-common = cminst44xx.o cm44xx.o prm44xx.o \
21213 prcm_mpu44xx.o prminst44xx.o \
21214 vc44xx_data.o vp44xx_data.o
21215 obj-$(CONFIG_ARCH_OMAP4) += $(omap-prcm-4-5-common)
21216 obj-$(CONFIG_SOC_OMAP5) += $(omap-prcm-4-5-common)
21217 obj-$(CONFIG_SOC_DRA7XX) += $(omap-prcm-4-5-common)
21218 +obj-$(CONFIG_SOC_AM43XX) += $(omap-prcm-4-5-common)
21219
21220 # OMAP voltage domains
21221 voltagedomain-common := voltage.o vc.o vp.o
21222 @@ -146,6 +149,7 @@ obj-$(CONFIG_ARCH_OMAP4) += powerdomain
21223 obj-$(CONFIG_SOC_AM33XX) += $(powerdomain-common)
21224 obj-$(CONFIG_SOC_AM33XX) += powerdomains33xx_data.o
21225 obj-$(CONFIG_SOC_AM43XX) += $(powerdomain-common)
21226 +obj-$(CONFIG_SOC_AM43XX) += powerdomains43xx_data.o
21227 obj-$(CONFIG_SOC_OMAP5) += $(powerdomain-common)
21228 obj-$(CONFIG_SOC_OMAP5) += powerdomains54xx_data.o
21229 obj-$(CONFIG_SOC_DRA7XX) += $(powerdomain-common)
21230 @@ -165,6 +169,7 @@ obj-$(CONFIG_ARCH_OMAP4) += clockdomain
21231 obj-$(CONFIG_SOC_AM33XX) += $(clockdomain-common)
21232 obj-$(CONFIG_SOC_AM33XX) += clockdomains33xx_data.o
21233 obj-$(CONFIG_SOC_AM43XX) += $(clockdomain-common)
21234 +obj-$(CONFIG_SOC_AM43XX) += clockdomains43xx_data.o
21235 obj-$(CONFIG_SOC_OMAP5) += $(clockdomain-common)
21236 obj-$(CONFIG_SOC_OMAP5) += clockdomains54xx_data.o
21237 obj-$(CONFIG_SOC_DRA7XX) += $(clockdomain-common)
21238 @@ -184,10 +189,9 @@ obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o
21239 obj-$(CONFIG_ARCH_OMAP3) += clock3517.o clock36xx.o
21240 obj-$(CONFIG_ARCH_OMAP3) += dpll3xxx.o cclock3xxx_data.o
21241 obj-$(CONFIG_ARCH_OMAP3) += clkt_iclk.o
21242 -obj-$(CONFIG_ARCH_OMAP4) += $(clock-common) cclock44xx_data.o
21243 +obj-$(CONFIG_ARCH_OMAP4) += $(clock-common)
21244 obj-$(CONFIG_ARCH_OMAP4) += dpll3xxx.o dpll44xx.o
21245 obj-$(CONFIG_SOC_AM33XX) += $(clock-common) dpll3xxx.o
21246 -obj-$(CONFIG_SOC_AM33XX) += cclock33xx_data.o
21247 obj-$(CONFIG_SOC_OMAP5) += $(clock-common)
21248 obj-$(CONFIG_SOC_OMAP5) += dpll3xxx.o dpll44xx.o
21249
21250 @@ -210,6 +214,7 @@ obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_
21251 obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_2xxx_3xxx_interconnect_data.o
21252 obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_3xxx_data.o
21253 obj-$(CONFIG_SOC_AM33XX) += omap_hwmod_33xx_data.o
21254 +obj-$(CONFIG_SOC_AM43XX) += omap_hwmod_33xx_data.o
21255 obj-$(CONFIG_ARCH_OMAP4) += omap_hwmod_44xx_data.o
21256 obj-$(CONFIG_SOC_OMAP5) += omap_hwmod_54xx_data.o
21257 obj-$(CONFIG_SOC_DRA7XX) += omap_hwmod_7xx_data.o
21258 @@ -228,10 +233,6 @@ endif
21259 # OMAP2420 MSDI controller integration support ("MMC")
21260 obj-$(CONFIG_SOC_OMAP2420) += msdi.o
21261
21262 -ifneq ($(CONFIG_DRM_OMAP),)
21263 -obj-y += drm.o
21264 -endif
21265 -
21266 # Specific board support
21267 obj-$(CONFIG_MACH_OMAP_GENERIC) += board-generic.o
21268 obj-$(CONFIG_MACH_OMAP_H4) += board-h4.o
21269 @@ -305,4 +306,4 @@ endif
21270 emac-$(CONFIG_TI_DAVINCI_EMAC) := am35xx-emac.o
21271 obj-y += $(emac-m) $(emac-y)
21272
21273 -obj-y += common-board-devices.o twl-common.o dss-common.o
21274 +obj-y += common-board-devices.o twl-common.o
21275 --- a/arch/arm/mach-omap2/omap4-common.c
21276 +++ b/arch/arm/mach-omap2/omap4-common.c
21277 @@ -181,7 +181,7 @@ static int __init omap_l2_cache_init(voi
21278 * To avoid code running on other OMAPs in
21279 * multi-omap builds
21280 */
21281 - if (!cpu_is_omap44xx())
21282 + if (!cpu_is_omap44xx() && !soc_is_am43xx())
21283 return -ENODEV;
21284
21285 /* Static mapping, never released */
21286 @@ -193,26 +193,32 @@ static int __init omap_l2_cache_init(voi
21287 * 16-way associativity, parity disabled
21288 * Way size - 32KB (es1.0)
21289 * Way size - 64KB (es2.0 +)
21290 + * Way size - 16KB (am43xx)
21291 */
21292 aux_ctrl = ((1 << L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT) |
21293 (0x1 << 25) |
21294 (0x1 << L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT) |
21295 (0x1 << L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT));
21296
21297 - if (omap_rev() == OMAP4430_REV_ES1_0) {
21298 + if (soc_is_am43xx())
21299 + aux_ctrl |= ((0x1 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT) |
21300 + (1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) |
21301 + (1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) |
21302 + (1 << L2X0_AUX_CTRL_EARLY_BRESP_SHIFT));
21303 + else if (omap_rev() == OMAP4430_REV_ES1_0)
21304 aux_ctrl |= 0x2 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT;
21305 - } else {
21306 + else
21307 aux_ctrl |= ((0x3 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT) |
21308 (1 << L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT) |
21309 (1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) |
21310 (1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) |
21311 (1 << L2X0_AUX_CTRL_EARLY_BRESP_SHIFT));
21312 - }
21313 - if (omap_rev() != OMAP4430_REV_ES1_0)
21314 +
21315 + if (soc_is_am43xx() || (omap_rev() != OMAP4430_REV_ES1_0))
21316 omap_smc1(0x109, aux_ctrl);
21317
21318 /* Enable PL310 L2 Cache controller */
21319 - omap_smc1(0x102, 0x1);
21320 + omap_smc1(0x102, L2X0_CTRL_EN);
21321
21322 if (of_have_populated_dt())
21323 l2x0_of_init(aux_ctrl, L2X0_AUX_CTRL_MASK);
21324 @@ -233,7 +239,10 @@ omap_early_initcall(omap_l2_cache_init);
21325
21326 void __iomem *omap4_get_sar_ram_base(void)
21327 {
21328 - return sar_ram_base;
21329 + if (sar_ram_base)
21330 + return sar_ram_base;
21331 + else
21332 + return NULL;
21333 }
21334
21335 /*
21336 --- a/arch/arm/mach-omap2/omap4-sar-layout.h
21337 +++ b/arch/arm/mach-omap2/omap4-sar-layout.h
21338 @@ -31,6 +31,8 @@
21339 /* CPUx Wakeup Non-Secure Physical Address offsets in SAR_BANK3 */
21340 #define CPU0_WAKEUP_NS_PA_ADDR_OFFSET 0xa04
21341 #define CPU1_WAKEUP_NS_PA_ADDR_OFFSET 0xa08
21342 +#define OMAP5_CPU0_WAKEUP_NS_PA_ADDR_OFFSET 0xe00
21343 +#define OMAP5_CPU1_WAKEUP_NS_PA_ADDR_OFFSET 0xe04
21344
21345 #define SAR_BACKUP_STATUS_OFFSET (SAR_BANK3_OFFSET + 0x500)
21346 #define SAR_SECURE_RAM_SIZE_OFFSET (SAR_BANK3_OFFSET + 0x504)
21347 --- a/arch/arm/mach-omap2/omap_device.c
21348 +++ b/arch/arm/mach-omap2/omap_device.c
21349 @@ -35,6 +35,7 @@
21350 #include <linux/pm_runtime.h>
21351 #include <linux/of.h>
21352 #include <linux/notifier.h>
21353 +#include <linux/suspend.h>
21354
21355 #include "soc.h"
21356 #include "omap_device.h"
21357 @@ -45,37 +46,32 @@
21358 static void _add_clkdev(struct omap_device *od, const char *clk_alias,
21359 const char *clk_name)
21360 {
21361 + int ret;
21362 struct clk *r;
21363 - struct clk_lookup *l;
21364 + struct device *dev = &od->pdev->dev;
21365 + struct device_node *node = dev->of_node;
21366
21367 if (!clk_alias || !clk_name)
21368 return;
21369
21370 - dev_dbg(&od->pdev->dev, "Creating %s -> %s\n", clk_alias, clk_name);
21371 + dev_dbg(dev, "Creating %s -> %s\n", clk_alias, clk_name);
21372
21373 - r = clk_get_sys(dev_name(&od->pdev->dev), clk_alias);
21374 + r = clk_get(dev, clk_alias);
21375 if (!IS_ERR(r)) {
21376 - dev_warn(&od->pdev->dev,
21377 - "alias %s already exists\n", clk_alias);
21378 + if (!node)
21379 + dev_warn(dev, "alias '%s' already exists\n", clk_alias);
21380 clk_put(r);
21381 return;
21382 }
21383
21384 - r = clk_get(NULL, clk_name);
21385 - if (IS_ERR(r)) {
21386 - dev_err(&od->pdev->dev,
21387 - "clk_get for %s failed\n", clk_name);
21388 - return;
21389 - }
21390 + if (node)
21391 + dev_err(dev, "FIXME: clock-name '%s' DOES NOT exist in dt!\n",
21392 + clk_alias);
21393
21394 - l = clkdev_alloc(r, clk_alias, dev_name(&od->pdev->dev));
21395 - if (!l) {
21396 - dev_err(&od->pdev->dev,
21397 - "clkdev_alloc for %s failed\n", clk_alias);
21398 - return;
21399 - }
21400 -
21401 - clkdev_add(l);
21402 + ret = clk_add_alias(clk_alias, dev_name(dev), (char *)clk_name, dev);
21403 + if (ret)
21404 + dev_err(dev, "Failed to alias %s to %s: %d\n", clk_alias,
21405 + clk_name, ret);
21406 }
21407
21408 /**
21409 @@ -621,6 +617,13 @@ static int _od_suspend_noirq(struct devi
21410
21411 if (!ret && !pm_runtime_status_suspended(dev)) {
21412 if (pm_generic_runtime_suspend(dev) == 0) {
21413 + if (!pm_runtime_suspended(dev)) {
21414 + /* NOTE: *might* indicate driver race */
21415 + dev_dbg(dev, "%s: Force suspending\n",
21416 + __func__);
21417 + pm_runtime_set_suspended(dev);
21418 + od->flags |= OMAP_DEVICE_SUSPEND_FORCED;
21419 + }
21420 omap_device_idle(pdev);
21421 od->flags |= OMAP_DEVICE_SUSPENDED;
21422 }
21423 @@ -634,10 +637,15 @@ static int _od_resume_noirq(struct devic
21424 struct platform_device *pdev = to_platform_device(dev);
21425 struct omap_device *od = to_omap_device(pdev);
21426
21427 - if ((od->flags & OMAP_DEVICE_SUSPENDED) &&
21428 - !pm_runtime_status_suspended(dev)) {
21429 + if (od->flags & OMAP_DEVICE_SUSPENDED) {
21430 od->flags &= ~OMAP_DEVICE_SUSPENDED;
21431 omap_device_enable(pdev);
21432 +
21433 + if (od->flags & OMAP_DEVICE_SUSPEND_FORCED) {
21434 + pm_runtime_set_active(dev);
21435 + od->flags &= ~OMAP_DEVICE_SUSPEND_FORCED;
21436 + }
21437 +
21438 pm_generic_runtime_resume(dev);
21439 }
21440
21441 @@ -850,6 +858,7 @@ static int __init omap_device_late_idle(
21442 {
21443 struct platform_device *pdev = to_platform_device(dev);
21444 struct omap_device *od = to_omap_device(pdev);
21445 + struct omap_hwmod *oh = NULL;
21446 int i;
21447
21448 if (!od)
21449 @@ -874,6 +883,19 @@ static int __init omap_device_late_idle(
21450 __func__);
21451 omap_device_idle(pdev);
21452 }
21453 + } else {
21454 + /*
21455 + * There are some IPs that do not have MSTANDBY asserted by default
21456 + * which is necessary for PER domain transition. If the drivers
21457 + * are not compiled into the kernel HWMOD code will not change the
21458 + * state of the IPs if the IP was never enabled, so we keep track of
21459 + * them here to idle them with a pm_notifier.
21460 + */
21461 + for (i = 0; i < od->hwmods_cnt; i++) {
21462 + oh = od->hwmods[i];
21463 + if (oh->flags & HWMOD_FORCE_MSTANDBY_REPEATED)
21464 + omap_hwmod_disable_force_mstandby_repeated(oh);
21465 + }
21466 }
21467
21468 return 0;
21469 --- a/arch/arm/mach-omap2/omap_device.h
21470 +++ b/arch/arm/mach-omap2/omap_device.h
21471 @@ -38,6 +38,7 @@ extern struct dev_pm_domain omap_device_
21472
21473 /* omap_device.flags values */
21474 #define OMAP_DEVICE_SUSPENDED BIT(0)
21475 +#define OMAP_DEVICE_SUSPEND_FORCED BIT(1)
21476
21477 /**
21478 * struct omap_device - omap_device wrapper for platform_devices
21479 --- a/arch/arm/mach-omap2/omap-hotplug.c
21480 +++ b/arch/arm/mach-omap2/omap-hotplug.c
21481 @@ -22,6 +22,7 @@
21482 #include "omap-wakeupgen.h"
21483 #include "common.h"
21484 #include "powerdomain.h"
21485 +#include "soc.h"
21486
21487 /*
21488 * platform-specific code to shutdown a CPU
21489 @@ -47,7 +48,10 @@ void __ref omap4_cpu_die(unsigned int cp
21490 /*
21491 * Enter into low power state
21492 */
21493 - omap4_hotplug_cpu(cpu, PWRDM_POWER_OFF);
21494 + if (soc_is_dra7xx())
21495 + omap4_hotplug_cpu(cpu, PWRDM_POWER_RET);
21496 + else
21497 + omap4_hotplug_cpu(cpu, PWRDM_POWER_OFF);
21498
21499 if (omap_secure_apis_support())
21500 boot_cpu = omap_read_auxcoreboot0();
21501 --- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
21502 +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
21503 @@ -26,9 +26,11 @@
21504 #include "cm33xx.h"
21505 #include "prm33xx.h"
21506 #include "prm-regbits-33xx.h"
21507 +#include "prcm43xx.h"
21508 #include "i2c.h"
21509 #include "mmc.h"
21510 #include "wd_timer.h"
21511 +#include "soc.h"
21512
21513 /*
21514 * IP blocks
21515 @@ -52,7 +54,7 @@ static struct omap_hwmod am33xx_emif_hwm
21516 .name = "emif",
21517 .class = &am33xx_emif_hwmod_class,
21518 .clkdm_name = "l3_clkdm",
21519 - .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
21520 + .flags = HWMOD_INIT_NO_IDLE,
21521 .main_clk = "dpll_ddr_m2_div2_ck",
21522 .prcm = {
21523 .omap4 = {
21524 @@ -74,11 +76,9 @@ static struct omap_hwmod am33xx_l3_main_
21525 .name = "l3_main",
21526 .class = &am33xx_l3_hwmod_class,
21527 .clkdm_name = "l3_clkdm",
21528 - .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
21529 - .main_clk = "l3_gclk",
21530 + .flags = HWMOD_INIT_NO_IDLE,
21531 .prcm = {
21532 .omap4 = {
21533 - .clkctrl_offs = AM33XX_CM_PER_L3_CLKCTRL_OFFSET,
21534 .modulemode = MODULEMODE_SWCTRL,
21535 },
21536 },
21537 @@ -96,11 +96,10 @@ static struct omap_hwmod am33xx_l3_instr
21538 .name = "l3_instr",
21539 .class = &am33xx_l3_hwmod_class,
21540 .clkdm_name = "l3_clkdm",
21541 - .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
21542 + .flags = HWMOD_INIT_NO_IDLE,
21543 .main_clk = "l3_gclk",
21544 .prcm = {
21545 .omap4 = {
21546 - .clkctrl_offs = AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET,
21547 .modulemode = MODULEMODE_SWCTRL,
21548 },
21549 },
21550 @@ -119,11 +118,10 @@ static struct omap_hwmod am33xx_l4_ls_hw
21551 .name = "l4_ls",
21552 .class = &am33xx_l4_hwmod_class,
21553 .clkdm_name = "l4ls_clkdm",
21554 - .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
21555 + .flags = HWMOD_INIT_NO_IDLE,
21556 .main_clk = "l4ls_gclk",
21557 .prcm = {
21558 .omap4 = {
21559 - .clkctrl_offs = AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET,
21560 .modulemode = MODULEMODE_SWCTRL,
21561 },
21562 },
21563 @@ -133,12 +131,10 @@ static struct omap_hwmod am33xx_l4_ls_hw
21564 static struct omap_hwmod am33xx_l4_hs_hwmod = {
21565 .name = "l4_hs",
21566 .class = &am33xx_l4_hwmod_class,
21567 - .clkdm_name = "l4hs_clkdm",
21568 - .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
21569 + .flags = HWMOD_INIT_NO_IDLE,
21570 .main_clk = "l4hs_gclk",
21571 .prcm = {
21572 .omap4 = {
21573 - .clkctrl_offs = AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET,
21574 .modulemode = MODULEMODE_SWCTRL,
21575 },
21576 },
21577 @@ -150,10 +146,9 @@ static struct omap_hwmod am33xx_l4_wkup_
21578 .name = "l4_wkup",
21579 .class = &am33xx_l4_hwmod_class,
21580 .clkdm_name = "l4_wkup_clkdm",
21581 - .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
21582 + .flags = HWMOD_INIT_NO_IDLE,
21583 .prcm = {
21584 .omap4 = {
21585 - .clkctrl_offs = AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
21586 .modulemode = MODULEMODE_SWCTRL,
21587 },
21588 },
21589 @@ -170,11 +165,10 @@ static struct omap_hwmod am33xx_mpu_hwmo
21590 .name = "mpu",
21591 .class = &am33xx_mpu_hwmod_class,
21592 .clkdm_name = "mpu_clkdm",
21593 - .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
21594 + .flags = HWMOD_INIT_NO_IDLE,
21595 .main_clk = "dpll_mpu_m2_ck",
21596 .prcm = {
21597 .omap4 = {
21598 - .clkctrl_offs = AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET,
21599 .modulemode = MODULEMODE_SWCTRL,
21600 },
21601 },
21602 @@ -198,13 +192,9 @@ static struct omap_hwmod am33xx_wkup_m3_
21603 .class = &am33xx_wkup_m3_hwmod_class,
21604 .clkdm_name = "l4_wkup_aon_clkdm",
21605 /* Keep hardreset asserted */
21606 - .flags = HWMOD_INIT_NO_RESET | HWMOD_NO_IDLEST,
21607 - .main_clk = "dpll_core_m4_div2_ck",
21608 + .flags = HWMOD_NO_IDLEST,
21609 .prcm = {
21610 .omap4 = {
21611 - .clkctrl_offs = AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
21612 - .rstctrl_offs = AM33XX_RM_WKUP_RSTCTRL_OFFSET,
21613 - .rstst_offs = AM33XX_RM_WKUP_RSTST_OFFSET,
21614 .modulemode = MODULEMODE_SWCTRL,
21615 },
21616 },
21617 @@ -233,8 +223,6 @@ static struct omap_hwmod am33xx_pruss_hw
21618 .main_clk = "pruss_ocp_gclk",
21619 .prcm = {
21620 .omap4 = {
21621 - .clkctrl_offs = AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET,
21622 - .rstctrl_offs = AM33XX_RM_PER_RSTCTRL_OFFSET,
21623 .modulemode = MODULEMODE_SWCTRL,
21624 },
21625 },
21626 @@ -259,9 +247,6 @@ static struct omap_hwmod am33xx_gfx_hwmo
21627 .main_clk = "gfx_fck_div_ck",
21628 .prcm = {
21629 .omap4 = {
21630 - .clkctrl_offs = AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET,
21631 - .rstctrl_offs = AM33XX_RM_GFX_RSTCTRL_OFFSET,
21632 - .rstst_offs = AM33XX_RM_GFX_RSTST_OFFSET,
21633 .modulemode = MODULEMODE_SWCTRL,
21634 },
21635 },
21636 @@ -305,11 +290,8 @@ static struct omap_hwmod_class am33xx_ad
21637 static struct omap_hwmod am33xx_adc_tsc_hwmod = {
21638 .name = "adc_tsc",
21639 .class = &am33xx_adc_tsc_hwmod_class,
21640 - .clkdm_name = "l4_wkup_clkdm",
21641 - .main_clk = "adc_tsc_fck",
21642 .prcm = {
21643 .omap4 = {
21644 - .clkctrl_offs = AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET,
21645 .modulemode = MODULEMODE_SWCTRL,
21646 },
21647 },
21648 @@ -395,6 +377,7 @@ static struct omap_hwmod_class_sysconfig
21649 .sysc_offs = 0x84,
21650 .syss_offs = 0x88,
21651 .sysc_flags = SYSS_HAS_RESET_STATUS,
21652 + .sysc_fields = &omap_hwmod_sysc_type4,
21653 };
21654
21655 static struct omap_hwmod_class am33xx_aes0_hwmod_class = {
21656 @@ -406,10 +389,8 @@ static struct omap_hwmod am33xx_aes0_hwm
21657 .name = "aes",
21658 .class = &am33xx_aes0_hwmod_class,
21659 .clkdm_name = "l3_clkdm",
21660 - .main_clk = "aes0_fck",
21661 .prcm = {
21662 .omap4 = {
21663 - .clkctrl_offs = AM33XX_CM_PER_AES0_CLKCTRL_OFFSET,
21664 .modulemode = MODULEMODE_SWCTRL,
21665 },
21666 },
21667 @@ -432,10 +413,8 @@ static struct omap_hwmod am33xx_sha0_hwm
21668 .name = "sham",
21669 .class = &am33xx_sha0_hwmod_class,
21670 .clkdm_name = "l3_clkdm",
21671 - .main_clk = "l3_gclk",
21672 .prcm = {
21673 .omap4 = {
21674 - .clkctrl_offs = AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET,
21675 .modulemode = MODULEMODE_SWCTRL,
21676 },
21677 },
21678 @@ -450,11 +429,9 @@ static struct omap_hwmod am33xx_ocmcram_
21679 .name = "ocmcram",
21680 .class = &am33xx_ocmcram_hwmod_class,
21681 .clkdm_name = "l3_clkdm",
21682 - .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
21683 - .main_clk = "l3_gclk",
21684 + .flags = HWMOD_INIT_NO_IDLE,
21685 .prcm = {
21686 .omap4 = {
21687 - .clkctrl_offs = AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET,
21688 .modulemode = MODULEMODE_SWCTRL,
21689 },
21690 },
21691 @@ -501,7 +478,6 @@ static struct omap_hwmod am33xx_smartref
21692 .main_clk = "smartreflex0_fck",
21693 .prcm = {
21694 .omap4 = {
21695 - .clkctrl_offs = AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET,
21696 .modulemode = MODULEMODE_SWCTRL,
21697 },
21698 },
21699 @@ -515,7 +491,6 @@ static struct omap_hwmod am33xx_smartref
21700 .main_clk = "smartreflex1_fck",
21701 .prcm = {
21702 .omap4 = {
21703 - .clkctrl_offs = AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET,
21704 .modulemode = MODULEMODE_SWCTRL,
21705 },
21706 },
21707 @@ -532,11 +507,9 @@ static struct omap_hwmod am33xx_control_
21708 .name = "control",
21709 .class = &am33xx_control_hwmod_class,
21710 .clkdm_name = "l4_wkup_clkdm",
21711 - .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
21712 - .main_clk = "dpll_core_m4_div2_ck",
21713 + .flags = HWMOD_INIT_NO_IDLE,
21714 .prcm = {
21715 .omap4 = {
21716 - .clkctrl_offs = AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET,
21717 .modulemode = MODULEMODE_SWCTRL,
21718 },
21719 },
21720 @@ -566,12 +539,11 @@ static struct omap_hwmod am33xx_cpgmac0_
21721 .name = "cpgmac0",
21722 .class = &am33xx_cpgmac0_hwmod_class,
21723 .clkdm_name = "cpsw_125mhz_clkdm",
21724 - .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
21725 - .main_clk = "cpsw_125mhz_gclk",
21726 + .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
21727 + HWMOD_FORCE_MSTANDBY_REPEATED),
21728 .mpu_rt_idx = 1,
21729 .prcm = {
21730 .omap4 = {
21731 - .clkctrl_offs = AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET,
21732 .modulemode = MODULEMODE_SWCTRL,
21733 },
21734 },
21735 @@ -588,7 +560,6 @@ static struct omap_hwmod am33xx_mdio_hwm
21736 .name = "davinci_mdio",
21737 .class = &am33xx_mdio_hwmod_class,
21738 .clkdm_name = "cpsw_125mhz_clkdm",
21739 - .main_clk = "cpsw_125mhz_gclk",
21740 };
21741
21742 /*
21743 @@ -603,10 +574,8 @@ static struct omap_hwmod am33xx_dcan0_hw
21744 .name = "d_can0",
21745 .class = &am33xx_dcan_hwmod_class,
21746 .clkdm_name = "l4ls_clkdm",
21747 - .main_clk = "dcan0_fck",
21748 .prcm = {
21749 .omap4 = {
21750 - .clkctrl_offs = AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET,
21751 .modulemode = MODULEMODE_SWCTRL,
21752 },
21753 },
21754 @@ -617,10 +586,8 @@ static struct omap_hwmod am33xx_dcan1_hw
21755 .name = "d_can1",
21756 .class = &am33xx_dcan_hwmod_class,
21757 .clkdm_name = "l4ls_clkdm",
21758 - .main_clk = "dcan1_fck",
21759 .prcm = {
21760 .omap4 = {
21761 - .clkctrl_offs = AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET,
21762 .modulemode = MODULEMODE_SWCTRL,
21763 },
21764 },
21765 @@ -647,10 +614,8 @@ static struct omap_hwmod am33xx_elm_hwmo
21766 .name = "elm",
21767 .class = &am33xx_elm_hwmod_class,
21768 .clkdm_name = "l4ls_clkdm",
21769 - .main_clk = "l4ls_gclk",
21770 .prcm = {
21771 .omap4 = {
21772 - .clkctrl_offs = AM33XX_CM_PER_ELM_CLKCTRL_OFFSET,
21773 .modulemode = MODULEMODE_SWCTRL,
21774 },
21775 },
21776 @@ -689,10 +654,8 @@ static struct omap_hwmod am33xx_epwmss0_
21777 .name = "epwmss0",
21778 .class = &am33xx_epwmss_hwmod_class,
21779 .clkdm_name = "l4ls_clkdm",
21780 - .main_clk = "l4ls_gclk",
21781 .prcm = {
21782 .omap4 = {
21783 - .clkctrl_offs = AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET,
21784 .modulemode = MODULEMODE_SWCTRL,
21785 },
21786 },
21787 @@ -703,7 +666,6 @@ static struct omap_hwmod am33xx_ecap0_hw
21788 .name = "ecap0",
21789 .class = &am33xx_ecap_hwmod_class,
21790 .clkdm_name = "l4ls_clkdm",
21791 - .main_clk = "l4ls_gclk",
21792 };
21793
21794 /* eqep0 */
21795 @@ -719,7 +681,6 @@ static struct omap_hwmod am33xx_ehrpwm0_
21796 .name = "ehrpwm0",
21797 .class = &am33xx_ehrpwm_hwmod_class,
21798 .clkdm_name = "l4ls_clkdm",
21799 - .main_clk = "l4ls_gclk",
21800 };
21801
21802 /* epwmss1 */
21803 @@ -727,10 +688,8 @@ static struct omap_hwmod am33xx_epwmss1_
21804 .name = "epwmss1",
21805 .class = &am33xx_epwmss_hwmod_class,
21806 .clkdm_name = "l4ls_clkdm",
21807 - .main_clk = "l4ls_gclk",
21808 .prcm = {
21809 .omap4 = {
21810 - .clkctrl_offs = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET,
21811 .modulemode = MODULEMODE_SWCTRL,
21812 },
21813 },
21814 @@ -741,7 +700,6 @@ static struct omap_hwmod am33xx_ecap1_hw
21815 .name = "ecap1",
21816 .class = &am33xx_ecap_hwmod_class,
21817 .clkdm_name = "l4ls_clkdm",
21818 - .main_clk = "l4ls_gclk",
21819 };
21820
21821 /* eqep1 */
21822 @@ -757,7 +715,6 @@ static struct omap_hwmod am33xx_ehrpwm1_
21823 .name = "ehrpwm1",
21824 .class = &am33xx_ehrpwm_hwmod_class,
21825 .clkdm_name = "l4ls_clkdm",
21826 - .main_clk = "l4ls_gclk",
21827 };
21828
21829 /* epwmss2 */
21830 @@ -765,10 +722,8 @@ static struct omap_hwmod am33xx_epwmss2_
21831 .name = "epwmss2",
21832 .class = &am33xx_epwmss_hwmod_class,
21833 .clkdm_name = "l4ls_clkdm",
21834 - .main_clk = "l4ls_gclk",
21835 .prcm = {
21836 .omap4 = {
21837 - .clkctrl_offs = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
21838 .modulemode = MODULEMODE_SWCTRL,
21839 },
21840 },
21841 @@ -779,7 +734,6 @@ static struct omap_hwmod am33xx_ecap2_hw
21842 .name = "ecap2",
21843 .class = &am33xx_ecap_hwmod_class,
21844 .clkdm_name = "l4ls_clkdm",
21845 - .main_clk = "l4ls_gclk",
21846 };
21847
21848 /* eqep2 */
21849 @@ -795,7 +749,6 @@ static struct omap_hwmod am33xx_ehrpwm2_
21850 .name = "ehrpwm2",
21851 .class = &am33xx_ehrpwm_hwmod_class,
21852 .clkdm_name = "l4ls_clkdm",
21853 - .main_clk = "l4ls_gclk",
21854 };
21855
21856 /*
21857 @@ -825,90 +778,62 @@ static struct omap_gpio_dev_attr gpio_de
21858 };
21859
21860 /* gpio0 */
21861 -static struct omap_hwmod_opt_clk gpio0_opt_clks[] = {
21862 - { .role = "dbclk", .clk = "gpio0_dbclk" },
21863 -};
21864
21865 static struct omap_hwmod am33xx_gpio0_hwmod = {
21866 .name = "gpio1",
21867 .class = &am33xx_gpio_hwmod_class,
21868 .clkdm_name = "l4_wkup_clkdm",
21869 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
21870 - .main_clk = "dpll_core_m4_div2_ck",
21871 .prcm = {
21872 .omap4 = {
21873 - .clkctrl_offs = AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET,
21874 .modulemode = MODULEMODE_SWCTRL,
21875 },
21876 },
21877 - .opt_clks = gpio0_opt_clks,
21878 - .opt_clks_cnt = ARRAY_SIZE(gpio0_opt_clks),
21879 .dev_attr = &gpio_dev_attr,
21880 };
21881
21882 /* gpio1 */
21883 -static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
21884 - { .role = "dbclk", .clk = "gpio1_dbclk" },
21885 -};
21886
21887 static struct omap_hwmod am33xx_gpio1_hwmod = {
21888 .name = "gpio2",
21889 .class = &am33xx_gpio_hwmod_class,
21890 .clkdm_name = "l4ls_clkdm",
21891 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
21892 - .main_clk = "l4ls_gclk",
21893 .prcm = {
21894 .omap4 = {
21895 - .clkctrl_offs = AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET,
21896 .modulemode = MODULEMODE_SWCTRL,
21897 },
21898 },
21899 - .opt_clks = gpio1_opt_clks,
21900 - .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
21901 .dev_attr = &gpio_dev_attr,
21902 };
21903
21904 /* gpio2 */
21905 -static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
21906 - { .role = "dbclk", .clk = "gpio2_dbclk" },
21907 -};
21908
21909 static struct omap_hwmod am33xx_gpio2_hwmod = {
21910 .name = "gpio3",
21911 .class = &am33xx_gpio_hwmod_class,
21912 .clkdm_name = "l4ls_clkdm",
21913 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
21914 - .main_clk = "l4ls_gclk",
21915 .prcm = {
21916 .omap4 = {
21917 - .clkctrl_offs = AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET,
21918 .modulemode = MODULEMODE_SWCTRL,
21919 },
21920 },
21921 - .opt_clks = gpio2_opt_clks,
21922 - .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
21923 .dev_attr = &gpio_dev_attr,
21924 };
21925
21926 /* gpio3 */
21927 -static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
21928 - { .role = "dbclk", .clk = "gpio3_dbclk" },
21929 -};
21930
21931 static struct omap_hwmod am33xx_gpio3_hwmod = {
21932 .name = "gpio4",
21933 .class = &am33xx_gpio_hwmod_class,
21934 .clkdm_name = "l4ls_clkdm",
21935 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
21936 - .main_clk = "l4ls_gclk",
21937 .prcm = {
21938 .omap4 = {
21939 - .clkctrl_offs = AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET,
21940 .modulemode = MODULEMODE_SWCTRL,
21941 },
21942 },
21943 - .opt_clks = gpio3_opt_clks,
21944 - .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
21945 .dev_attr = &gpio_dev_attr,
21946 };
21947
21948 @@ -932,11 +857,9 @@ static struct omap_hwmod am33xx_gpmc_hwm
21949 .name = "gpmc",
21950 .class = &am33xx_gpmc_hwmod_class,
21951 .clkdm_name = "l3s_clkdm",
21952 - .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
21953 - .main_clk = "l3s_gclk",
21954 + .flags = HWMOD_INIT_NO_RESET,
21955 .prcm = {
21956 .omap4 = {
21957 - .clkctrl_offs = AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET,
21958 .modulemode = MODULEMODE_SWCTRL,
21959 },
21960 },
21961 @@ -971,10 +894,8 @@ static struct omap_hwmod am33xx_i2c1_hwm
21962 .class = &i2c_class,
21963 .clkdm_name = "l4_wkup_clkdm",
21964 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
21965 - .main_clk = "dpll_per_m2_div4_wkupdm_ck",
21966 .prcm = {
21967 .omap4 = {
21968 - .clkctrl_offs = AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET,
21969 .modulemode = MODULEMODE_SWCTRL,
21970 },
21971 },
21972 @@ -987,10 +908,8 @@ static struct omap_hwmod am33xx_i2c2_hwm
21973 .class = &i2c_class,
21974 .clkdm_name = "l4ls_clkdm",
21975 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
21976 - .main_clk = "dpll_per_m2_div4_ck",
21977 .prcm = {
21978 .omap4 = {
21979 - .clkctrl_offs = AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET,
21980 .modulemode = MODULEMODE_SWCTRL,
21981 },
21982 },
21983 @@ -1003,10 +922,8 @@ static struct omap_hwmod am33xx_i2c3_hwm
21984 .class = &i2c_class,
21985 .clkdm_name = "l4ls_clkdm",
21986 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
21987 - .main_clk = "dpll_per_m2_div4_ck",
21988 .prcm = {
21989 .omap4 = {
21990 - .clkctrl_offs = AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET,
21991 .modulemode = MODULEMODE_SWCTRL,
21992 },
21993 },
21994 @@ -1065,10 +982,8 @@ static struct omap_hwmod am33xx_mailbox_
21995 .name = "mailbox",
21996 .class = &am33xx_mailbox_hwmod_class,
21997 .clkdm_name = "l4ls_clkdm",
21998 - .main_clk = "l4ls_gclk",
21999 .prcm = {
22000 .omap4 = {
22001 - .clkctrl_offs = AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET,
22002 .modulemode = MODULEMODE_SWCTRL,
22003 },
22004 },
22005 @@ -1098,7 +1013,6 @@ static struct omap_hwmod am33xx_mcasp0_h
22006 .main_clk = "mcasp0_fck",
22007 .prcm = {
22008 .omap4 = {
22009 - .clkctrl_offs = AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET,
22010 .modulemode = MODULEMODE_SWCTRL,
22011 },
22012 },
22013 @@ -1112,7 +1026,6 @@ static struct omap_hwmod am33xx_mcasp1_h
22014 .main_clk = "mcasp1_fck",
22015 .prcm = {
22016 .omap4 = {
22017 - .clkctrl_offs = AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET,
22018 .modulemode = MODULEMODE_SWCTRL,
22019 },
22020 },
22021 @@ -1147,7 +1060,6 @@ static struct omap_hwmod am33xx_mmc0_hwm
22022 .main_clk = "mmc_clk",
22023 .prcm = {
22024 .omap4 = {
22025 - .clkctrl_offs = AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET,
22026 .modulemode = MODULEMODE_SWCTRL,
22027 },
22028 },
22029 @@ -1166,7 +1078,6 @@ static struct omap_hwmod am33xx_mmc1_hwm
22030 .main_clk = "mmc_clk",
22031 .prcm = {
22032 .omap4 = {
22033 - .clkctrl_offs = AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET,
22034 .modulemode = MODULEMODE_SWCTRL,
22035 },
22036 },
22037 @@ -1184,7 +1095,6 @@ static struct omap_hwmod am33xx_mmc2_hwm
22038 .main_clk = "mmc_clk",
22039 .prcm = {
22040 .omap4 = {
22041 - .clkctrl_offs = AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET,
22042 .modulemode = MODULEMODE_SWCTRL,
22043 },
22044 },
22045 @@ -1213,10 +1123,8 @@ static struct omap_hwmod am33xx_rtc_hwmo
22046 .name = "rtc",
22047 .class = &am33xx_rtc_hwmod_class,
22048 .clkdm_name = "l4_rtc_clkdm",
22049 - .main_clk = "clk_32768_ck",
22050 .prcm = {
22051 .omap4 = {
22052 - .clkctrl_offs = AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET,
22053 .modulemode = MODULEMODE_SWCTRL,
22054 },
22055 },
22056 @@ -1248,10 +1156,8 @@ static struct omap_hwmod am33xx_spi0_hwm
22057 .name = "spi0",
22058 .class = &am33xx_spi_hwmod_class,
22059 .clkdm_name = "l4ls_clkdm",
22060 - .main_clk = "dpll_per_m2_div4_ck",
22061 .prcm = {
22062 .omap4 = {
22063 - .clkctrl_offs = AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET,
22064 .modulemode = MODULEMODE_SWCTRL,
22065 },
22066 },
22067 @@ -1263,10 +1169,8 @@ static struct omap_hwmod am33xx_spi1_hwm
22068 .name = "spi1",
22069 .class = &am33xx_spi_hwmod_class,
22070 .clkdm_name = "l4ls_clkdm",
22071 - .main_clk = "dpll_per_m2_div4_ck",
22072 .prcm = {
22073 .omap4 = {
22074 - .clkctrl_offs = AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET,
22075 .modulemode = MODULEMODE_SWCTRL,
22076 },
22077 },
22078 @@ -1289,12 +1193,119 @@ static struct omap_hwmod am33xx_spinlock
22079 .main_clk = "l4ls_gclk",
22080 .prcm = {
22081 .omap4 = {
22082 - .clkctrl_offs = AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET,
22083 .modulemode = MODULEMODE_SWCTRL,
22084 },
22085 },
22086 };
22087
22088 +static struct omap_hwmod_class_sysconfig am43xx_qspi_sysc = {
22089 + .sysc_offs = 0x0010,
22090 + .sysc_flags = SYSC_HAS_SIDLEMODE,
22091 + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
22092 + SIDLE_SMART_WKUP),
22093 + .sysc_fields = &omap_hwmod_sysc_type2,
22094 +};
22095 +
22096 +static struct omap_hwmod_class am43xx_qspi_hwmod_class = {
22097 + .name = "qspi",
22098 + .sysc = &am43xx_qspi_sysc,
22099 +};
22100 +
22101 +static struct omap_hwmod am43xx_qspi_hwmod = {
22102 + .name = "qspi",
22103 + .class = &am43xx_qspi_hwmod_class,
22104 + .clkdm_name = "l3s_clkdm",
22105 + .main_clk = "l3s_gclk",
22106 + .prcm = {
22107 + .omap4 = {
22108 + .clkctrl_offs = AM43XX_CM_PER_QSPI_CLKCTRL_OFFSET,
22109 + .modulemode = MODULEMODE_SWCTRL,
22110 + },
22111 + },
22112 +};
22113 +
22114 +/* 'ocp2scp' class
22115 + *
22116 + */
22117 +
22118 +
22119 +static struct omap_hwmod_class am43xx_ocp2scp_hwmod_class = {
22120 + .name = "ocp2scp",
22121 +};
22122 +
22123 +/* ocp2scp0 */
22124 +static struct omap_hwmod am43xx_ocp2scp0_hwmod = {
22125 + .name = "ocp2scp0",
22126 + .class = &am43xx_ocp2scp_hwmod_class,
22127 + .clkdm_name = "l4ls_clkdm",
22128 + .main_clk = "l4ls_gclk",
22129 + .prcm = {
22130 + .omap4 = {
22131 + .clkctrl_offs = AM43XX_CM_PER_USBPHYOCP2SCP0_CLKCTRL_OFFSET,
22132 + .modulemode = MODULEMODE_SWCTRL,
22133 + },
22134 + },
22135 +};
22136 +
22137 +/* ocp2scp1 */
22138 +static struct omap_hwmod am43xx_ocp2scp1_hwmod = {
22139 + .name = "ocp2scp1",
22140 + .class = &am43xx_ocp2scp_hwmod_class,
22141 + .clkdm_name = "l4ls_clkdm",
22142 + .main_clk = "l4ls_gclk",
22143 + .prcm = {
22144 + .omap4 = {
22145 + .clkctrl_offs = AM43XX_CM_PER_USBPHYOCP2SCP1_CLKCTRL_OFFSET,
22146 + .modulemode = MODULEMODE_SWCTRL,
22147 + },
22148 + },
22149 +};
22150 +
22151 +/* 'usb_otg_ss' class */
22152 +static struct omap_hwmod_class_sysconfig am43xx_usb_otg_ss_sysc = {
22153 + .rev_offs = 0x0000,
22154 + .sysc_offs = 0x0010,
22155 + .sysc_flags = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
22156 + SYSC_HAS_SIDLEMODE),
22157 + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
22158 + SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
22159 + MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
22160 + .sysc_fields = &omap_hwmod_sysc_type2,
22161 +};
22162 +
22163 +static struct omap_hwmod_class am43xx_usb_otg_ss_hwmod_class = {
22164 + .name = "usb_otg_ss",
22165 + .sysc = &am43xx_usb_otg_ss_sysc,
22166 +};
22167 +
22168 +/* usb_otg_ss0 */
22169 +static struct omap_hwmod am43xx_usb_otg_ss0_hwmod = {
22170 + .name = "usb_otg_ss0",
22171 + .class = &am43xx_usb_otg_ss_hwmod_class,
22172 + .clkdm_name = "l3s_clkdm",
22173 + .main_clk = "l3s_gclk",
22174 + .prcm = {
22175 + .omap4 = {
22176 + .clkctrl_offs = AM43XX_CM_PER_USB_OTG_SS0_CLKCTRL_OFFSET,
22177 + .modulemode = MODULEMODE_SWCTRL,
22178 + },
22179 + },
22180 +};
22181 +
22182 +/* usb_otg_ss1 */
22183 +static struct omap_hwmod am43xx_usb_otg_ss1_hwmod = {
22184 + .name = "usb_otg_ss1",
22185 + .class = &am43xx_usb_otg_ss_hwmod_class,
22186 + .clkdm_name = "l3s_clkdm",
22187 + .main_clk = "l3s_gclk",
22188 + .prcm = {
22189 + .omap4 = {
22190 + .clkctrl_offs = AM43XX_CM_PER_USB_OTG_SS1_CLKCTRL_OFFSET,
22191 + .modulemode = MODULEMODE_SWCTRL,
22192 + },
22193 + },
22194 +};
22195 +
22196 /* 'timer 2-7' class */
22197 static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = {
22198 .rev_offs = 0x0000,
22199 @@ -1332,10 +1343,8 @@ static struct omap_hwmod am33xx_timer1_h
22200 .name = "timer1",
22201 .class = &am33xx_timer1ms_hwmod_class,
22202 .clkdm_name = "l4_wkup_clkdm",
22203 - .main_clk = "timer1_fck",
22204 .prcm = {
22205 .omap4 = {
22206 - .clkctrl_offs = AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
22207 .modulemode = MODULEMODE_SWCTRL,
22208 },
22209 },
22210 @@ -1345,10 +1354,8 @@ static struct omap_hwmod am33xx_timer2_h
22211 .name = "timer2",
22212 .class = &am33xx_timer_hwmod_class,
22213 .clkdm_name = "l4ls_clkdm",
22214 - .main_clk = "timer2_fck",
22215 .prcm = {
22216 .omap4 = {
22217 - .clkctrl_offs = AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET,
22218 .modulemode = MODULEMODE_SWCTRL,
22219 },
22220 },
22221 @@ -1358,10 +1365,8 @@ static struct omap_hwmod am33xx_timer3_h
22222 .name = "timer3",
22223 .class = &am33xx_timer_hwmod_class,
22224 .clkdm_name = "l4ls_clkdm",
22225 - .main_clk = "timer3_fck",
22226 .prcm = {
22227 .omap4 = {
22228 - .clkctrl_offs = AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET,
22229 .modulemode = MODULEMODE_SWCTRL,
22230 },
22231 },
22232 @@ -1371,10 +1376,8 @@ static struct omap_hwmod am33xx_timer4_h
22233 .name = "timer4",
22234 .class = &am33xx_timer_hwmod_class,
22235 .clkdm_name = "l4ls_clkdm",
22236 - .main_clk = "timer4_fck",
22237 .prcm = {
22238 .omap4 = {
22239 - .clkctrl_offs = AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET,
22240 .modulemode = MODULEMODE_SWCTRL,
22241 },
22242 },
22243 @@ -1384,10 +1387,8 @@ static struct omap_hwmod am33xx_timer5_h
22244 .name = "timer5",
22245 .class = &am33xx_timer_hwmod_class,
22246 .clkdm_name = "l4ls_clkdm",
22247 - .main_clk = "timer5_fck",
22248 .prcm = {
22249 .omap4 = {
22250 - .clkctrl_offs = AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET,
22251 .modulemode = MODULEMODE_SWCTRL,
22252 },
22253 },
22254 @@ -1397,10 +1398,8 @@ static struct omap_hwmod am33xx_timer6_h
22255 .name = "timer6",
22256 .class = &am33xx_timer_hwmod_class,
22257 .clkdm_name = "l4ls_clkdm",
22258 - .main_clk = "timer6_fck",
22259 .prcm = {
22260 .omap4 = {
22261 - .clkctrl_offs = AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET,
22262 .modulemode = MODULEMODE_SWCTRL,
22263 },
22264 },
22265 @@ -1410,10 +1409,8 @@ static struct omap_hwmod am33xx_timer7_h
22266 .name = "timer7",
22267 .class = &am33xx_timer_hwmod_class,
22268 .clkdm_name = "l4ls_clkdm",
22269 - .main_clk = "timer7_fck",
22270 .prcm = {
22271 .omap4 = {
22272 - .clkctrl_offs = AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET,
22273 .modulemode = MODULEMODE_SWCTRL,
22274 },
22275 },
22276 @@ -1431,7 +1428,6 @@ static struct omap_hwmod am33xx_tpcc_hwm
22277 .main_clk = "l3_gclk",
22278 .prcm = {
22279 .omap4 = {
22280 - .clkctrl_offs = AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET,
22281 .modulemode = MODULEMODE_SWCTRL,
22282 },
22283 },
22284 @@ -1457,11 +1453,11 @@ static struct omap_hwmod am33xx_tptc0_hw
22285 .name = "tptc0",
22286 .class = &am33xx_tptc_hwmod_class,
22287 .clkdm_name = "l3_clkdm",
22288 - .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
22289 + .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
22290 + HWMOD_FORCE_MSTANDBY_REPEATED,
22291 .main_clk = "l3_gclk",
22292 .prcm = {
22293 .omap4 = {
22294 - .clkctrl_offs = AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET,
22295 .modulemode = MODULEMODE_SWCTRL,
22296 },
22297 },
22298 @@ -1472,11 +1468,11 @@ static struct omap_hwmod am33xx_tptc1_hw
22299 .name = "tptc1",
22300 .class = &am33xx_tptc_hwmod_class,
22301 .clkdm_name = "l3_clkdm",
22302 - .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
22303 + .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
22304 + HWMOD_FORCE_MSTANDBY_REPEATED),
22305 .main_clk = "l3_gclk",
22306 .prcm = {
22307 .omap4 = {
22308 - .clkctrl_offs = AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET,
22309 .modulemode = MODULEMODE_SWCTRL,
22310 },
22311 },
22312 @@ -1487,11 +1483,11 @@ static struct omap_hwmod am33xx_tptc2_hw
22313 .name = "tptc2",
22314 .class = &am33xx_tptc_hwmod_class,
22315 .clkdm_name = "l3_clkdm",
22316 - .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
22317 + .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
22318 + HWMOD_FORCE_MSTANDBY_REPEATED),
22319 .main_clk = "l3_gclk",
22320 .prcm = {
22321 .omap4 = {
22322 - .clkctrl_offs = AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET,
22323 .modulemode = MODULEMODE_SWCTRL,
22324 },
22325 },
22326 @@ -1520,10 +1516,8 @@ static struct omap_hwmod am33xx_uart1_hw
22327 .class = &uart_class,
22328 .clkdm_name = "l4_wkup_clkdm",
22329 .flags = DEBUG_AM33XXUART1_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
22330 - .main_clk = "dpll_per_m2_div4_wkupdm_ck",
22331 .prcm = {
22332 .omap4 = {
22333 - .clkctrl_offs = AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET,
22334 .modulemode = MODULEMODE_SWCTRL,
22335 },
22336 },
22337 @@ -1534,10 +1528,8 @@ static struct omap_hwmod am33xx_uart2_hw
22338 .class = &uart_class,
22339 .clkdm_name = "l4ls_clkdm",
22340 .flags = HWMOD_SWSUP_SIDLE_ACT,
22341 - .main_clk = "dpll_per_m2_div4_ck",
22342 .prcm = {
22343 .omap4 = {
22344 - .clkctrl_offs = AM33XX_CM_PER_UART1_CLKCTRL_OFFSET,
22345 .modulemode = MODULEMODE_SWCTRL,
22346 },
22347 },
22348 @@ -1549,10 +1541,8 @@ static struct omap_hwmod am33xx_uart3_hw
22349 .class = &uart_class,
22350 .clkdm_name = "l4ls_clkdm",
22351 .flags = HWMOD_SWSUP_SIDLE_ACT,
22352 - .main_clk = "dpll_per_m2_div4_ck",
22353 .prcm = {
22354 .omap4 = {
22355 - .clkctrl_offs = AM33XX_CM_PER_UART2_CLKCTRL_OFFSET,
22356 .modulemode = MODULEMODE_SWCTRL,
22357 },
22358 },
22359 @@ -1563,10 +1553,8 @@ static struct omap_hwmod am33xx_uart4_hw
22360 .class = &uart_class,
22361 .clkdm_name = "l4ls_clkdm",
22362 .flags = HWMOD_SWSUP_SIDLE_ACT,
22363 - .main_clk = "dpll_per_m2_div4_ck",
22364 .prcm = {
22365 .omap4 = {
22366 - .clkctrl_offs = AM33XX_CM_PER_UART3_CLKCTRL_OFFSET,
22367 .modulemode = MODULEMODE_SWCTRL,
22368 },
22369 },
22370 @@ -1577,10 +1565,8 @@ static struct omap_hwmod am33xx_uart5_hw
22371 .class = &uart_class,
22372 .clkdm_name = "l4ls_clkdm",
22373 .flags = HWMOD_SWSUP_SIDLE_ACT,
22374 - .main_clk = "dpll_per_m2_div4_ck",
22375 .prcm = {
22376 .omap4 = {
22377 - .clkctrl_offs = AM33XX_CM_PER_UART4_CLKCTRL_OFFSET,
22378 .modulemode = MODULEMODE_SWCTRL,
22379 },
22380 },
22381 @@ -1591,10 +1577,8 @@ static struct omap_hwmod am33xx_uart6_hw
22382 .class = &uart_class,
22383 .clkdm_name = "l4ls_clkdm",
22384 .flags = HWMOD_SWSUP_SIDLE_ACT,
22385 - .main_clk = "dpll_per_m2_div4_ck",
22386 .prcm = {
22387 .omap4 = {
22388 - .clkctrl_offs = AM33XX_CM_PER_UART5_CLKCTRL_OFFSET,
22389 .modulemode = MODULEMODE_SWCTRL,
22390 },
22391 },
22392 @@ -1627,10 +1611,8 @@ static struct omap_hwmod am33xx_wd_timer
22393 .class = &am33xx_wd_timer_hwmod_class,
22394 .clkdm_name = "l4_wkup_clkdm",
22395 .flags = HWMOD_SWSUP_SIDLE,
22396 - .main_clk = "wdt1_fck",
22397 .prcm = {
22398 .omap4 = {
22399 - .clkctrl_offs = AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET,
22400 .modulemode = MODULEMODE_SWCTRL,
22401 },
22402 },
22403 @@ -1658,8 +1640,8 @@ static struct omap_hwmod am33xx_usbss_hw
22404 .name = "usb_otg_hs",
22405 .class = &am33xx_usbotg_class,
22406 .clkdm_name = "l3s_clkdm",
22407 - .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
22408 - .main_clk = "usbotg_fck",
22409 + .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
22410 + HWMOD_FORCE_MSTANDBY_REPEATED,
22411 .prcm = {
22412 .omap4 = {
22413 .clkctrl_offs = AM33XX_CM_PER_USB0_CLKCTRL_OFFSET,
22414 @@ -1668,6 +1650,272 @@ static struct omap_hwmod am33xx_usbss_hw
22415 },
22416 };
22417
22418 +static struct omap_hwmod_class_sysconfig am43xx_synctimer_sysc = {
22419 + .rev_offs = 0x0,
22420 + .sysc_offs = 0x4,
22421 + .sysc_flags = SYSC_HAS_SIDLEMODE,
22422 + .idlemodes = (SIDLE_FORCE | SIDLE_NO),
22423 + .sysc_fields = &omap_hwmod_sysc_type1,
22424 +};
22425 +
22426 +static struct omap_hwmod_class am43xx_synctimer_hwmod_class = {
22427 + .name = "synctimer",
22428 + .sysc = &am43xx_synctimer_sysc,
22429 +};
22430 +
22431 +static struct omap_hwmod am43xx_synctimer_hwmod = {
22432 + .name = "counter_32k",
22433 + .class = &am43xx_synctimer_hwmod_class,
22434 + .clkdm_name = "l4_wkup_aon_clkdm",
22435 + .flags = HWMOD_SWSUP_SIDLE,
22436 + .prcm = {
22437 + .omap4 = {
22438 + .clkctrl_offs = AM43XX_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
22439 + .modulemode = MODULEMODE_SWCTRL,
22440 + },
22441 + },
22442 +};
22443 +
22444 +static struct omap_hwmod am43xx_timer8_hwmod = {
22445 + .name = "timer8",
22446 + .class = &am33xx_timer_hwmod_class,
22447 + .clkdm_name = "l4ls_clkdm",
22448 + .prcm = {
22449 + .omap4 = {
22450 + .clkctrl_offs = AM43XX_CM_PER_TIMER8_CLKCTRL_OFFSET,
22451 + .modulemode = MODULEMODE_SWCTRL,
22452 + },
22453 + },
22454 +};
22455 +
22456 +static struct omap_hwmod am43xx_timer9_hwmod = {
22457 + .name = "timer9",
22458 + .class = &am33xx_timer_hwmod_class,
22459 + .clkdm_name = "l4ls_clkdm",
22460 + .prcm = {
22461 + .omap4 = {
22462 + .clkctrl_offs = AM43XX_CM_PER_TIMER9_CLKCTRL_OFFSET,
22463 + .modulemode = MODULEMODE_SWCTRL,
22464 + },
22465 + },
22466 +};
22467 +
22468 +static struct omap_hwmod am43xx_timer10_hwmod = {
22469 + .name = "timer10",
22470 + .class = &am33xx_timer_hwmod_class,
22471 + .clkdm_name = "l4ls_clkdm",
22472 + .prcm = {
22473 + .omap4 = {
22474 + .clkctrl_offs = AM43XX_CM_PER_TIMER10_CLKCTRL_OFFSET,
22475 + .modulemode = MODULEMODE_SWCTRL,
22476 + },
22477 + },
22478 +};
22479 +
22480 +static struct omap_hwmod am43xx_timer11_hwmod = {
22481 + .name = "timer11",
22482 + .class = &am33xx_timer_hwmod_class,
22483 + .clkdm_name = "l4ls_clkdm",
22484 + .prcm = {
22485 + .omap4 = {
22486 + .clkctrl_offs = AM43XX_CM_PER_TIMER11_CLKCTRL_OFFSET,
22487 + .modulemode = MODULEMODE_SWCTRL,
22488 + },
22489 + },
22490 +};
22491 +
22492 +static struct omap_hwmod am43xx_epwmss3_hwmod = {
22493 + .name = "epwmss3",
22494 + .class = &am33xx_epwmss_hwmod_class,
22495 + .clkdm_name = "l4ls_clkdm",
22496 + .prcm = {
22497 + .omap4 = {
22498 + .clkctrl_offs = AM43XX_CM_PER_EPWMSS3_CLKCTRL_OFFSET,
22499 + .modulemode = MODULEMODE_SWCTRL,
22500 + },
22501 + },
22502 +};
22503 +
22504 +static struct omap_hwmod am43xx_ehrpwm3_hwmod = {
22505 + .name = "ehrpwm3",
22506 + .class = &am33xx_ehrpwm_hwmod_class,
22507 + .clkdm_name = "l4ls_clkdm",
22508 +};
22509 +
22510 +static struct omap_hwmod am43xx_epwmss4_hwmod = {
22511 + .name = "epwmss4",
22512 + .class = &am33xx_epwmss_hwmod_class,
22513 + .clkdm_name = "l4ls_clkdm",
22514 + .prcm = {
22515 + .omap4 = {
22516 + .clkctrl_offs = AM43XX_CM_PER_EPWMSS4_CLKCTRL_OFFSET,
22517 + .modulemode = MODULEMODE_SWCTRL,
22518 + },
22519 + },
22520 +};
22521 +
22522 +static struct omap_hwmod am43xx_ehrpwm4_hwmod = {
22523 + .name = "ehrpwm4",
22524 + .class = &am33xx_ehrpwm_hwmod_class,
22525 + .clkdm_name = "l4ls_clkdm",
22526 +};
22527 +
22528 +static struct omap_hwmod am43xx_epwmss5_hwmod = {
22529 + .name = "epwmss5",
22530 + .class = &am33xx_epwmss_hwmod_class,
22531 + .clkdm_name = "l4ls_clkdm",
22532 + .prcm = {
22533 + .omap4 = {
22534 + .clkctrl_offs = AM43XX_CM_PER_EPWMSS5_CLKCTRL_OFFSET,
22535 + .modulemode = MODULEMODE_SWCTRL,
22536 + },
22537 + },
22538 +};
22539 +
22540 +static struct omap_hwmod am43xx_ehrpwm5_hwmod = {
22541 + .name = "ehrpwm5",
22542 + .class = &am33xx_ehrpwm_hwmod_class,
22543 + .clkdm_name = "l4ls_clkdm",
22544 +};
22545 +
22546 +static struct omap_hwmod am43xx_spi2_hwmod = {
22547 + .name = "spi2",
22548 + .class = &am33xx_spi_hwmod_class,
22549 + .clkdm_name = "l4ls_clkdm",
22550 + .prcm = {
22551 + .omap4 = {
22552 + .clkctrl_offs = AM43XX_CM_PER_SPI2_CLKCTRL_OFFSET,
22553 + .modulemode = MODULEMODE_SWCTRL,
22554 + },
22555 + },
22556 + .dev_attr = &mcspi_attrib,
22557 +};
22558 +
22559 +static struct omap_hwmod am43xx_spi3_hwmod = {
22560 + .name = "spi3",
22561 + .class = &am33xx_spi_hwmod_class,
22562 + .clkdm_name = "l4ls_clkdm",
22563 + .prcm = {
22564 + .omap4 = {
22565 + .clkctrl_offs = AM43XX_CM_PER_SPI3_CLKCTRL_OFFSET,
22566 + .modulemode = MODULEMODE_SWCTRL,
22567 + },
22568 + },
22569 + .dev_attr = &mcspi_attrib,
22570 +};
22571 +
22572 +static struct omap_hwmod am43xx_spi4_hwmod = {
22573 + .name = "spi4",
22574 + .class = &am33xx_spi_hwmod_class,
22575 + .clkdm_name = "l4ls_clkdm",
22576 + .prcm = {
22577 + .omap4 = {
22578 + .clkctrl_offs = AM43XX_CM_PER_SPI4_CLKCTRL_OFFSET,
22579 + .modulemode = MODULEMODE_SWCTRL,
22580 + },
22581 + },
22582 + .dev_attr = &mcspi_attrib,
22583 +};
22584 +
22585 +static struct omap_hwmod am43xx_gpio4_hwmod = {
22586 + .name = "gpio5",
22587 + .class = &am33xx_gpio_hwmod_class,
22588 + .clkdm_name = "l4ls_clkdm",
22589 + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
22590 + .prcm = {
22591 + .omap4 = {
22592 + .clkctrl_offs = AM43XX_CM_PER_GPIO4_CLKCTRL_OFFSET,
22593 + .modulemode = MODULEMODE_SWCTRL,
22594 + },
22595 + },
22596 + .dev_attr = &gpio_dev_attr,
22597 +};
22598 +
22599 +static struct omap_hwmod am43xx_gpio5_hwmod = {
22600 + .name = "gpio6",
22601 + .class = &am33xx_gpio_hwmod_class,
22602 + .clkdm_name = "l4ls_clkdm",
22603 + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
22604 + .prcm = {
22605 + .omap4 = {
22606 + .clkctrl_offs = AM43XX_CM_PER_GPIO5_CLKCTRL_OFFSET,
22607 + .modulemode = MODULEMODE_SWCTRL,
22608 + },
22609 + },
22610 + .dev_attr = &gpio_dev_attr,
22611 +};
22612 +
22613 +/* Display sub system - DSS */
22614 +
22615 +static struct omap_hwmod_dma_info am43xx_dss_sdma_chs[] = {
22616 + { .name = "dispc", .dma_req = 5 },
22617 + { .dma_req = -1 },
22618 +};
22619 +
22620 +struct omap_dss_dispc_dev_attr am43xx_dss_dispc_dev_attr = {
22621 + .manager_count = 1,
22622 + .has_framedonetv_irq = 0
22623 +};
22624 +
22625 +
22626 +static struct omap_hwmod_class_sysconfig am43xx_dispc_sysc = {
22627 + .rev_offs = 0x0000,
22628 + .sysc_offs = 0x0010,
22629 + .syss_offs = 0x0014,
22630 + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
22631 + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
22632 + .sysc_fields = &omap_hwmod_sysc_type1,
22633 +};
22634 +
22635 +static struct omap_hwmod_class am43xx_dispc_hwmod_class = {
22636 + .name = "dispc",
22637 + .sysc = &am43xx_dispc_sysc,
22638 +};
22639 +
22640 +
22641 +
22642 +static struct omap_hwmod am43xx_dss_core_hwmod = {
22643 + .name = "dss_core",
22644 + .class = &omap2_dss_hwmod_class,
22645 + .clkdm_name = "dss_clkdm",
22646 + .main_clk = "disp_clk",
22647 + .sdma_reqs = am43xx_dss_sdma_chs,
22648 + .prcm = {
22649 + .omap4 = {
22650 + .clkctrl_offs = AM43XX_CM_PER_DSS_CLKCTRL_OFFSET,
22651 + .modulemode = MODULEMODE_SWCTRL,
22652 + },
22653 + },
22654 +};
22655 +
22656 +/* display controller -dispc*/
22657 +
22658 +static struct omap_hwmod am43xx_dss_dispc_hwmod = {
22659 + .name = "dss_dispc",
22660 + .class = &am43xx_dispc_hwmod_class,
22661 + .clkdm_name = "dss_clkdm",
22662 + .main_clk = "disp_clk",
22663 + .prcm = {
22664 + .omap4 = {
22665 + .clkctrl_offs = AM43XX_CM_PER_DSS_CLKCTRL_OFFSET,
22666 + },
22667 + },
22668 + .dev_attr = &am43xx_dss_dispc_dev_attr,
22669 +};
22670 +
22671 +/*RFBI*/
22672 +
22673 +static struct omap_hwmod am43xx_dss_rfbi_hwmod = {
22674 + .name = "dss_rfbi",
22675 + .class = &omap2_rfbi_hwmod_class,
22676 + .clkdm_name = "dss_clkdm",
22677 + .main_clk = "disp_clk",
22678 + .prcm = {
22679 + .omap4 = {
22680 + .clkctrl_offs = AM43XX_CM_PER_DSS_CLKCTRL_OFFSET,
22681 + },
22682 + },
22683 +};
22684
22685 /*
22686 * Interfaces
22687 @@ -1766,7 +2014,6 @@ static struct omap_hwmod_ocp_if am33xx_p
22688 static struct omap_hwmod_ocp_if am33xx_wkup_m3__l4_wkup = {
22689 .master = &am33xx_wkup_m3_hwmod,
22690 .slave = &am33xx_l4_wkup_hwmod,
22691 - .clk = "dpll_core_m4_div2_ck",
22692 .user = OCP_USER_MPU | OCP_USER_SDMA,
22693 };
22694
22695 @@ -1782,7 +2029,6 @@ static struct omap_hwmod_ocp_if am33xx_g
22696 static struct omap_hwmod_ocp_if am33xx_l4_wkup__wkup_m3 = {
22697 .master = &am33xx_l4_wkup_hwmod,
22698 .slave = &am33xx_wkup_m3_hwmod,
22699 - .clk = "dpll_core_m4_div2_ck",
22700 .user = OCP_USER_MPU | OCP_USER_SDMA,
22701 };
22702
22703 @@ -1824,7 +2070,6 @@ static struct omap_hwmod_ocp_if am33xx_l
22704 static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex0 = {
22705 .master = &am33xx_l4_wkup_hwmod,
22706 .slave = &am33xx_smartreflex0_hwmod,
22707 - .clk = "dpll_core_m4_div2_ck",
22708 .user = OCP_USER_MPU,
22709 };
22710
22711 @@ -1832,7 +2077,6 @@ static struct omap_hwmod_ocp_if am33xx_l
22712 static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex1 = {
22713 .master = &am33xx_l4_wkup_hwmod,
22714 .slave = &am33xx_smartreflex1_hwmod,
22715 - .clk = "dpll_core_m4_div2_ck",
22716 .user = OCP_USER_MPU,
22717 };
22718
22719 @@ -1840,7 +2084,6 @@ static struct omap_hwmod_ocp_if am33xx_l
22720 static struct omap_hwmod_ocp_if am33xx_l4_wkup__control = {
22721 .master = &am33xx_l4_wkup_hwmod,
22722 .slave = &am33xx_control_hwmod,
22723 - .clk = "dpll_core_m4_div2_ck",
22724 .user = OCP_USER_MPU,
22725 };
22726
22727 @@ -1896,7 +2139,6 @@ static struct omap_hwmod_ocp_if am33xx_l
22728 static struct omap_hwmod_ocp_if am33xx_l4_wkup__i2c1 = {
22729 .master = &am33xx_l4_wkup_hwmod,
22730 .slave = &am33xx_i2c1_hwmod,
22731 - .clk = "dpll_core_m4_div2_ck",
22732 .user = OCP_USER_MPU,
22733 };
22734
22735 @@ -1904,7 +2146,6 @@ static struct omap_hwmod_ocp_if am33xx_l
22736 static struct omap_hwmod_ocp_if am33xx_l4_wkup__gpio0 = {
22737 .master = &am33xx_l4_wkup_hwmod,
22738 .slave = &am33xx_gpio0_hwmod,
22739 - .clk = "dpll_core_m4_div2_ck",
22740 .user = OCP_USER_MPU | OCP_USER_SDMA,
22741 };
22742
22743 @@ -2237,6 +2478,45 @@ static struct omap_hwmod_ocp_if am33xx_l
22744 .user = OCP_USER_MPU,
22745 };
22746
22747 +static struct omap_hwmod_ocp_if am43xx_l3_s__qspi = {
22748 + .master = &am33xx_l3_s_hwmod,
22749 + .slave = &am43xx_qspi_hwmod,
22750 + .clk = "l3s_gclk",
22751 + .user = OCP_USER_MPU | OCP_USER_SDMA,
22752 +};
22753 +
22754 +/* l3_main_1 -> usb_otg_ss0 */
22755 +static struct omap_hwmod_ocp_if am43xx_l3_s__usbotgss0 = {
22756 + .master = &am33xx_l3_s_hwmod,
22757 + .slave = &am43xx_usb_otg_ss0_hwmod,
22758 + .clk = "l3s_gclk",
22759 + .user = OCP_USER_MPU | OCP_USER_SDMA,
22760 +};
22761 +
22762 +/* l3_main_1 -> usb_otg_ss1 */
22763 +static struct omap_hwmod_ocp_if am43xx_l3_s__usbotgss1 = {
22764 + .master = &am33xx_l3_s_hwmod,
22765 + .slave = &am43xx_usb_otg_ss1_hwmod,
22766 + .clk = "l3s_gclk",
22767 + .user = OCP_USER_MPU | OCP_USER_SDMA,
22768 +};
22769 +
22770 +/* l4 ls -> ocp2scp0 */
22771 +static struct omap_hwmod_ocp_if am33xx_l4_ls__ocp2scp0 = {
22772 + .master = &am33xx_l4_ls_hwmod,
22773 + .slave = &am43xx_ocp2scp0_hwmod,
22774 + .clk = "l4ls_gclk",
22775 + .user = OCP_USER_MPU,
22776 +};
22777 +
22778 +/* l4 ls -> ocp2scp0 */
22779 +static struct omap_hwmod_ocp_if am33xx_l4_ls__ocp2scp1 = {
22780 + .master = &am33xx_l4_ls_hwmod,
22781 + .slave = &am43xx_ocp2scp1_hwmod,
22782 + .clk = "l4ls_gclk",
22783 + .user = OCP_USER_MPU,
22784 +};
22785 +
22786 /* l4 ls -> mcspi0 */
22787 static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi0 = {
22788 .master = &am33xx_l4_ls_hwmod,
22789 @@ -2257,7 +2537,6 @@ static struct omap_hwmod_ocp_if am33xx_l
22790 static struct omap_hwmod_ocp_if am33xx_l4_wkup__timer1 = {
22791 .master = &am33xx_l4_wkup_hwmod,
22792 .slave = &am33xx_timer1_hwmod,
22793 - .clk = "dpll_core_m4_div2_ck",
22794 .user = OCP_USER_MPU,
22795 };
22796
22797 @@ -2375,7 +2654,6 @@ static struct omap_hwmod_ocp_if am33xx_l
22798 static struct omap_hwmod_ocp_if am33xx_l4_wkup__uart1 = {
22799 .master = &am33xx_l4_wkup_hwmod,
22800 .slave = &am33xx_uart1_hwmod,
22801 - .clk = "dpll_core_m4_div2_ck",
22802 .user = OCP_USER_MPU,
22803 };
22804
22805 @@ -2423,7 +2701,6 @@ static struct omap_hwmod_ocp_if am33xx_l
22806 static struct omap_hwmod_ocp_if am33xx_l4_wkup__wd_timer1 = {
22807 .master = &am33xx_l4_wkup_hwmod,
22808 .slave = &am33xx_wd_timer1_hwmod,
22809 - .clk = "dpll_core_m4_div2_ck",
22810 .user = OCP_USER_MPU,
22811 };
22812
22813 @@ -2480,8 +2757,473 @@ static struct omap_hwmod_ocp_if am33xx_l
22814 .user = OCP_USER_MPU | OCP_USER_SDMA,
22815 };
22816
22817 +static struct omap_hwmod_ocp_if am33xx_l4_wkup__synctimer = {
22818 + .master = &am33xx_l4_wkup_hwmod,
22819 + .slave = &am43xx_synctimer_hwmod,
22820 + .clk = "sys_clkin_ck",
22821 + .user = OCP_USER_MPU,
22822 +};
22823 +
22824 +static struct omap_hwmod_ocp_if am43xx_l4_ls__timer8 = {
22825 + .master = &am33xx_l4_ls_hwmod,
22826 + .slave = &am43xx_timer8_hwmod,
22827 + .clk = "l4ls_gclk",
22828 + .user = OCP_USER_MPU,
22829 +};
22830 +
22831 +static struct omap_hwmod_ocp_if am43xx_l4_ls__timer9 = {
22832 + .master = &am33xx_l4_ls_hwmod,
22833 + .slave = &am43xx_timer9_hwmod,
22834 + .clk = "l4ls_gclk",
22835 + .user = OCP_USER_MPU,
22836 +};
22837 +
22838 +static struct omap_hwmod_ocp_if am43xx_l4_ls__timer10 = {
22839 + .master = &am33xx_l4_ls_hwmod,
22840 + .slave = &am43xx_timer10_hwmod,
22841 + .clk = "l4ls_gclk",
22842 + .user = OCP_USER_MPU,
22843 +};
22844 +
22845 +static struct omap_hwmod_ocp_if am43xx_l4_ls__timer11 = {
22846 + .master = &am33xx_l4_ls_hwmod,
22847 + .slave = &am43xx_timer11_hwmod,
22848 + .clk = "l4ls_gclk",
22849 + .user = OCP_USER_MPU,
22850 +};
22851 +
22852 +static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss3 = {
22853 + .master = &am33xx_l4_ls_hwmod,
22854 + .slave = &am43xx_epwmss3_hwmod,
22855 + .clk = "l4ls_gclk",
22856 + .user = OCP_USER_MPU,
22857 +};
22858 +
22859 +static struct omap_hwmod_ocp_if am43xx_epwmss3__ehrpwm3 = {
22860 + .master = &am43xx_epwmss3_hwmod,
22861 + .slave = &am43xx_ehrpwm3_hwmod,
22862 + .clk = "l4ls_gclk",
22863 + .user = OCP_USER_MPU,
22864 +};
22865 +
22866 +static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss4 = {
22867 + .master = &am33xx_l4_ls_hwmod,
22868 + .slave = &am43xx_epwmss4_hwmod,
22869 + .clk = "l4ls_gclk",
22870 + .user = OCP_USER_MPU,
22871 +};
22872 +
22873 +static struct omap_hwmod_ocp_if am43xx_epwmss4__ehrpwm4 = {
22874 + .master = &am43xx_epwmss4_hwmod,
22875 + .slave = &am43xx_ehrpwm4_hwmod,
22876 + .clk = "l4ls_gclk",
22877 + .user = OCP_USER_MPU,
22878 +};
22879 +
22880 +static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss5 = {
22881 + .master = &am33xx_l4_ls_hwmod,
22882 + .slave = &am43xx_epwmss5_hwmod,
22883 + .clk = "l4ls_gclk",
22884 + .user = OCP_USER_MPU,
22885 +};
22886 +
22887 +static struct omap_hwmod_ocp_if am43xx_epwmss5__ehrpwm5 = {
22888 + .master = &am43xx_epwmss5_hwmod,
22889 + .slave = &am43xx_ehrpwm5_hwmod,
22890 + .clk = "l4ls_gclk",
22891 + .user = OCP_USER_MPU,
22892 +};
22893 +
22894 +static struct omap_hwmod_ocp_if am43xx_l4_ls__mcspi2 = {
22895 + .master = &am33xx_l4_ls_hwmod,
22896 + .slave = &am43xx_spi2_hwmod,
22897 + .clk = "l4ls_gclk",
22898 + .user = OCP_USER_MPU,
22899 +};
22900 +
22901 +static struct omap_hwmod_ocp_if am43xx_l4_ls__mcspi3 = {
22902 + .master = &am33xx_l4_ls_hwmod,
22903 + .slave = &am43xx_spi3_hwmod,
22904 + .clk = "l4ls_gclk",
22905 + .user = OCP_USER_MPU,
22906 +};
22907 +
22908 +static struct omap_hwmod_ocp_if am43xx_l4_ls__mcspi4 = {
22909 + .master = &am33xx_l4_ls_hwmod,
22910 + .slave = &am43xx_spi4_hwmod,
22911 + .clk = "l4ls_gclk",
22912 + .user = OCP_USER_MPU,
22913 +};
22914 +
22915 +static struct omap_hwmod_ocp_if am43xx_l4_ls__gpio4 = {
22916 + .master = &am33xx_l4_ls_hwmod,
22917 + .slave = &am43xx_gpio4_hwmod,
22918 + .clk = "l4ls_gclk",
22919 + .user = OCP_USER_MPU | OCP_USER_SDMA,
22920 +};
22921 +
22922 +static struct omap_hwmod_ocp_if am43xx_l4_ls__gpio5 = {
22923 + .master = &am33xx_l4_ls_hwmod,
22924 + .slave = &am43xx_gpio5_hwmod,
22925 + .clk = "l4ls_gclk",
22926 + .user = OCP_USER_MPU | OCP_USER_SDMA,
22927 +};
22928 +
22929 +static struct omap_hwmod_ocp_if am43xx_l3_main__pruss = {
22930 + .master = &am33xx_l3_main_hwmod,
22931 + .slave = &am33xx_pruss_hwmod,
22932 + .clk = "dpll_core_m4_ck",
22933 + .user = OCP_USER_MPU,
22934 +};
22935 +
22936 +/* rng */
22937 +static struct omap_hwmod_class_sysconfig am33xx_rng_sysc = {
22938 + .rev_offs = 0x1fe0,
22939 + .sysc_offs = 0x1fe4,
22940 + .sysc_flags = SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE,
22941 + .idlemodes = SIDLE_FORCE | SIDLE_NO,
22942 + .sysc_fields = &omap_hwmod_sysc_type1,
22943 +};
22944 +
22945 +static struct omap_hwmod_class am33xx_rng_hwmod_class = {
22946 + .name = "rng",
22947 + .sysc = &am33xx_rng_sysc,
22948 +};
22949 +
22950 +static struct omap_hwmod am33xx_rng_hwmod = {
22951 + .name = "rng",
22952 + .class = &am33xx_rng_hwmod_class,
22953 + .clkdm_name = "l4ls_clkdm",
22954 + .flags = HWMOD_SWSUP_SIDLE,
22955 + .prcm = {
22956 + .omap4 = {
22957 + .modulemode = MODULEMODE_SWCTRL,
22958 + },
22959 + },
22960 +};
22961 +
22962 +static struct omap_hwmod_ocp_if am33xx_l4_per__rng = {
22963 + .master = &am33xx_l4_ls_hwmod,
22964 + .slave = &am33xx_rng_hwmod,
22965 + .clk = "rng_fck",
22966 + .user = OCP_USER_MPU,
22967 +};
22968 +
22969 +static struct omap_hwmod_class_sysconfig am43xx_des_sysc = {
22970 + .rev_offs = 0x30,
22971 + .sysc_offs = 0x34,
22972 + .syss_offs = 0x38,
22973 + .sysc_flags = SYSS_HAS_RESET_STATUS,
22974 +};
22975 +
22976 +static struct omap_hwmod_class am43xx_des_hwmod_class = {
22977 + .name = "des",
22978 + .sysc = &am43xx_des_sysc,
22979 +};
22980 +
22981 +static struct omap_hwmod am43xx_des_hwmod = {
22982 + .name = "des",
22983 + .class = &am43xx_des_hwmod_class,
22984 + .clkdm_name = "l3_clkdm",
22985 + .prcm = {
22986 + .omap4 = {
22987 + .clkctrl_offs = AM43XX_CM_PER_DES_CLKCTRL_OFFSET,
22988 + .modulemode = MODULEMODE_SWCTRL,
22989 + },
22990 + },
22991 +};
22992 +
22993 +static struct omap_hwmod_ocp_if am43xx_l3_main__des = {
22994 + .master = &am33xx_l3_main_hwmod,
22995 + .slave = &am43xx_des_hwmod,
22996 + .clk = "l3_gclk",
22997 + .user = OCP_USER_MPU,
22998 +};
22999 +
23000 +/* DSS -> L3 Main */
23001 +static struct omap_hwmod_ocp_if am43xx_dss__l3_main = {
23002 + .master = &am43xx_dss_core_hwmod,
23003 + .slave = &am33xx_l3_main_hwmod,
23004 + .clk = "disp_clk",
23005 + .user = OCP_USER_MPU | OCP_USER_SDMA,
23006 +};
23007 +
23008 +/* L4-ls -> DSS */
23009 +static struct omap_hwmod_ocp_if am43xx_l4_ls__dss = {
23010 + .master = &am33xx_l4_ls_hwmod,
23011 + .slave = &am43xx_dss_core_hwmod,
23012 + .clk = "l4ls_gclk",
23013 + .user = OCP_USER_MPU | OCP_USER_SDMA,
23014 +};
23015 +
23016 +/* L4_ls -> dss_dispc */
23017 +static struct omap_hwmod_ocp_if am43xx_l4_ls__dss_dispc = {
23018 + .master = &am33xx_l4_ls_hwmod,
23019 + .slave = &am43xx_dss_dispc_hwmod,
23020 + .clk = "l4ls_gclk",
23021 + .user = OCP_USER_MPU | OCP_USER_SDMA,
23022 +};
23023 +
23024 +/* L4_ls -> dss_rfbi */
23025 +static struct omap_hwmod_ocp_if am43xx_l4_ls__dss_rfbi = {
23026 + .master = &am33xx_l4_ls_hwmod,
23027 + .slave = &am43xx_dss_rfbi_hwmod,
23028 + .clk = "l4ls_gclk",
23029 + .user = OCP_USER_MPU | OCP_USER_SDMA,
23030 +};
23031 +
23032 +#define CLKCTRL(oh, clkctrl) ((oh).prcm.omap4.clkctrl_offs = (clkctrl))
23033 +
23034 +static void am43xx_hwmod_clkctrl(void)
23035 +{
23036 + CLKCTRL(am33xx_uart2_hwmod, AM43XX_CM_PER_UART1_CLKCTRL_OFFSET);
23037 + CLKCTRL(am33xx_uart3_hwmod, AM43XX_CM_PER_UART2_CLKCTRL_OFFSET);
23038 + CLKCTRL(am33xx_uart4_hwmod, AM43XX_CM_PER_UART3_CLKCTRL_OFFSET);
23039 + CLKCTRL(am33xx_uart5_hwmod, AM43XX_CM_PER_UART4_CLKCTRL_OFFSET);
23040 + CLKCTRL(am33xx_uart6_hwmod, AM43XX_CM_PER_UART5_CLKCTRL_OFFSET);
23041 + CLKCTRL(am33xx_dcan0_hwmod, AM43XX_CM_PER_DCAN0_CLKCTRL_OFFSET);
23042 + CLKCTRL(am33xx_dcan1_hwmod, AM43XX_CM_PER_DCAN1_CLKCTRL_OFFSET);
23043 + CLKCTRL(am33xx_elm_hwmod, AM43XX_CM_PER_ELM_CLKCTRL_OFFSET);
23044 + CLKCTRL(am33xx_epwmss0_hwmod, AM43XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET);
23045 + CLKCTRL(am33xx_epwmss1_hwmod, AM43XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET);
23046 + CLKCTRL(am33xx_epwmss2_hwmod, AM43XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET);
23047 + CLKCTRL(am33xx_gpio1_hwmod, AM43XX_CM_PER_GPIO1_CLKCTRL_OFFSET);
23048 + CLKCTRL(am33xx_gpio2_hwmod, AM43XX_CM_PER_GPIO2_CLKCTRL_OFFSET);
23049 + CLKCTRL(am33xx_gpio3_hwmod, AM43XX_CM_PER_GPIO3_CLKCTRL_OFFSET);
23050 + CLKCTRL(am33xx_i2c2_hwmod, AM43XX_CM_PER_I2C1_CLKCTRL_OFFSET);
23051 + CLKCTRL(am33xx_i2c3_hwmod, AM43XX_CM_PER_I2C2_CLKCTRL_OFFSET);
23052 + CLKCTRL(am33xx_mailbox_hwmod, AM43XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET);
23053 + CLKCTRL(am33xx_mmc0_hwmod, AM43XX_CM_PER_MMC0_CLKCTRL_OFFSET);
23054 + CLKCTRL(am33xx_mmc1_hwmod, AM43XX_CM_PER_MMC1_CLKCTRL_OFFSET);
23055 + CLKCTRL(am33xx_spi0_hwmod, AM43XX_CM_PER_SPI0_CLKCTRL_OFFSET);
23056 + CLKCTRL(am33xx_spi1_hwmod, AM43XX_CM_PER_SPI1_CLKCTRL_OFFSET);
23057 + CLKCTRL(am33xx_spinlock_hwmod, AM43XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET);
23058 + CLKCTRL(am33xx_timer2_hwmod, AM43XX_CM_PER_TIMER2_CLKCTRL_OFFSET);
23059 + CLKCTRL(am33xx_timer3_hwmod, AM43XX_CM_PER_TIMER3_CLKCTRL_OFFSET);
23060 + CLKCTRL(am33xx_timer4_hwmod, AM43XX_CM_PER_TIMER4_CLKCTRL_OFFSET);
23061 + CLKCTRL(am33xx_timer5_hwmod, AM43XX_CM_PER_TIMER5_CLKCTRL_OFFSET);
23062 + CLKCTRL(am33xx_timer6_hwmod, AM43XX_CM_PER_TIMER6_CLKCTRL_OFFSET);
23063 + CLKCTRL(am33xx_timer7_hwmod, AM43XX_CM_PER_TIMER7_CLKCTRL_OFFSET);
23064 + CLKCTRL(am33xx_wkup_m3_hwmod, AM43XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET);
23065 + CLKCTRL(am33xx_control_hwmod, AM43XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET);
23066 + CLKCTRL(am33xx_smartreflex0_hwmod,
23067 + AM43XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET);
23068 + CLKCTRL(am33xx_smartreflex1_hwmod,
23069 + AM43XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET);
23070 + CLKCTRL(am33xx_uart1_hwmod, AM43XX_CM_WKUP_UART0_CLKCTRL_OFFSET);
23071 + CLKCTRL(am33xx_timer1_hwmod, AM43XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET);
23072 + CLKCTRL(am33xx_i2c1_hwmod, AM43XX_CM_WKUP_I2C0_CLKCTRL_OFFSET);
23073 + CLKCTRL(am33xx_gpio0_hwmod, AM43XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET);
23074 + CLKCTRL(am33xx_adc_tsc_hwmod, AM43XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET);
23075 + CLKCTRL(am33xx_wd_timer1_hwmod, AM43XX_CM_WKUP_WDT1_CLKCTRL_OFFSET);
23076 + CLKCTRL(am33xx_l4_wkup_hwmod, AM43XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET);
23077 + CLKCTRL(am33xx_rtc_hwmod, AM43XX_CM_RTC_RTC_CLKCTRL_OFFSET);
23078 + CLKCTRL(am33xx_mmc2_hwmod, AM43XX_CM_PER_MMC2_CLKCTRL_OFFSET);
23079 + CLKCTRL(am33xx_gpmc_hwmod, AM43XX_CM_PER_GPMC_CLKCTRL_OFFSET);
23080 + CLKCTRL(am33xx_mcasp0_hwmod, AM43XX_CM_PER_MCASP0_CLKCTRL_OFFSET);
23081 + CLKCTRL(am33xx_mcasp1_hwmod, AM43XX_CM_PER_MCASP1_CLKCTRL_OFFSET);
23082 + CLKCTRL(am33xx_l4_ls_hwmod, AM43XX_CM_PER_L4LS_CLKCTRL_OFFSET);
23083 + CLKCTRL(am33xx_l3_main_hwmod, AM43XX_CM_PER_L3_CLKCTRL_OFFSET);
23084 + CLKCTRL(am33xx_tpcc_hwmod, AM43XX_CM_PER_TPCC_CLKCTRL_OFFSET);
23085 + CLKCTRL(am33xx_tptc0_hwmod, AM43XX_CM_PER_TPTC0_CLKCTRL_OFFSET);
23086 + CLKCTRL(am33xx_tptc1_hwmod, AM43XX_CM_PER_TPTC1_CLKCTRL_OFFSET);
23087 + CLKCTRL(am33xx_tptc2_hwmod, AM43XX_CM_PER_TPTC2_CLKCTRL_OFFSET);
23088 + CLKCTRL(am33xx_cpgmac0_hwmod, AM43XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET);
23089 + CLKCTRL(am33xx_pruss_hwmod, AM43XX_CM_PER_PRUSS_CLKCTRL_OFFSET);
23090 + CLKCTRL(am33xx_gfx_hwmod, AM43XX_CM_GFX_GFX_CLKCTRL_OFFSET);
23091 + CLKCTRL(am33xx_l4_hs_hwmod, AM43XX_CM_PER_L4HS_CLKCTRL_OFFSET);
23092 + CLKCTRL(am33xx_mpu_hwmod , AM43XX_CM_MPU_MPU_CLKCTRL_OFFSET);
23093 + CLKCTRL(am33xx_l3_instr_hwmod , AM43XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET);
23094 + CLKCTRL(am33xx_ocmcram_hwmod , AM43XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET);
23095 + CLKCTRL(am33xx_sha0_hwmod , AM43XX_CM_PER_SHA0_CLKCTRL_OFFSET);
23096 + CLKCTRL(am33xx_aes0_hwmod , AM43XX_CM_PER_AES0_CLKCTRL_OFFSET);
23097 + CLKCTRL(am33xx_rng_hwmod , AM43XX_CM_PER_RNG_CLKCTRL_OFFSET);
23098 +}
23099 +
23100 +static void am33xx_hwmod_clkctrl(void)
23101 +{
23102 + CLKCTRL(am33xx_uart2_hwmod, AM33XX_CM_PER_UART1_CLKCTRL_OFFSET);
23103 + CLKCTRL(am33xx_uart3_hwmod, AM33XX_CM_PER_UART2_CLKCTRL_OFFSET);
23104 + CLKCTRL(am33xx_uart4_hwmod, AM33XX_CM_PER_UART3_CLKCTRL_OFFSET);
23105 + CLKCTRL(am33xx_uart5_hwmod, AM33XX_CM_PER_UART4_CLKCTRL_OFFSET);
23106 + CLKCTRL(am33xx_uart6_hwmod, AM33XX_CM_PER_UART5_CLKCTRL_OFFSET);
23107 + CLKCTRL(am33xx_dcan0_hwmod, AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET);
23108 + CLKCTRL(am33xx_dcan1_hwmod, AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET);
23109 + CLKCTRL(am33xx_elm_hwmod, AM33XX_CM_PER_ELM_CLKCTRL_OFFSET);
23110 + CLKCTRL(am33xx_epwmss0_hwmod, AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET);
23111 + CLKCTRL(am33xx_epwmss1_hwmod, AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET);
23112 + CLKCTRL(am33xx_epwmss2_hwmod, AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET);
23113 + CLKCTRL(am33xx_gpio1_hwmod, AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET);
23114 + CLKCTRL(am33xx_gpio2_hwmod, AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET);
23115 + CLKCTRL(am33xx_gpio3_hwmod, AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET);
23116 + CLKCTRL(am33xx_i2c2_hwmod, AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET);
23117 + CLKCTRL(am33xx_i2c3_hwmod, AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET);
23118 + CLKCTRL(am33xx_mailbox_hwmod, AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET);
23119 + CLKCTRL(am33xx_mcasp0_hwmod, AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET);
23120 + CLKCTRL(am33xx_mcasp1_hwmod, AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET);
23121 + CLKCTRL(am33xx_mmc0_hwmod, AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET);
23122 + CLKCTRL(am33xx_mmc1_hwmod, AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET);
23123 + CLKCTRL(am33xx_spi0_hwmod, AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET);
23124 + CLKCTRL(am33xx_spi1_hwmod, AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET);
23125 + CLKCTRL(am33xx_spinlock_hwmod, AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET);
23126 + CLKCTRL(am33xx_timer2_hwmod, AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET);
23127 + CLKCTRL(am33xx_timer3_hwmod, AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET);
23128 + CLKCTRL(am33xx_timer4_hwmod, AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET);
23129 + CLKCTRL(am33xx_timer5_hwmod, AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET);
23130 + CLKCTRL(am33xx_timer6_hwmod, AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET);
23131 + CLKCTRL(am33xx_timer7_hwmod, AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET);
23132 + CLKCTRL(am33xx_wkup_m3_hwmod, AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET);
23133 + CLKCTRL(am33xx_control_hwmod, AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET);
23134 + CLKCTRL(am33xx_smartreflex0_hwmod,
23135 + AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET);
23136 + CLKCTRL(am33xx_smartreflex1_hwmod,
23137 + AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET);
23138 + CLKCTRL(am33xx_uart1_hwmod, AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET);
23139 + CLKCTRL(am33xx_timer1_hwmod, AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET);
23140 + CLKCTRL(am33xx_i2c1_hwmod, AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET);
23141 + CLKCTRL(am33xx_gpio0_hwmod, AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET);
23142 + CLKCTRL(am33xx_adc_tsc_hwmod, AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET);
23143 + CLKCTRL(am33xx_wd_timer1_hwmod, AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET);
23144 + CLKCTRL(am33xx_rtc_hwmod, AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET);
23145 + CLKCTRL(am33xx_mmc2_hwmod, AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET);
23146 + CLKCTRL(am33xx_gpmc_hwmod, AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET);
23147 + CLKCTRL(am33xx_l4_ls_hwmod, AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET);
23148 + CLKCTRL(am33xx_l4_wkup_hwmod, AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET);
23149 + CLKCTRL(am33xx_l3_main_hwmod, AM33XX_CM_PER_L3_CLKCTRL_OFFSET);
23150 + CLKCTRL(am33xx_tpcc_hwmod, AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET);
23151 + CLKCTRL(am33xx_tptc0_hwmod, AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET);
23152 + CLKCTRL(am33xx_tptc1_hwmod, AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET);
23153 + CLKCTRL(am33xx_tptc2_hwmod, AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET);
23154 + CLKCTRL(am33xx_gfx_hwmod, AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET);
23155 + CLKCTRL(am33xx_l4_hs_hwmod, AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET);
23156 + CLKCTRL(am33xx_cpgmac0_hwmod, AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET);
23157 + CLKCTRL(am33xx_pruss_hwmod, AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET);
23158 + CLKCTRL(am33xx_mpu_hwmod , AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET);
23159 + CLKCTRL(am33xx_l3_instr_hwmod , AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET);
23160 + CLKCTRL(am33xx_ocmcram_hwmod , AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET);
23161 + CLKCTRL(am33xx_sha0_hwmod , AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET);
23162 + CLKCTRL(am33xx_aes0_hwmod , AM33XX_CM_PER_AES0_CLKCTRL_OFFSET);
23163 + CLKCTRL(am33xx_rng_hwmod, AM33XX_CM_PER_RNG_CLKCTRL_OFFSET);
23164 +}
23165 +
23166 +#define RSTCTRL(oh, rstctrl) ((oh).prcm.omap4.rstctrl_offs = (rstctrl))
23167 +
23168 +static void am43xx_hwmod_rstctrl(void)
23169 +{
23170 + RSTCTRL(am33xx_pruss_hwmod, AM43XX_RM_PER_RSTCTRL_OFFSET);
23171 + RSTCTRL(am33xx_gfx_hwmod, AM43XX_RM_GFX_RSTCTRL_OFFSET);
23172 + RSTCTRL(am33xx_wkup_m3_hwmod, AM43XX_RM_WKUP_RSTCTRL_OFFSET);
23173 +}
23174 +
23175 +static void am33xx_hwmod_rstctrl(void)
23176 +{
23177 + RSTCTRL(am33xx_pruss_hwmod, AM33XX_RM_PER_RSTCTRL_OFFSET);
23178 + RSTCTRL(am33xx_gfx_hwmod, AM33XX_RM_GFX_RSTCTRL_OFFSET);
23179 + RSTCTRL(am33xx_wkup_m3_hwmod, AM33XX_RM_WKUP_RSTCTRL_OFFSET);
23180 +}
23181 +
23182 +#define RSTST(oh, rstst) ((oh).prcm.omap4.rstst_offs = (rstst))
23183 +
23184 +static void am43xx_hwmod_rstst(void)
23185 +{
23186 + RSTST(am33xx_gfx_hwmod, AM43XX_RM_GFX_RSTST_OFFSET);
23187 + RSTST(am33xx_wkup_m3_hwmod, AM43XX_RM_WKUP_RSTST_OFFSET);
23188 +}
23189 +
23190 +static void am33xx_hwmod_rstst(void)
23191 +{
23192 + RSTST(am33xx_gfx_hwmod, AM33XX_RM_GFX_RSTST_OFFSET);
23193 + RSTST(am33xx_wkup_m3_hwmod, AM33XX_RM_WKUP_RSTST_OFFSET);
23194 +}
23195 +
23196 +static void am43xx_hwmod_clockdomain(void)
23197 +{
23198 + am33xx_l4_hs_hwmod.clkdm_name = "l3_clkdm";
23199 + am33xx_adc_tsc_hwmod.clkdm_name = "l3s_tsc_clkdm";
23200 +}
23201 +
23202 +static void am33xx_hwmod_clockdomain(void)
23203 +{
23204 + am33xx_l4_hs_hwmod.clkdm_name = "l4hs_clkdm";
23205 + am33xx_adc_tsc_hwmod.clkdm_name = "l4_wkup_clkdm";
23206 +}
23207 +
23208 +#define AM43XX_L4_WKUP_OCPIF_CLK "sys_clkin_ck"
23209 +
23210 +static void am43xx_hwmod_ocpif_clk(void)
23211 +{
23212 + am33xx_l4_wkup__wkup_m3.clk = AM43XX_L4_WKUP_OCPIF_CLK;
23213 + am33xx_l4_wkup__control.clk = AM43XX_L4_WKUP_OCPIF_CLK;
23214 + am33xx_l4_wkup__smartreflex0.clk = AM43XX_L4_WKUP_OCPIF_CLK;
23215 + am33xx_l4_wkup__smartreflex1.clk = AM43XX_L4_WKUP_OCPIF_CLK;
23216 + am33xx_l4_wkup__uart1.clk = AM43XX_L4_WKUP_OCPIF_CLK;
23217 + am33xx_l4_wkup__timer1.clk = AM43XX_L4_WKUP_OCPIF_CLK;
23218 + am33xx_l4_wkup__i2c1.clk = AM43XX_L4_WKUP_OCPIF_CLK;
23219 + am33xx_l4_wkup__gpio0.clk = AM43XX_L4_WKUP_OCPIF_CLK;
23220 + am33xx_l4_wkup__wd_timer1.clk = AM43XX_L4_WKUP_OCPIF_CLK;
23221 + am33xx_wkup_m3__l4_wkup.clk = AM43XX_L4_WKUP_OCPIF_CLK;
23222 + am33xx_control_hwmod.main_clk = AM43XX_L4_WKUP_OCPIF_CLK;
23223 +}
23224 +
23225 +#define AM33XX_L4_WKUP_OCPIF_CLK "dpll_core_m4_div2_ck"
23226 +
23227 +static void am33xx_hwmod_ocpif_clk(void)
23228 +{
23229 + am33xx_l4_wkup__wkup_m3.clk = AM33XX_L4_WKUP_OCPIF_CLK;
23230 + am33xx_l4_wkup__control.clk = AM33XX_L4_WKUP_OCPIF_CLK;
23231 + am33xx_l4_wkup__smartreflex0.clk = AM33XX_L4_WKUP_OCPIF_CLK;
23232 + am33xx_l4_wkup__smartreflex1.clk = AM33XX_L4_WKUP_OCPIF_CLK;
23233 + am33xx_l4_wkup__uart1.clk = AM33XX_L4_WKUP_OCPIF_CLK;
23234 + am33xx_l4_wkup__timer1.clk = AM33XX_L4_WKUP_OCPIF_CLK;
23235 + am33xx_l4_wkup__i2c1.clk = AM33XX_L4_WKUP_OCPIF_CLK;
23236 + am33xx_l4_wkup__gpio0.clk = AM33XX_L4_WKUP_OCPIF_CLK;
23237 + am33xx_l4_wkup__wd_timer1.clk = AM33XX_L4_WKUP_OCPIF_CLK;
23238 + am33xx_wkup_m3__l4_wkup.clk = AM33XX_L4_WKUP_OCPIF_CLK;
23239 + am33xx_control_hwmod.main_clk = AM33XX_L4_WKUP_OCPIF_CLK;
23240 +}
23241 +
23242 +static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = {
23243 + &am33xx_l4_wkup__synctimer,
23244 + &am43xx_l4_ls__timer8,
23245 + &am43xx_l4_ls__timer9,
23246 + &am43xx_l4_ls__timer10,
23247 + &am43xx_l4_ls__timer11,
23248 + &am43xx_l4_ls__epwmss3,
23249 + &am43xx_epwmss3__ehrpwm3,
23250 + &am43xx_l4_ls__epwmss4,
23251 + &am43xx_epwmss4__ehrpwm4,
23252 + &am43xx_l4_ls__epwmss5,
23253 + &am43xx_epwmss5__ehrpwm5,
23254 + &am43xx_l4_ls__mcspi2,
23255 + &am43xx_l4_ls__mcspi3,
23256 + &am43xx_l4_ls__mcspi4,
23257 + &am43xx_l4_ls__gpio4,
23258 + &am43xx_l4_ls__gpio5,
23259 + &am43xx_l3_main__pruss,
23260 + &am43xx_l3_main__des,
23261 + &am43xx_l3_s__qspi,
23262 + &am43xx_l3_s__usbotgss0,
23263 + &am43xx_l3_s__usbotgss1,
23264 + &am33xx_l4_ls__ocp2scp0,
23265 + &am33xx_l4_ls__ocp2scp1,
23266 + &am43xx_dss__l3_main,
23267 + &am43xx_l4_ls__dss,
23268 + &am43xx_l4_ls__dss_dispc,
23269 + &am43xx_l4_ls__dss_rfbi,
23270 + NULL,
23271 +};
23272 +
23273 static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
23274 &am33xx_l3_main__emif,
23275 + &am33xx_l3_main__debugss,
23276 + &am33xx_l4_hs__pruss,
23277 + &am33xx_l3_main__lcdc,
23278 + &am33xx_l3_s__usbss,
23279 + &am33xx_l4_wkup__rtc,
23280 + NULL,
23281 +};
23282 +
23283 +static struct omap_hwmod_ocp_if *amx3xx_hwmod_ocp_ifs[] __initdata = {
23284 &am33xx_mpu__l3_main,
23285 &am33xx_mpu__prcm,
23286 &am33xx_l3_s__l4_ls,
23287 @@ -2494,19 +3236,16 @@ static struct omap_hwmod_ocp_if *am33xx_
23288 &am33xx_pruss__l3_main,
23289 &am33xx_wkup_m3__l4_wkup,
23290 &am33xx_gfx__l3_main,
23291 - &am33xx_l3_main__debugss,
23292 &am33xx_l4_wkup__wkup_m3,
23293 &am33xx_l4_wkup__control,
23294 &am33xx_l4_wkup__smartreflex0,
23295 &am33xx_l4_wkup__smartreflex1,
23296 &am33xx_l4_wkup__uart1,
23297 &am33xx_l4_wkup__timer1,
23298 - &am33xx_l4_wkup__rtc,
23299 &am33xx_l4_wkup__i2c1,
23300 &am33xx_l4_wkup__gpio0,
23301 &am33xx_l4_wkup__adc_tsc,
23302 &am33xx_l4_wkup__wd_timer1,
23303 - &am33xx_l4_hs__pruss,
23304 &am33xx_l4_per__dcan0,
23305 &am33xx_l4_per__dcan1,
23306 &am33xx_l4_per__gpio1,
23307 @@ -2547,23 +3286,46 @@ static struct omap_hwmod_ocp_if *am33xx_
23308 &am33xx_epwmss2__eqep2,
23309 &am33xx_epwmss2__ehrpwm2,
23310 &am33xx_l3_s__gpmc,
23311 - &am33xx_l3_main__lcdc,
23312 &am33xx_l4_ls__mcspi0,
23313 &am33xx_l4_ls__mcspi1,
23314 &am33xx_l3_main__tptc0,
23315 &am33xx_l3_main__tptc1,
23316 &am33xx_l3_main__tptc2,
23317 &am33xx_l3_main__ocmc,
23318 - &am33xx_l3_s__usbss,
23319 &am33xx_l4_hs__cpgmac0,
23320 &am33xx_cpgmac0__mdio,
23321 &am33xx_l3_main__sha0,
23322 &am33xx_l3_main__aes0,
23323 + &am33xx_l4_per__rng,
23324 NULL,
23325 };
23326
23327 int __init am33xx_hwmod_init(void)
23328 {
23329 + int ret;
23330 +
23331 omap_hwmod_init();
23332 - return omap_hwmod_register_links(am33xx_hwmod_ocp_ifs);
23333 +
23334 + if (soc_is_am33xx()) {
23335 + am33xx_hwmod_clkctrl();
23336 + am33xx_hwmod_rstctrl();
23337 + am33xx_hwmod_rstst();
23338 + am33xx_hwmod_clockdomain();
23339 + am33xx_hwmod_ocpif_clk();
23340 + } else {
23341 + am43xx_hwmod_clkctrl();
23342 + am43xx_hwmod_rstctrl();
23343 + am43xx_hwmod_rstst();
23344 + am43xx_hwmod_clockdomain();
23345 + am43xx_hwmod_ocpif_clk();
23346 + }
23347 +
23348 + ret = omap_hwmod_register_links(amx3xx_hwmod_ocp_ifs);
23349 + if (ret < 0)
23350 + return ret;
23351 +
23352 + if (soc_is_am33xx())
23353 + return omap_hwmod_register_links(am33xx_hwmod_ocp_ifs);
23354 + else
23355 + return omap_hwmod_register_links(am43xx_hwmod_ocp_ifs);
23356 }
23357 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
23358 +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
23359 @@ -200,7 +200,6 @@ static struct omap_timer_capability_dev_
23360 static struct omap_hwmod omap3xxx_timer1_hwmod = {
23361 .name = "timer1",
23362 .mpu_irqs = omap2_timer1_mpu_irqs,
23363 - .main_clk = "gpt1_fck",
23364 .prcm = {
23365 .omap2 = {
23366 .prcm_reg_id = 1,
23367 @@ -219,7 +218,6 @@ static struct omap_hwmod omap3xxx_timer1
23368 static struct omap_hwmod omap3xxx_timer2_hwmod = {
23369 .name = "timer2",
23370 .mpu_irqs = omap2_timer2_mpu_irqs,
23371 - .main_clk = "gpt2_fck",
23372 .prcm = {
23373 .omap2 = {
23374 .prcm_reg_id = 1,
23375 @@ -237,7 +235,6 @@ static struct omap_hwmod omap3xxx_timer2
23376 static struct omap_hwmod omap3xxx_timer3_hwmod = {
23377 .name = "timer3",
23378 .mpu_irqs = omap2_timer3_mpu_irqs,
23379 - .main_clk = "gpt3_fck",
23380 .prcm = {
23381 .omap2 = {
23382 .prcm_reg_id = 1,
23383 @@ -255,7 +252,6 @@ static struct omap_hwmod omap3xxx_timer3
23384 static struct omap_hwmod omap3xxx_timer4_hwmod = {
23385 .name = "timer4",
23386 .mpu_irqs = omap2_timer4_mpu_irqs,
23387 - .main_clk = "gpt4_fck",
23388 .prcm = {
23389 .omap2 = {
23390 .prcm_reg_id = 1,
23391 @@ -273,7 +269,6 @@ static struct omap_hwmod omap3xxx_timer4
23392 static struct omap_hwmod omap3xxx_timer5_hwmod = {
23393 .name = "timer5",
23394 .mpu_irqs = omap2_timer5_mpu_irqs,
23395 - .main_clk = "gpt5_fck",
23396 .prcm = {
23397 .omap2 = {
23398 .prcm_reg_id = 1,
23399 @@ -292,7 +287,6 @@ static struct omap_hwmod omap3xxx_timer5
23400 static struct omap_hwmod omap3xxx_timer6_hwmod = {
23401 .name = "timer6",
23402 .mpu_irqs = omap2_timer6_mpu_irqs,
23403 - .main_clk = "gpt6_fck",
23404 .prcm = {
23405 .omap2 = {
23406 .prcm_reg_id = 1,
23407 @@ -311,7 +305,6 @@ static struct omap_hwmod omap3xxx_timer6
23408 static struct omap_hwmod omap3xxx_timer7_hwmod = {
23409 .name = "timer7",
23410 .mpu_irqs = omap2_timer7_mpu_irqs,
23411 - .main_clk = "gpt7_fck",
23412 .prcm = {
23413 .omap2 = {
23414 .prcm_reg_id = 1,
23415 @@ -330,7 +323,6 @@ static struct omap_hwmod omap3xxx_timer7
23416 static struct omap_hwmod omap3xxx_timer8_hwmod = {
23417 .name = "timer8",
23418 .mpu_irqs = omap2_timer8_mpu_irqs,
23419 - .main_clk = "gpt8_fck",
23420 .prcm = {
23421 .omap2 = {
23422 .prcm_reg_id = 1,
23423 @@ -349,7 +341,6 @@ static struct omap_hwmod omap3xxx_timer8
23424 static struct omap_hwmod omap3xxx_timer9_hwmod = {
23425 .name = "timer9",
23426 .mpu_irqs = omap2_timer9_mpu_irqs,
23427 - .main_clk = "gpt9_fck",
23428 .prcm = {
23429 .omap2 = {
23430 .prcm_reg_id = 1,
23431 @@ -368,7 +359,6 @@ static struct omap_hwmod omap3xxx_timer9
23432 static struct omap_hwmod omap3xxx_timer10_hwmod = {
23433 .name = "timer10",
23434 .mpu_irqs = omap2_timer10_mpu_irqs,
23435 - .main_clk = "gpt10_fck",
23436 .prcm = {
23437 .omap2 = {
23438 .prcm_reg_id = 1,
23439 @@ -387,7 +377,6 @@ static struct omap_hwmod omap3xxx_timer1
23440 static struct omap_hwmod omap3xxx_timer11_hwmod = {
23441 .name = "timer11",
23442 .mpu_irqs = omap2_timer11_mpu_irqs,
23443 - .main_clk = "gpt11_fck",
23444 .prcm = {
23445 .omap2 = {
23446 .prcm_reg_id = 1,
23447 @@ -411,7 +400,6 @@ static struct omap_hwmod_irq_info omap3x
23448 static struct omap_hwmod omap3xxx_timer12_hwmod = {
23449 .name = "timer12",
23450 .mpu_irqs = omap3xxx_timer12_mpu_irqs,
23451 - .main_clk = "gpt12_fck",
23452 .prcm = {
23453 .omap2 = {
23454 .prcm_reg_id = 1,
23455 @@ -467,7 +455,6 @@ static struct omap_hwmod_class omap3xxx_
23456 static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
23457 .name = "wd_timer2",
23458 .class = &omap3xxx_wd_timer_hwmod_class,
23459 - .main_clk = "wdt2_fck",
23460 .prcm = {
23461 .omap2 = {
23462 .prcm_reg_id = 1,
23463 @@ -489,7 +476,6 @@ static struct omap_hwmod omap3xxx_uart1_
23464 .name = "uart1",
23465 .mpu_irqs = omap2_uart1_mpu_irqs,
23466 .sdma_reqs = omap2_uart1_sdma_reqs,
23467 - .main_clk = "uart1_fck",
23468 .flags = DEBUG_TI81XXUART1_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
23469 .prcm = {
23470 .omap2 = {
23471 @@ -508,7 +494,6 @@ static struct omap_hwmod omap3xxx_uart2_
23472 .name = "uart2",
23473 .mpu_irqs = omap2_uart2_mpu_irqs,
23474 .sdma_reqs = omap2_uart2_sdma_reqs,
23475 - .main_clk = "uart2_fck",
23476 .flags = DEBUG_TI81XXUART2_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
23477 .prcm = {
23478 .omap2 = {
23479 @@ -527,7 +512,6 @@ static struct omap_hwmod omap3xxx_uart3_
23480 .name = "uart3",
23481 .mpu_irqs = omap2_uart3_mpu_irqs,
23482 .sdma_reqs = omap2_uart3_sdma_reqs,
23483 - .main_clk = "uart3_fck",
23484 .flags = DEBUG_OMAP3UART3_FLAGS | DEBUG_TI81XXUART3_FLAGS |
23485 HWMOD_SWSUP_SIDLE_ACT,
23486 .prcm = {
23487 @@ -807,7 +791,6 @@ static struct omap_hwmod omap3xxx_i2c1_h
23488 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
23489 .mpu_irqs = omap2_i2c1_mpu_irqs,
23490 .sdma_reqs = omap2_i2c1_sdma_reqs,
23491 - .main_clk = "i2c1_fck",
23492 .prcm = {
23493 .omap2 = {
23494 .module_offs = CORE_MOD,
23495 @@ -832,7 +815,6 @@ static struct omap_hwmod omap3xxx_i2c2_h
23496 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
23497 .mpu_irqs = omap2_i2c2_mpu_irqs,
23498 .sdma_reqs = omap2_i2c2_sdma_reqs,
23499 - .main_clk = "i2c2_fck",
23500 .prcm = {
23501 .omap2 = {
23502 .module_offs = CORE_MOD,
23503 @@ -868,7 +850,6 @@ static struct omap_hwmod omap3xxx_i2c3_h
23504 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
23505 .mpu_irqs = i2c3_mpu_irqs,
23506 .sdma_reqs = i2c3_sdma_reqs,
23507 - .main_clk = "i2c3_fck",
23508 .prcm = {
23509 .omap2 = {
23510 .module_offs = CORE_MOD,
23511 @@ -911,17 +892,11 @@ static struct omap_gpio_dev_attr gpio_de
23512 };
23513
23514 /* gpio1 */
23515 -static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
23516 - { .role = "dbclk", .clk = "gpio1_dbck", },
23517 -};
23518
23519 static struct omap_hwmod omap3xxx_gpio1_hwmod = {
23520 .name = "gpio1",
23521 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
23522 .mpu_irqs = omap2_gpio1_irqs,
23523 - .main_clk = "gpio1_ick",
23524 - .opt_clks = gpio1_opt_clks,
23525 - .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
23526 .prcm = {
23527 .omap2 = {
23528 .prcm_reg_id = 1,
23529 @@ -936,17 +911,11 @@ static struct omap_hwmod omap3xxx_gpio1_
23530 };
23531
23532 /* gpio2 */
23533 -static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
23534 - { .role = "dbclk", .clk = "gpio2_dbck", },
23535 -};
23536
23537 static struct omap_hwmod omap3xxx_gpio2_hwmod = {
23538 .name = "gpio2",
23539 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
23540 .mpu_irqs = omap2_gpio2_irqs,
23541 - .main_clk = "gpio2_ick",
23542 - .opt_clks = gpio2_opt_clks,
23543 - .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
23544 .prcm = {
23545 .omap2 = {
23546 .prcm_reg_id = 1,
23547 @@ -961,17 +930,11 @@ static struct omap_hwmod omap3xxx_gpio2_
23548 };
23549
23550 /* gpio3 */
23551 -static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
23552 - { .role = "dbclk", .clk = "gpio3_dbck", },
23553 -};
23554
23555 static struct omap_hwmod omap3xxx_gpio3_hwmod = {
23556 .name = "gpio3",
23557 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
23558 .mpu_irqs = omap2_gpio3_irqs,
23559 - .main_clk = "gpio3_ick",
23560 - .opt_clks = gpio3_opt_clks,
23561 - .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
23562 .prcm = {
23563 .omap2 = {
23564 .prcm_reg_id = 1,
23565 @@ -986,17 +949,11 @@ static struct omap_hwmod omap3xxx_gpio3_
23566 };
23567
23568 /* gpio4 */
23569 -static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
23570 - { .role = "dbclk", .clk = "gpio4_dbck", },
23571 -};
23572
23573 static struct omap_hwmod omap3xxx_gpio4_hwmod = {
23574 .name = "gpio4",
23575 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
23576 .mpu_irqs = omap2_gpio4_irqs,
23577 - .main_clk = "gpio4_ick",
23578 - .opt_clks = gpio4_opt_clks,
23579 - .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
23580 .prcm = {
23581 .omap2 = {
23582 .prcm_reg_id = 1,
23583 @@ -1016,17 +973,11 @@ static struct omap_hwmod_irq_info omap3x
23584 { .irq = -1 },
23585 };
23586
23587 -static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
23588 - { .role = "dbclk", .clk = "gpio5_dbck", },
23589 -};
23590
23591 static struct omap_hwmod omap3xxx_gpio5_hwmod = {
23592 .name = "gpio5",
23593 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
23594 .mpu_irqs = omap3xxx_gpio5_irqs,
23595 - .main_clk = "gpio5_ick",
23596 - .opt_clks = gpio5_opt_clks,
23597 - .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
23598 .prcm = {
23599 .omap2 = {
23600 .prcm_reg_id = 1,
23601 @@ -1046,17 +997,11 @@ static struct omap_hwmod_irq_info omap3x
23602 { .irq = -1 },
23603 };
23604
23605 -static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
23606 - { .role = "dbclk", .clk = "gpio6_dbck", },
23607 -};
23608
23609 static struct omap_hwmod omap3xxx_gpio6_hwmod = {
23610 .name = "gpio6",
23611 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
23612 .mpu_irqs = omap3xxx_gpio6_irqs,
23613 - .main_clk = "gpio6_ick",
23614 - .opt_clks = gpio6_opt_clks,
23615 - .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
23616 .prcm = {
23617 .omap2 = {
23618 .prcm_reg_id = 1,
23619 @@ -1100,7 +1045,6 @@ static struct omap_hwmod omap3xxx_dma_sy
23620 .name = "dma",
23621 .class = &omap3xxx_dma_hwmod_class,
23622 .mpu_irqs = omap2_dma_system_irqs,
23623 - .main_clk = "core_l3_ick",
23624 .prcm = {
23625 .omap2 = {
23626 .module_offs = CORE_MOD,
23627 @@ -1135,15 +1079,7 @@ static struct omap_hwmod_class omap3xxx_
23628 };
23629
23630 /* McBSP functional clock mapping */
23631 -static struct omap_hwmod_opt_clk mcbsp15_opt_clks[] = {
23632 - { .role = "pad_fck", .clk = "mcbsp_clks" },
23633 - { .role = "prcm_fck", .clk = "core_96m_fck" },
23634 -};
23635
23636 -static struct omap_hwmod_opt_clk mcbsp234_opt_clks[] = {
23637 - { .role = "pad_fck", .clk = "mcbsp_clks" },
23638 - { .role = "prcm_fck", .clk = "per_96m_fck" },
23639 -};
23640
23641 /* mcbsp1 */
23642 static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
23643 @@ -1158,7 +1094,6 @@ static struct omap_hwmod omap3xxx_mcbsp1
23644 .class = &omap3xxx_mcbsp_hwmod_class,
23645 .mpu_irqs = omap3xxx_mcbsp1_irqs,
23646 .sdma_reqs = omap2_mcbsp1_sdma_reqs,
23647 - .main_clk = "mcbsp1_fck",
23648 .prcm = {
23649 .omap2 = {
23650 .prcm_reg_id = 1,
23651 @@ -1168,8 +1103,6 @@ static struct omap_hwmod omap3xxx_mcbsp1
23652 .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT,
23653 },
23654 },
23655 - .opt_clks = mcbsp15_opt_clks,
23656 - .opt_clks_cnt = ARRAY_SIZE(mcbsp15_opt_clks),
23657 };
23658
23659 /* mcbsp2 */
23660 @@ -1189,7 +1122,6 @@ static struct omap_hwmod omap3xxx_mcbsp2
23661 .class = &omap3xxx_mcbsp_hwmod_class,
23662 .mpu_irqs = omap3xxx_mcbsp2_irqs,
23663 .sdma_reqs = omap2_mcbsp2_sdma_reqs,
23664 - .main_clk = "mcbsp2_fck",
23665 .prcm = {
23666 .omap2 = {
23667 .prcm_reg_id = 1,
23668 @@ -1199,8 +1131,6 @@ static struct omap_hwmod omap3xxx_mcbsp2
23669 .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
23670 },
23671 },
23672 - .opt_clks = mcbsp234_opt_clks,
23673 - .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks),
23674 .dev_attr = &omap34xx_mcbsp2_dev_attr,
23675 };
23676
23677 @@ -1221,7 +1151,6 @@ static struct omap_hwmod omap3xxx_mcbsp3
23678 .class = &omap3xxx_mcbsp_hwmod_class,
23679 .mpu_irqs = omap3xxx_mcbsp3_irqs,
23680 .sdma_reqs = omap2_mcbsp3_sdma_reqs,
23681 - .main_clk = "mcbsp3_fck",
23682 .prcm = {
23683 .omap2 = {
23684 .prcm_reg_id = 1,
23685 @@ -1231,8 +1160,6 @@ static struct omap_hwmod omap3xxx_mcbsp3
23686 .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
23687 },
23688 },
23689 - .opt_clks = mcbsp234_opt_clks,
23690 - .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks),
23691 .dev_attr = &omap34xx_mcbsp3_dev_attr,
23692 };
23693
23694 @@ -1255,7 +1182,6 @@ static struct omap_hwmod omap3xxx_mcbsp4
23695 .class = &omap3xxx_mcbsp_hwmod_class,
23696 .mpu_irqs = omap3xxx_mcbsp4_irqs,
23697 .sdma_reqs = omap3xxx_mcbsp4_sdma_chs,
23698 - .main_clk = "mcbsp4_fck",
23699 .prcm = {
23700 .omap2 = {
23701 .prcm_reg_id = 1,
23702 @@ -1265,8 +1191,6 @@ static struct omap_hwmod omap3xxx_mcbsp4
23703 .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT,
23704 },
23705 },
23706 - .opt_clks = mcbsp234_opt_clks,
23707 - .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks),
23708 };
23709
23710 /* mcbsp5 */
23711 @@ -1288,7 +1212,6 @@ static struct omap_hwmod omap3xxx_mcbsp5
23712 .class = &omap3xxx_mcbsp_hwmod_class,
23713 .mpu_irqs = omap3xxx_mcbsp5_irqs,
23714 .sdma_reqs = omap3xxx_mcbsp5_sdma_chs,
23715 - .main_clk = "mcbsp5_fck",
23716 .prcm = {
23717 .omap2 = {
23718 .prcm_reg_id = 1,
23719 @@ -1298,8 +1221,6 @@ static struct omap_hwmod omap3xxx_mcbsp5
23720 .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT,
23721 },
23722 },
23723 - .opt_clks = mcbsp15_opt_clks,
23724 - .opt_clks_cnt = ARRAY_SIZE(mcbsp15_opt_clks),
23725 };
23726
23727 /* 'mcbsp sidetone' class */
23728 @@ -1324,7 +1245,6 @@ static struct omap_hwmod omap3xxx_mcbsp2
23729 .name = "mcbsp2_sidetone",
23730 .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
23731 .mpu_irqs = omap3xxx_mcbsp2_sidetone_irqs,
23732 - .main_clk = "mcbsp2_fck",
23733 .prcm = {
23734 .omap2 = {
23735 .prcm_reg_id = 1,
23736 @@ -1346,7 +1266,6 @@ static struct omap_hwmod omap3xxx_mcbsp3
23737 .name = "mcbsp3_sidetone",
23738 .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
23739 .mpu_irqs = omap3xxx_mcbsp3_sidetone_irqs,
23740 - .main_clk = "mcbsp3_fck",
23741 .prcm = {
23742 .omap2 = {
23743 .prcm_reg_id = 1,
23744 @@ -1571,7 +1490,6 @@ static struct omap_hwmod omap34xx_mcspi1
23745 .name = "mcspi1",
23746 .mpu_irqs = omap2_mcspi1_mpu_irqs,
23747 .sdma_reqs = omap2_mcspi1_sdma_reqs,
23748 - .main_clk = "mcspi1_fck",
23749 .prcm = {
23750 .omap2 = {
23751 .module_offs = CORE_MOD,
23752 @@ -1594,7 +1512,6 @@ static struct omap_hwmod omap34xx_mcspi2
23753 .name = "mcspi2",
23754 .mpu_irqs = omap2_mcspi2_mpu_irqs,
23755 .sdma_reqs = omap2_mcspi2_sdma_reqs,
23756 - .main_clk = "mcspi2_fck",
23757 .prcm = {
23758 .omap2 = {
23759 .module_offs = CORE_MOD,
23760 @@ -1630,7 +1547,6 @@ static struct omap_hwmod omap34xx_mcspi3
23761 .name = "mcspi3",
23762 .mpu_irqs = omap34xx_mcspi3_mpu_irqs,
23763 .sdma_reqs = omap34xx_mcspi3_sdma_reqs,
23764 - .main_clk = "mcspi3_fck",
23765 .prcm = {
23766 .omap2 = {
23767 .module_offs = CORE_MOD,
23768 @@ -1664,7 +1580,6 @@ static struct omap_hwmod omap34xx_mcspi4
23769 .name = "mcspi4",
23770 .mpu_irqs = omap34xx_mcspi4_mpu_irqs,
23771 .sdma_reqs = omap34xx_mcspi4_sdma_reqs,
23772 - .main_clk = "mcspi4_fck",
23773 .prcm = {
23774 .omap2 = {
23775 .module_offs = CORE_MOD,
23776 @@ -1707,7 +1622,6 @@ static struct omap_hwmod_irq_info omap3x
23777 static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
23778 .name = "usb_otg_hs",
23779 .mpu_irqs = omap3xxx_usbhsotg_mpu_irqs,
23780 - .main_clk = "hsotgusb_ick",
23781 .prcm = {
23782 .omap2 = {
23783 .prcm_reg_id = 1,
23784 @@ -1782,9 +1696,6 @@ static struct omap_hwmod_dma_info omap34
23785 { .dma_req = -1 }
23786 };
23787
23788 -static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = {
23789 - { .role = "dbck", .clk = "omap_32k_fck", },
23790 -};
23791
23792 static struct omap_mmc_dev_attr mmc1_dev_attr = {
23793 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
23794 @@ -1800,9 +1711,6 @@ static struct omap_hwmod omap3xxx_pre_es
23795 .name = "mmc1",
23796 .mpu_irqs = omap34xx_mmc1_mpu_irqs,
23797 .sdma_reqs = omap34xx_mmc1_sdma_reqs,
23798 - .opt_clks = omap34xx_mmc1_opt_clks,
23799 - .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
23800 - .main_clk = "mmchs1_fck",
23801 .prcm = {
23802 .omap2 = {
23803 .module_offs = CORE_MOD,
23804 @@ -1820,9 +1728,6 @@ static struct omap_hwmod omap3xxx_es3plu
23805 .name = "mmc1",
23806 .mpu_irqs = omap34xx_mmc1_mpu_irqs,
23807 .sdma_reqs = omap34xx_mmc1_sdma_reqs,
23808 - .opt_clks = omap34xx_mmc1_opt_clks,
23809 - .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
23810 - .main_clk = "mmchs1_fck",
23811 .prcm = {
23812 .omap2 = {
23813 .module_offs = CORE_MOD,
23814 @@ -1849,9 +1754,6 @@ static struct omap_hwmod_dma_info omap34
23815 { .dma_req = -1 }
23816 };
23817
23818 -static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = {
23819 - { .role = "dbck", .clk = "omap_32k_fck", },
23820 -};
23821
23822 /* See 35xx errata 2.1.1.128 in SPRZ278F */
23823 static struct omap_mmc_dev_attr mmc2_pre_es3_dev_attr = {
23824 @@ -1862,9 +1764,6 @@ static struct omap_hwmod omap3xxx_pre_es
23825 .name = "mmc2",
23826 .mpu_irqs = omap34xx_mmc2_mpu_irqs,
23827 .sdma_reqs = omap34xx_mmc2_sdma_reqs,
23828 - .opt_clks = omap34xx_mmc2_opt_clks,
23829 - .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
23830 - .main_clk = "mmchs2_fck",
23831 .prcm = {
23832 .omap2 = {
23833 .module_offs = CORE_MOD,
23834 @@ -1882,9 +1781,6 @@ static struct omap_hwmod omap3xxx_es3plu
23835 .name = "mmc2",
23836 .mpu_irqs = omap34xx_mmc2_mpu_irqs,
23837 .sdma_reqs = omap34xx_mmc2_sdma_reqs,
23838 - .opt_clks = omap34xx_mmc2_opt_clks,
23839 - .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
23840 - .main_clk = "mmchs2_fck",
23841 .prcm = {
23842 .omap2 = {
23843 .module_offs = CORE_MOD,
23844 @@ -1910,17 +1806,11 @@ static struct omap_hwmod_dma_info omap34
23845 { .dma_req = -1 }
23846 };
23847
23848 -static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
23849 - { .role = "dbck", .clk = "omap_32k_fck", },
23850 -};
23851
23852 static struct omap_hwmod omap3xxx_mmc3_hwmod = {
23853 .name = "mmc3",
23854 .mpu_irqs = omap34xx_mmc3_mpu_irqs,
23855 .sdma_reqs = omap34xx_mmc3_sdma_reqs,
23856 - .opt_clks = omap34xx_mmc3_opt_clks,
23857 - .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc3_opt_clks),
23858 - .main_clk = "mmchs3_fck",
23859 .prcm = {
23860 .omap2 = {
23861 .prcm_reg_id = 1,
23862 @@ -1954,9 +1844,6 @@ static struct omap_hwmod_class omap3xxx_
23863 .sysc = &omap3xxx_usb_host_hs_sysc,
23864 };
23865
23866 -static struct omap_hwmod_opt_clk omap3xxx_usb_host_hs_opt_clks[] = {
23867 - { .role = "ehci_logic_fck", .clk = "usbhost_120m_fck", },
23868 -};
23869
23870 static struct omap_hwmod_irq_info omap3xxx_usb_host_hs_irqs[] = {
23871 { .name = "ohci-irq", .irq = 76 + OMAP_INTC_START, },
23872 @@ -1969,7 +1856,6 @@ static struct omap_hwmod omap3xxx_usb_ho
23873 .class = &omap3xxx_usb_host_hs_hwmod_class,
23874 .clkdm_name = "l3_init_clkdm",
23875 .mpu_irqs = omap3xxx_usb_host_hs_irqs,
23876 - .main_clk = "usbhost_48m_fck",
23877 .prcm = {
23878 .omap2 = {
23879 .module_offs = OMAP3430ES2_USBHOST_MOD,
23880 @@ -1980,8 +1866,6 @@ static struct omap_hwmod omap3xxx_usb_ho
23881 .idlest_stdby_bit = OMAP3430ES2_ST_USBHOST_STDBY_SHIFT,
23882 },
23883 },
23884 - .opt_clks = omap3xxx_usb_host_hs_opt_clks,
23885 - .opt_clks_cnt = ARRAY_SIZE(omap3xxx_usb_host_hs_opt_clks),
23886
23887 /*
23888 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
23889 @@ -2062,7 +1946,6 @@ static struct omap_hwmod omap3xxx_usb_tl
23890 .class = &omap3xxx_usb_tll_hs_hwmod_class,
23891 .clkdm_name = "l3_init_clkdm",
23892 .mpu_irqs = omap3xxx_usb_tll_hs_irqs,
23893 - .main_clk = "usbtll_fck",
23894 .prcm = {
23895 .omap2 = {
23896 .module_offs = CORE_MOD,
23897 @@ -2139,7 +2022,6 @@ static struct omap_hwmod omap3xxx_counte
23898 .class = &omap3xxx_counter_hwmod_class,
23899 .clkdm_name = "wkup_clkdm",
23900 .flags = HWMOD_SWSUP_SIDLE,
23901 - .main_clk = "wkup_32k_fck",
23902 .prcm = {
23903 .omap2 = {
23904 .module_offs = WKUP_MOD,
23905 @@ -2181,7 +2063,6 @@ static struct omap_hwmod omap3xxx_gpmc_h
23906 .class = &omap3xxx_gpmc_hwmod_class,
23907 .clkdm_name = "core_l3_clkdm",
23908 .mpu_irqs = omap3xxx_gpmc_irqs,
23909 - .main_clk = "gpmc_fck",
23910 /*
23911 * XXX HWMOD_INIT_NO_RESET should not be needed for this IP
23912 * block. It is not being added due to any known bugs with
23913 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
23914 +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
23915 @@ -334,7 +334,6 @@ static struct omap_hwmod omap44xx_counte
23916 .class = &omap44xx_counter_hwmod_class,
23917 .clkdm_name = "l4_wkup_clkdm",
23918 .flags = HWMOD_SWSUP_SIDLE,
23919 - .main_clk = "sys_32k_ck",
23920 .prcm = {
23921 .omap4 = {
23922 .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
23923 @@ -479,7 +478,6 @@ static struct omap_hwmod omap44xx_dma_sy
23924 .class = &omap44xx_dma_hwmod_class,
23925 .clkdm_name = "l3_dma_clkdm",
23926 .mpu_irqs = omap44xx_dma_system_irqs,
23927 - .main_clk = "l3_div_ck",
23928 .prcm = {
23929 .omap4 = {
23930 .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET,
23931 @@ -514,7 +512,6 @@ static struct omap_hwmod omap44xx_dmic_h
23932 .name = "dmic",
23933 .class = &omap44xx_dmic_hwmod_class,
23934 .clkdm_name = "abe_clkdm",
23935 - .main_clk = "func_dmic_abe_gfclk",
23936 .prcm = {
23937 .omap4 = {
23938 .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET,
23939 @@ -914,8 +911,6 @@ static struct omap_hwmod omap44xx_emif1_
23940 .name = "emif1",
23941 .class = &omap44xx_emif_hwmod_class,
23942 .clkdm_name = "l3_emif_clkdm",
23943 - .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
23944 - .main_clk = "ddrphy_ck",
23945 .prcm = {
23946 .omap4 = {
23947 .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET,
23948 @@ -930,8 +925,6 @@ static struct omap_hwmod omap44xx_emif2_
23949 .name = "emif2",
23950 .class = &omap44xx_emif_hwmod_class,
23951 .clkdm_name = "l3_emif_clkdm",
23952 - .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
23953 - .main_clk = "ddrphy_ck",
23954 .prcm = {
23955 .omap4 = {
23956 .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET,
23957 @@ -1015,15 +1008,11 @@ static struct omap_gpio_dev_attr gpio_de
23958 };
23959
23960 /* gpio1 */
23961 -static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
23962 - { .role = "dbclk", .clk = "gpio1_dbclk" },
23963 -};
23964
23965 static struct omap_hwmod omap44xx_gpio1_hwmod = {
23966 .name = "gpio1",
23967 .class = &omap44xx_gpio_hwmod_class,
23968 .clkdm_name = "l4_wkup_clkdm",
23969 - .main_clk = "l4_wkup_clk_mux_ck",
23970 .prcm = {
23971 .omap4 = {
23972 .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET,
23973 @@ -1031,22 +1020,16 @@ static struct omap_hwmod omap44xx_gpio1_
23974 .modulemode = MODULEMODE_HWCTRL,
23975 },
23976 },
23977 - .opt_clks = gpio1_opt_clks,
23978 - .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
23979 .dev_attr = &gpio_dev_attr,
23980 };
23981
23982 /* gpio2 */
23983 -static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
23984 - { .role = "dbclk", .clk = "gpio2_dbclk" },
23985 -};
23986
23987 static struct omap_hwmod omap44xx_gpio2_hwmod = {
23988 .name = "gpio2",
23989 .class = &omap44xx_gpio_hwmod_class,
23990 .clkdm_name = "l4_per_clkdm",
23991 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
23992 - .main_clk = "l4_div_ck",
23993 .prcm = {
23994 .omap4 = {
23995 .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
23996 @@ -1054,22 +1037,16 @@ static struct omap_hwmod omap44xx_gpio2_
23997 .modulemode = MODULEMODE_HWCTRL,
23998 },
23999 },
24000 - .opt_clks = gpio2_opt_clks,
24001 - .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
24002 .dev_attr = &gpio_dev_attr,
24003 };
24004
24005 /* gpio3 */
24006 -static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
24007 - { .role = "dbclk", .clk = "gpio3_dbclk" },
24008 -};
24009
24010 static struct omap_hwmod omap44xx_gpio3_hwmod = {
24011 .name = "gpio3",
24012 .class = &omap44xx_gpio_hwmod_class,
24013 .clkdm_name = "l4_per_clkdm",
24014 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
24015 - .main_clk = "l4_div_ck",
24016 .prcm = {
24017 .omap4 = {
24018 .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
24019 @@ -1077,22 +1054,16 @@ static struct omap_hwmod omap44xx_gpio3_
24020 .modulemode = MODULEMODE_HWCTRL,
24021 },
24022 },
24023 - .opt_clks = gpio3_opt_clks,
24024 - .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
24025 .dev_attr = &gpio_dev_attr,
24026 };
24027
24028 /* gpio4 */
24029 -static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
24030 - { .role = "dbclk", .clk = "gpio4_dbclk" },
24031 -};
24032
24033 static struct omap_hwmod omap44xx_gpio4_hwmod = {
24034 .name = "gpio4",
24035 .class = &omap44xx_gpio_hwmod_class,
24036 .clkdm_name = "l4_per_clkdm",
24037 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
24038 - .main_clk = "l4_div_ck",
24039 .prcm = {
24040 .omap4 = {
24041 .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
24042 @@ -1100,22 +1071,16 @@ static struct omap_hwmod omap44xx_gpio4_
24043 .modulemode = MODULEMODE_HWCTRL,
24044 },
24045 },
24046 - .opt_clks = gpio4_opt_clks,
24047 - .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
24048 .dev_attr = &gpio_dev_attr,
24049 };
24050
24051 /* gpio5 */
24052 -static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
24053 - { .role = "dbclk", .clk = "gpio5_dbclk" },
24054 -};
24055
24056 static struct omap_hwmod omap44xx_gpio5_hwmod = {
24057 .name = "gpio5",
24058 .class = &omap44xx_gpio_hwmod_class,
24059 .clkdm_name = "l4_per_clkdm",
24060 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
24061 - .main_clk = "l4_div_ck",
24062 .prcm = {
24063 .omap4 = {
24064 .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
24065 @@ -1123,22 +1088,16 @@ static struct omap_hwmod omap44xx_gpio5_
24066 .modulemode = MODULEMODE_HWCTRL,
24067 },
24068 },
24069 - .opt_clks = gpio5_opt_clks,
24070 - .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
24071 .dev_attr = &gpio_dev_attr,
24072 };
24073
24074 /* gpio6 */
24075 -static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
24076 - { .role = "dbclk", .clk = "gpio6_dbclk" },
24077 -};
24078
24079 static struct omap_hwmod omap44xx_gpio6_hwmod = {
24080 .name = "gpio6",
24081 .class = &omap44xx_gpio_hwmod_class,
24082 .clkdm_name = "l4_per_clkdm",
24083 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
24084 - .main_clk = "l4_div_ck",
24085 .prcm = {
24086 .omap4 = {
24087 .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
24088 @@ -1146,8 +1105,6 @@ static struct omap_hwmod omap44xx_gpio6_
24089 .modulemode = MODULEMODE_HWCTRL,
24090 },
24091 },
24092 - .opt_clks = gpio6_opt_clks,
24093 - .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
24094 .dev_attr = &gpio_dev_attr,
24095 };
24096
24097 @@ -1184,7 +1141,7 @@ static struct omap_hwmod omap44xx_gpmc_h
24098 * the kernel from the board file or DT data.
24099 * HWMOD_INIT_NO_RESET should be removed ASAP.
24100 */
24101 - .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
24102 + .flags = HWMOD_INIT_NO_RESET,
24103 .prcm = {
24104 .omap4 = {
24105 .clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET,
24106 @@ -1337,7 +1294,6 @@ static struct omap_hwmod omap44xx_i2c1_h
24107 .class = &omap44xx_i2c_hwmod_class,
24108 .clkdm_name = "l4_per_clkdm",
24109 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
24110 - .main_clk = "func_96m_fclk",
24111 .prcm = {
24112 .omap4 = {
24113 .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET,
24114 @@ -1354,7 +1310,6 @@ static struct omap_hwmod omap44xx_i2c2_h
24115 .class = &omap44xx_i2c_hwmod_class,
24116 .clkdm_name = "l4_per_clkdm",
24117 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
24118 - .main_clk = "func_96m_fclk",
24119 .prcm = {
24120 .omap4 = {
24121 .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET,
24122 @@ -1371,7 +1326,6 @@ static struct omap_hwmod omap44xx_i2c3_h
24123 .class = &omap44xx_i2c_hwmod_class,
24124 .clkdm_name = "l4_per_clkdm",
24125 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
24126 - .main_clk = "func_96m_fclk",
24127 .prcm = {
24128 .omap4 = {
24129 .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET,
24130 @@ -1388,7 +1342,6 @@ static struct omap_hwmod omap44xx_i2c4_h
24131 .class = &omap44xx_i2c_hwmod_class,
24132 .clkdm_name = "l4_per_clkdm",
24133 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
24134 - .main_clk = "func_96m_fclk",
24135 .prcm = {
24136 .omap4 = {
24137 .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET,
24138 @@ -1542,7 +1495,6 @@ static struct omap_hwmod omap44xx_kbd_hw
24139 .name = "kbd",
24140 .class = &omap44xx_kbd_hwmod_class,
24141 .clkdm_name = "l4_wkup_clkdm",
24142 - .main_clk = "sys_32k_ck",
24143 .prcm = {
24144 .omap4 = {
24145 .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET,
24146 @@ -1643,16 +1595,11 @@ static struct omap_hwmod_class omap44xx_
24147 };
24148
24149 /* mcbsp1 */
24150 -static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
24151 - { .role = "pad_fck", .clk = "pad_clks_ck" },
24152 - { .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" },
24153 -};
24154
24155 static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
24156 .name = "mcbsp1",
24157 .class = &omap44xx_mcbsp_hwmod_class,
24158 .clkdm_name = "abe_clkdm",
24159 - .main_clk = "func_mcbsp1_gfclk",
24160 .prcm = {
24161 .omap4 = {
24162 .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET,
24163 @@ -1660,21 +1607,14 @@ static struct omap_hwmod omap44xx_mcbsp1
24164 .modulemode = MODULEMODE_SWCTRL,
24165 },
24166 },
24167 - .opt_clks = mcbsp1_opt_clks,
24168 - .opt_clks_cnt = ARRAY_SIZE(mcbsp1_opt_clks),
24169 };
24170
24171 /* mcbsp2 */
24172 -static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
24173 - { .role = "pad_fck", .clk = "pad_clks_ck" },
24174 - { .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" },
24175 -};
24176
24177 static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
24178 .name = "mcbsp2",
24179 .class = &omap44xx_mcbsp_hwmod_class,
24180 .clkdm_name = "abe_clkdm",
24181 - .main_clk = "func_mcbsp2_gfclk",
24182 .prcm = {
24183 .omap4 = {
24184 .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET,
24185 @@ -1682,21 +1622,14 @@ static struct omap_hwmod omap44xx_mcbsp2
24186 .modulemode = MODULEMODE_SWCTRL,
24187 },
24188 },
24189 - .opt_clks = mcbsp2_opt_clks,
24190 - .opt_clks_cnt = ARRAY_SIZE(mcbsp2_opt_clks),
24191 };
24192
24193 /* mcbsp3 */
24194 -static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
24195 - { .role = "pad_fck", .clk = "pad_clks_ck" },
24196 - { .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" },
24197 -};
24198
24199 static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
24200 .name = "mcbsp3",
24201 .class = &omap44xx_mcbsp_hwmod_class,
24202 .clkdm_name = "abe_clkdm",
24203 - .main_clk = "func_mcbsp3_gfclk",
24204 .prcm = {
24205 .omap4 = {
24206 .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET,
24207 @@ -1704,21 +1637,14 @@ static struct omap_hwmod omap44xx_mcbsp3
24208 .modulemode = MODULEMODE_SWCTRL,
24209 },
24210 },
24211 - .opt_clks = mcbsp3_opt_clks,
24212 - .opt_clks_cnt = ARRAY_SIZE(mcbsp3_opt_clks),
24213 };
24214
24215 /* mcbsp4 */
24216 -static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = {
24217 - { .role = "pad_fck", .clk = "pad_clks_ck" },
24218 - { .role = "prcm_fck", .clk = "mcbsp4_sync_mux_ck" },
24219 -};
24220
24221 static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
24222 .name = "mcbsp4",
24223 .class = &omap44xx_mcbsp_hwmod_class,
24224 .clkdm_name = "l4_per_clkdm",
24225 - .main_clk = "per_mcbsp4_gfclk",
24226 .prcm = {
24227 .omap4 = {
24228 .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET,
24229 @@ -1726,8 +1652,6 @@ static struct omap_hwmod omap44xx_mcbsp4
24230 .modulemode = MODULEMODE_SWCTRL,
24231 },
24232 },
24233 - .opt_clks = mcbsp4_opt_clks,
24234 - .opt_clks_cnt = ARRAY_SIZE(mcbsp4_opt_clks),
24235 };
24236
24237 /*
24238 @@ -1768,7 +1692,6 @@ static struct omap_hwmod omap44xx_mcpdm_
24239 * results 'slow motion' audio playback.
24240 */
24241 .flags = HWMOD_EXT_OPT_MAIN_CLK | HWMOD_SWSUP_SIDLE,
24242 - .main_clk = "pad_clks_ck",
24243 .prcm = {
24244 .omap4 = {
24245 .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET,
24246 @@ -1823,7 +1746,6 @@ static struct omap_hwmod omap44xx_mcspi1
24247 .class = &omap44xx_mcspi_hwmod_class,
24248 .clkdm_name = "l4_per_clkdm",
24249 .sdma_reqs = omap44xx_mcspi1_sdma_reqs,
24250 - .main_clk = "func_48m_fclk",
24251 .prcm = {
24252 .omap4 = {
24253 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
24254 @@ -1853,7 +1775,6 @@ static struct omap_hwmod omap44xx_mcspi2
24255 .class = &omap44xx_mcspi_hwmod_class,
24256 .clkdm_name = "l4_per_clkdm",
24257 .sdma_reqs = omap44xx_mcspi2_sdma_reqs,
24258 - .main_clk = "func_48m_fclk",
24259 .prcm = {
24260 .omap4 = {
24261 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
24262 @@ -1883,7 +1804,6 @@ static struct omap_hwmod omap44xx_mcspi3
24263 .class = &omap44xx_mcspi_hwmod_class,
24264 .clkdm_name = "l4_per_clkdm",
24265 .sdma_reqs = omap44xx_mcspi3_sdma_reqs,
24266 - .main_clk = "func_48m_fclk",
24267 .prcm = {
24268 .omap4 = {
24269 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
24270 @@ -1911,7 +1831,6 @@ static struct omap_hwmod omap44xx_mcspi4
24271 .class = &omap44xx_mcspi_hwmod_class,
24272 .clkdm_name = "l4_per_clkdm",
24273 .sdma_reqs = omap44xx_mcspi4_sdma_reqs,
24274 - .main_clk = "func_48m_fclk",
24275 .prcm = {
24276 .omap4 = {
24277 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
24278 @@ -1961,7 +1880,6 @@ static struct omap_hwmod omap44xx_mmc1_h
24279 .class = &omap44xx_mmc_hwmod_class,
24280 .clkdm_name = "l3_init_clkdm",
24281 .sdma_reqs = omap44xx_mmc1_sdma_reqs,
24282 - .main_clk = "hsmmc1_fclk",
24283 .prcm = {
24284 .omap4 = {
24285 .clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
24286 @@ -1984,7 +1902,6 @@ static struct omap_hwmod omap44xx_mmc2_h
24287 .class = &omap44xx_mmc_hwmod_class,
24288 .clkdm_name = "l3_init_clkdm",
24289 .sdma_reqs = omap44xx_mmc2_sdma_reqs,
24290 - .main_clk = "hsmmc2_fclk",
24291 .prcm = {
24292 .omap4 = {
24293 .clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
24294 @@ -2006,7 +1923,6 @@ static struct omap_hwmod omap44xx_mmc3_h
24295 .class = &omap44xx_mmc_hwmod_class,
24296 .clkdm_name = "l4_per_clkdm",
24297 .sdma_reqs = omap44xx_mmc3_sdma_reqs,
24298 - .main_clk = "func_48m_fclk",
24299 .prcm = {
24300 .omap4 = {
24301 .clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET,
24302 @@ -2028,7 +1944,6 @@ static struct omap_hwmod omap44xx_mmc4_h
24303 .class = &omap44xx_mmc_hwmod_class,
24304 .clkdm_name = "l4_per_clkdm",
24305 .sdma_reqs = omap44xx_mmc4_sdma_reqs,
24306 - .main_clk = "func_48m_fclk",
24307 .prcm = {
24308 .omap4 = {
24309 .clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET,
24310 @@ -2050,7 +1965,6 @@ static struct omap_hwmod omap44xx_mmc5_h
24311 .class = &omap44xx_mmc_hwmod_class,
24312 .clkdm_name = "l4_per_clkdm",
24313 .sdma_reqs = omap44xx_mmc5_sdma_reqs,
24314 - .main_clk = "func_48m_fclk",
24315 .prcm = {
24316 .omap4 = {
24317 .clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET,
24318 @@ -2193,7 +2107,7 @@ static struct omap_hwmod omap44xx_mpu_hw
24319 .name = "mpu",
24320 .class = &omap44xx_mpu_hwmod_class,
24321 .clkdm_name = "mpuss_clkdm",
24322 - .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
24323 + .flags = HWMOD_INIT_NO_IDLE,
24324 .main_clk = "dpll_mpu_m2_ck",
24325 .prcm = {
24326 .omap4 = {
24327 @@ -2261,7 +2175,6 @@ static struct omap_hwmod omap44xx_ocp2sc
24328 * So listing ocp2scp_usb_phy_phy_48m as a main_clk here seems
24329 * to be the best workaround.
24330 */
24331 - .main_clk = "ocp2scp_usb_phy_phy_48m",
24332 .prcm = {
24333 .omap4 = {
24334 .clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET,
24335 @@ -2629,7 +2542,6 @@ static struct omap_hwmod omap44xx_timer1
24336 .class = &omap44xx_timer_1ms_hwmod_class,
24337 .clkdm_name = "l4_wkup_clkdm",
24338 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
24339 - .main_clk = "dmt1_clk_mux",
24340 .prcm = {
24341 .omap4 = {
24342 .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
24343 @@ -2646,7 +2558,6 @@ static struct omap_hwmod omap44xx_timer2
24344 .class = &omap44xx_timer_1ms_hwmod_class,
24345 .clkdm_name = "l4_per_clkdm",
24346 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
24347 - .main_clk = "cm2_dm2_mux",
24348 .prcm = {
24349 .omap4 = {
24350 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET,
24351 @@ -2661,7 +2572,6 @@ static struct omap_hwmod omap44xx_timer3
24352 .name = "timer3",
24353 .class = &omap44xx_timer_hwmod_class,
24354 .clkdm_name = "l4_per_clkdm",
24355 - .main_clk = "cm2_dm3_mux",
24356 .prcm = {
24357 .omap4 = {
24358 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET,
24359 @@ -2676,7 +2586,6 @@ static struct omap_hwmod omap44xx_timer4
24360 .name = "timer4",
24361 .class = &omap44xx_timer_hwmod_class,
24362 .clkdm_name = "l4_per_clkdm",
24363 - .main_clk = "cm2_dm4_mux",
24364 .prcm = {
24365 .omap4 = {
24366 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET,
24367 @@ -2691,7 +2600,6 @@ static struct omap_hwmod omap44xx_timer5
24368 .name = "timer5",
24369 .class = &omap44xx_timer_hwmod_class,
24370 .clkdm_name = "abe_clkdm",
24371 - .main_clk = "timer5_sync_mux",
24372 .prcm = {
24373 .omap4 = {
24374 .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET,
24375 @@ -2707,7 +2615,6 @@ static struct omap_hwmod omap44xx_timer6
24376 .name = "timer6",
24377 .class = &omap44xx_timer_hwmod_class,
24378 .clkdm_name = "abe_clkdm",
24379 - .main_clk = "timer6_sync_mux",
24380 .prcm = {
24381 .omap4 = {
24382 .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET,
24383 @@ -2723,7 +2630,6 @@ static struct omap_hwmod omap44xx_timer7
24384 .name = "timer7",
24385 .class = &omap44xx_timer_hwmod_class,
24386 .clkdm_name = "abe_clkdm",
24387 - .main_clk = "timer7_sync_mux",
24388 .prcm = {
24389 .omap4 = {
24390 .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET,
24391 @@ -2739,7 +2645,6 @@ static struct omap_hwmod omap44xx_timer8
24392 .name = "timer8",
24393 .class = &omap44xx_timer_hwmod_class,
24394 .clkdm_name = "abe_clkdm",
24395 - .main_clk = "timer8_sync_mux",
24396 .prcm = {
24397 .omap4 = {
24398 .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET,
24399 @@ -2755,7 +2660,6 @@ static struct omap_hwmod omap44xx_timer9
24400 .name = "timer9",
24401 .class = &omap44xx_timer_hwmod_class,
24402 .clkdm_name = "l4_per_clkdm",
24403 - .main_clk = "cm2_dm9_mux",
24404 .prcm = {
24405 .omap4 = {
24406 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET,
24407 @@ -2772,7 +2676,6 @@ static struct omap_hwmod omap44xx_timer1
24408 .class = &omap44xx_timer_1ms_hwmod_class,
24409 .clkdm_name = "l4_per_clkdm",
24410 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
24411 - .main_clk = "cm2_dm10_mux",
24412 .prcm = {
24413 .omap4 = {
24414 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET,
24415 @@ -2788,7 +2691,6 @@ static struct omap_hwmod omap44xx_timer1
24416 .name = "timer11",
24417 .class = &omap44xx_timer_hwmod_class,
24418 .clkdm_name = "l4_per_clkdm",
24419 - .main_clk = "cm2_dm11_mux",
24420 .prcm = {
24421 .omap4 = {
24422 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET,
24423 @@ -2827,7 +2729,6 @@ static struct omap_hwmod omap44xx_uart1_
24424 .class = &omap44xx_uart_hwmod_class,
24425 .clkdm_name = "l4_per_clkdm",
24426 .flags = HWMOD_SWSUP_SIDLE_ACT,
24427 - .main_clk = "func_48m_fclk",
24428 .prcm = {
24429 .omap4 = {
24430 .clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET,
24431 @@ -2843,7 +2744,6 @@ static struct omap_hwmod omap44xx_uart2_
24432 .class = &omap44xx_uart_hwmod_class,
24433 .clkdm_name = "l4_per_clkdm",
24434 .flags = HWMOD_SWSUP_SIDLE_ACT,
24435 - .main_clk = "func_48m_fclk",
24436 .prcm = {
24437 .omap4 = {
24438 .clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET,
24439 @@ -2859,7 +2759,6 @@ static struct omap_hwmod omap44xx_uart3_
24440 .class = &omap44xx_uart_hwmod_class,
24441 .clkdm_name = "l4_per_clkdm",
24442 .flags = DEBUG_OMAP4UART3_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
24443 - .main_clk = "func_48m_fclk",
24444 .prcm = {
24445 .omap4 = {
24446 .clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET,
24447 @@ -2875,7 +2774,6 @@ static struct omap_hwmod omap44xx_uart4_
24448 .class = &omap44xx_uart_hwmod_class,
24449 .clkdm_name = "l4_per_clkdm",
24450 .flags = DEBUG_OMAP4UART4_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
24451 - .main_clk = "func_48m_fclk",
24452 .prcm = {
24453 .omap4 = {
24454 .clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET,
24455 @@ -2954,7 +2852,6 @@ static struct omap_hwmod omap44xx_usb_ho
24456 .name = "usb_host_hs",
24457 .class = &omap44xx_usb_host_hs_hwmod_class,
24458 .clkdm_name = "l3_init_clkdm",
24459 - .main_clk = "usb_host_hs_fck",
24460 .prcm = {
24461 .omap4 = {
24462 .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET,
24463 @@ -3036,16 +2933,12 @@ static struct omap_hwmod_class omap44xx_
24464 };
24465
24466 /* usb_otg_hs */
24467 -static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
24468 - { .role = "xclk", .clk = "usb_otg_hs_xclk" },
24469 -};
24470
24471 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
24472 .name = "usb_otg_hs",
24473 .class = &omap44xx_usb_otg_hs_hwmod_class,
24474 .clkdm_name = "l3_init_clkdm",
24475 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
24476 - .main_clk = "usb_otg_hs_ick",
24477 .prcm = {
24478 .omap4 = {
24479 .clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET,
24480 @@ -3053,8 +2946,6 @@ static struct omap_hwmod omap44xx_usb_ot
24481 .modulemode = MODULEMODE_HWCTRL,
24482 },
24483 },
24484 - .opt_clks = usb_otg_hs_opt_clks,
24485 - .opt_clks_cnt = ARRAY_SIZE(usb_otg_hs_opt_clks),
24486 };
24487
24488 /*
24489 @@ -3082,7 +2973,6 @@ static struct omap_hwmod omap44xx_usb_tl
24490 .name = "usb_tll_hs",
24491 .class = &omap44xx_usb_tll_hs_hwmod_class,
24492 .clkdm_name = "l3_init_clkdm",
24493 - .main_clk = "usb_tll_hs_ick",
24494 .prcm = {
24495 .omap4 = {
24496 .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET,
24497 @@ -3121,7 +3011,6 @@ static struct omap_hwmod omap44xx_wd_tim
24498 .name = "wd_timer2",
24499 .class = &omap44xx_wd_timer_hwmod_class,
24500 .clkdm_name = "l4_wkup_clkdm",
24501 - .main_clk = "sys_32k_ck",
24502 .prcm = {
24503 .omap4 = {
24504 .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET,
24505 @@ -4791,6 +4680,105 @@ static struct omap_hwmod_ocp_if omap44xx
24506 .user = OCP_USER_MPU | OCP_USER_SDMA,
24507 };
24508
24509 +/*
24510 + Crypto modules AES0/1 belong to:
24511 + PD_L4_PER power domain
24512 + CD_L4_SEC clock domain
24513 + On the L3, the AES modules are mapped to
24514 + L3_CLK2: Peripherals and multimedia sub clock domain
24515 +*/
24516 +
24517 +static struct omap_hwmod_class_sysconfig omap4_aes1_sysc = {
24518 + .rev_offs = 0x80,
24519 + .sysc_offs = 0x84,
24520 + .syss_offs = 0x88,
24521 + .sysc_flags = SYSS_HAS_RESET_STATUS,
24522 + .sysc_fields = &omap_hwmod_sysc_type4,
24523 +};
24524 +
24525 +static struct omap_hwmod_class omap4_aes1_hwmod_class = {
24526 + .name = "aes1",
24527 + .sysc = &omap4_aes1_sysc,
24528 +};
24529 +
24530 +static struct omap_hwmod omap4_aes1_hwmod = {
24531 + .name = "aes",
24532 + .class = &omap4_aes1_hwmod_class,
24533 + .clkdm_name = "l4_secure_clkdm",
24534 + .main_clk = "aes1_fck",
24535 + .prcm = {
24536 + .omap4 = {
24537 + .clkctrl_offs = OMAP4_CM_L4SEC_AES1_CLKCTRL_OFFSET,
24538 + .context_offs = OMAP4_RM_L4SEC_AES1_CONTEXT_OFFSET,
24539 + .modulemode = MODULEMODE_SWCTRL,
24540 + },
24541 + },
24542 +};
24543 +
24544 +/* l3_main_2 -> aes1 */
24545 +static struct omap_hwmod_addr_space omap4_aes1_addrs[] = {
24546 + {
24547 + .pa_start = 0x4B500000,
24548 + .pa_end = 0x4B500000 + SZ_1M - 1,
24549 + .flags = ADDR_TYPE_RT
24550 + },
24551 + { }
24552 +};
24553 +
24554 +static struct omap_hwmod_ocp_if omap4_l3_main_2__aes1 = {
24555 + .master = &omap44xx_l3_main_2_hwmod,
24556 + .slave = &omap4_aes1_hwmod,
24557 + .clk = "aes1_fck",
24558 + .addr = omap4_aes1_addrs,
24559 + .user = OCP_USER_MPU | OCP_USER_SDMA,
24560 +};
24561 +
24562 +/* DES3DES */
24563 +static struct omap_hwmod_class_sysconfig omap4_des_sysc = {
24564 + .rev_offs = 0x30,
24565 + .sysc_offs = 0x34,
24566 + .syss_offs = 0x38,
24567 + .sysc_flags = SYSS_HAS_RESET_STATUS,
24568 + .sysc_fields = &omap_hwmod_sysc_type4,
24569 +};
24570 +
24571 +static struct omap_hwmod_class omap4_des_hwmod_class = {
24572 + .name = "des",
24573 + .sysc = &omap4_des_sysc,
24574 +};
24575 +
24576 +
24577 +static struct omap_hwmod omap4_des_hwmod = {
24578 + .name = "des",
24579 + .class = &omap4_des_hwmod_class,
24580 + .clkdm_name = "l4_secure_clkdm",
24581 + .main_clk = "des_fck",
24582 + .prcm = {
24583 + .omap4 = {
24584 + .clkctrl_offs = OMAP4_CM_L4SEC_DES3DES_CLKCTRL_OFFSET,
24585 + .context_offs = OMAP4_RM_L4SEC_DES3DES_CONTEXT_OFFSET,
24586 + .modulemode = MODULEMODE_SWCTRL,
24587 + },
24588 + },
24589 +};
24590 +
24591 +static struct omap_hwmod_addr_space omap4_des_addrs[] = {
24592 + {
24593 + .pa_start = 0x480A4000,
24594 + .pa_end = 0x481A4000,
24595 + .flags = ADDR_TYPE_RT
24596 + },
24597 + { }
24598 +};
24599 +
24600 +static struct omap_hwmod_ocp_if omap4_l4_per__des = {
24601 + .master = &omap44xx_l4_per_hwmod,
24602 + .slave = &omap4_des_hwmod,
24603 + .clk = "des_fck",
24604 + .addr = omap4_des_addrs,
24605 + .user = OCP_USER_MPU | OCP_USER_SDMA,
24606 +};
24607 +
24608 static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
24609 &omap44xx_l3_main_1__dmm,
24610 &omap44xx_mpu__dmm,
24611 @@ -4945,6 +4933,8 @@ static struct omap_hwmod_ocp_if *omap44x
24612 &omap44xx_l4_abe__wd_timer3_dma,
24613 &omap44xx_mpu__emif1,
24614 &omap44xx_mpu__emif2,
24615 + &omap4_l3_main_2__aes1,
24616 + &omap4_l4_per__des,
24617 NULL,
24618 };
24619
24620 --- a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
24621 +++ b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
24622 @@ -234,7 +234,6 @@ static struct omap_hwmod omap54xx_counte
24623 .class = &omap54xx_counter_hwmod_class,
24624 .clkdm_name = "wkupaon_clkdm",
24625 .flags = HWMOD_SWSUP_SIDLE,
24626 - .main_clk = "wkupaon_iclk_mux",
24627 .prcm = {
24628 .omap4 = {
24629 .clkctrl_offs = OMAP54XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
24630 @@ -288,7 +287,6 @@ static struct omap_hwmod omap54xx_dma_sy
24631 .class = &omap54xx_dma_hwmod_class,
24632 .clkdm_name = "dma_clkdm",
24633 .mpu_irqs = omap54xx_dma_system_irqs,
24634 - .main_clk = "l3_iclk_div",
24635 .prcm = {
24636 .omap4 = {
24637 .clkctrl_offs = OMAP54XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET,
24638 @@ -323,7 +321,6 @@ static struct omap_hwmod omap54xx_dmic_h
24639 .name = "dmic",
24640 .class = &omap54xx_dmic_hwmod_class,
24641 .clkdm_name = "abe_clkdm",
24642 - .main_clk = "dmic_gfclk",
24643 .prcm = {
24644 .omap4 = {
24645 .clkctrl_offs = OMAP54XX_CM_ABE_DMIC_CLKCTRL_OFFSET,
24646 @@ -334,6 +331,235 @@ static struct omap_hwmod omap54xx_dmic_h
24647 };
24648
24649 /*
24650 + * 'dss' class
24651 + * display sub-system
24652 + */
24653 +static struct omap_hwmod_class_sysconfig omap54xx_dss_sysc = {
24654 + .rev_offs = 0x0000,
24655 + .syss_offs = 0x0014,
24656 + .sysc_flags = SYSS_HAS_RESET_STATUS,
24657 +};
24658 +
24659 +static struct omap_hwmod_class omap54xx_dss_hwmod_class = {
24660 + .name = "dss",
24661 + .sysc = &omap54xx_dss_sysc,
24662 + .reset = omap_dss_reset,
24663 +};
24664 +
24665 +/* dss */
24666 +static struct omap_hwmod_opt_clk dss_opt_clks[] = {
24667 + { .role = "32khz_clk", .clk = "dss_32khz_clk" },
24668 + { .role = "sys_clk", .clk = "dss_sys_clk" },
24669 + { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
24670 +};
24671 +
24672 +static struct omap_hwmod omap54xx_dss_hwmod = {
24673 + .name = "dss_core",
24674 + .class = &omap54xx_dss_hwmod_class,
24675 + .clkdm_name = "dss_clkdm",
24676 + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
24677 + .main_clk = "dss_dss_clk",
24678 + .prcm = {
24679 + .omap4 = {
24680 + .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
24681 + .context_offs = OMAP54XX_RM_DSS_DSS_CONTEXT_OFFSET,
24682 + .modulemode = MODULEMODE_SWCTRL,
24683 + },
24684 + },
24685 + .opt_clks = dss_opt_clks,
24686 + .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
24687 +};
24688 +
24689 +/*
24690 + * 'dispc' class
24691 + * display controller
24692 + */
24693 +
24694 +static struct omap_hwmod_class_sysconfig omap54xx_dispc_sysc = {
24695 + .rev_offs = 0x0000,
24696 + .sysc_offs = 0x0010,
24697 + .syss_offs = 0x0014,
24698 + .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
24699 + SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
24700 + SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
24701 + SYSS_HAS_RESET_STATUS),
24702 + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
24703 + MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
24704 + .sysc_fields = &omap_hwmod_sysc_type1,
24705 +};
24706 +
24707 +static struct omap_hwmod_class omap54xx_dispc_hwmod_class = {
24708 + .name = "dispc",
24709 + .sysc = &omap54xx_dispc_sysc,
24710 +};
24711 +
24712 +/* dss_dispc */
24713 +static struct omap_hwmod_opt_clk dss_dispc_opt_clks[] = {
24714 + { .role = "sys_clk", .clk = "dss_sys_clk" },
24715 +};
24716 +
24717 +/* dss_dispc dev_attr */
24718 +static struct omap_dss_dispc_dev_attr dss_dispc_dev_attr = {
24719 + .has_framedonetv_irq = 1,
24720 + .manager_count = 4,
24721 +};
24722 +
24723 +static struct omap_hwmod omap54xx_dss_dispc_hwmod = {
24724 + .name = "dss_dispc",
24725 + .class = &omap54xx_dispc_hwmod_class,
24726 + .clkdm_name = "dss_clkdm",
24727 + .main_clk = "dss_dss_clk",
24728 + .prcm = {
24729 + .omap4 = {
24730 + .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
24731 + .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
24732 + },
24733 + },
24734 + .opt_clks = dss_dispc_opt_clks,
24735 + .opt_clks_cnt = ARRAY_SIZE(dss_dispc_opt_clks),
24736 + .dev_attr = &dss_dispc_dev_attr,
24737 +};
24738 +
24739 +/*
24740 + * 'dsi1' class
24741 + * display serial interface controller
24742 + */
24743 +
24744 +static struct omap_hwmod_class_sysconfig omap54xx_dsi1_sysc = {
24745 + .rev_offs = 0x0000,
24746 + .sysc_offs = 0x0010,
24747 + .syss_offs = 0x0014,
24748 + .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
24749 + SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
24750 + SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
24751 + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
24752 + .sysc_fields = &omap_hwmod_sysc_type1,
24753 +};
24754 +
24755 +static struct omap_hwmod_class omap54xx_dsi1_hwmod_class = {
24756 + .name = "dsi1",
24757 + .sysc = &omap54xx_dsi1_sysc,
24758 +};
24759 +
24760 +/* dss_dsi1_a */
24761 +static struct omap_hwmod_opt_clk dss_dsi1_a_opt_clks[] = {
24762 + { .role = "sys_clk", .clk = "dss_sys_clk" },
24763 +};
24764 +
24765 +static struct omap_hwmod omap54xx_dss_dsi1_a_hwmod = {
24766 + .name = "dss_dsi1",
24767 + .class = &omap54xx_dsi1_hwmod_class,
24768 + .clkdm_name = "dss_clkdm",
24769 + .main_clk = "dss_dss_clk",
24770 + .prcm = {
24771 + .omap4 = {
24772 + .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
24773 + .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
24774 + },
24775 + },
24776 + .opt_clks = dss_dsi1_a_opt_clks,
24777 + .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_a_opt_clks),
24778 +};
24779 +
24780 +/* dss_dsi1_c */
24781 +static struct omap_hwmod_opt_clk dss_dsi1_c_opt_clks[] = {
24782 + { .role = "sys_clk", .clk = "dss_sys_clk" },
24783 +};
24784 +
24785 +static struct omap_hwmod omap54xx_dss_dsi1_c_hwmod = {
24786 + .name = "dss_dsi2",
24787 + .class = &omap54xx_dsi1_hwmod_class,
24788 + .clkdm_name = "dss_clkdm",
24789 + .main_clk = "dss_dss_clk",
24790 + .prcm = {
24791 + .omap4 = {
24792 + .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
24793 + .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
24794 + },
24795 + },
24796 + .opt_clks = dss_dsi1_c_opt_clks,
24797 + .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_c_opt_clks),
24798 +};
24799 +
24800 +/*
24801 + * 'hdmi' class
24802 + * hdmi controller
24803 + */
24804 +
24805 +static struct omap_hwmod_class_sysconfig omap54xx_hdmi_sysc = {
24806 + .rev_offs = 0x0000,
24807 + .sysc_offs = 0x0010,
24808 + .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
24809 + SYSC_HAS_SOFTRESET),
24810 + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
24811 + SIDLE_SMART_WKUP),
24812 + .sysc_fields = &omap_hwmod_sysc_type2,
24813 +};
24814 +
24815 +static struct omap_hwmod_class omap54xx_hdmi_hwmod_class = {
24816 + .name = "hdmi",
24817 + .sysc = &omap54xx_hdmi_sysc,
24818 +};
24819 +
24820 +static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
24821 + { .role = "sys_clk", .clk = "dss_sys_clk" },
24822 +};
24823 +
24824 +static struct omap_hwmod omap54xx_dss_hdmi_hwmod = {
24825 + .name = "dss_hdmi",
24826 + .class = &omap54xx_hdmi_hwmod_class,
24827 + .clkdm_name = "dss_clkdm",
24828 + .main_clk = "dss_48mhz_clk",
24829 + .prcm = {
24830 + .omap4 = {
24831 + .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
24832 + .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
24833 + },
24834 + },
24835 + .opt_clks = dss_hdmi_opt_clks,
24836 + .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks),
24837 +};
24838 +
24839 +/*
24840 + * 'rfbi' class
24841 + * remote frame buffer interface
24842 + */
24843 +
24844 +static struct omap_hwmod_class_sysconfig omap54xx_rfbi_sysc = {
24845 + .rev_offs = 0x0000,
24846 + .sysc_offs = 0x0010,
24847 + .syss_offs = 0x0014,
24848 + .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
24849 + SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
24850 + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
24851 + .sysc_fields = &omap_hwmod_sysc_type1,
24852 +};
24853 +
24854 +static struct omap_hwmod_class omap54xx_rfbi_hwmod_class = {
24855 + .name = "rfbi",
24856 + .sysc = &omap54xx_rfbi_sysc,
24857 +};
24858 +
24859 +/* dss_rfbi */
24860 +static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
24861 + { .role = "ick", .clk = "l3_iclk_div" },
24862 +};
24863 +
24864 +static struct omap_hwmod omap54xx_dss_rfbi_hwmod = {
24865 + .name = "dss_rfbi",
24866 + .class = &omap54xx_rfbi_hwmod_class,
24867 + .clkdm_name = "dss_clkdm",
24868 + .prcm = {
24869 + .omap4 = {
24870 + .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
24871 + .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
24872 + },
24873 + },
24874 + .opt_clks = dss_rfbi_opt_clks,
24875 + .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
24876 +};
24877 +
24878 +/*
24879 * 'emif' class
24880 * external memory interface no1 (wrapper)
24881 */
24882 @@ -352,8 +578,6 @@ static struct omap_hwmod omap54xx_emif1_
24883 .name = "emif1",
24884 .class = &omap54xx_emif_hwmod_class,
24885 .clkdm_name = "emif_clkdm",
24886 - .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
24887 - .main_clk = "dpll_core_h11x2_ck",
24888 .prcm = {
24889 .omap4 = {
24890 .clkctrl_offs = OMAP54XX_CM_EMIF_EMIF1_CLKCTRL_OFFSET,
24891 @@ -368,8 +592,6 @@ static struct omap_hwmod omap54xx_emif2_
24892 .name = "emif2",
24893 .class = &omap54xx_emif_hwmod_class,
24894 .clkdm_name = "emif_clkdm",
24895 - .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
24896 - .main_clk = "dpll_core_h11x2_ck",
24897 .prcm = {
24898 .omap4 = {
24899 .clkctrl_offs = OMAP54XX_CM_EMIF_EMIF2_CLKCTRL_OFFSET,
24900 @@ -409,15 +631,11 @@ static struct omap_gpio_dev_attr gpio_de
24901 };
24902
24903 /* gpio1 */
24904 -static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
24905 - { .role = "dbclk", .clk = "gpio1_dbclk" },
24906 -};
24907
24908 static struct omap_hwmod omap54xx_gpio1_hwmod = {
24909 .name = "gpio1",
24910 .class = &omap54xx_gpio_hwmod_class,
24911 .clkdm_name = "wkupaon_clkdm",
24912 - .main_clk = "wkupaon_iclk_mux",
24913 .prcm = {
24914 .omap4 = {
24915 .clkctrl_offs = OMAP54XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET,
24916 @@ -425,22 +643,16 @@ static struct omap_hwmod omap54xx_gpio1_
24917 .modulemode = MODULEMODE_HWCTRL,
24918 },
24919 },
24920 - .opt_clks = gpio1_opt_clks,
24921 - .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
24922 .dev_attr = &gpio_dev_attr,
24923 };
24924
24925 /* gpio2 */
24926 -static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
24927 - { .role = "dbclk", .clk = "gpio2_dbclk" },
24928 -};
24929
24930 static struct omap_hwmod omap54xx_gpio2_hwmod = {
24931 .name = "gpio2",
24932 .class = &omap54xx_gpio_hwmod_class,
24933 .clkdm_name = "l4per_clkdm",
24934 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
24935 - .main_clk = "l4_root_clk_div",
24936 .prcm = {
24937 .omap4 = {
24938 .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
24939 @@ -448,22 +660,16 @@ static struct omap_hwmod omap54xx_gpio2_
24940 .modulemode = MODULEMODE_HWCTRL,
24941 },
24942 },
24943 - .opt_clks = gpio2_opt_clks,
24944 - .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
24945 .dev_attr = &gpio_dev_attr,
24946 };
24947
24948 /* gpio3 */
24949 -static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
24950 - { .role = "dbclk", .clk = "gpio3_dbclk" },
24951 -};
24952
24953 static struct omap_hwmod omap54xx_gpio3_hwmod = {
24954 .name = "gpio3",
24955 .class = &omap54xx_gpio_hwmod_class,
24956 .clkdm_name = "l4per_clkdm",
24957 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
24958 - .main_clk = "l4_root_clk_div",
24959 .prcm = {
24960 .omap4 = {
24961 .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
24962 @@ -471,22 +677,16 @@ static struct omap_hwmod omap54xx_gpio3_
24963 .modulemode = MODULEMODE_HWCTRL,
24964 },
24965 },
24966 - .opt_clks = gpio3_opt_clks,
24967 - .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
24968 .dev_attr = &gpio_dev_attr,
24969 };
24970
24971 /* gpio4 */
24972 -static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
24973 - { .role = "dbclk", .clk = "gpio4_dbclk" },
24974 -};
24975
24976 static struct omap_hwmod omap54xx_gpio4_hwmod = {
24977 .name = "gpio4",
24978 .class = &omap54xx_gpio_hwmod_class,
24979 .clkdm_name = "l4per_clkdm",
24980 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
24981 - .main_clk = "l4_root_clk_div",
24982 .prcm = {
24983 .omap4 = {
24984 .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
24985 @@ -494,22 +694,16 @@ static struct omap_hwmod omap54xx_gpio4_
24986 .modulemode = MODULEMODE_HWCTRL,
24987 },
24988 },
24989 - .opt_clks = gpio4_opt_clks,
24990 - .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
24991 .dev_attr = &gpio_dev_attr,
24992 };
24993
24994 /* gpio5 */
24995 -static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
24996 - { .role = "dbclk", .clk = "gpio5_dbclk" },
24997 -};
24998
24999 static struct omap_hwmod omap54xx_gpio5_hwmod = {
25000 .name = "gpio5",
25001 .class = &omap54xx_gpio_hwmod_class,
25002 .clkdm_name = "l4per_clkdm",
25003 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
25004 - .main_clk = "l4_root_clk_div",
25005 .prcm = {
25006 .omap4 = {
25007 .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
25008 @@ -517,22 +711,16 @@ static struct omap_hwmod omap54xx_gpio5_
25009 .modulemode = MODULEMODE_HWCTRL,
25010 },
25011 },
25012 - .opt_clks = gpio5_opt_clks,
25013 - .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
25014 .dev_attr = &gpio_dev_attr,
25015 };
25016
25017 /* gpio6 */
25018 -static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
25019 - { .role = "dbclk", .clk = "gpio6_dbclk" },
25020 -};
25021
25022 static struct omap_hwmod omap54xx_gpio6_hwmod = {
25023 .name = "gpio6",
25024 .class = &omap54xx_gpio_hwmod_class,
25025 .clkdm_name = "l4per_clkdm",
25026 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
25027 - .main_clk = "l4_root_clk_div",
25028 .prcm = {
25029 .omap4 = {
25030 .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
25031 @@ -540,22 +728,16 @@ static struct omap_hwmod omap54xx_gpio6_
25032 .modulemode = MODULEMODE_HWCTRL,
25033 },
25034 },
25035 - .opt_clks = gpio6_opt_clks,
25036 - .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
25037 .dev_attr = &gpio_dev_attr,
25038 };
25039
25040 /* gpio7 */
25041 -static struct omap_hwmod_opt_clk gpio7_opt_clks[] = {
25042 - { .role = "dbclk", .clk = "gpio7_dbclk" },
25043 -};
25044
25045 static struct omap_hwmod omap54xx_gpio7_hwmod = {
25046 .name = "gpio7",
25047 .class = &omap54xx_gpio_hwmod_class,
25048 .clkdm_name = "l4per_clkdm",
25049 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
25050 - .main_clk = "l4_root_clk_div",
25051 .prcm = {
25052 .omap4 = {
25053 .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET,
25054 @@ -563,22 +745,16 @@ static struct omap_hwmod omap54xx_gpio7_
25055 .modulemode = MODULEMODE_HWCTRL,
25056 },
25057 },
25058 - .opt_clks = gpio7_opt_clks,
25059 - .opt_clks_cnt = ARRAY_SIZE(gpio7_opt_clks),
25060 .dev_attr = &gpio_dev_attr,
25061 };
25062
25063 /* gpio8 */
25064 -static struct omap_hwmod_opt_clk gpio8_opt_clks[] = {
25065 - { .role = "dbclk", .clk = "gpio8_dbclk" },
25066 -};
25067
25068 static struct omap_hwmod omap54xx_gpio8_hwmod = {
25069 .name = "gpio8",
25070 .class = &omap54xx_gpio_hwmod_class,
25071 .clkdm_name = "l4per_clkdm",
25072 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
25073 - .main_clk = "l4_root_clk_div",
25074 .prcm = {
25075 .omap4 = {
25076 .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET,
25077 @@ -586,8 +762,6 @@ static struct omap_hwmod omap54xx_gpio8_
25078 .modulemode = MODULEMODE_HWCTRL,
25079 },
25080 },
25081 - .opt_clks = gpio8_opt_clks,
25082 - .opt_clks_cnt = ARRAY_SIZE(gpio8_opt_clks),
25083 .dev_attr = &gpio_dev_attr,
25084 };
25085
25086 @@ -626,7 +800,6 @@ static struct omap_hwmod omap54xx_i2c1_h
25087 .class = &omap54xx_i2c_hwmod_class,
25088 .clkdm_name = "l4per_clkdm",
25089 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
25090 - .main_clk = "func_96m_fclk",
25091 .prcm = {
25092 .omap4 = {
25093 .clkctrl_offs = OMAP54XX_CM_L4PER_I2C1_CLKCTRL_OFFSET,
25094 @@ -643,7 +816,6 @@ static struct omap_hwmod omap54xx_i2c2_h
25095 .class = &omap54xx_i2c_hwmod_class,
25096 .clkdm_name = "l4per_clkdm",
25097 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
25098 - .main_clk = "func_96m_fclk",
25099 .prcm = {
25100 .omap4 = {
25101 .clkctrl_offs = OMAP54XX_CM_L4PER_I2C2_CLKCTRL_OFFSET,
25102 @@ -660,7 +832,6 @@ static struct omap_hwmod omap54xx_i2c3_h
25103 .class = &omap54xx_i2c_hwmod_class,
25104 .clkdm_name = "l4per_clkdm",
25105 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
25106 - .main_clk = "func_96m_fclk",
25107 .prcm = {
25108 .omap4 = {
25109 .clkctrl_offs = OMAP54XX_CM_L4PER_I2C3_CLKCTRL_OFFSET,
25110 @@ -677,7 +848,6 @@ static struct omap_hwmod omap54xx_i2c4_h
25111 .class = &omap54xx_i2c_hwmod_class,
25112 .clkdm_name = "l4per_clkdm",
25113 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
25114 - .main_clk = "func_96m_fclk",
25115 .prcm = {
25116 .omap4 = {
25117 .clkctrl_offs = OMAP54XX_CM_L4PER_I2C4_CLKCTRL_OFFSET,
25118 @@ -694,7 +864,6 @@ static struct omap_hwmod omap54xx_i2c5_h
25119 .class = &omap54xx_i2c_hwmod_class,
25120 .clkdm_name = "l4per_clkdm",
25121 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
25122 - .main_clk = "func_96m_fclk",
25123 .prcm = {
25124 .omap4 = {
25125 .clkctrl_offs = OMAP54XX_CM_L4PER_I2C5_CLKCTRL_OFFSET,
25126 @@ -729,7 +898,6 @@ static struct omap_hwmod omap54xx_kbd_hw
25127 .name = "kbd",
25128 .class = &omap54xx_kbd_hwmod_class,
25129 .clkdm_name = "wkupaon_clkdm",
25130 - .main_clk = "sys_32k_ck",
25131 .prcm = {
25132 .omap4 = {
25133 .clkctrl_offs = OMAP54XX_CM_WKUPAON_KBD_CLKCTRL_OFFSET,
25134 @@ -792,16 +960,11 @@ static struct omap_hwmod_class omap54xx_
25135 };
25136
25137 /* mcbsp1 */
25138 -static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
25139 - { .role = "pad_fck", .clk = "pad_clks_ck" },
25140 - { .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" },
25141 -};
25142
25143 static struct omap_hwmod omap54xx_mcbsp1_hwmod = {
25144 .name = "mcbsp1",
25145 .class = &omap54xx_mcbsp_hwmod_class,
25146 .clkdm_name = "abe_clkdm",
25147 - .main_clk = "mcbsp1_gfclk",
25148 .prcm = {
25149 .omap4 = {
25150 .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP1_CLKCTRL_OFFSET,
25151 @@ -809,21 +972,14 @@ static struct omap_hwmod omap54xx_mcbsp1
25152 .modulemode = MODULEMODE_SWCTRL,
25153 },
25154 },
25155 - .opt_clks = mcbsp1_opt_clks,
25156 - .opt_clks_cnt = ARRAY_SIZE(mcbsp1_opt_clks),
25157 };
25158
25159 /* mcbsp2 */
25160 -static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
25161 - { .role = "pad_fck", .clk = "pad_clks_ck" },
25162 - { .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" },
25163 -};
25164
25165 static struct omap_hwmod omap54xx_mcbsp2_hwmod = {
25166 .name = "mcbsp2",
25167 .class = &omap54xx_mcbsp_hwmod_class,
25168 .clkdm_name = "abe_clkdm",
25169 - .main_clk = "mcbsp2_gfclk",
25170 .prcm = {
25171 .omap4 = {
25172 .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP2_CLKCTRL_OFFSET,
25173 @@ -831,21 +987,14 @@ static struct omap_hwmod omap54xx_mcbsp2
25174 .modulemode = MODULEMODE_SWCTRL,
25175 },
25176 },
25177 - .opt_clks = mcbsp2_opt_clks,
25178 - .opt_clks_cnt = ARRAY_SIZE(mcbsp2_opt_clks),
25179 };
25180
25181 /* mcbsp3 */
25182 -static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
25183 - { .role = "pad_fck", .clk = "pad_clks_ck" },
25184 - { .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" },
25185 -};
25186
25187 static struct omap_hwmod omap54xx_mcbsp3_hwmod = {
25188 .name = "mcbsp3",
25189 .class = &omap54xx_mcbsp_hwmod_class,
25190 .clkdm_name = "abe_clkdm",
25191 - .main_clk = "mcbsp3_gfclk",
25192 .prcm = {
25193 .omap4 = {
25194 .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP3_CLKCTRL_OFFSET,
25195 @@ -853,8 +1002,6 @@ static struct omap_hwmod omap54xx_mcbsp3
25196 .modulemode = MODULEMODE_SWCTRL,
25197 },
25198 },
25199 - .opt_clks = mcbsp3_opt_clks,
25200 - .opt_clks_cnt = ARRAY_SIZE(mcbsp3_opt_clks),
25201 };
25202
25203 /*
25204 @@ -896,7 +1043,6 @@ static struct omap_hwmod omap54xx_mcpdm_
25205 */
25206
25207 .flags = HWMOD_EXT_OPT_MAIN_CLK,
25208 - .main_clk = "pad_clks_ck",
25209 .prcm = {
25210 .omap4 = {
25211 .clkctrl_offs = OMAP54XX_CM_ABE_MCPDM_CLKCTRL_OFFSET,
25212 @@ -938,7 +1084,6 @@ static struct omap_hwmod omap54xx_mcspi1
25213 .name = "mcspi1",
25214 .class = &omap54xx_mcspi_hwmod_class,
25215 .clkdm_name = "l4per_clkdm",
25216 - .main_clk = "func_48m_fclk",
25217 .prcm = {
25218 .omap4 = {
25219 .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
25220 @@ -959,7 +1104,6 @@ static struct omap_hwmod omap54xx_mcspi2
25221 .name = "mcspi2",
25222 .class = &omap54xx_mcspi_hwmod_class,
25223 .clkdm_name = "l4per_clkdm",
25224 - .main_clk = "func_48m_fclk",
25225 .prcm = {
25226 .omap4 = {
25227 .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
25228 @@ -980,7 +1124,6 @@ static struct omap_hwmod omap54xx_mcspi3
25229 .name = "mcspi3",
25230 .class = &omap54xx_mcspi_hwmod_class,
25231 .clkdm_name = "l4per_clkdm",
25232 - .main_clk = "func_48m_fclk",
25233 .prcm = {
25234 .omap4 = {
25235 .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
25236 @@ -1001,7 +1144,6 @@ static struct omap_hwmod omap54xx_mcspi4
25237 .name = "mcspi4",
25238 .class = &omap54xx_mcspi_hwmod_class,
25239 .clkdm_name = "l4per_clkdm",
25240 - .main_clk = "func_48m_fclk",
25241 .prcm = {
25242 .omap4 = {
25243 .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
25244 @@ -1035,9 +1177,6 @@ static struct omap_hwmod_class omap54xx_
25245 };
25246
25247 /* mmc1 */
25248 -static struct omap_hwmod_opt_clk mmc1_opt_clks[] = {
25249 - { .role = "32khz_clk", .clk = "mmc1_32khz_clk" },
25250 -};
25251
25252 /* mmc1 dev_attr */
25253 static struct omap_mmc_dev_attr mmc1_dev_attr = {
25254 @@ -1048,7 +1187,6 @@ static struct omap_hwmod omap54xx_mmc1_h
25255 .name = "mmc1",
25256 .class = &omap54xx_mmc_hwmod_class,
25257 .clkdm_name = "l3init_clkdm",
25258 - .main_clk = "mmc1_fclk",
25259 .prcm = {
25260 .omap4 = {
25261 .clkctrl_offs = OMAP54XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
25262 @@ -1056,8 +1194,6 @@ static struct omap_hwmod omap54xx_mmc1_h
25263 .modulemode = MODULEMODE_SWCTRL,
25264 },
25265 },
25266 - .opt_clks = mmc1_opt_clks,
25267 - .opt_clks_cnt = ARRAY_SIZE(mmc1_opt_clks),
25268 .dev_attr = &mmc1_dev_attr,
25269 };
25270
25271 @@ -1066,7 +1202,6 @@ static struct omap_hwmod omap54xx_mmc2_h
25272 .name = "mmc2",
25273 .class = &omap54xx_mmc_hwmod_class,
25274 .clkdm_name = "l3init_clkdm",
25275 - .main_clk = "mmc2_fclk",
25276 .prcm = {
25277 .omap4 = {
25278 .clkctrl_offs = OMAP54XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
25279 @@ -1081,7 +1216,6 @@ static struct omap_hwmod omap54xx_mmc3_h
25280 .name = "mmc3",
25281 .class = &omap54xx_mmc_hwmod_class,
25282 .clkdm_name = "l4per_clkdm",
25283 - .main_clk = "func_48m_fclk",
25284 .prcm = {
25285 .omap4 = {
25286 .clkctrl_offs = OMAP54XX_CM_L4PER_MMC3_CLKCTRL_OFFSET,
25287 @@ -1096,7 +1230,6 @@ static struct omap_hwmod omap54xx_mmc4_h
25288 .name = "mmc4",
25289 .class = &omap54xx_mmc_hwmod_class,
25290 .clkdm_name = "l4per_clkdm",
25291 - .main_clk = "func_48m_fclk",
25292 .prcm = {
25293 .omap4 = {
25294 .clkctrl_offs = OMAP54XX_CM_L4PER_MMC4_CLKCTRL_OFFSET,
25295 @@ -1111,7 +1244,6 @@ static struct omap_hwmod omap54xx_mmc5_h
25296 .name = "mmc5",
25297 .class = &omap54xx_mmc_hwmod_class,
25298 .clkdm_name = "l4per_clkdm",
25299 - .main_clk = "func_96m_fclk",
25300 .prcm = {
25301 .omap4 = {
25302 .clkctrl_offs = OMAP54XX_CM_L4PER_MMC5_CLKCTRL_OFFSET,
25303 @@ -1135,7 +1267,7 @@ static struct omap_hwmod omap54xx_mpu_hw
25304 .name = "mpu",
25305 .class = &omap54xx_mpu_hwmod_class,
25306 .clkdm_name = "mpu_clkdm",
25307 - .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
25308 + .flags = HWMOD_INIT_NO_IDLE,
25309 .main_clk = "dpll_mpu_m2_ck",
25310 .prcm = {
25311 .omap4 = {
25312 @@ -1146,6 +1278,42 @@ static struct omap_hwmod omap54xx_mpu_hw
25313 };
25314
25315 /*
25316 + * 'ocp2scp' class
25317 + * bridge to transform ocp interface protocol to scp (serial control port)
25318 + * protocol
25319 + */
25320 +
25321 +static struct omap_hwmod_class_sysconfig omap54xx_ocp2scp_sysc = {
25322 + .rev_offs = 0x0000,
25323 + .sysc_offs = 0x0010,
25324 + .syss_offs = 0x0014,
25325 + .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
25326 + SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
25327 + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
25328 + .sysc_fields = &omap_hwmod_sysc_type1,
25329 +};
25330 +
25331 +static struct omap_hwmod_class omap54xx_ocp2scp_hwmod_class = {
25332 + .name = "ocp2scp",
25333 + .sysc = &omap54xx_ocp2scp_sysc,
25334 +};
25335 +
25336 +/* ocp2scp1 */
25337 +static struct omap_hwmod omap54xx_ocp2scp1_hwmod = {
25338 + .name = "ocp2scp1",
25339 + .class = &omap54xx_ocp2scp_hwmod_class,
25340 + .clkdm_name = "l3init_clkdm",
25341 + .main_clk = "l4_root_clk_div",
25342 + .prcm = {
25343 + .omap4 = {
25344 + .clkctrl_offs = OMAP54XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET,
25345 + .context_offs = OMAP54XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET,
25346 + .modulemode = MODULEMODE_HWCTRL,
25347 + },
25348 + },
25349 +};
25350 +
25351 +/*
25352 * 'timer' class
25353 * general purpose timer module with accurate 1ms tick
25354 * This class contains several variants: ['timer_1ms', 'timer']
25355 @@ -1187,7 +1355,6 @@ static struct omap_hwmod omap54xx_timer1
25356 .name = "timer1",
25357 .class = &omap54xx_timer_1ms_hwmod_class,
25358 .clkdm_name = "wkupaon_clkdm",
25359 - .main_clk = "timer1_gfclk_mux",
25360 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
25361 .prcm = {
25362 .omap4 = {
25363 @@ -1203,7 +1370,6 @@ static struct omap_hwmod omap54xx_timer2
25364 .name = "timer2",
25365 .class = &omap54xx_timer_1ms_hwmod_class,
25366 .clkdm_name = "l4per_clkdm",
25367 - .main_clk = "timer2_gfclk_mux",
25368 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
25369 .prcm = {
25370 .omap4 = {
25371 @@ -1219,7 +1385,6 @@ static struct omap_hwmod omap54xx_timer3
25372 .name = "timer3",
25373 .class = &omap54xx_timer_hwmod_class,
25374 .clkdm_name = "l4per_clkdm",
25375 - .main_clk = "timer3_gfclk_mux",
25376 .prcm = {
25377 .omap4 = {
25378 .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
25379 @@ -1234,7 +1399,6 @@ static struct omap_hwmod omap54xx_timer4
25380 .name = "timer4",
25381 .class = &omap54xx_timer_hwmod_class,
25382 .clkdm_name = "l4per_clkdm",
25383 - .main_clk = "timer4_gfclk_mux",
25384 .prcm = {
25385 .omap4 = {
25386 .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
25387 @@ -1249,7 +1413,6 @@ static struct omap_hwmod omap54xx_timer5
25388 .name = "timer5",
25389 .class = &omap54xx_timer_hwmod_class,
25390 .clkdm_name = "abe_clkdm",
25391 - .main_clk = "timer5_gfclk_mux",
25392 .prcm = {
25393 .omap4 = {
25394 .clkctrl_offs = OMAP54XX_CM_ABE_TIMER5_CLKCTRL_OFFSET,
25395 @@ -1264,7 +1427,6 @@ static struct omap_hwmod omap54xx_timer6
25396 .name = "timer6",
25397 .class = &omap54xx_timer_hwmod_class,
25398 .clkdm_name = "abe_clkdm",
25399 - .main_clk = "timer6_gfclk_mux",
25400 .prcm = {
25401 .omap4 = {
25402 .clkctrl_offs = OMAP54XX_CM_ABE_TIMER6_CLKCTRL_OFFSET,
25403 @@ -1279,7 +1441,6 @@ static struct omap_hwmod omap54xx_timer7
25404 .name = "timer7",
25405 .class = &omap54xx_timer_hwmod_class,
25406 .clkdm_name = "abe_clkdm",
25407 - .main_clk = "timer7_gfclk_mux",
25408 .prcm = {
25409 .omap4 = {
25410 .clkctrl_offs = OMAP54XX_CM_ABE_TIMER7_CLKCTRL_OFFSET,
25411 @@ -1294,7 +1455,6 @@ static struct omap_hwmod omap54xx_timer8
25412 .name = "timer8",
25413 .class = &omap54xx_timer_hwmod_class,
25414 .clkdm_name = "abe_clkdm",
25415 - .main_clk = "timer8_gfclk_mux",
25416 .prcm = {
25417 .omap4 = {
25418 .clkctrl_offs = OMAP54XX_CM_ABE_TIMER8_CLKCTRL_OFFSET,
25419 @@ -1309,7 +1469,6 @@ static struct omap_hwmod omap54xx_timer9
25420 .name = "timer9",
25421 .class = &omap54xx_timer_hwmod_class,
25422 .clkdm_name = "l4per_clkdm",
25423 - .main_clk = "timer9_gfclk_mux",
25424 .prcm = {
25425 .omap4 = {
25426 .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET,
25427 @@ -1324,7 +1483,6 @@ static struct omap_hwmod omap54xx_timer1
25428 .name = "timer10",
25429 .class = &omap54xx_timer_1ms_hwmod_class,
25430 .clkdm_name = "l4per_clkdm",
25431 - .main_clk = "timer10_gfclk_mux",
25432 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
25433 .prcm = {
25434 .omap4 = {
25435 @@ -1340,7 +1498,6 @@ static struct omap_hwmod omap54xx_timer1
25436 .name = "timer11",
25437 .class = &omap54xx_timer_hwmod_class,
25438 .clkdm_name = "l4per_clkdm",
25439 - .main_clk = "timer11_gfclk_mux",
25440 .prcm = {
25441 .omap4 = {
25442 .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET,
25443 @@ -1377,7 +1534,6 @@ static struct omap_hwmod omap54xx_uart1_
25444 .name = "uart1",
25445 .class = &omap54xx_uart_hwmod_class,
25446 .clkdm_name = "l4per_clkdm",
25447 - .main_clk = "func_48m_fclk",
25448 .prcm = {
25449 .omap4 = {
25450 .clkctrl_offs = OMAP54XX_CM_L4PER_UART1_CLKCTRL_OFFSET,
25451 @@ -1392,7 +1548,6 @@ static struct omap_hwmod omap54xx_uart2_
25452 .name = "uart2",
25453 .class = &omap54xx_uart_hwmod_class,
25454 .clkdm_name = "l4per_clkdm",
25455 - .main_clk = "func_48m_fclk",
25456 .prcm = {
25457 .omap4 = {
25458 .clkctrl_offs = OMAP54XX_CM_L4PER_UART2_CLKCTRL_OFFSET,
25459 @@ -1408,7 +1563,6 @@ static struct omap_hwmod omap54xx_uart3_
25460 .class = &omap54xx_uart_hwmod_class,
25461 .clkdm_name = "l4per_clkdm",
25462 .flags = DEBUG_OMAP4UART3_FLAGS,
25463 - .main_clk = "func_48m_fclk",
25464 .prcm = {
25465 .omap4 = {
25466 .clkctrl_offs = OMAP54XX_CM_L4PER_UART3_CLKCTRL_OFFSET,
25467 @@ -1424,7 +1578,6 @@ static struct omap_hwmod omap54xx_uart4_
25468 .class = &omap54xx_uart_hwmod_class,
25469 .clkdm_name = "l4per_clkdm",
25470 .flags = DEBUG_OMAP4UART4_FLAGS,
25471 - .main_clk = "func_48m_fclk",
25472 .prcm = {
25473 .omap4 = {
25474 .clkctrl_offs = OMAP54XX_CM_L4PER_UART4_CLKCTRL_OFFSET,
25475 @@ -1439,7 +1592,6 @@ static struct omap_hwmod omap54xx_uart5_
25476 .name = "uart5",
25477 .class = &omap54xx_uart_hwmod_class,
25478 .clkdm_name = "l4per_clkdm",
25479 - .main_clk = "func_48m_fclk",
25480 .prcm = {
25481 .omap4 = {
25482 .clkctrl_offs = OMAP54XX_CM_L4PER_UART5_CLKCTRL_OFFSET,
25483 @@ -1454,7 +1606,6 @@ static struct omap_hwmod omap54xx_uart6_
25484 .name = "uart6",
25485 .class = &omap54xx_uart_hwmod_class,
25486 .clkdm_name = "l4per_clkdm",
25487 - .main_clk = "func_48m_fclk",
25488 .prcm = {
25489 .omap4 = {
25490 .clkctrl_offs = OMAP54XX_CM_L4PER_UART6_CLKCTRL_OFFSET,
25491 @@ -1465,6 +1616,145 @@ static struct omap_hwmod omap54xx_uart6_
25492 };
25493
25494 /*
25495 + * 'usb_host_hs' class
25496 + * high-speed multi-port usb host controller
25497 + */
25498 +
25499 +static struct omap_hwmod_class_sysconfig omap54xx_usb_host_hs_sysc = {
25500 + .rev_offs = 0x0000,
25501 + .sysc_offs = 0x0010,
25502 + .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
25503 + SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
25504 + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
25505 + SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
25506 + MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
25507 + .sysc_fields = &omap_hwmod_sysc_type2,
25508 +};
25509 +
25510 +static struct omap_hwmod_class omap54xx_usb_host_hs_hwmod_class = {
25511 + .name = "usb_host_hs",
25512 + .sysc = &omap54xx_usb_host_hs_sysc,
25513 +};
25514 +
25515 +static struct omap_hwmod_opt_clk usb_host_hs_opt_clks[] = {
25516 + { .role = "hsic60m_p2_clk", .clk = "usb_host_hs_hsic60m_p2_clk" },
25517 + { .role = "hsic60m_p3_clk", .clk = "usb_host_hs_hsic60m_p3_clk" },
25518 + { .role = "utmi_p1_clk", .clk = "usb_host_hs_utmi_p1_clk" },
25519 + { .role = "utmi_p2_clk", .clk = "usb_host_hs_utmi_p2_clk" },
25520 + { .role = "utmi_p3_clk", .clk = "usb_host_hs_utmi_p3_clk" },
25521 + { .role = "hsic480m_p1_clk", .clk = "usb_host_hs_hsic480m_p1_clk" },
25522 + { .role = "hsic60m_p1_clk", .clk = "usb_host_hs_hsic60m_p1_clk" },
25523 + { .role = "hsic480m_p3_clk", .clk = "usb_host_hs_hsic480m_p3_clk" },
25524 + { .role = "hsic480m_p2_clk", .clk = "usb_host_hs_hsic480m_p2_clk" },
25525 +};
25526 +
25527 +static struct omap_hwmod omap54xx_usb_host_hs_hwmod = {
25528 + .name = "usb_host_hs",
25529 + .class = &omap54xx_usb_host_hs_hwmod_class,
25530 + .clkdm_name = "l3init_clkdm",
25531 + /*
25532 + * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
25533 + * id: i660
25534 + *
25535 + * Description:
25536 + * In the following configuration :
25537 + * - USBHOST module is set to smart-idle mode
25538 + * - PRCM asserts idle_req to the USBHOST module ( This typically
25539 + * happens when the system is going to a low power mode : all ports
25540 + * have been suspended, the master part of the USBHOST module has
25541 + * entered the standby state, and SW has cut the functional clocks)
25542 + * - an USBHOST interrupt occurs before the module is able to answer
25543 + * idle_ack, typically a remote wakeup IRQ.
25544 + * Then the USB HOST module will enter a deadlock situation where it
25545 + * is no more accessible nor functional.
25546 + *
25547 + * Workaround:
25548 + * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
25549 + */
25550 +
25551 + /*
25552 + * Errata: USB host EHCI may stall when entering smart-standby mode
25553 + * Id: i571
25554 + *
25555 + * Description:
25556 + * When the USBHOST module is set to smart-standby mode, and when it is
25557 + * ready to enter the standby state (i.e. all ports are suspended and
25558 + * all attached devices are in suspend mode), then it can wrongly assert
25559 + * the Mstandby signal too early while there are still some residual OCP
25560 + * transactions ongoing. If this condition occurs, the internal state
25561 + * machine may go to an undefined state and the USB link may be stuck
25562 + * upon the next resume.
25563 + *
25564 + * Workaround:
25565 + * Don't use smart standby; use only force standby,
25566 + * hence HWMOD_SWSUP_MSTANDBY
25567 + */
25568 +
25569 + /*
25570 + * During system boot; If the hwmod framework resets the module
25571 + * the module will have smart idle settings; which can lead to deadlock
25572 + * (above Errata Id:i660); so, dont reset the module during boot;
25573 + * Use HWMOD_INIT_NO_RESET.
25574 + */
25575 +
25576 + .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
25577 + HWMOD_INIT_NO_RESET,
25578 + .main_clk = "l3init_60m_fclk",
25579 + .prcm = {
25580 + .omap4 = {
25581 + .clkctrl_offs = OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL_OFFSET,
25582 + .context_offs = OMAP54XX_RM_L3INIT_USB_HOST_HS_CONTEXT_OFFSET,
25583 + .modulemode = MODULEMODE_SWCTRL,
25584 + },
25585 + },
25586 + .opt_clks = usb_host_hs_opt_clks,
25587 + .opt_clks_cnt = ARRAY_SIZE(usb_host_hs_opt_clks),
25588 +};
25589 +
25590 +/*
25591 + * 'usb_tll_hs' class
25592 + * usb_tll_hs module is the adapter on the usb_host_hs ports
25593 + */
25594 +
25595 +static struct omap_hwmod_class_sysconfig omap54xx_usb_tll_hs_sysc = {
25596 + .rev_offs = 0x0000,
25597 + .sysc_offs = 0x0010,
25598 + .syss_offs = 0x0014,
25599 + .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
25600 + SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
25601 + SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
25602 + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
25603 + .sysc_fields = &omap_hwmod_sysc_type1,
25604 +};
25605 +
25606 +static struct omap_hwmod_class omap54xx_usb_tll_hs_hwmod_class = {
25607 + .name = "usb_tll_hs",
25608 + .sysc = &omap54xx_usb_tll_hs_sysc,
25609 +};
25610 +
25611 +static struct omap_hwmod_opt_clk usb_tll_hs_opt_clks[] = {
25612 + { .role = "usb_ch2_clk", .clk = "usb_tll_hs_usb_ch2_clk" },
25613 + { .role = "usb_ch0_clk", .clk = "usb_tll_hs_usb_ch0_clk" },
25614 + { .role = "usb_ch1_clk", .clk = "usb_tll_hs_usb_ch1_clk" },
25615 +};
25616 +
25617 +static struct omap_hwmod omap54xx_usb_tll_hs_hwmod = {
25618 + .name = "usb_tll_hs",
25619 + .class = &omap54xx_usb_tll_hs_hwmod_class,
25620 + .clkdm_name = "l3init_clkdm",
25621 + .main_clk = "l4_root_clk_div",
25622 + .prcm = {
25623 + .omap4 = {
25624 + .clkctrl_offs = OMAP54XX_CM_L3INIT_USB_TLL_HS_CLKCTRL_OFFSET,
25625 + .context_offs = OMAP54XX_RM_L3INIT_USB_TLL_HS_CONTEXT_OFFSET,
25626 + .modulemode = MODULEMODE_HWCTRL,
25627 + },
25628 + },
25629 + .opt_clks = usb_tll_hs_opt_clks,
25630 + .opt_clks_cnt = ARRAY_SIZE(usb_tll_hs_opt_clks),
25631 +};
25632 +
25633 +/*
25634 * 'usb_otg_ss' class
25635 * 2.0 super speed (usb_otg_ss) controller
25636 */
25637 @@ -1486,16 +1776,12 @@ static struct omap_hwmod_class omap54xx_
25638 };
25639
25640 /* usb_otg_ss */
25641 -static struct omap_hwmod_opt_clk usb_otg_ss_opt_clks[] = {
25642 - { .role = "refclk960m", .clk = "usb_otg_ss_refclk960m" },
25643 -};
25644
25645 static struct omap_hwmod omap54xx_usb_otg_ss_hwmod = {
25646 .name = "usb_otg_ss",
25647 .class = &omap54xx_usb_otg_ss_hwmod_class,
25648 .clkdm_name = "l3init_clkdm",
25649 .flags = HWMOD_SWSUP_SIDLE,
25650 - .main_clk = "dpll_core_h13x2_ck",
25651 .prcm = {
25652 .omap4 = {
25653 .clkctrl_offs = OMAP54XX_CM_L3INIT_USB_OTG_SS_CLKCTRL_OFFSET,
25654 @@ -1503,8 +1789,6 @@ static struct omap_hwmod omap54xx_usb_ot
25655 .modulemode = MODULEMODE_HWCTRL,
25656 },
25657 },
25658 - .opt_clks = usb_otg_ss_opt_clks,
25659 - .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss_opt_clks),
25660 };
25661
25662 /*
25663 @@ -1535,7 +1819,6 @@ static struct omap_hwmod omap54xx_wd_tim
25664 .name = "wd_timer2",
25665 .class = &omap54xx_wd_timer_hwmod_class,
25666 .clkdm_name = "wkupaon_clkdm",
25667 - .main_clk = "sys_32k_ck",
25668 .prcm = {
25669 .omap4 = {
25670 .clkctrl_offs = OMAP54XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET,
25671 @@ -1545,6 +1828,76 @@ static struct omap_hwmod omap54xx_wd_tim
25672 },
25673 };
25674
25675 +/*
25676 + * 'ocp2scp' class
25677 + * bridge to transform ocp interface protocol to scp (serial control port)
25678 + * protocol
25679 + */
25680 +/* ocp2scp3 */
25681 +static struct omap_hwmod omap54xx_ocp2scp3_hwmod;
25682 +/* l4_cfg -> ocp2scp3 */
25683 +static struct omap_hwmod_ocp_if omap54xx_l4_cfg__ocp2scp3 = {
25684 + .master = &omap54xx_l4_cfg_hwmod,
25685 + .slave = &omap54xx_ocp2scp3_hwmod,
25686 + .clk = "l4_root_clk_div",
25687 + .user = OCP_USER_MPU | OCP_USER_SDMA,
25688 +};
25689 +
25690 +static struct omap_hwmod omap54xx_ocp2scp3_hwmod = {
25691 + .name = "ocp2scp3",
25692 + .class = &omap54xx_ocp2scp_hwmod_class,
25693 + .clkdm_name = "l3init_clkdm",
25694 + .prcm = {
25695 + .omap4 = {
25696 + .clkctrl_offs = OMAP54XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
25697 + .context_offs = OMAP54XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
25698 + .modulemode = MODULEMODE_HWCTRL,
25699 + },
25700 + },
25701 +};
25702 +
25703 +/*
25704 + * 'sata' class
25705 + * sata: serial ata interface gen2 compliant ( 1 rx/ 1 tx)
25706 + */
25707 +
25708 +static struct omap_hwmod_class_sysconfig omap54xx_sata_sysc = {
25709 + .sysc_offs = 0x0000,
25710 + .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
25711 + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
25712 + SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
25713 + MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
25714 + .sysc_fields = &omap_hwmod_sysc_type2,
25715 +};
25716 +
25717 +static struct omap_hwmod_class omap54xx_sata_hwmod_class = {
25718 + .name = "sata",
25719 + .sysc = &omap54xx_sata_sysc,
25720 +};
25721 +
25722 +/* sata */
25723 +static struct omap_hwmod omap54xx_sata_hwmod = {
25724 + .name = "sata",
25725 + .class = &omap54xx_sata_hwmod_class,
25726 + .clkdm_name = "l3init_clkdm",
25727 + .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
25728 + .main_clk = "func_48m_fclk",
25729 + .prcm = {
25730 + .omap4 = {
25731 + .clkctrl_offs = OMAP54XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
25732 + .context_offs = OMAP54XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
25733 + .modulemode = MODULEMODE_SWCTRL,
25734 + },
25735 + },
25736 +};
25737 +
25738 +/* l4_cfg -> sata */
25739 +static struct omap_hwmod_ocp_if omap54xx_l4_cfg__sata = {
25740 + .master = &omap54xx_l4_cfg_hwmod,
25741 + .slave = &omap54xx_sata_hwmod,
25742 + .clk = "l3_iclk_div",
25743 + .user = OCP_USER_MPU | OCP_USER_SDMA,
25744 +};
25745
25746 /*
25747 * Interfaces
25748 @@ -1712,6 +2065,54 @@ static struct omap_hwmod_ocp_if omap54xx
25749 .user = OCP_USER_MPU,
25750 };
25751
25752 +/* l3_main_2 -> dss */
25753 +static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss = {
25754 + .master = &omap54xx_l3_main_2_hwmod,
25755 + .slave = &omap54xx_dss_hwmod,
25756 + .clk = "l3_iclk_div",
25757 + .user = OCP_USER_MPU | OCP_USER_SDMA,
25758 +};
25759 +
25760 +/* l3_main_2 -> dss_dispc */
25761 +static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_dispc = {
25762 + .master = &omap54xx_l3_main_2_hwmod,
25763 + .slave = &omap54xx_dss_dispc_hwmod,
25764 + .clk = "l3_iclk_div",
25765 + .user = OCP_USER_MPU | OCP_USER_SDMA,
25766 +};
25767 +
25768 +/* l3_main_2 -> dss_dsi1_a */
25769 +static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_dsi1_a = {
25770 + .master = &omap54xx_l3_main_2_hwmod,
25771 + .slave = &omap54xx_dss_dsi1_a_hwmod,
25772 + .clk = "l3_iclk_div",
25773 + .user = OCP_USER_MPU | OCP_USER_SDMA,
25774 +};
25775 +
25776 +/* l3_main_2 -> dss_dsi1_c */
25777 +static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_dsi1_c = {
25778 + .master = &omap54xx_l3_main_2_hwmod,
25779 + .slave = &omap54xx_dss_dsi1_c_hwmod,
25780 + .clk = "l3_iclk_div",
25781 + .user = OCP_USER_MPU | OCP_USER_SDMA,
25782 +};
25783 +
25784 +/* l3_main_2 -> dss_hdmi */
25785 +static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_hdmi = {
25786 + .master = &omap54xx_l3_main_2_hwmod,
25787 + .slave = &omap54xx_dss_hdmi_hwmod,
25788 + .clk = "l3_iclk_div",
25789 + .user = OCP_USER_MPU | OCP_USER_SDMA,
25790 +};
25791 +
25792 +/* l3_main_2 -> dss_rfbi */
25793 +static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_rfbi = {
25794 + .master = &omap54xx_l3_main_2_hwmod,
25795 + .slave = &omap54xx_dss_rfbi_hwmod,
25796 + .clk = "l3_iclk_div",
25797 + .user = OCP_USER_MPU | OCP_USER_SDMA,
25798 +};
25799 +
25800 /* mpu -> emif1 */
25801 static struct omap_hwmod_ocp_if omap54xx_mpu__emif1 = {
25802 .master = &omap54xx_mpu_hwmod,
25803 @@ -1960,6 +2361,14 @@ static struct omap_hwmod_ocp_if omap54xx
25804 .user = OCP_USER_MPU | OCP_USER_SDMA,
25805 };
25806
25807 +/* l4_cfg -> ocp2scp1 */
25808 +static struct omap_hwmod_ocp_if omap54xx_l4_cfg__ocp2scp1 = {
25809 + .master = &omap54xx_l4_cfg_hwmod,
25810 + .slave = &omap54xx_ocp2scp1_hwmod,
25811 + .clk = "l4_root_clk_div",
25812 + .user = OCP_USER_MPU | OCP_USER_SDMA,
25813 +};
25814 +
25815 /* l4_wkup -> timer1 */
25816 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__timer1 = {
25817 .master = &omap54xx_l4_wkup_hwmod,
25818 @@ -2096,6 +2505,22 @@ static struct omap_hwmod_ocp_if omap54xx
25819 .user = OCP_USER_MPU | OCP_USER_SDMA,
25820 };
25821
25822 +/* l4_cfg -> usb_host_hs */
25823 +static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_host_hs = {
25824 + .master = &omap54xx_l4_cfg_hwmod,
25825 + .slave = &omap54xx_usb_host_hs_hwmod,
25826 + .clk = "l3_iclk_div",
25827 + .user = OCP_USER_MPU | OCP_USER_SDMA,
25828 +};
25829 +
25830 +/* l4_cfg -> usb_tll_hs */
25831 +static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_tll_hs = {
25832 + .master = &omap54xx_l4_cfg_hwmod,
25833 + .slave = &omap54xx_usb_tll_hs_hwmod,
25834 + .clk = "l4_root_clk_div",
25835 + .user = OCP_USER_MPU | OCP_USER_SDMA,
25836 +};
25837 +
25838 /* l4_cfg -> usb_otg_ss */
25839 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_otg_ss = {
25840 .master = &omap54xx_l4_cfg_hwmod,
25841 @@ -2132,6 +2557,12 @@ static struct omap_hwmod_ocp_if *omap54x
25842 &omap54xx_l4_wkup__counter_32k,
25843 &omap54xx_l4_cfg__dma_system,
25844 &omap54xx_l4_abe__dmic,
25845 + &omap54xx_l3_main_2__dss,
25846 + &omap54xx_l3_main_2__dss_dispc,
25847 + &omap54xx_l3_main_2__dss_dsi1_a,
25848 + &omap54xx_l3_main_2__dss_dsi1_c,
25849 + &omap54xx_l3_main_2__dss_hdmi,
25850 + &omap54xx_l3_main_2__dss_rfbi,
25851 &omap54xx_mpu__emif1,
25852 &omap54xx_mpu__emif2,
25853 &omap54xx_l4_wkup__gpio1,
25854 @@ -2163,6 +2594,7 @@ static struct omap_hwmod_ocp_if *omap54x
25855 &omap54xx_l4_per__mmc4,
25856 &omap54xx_l4_per__mmc5,
25857 &omap54xx_l4_cfg__mpu,
25858 + &omap54xx_l4_cfg__ocp2scp1,
25859 &omap54xx_l4_wkup__timer1,
25860 &omap54xx_l4_per__timer2,
25861 &omap54xx_l4_per__timer3,
25862 @@ -2180,8 +2612,12 @@ static struct omap_hwmod_ocp_if *omap54x
25863 &omap54xx_l4_per__uart4,
25864 &omap54xx_l4_per__uart5,
25865 &omap54xx_l4_per__uart6,
25866 + &omap54xx_l4_cfg__usb_host_hs,
25867 + &omap54xx_l4_cfg__usb_tll_hs,
25868 &omap54xx_l4_cfg__usb_otg_ss,
25869 &omap54xx_l4_wkup__wd_timer2,
25870 + &omap54xx_l4_cfg__ocp2scp3,
25871 + &omap54xx_l4_cfg__sata,
25872 NULL,
25873 };
25874
25875 --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
25876 +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
25877 @@ -242,7 +242,6 @@ static struct omap_hwmod dra7xx_counter_
25878 .class = &dra7xx_counter_hwmod_class,
25879 .clkdm_name = "wkupaon_clkdm",
25880 .flags = HWMOD_SWSUP_SIDLE,
25881 - .main_clk = "wkupaon_iclk_mux",
25882 .prcm = {
25883 .omap4 = {
25884 .clkctrl_offs = DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
25885 @@ -273,6 +272,56 @@ static struct omap_hwmod dra7xx_ctrl_mod
25886 };
25887
25888 /*
25889 + * 'gmac' class
25890 + * cpsw/gmac sub system
25891 + */
25892 +static struct omap_hwmod_class_sysconfig dra7xx_gmac_sysc = {
25893 + .rev_offs = 0x0,
25894 + .sysc_offs = 0x8,
25895 + .syss_offs = 0x4,
25896 + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
25897 + SYSS_HAS_RESET_STATUS),
25898 + .idlemodes = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
25899 + MSTANDBY_NO),
25900 + .sysc_fields = &omap_hwmod_sysc_type3,
25901 +};
25902 +
25903 +static struct omap_hwmod_class dra7xx_gmac_hwmod_class = {
25904 + .name = "gmac",
25905 + .sysc = &dra7xx_gmac_sysc,
25906 +};
25907 +
25908 +static struct omap_hwmod dra7xx_gmac_hwmod = {
25909 + .name = "gmac",
25910 + .class = &dra7xx_gmac_hwmod_class,
25911 + .clkdm_name = "gmac_clkdm",
25912 + .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
25913 + .main_clk = "dpll_gmac_ck",
25914 + .mpu_rt_idx = 1,
25915 + .prcm = {
25916 + .omap4 = {
25917 + .clkctrl_offs = DRA7XX_CM_GMAC_GMAC_CLKCTRL_OFFSET,
25918 + .context_offs = DRA7XX_RM_GMAC_GMAC_CONTEXT_OFFSET,
25919 + .modulemode = MODULEMODE_SWCTRL,
25920 + },
25921 + },
25922 +};
25923 +
25924 +/*
25925 + * 'mdio' class
25926 + */
25927 +static struct omap_hwmod_class dra7xx_mdio_hwmod_class = {
25928 + .name = "davinci_mdio",
25929 +};
25930 +
25931 +static struct omap_hwmod dra7xx_mdio_hwmod = {
25932 + .name = "davinci_mdio",
25933 + .class = &dra7xx_mdio_hwmod_class,
25934 + .clkdm_name = "gmac_clkdm",
25935 + .main_clk = "dpll_gmac_ck",
25936 +};
25937 +
25938 +/*
25939 * 'dcan' class
25940 *
25941 */
25942 @@ -325,8 +374,8 @@ static struct omap_hwmod_class_sysconfig
25943 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
25944 SYSS_HAS_RESET_STATUS),
25945 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
25946 - SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
25947 - MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
25948 + MSTANDBY_FORCE | MSTANDBY_NO |
25949 + MSTANDBY_SMART),
25950 .sysc_fields = &omap_hwmod_sysc_type1,
25951 };
25952
25953 @@ -356,7 +405,6 @@ static struct omap_hwmod dra7xx_dma_syst
25954 .class = &dra7xx_dma_hwmod_class,
25955 .clkdm_name = "dma_clkdm",
25956 .mpu_irqs = dra7xx_dma_system_irqs,
25957 - .main_clk = "l3_iclk_div",
25958 .prcm = {
25959 .omap4 = {
25960 .clkctrl_offs = DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET,
25961 @@ -561,6 +609,40 @@ static struct omap_hwmod_class dra7xx_gp
25962 .rev = 2,
25963 };
25964
25965 +static struct omap_hwmod_class_sysconfig dra7xx_aes_sysc = {
25966 + .rev_offs = 0x0080,
25967 + .sysc_offs = 0x0084,
25968 + .syss_offs = 0x0088,
25969 + .sysc_flags = (SYSC_HAS_AUTOIDLE |
25970 + SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
25971 + SYSS_HAS_RESET_STATUS),
25972 + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
25973 + .sysc_fields = &omap_hwmod_sysc_type4,
25974 +};
25975 +
25976 +static struct omap_hwmod_class_sysconfig dra7xx_des_sysc = {
25977 + .rev_offs = 0x0030,
25978 + .sysc_offs = 0x0034,
25979 + .syss_offs = 0x0038,
25980 + .sysc_flags = (SYSC_HAS_AUTOIDLE |
25981 + SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
25982 + SYSS_HAS_RESET_STATUS),
25983 + .idlemodes = (SIDLE_FORCE | SIDLE_NO),
25984 + .sysc_fields = &omap_hwmod_sysc_type4,
25985 +};
25986 +
25987 +static struct omap_hwmod_class dra7xx_aes_hwmod_class = {
25988 + .name = "aes",
25989 + .sysc = &dra7xx_aes_sysc,
25990 + .rev = 2,
25991 +};
25992 +
25993 +static struct omap_hwmod_class dra7xx_des_hwmod_class = {
25994 + .name = "des",
25995 + .sysc = &dra7xx_des_sysc,
25996 + .rev = 2,
25997 +};
25998 +
25999 /* gpio dev_attr */
26000 static struct omap_gpio_dev_attr gpio_dev_attr = {
26001 .bank_width = 32,
26002 @@ -568,15 +650,11 @@ static struct omap_gpio_dev_attr gpio_de
26003 };
26004
26005 /* gpio1 */
26006 -static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
26007 - { .role = "dbclk", .clk = "gpio1_dbclk" },
26008 -};
26009
26010 static struct omap_hwmod dra7xx_gpio1_hwmod = {
26011 .name = "gpio1",
26012 .class = &dra7xx_gpio_hwmod_class,
26013 .clkdm_name = "wkupaon_clkdm",
26014 - .main_clk = "wkupaon_iclk_mux",
26015 .prcm = {
26016 .omap4 = {
26017 .clkctrl_offs = DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET,
26018 @@ -584,22 +662,16 @@ static struct omap_hwmod dra7xx_gpio1_hw
26019 .modulemode = MODULEMODE_HWCTRL,
26020 },
26021 },
26022 - .opt_clks = gpio1_opt_clks,
26023 - .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
26024 .dev_attr = &gpio_dev_attr,
26025 };
26026
26027 /* gpio2 */
26028 -static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
26029 - { .role = "dbclk", .clk = "gpio2_dbclk" },
26030 -};
26031
26032 static struct omap_hwmod dra7xx_gpio2_hwmod = {
26033 .name = "gpio2",
26034 .class = &dra7xx_gpio_hwmod_class,
26035 .clkdm_name = "l4per_clkdm",
26036 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
26037 - .main_clk = "l3_iclk_div",
26038 .prcm = {
26039 .omap4 = {
26040 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
26041 @@ -607,22 +679,16 @@ static struct omap_hwmod dra7xx_gpio2_hw
26042 .modulemode = MODULEMODE_HWCTRL,
26043 },
26044 },
26045 - .opt_clks = gpio2_opt_clks,
26046 - .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
26047 .dev_attr = &gpio_dev_attr,
26048 };
26049
26050 /* gpio3 */
26051 -static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
26052 - { .role = "dbclk", .clk = "gpio3_dbclk" },
26053 -};
26054
26055 static struct omap_hwmod dra7xx_gpio3_hwmod = {
26056 .name = "gpio3",
26057 .class = &dra7xx_gpio_hwmod_class,
26058 .clkdm_name = "l4per_clkdm",
26059 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
26060 - .main_clk = "l3_iclk_div",
26061 .prcm = {
26062 .omap4 = {
26063 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
26064 @@ -630,22 +696,16 @@ static struct omap_hwmod dra7xx_gpio3_hw
26065 .modulemode = MODULEMODE_HWCTRL,
26066 },
26067 },
26068 - .opt_clks = gpio3_opt_clks,
26069 - .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
26070 .dev_attr = &gpio_dev_attr,
26071 };
26072
26073 /* gpio4 */
26074 -static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
26075 - { .role = "dbclk", .clk = "gpio4_dbclk" },
26076 -};
26077
26078 static struct omap_hwmod dra7xx_gpio4_hwmod = {
26079 .name = "gpio4",
26080 .class = &dra7xx_gpio_hwmod_class,
26081 .clkdm_name = "l4per_clkdm",
26082 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
26083 - .main_clk = "l3_iclk_div",
26084 .prcm = {
26085 .omap4 = {
26086 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
26087 @@ -653,22 +713,16 @@ static struct omap_hwmod dra7xx_gpio4_hw
26088 .modulemode = MODULEMODE_HWCTRL,
26089 },
26090 },
26091 - .opt_clks = gpio4_opt_clks,
26092 - .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
26093 .dev_attr = &gpio_dev_attr,
26094 };
26095
26096 /* gpio5 */
26097 -static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
26098 - { .role = "dbclk", .clk = "gpio5_dbclk" },
26099 -};
26100
26101 static struct omap_hwmod dra7xx_gpio5_hwmod = {
26102 .name = "gpio5",
26103 .class = &dra7xx_gpio_hwmod_class,
26104 .clkdm_name = "l4per_clkdm",
26105 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
26106 - .main_clk = "l3_iclk_div",
26107 .prcm = {
26108 .omap4 = {
26109 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
26110 @@ -676,22 +730,16 @@ static struct omap_hwmod dra7xx_gpio5_hw
26111 .modulemode = MODULEMODE_HWCTRL,
26112 },
26113 },
26114 - .opt_clks = gpio5_opt_clks,
26115 - .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
26116 .dev_attr = &gpio_dev_attr,
26117 };
26118
26119 /* gpio6 */
26120 -static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
26121 - { .role = "dbclk", .clk = "gpio6_dbclk" },
26122 -};
26123
26124 static struct omap_hwmod dra7xx_gpio6_hwmod = {
26125 .name = "gpio6",
26126 .class = &dra7xx_gpio_hwmod_class,
26127 .clkdm_name = "l4per_clkdm",
26128 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
26129 - .main_clk = "l3_iclk_div",
26130 .prcm = {
26131 .omap4 = {
26132 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
26133 @@ -699,22 +747,16 @@ static struct omap_hwmod dra7xx_gpio6_hw
26134 .modulemode = MODULEMODE_HWCTRL,
26135 },
26136 },
26137 - .opt_clks = gpio6_opt_clks,
26138 - .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
26139 .dev_attr = &gpio_dev_attr,
26140 };
26141
26142 /* gpio7 */
26143 -static struct omap_hwmod_opt_clk gpio7_opt_clks[] = {
26144 - { .role = "dbclk", .clk = "gpio7_dbclk" },
26145 -};
26146
26147 static struct omap_hwmod dra7xx_gpio7_hwmod = {
26148 .name = "gpio7",
26149 .class = &dra7xx_gpio_hwmod_class,
26150 .clkdm_name = "l4per_clkdm",
26151 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
26152 - .main_clk = "l3_iclk_div",
26153 .prcm = {
26154 .omap4 = {
26155 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET,
26156 @@ -722,22 +764,16 @@ static struct omap_hwmod dra7xx_gpio7_hw
26157 .modulemode = MODULEMODE_HWCTRL,
26158 },
26159 },
26160 - .opt_clks = gpio7_opt_clks,
26161 - .opt_clks_cnt = ARRAY_SIZE(gpio7_opt_clks),
26162 .dev_attr = &gpio_dev_attr,
26163 };
26164
26165 /* gpio8 */
26166 -static struct omap_hwmod_opt_clk gpio8_opt_clks[] = {
26167 - { .role = "dbclk", .clk = "gpio8_dbclk" },
26168 -};
26169
26170 static struct omap_hwmod dra7xx_gpio8_hwmod = {
26171 .name = "gpio8",
26172 .class = &dra7xx_gpio_hwmod_class,
26173 .clkdm_name = "l4per_clkdm",
26174 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
26175 - .main_clk = "l3_iclk_div",
26176 .prcm = {
26177 .omap4 = {
26178 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET,
26179 @@ -745,11 +781,35 @@ static struct omap_hwmod dra7xx_gpio8_hw
26180 .modulemode = MODULEMODE_HWCTRL,
26181 },
26182 },
26183 - .opt_clks = gpio8_opt_clks,
26184 - .opt_clks_cnt = ARRAY_SIZE(gpio8_opt_clks),
26185 .dev_attr = &gpio_dev_attr,
26186 };
26187
26188 +static struct omap_hwmod dra7xx_aes_hwmod = {
26189 + .name = "aes",
26190 + .class = &dra7xx_aes_hwmod_class,
26191 + .clkdm_name = "l4sec_clkdm",
26192 + .prcm = {
26193 + .omap4 = {
26194 + .clkctrl_offs = DRA7XX_CM_L4SEC_AES1_CLKCTRL_OFFSET,
26195 + .context_offs = DRA7XX_RM_L4SEC_AES1_CONTEXT_OFFSET,
26196 + .modulemode = MODULEMODE_HWCTRL,
26197 + },
26198 + },
26199 +};
26200 +
26201 +static struct omap_hwmod dra7xx_des_hwmod = {
26202 + .name = "des",
26203 + .class = &dra7xx_des_hwmod_class,
26204 + .clkdm_name = "l4sec_clkdm",
26205 + .prcm = {
26206 + .omap4 = {
26207 + .clkctrl_offs = DRA7XX_CM_L4SEC_DES3DES_CLKCTRL_OFFSET,
26208 + .context_offs = DRA7XX_RM_L4SEC_DES3DES_CONTEXT_OFFSET,
26209 + .modulemode = MODULEMODE_HWCTRL,
26210 + },
26211 + },
26212 +};
26213 +
26214 /*
26215 * 'gpmc' class
26216 *
26217 @@ -859,7 +919,6 @@ static struct omap_hwmod dra7xx_i2c1_hwm
26218 .class = &dra7xx_i2c_hwmod_class,
26219 .clkdm_name = "l4per_clkdm",
26220 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
26221 - .main_clk = "func_96m_fclk",
26222 .prcm = {
26223 .omap4 = {
26224 .clkctrl_offs = DRA7XX_CM_L4PER_I2C1_CLKCTRL_OFFSET,
26225 @@ -876,7 +935,6 @@ static struct omap_hwmod dra7xx_i2c2_hwm
26226 .class = &dra7xx_i2c_hwmod_class,
26227 .clkdm_name = "l4per_clkdm",
26228 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
26229 - .main_clk = "func_96m_fclk",
26230 .prcm = {
26231 .omap4 = {
26232 .clkctrl_offs = DRA7XX_CM_L4PER_I2C2_CLKCTRL_OFFSET,
26233 @@ -893,7 +951,6 @@ static struct omap_hwmod dra7xx_i2c3_hwm
26234 .class = &dra7xx_i2c_hwmod_class,
26235 .clkdm_name = "l4per_clkdm",
26236 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
26237 - .main_clk = "func_96m_fclk",
26238 .prcm = {
26239 .omap4 = {
26240 .clkctrl_offs = DRA7XX_CM_L4PER_I2C3_CLKCTRL_OFFSET,
26241 @@ -910,7 +967,6 @@ static struct omap_hwmod dra7xx_i2c4_hwm
26242 .class = &dra7xx_i2c_hwmod_class,
26243 .clkdm_name = "l4per_clkdm",
26244 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
26245 - .main_clk = "func_96m_fclk",
26246 .prcm = {
26247 .omap4 = {
26248 .clkctrl_offs = DRA7XX_CM_L4PER_I2C4_CLKCTRL_OFFSET,
26249 @@ -927,7 +983,6 @@ static struct omap_hwmod dra7xx_i2c5_hwm
26250 .class = &dra7xx_i2c_hwmod_class,
26251 .clkdm_name = "ipu_clkdm",
26252 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
26253 - .main_clk = "func_96m_fclk",
26254 .prcm = {
26255 .omap4 = {
26256 .clkctrl_offs = DRA7XX_CM_IPU_I2C5_CLKCTRL_OFFSET,
26257 @@ -939,6 +994,207 @@ static struct omap_hwmod dra7xx_i2c5_hwm
26258 };
26259
26260 /*
26261 + * 'mailbox' class
26262 + *
26263 + */
26264 +
26265 +static struct omap_hwmod_class_sysconfig dra7xx_mailbox_sysc = {
26266 + .rev_offs = 0x0000,
26267 + .sysc_offs = 0x0010,
26268 + .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
26269 + SYSC_HAS_SOFTRESET),
26270 + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
26271 + .sysc_fields = &omap_hwmod_sysc_type2,
26272 +};
26273 +
26274 +static struct omap_hwmod_class dra7xx_mailbox_hwmod_class = {
26275 + .name = "mailbox",
26276 + .sysc = &dra7xx_mailbox_sysc,
26277 +};
26278 +
26279 +/* mailbox1 */
26280 +static struct omap_hwmod dra7xx_mailbox1_hwmod = {
26281 + .name = "mailbox1",
26282 + .class = &dra7xx_mailbox_hwmod_class,
26283 + .clkdm_name = "l4cfg_clkdm",
26284 + .main_clk = "l3_iclk_div",
26285 + .prcm = {
26286 + .omap4 = {
26287 + .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL_OFFSET,
26288 + .context_offs = DRA7XX_RM_L4CFG_MAILBOX1_CONTEXT_OFFSET,
26289 + },
26290 + },
26291 +};
26292 +
26293 +/* mailbox2 */
26294 +static struct omap_hwmod dra7xx_mailbox2_hwmod = {
26295 + .name = "mailbox2",
26296 + .class = &dra7xx_mailbox_hwmod_class,
26297 + .clkdm_name = "l4cfg_clkdm",
26298 + .main_clk = "l3_iclk_div",
26299 + .prcm = {
26300 + .omap4 = {
26301 + .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL_OFFSET,
26302 + .context_offs = DRA7XX_RM_L4CFG_MAILBOX2_CONTEXT_OFFSET,
26303 + },
26304 + },
26305 +};
26306 +
26307 +/* mailbox3 */
26308 +static struct omap_hwmod dra7xx_mailbox3_hwmod = {
26309 + .name = "mailbox3",
26310 + .class = &dra7xx_mailbox_hwmod_class,
26311 + .clkdm_name = "l4cfg_clkdm",
26312 + .main_clk = "l3_iclk_div",
26313 + .prcm = {
26314 + .omap4 = {
26315 + .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL_OFFSET,
26316 + .context_offs = DRA7XX_RM_L4CFG_MAILBOX3_CONTEXT_OFFSET,
26317 + },
26318 + },
26319 +};
26320 +
26321 +/* mailbox4 */
26322 +static struct omap_hwmod dra7xx_mailbox4_hwmod = {
26323 + .name = "mailbox4",
26324 + .class = &dra7xx_mailbox_hwmod_class,
26325 + .clkdm_name = "l4cfg_clkdm",
26326 + .main_clk = "l3_iclk_div",
26327 + .prcm = {
26328 + .omap4 = {
26329 + .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL_OFFSET,
26330 + .context_offs = DRA7XX_RM_L4CFG_MAILBOX4_CONTEXT_OFFSET,
26331 + },
26332 + },
26333 +};
26334 +
26335 +/* mailbox5 */
26336 +static struct omap_hwmod dra7xx_mailbox5_hwmod = {
26337 + .name = "mailbox5",
26338 + .class = &dra7xx_mailbox_hwmod_class,
26339 + .clkdm_name = "l4cfg_clkdm",
26340 + .main_clk = "l3_iclk_div",
26341 + .prcm = {
26342 + .omap4 = {
26343 + .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL_OFFSET,
26344 + .context_offs = DRA7XX_RM_L4CFG_MAILBOX5_CONTEXT_OFFSET,
26345 + },
26346 + },
26347 +};
26348 +
26349 +/* mailbox6 */
26350 +static struct omap_hwmod dra7xx_mailbox6_hwmod = {
26351 + .name = "mailbox6",
26352 + .class = &dra7xx_mailbox_hwmod_class,
26353 + .clkdm_name = "l4cfg_clkdm",
26354 + .main_clk = "l3_iclk_div",
26355 + .prcm = {
26356 + .omap4 = {
26357 + .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL_OFFSET,
26358 + .context_offs = DRA7XX_RM_L4CFG_MAILBOX6_CONTEXT_OFFSET,
26359 + },
26360 + },
26361 +};
26362 +
26363 +/* mailbox7 */
26364 +static struct omap_hwmod dra7xx_mailbox7_hwmod = {
26365 + .name = "mailbox7",
26366 + .class = &dra7xx_mailbox_hwmod_class,
26367 + .clkdm_name = "l4cfg_clkdm",
26368 + .main_clk = "l3_iclk_div",
26369 + .prcm = {
26370 + .omap4 = {
26371 + .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL_OFFSET,
26372 + .context_offs = DRA7XX_RM_L4CFG_MAILBOX7_CONTEXT_OFFSET,
26373 + },
26374 + },
26375 +};
26376 +
26377 +/* mailbox8 */
26378 +static struct omap_hwmod dra7xx_mailbox8_hwmod = {
26379 + .name = "mailbox8",
26380 + .class = &dra7xx_mailbox_hwmod_class,
26381 + .clkdm_name = "l4cfg_clkdm",
26382 + .main_clk = "l3_iclk_div",
26383 + .prcm = {
26384 + .omap4 = {
26385 + .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL_OFFSET,
26386 + .context_offs = DRA7XX_RM_L4CFG_MAILBOX8_CONTEXT_OFFSET,
26387 + },
26388 + },
26389 +};
26390 +
26391 +/* mailbox9 */
26392 +static struct omap_hwmod dra7xx_mailbox9_hwmod = {
26393 + .name = "mailbox9",
26394 + .class = &dra7xx_mailbox_hwmod_class,
26395 + .clkdm_name = "l4cfg_clkdm",
26396 + .main_clk = "l3_iclk_div",
26397 + .prcm = {
26398 + .omap4 = {
26399 + .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL_OFFSET,
26400 + .context_offs = DRA7XX_RM_L4CFG_MAILBOX9_CONTEXT_OFFSET,
26401 + },
26402 + },
26403 +};
26404 +
26405 +/* mailbox10 */
26406 +static struct omap_hwmod dra7xx_mailbox10_hwmod = {
26407 + .name = "mailbox10",
26408 + .class = &dra7xx_mailbox_hwmod_class,
26409 + .clkdm_name = "l4cfg_clkdm",
26410 + .main_clk = "l3_iclk_div",
26411 + .prcm = {
26412 + .omap4 = {
26413 + .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL_OFFSET,
26414 + .context_offs = DRA7XX_RM_L4CFG_MAILBOX10_CONTEXT_OFFSET,
26415 + },
26416 + },
26417 +};
26418 +
26419 +/* mailbox11 */
26420 +static struct omap_hwmod dra7xx_mailbox11_hwmod = {
26421 + .name = "mailbox11",
26422 + .class = &dra7xx_mailbox_hwmod_class,
26423 + .clkdm_name = "l4cfg_clkdm",
26424 + .main_clk = "l3_iclk_div",
26425 + .prcm = {
26426 + .omap4 = {
26427 + .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL_OFFSET,
26428 + .context_offs = DRA7XX_RM_L4CFG_MAILBOX11_CONTEXT_OFFSET,
26429 + },
26430 + },
26431 +};
26432 +
26433 +/* mailbox12 */
26434 +static struct omap_hwmod dra7xx_mailbox12_hwmod = {
26435 + .name = "mailbox12",
26436 + .class = &dra7xx_mailbox_hwmod_class,
26437 + .clkdm_name = "l4cfg_clkdm",
26438 + .main_clk = "l3_iclk_div",
26439 + .prcm = {
26440 + .omap4 = {
26441 + .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL_OFFSET,
26442 + .context_offs = DRA7XX_RM_L4CFG_MAILBOX12_CONTEXT_OFFSET,
26443 + },
26444 + },
26445 +};
26446 +
26447 +/* mailbox13 */
26448 +static struct omap_hwmod dra7xx_mailbox13_hwmod = {
26449 + .name = "mailbox13",
26450 + .class = &dra7xx_mailbox_hwmod_class,
26451 + .clkdm_name = "l4cfg_clkdm",
26452 + .main_clk = "l3_iclk_div",
26453 + .prcm = {
26454 + .omap4 = {
26455 + .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL_OFFSET,
26456 + .context_offs = DRA7XX_RM_L4CFG_MAILBOX13_CONTEXT_OFFSET,
26457 + },
26458 + },
26459 +};
26460 +
26461 +/*
26462 * 'mcspi' class
26463 *
26464 */
26465 @@ -969,7 +1225,6 @@ static struct omap_hwmod dra7xx_mcspi1_h
26466 .name = "mcspi1",
26467 .class = &dra7xx_mcspi_hwmod_class,
26468 .clkdm_name = "l4per_clkdm",
26469 - .main_clk = "func_48m_fclk",
26470 .prcm = {
26471 .omap4 = {
26472 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
26473 @@ -990,7 +1245,6 @@ static struct omap_hwmod dra7xx_mcspi2_h
26474 .name = "mcspi2",
26475 .class = &dra7xx_mcspi_hwmod_class,
26476 .clkdm_name = "l4per_clkdm",
26477 - .main_clk = "func_48m_fclk",
26478 .prcm = {
26479 .omap4 = {
26480 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
26481 @@ -1011,7 +1265,6 @@ static struct omap_hwmod dra7xx_mcspi3_h
26482 .name = "mcspi3",
26483 .class = &dra7xx_mcspi_hwmod_class,
26484 .clkdm_name = "l4per_clkdm",
26485 - .main_clk = "func_48m_fclk",
26486 .prcm = {
26487 .omap4 = {
26488 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
26489 @@ -1032,7 +1285,6 @@ static struct omap_hwmod dra7xx_mcspi4_h
26490 .name = "mcspi4",
26491 .class = &dra7xx_mcspi_hwmod_class,
26492 .clkdm_name = "l4per_clkdm",
26493 - .main_clk = "func_48m_fclk",
26494 .prcm = {
26495 .omap4 = {
26496 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
26497 @@ -1066,9 +1318,6 @@ static struct omap_hwmod_class dra7xx_mm
26498 };
26499
26500 /* mmc1 */
26501 -static struct omap_hwmod_opt_clk mmc1_opt_clks[] = {
26502 - { .role = "clk32k", .clk = "mmc1_clk32k" },
26503 -};
26504
26505 /* mmc1 dev_attr */
26506 static struct omap_mmc_dev_attr mmc1_dev_attr = {
26507 @@ -1079,7 +1328,6 @@ static struct omap_hwmod dra7xx_mmc1_hwm
26508 .name = "mmc1",
26509 .class = &dra7xx_mmc_hwmod_class,
26510 .clkdm_name = "l3init_clkdm",
26511 - .main_clk = "mmc1_fclk_div",
26512 .prcm = {
26513 .omap4 = {
26514 .clkctrl_offs = DRA7XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
26515 @@ -1087,21 +1335,15 @@ static struct omap_hwmod dra7xx_mmc1_hwm
26516 .modulemode = MODULEMODE_SWCTRL,
26517 },
26518 },
26519 - .opt_clks = mmc1_opt_clks,
26520 - .opt_clks_cnt = ARRAY_SIZE(mmc1_opt_clks),
26521 .dev_attr = &mmc1_dev_attr,
26522 };
26523
26524 /* mmc2 */
26525 -static struct omap_hwmod_opt_clk mmc2_opt_clks[] = {
26526 - { .role = "clk32k", .clk = "mmc2_clk32k" },
26527 -};
26528
26529 static struct omap_hwmod dra7xx_mmc2_hwmod = {
26530 .name = "mmc2",
26531 .class = &dra7xx_mmc_hwmod_class,
26532 .clkdm_name = "l3init_clkdm",
26533 - .main_clk = "mmc2_fclk_div",
26534 .prcm = {
26535 .omap4 = {
26536 .clkctrl_offs = DRA7XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
26537 @@ -1109,20 +1351,14 @@ static struct omap_hwmod dra7xx_mmc2_hwm
26538 .modulemode = MODULEMODE_SWCTRL,
26539 },
26540 },
26541 - .opt_clks = mmc2_opt_clks,
26542 - .opt_clks_cnt = ARRAY_SIZE(mmc2_opt_clks),
26543 };
26544
26545 /* mmc3 */
26546 -static struct omap_hwmod_opt_clk mmc3_opt_clks[] = {
26547 - { .role = "clk32k", .clk = "mmc3_clk32k" },
26548 -};
26549
26550 static struct omap_hwmod dra7xx_mmc3_hwmod = {
26551 .name = "mmc3",
26552 .class = &dra7xx_mmc_hwmod_class,
26553 .clkdm_name = "l4per_clkdm",
26554 - .main_clk = "mmc3_gfclk_div",
26555 .prcm = {
26556 .omap4 = {
26557 .clkctrl_offs = DRA7XX_CM_L4PER_MMC3_CLKCTRL_OFFSET,
26558 @@ -1130,20 +1366,14 @@ static struct omap_hwmod dra7xx_mmc3_hwm
26559 .modulemode = MODULEMODE_SWCTRL,
26560 },
26561 },
26562 - .opt_clks = mmc3_opt_clks,
26563 - .opt_clks_cnt = ARRAY_SIZE(mmc3_opt_clks),
26564 };
26565
26566 /* mmc4 */
26567 -static struct omap_hwmod_opt_clk mmc4_opt_clks[] = {
26568 - { .role = "clk32k", .clk = "mmc4_clk32k" },
26569 -};
26570
26571 static struct omap_hwmod dra7xx_mmc4_hwmod = {
26572 .name = "mmc4",
26573 .class = &dra7xx_mmc_hwmod_class,
26574 .clkdm_name = "l4per_clkdm",
26575 - .main_clk = "mmc4_gfclk_div",
26576 .prcm = {
26577 .omap4 = {
26578 .clkctrl_offs = DRA7XX_CM_L4PER_MMC4_CLKCTRL_OFFSET,
26579 @@ -1151,8 +1381,6 @@ static struct omap_hwmod dra7xx_mmc4_hwm
26580 .modulemode = MODULEMODE_SWCTRL,
26581 },
26582 },
26583 - .opt_clks = mmc4_opt_clks,
26584 - .opt_clks_cnt = ARRAY_SIZE(mmc4_opt_clks),
26585 };
26586
26587 /*
26588 @@ -1215,6 +1443,30 @@ static struct omap_hwmod dra7xx_ocp2scp1
26589 },
26590 };
26591
26592 +/* ocp2scp3 */
26593 +static struct omap_hwmod dra7xx_ocp2scp3_hwmod;
26594 +
26595 +/* l4_cfg -> ocp2scp3 */
26596 +static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3 = {
26597 + .master = &dra7xx_l4_cfg_hwmod,
26598 + .slave = &dra7xx_ocp2scp3_hwmod,
26599 + .clk = "l4_root_clk_div",
26600 + .user = OCP_USER_MPU | OCP_USER_SDMA,
26601 +};
26602 +
26603 +static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
26604 + .name = "ocp2scp3",
26605 + .class = &dra7xx_ocp2scp_hwmod_class,
26606 + .clkdm_name = "l3init_clkdm",
26607 + .prcm = {
26608 + .omap4 = {
26609 + .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
26610 + .context_offs = DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
26611 + .modulemode = MODULEMODE_HWCTRL,
26612 + },
26613 + },
26614 +};
26615 +
26616 /*
26617 * 'qspi' class
26618 *
26619 @@ -1249,6 +1501,38 @@ static struct omap_hwmod dra7xx_qspi_hwm
26620 };
26621
26622 /*
26623 + * 'rtcss' class
26624 + *
26625 + */
26626 +static struct omap_hwmod_class_sysconfig dra7xx_rtcss_sysc = {
26627 + .sysc_offs = 0x0078,
26628 + .sysc_flags = SYSC_HAS_SIDLEMODE,
26629 + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
26630 + SIDLE_SMART_WKUP),
26631 + .sysc_fields = &omap_hwmod_sysc_type3,
26632 +};
26633 +
26634 +static struct omap_hwmod_class dra7xx_rtcss_hwmod_class = {
26635 + .name = "rtcss",
26636 + .sysc = &dra7xx_rtcss_sysc,
26637 +};
26638 +
26639 +/* rtcss */
26640 +static struct omap_hwmod dra7xx_rtcss_hwmod = {
26641 + .name = "rtcss",
26642 + .class = &dra7xx_rtcss_hwmod_class,
26643 + .clkdm_name = "rtc_clkdm",
26644 + .main_clk = "sys_32k_ck",
26645 + .prcm = {
26646 + .omap4 = {
26647 + .clkctrl_offs = DRA7XX_CM_RTC_RTCSS_CLKCTRL_OFFSET,
26648 + .context_offs = DRA7XX_RM_RTC_RTCSS_CONTEXT_OFFSET,
26649 + .modulemode = MODULEMODE_SWCTRL,
26650 + },
26651 + },
26652 +};
26653 +
26654 +/*
26655 * 'sata' class
26656 *
26657 */
26658 @@ -1268,9 +1552,6 @@ static struct omap_hwmod_class dra7xx_sa
26659 };
26660
26661 /* sata */
26662 -static struct omap_hwmod_opt_clk sata_opt_clks[] = {
26663 - { .role = "ref_clk", .clk = "sata_ref_clk" },
26664 -};
26665
26666 static struct omap_hwmod dra7xx_sata_hwmod = {
26667 .name = "sata",
26668 @@ -1285,8 +1566,6 @@ static struct omap_hwmod dra7xx_sata_hwm
26669 .modulemode = MODULEMODE_SWCTRL,
26670 },
26671 },
26672 - .opt_clks = sata_opt_clks,
26673 - .opt_clks_cnt = ARRAY_SIZE(sata_opt_clks),
26674 };
26675
26676 /*
26677 @@ -1449,7 +1728,6 @@ static struct omap_hwmod dra7xx_timer1_h
26678 .name = "timer1",
26679 .class = &dra7xx_timer_1ms_hwmod_class,
26680 .clkdm_name = "wkupaon_clkdm",
26681 - .main_clk = "timer1_gfclk_mux",
26682 .prcm = {
26683 .omap4 = {
26684 .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
26685 @@ -1464,7 +1742,6 @@ static struct omap_hwmod dra7xx_timer2_h
26686 .name = "timer2",
26687 .class = &dra7xx_timer_1ms_hwmod_class,
26688 .clkdm_name = "l4per_clkdm",
26689 - .main_clk = "timer2_gfclk_mux",
26690 .prcm = {
26691 .omap4 = {
26692 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET,
26693 @@ -1479,7 +1756,6 @@ static struct omap_hwmod dra7xx_timer3_h
26694 .name = "timer3",
26695 .class = &dra7xx_timer_hwmod_class,
26696 .clkdm_name = "l4per_clkdm",
26697 - .main_clk = "timer3_gfclk_mux",
26698 .prcm = {
26699 .omap4 = {
26700 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
26701 @@ -1494,7 +1770,6 @@ static struct omap_hwmod dra7xx_timer4_h
26702 .name = "timer4",
26703 .class = &dra7xx_timer_secure_hwmod_class,
26704 .clkdm_name = "l4per_clkdm",
26705 - .main_clk = "timer4_gfclk_mux",
26706 .prcm = {
26707 .omap4 = {
26708 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
26709 @@ -1509,7 +1784,6 @@ static struct omap_hwmod dra7xx_timer5_h
26710 .name = "timer5",
26711 .class = &dra7xx_timer_hwmod_class,
26712 .clkdm_name = "ipu_clkdm",
26713 - .main_clk = "timer5_gfclk_mux",
26714 .prcm = {
26715 .omap4 = {
26716 .clkctrl_offs = DRA7XX_CM_IPU_TIMER5_CLKCTRL_OFFSET,
26717 @@ -1524,7 +1798,6 @@ static struct omap_hwmod dra7xx_timer6_h
26718 .name = "timer6",
26719 .class = &dra7xx_timer_hwmod_class,
26720 .clkdm_name = "ipu_clkdm",
26721 - .main_clk = "timer6_gfclk_mux",
26722 .prcm = {
26723 .omap4 = {
26724 .clkctrl_offs = DRA7XX_CM_IPU_TIMER6_CLKCTRL_OFFSET,
26725 @@ -1539,7 +1812,6 @@ static struct omap_hwmod dra7xx_timer7_h
26726 .name = "timer7",
26727 .class = &dra7xx_timer_hwmod_class,
26728 .clkdm_name = "ipu_clkdm",
26729 - .main_clk = "timer7_gfclk_mux",
26730 .prcm = {
26731 .omap4 = {
26732 .clkctrl_offs = DRA7XX_CM_IPU_TIMER7_CLKCTRL_OFFSET,
26733 @@ -1554,7 +1826,6 @@ static struct omap_hwmod dra7xx_timer8_h
26734 .name = "timer8",
26735 .class = &dra7xx_timer_hwmod_class,
26736 .clkdm_name = "ipu_clkdm",
26737 - .main_clk = "timer8_gfclk_mux",
26738 .prcm = {
26739 .omap4 = {
26740 .clkctrl_offs = DRA7XX_CM_IPU_TIMER8_CLKCTRL_OFFSET,
26741 @@ -1569,7 +1840,6 @@ static struct omap_hwmod dra7xx_timer9_h
26742 .name = "timer9",
26743 .class = &dra7xx_timer_hwmod_class,
26744 .clkdm_name = "l4per_clkdm",
26745 - .main_clk = "timer9_gfclk_mux",
26746 .prcm = {
26747 .omap4 = {
26748 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET,
26749 @@ -1584,7 +1854,6 @@ static struct omap_hwmod dra7xx_timer10_
26750 .name = "timer10",
26751 .class = &dra7xx_timer_1ms_hwmod_class,
26752 .clkdm_name = "l4per_clkdm",
26753 - .main_clk = "timer10_gfclk_mux",
26754 .prcm = {
26755 .omap4 = {
26756 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET,
26757 @@ -1599,7 +1868,6 @@ static struct omap_hwmod dra7xx_timer11_
26758 .name = "timer11",
26759 .class = &dra7xx_timer_hwmod_class,
26760 .clkdm_name = "l4per_clkdm",
26761 - .main_clk = "timer11_gfclk_mux",
26762 .prcm = {
26763 .omap4 = {
26764 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET,
26765 @@ -1636,8 +1904,7 @@ static struct omap_hwmod dra7xx_uart1_hw
26766 .name = "uart1",
26767 .class = &dra7xx_uart_hwmod_class,
26768 .clkdm_name = "l4per_clkdm",
26769 - .main_clk = "uart1_gfclk_mux",
26770 - .flags = HWMOD_SWSUP_SIDLE_ACT,
26771 + .flags = DEBUG_OMAP2UART1_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
26772 .prcm = {
26773 .omap4 = {
26774 .clkctrl_offs = DRA7XX_CM_L4PER_UART1_CLKCTRL_OFFSET,
26775 @@ -1652,7 +1919,6 @@ static struct omap_hwmod dra7xx_uart2_hw
26776 .name = "uart2",
26777 .class = &dra7xx_uart_hwmod_class,
26778 .clkdm_name = "l4per_clkdm",
26779 - .main_clk = "uart2_gfclk_mux",
26780 .flags = HWMOD_SWSUP_SIDLE_ACT,
26781 .prcm = {
26782 .omap4 = {
26783 @@ -1668,7 +1934,6 @@ static struct omap_hwmod dra7xx_uart3_hw
26784 .name = "uart3",
26785 .class = &dra7xx_uart_hwmod_class,
26786 .clkdm_name = "l4per_clkdm",
26787 - .main_clk = "uart3_gfclk_mux",
26788 .flags = HWMOD_SWSUP_SIDLE_ACT,
26789 .prcm = {
26790 .omap4 = {
26791 @@ -1684,7 +1949,6 @@ static struct omap_hwmod dra7xx_uart4_hw
26792 .name = "uart4",
26793 .class = &dra7xx_uart_hwmod_class,
26794 .clkdm_name = "l4per_clkdm",
26795 - .main_clk = "uart4_gfclk_mux",
26796 .flags = HWMOD_SWSUP_SIDLE_ACT,
26797 .prcm = {
26798 .omap4 = {
26799 @@ -1700,7 +1964,6 @@ static struct omap_hwmod dra7xx_uart5_hw
26800 .name = "uart5",
26801 .class = &dra7xx_uart_hwmod_class,
26802 .clkdm_name = "l4per_clkdm",
26803 - .main_clk = "uart5_gfclk_mux",
26804 .flags = HWMOD_SWSUP_SIDLE_ACT,
26805 .prcm = {
26806 .omap4 = {
26807 @@ -1716,7 +1979,6 @@ static struct omap_hwmod dra7xx_uart6_hw
26808 .name = "uart6",
26809 .class = &dra7xx_uart_hwmod_class,
26810 .clkdm_name = "ipu_clkdm",
26811 - .main_clk = "uart6_gfclk_mux",
26812 .flags = HWMOD_SWSUP_SIDLE_ACT,
26813 .prcm = {
26814 .omap4 = {
26815 @@ -1732,8 +1994,20 @@ static struct omap_hwmod dra7xx_uart6_hw
26816 *
26817 */
26818
26819 +static struct omap_hwmod_class_sysconfig dra7xx_usb_otg_ss_sysc = {
26820 + .rev_offs = 0x0000,
26821 + .sysc_offs = 0x0010,
26822 + .sysc_flags = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
26823 + SYSC_HAS_SIDLEMODE),
26824 + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
26825 + SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
26826 + MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
26827 + .sysc_fields = &omap_hwmod_sysc_type2,
26828 +};
26829 +
26830 static struct omap_hwmod_class dra7xx_usb_otg_ss_hwmod_class = {
26831 .name = "usb_otg_ss",
26832 + .sysc = &dra7xx_usb_otg_ss_sysc,
26833 };
26834
26835 /* usb_otg_ss1 */
26836 @@ -1873,7 +2147,6 @@ static struct omap_hwmod dra7xx_wd_timer
26837 .name = "wd_timer2",
26838 .class = &dra7xx_wd_timer_hwmod_class,
26839 .clkdm_name = "wkupaon_clkdm",
26840 - .main_clk = "sys_32k_ck",
26841 .prcm = {
26842 .omap4 = {
26843 .clkctrl_offs = DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET,
26844 @@ -1883,6 +2156,39 @@ static struct omap_hwmod dra7xx_wd_timer
26845 },
26846 };
26847
26848 +/*
26849 + * 'vpe' class
26850 + *
26851 + */
26852 +
26853 +static struct omap_hwmod_class_sysconfig dra7xx_vpe_sysc = {
26854 + .sysc_offs = 0x0010,
26855 + .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
26856 + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
26857 + SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
26858 + MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
26859 + .sysc_fields = &omap_hwmod_sysc_type2,
26860 +};
26861 +
26862 +static struct omap_hwmod_class dra7xx_vpe_hwmod_class = {
26863 + .name = "vpe",
26864 + .sysc = &dra7xx_vpe_sysc,
26865 +};
26866 +
26867 +/* vpe */
26868 +static struct omap_hwmod dra7xx_vpe_hwmod = {
26869 + .name = "vpe",
26870 + .class = &dra7xx_vpe_hwmod_class,
26871 + .clkdm_name = "vpe_clkdm",
26872 + .main_clk = "dpll_core_h23x2_ck",
26873 + .prcm = {
26874 + .omap4 = {
26875 + .clkctrl_offs = DRA7XX_CM_VPE_VPE_CLKCTRL_OFFSET,
26876 + .context_offs = DRA7XX_RM_VPE_VPE_CONTEXT_OFFSET,
26877 + .modulemode = MODULEMODE_HWCTRL,
26878 + },
26879 + },
26880 +};
26881
26882 /*
26883 * Interfaces
26884 @@ -2000,6 +2306,19 @@ static struct omap_hwmod_ocp_if dra7xx_l
26885 .user = OCP_USER_MPU | OCP_USER_SDMA,
26886 };
26887
26888 +static struct omap_hwmod_ocp_if dra7xx_l4_per2__cpgmac0 = {
26889 + .master = &dra7xx_l4_per2_hwmod,
26890 + .slave = &dra7xx_gmac_hwmod,
26891 + .clk = "dpll_gmac_ck",
26892 + .user = OCP_USER_MPU,
26893 +};
26894 +
26895 +static struct omap_hwmod_ocp_if dra7xx_gmac__mdio = {
26896 + .master = &dra7xx_gmac_hwmod,
26897 + .slave = &dra7xx_mdio_hwmod,
26898 + .user = OCP_USER_MPU,
26899 +};
26900 +
26901 /* l4_wkup -> dcan1 */
26902 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__dcan1 = {
26903 .master = &dra7xx_l4_wkup_hwmod,
26904 @@ -2089,6 +2408,14 @@ static struct omap_hwmod_ocp_if dra7xx_l
26905 .user = OCP_USER_MPU | OCP_USER_SDMA,
26906 };
26907
26908 +/* l3_main_1 -> aes */
26909 +static struct omap_hwmod_ocp_if dra7xx_l3_main_1__aes = {
26910 + .master = &dra7xx_l3_main_1_hwmod,
26911 + .slave = &dra7xx_aes_hwmod,
26912 + .clk = "l3_iclk_div",
26913 + .user = OCP_USER_MPU | OCP_USER_SDMA,
26914 +};
26915 +
26916 static struct omap_hwmod_addr_space dra7xx_elm_addrs[] = {
26917 {
26918 .pa_start = 0x48078000,
26919 @@ -2171,6 +2498,14 @@ static struct omap_hwmod_ocp_if dra7xx_l
26920 .user = OCP_USER_MPU | OCP_USER_SDMA,
26921 };
26922
26923 +/* l4_per1 -> des */
26924 +static struct omap_hwmod_ocp_if dra7xx_l4_per1__des = {
26925 + .master = &dra7xx_l4_per1_hwmod,
26926 + .slave = &dra7xx_des_hwmod,
26927 + .clk = "l3_iclk_div",
26928 + .user = OCP_USER_MPU | OCP_USER_SDMA,
26929 +};
26930 +
26931 static struct omap_hwmod_addr_space dra7xx_gpmc_addrs[] = {
26932 {
26933 .pa_start = 0x50000000,
26934 @@ -2247,6 +2582,110 @@ static struct omap_hwmod_ocp_if dra7xx_l
26935 .user = OCP_USER_MPU | OCP_USER_SDMA,
26936 };
26937
26938 +/* l4_cfg -> mailbox1 */
26939 +static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mailbox1 = {
26940 + .master = &dra7xx_l4_cfg_hwmod,
26941 + .slave = &dra7xx_mailbox1_hwmod,
26942 + .clk = "l3_iclk_div",
26943 + .user = OCP_USER_MPU | OCP_USER_SDMA,
26944 +};
26945 +
26946 +/* l4_per3 -> mailbox2 */
26947 +static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox2 = {
26948 + .master = &dra7xx_l4_per3_hwmod,
26949 + .slave = &dra7xx_mailbox2_hwmod,
26950 + .clk = "l3_iclk_div",
26951 + .user = OCP_USER_MPU | OCP_USER_SDMA,
26952 +};
26953 +
26954 +/* l4_per3 -> mailbox3 */
26955 +static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox3 = {
26956 + .master = &dra7xx_l4_per3_hwmod,
26957 + .slave = &dra7xx_mailbox3_hwmod,
26958 + .clk = "l3_iclk_div",
26959 + .user = OCP_USER_MPU | OCP_USER_SDMA,
26960 +};
26961 +
26962 +/* l4_per3 -> mailbox4 */
26963 +static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox4 = {
26964 + .master = &dra7xx_l4_per3_hwmod,
26965 + .slave = &dra7xx_mailbox4_hwmod,
26966 + .clk = "l3_iclk_div",
26967 + .user = OCP_USER_MPU | OCP_USER_SDMA,
26968 +};
26969 +
26970 +/* l4_per3 -> mailbox5 */
26971 +static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox5 = {
26972 + .master = &dra7xx_l4_per3_hwmod,
26973 + .slave = &dra7xx_mailbox5_hwmod,
26974 + .clk = "l3_iclk_div",
26975 + .user = OCP_USER_MPU | OCP_USER_SDMA,
26976 +};
26977 +
26978 +/* l4_per3 -> mailbox6 */
26979 +static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox6 = {
26980 + .master = &dra7xx_l4_per3_hwmod,
26981 + .slave = &dra7xx_mailbox6_hwmod,
26982 + .clk = "l3_iclk_div",
26983 + .user = OCP_USER_MPU | OCP_USER_SDMA,
26984 +};
26985 +
26986 +/* l4_per3 -> mailbox7 */
26987 +static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox7 = {
26988 + .master = &dra7xx_l4_per3_hwmod,
26989 + .slave = &dra7xx_mailbox7_hwmod,
26990 + .clk = "l3_iclk_div",
26991 + .user = OCP_USER_MPU | OCP_USER_SDMA,
26992 +};
26993 +
26994 +/* l4_per3 -> mailbox8 */
26995 +static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox8 = {
26996 + .master = &dra7xx_l4_per3_hwmod,
26997 + .slave = &dra7xx_mailbox8_hwmod,
26998 + .clk = "l3_iclk_div",
26999 + .user = OCP_USER_MPU | OCP_USER_SDMA,
27000 +};
27001 +
27002 +/* l4_per3 -> mailbox9 */
27003 +static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox9 = {
27004 + .master = &dra7xx_l4_per3_hwmod,
27005 + .slave = &dra7xx_mailbox9_hwmod,
27006 + .clk = "l3_iclk_div",
27007 + .user = OCP_USER_MPU | OCP_USER_SDMA,
27008 +};
27009 +
27010 +/* l4_per3 -> mailbox10 */
27011 +static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox10 = {
27012 + .master = &dra7xx_l4_per3_hwmod,
27013 + .slave = &dra7xx_mailbox10_hwmod,
27014 + .clk = "l3_iclk_div",
27015 + .user = OCP_USER_MPU | OCP_USER_SDMA,
27016 +};
27017 +
27018 +/* l4_per3 -> mailbox11 */
27019 +static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox11 = {
27020 + .master = &dra7xx_l4_per3_hwmod,
27021 + .slave = &dra7xx_mailbox11_hwmod,
27022 + .clk = "l3_iclk_div",
27023 + .user = OCP_USER_MPU | OCP_USER_SDMA,
27024 +};
27025 +
27026 +/* l4_per3 -> mailbox12 */
27027 +static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox12 = {
27028 + .master = &dra7xx_l4_per3_hwmod,
27029 + .slave = &dra7xx_mailbox12_hwmod,
27030 + .clk = "l3_iclk_div",
27031 + .user = OCP_USER_MPU | OCP_USER_SDMA,
27032 +};
27033 +
27034 +/* l4_per3 -> mailbox13 */
27035 +static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox13 = {
27036 + .master = &dra7xx_l4_per3_hwmod,
27037 + .slave = &dra7xx_mailbox13_hwmod,
27038 + .clk = "l3_iclk_div",
27039 + .user = OCP_USER_MPU | OCP_USER_SDMA,
27040 +};
27041 +
27042 /* l4_per1 -> mcspi1 */
27043 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi1 = {
27044 .master = &dra7xx_l4_per1_hwmod,
27045 @@ -2319,21 +2758,11 @@ static struct omap_hwmod_ocp_if dra7xx_l
27046 .user = OCP_USER_MPU | OCP_USER_SDMA,
27047 };
27048
27049 -static struct omap_hwmod_addr_space dra7xx_ocp2scp1_addrs[] = {
27050 - {
27051 - .pa_start = 0x4a080000,
27052 - .pa_end = 0x4a08001f,
27053 - .flags = ADDR_TYPE_RT
27054 - },
27055 - { }
27056 -};
27057 -
27058 /* l4_cfg -> ocp2scp1 */
27059 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = {
27060 .master = &dra7xx_l4_cfg_hwmod,
27061 .slave = &dra7xx_ocp2scp1_hwmod,
27062 .clk = "l4_root_clk_div",
27063 - .addr = dra7xx_ocp2scp1_addrs,
27064 .user = OCP_USER_MPU | OCP_USER_SDMA,
27065 };
27066
27067 @@ -2355,6 +2784,14 @@ static struct omap_hwmod_ocp_if dra7xx_l
27068 .user = OCP_USER_MPU | OCP_USER_SDMA,
27069 };
27070
27071 +/* l4_per3 -> rtcss */
27072 +static struct omap_hwmod_ocp_if dra7xx_l4_per3__rtcss = {
27073 + .master = &dra7xx_l4_per3_hwmod,
27074 + .slave = &dra7xx_rtcss_hwmod,
27075 + .clk = "l4_root_clk_div",
27076 + .user = OCP_USER_MPU | OCP_USER_SDMA,
27077 +};
27078 +
27079 static struct omap_hwmod_addr_space dra7xx_sata_addrs[] = {
27080 {
27081 .name = "sysc",
27082 @@ -2636,6 +3073,14 @@ static struct omap_hwmod_ocp_if dra7xx_l
27083 .user = OCP_USER_MPU | OCP_USER_SDMA,
27084 };
27085
27086 +/* l4_per3 -> vpe */
27087 +static struct omap_hwmod_ocp_if dra7xx_l4_per3__vpe = {
27088 + .master = &dra7xx_l4_per3_hwmod,
27089 + .slave = &dra7xx_vpe_hwmod,
27090 + .clk = "l3_iclk_div",
27091 + .user = OCP_USER_MPU | OCP_USER_SDMA,
27092 +};
27093 +
27094 static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
27095 &dra7xx_l3_main_2__l3_instr,
27096 &dra7xx_l4_cfg__l3_main_1,
27097 @@ -2653,10 +3098,13 @@ static struct omap_hwmod_ocp_if *dra7xx_
27098 &dra7xx_l4_wkup__ctrl_module_wkup,
27099 &dra7xx_l4_wkup__dcan1,
27100 &dra7xx_l4_per2__dcan2,
27101 + &dra7xx_l4_per2__cpgmac0,
27102 + &dra7xx_gmac__mdio,
27103 &dra7xx_l4_cfg__dma_system,
27104 &dra7xx_l3_main_1__dss,
27105 &dra7xx_l3_main_1__dispc,
27106 &dra7xx_l3_main_1__hdmi,
27107 + &dra7xx_l3_main_1__aes,
27108 &dra7xx_l4_per1__elm,
27109 &dra7xx_l4_wkup__gpio1,
27110 &dra7xx_l4_per1__gpio2,
27111 @@ -2673,6 +3121,19 @@ static struct omap_hwmod_ocp_if *dra7xx_
27112 &dra7xx_l4_per1__i2c3,
27113 &dra7xx_l4_per1__i2c4,
27114 &dra7xx_l4_per1__i2c5,
27115 + &dra7xx_l4_cfg__mailbox1,
27116 + &dra7xx_l4_per3__mailbox2,
27117 + &dra7xx_l4_per3__mailbox3,
27118 + &dra7xx_l4_per3__mailbox4,
27119 + &dra7xx_l4_per3__mailbox5,
27120 + &dra7xx_l4_per3__mailbox6,
27121 + &dra7xx_l4_per3__mailbox7,
27122 + &dra7xx_l4_per3__mailbox8,
27123 + &dra7xx_l4_per3__mailbox9,
27124 + &dra7xx_l4_per3__mailbox10,
27125 + &dra7xx_l4_per3__mailbox11,
27126 + &dra7xx_l4_per3__mailbox12,
27127 + &dra7xx_l4_per3__mailbox13,
27128 &dra7xx_l4_per1__mcspi1,
27129 &dra7xx_l4_per1__mcspi2,
27130 &dra7xx_l4_per1__mcspi3,
27131 @@ -2683,7 +3144,9 @@ static struct omap_hwmod_ocp_if *dra7xx_
27132 &dra7xx_l4_per1__mmc4,
27133 &dra7xx_l4_cfg__mpu,
27134 &dra7xx_l4_cfg__ocp2scp1,
27135 + &dra7xx_l4_cfg__ocp2scp3,
27136 &dra7xx_l3_main_1__qspi,
27137 + &dra7xx_l4_per3__rtcss,
27138 &dra7xx_l4_cfg__sata,
27139 &dra7xx_l4_cfg__smartreflex_core,
27140 &dra7xx_l4_cfg__smartreflex_mpu,
27141 @@ -2705,6 +3168,7 @@ static struct omap_hwmod_ocp_if *dra7xx_
27142 &dra7xx_l4_per1__uart4,
27143 &dra7xx_l4_per1__uart5,
27144 &dra7xx_l4_per1__uart6,
27145 + &dra7xx_l4_per1__des,
27146 &dra7xx_l4_per3__usb_otg_ss1,
27147 &dra7xx_l4_per3__usb_otg_ss2,
27148 &dra7xx_l4_per3__usb_otg_ss3,
27149 @@ -2714,6 +3178,7 @@ static struct omap_hwmod_ocp_if *dra7xx_
27150 &dra7xx_l3_main_1__vcp2,
27151 &dra7xx_l4_per2__vcp2,
27152 &dra7xx_l4_wkup__wd_timer2,
27153 + &dra7xx_l4_per3__vpe,
27154 NULL,
27155 };
27156
27157 --- a/arch/arm/mach-omap2/omap_hwmod.c
27158 +++ b/arch/arm/mach-omap2/omap_hwmod.c
27159 @@ -141,6 +141,7 @@
27160 #include <linux/cpu.h>
27161 #include <linux/of.h>
27162 #include <linux/of_address.h>
27163 +#include <linux/suspend.h>
27164
27165 #include <asm/system_misc.h>
27166
27167 @@ -208,6 +209,9 @@ static struct omap_hwmod *mpu_oh;
27168 /* io_chain_lock: used to serialize reconfigurations of the I/O chain */
27169 static DEFINE_SPINLOCK(io_chain_lock);
27170
27171 +/* _oh_force_mstandby_repeated_list for tracking nonstandard mstandby hwmods */
27172 +static LIST_HEAD(_oh_force_mstandby_repeated_list);
27173 +
27174 /*
27175 * linkspace: ptr to a buffer that struct omap_hwmod_link records are
27176 * allocated from - used to reduce the number of small memory
27177 @@ -656,6 +660,8 @@ static struct clockdomain *_get_clkdm(st
27178 if (oh->clkdm) {
27179 return oh->clkdm;
27180 } else if (oh->_clk) {
27181 + if (__clk_get_flags(oh->_clk) & CLK_IS_BASIC)
27182 + return NULL;
27183 clk = to_clk_hw_omap(__clk_get_hw(oh->_clk));
27184 return clk->clkdm;
27185 }
27186 @@ -728,14 +734,18 @@ static int _del_initiator_dep(struct oma
27187 * functional clock pointer) if a main_clk is present. Returns 0 on
27188 * success or -EINVAL on error.
27189 */
27190 -static int _init_main_clk(struct omap_hwmod *oh)
27191 +static int _init_main_clk(struct omap_hwmod *oh, struct device_node *np)
27192 {
27193 int ret = 0;
27194
27195 - if (!oh->main_clk)
27196 + if (!oh->main_clk && !of_get_property(np, "clocks", NULL))
27197 return 0;
27198
27199 - oh->_clk = clk_get(NULL, oh->main_clk);
27200 + if (oh->main_clk)
27201 + oh->_clk = clk_get(NULL, oh->main_clk);
27202 + else
27203 + oh->_clk = of_clk_get_by_name(np, "fck");
27204 +
27205 if (IS_ERR(oh->_clk)) {
27206 pr_warning("omap_hwmod: %s: cannot clk_get main_clk %s\n",
27207 oh->name, oh->main_clk);
27208 @@ -801,6 +811,63 @@ static int _init_interface_clks(struct o
27209 return ret;
27210 }
27211
27212 +static const char **_parse_opt_clks_dt(struct omap_hwmod *oh,
27213 + struct device_node *np,
27214 + int *opt_clks_cnt)
27215 +{
27216 + int i, clks_cnt;
27217 + const char *clk_name;
27218 + const char **opt_clk_names;
27219 +
27220 + clks_cnt = of_property_count_strings(np, "clock-names");
27221 + if (!clks_cnt)
27222 + return NULL;
27223 +
27224 + opt_clk_names = kzalloc(sizeof(char *)*clks_cnt, GFP_KERNEL);
27225 + if (!opt_clk_names)
27226 + return NULL;
27227 +
27228 + for (i = 0; i < clks_cnt; i++) {
27229 + of_property_read_string_index(np, "clock-names", i, &clk_name);
27230 + if (!strcmp(clk_name, "fck"))
27231 + continue;
27232 + opt_clk_names[(*opt_clks_cnt)++] = clk_name;
27233 + }
27234 + return opt_clk_names;
27235 +}
27236 +
27237 +static int _init_opt_clks_dt(struct omap_hwmod *oh, struct device_node *np)
27238 +{
27239 + struct clk *c;
27240 + int i, opt_clks_cnt = 0;
27241 + int ret = 0;
27242 + const char **opt_clk_names;
27243 +
27244 + opt_clk_names = _parse_opt_clks_dt(oh, np, &opt_clks_cnt);
27245 + if (!opt_clk_names)
27246 + return -EINVAL;
27247 +
27248 + oh->opt_clks = kzalloc(sizeof(struct omap_hwmod_opt_clk *)
27249 + * opt_clks_cnt, GFP_KERNEL);
27250 + if (!oh->opt_clks)
27251 + return -ENOMEM;
27252 +
27253 + oh->opt_clks_cnt = opt_clks_cnt;
27254 +
27255 + for (i = 0; i < opt_clks_cnt; i++) {
27256 + c = of_clk_get_by_name(np, opt_clk_names[i]);
27257 + if (IS_ERR(c)) {
27258 + pr_warn("omap_hwmod: %s: cannot clk_get opt_clk %s\n",
27259 + oh->name, opt_clk_names[i]);
27260 + ret = -EINVAL;
27261 + }
27262 + oh->opt_clks[i]._clk = c;
27263 + oh->opt_clks[i].role = opt_clk_names[i];
27264 + clk_prepare(oh->opt_clks[i]._clk);
27265 + }
27266 + return ret;
27267 +}
27268 +
27269 /**
27270 * _init_opt_clk - get a struct clk * for the the hwmod's optional clocks
27271 * @oh: struct omap_hwmod *
27272 @@ -808,13 +875,16 @@ static int _init_interface_clks(struct o
27273 * Called from _init_clocks(). Populates the @oh omap_hwmod_opt_clk
27274 * clock pointers. Returns 0 on success or -EINVAL on error.
27275 */
27276 -static int _init_opt_clks(struct omap_hwmod *oh)
27277 +static int _init_opt_clks(struct omap_hwmod *oh, struct device_node *np)
27278 {
27279 struct omap_hwmod_opt_clk *oc;
27280 struct clk *c;
27281 int i;
27282 int ret = 0;
27283
27284 + if (of_get_property(np, "clocks", NULL))
27285 + return _init_opt_clks_dt(oh, np);
27286 +
27287 for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) {
27288 c = clk_get(NULL, oc->clk);
27289 if (IS_ERR(c)) {
27290 @@ -1544,7 +1614,7 @@ static int _init_clkdm(struct omap_hwmod
27291 if (!oh->clkdm) {
27292 pr_warning("omap_hwmod: %s: could not associate to clkdm %s\n",
27293 oh->name, oh->clkdm_name);
27294 - return -EINVAL;
27295 + return 0;
27296 }
27297
27298 pr_debug("omap_hwmod: %s: associated to clkdm %s\n",
27299 @@ -1563,7 +1633,8 @@ static int _init_clkdm(struct omap_hwmod
27300 * Resolves all clock names embedded in the hwmod. Returns 0 on
27301 * success, or a negative error code on failure.
27302 */
27303 -static int _init_clocks(struct omap_hwmod *oh, void *data)
27304 +static int _init_clocks(struct omap_hwmod *oh, void *data,
27305 + struct device_node *np)
27306 {
27307 int ret = 0;
27308
27309 @@ -1575,9 +1646,9 @@ static int _init_clocks(struct omap_hwmo
27310 if (soc_ops.init_clkdm)
27311 ret |= soc_ops.init_clkdm(oh);
27312
27313 - ret |= _init_main_clk(oh);
27314 + ret |= _init_main_clk(oh, np);
27315 ret |= _init_interface_clks(oh);
27316 - ret |= _init_opt_clks(oh);
27317 + ret |= _init_opt_clks(oh, np);
27318
27319 if (!ret)
27320 oh->_state = _HWMOD_STATE_CLKS_INITED;
27321 @@ -2363,11 +2434,11 @@ static struct device_node *of_dev_hwmod_
27322 * are part of the device's address space can be ioremapped properly.
27323 * No return value.
27324 */
27325 -static void __init _init_mpu_rt_base(struct omap_hwmod *oh, void *data)
27326 +static void __init _init_mpu_rt_base(struct omap_hwmod *oh, void *data,
27327 + struct device_node *np)
27328 {
27329 struct omap_hwmod_addr_space *mem;
27330 void __iomem *va_start = NULL;
27331 - struct device_node *np;
27332
27333 if (!oh)
27334 return;
27335 @@ -2383,12 +2454,10 @@ static void __init _init_mpu_rt_base(str
27336 oh->name);
27337
27338 /* Extract the IO space from device tree blob */
27339 - if (!of_have_populated_dt())
27340 + if (!np)
27341 return;
27342
27343 - np = of_dev_hwmod_lookup(of_find_node_by_name(NULL, "ocp"), oh);
27344 - if (np)
27345 - va_start = of_iomap(np, oh->mpu_rt_idx);
27346 + va_start = of_iomap(np, oh->mpu_rt_idx);
27347 } else {
27348 va_start = ioremap(mem->pa_start, mem->pa_end - mem->pa_start);
27349 }
27350 @@ -2420,19 +2489,31 @@ static void __init _init_mpu_rt_base(str
27351 static int __init _init(struct omap_hwmod *oh, void *data)
27352 {
27353 int r;
27354 + struct device_node *np = NULL;
27355
27356 if (oh->_state != _HWMOD_STATE_REGISTERED)
27357 return 0;
27358
27359 + /* If booting with DT, parse the DT node for IO space/clocks etc */
27360 + if (of_have_populated_dt())
27361 + np = of_dev_hwmod_lookup(of_find_node_by_name(NULL, "ocp"), oh);
27362 +
27363 if (oh->class->sysc)
27364 - _init_mpu_rt_base(oh, NULL);
27365 + _init_mpu_rt_base(oh, NULL, np);
27366
27367 - r = _init_clocks(oh, NULL);
27368 + r = _init_clocks(oh, NULL, np);
27369 if (r < 0) {
27370 WARN(1, "omap_hwmod: %s: couldn't init clocks\n", oh->name);
27371 return -EINVAL;
27372 }
27373
27374 + if (np) {
27375 + if (of_find_property(np, "ti,no-reset", NULL))
27376 + oh->flags |= HWMOD_INIT_NO_RESET;
27377 + if (of_find_property(np, "ti,no-idle", NULL))
27378 + oh->flags |= HWMOD_INIT_NO_IDLE;
27379 + }
27380 +
27381 oh->_state = _HWMOD_STATE_INITIALIZED;
27382
27383 return 0;
27384 @@ -3826,6 +3907,75 @@ int omap_hwmod_disable_wakeup(struct oma
27385 return 0;
27386 }
27387
27388 +/*
27389 + * There are some IPs that do not have MSTANDBY asserted by default
27390 + * which is necessary for PER domain transition. If the drivers
27391 + * are not compiled into the kernel HWMOD code will not change the
27392 + * state of the IPs if the IP was never enabled, so we keep track of
27393 + * them here to idle them with a pm_notifier.
27394 + */
27395 +
27396 +static int _omap_mstandby_pm_notifier(struct notifier_block *self,
27397 + unsigned long action, void *dev)
27398 +{
27399 + struct omap_hwmod_list *oh_list_item = NULL;
27400 + switch (action) {
27401 + case PM_POST_SUSPEND:
27402 + list_for_each_entry(oh_list_item,
27403 + &_oh_force_mstandby_repeated_list, oh_list) {
27404 + omap_hwmod_enable(oh_list_item->oh);
27405 + omap_hwmod_idle(oh_list_item->oh);
27406 + }
27407 + }
27408 +
27409 + return NOTIFY_DONE;
27410 +}
27411 +
27412 +struct notifier_block pm_nb = {
27413 + .notifier_call = _omap_mstandby_pm_notifier,
27414 +};
27415 +
27416 +static int _check_for_force_mstandby_repeated(struct omap_hwmod *oh, void *data)
27417 +{
27418 + if (oh->flags & HWMOD_FORCE_MSTANDBY_REPEATED)
27419 + omap_hwmod_enable_force_mstandby_repeated(oh);
27420 +
27421 + return 0;
27422 +}
27423 +
27424 +int omap_hwmod_force_mstandby_repeated(void)
27425 +{
27426 + omap_hwmod_for_each(_check_for_force_mstandby_repeated, NULL);
27427 + register_pm_notifier(&pm_nb);
27428 + return 0;
27429 +}
27430 +
27431 +int omap_hwmod_enable_force_mstandby_repeated(struct omap_hwmod *oh)
27432 +{
27433 + struct omap_hwmod_list *oh_list_item = NULL;
27434 +
27435 + oh_list_item = kzalloc(sizeof(*oh_list_item), GFP_KERNEL);
27436 + oh_list_item->oh = oh;
27437 + list_add(&oh_list_item->oh_list, &_oh_force_mstandby_repeated_list);
27438 +
27439 + return 0;
27440 +}
27441 +
27442 +int omap_hwmod_disable_force_mstandby_repeated(struct omap_hwmod *oh)
27443 +{
27444 + struct omap_hwmod_list *oh_list_item, *tmp;
27445 +
27446 + list_for_each_entry_safe(oh_list_item, tmp,
27447 + &_oh_force_mstandby_repeated_list, oh_list) {
27448 + if (oh_list_item->oh == oh) {
27449 + list_del(&oh_list_item->oh_list);
27450 + kfree(oh_list_item);
27451 + }
27452 + }
27453 +
27454 + return 0;
27455 +}
27456 +
27457 /**
27458 * omap_hwmod_assert_hardreset - assert the HW reset line of submodules
27459 * contained in the hwmod module.
27460 @@ -4115,6 +4265,7 @@ void __init omap_hwmod_init(void)
27461 soc_ops.assert_hardreset = _omap2_assert_hardreset;
27462 soc_ops.deassert_hardreset = _omap2_deassert_hardreset;
27463 soc_ops.is_hardreset_asserted = _omap2_is_hardreset_asserted;
27464 + soc_ops.init_clkdm = _init_clkdm;
27465 } else if (cpu_is_omap44xx() || soc_is_omap54xx() || soc_is_dra7xx()) {
27466 soc_ops.enable_module = _omap4_enable_module;
27467 soc_ops.disable_module = _omap4_disable_module;
27468 @@ -4125,6 +4276,14 @@ void __init omap_hwmod_init(void)
27469 soc_ops.init_clkdm = _init_clkdm;
27470 soc_ops.update_context_lost = _omap4_update_context_lost;
27471 soc_ops.get_context_lost = _omap4_get_context_lost;
27472 + } else if (soc_is_am43xx()) {
27473 + soc_ops.enable_module = _omap4_enable_module;
27474 + soc_ops.disable_module = _omap4_disable_module;
27475 + soc_ops.wait_target_ready = _omap4_wait_target_ready;
27476 + soc_ops.assert_hardreset = _omap4_assert_hardreset;
27477 + soc_ops.deassert_hardreset = _omap4_deassert_hardreset;
27478 + soc_ops.is_hardreset_asserted = _omap4_is_hardreset_asserted;
27479 + soc_ops.init_clkdm = _init_clkdm;
27480 } else if (soc_is_am33xx()) {
27481 soc_ops.enable_module = _am33xx_enable_module;
27482 soc_ops.disable_module = _am33xx_disable_module;
27483 --- a/arch/arm/mach-omap2/omap_hwmod_common_data.c
27484 +++ b/arch/arm/mach-omap2/omap_hwmod_common_data.c
27485 @@ -59,6 +59,16 @@ struct omap_hwmod_sysc_fields omap_hwmod
27486 .sidle_shift = SYSC_TYPE3_SIDLEMODE_SHIFT,
27487 };
27488
27489 +/**
27490 + * struct omap_hwmod_sysc_type4 - TYPE4 sysconfig scheme.
27491 + * Used by some IPs on AM33xx
27492 + */
27493 +struct omap_hwmod_sysc_fields omap_hwmod_sysc_type4 = {
27494 + .sidle_shift = SYSC_TYPE4_SIDLEMODE_SHIFT,
27495 + .srst_shift = SYSC_TYPE4_SOFTRESET_SHIFT,
27496 + .autoidle_shift = SYSC_TYPE4_AUTOIDLE_SHIFT,
27497 +};
27498 +
27499 struct omap_dss_dispc_dev_attr omap2_3_dss_dispc_dev_attr = {
27500 .manager_count = 2,
27501 .has_framedonetv_irq = 0
27502 --- a/arch/arm/mach-omap2/omap_hwmod.h
27503 +++ b/arch/arm/mach-omap2/omap_hwmod.h
27504 @@ -41,6 +41,7 @@ struct omap_device;
27505 extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type1;
27506 extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2;
27507 extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type3;
27508 +extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type4;
27509
27510 /*
27511 * OCP SYSCONFIG bit shifts/masks TYPE1. These are for IPs compliant
27512 @@ -81,6 +82,16 @@ extern struct omap_hwmod_sysc_fields oma
27513 #define SYSC_TYPE3_MIDLEMODE_SHIFT 2
27514 #define SYSC_TYPE3_MIDLEMODE_MASK (0x3 << SYSC_TYPE3_MIDLEMODE_SHIFT)
27515
27516 +/*
27517 + * OCP SYSCONFIG bit shifts/masks TYPE4.
27518 + */
27519 +#define SYSC_TYPE4_SIDLEMODE_SHIFT 2
27520 +#define SYSC_TYPE4_SIDLEMODE_MASK (0x3 << SYSC_TYPE4_SIDLEMODE_SHIFT)
27521 +#define SYSC_TYPE4_SOFTRESET_SHIFT 1
27522 +#define SYSC_TYPE4_SOFTRESET_MASK (1 << SYSC_TYPE4_SOFTRESET_SHIFT)
27523 +#define SYSC_TYPE4_AUTOIDLE_SHIFT 0
27524 +#define SYSC_TYPE4_AUTOIDLE_MASK (1 << SYSC_TYPE4_AUTOIDLE_SHIFT)
27525 +
27526 /* OCP SYSSTATUS bit shifts/masks */
27527 #define SYSS_RESETDONE_SHIFT 0
27528 #define SYSS_RESETDONE_MASK (1 << SYSS_RESETDONE_SHIFT)
27529 @@ -528,6 +539,7 @@ struct omap_hwmod_omap4_prcm {
27530 #define HWMOD_BLOCK_WFI (1 << 10)
27531 #define HWMOD_FORCE_MSTANDBY (1 << 11)
27532 #define HWMOD_SWSUP_SIDLE_ACT (1 << 12)
27533 +#define HWMOD_FORCE_MSTANDBY_REPEATED (1 << 13)
27534
27535 /*
27536 * omap_hwmod._int_flags definitions
27537 @@ -678,6 +690,11 @@ struct omap_hwmod {
27538 u8 _postsetup_state;
27539 };
27540
27541 +struct omap_hwmod_list {
27542 + struct omap_hwmod *oh;
27543 + struct list_head oh_list;
27544 +};
27545 +
27546 struct omap_hwmod *omap_hwmod_lookup(const char *name);
27547 int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data),
27548 void *data);
27549 @@ -731,6 +748,10 @@ int omap_hwmod_no_setup_reset(struct oma
27550
27551 int omap_hwmod_pad_route_irq(struct omap_hwmod *oh, int pad_idx, int irq_idx);
27552
27553 +int omap_hwmod_force_mstandby_repeated(void);
27554 +int omap_hwmod_enable_force_mstandby_repeated(struct omap_hwmod *oh);
27555 +int omap_hwmod_disable_force_mstandby_repeated(struct omap_hwmod *oh);
27556 +
27557 extern void __init omap_hwmod_init(void);
27558
27559 const char *omap_hwmod_get_main_clk(struct omap_hwmod *oh);
27560 --- a/arch/arm/mach-omap2/omap-mpuss-lowpower.c
27561 +++ b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
27562 @@ -56,6 +56,7 @@
27563 #include "omap4-sar-layout.h"
27564 #include "pm.h"
27565 #include "prcm_mpu44xx.h"
27566 +#include "prcm_mpu54xx.h"
27567 #include "prminst44xx.h"
27568 #include "prcm44xx.h"
27569 #include "prm44xx.h"
27570 @@ -84,11 +85,13 @@ struct cpu_pm_ops {
27571 int (*finish_suspend)(unsigned long cpu_state);
27572 void (*resume)(void);
27573 void (*scu_prepare)(unsigned int cpu_id, unsigned int cpu_state);
27574 + void (*hotplug_restart)(void);
27575 };
27576
27577 static DEFINE_PER_CPU(struct omap4_cpu_pm_info, omap4_pm_info);
27578 static struct powerdomain *mpuss_pd;
27579 static void __iomem *sar_base;
27580 +static u32 cpu_context_offset;
27581
27582 static int default_finish_suspend(unsigned long cpu_state)
27583 {
27584 @@ -106,6 +109,7 @@ struct cpu_pm_ops omap_pm_ops = {
27585 .finish_suspend = default_finish_suspend,
27586 .resume = dummy_cpu_resume,
27587 .scu_prepare = dummy_scu_prepare,
27588 + .hotplug_restart = dummy_cpu_resume,
27589 };
27590
27591 /*
27592 @@ -116,7 +120,8 @@ static inline void set_cpu_wakeup_addr(u
27593 {
27594 struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
27595
27596 - __raw_writel(addr, pm_info->wkup_sar_addr);
27597 + if (pm_info->wkup_sar_addr)
27598 + __raw_writel(addr, pm_info->wkup_sar_addr);
27599 }
27600
27601 /*
27602 @@ -127,6 +132,9 @@ static void scu_pwrst_prepare(unsigned i
27603 struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
27604 u32 scu_pwr_st;
27605
27606 + if (!pm_info->scu_sar_addr)
27607 + return;
27608 +
27609 switch (cpu_state) {
27610 case PWRDM_POWER_RET:
27611 scu_pwr_st = SCU_PM_DORMANT;
27612 @@ -161,14 +169,14 @@ static inline void cpu_clear_prev_logic_
27613
27614 if (cpu_id) {
27615 reg = omap4_prcm_mpu_read_inst_reg(OMAP4430_PRCM_MPU_CPU1_INST,
27616 - OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET);
27617 + cpu_context_offset);
27618 omap4_prcm_mpu_write_inst_reg(reg, OMAP4430_PRCM_MPU_CPU1_INST,
27619 - OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET);
27620 + cpu_context_offset);
27621 } else {
27622 reg = omap4_prcm_mpu_read_inst_reg(OMAP4430_PRCM_MPU_CPU0_INST,
27623 - OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET);
27624 + cpu_context_offset);
27625 omap4_prcm_mpu_write_inst_reg(reg, OMAP4430_PRCM_MPU_CPU0_INST,
27626 - OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET);
27627 + cpu_context_offset);
27628 }
27629 }
27630
27631 @@ -179,7 +187,8 @@ static void l2x0_pwrst_prepare(unsigned
27632 {
27633 struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
27634
27635 - __raw_writel(save_state, pm_info->l2x0_sar_addr);
27636 + if (pm_info->l2x0_sar_addr)
27637 + __raw_writel(save_state, pm_info->l2x0_sar_addr);
27638 }
27639
27640 /*
27641 @@ -235,6 +244,8 @@ int omap4_enter_lowpower(unsigned int cp
27642 save_state = 1;
27643 break;
27644 case PWRDM_POWER_RET:
27645 + save_state = 0;
27646 + break;
27647 default:
27648 /*
27649 * CPUx CSWR is invalid hardware state. Also CPUx OSWR
27650 @@ -304,7 +315,7 @@ int omap4_hotplug_cpu(unsigned int cpu,
27651
27652 pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);
27653 pwrdm_set_next_pwrst(pm_info->pwrdm, power_state);
27654 - set_cpu_wakeup_addr(cpu, virt_to_phys(pm_info->secondary_startup));
27655 + set_cpu_wakeup_addr(cpu, virt_to_phys(omap_pm_ops.hotplug_restart));
27656 omap_pm_ops.scu_prepare(cpu, power_state);
27657
27658 /*
27659 @@ -320,11 +331,26 @@ int omap4_hotplug_cpu(unsigned int cpu,
27660
27661
27662 /*
27663 + * Enable Mercury Fast HG retention mode by default.
27664 + */
27665 +static void enable_mercury_retention_mode(void)
27666 +{
27667 + u32 reg;
27668 +
27669 + reg = omap4_prcm_mpu_read_inst_reg(OMAP54XX_PRCM_MPU_DEVICE_INST,
27670 + OMAP54XX_PRCM_MPU_PRM_PSCON_COUNT_OFFSET);
27671 + reg |= BIT(24) | BIT(25);
27672 + omap4_prcm_mpu_write_inst_reg(reg, OMAP54XX_PRCM_MPU_DEVICE_INST,
27673 + OMAP54XX_PRCM_MPU_PRM_PSCON_COUNT_OFFSET);
27674 +}
27675 +
27676 +/*
27677 * Initialise OMAP4 MPUSS
27678 */
27679 int __init omap4_mpuss_init(void)
27680 {
27681 struct omap4_cpu_pm_info *pm_info;
27682 + u32 cpu_wakeup_addr = 0;
27683
27684 if (omap_rev() == OMAP4430_REV_ES1_0) {
27685 WARN(1, "Power Management not supported on OMAP4430 ES1.0\n");
27686 @@ -334,10 +360,16 @@ int __init omap4_mpuss_init(void)
27687 sar_base = omap4_get_sar_ram_base();
27688
27689 /* Initilaise per CPU PM information */
27690 + if (cpu_is_omap44xx())
27691 + cpu_wakeup_addr = CPU0_WAKEUP_NS_PA_ADDR_OFFSET;
27692 + else if (soc_is_omap54xx())
27693 + cpu_wakeup_addr = OMAP5_CPU0_WAKEUP_NS_PA_ADDR_OFFSET;
27694 pm_info = &per_cpu(omap4_pm_info, 0x0);
27695 - pm_info->scu_sar_addr = sar_base + SCU_OFFSET0;
27696 - pm_info->wkup_sar_addr = sar_base + CPU0_WAKEUP_NS_PA_ADDR_OFFSET;
27697 - pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET0;
27698 + if (sar_base) {
27699 + pm_info->scu_sar_addr = sar_base + SCU_OFFSET0;
27700 + pm_info->wkup_sar_addr = sar_base + cpu_wakeup_addr;
27701 + pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET0;
27702 + }
27703 pm_info->pwrdm = pwrdm_lookup("cpu0_pwrdm");
27704 if (!pm_info->pwrdm) {
27705 pr_err("Lookup failed for CPU0 pwrdm\n");
27706 @@ -351,14 +383,17 @@ int __init omap4_mpuss_init(void)
27707 /* Initialise CPU0 power domain state to ON */
27708 pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);
27709
27710 + if (cpu_is_omap44xx())
27711 + cpu_wakeup_addr = CPU1_WAKEUP_NS_PA_ADDR_OFFSET;
27712 + else if (soc_is_omap54xx())
27713 + cpu_wakeup_addr = OMAP5_CPU1_WAKEUP_NS_PA_ADDR_OFFSET;
27714 +
27715 pm_info = &per_cpu(omap4_pm_info, 0x1);
27716 - pm_info->scu_sar_addr = sar_base + SCU_OFFSET1;
27717 - pm_info->wkup_sar_addr = sar_base + CPU1_WAKEUP_NS_PA_ADDR_OFFSET;
27718 - pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET1;
27719 - if (cpu_is_omap446x())
27720 - pm_info->secondary_startup = omap4460_secondary_startup;
27721 - else
27722 - pm_info->secondary_startup = omap4_secondary_startup;
27723 + if (sar_base) {
27724 + pm_info->scu_sar_addr = sar_base + SCU_OFFSET1;
27725 + pm_info->wkup_sar_addr = sar_base + cpu_wakeup_addr;
27726 + pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET1;
27727 + }
27728
27729 pm_info->pwrdm = pwrdm_lookup("cpu1_pwrdm");
27730 if (!pm_info->pwrdm) {
27731 @@ -382,19 +417,32 @@ int __init omap4_mpuss_init(void)
27732 mpuss_clear_prev_logic_pwrst();
27733
27734 /* Save device type on scratchpad for low level code to use */
27735 - if (omap_type() != OMAP2_DEVICE_TYPE_GP)
27736 - __raw_writel(1, sar_base + OMAP_TYPE_OFFSET);
27737 - else
27738 - __raw_writel(0, sar_base + OMAP_TYPE_OFFSET);
27739 + if (sar_base) {
27740 + if (omap_type() != OMAP2_DEVICE_TYPE_GP)
27741 + __raw_writel(1, sar_base + OMAP_TYPE_OFFSET);
27742 + else
27743 + __raw_writel(0, sar_base + OMAP_TYPE_OFFSET);
27744
27745 - save_l2x0_context();
27746 + save_l2x0_context();
27747 + }
27748
27749 if (cpu_is_omap44xx()) {
27750 omap_pm_ops.finish_suspend = omap4_finish_suspend;
27751 + omap_pm_ops.hotplug_restart = omap4_secondary_startup;
27752 omap_pm_ops.resume = omap4_cpu_resume;
27753 omap_pm_ops.scu_prepare = scu_pwrst_prepare;
27754 + cpu_context_offset = OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET;
27755 + } else if (soc_is_omap54xx() || soc_is_dra7xx()) {
27756 + omap_pm_ops.finish_suspend = omap5_finish_suspend;
27757 + omap_pm_ops.hotplug_restart = omap5_secondary_startup;
27758 + omap_pm_ops.resume = omap5_cpu_resume;
27759 + cpu_context_offset = OMAP54XX_RM_CPU0_CPU0_CONTEXT_OFFSET;
27760 + enable_mercury_retention_mode();
27761 }
27762
27763 + if (cpu_is_omap446x())
27764 + omap_pm_ops.hotplug_restart = omap4460_secondary_startup;
27765 +
27766 return 0;
27767 }
27768
27769 --- a/arch/arm/mach-omap2/omap-secure.h
27770 +++ b/arch/arm/mach-omap2/omap-secure.h
27771 @@ -34,6 +34,10 @@
27772 #define OMAP4_HAL_SAVEHW_INDEX 0x1b
27773 #define OMAP4_HAL_SAVEALL_INDEX 0x1c
27774 #define OMAP4_HAL_SAVEGIC_INDEX 0x1d
27775 +#define OMAP5_HAL_SAVESECURERAM_INDEX 0x1c
27776 +#define OMAP5_HAL_SAVEHW_INDEX 0x1d
27777 +#define OMAP5_HAL_SAVEALL_INDEX 0x1e
27778 +#define OMAP5_HAL_SAVEGIC_INDEX 0x1f
27779
27780 /* Secure Monitor mode APIs */
27781 #define OMAP4_MON_SCU_PWR_INDEX 0x108
27782 @@ -41,6 +45,13 @@
27783 #define OMAP4_MON_L2X0_CTRL_INDEX 0x102
27784 #define OMAP4_MON_L2X0_AUXCTRL_INDEX 0x109
27785 #define OMAP4_MON_L2X0_PREFETCH_INDEX 0x113
27786 +#define OMAP5_MON_CACHES_CLEAN_INDEX 0x103
27787 +#define OMAP5_MON_AUX_CTRL_INDEX 0x107
27788 +#define OMAP5_MON_L2AUX_CTRL_INDEX 0x104
27789 +
27790 +#define OMAP5_MON_AMBA_IF_INDEX 0x108
27791 +
27792 +#define OMAP5_DRA7_MON_SET_CNTFRQ_INDEX 0x109
27793
27794 /* Secure PPA(Primary Protected Application) APIs */
27795 #define OMAP4_PPA_L2_POR_INDEX 0x23
27796 --- a/arch/arm/mach-omap2/omap-smp.c
27797 +++ b/arch/arm/mach-omap2/omap-smp.c
27798 @@ -41,6 +41,8 @@
27799
27800 u16 pm44xx_errata;
27801
27802 +extern unsigned long arch_timer_freq;
27803 +
27804 /* SCU base address */
27805 static void __iomem *scu_base;
27806
27807 @@ -66,6 +68,13 @@ static void omap4_secondary_init(unsigne
27808 4, 0, 0, 0, 0, 0);
27809
27810 /*
27811 + * Configure the CNTFRQ register for the secondary cpu's which
27812 + * indicates the frequency of the cpu local timers.
27813 + */
27814 + if (soc_is_omap54xx() || soc_is_dra7xx())
27815 + omap_smc1(OMAP5_DRA7_MON_SET_CNTFRQ_INDEX, arch_timer_freq);
27816 +
27817 + /*
27818 * Synchronise with the boot thread.
27819 */
27820 spin_lock(&boot_lock);
27821 --- a/arch/arm/mach-omap2/omap-wakeupgen.c
27822 +++ b/arch/arm/mach-omap2/omap-wakeupgen.c
27823 @@ -33,8 +33,11 @@
27824 #include "omap4-sar-layout.h"
27825 #include "common.h"
27826
27827 -#define MAX_NR_REG_BANKS 5
27828 -#define MAX_IRQS 160
27829 +/* maximum value correspond to that of AM43x */
27830 +#define MAX_NR_REG_BANKS 7
27831 +#define MAX_IRQS 224
27832 +#define DEFAULT_NR_REG_BANKS 5
27833 +#define DEFAULT_IRQS 160
27834 #define WKG_MASK_ALL 0x00000000
27835 #define WKG_UNMASK_ALL 0xffffffff
27836 #define CPU_ENA_OFFSET 0x400
27837 @@ -47,9 +50,9 @@ static void __iomem *wakeupgen_base;
27838 static void __iomem *sar_base;
27839 static DEFINE_RAW_SPINLOCK(wakeupgen_lock);
27840 static unsigned int irq_target_cpu[MAX_IRQS];
27841 -static unsigned int irq_banks = MAX_NR_REG_BANKS;
27842 -static unsigned int max_irqs = MAX_IRQS;
27843 -static unsigned int omap_secure_apis;
27844 +static unsigned int irq_banks = DEFAULT_NR_REG_BANKS;
27845 +static unsigned int max_irqs = DEFAULT_IRQS;
27846 +static unsigned int omap_secure_apis, secure_api_index;
27847
27848 /*
27849 * Static helper functions.
27850 @@ -314,7 +317,7 @@ static void irq_sar_clear(void)
27851 static void irq_save_secure_context(void)
27852 {
27853 u32 ret;
27854 - ret = omap_secure_dispatcher(OMAP4_HAL_SAVEGIC_INDEX,
27855 + ret = omap_secure_dispatcher(secure_api_index,
27856 FLAG_START_CRITICAL,
27857 0, 0, 0, 0, 0);
27858 if (ret != API_HAL_RET_VALUE_OK)
27859 @@ -376,8 +379,8 @@ static struct notifier_block irq_notifie
27860
27861 static void __init irq_pm_init(void)
27862 {
27863 - /* FIXME: Remove this when MPU OSWR support is added */
27864 - if (!soc_is_omap54xx())
27865 + /* No OFF mode support on dra7xx */
27866 + if (!soc_is_dra7xx())
27867 cpu_pm_register_notifier(&irq_notifier_block);
27868 }
27869 #else
27870 @@ -402,6 +405,8 @@ int __init omap_wakeupgen_init(void)
27871 {
27872 int i;
27873 unsigned int boot_cpu = smp_processor_id();
27874 + u32 val;
27875 + bool am43x = soc_is_am43xx() ? true : false;
27876
27877 /* Not supported on OMAP4 ES1.0 silicon */
27878 if (omap_rev() == OMAP4430_REV_ES1_0) {
27879 @@ -418,12 +423,19 @@ int __init omap_wakeupgen_init(void)
27880 irq_banks = OMAP4_NR_BANKS;
27881 max_irqs = OMAP4_NR_IRQS;
27882 omap_secure_apis = 1;
27883 + secure_api_index = OMAP4_HAL_SAVEGIC_INDEX;
27884 + } else if (soc_is_omap54xx()) {
27885 + secure_api_index = OMAP5_HAL_SAVEGIC_INDEX;
27886 + } else if (am43x) {
27887 + irq_banks = MAX_NR_REG_BANKS;
27888 + max_irqs = MAX_IRQS;
27889 }
27890
27891 /* Clear all IRQ bitmasks at wakeupGen level */
27892 for (i = 0; i < irq_banks; i++) {
27893 wakeupgen_writel(0, i, CPU0_ID);
27894 - wakeupgen_writel(0, i, CPU1_ID);
27895 + if (!am43x)
27896 + wakeupgen_writel(0, i, CPU1_ID);
27897 }
27898
27899 /*
27900 @@ -443,6 +455,19 @@ int __init omap_wakeupgen_init(void)
27901 for (i = 0; i < max_irqs; i++)
27902 irq_target_cpu[i] = boot_cpu;
27903
27904 + /*
27905 + * Enables OMAP5 ES2 PM Mode using ES2_PM_MODE in AMBA_IF_MODE
27906 + * 0x0: ES1 behavior, CPU cores would enter and exit OFF mode together.
27907 + * 0x1: ES2 behavior, CPU cores are allowed to enter/exit OFF mode
27908 + * independently.
27909 + * This needs to be set one time thanks to always ON domain.
27910 + */
27911 + if (soc_is_omap54xx()) {
27912 + val = __raw_readl(wakeupgen_base + OMAP_AMBA_IF_MODE);
27913 + val |= BIT(5);
27914 + omap_smc1(OMAP5_MON_AMBA_IF_INDEX, val);
27915 + }
27916 +
27917 irq_hotplug_init();
27918 irq_pm_init();
27919
27920 --- a/arch/arm/mach-omap2/omap-wakeupgen.h
27921 +++ b/arch/arm/mach-omap2/omap-wakeupgen.h
27922 @@ -27,6 +27,7 @@
27923 #define OMAP_WKG_ENB_E_1 0x420
27924 #define OMAP_AUX_CORE_BOOT_0 0x800
27925 #define OMAP_AUX_CORE_BOOT_1 0x804
27926 +#define OMAP_AMBA_IF_MODE 0x80c
27927 #define OMAP_PTMSYNCREQ_MASK 0xc00
27928 #define OMAP_PTMSYNCREQ_EN 0xc04
27929 #define OMAP_TIMESTAMPCYCLELO 0xc08
27930 --- a/arch/arm/mach-omap2/opp.c
27931 +++ b/arch/arm/mach-omap2/opp.c
27932 @@ -17,6 +17,7 @@
27933 * GNU General Public License for more details.
27934 */
27935 #include <linux/module.h>
27936 +#include <linux/of.h>
27937 #include <linux/opp.h>
27938 #include <linux/cpu.h>
27939
27940 @@ -40,6 +41,9 @@ int __init omap_init_opp_table(struct om
27941 {
27942 int i, r;
27943
27944 + if (of_have_populated_dt())
27945 + return -EINVAL;
27946 +
27947 if (!opp_def || !opp_def_size) {
27948 pr_err("%s: invalid params!\n", __func__);
27949 return -EINVAL;
27950 --- /dev/null
27951 +++ b/arch/arm/mach-omap2/pm33xx.c
27952 @@ -0,0 +1,387 @@
27953 +/*
27954 + * AM33XX Power Management Routines
27955 + *
27956 + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
27957 + * Vaibhav Bedia <vaibhav.bedia@ti.com>
27958 + *
27959 + * This program is free software; you can redistribute it and/or
27960 + * modify it under the terms of the GNU General Public License as
27961 + * published by the Free Software Foundation version 2.
27962 + *
27963 + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
27964 + * kind, whether express or implied; without even the implied warranty
27965 + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27966 + * GNU General Public License for more details.
27967 + */
27968 +
27969 +#include <linux/kernel.h>
27970 +#include <linux/init.h>
27971 +#include <linux/cpu.h>
27972 +#include <linux/err.h>
27973 +#include <linux/firmware.h>
27974 +#include <linux/io.h>
27975 +#include <linux/platform_device.h>
27976 +#include <linux/sched.h>
27977 +#include <linux/suspend.h>
27978 +#include <linux/completion.h>
27979 +#include <linux/module.h>
27980 +#include <linux/interrupt.h>
27981 +#include <linux/ti_emif.h>
27982 +#include <linux/omap-mailbox.h>
27983 +
27984 +#include <asm/suspend.h>
27985 +#include <asm/proc-fns.h>
27986 +#include <asm/sizes.h>
27987 +#include <asm/fncpy.h>
27988 +#include <asm/system_misc.h>
27989 +
27990 +#include "pm.h"
27991 +#include "cm33xx.h"
27992 +#include "pm33xx.h"
27993 +#include "common.h"
27994 +#include "clockdomain.h"
27995 +#include "powerdomain.h"
27996 +#include "soc.h"
27997 +#include "sram.h"
27998 +
27999 +static void __iomem *am33xx_emif_base;
28000 +static struct powerdomain *cefuse_pwrdm, *gfx_pwrdm, *per_pwrdm, *mpu_pwrdm;
28001 +static struct clockdomain *gfx_l4ls_clkdm;
28002 +static struct clockdomain *l3s_clkdm, *l4fw_clkdm, *clk_24mhz_clkdm;
28003 +
28004 +static struct am33xx_pm_context *am33xx_pm;
28005 +
28006 +static DECLARE_COMPLETION(am33xx_pm_sync);
28007 +
28008 +static void (*am33xx_do_wfi_sram)(struct am33xx_suspend_params *);
28009 +
28010 +static struct am33xx_suspend_params susp_params;
28011 +
28012 +#ifdef CONFIG_SUSPEND
28013 +
28014 +static int am33xx_do_sram_idle(long unsigned int unused)
28015 +{
28016 + am33xx_do_wfi_sram(&susp_params);
28017 + return 0;
28018 +}
28019 +
28020 +static int am33xx_pm_suspend(unsigned int state)
28021 +{
28022 + int i, ret = 0;
28023 + int status = 0;
28024 + struct wkup_m3_wakeup_src wakeup_src;
28025 +
28026 + if (state == PM_SUSPEND_STANDBY) {
28027 + clkdm_wakeup(l3s_clkdm);
28028 + clkdm_wakeup(l4fw_clkdm);
28029 + clkdm_wakeup(clk_24mhz_clkdm);
28030 + }
28031 +
28032 + /* Try to put GFX to sleep */
28033 + omap_set_pwrdm_state(gfx_pwrdm, PWRDM_POWER_OFF);
28034 +
28035 + ret = cpu_suspend(0, am33xx_do_sram_idle);
28036 +
28037 + status = pwrdm_read_pwrst(gfx_pwrdm);
28038 + if (status != PWRDM_POWER_OFF)
28039 + pr_err("PM: GFX domain did not transition\n");
28040 +
28041 + /*
28042 + * BUG: GFX_L4LS clock domain needs to be woken up to
28043 + * ensure thet L4LS clock domain does not get stuck in transition
28044 + * If that happens L3 module does not get disabled, thereby leading
28045 + * to PER power domain transition failing
28046 + */
28047 + clkdm_wakeup(gfx_l4ls_clkdm);
28048 + clkdm_sleep(gfx_l4ls_clkdm);
28049 +
28050 + if (ret) {
28051 + pr_err("PM: Kernel suspend failure\n");
28052 + } else {
28053 + i = wkup_m3_pm_status();
28054 + switch (i) {
28055 + case 0:
28056 + pr_info("PM: Successfully put all powerdomains to target state\n");
28057 +
28058 + /*
28059 + * The PRCM registers on AM335x do not contain
28060 + * previous state information like those present on
28061 + * OMAP4 so we must manually indicate transition so
28062 + * state counters are properly incremented
28063 + */
28064 + pwrdm_post_transition(mpu_pwrdm);
28065 + pwrdm_post_transition(per_pwrdm);
28066 + break;
28067 + case 1:
28068 + pr_err("PM: Could not transition all powerdomains to target state\n");
28069 + ret = -1;
28070 + break;
28071 + default:
28072 + pr_err("PM: CM3 returned unknown result = %d\n", i);
28073 + ret = -1;
28074 + }
28075 + /* print the wakeup reason */
28076 + wakeup_src = wkup_m3_wake_src();
28077 +
28078 + pr_info("PM: Wakeup source %s\n", wakeup_src.src);
28079 + }
28080 +
28081 + return ret;
28082 +}
28083 +
28084 +static int am33xx_pm_enter(suspend_state_t suspend_state)
28085 +{
28086 + int ret = 0;
28087 +
28088 + switch (suspend_state) {
28089 + case PM_SUSPEND_STANDBY:
28090 + case PM_SUSPEND_MEM:
28091 + ret = am33xx_pm_suspend(suspend_state);
28092 + break;
28093 + default:
28094 + ret = -EINVAL;
28095 + }
28096 +
28097 + return ret;
28098 +}
28099 +
28100 +
28101 +static void am33xx_m3_state_machine_reset(void)
28102 +{
28103 + int i;
28104 +
28105 + am33xx_pm->ipc.reg1 = IPC_CMD_RESET;
28106 +
28107 + wkup_m3_pm_set_cmd(&am33xx_pm->ipc);
28108 +
28109 + am33xx_pm->state = M3_STATE_MSG_FOR_RESET;
28110 +
28111 + if (!wkup_m3_ping()) {
28112 + i = wait_for_completion_timeout(&am33xx_pm_sync,
28113 + msecs_to_jiffies(500));
28114 + if (!i) {
28115 + WARN(1, "PM: MPU<->CM3 sync failure\n");
28116 + am33xx_pm->state = M3_STATE_UNKNOWN;
28117 + }
28118 + } else {
28119 + pr_warn("PM: Unable to ping CM3\n");
28120 + }
28121 +}
28122 +
28123 +static int am33xx_pm_begin(suspend_state_t state)
28124 +{
28125 + int i;
28126 +
28127 + cpu_idle_poll_ctrl(true);
28128 +
28129 + switch (state) {
28130 + case PM_SUSPEND_MEM:
28131 + am33xx_pm->ipc.reg1 = IPC_CMD_DS0;
28132 + break;
28133 + case PM_SUSPEND_STANDBY:
28134 + am33xx_pm->ipc.reg1 = IPC_CMD_STANDBY;
28135 + break;
28136 + }
28137 +
28138 + am33xx_pm->ipc.reg2 = DS_IPC_DEFAULT;
28139 + am33xx_pm->ipc.reg3 = DS_IPC_DEFAULT;
28140 +
28141 + wkup_m3_pm_set_cmd(&am33xx_pm->ipc);
28142 +
28143 + am33xx_pm->state = M3_STATE_MSG_FOR_LP;
28144 +
28145 + if (!wkup_m3_ping()) {
28146 + i = wait_for_completion_timeout(&am33xx_pm_sync,
28147 + msecs_to_jiffies(500));
28148 + if (!i) {
28149 + WARN(1, "PM: MPU<->CM3 sync failure\n");
28150 + return -1;
28151 + }
28152 + } else {
28153 + pr_warn("PM: Unable to ping CM3\n");
28154 + return -1;
28155 + }
28156 +
28157 + return 0;
28158 +}
28159 +
28160 +static void am33xx_pm_end(void)
28161 +{
28162 + am33xx_m3_state_machine_reset();
28163 +
28164 + cpu_idle_poll_ctrl(false);
28165 +
28166 + return;
28167 +}
28168 +
28169 +static int am33xx_pm_valid(suspend_state_t state)
28170 +{
28171 + switch (state) {
28172 + case PM_SUSPEND_STANDBY:
28173 + case PM_SUSPEND_MEM:
28174 + return 1;
28175 + default:
28176 + return 0;
28177 + }
28178 +}
28179 +
28180 +static const struct platform_suspend_ops am33xx_pm_ops = {
28181 + .begin = am33xx_pm_begin,
28182 + .end = am33xx_pm_end,
28183 + .enter = am33xx_pm_enter,
28184 + .valid = am33xx_pm_valid,
28185 +};
28186 +#endif /* CONFIG_SUSPEND */
28187 +
28188 +static void am33xx_txev_handler(void)
28189 +{
28190 + switch (am33xx_pm->state) {
28191 + case M3_STATE_RESET:
28192 + am33xx_pm->state = M3_STATE_INITED;
28193 + complete(&am33xx_pm_sync);
28194 + break;
28195 + case M3_STATE_MSG_FOR_RESET:
28196 + am33xx_pm->state = M3_STATE_INITED;
28197 + complete(&am33xx_pm_sync);
28198 + break;
28199 + case M3_STATE_MSG_FOR_LP:
28200 + complete(&am33xx_pm_sync);
28201 + break;
28202 + case M3_STATE_UNKNOWN:
28203 + pr_warn("PM: Unknown CM3 State\n");
28204 + }
28205 +
28206 + return;
28207 +}
28208 +
28209 +static void am33xx_m3_fw_ready_cb(void)
28210 +{
28211 + int ret = 0;
28212 +
28213 + ret = wkup_m3_prepare();
28214 + if (ret) {
28215 + pr_err("PM: Could not prepare WKUP_M3\n");
28216 + return;
28217 + }
28218 +
28219 + ret = wait_for_completion_timeout(&am33xx_pm_sync,
28220 + msecs_to_jiffies(500));
28221 +
28222 + if (WARN(ret == 0, "PM: MPU<->CM3 sync failure\n"))
28223 + return;
28224 +
28225 + am33xx_pm->ver = wkup_m3_fw_version_read();
28226 +
28227 + if (am33xx_pm->ver == M3_VERSION_UNKNOWN ||
28228 + am33xx_pm->ver < M3_BASELINE_VERSION) {
28229 + pr_warn("PM: CM3 Firmware Version %x not supported\n",
28230 + am33xx_pm->ver);
28231 + return;
28232 + } else {
28233 + pr_info("PM: CM3 Firmware Version = 0x%x\n",
28234 + am33xx_pm->ver);
28235 + }
28236 +
28237 +#ifdef CONFIG_SUSPEND
28238 + suspend_set_ops(&am33xx_pm_ops);
28239 +#endif /* CONFIG_SUSPEND */
28240 +}
28241 +
28242 +static struct wkup_m3_ops am33xx_wkup_m3_ops = {
28243 + .txev_handler = am33xx_txev_handler,
28244 + .firmware_loaded = am33xx_m3_fw_ready_cb,
28245 +};
28246 +
28247 +/*
28248 + * Push the minimal suspend-resume code to SRAM
28249 + */
28250 +void am33xx_push_sram_idle(void)
28251 +{
28252 + am33xx_do_wfi_sram = (void *)omap_sram_push
28253 + (am33xx_do_wfi, am33xx_do_wfi_sz);
28254 +}
28255 +
28256 +static int __init am33xx_map_emif(void)
28257 +{
28258 + am33xx_emif_base = ioremap(AM33XX_EMIF_BASE, SZ_32K);
28259 +
28260 + if (!am33xx_emif_base)
28261 + return -ENOMEM;
28262 +
28263 + return 0;
28264 +}
28265 +
28266 +int __init am33xx_pm_init(void)
28267 +{
28268 + int ret;
28269 + u32 temp;
28270 +
28271 + if (!soc_is_am33xx())
28272 + return -ENODEV;
28273 +
28274 + gfx_pwrdm = pwrdm_lookup("gfx_pwrdm");
28275 + per_pwrdm = pwrdm_lookup("per_pwrdm");
28276 + mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
28277 +
28278 + gfx_l4ls_clkdm = clkdm_lookup("gfx_l4ls_gfx_clkdm");
28279 + l3s_clkdm = clkdm_lookup("l3s_clkdm");
28280 + l4fw_clkdm = clkdm_lookup("l4fw_clkdm");
28281 + clk_24mhz_clkdm = clkdm_lookup("clk_24mhz_clkdm");
28282 +
28283 + if ((!gfx_pwrdm) || (!per_pwrdm) || (!mpu_pwrdm) || (!gfx_l4ls_clkdm) ||
28284 + (!l3s_clkdm) || (!l4fw_clkdm) || (!clk_24mhz_clkdm)) {
28285 + ret = -ENODEV;
28286 + goto err;
28287 + }
28288 +
28289 + am33xx_pm = kzalloc(sizeof(*am33xx_pm), GFP_KERNEL);
28290 + if (!am33xx_pm) {
28291 + pr_err("Memory allocation failed\n");
28292 + ret = -ENOMEM;
28293 + return ret;
28294 + }
28295 +
28296 + ret = am33xx_map_emif();
28297 + if (ret) {
28298 + pr_err("PM: Could not ioremap EMIF\n");
28299 + goto err;
28300 + }
28301 +
28302 + /* Determine Memory Type */
28303 + temp = readl(am33xx_emif_base + EMIF_SDRAM_CONFIG);
28304 + temp = (temp & SDRAM_TYPE_MASK) >> SDRAM_TYPE_SHIFT;
28305 + /* Parameters to pass to aseembly code */
28306 + susp_params.emif_addr_virt = am33xx_emif_base;
28307 + susp_params.dram_sync = am33xx_dram_sync;
28308 + susp_params.mem_type = temp;
28309 + am33xx_pm->ipc.reg4 = temp;
28310 +
28311 + (void) clkdm_for_each(omap_pm_clkdms_setup, NULL);
28312 +
28313 + /* CEFUSE domain can be turned off post bootup */
28314 + cefuse_pwrdm = pwrdm_lookup("cefuse_pwrdm");
28315 + if (cefuse_pwrdm)
28316 + omap_set_pwrdm_state(cefuse_pwrdm, PWRDM_POWER_OFF);
28317 + else
28318 + pr_err("PM: Failed to get cefuse_pwrdm\n");
28319 +
28320 + am33xx_pm->state = M3_STATE_RESET;
28321 +
28322 + wkup_m3_set_ops(&am33xx_wkup_m3_ops);
28323 +
28324 + /* m3 may have already loaded but ops were not set yet,
28325 + * manually invoke */
28326 +
28327 + if (wkup_m3_is_valid())
28328 + am33xx_m3_fw_ready_cb();
28329 +
28330 + /* Physical resume address to be used by ROM code */
28331 + am33xx_pm->ipc.reg0 = (AM33XX_OCMC_END -
28332 + am33xx_do_wfi_sz + am33xx_resume_offset + 0x4);
28333 +
28334 + return 0;
28335 +
28336 +err:
28337 + kfree(am33xx_pm);
28338 + return ret;
28339 +}
28340 --- /dev/null
28341 +++ b/arch/arm/mach-omap2/pm33xx.h
28342 @@ -0,0 +1,77 @@
28343 +/*
28344 + * AM33XX Power Management Routines
28345 + *
28346 + * Copyright (C) 2012 Texas Instruments Inc.
28347 + * Vaibhav Bedia <vaibhav.bedia@ti.com>
28348 + *
28349 + * This program is free software; you can redistribute it and/or
28350 + * modify it under the terms of the GNU General Public License as
28351 + * published by the Free Software Foundation version 2.
28352 + *
28353 + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
28354 + * kind, whether express or implied; without even the implied warranty
28355 + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28356 + * GNU General Public License for more details.
28357 + */
28358 +#ifndef __ARCH_ARM_MACH_OMAP2_PM33XX_H
28359 +#define __ARCH_ARM_MACH_OMAP2_PM33XX_H
28360 +
28361 +#include "wkup_m3.h"
28362 +
28363 +#ifndef __ASSEMBLER__
28364 +
28365 +struct am33xx_pm_context {
28366 + struct am33xx_ipc_regs ipc;
28367 + struct firmware *firmware;
28368 + struct omap_mbox *mbox;
28369 + u8 state;
28370 + u32 ver;
28371 +};
28372 +
28373 +/*
28374 + * Params passed to suspend routine
28375 + *
28376 + * These are used to load into registers by suspend code,
28377 + * entries here must always be in sync with the suspend code
28378 + * in arm/mach-omap2/sleep33xx.S
28379 + */
28380 +struct am33xx_suspend_params {
28381 + void __iomem *emif_addr_virt;
28382 + u32 mem_type;
28383 + void __iomem *dram_sync;
28384 +};
28385 +
28386 +
28387 +#endif
28388 +
28389 +#define IPC_CMD_DS0 0x4
28390 +#define IPC_CMD_STANDBY 0xc
28391 +#define IPC_CMD_RESET 0xe
28392 +#define DS_IPC_DEFAULT 0xffffffff
28393 +#define M3_VERSION_UNKNOWN 0x0000ffff
28394 +#define M3_BASELINE_VERSION 0x21
28395 +
28396 +#define M3_STATE_UNKNOWN 0
28397 +#define M3_STATE_RESET 1
28398 +#define M3_STATE_INITED 2
28399 +#define M3_STATE_MSG_FOR_LP 3
28400 +#define M3_STATE_MSG_FOR_RESET 4
28401 +
28402 +#define AM33XX_OCMC_END 0x40310000
28403 +#define AM33XX_EMIF_BASE 0x4C000000
28404 +
28405 +#define MEM_TYPE_DDR2 2
28406 +
28407 +/*
28408 + * 9-4 = VTT GPIO PIN (6 Bits)
28409 + * 3 = VTT Status (1 Bit)
28410 + * 2-0 = Memory Type (2 Bits)
28411 +*/
28412 +#define MEM_TYPE_SHIFT (0x0)
28413 +#define MEM_TYPE_MASK (0x7 << 0)
28414 +#define VTT_STAT_SHIFT (0x3)
28415 +#define VTT_STAT_MASK (0x1 << 3)
28416 +#define VTT_GPIO_PIN_SHIFT (0x4)
28417 +#define VTT_GPIO_PIN_MASK (0x2f << 4)
28418 +
28419 +#endif
28420 --- a/arch/arm/mach-omap2/pm44xx.c
28421 +++ b/arch/arm/mach-omap2/pm44xx.c
28422 @@ -35,6 +35,7 @@ struct power_state {
28423 };
28424
28425 static LIST_HEAD(pwrst_list);
28426 +u32 cpu_suspend_state;
28427
28428 #ifdef CONFIG_SUSPEND
28429 static int omap4_pm_suspend(void)
28430 @@ -52,7 +53,10 @@ static int omap4_pm_suspend(void)
28431 /* Set targeted power domain states by suspend */
28432 list_for_each_entry(pwrst, &pwrst_list, node) {
28433 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
28434 - pwrdm_set_logic_retst(pwrst->pwrdm, PWRDM_POWER_OFF);
28435 + if (!strcmp(pwrst->pwrdm->name, "mpu_pwrdm"))
28436 + pwrdm_set_logic_retst(pwrst->pwrdm, PWRDM_POWER_ON);
28437 + else
28438 + pwrdm_set_logic_retst(pwrst->pwrdm, PWRDM_POWER_OFF);
28439 }
28440
28441 /*
28442 @@ -64,7 +68,7 @@ static int omap4_pm_suspend(void)
28443 * domain CSWR is not supported by hardware.
28444 * More details can be found in OMAP4430 TRM section 4.3.4.2.
28445 */
28446 - omap4_enter_lowpower(cpu_id, PWRDM_POWER_OFF);
28447 + omap4_enter_lowpower(cpu_id, cpu_suspend_state);
28448
28449 /* Restore next powerdomain state */
28450 list_for_each_entry(pwrst, &pwrst_list, node) {
28451 @@ -199,6 +203,32 @@ static inline int omap4_init_static_deps
28452 }
28453
28454 /**
28455 + * omap5_dra7_init_static_deps - Init static clkdm dependencies on OMAP5
28456 + * and DRA7
28457 + *
28458 + * The dynamic dependency between MPUSS -> EMIF is broken and has
28459 + * not worked as expected. The hardware recommendation is to
28460 + * enable static dependencies for these to avoid system
28461 + * lock ups or random crashes.
28462 + */
28463 +static inline int omap5_dra7_init_static_deps(void)
28464 +{
28465 + struct clockdomain *mpuss_clkdm, *emif_clkdm;
28466 + int ret;
28467 +
28468 + mpuss_clkdm = clkdm_lookup("mpu_clkdm");
28469 + emif_clkdm = clkdm_lookup("emif_clkdm");
28470 + if (!mpuss_clkdm || !emif_clkdm)
28471 + return -EINVAL;
28472 +
28473 + ret = clkdm_add_wkdep(mpuss_clkdm, emif_clkdm);
28474 + if (ret)
28475 + pr_err("Failed to add MPUSS -> EMIF wakeup dependency\n");
28476 +
28477 + return ret;
28478 +}
28479 +
28480 +/**
28481 * omap4_pm_init - Init routine for OMAP4+ devices
28482 *
28483 * Initializes all powerdomain and clockdomain target states
28484 @@ -222,10 +252,14 @@ int __init omap4_pm_init(void)
28485 goto err2;
28486 }
28487
28488 - if (cpu_is_omap44xx()) {
28489 + if (cpu_is_omap44xx())
28490 ret = omap4_init_static_deps();
28491 - if (ret)
28492 - goto err2;
28493 + else if (soc_is_omap54xx() || soc_is_dra7xx())
28494 + ret = omap5_dra7_init_static_deps();
28495 +
28496 + if (ret) {
28497 + pr_err("Failed to initialise static dependencies.\n");
28498 + goto err2;
28499 }
28500
28501 ret = omap4_mpuss_init();
28502 @@ -246,6 +280,11 @@ int __init omap4_pm_init(void)
28503 if (cpu_is_omap44xx())
28504 omap4_idle_init();
28505
28506 + if (soc_is_dra7xx())
28507 + cpu_suspend_state = PWRDM_POWER_RET;
28508 + else
28509 + cpu_suspend_state = PWRDM_POWER_OFF;
28510 +
28511 err2:
28512 return ret;
28513 }
28514 --- a/arch/arm/mach-omap2/pm.c
28515 +++ b/arch/arm/mach-omap2/pm.c
28516 @@ -266,7 +266,12 @@ static void __init omap4_init_voltages(v
28517
28518 static inline void omap_init_cpufreq(void)
28519 {
28520 - struct platform_device_info devinfo = { .name = "omap-cpufreq", };
28521 + struct platform_device_info devinfo = { };
28522 +
28523 + if (!of_have_populated_dt())
28524 + devinfo.name = "omap-cpufreq";
28525 + else
28526 + devinfo.name = "cpufreq-cpu0";
28527 platform_device_register_full(&devinfo);
28528 }
28529
28530 @@ -300,13 +305,16 @@ int __init omap2_common_pm_late_init(voi
28531 /* Smartreflex device init */
28532 omap_devinit_smartreflex();
28533
28534 - /* cpufreq dummy device instantiation */
28535 - omap_init_cpufreq();
28536 }
28537
28538 -#ifdef CONFIG_SUSPEND
28539 - suspend_set_ops(&omap_pm_ops);
28540 -#endif
28541 + /* cpufreq dummy device instantiation */
28542 + omap_init_cpufreq();
28543
28544 return 0;
28545 }
28546 +
28547 +void __init omap2_common_suspend_init(void)
28548 +{
28549 + suspend_set_ops(&omap_pm_ops);
28550 +}
28551 +
28552 --- a/arch/arm/mach-omap2/pm.h
28553 +++ b/arch/arm/mach-omap2/pm.h
28554 @@ -82,6 +82,11 @@ extern unsigned int omap3_do_wfi_sz;
28555 /* ... and its pointer from SRAM after copy */
28556 extern void (*omap3_do_wfi_sram)(void);
28557
28558 +/* am33xx_do_wfi function pointer and size, for copy to SRAM */
28559 +extern void am33xx_do_wfi(void);
28560 +extern unsigned int am33xx_do_wfi_sz;
28561 +extern unsigned int am33xx_resume_offset;
28562 +
28563 /* save_secure_ram_context function pointer and size, for copy to SRAM */
28564 extern int save_secure_ram_context(u32 *addr);
28565 extern unsigned int save_secure_ram_context_sz;
28566 --- a/arch/arm/mach-omap2/powerdomain.h
28567 +++ b/arch/arm/mach-omap2/powerdomain.h
28568 @@ -254,6 +254,7 @@ extern void omap242x_powerdomains_init(v
28569 extern void omap243x_powerdomains_init(void);
28570 extern void omap3xxx_powerdomains_init(void);
28571 extern void am33xx_powerdomains_init(void);
28572 +extern void am43xx_powerdomains_init(void);
28573 extern void omap44xx_powerdomains_init(void);
28574 extern void omap54xx_powerdomains_init(void);
28575 extern void dra7xx_powerdomains_init(void);
28576 --- /dev/null
28577 +++ b/arch/arm/mach-omap2/powerdomains43xx_data.c
28578 @@ -0,0 +1,145 @@
28579 +/*
28580 + * AM43xx Power domains framework
28581 + *
28582 + * Copyright (C) 2013 Texas Instruments, Inc.
28583 + *
28584 + * This file is made by modifying the file generated automatically
28585 + * from the OMAP hardware databases.
28586 + *
28587 + * This program is free software; you can redistribute it and/or modify
28588 + * it under the terms of the GNU General Public License version 2 as
28589 + * published by the Free Software Foundation.
28590 + */
28591 +
28592 +#include <linux/kernel.h>
28593 +#include <linux/init.h>
28594 +
28595 +#include "powerdomain.h"
28596 +
28597 +#include "prcm-common.h"
28598 +#include "prcm44xx.h"
28599 +#include "prcm43xx.h"
28600 +
28601 +static struct powerdomain gfx_43xx_pwrdm = {
28602 + .name = "gfx_pwrdm",
28603 + .voltdm = { .name = "core" },
28604 + .prcm_offs = AM43XX_PRM_GFX_INST,
28605 + .prcm_partition = AM43XX_PRM_PARTITION,
28606 + .pwrsts = PWRSTS_OFF_ON,
28607 + .banks = 1,
28608 + .pwrsts_mem_ret = {
28609 + [0] = PWRSTS_OFF_RET, /* gfx_mem */
28610 + },
28611 + .pwrsts_mem_on = {
28612 + [0] = PWRSTS_ON, /* gfx_mem */
28613 + },
28614 + .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
28615 +};
28616 +
28617 +static struct powerdomain mpu_43xx_pwrdm = {
28618 + .name = "mpu_pwrdm",
28619 + .voltdm = { .name = "mpu" },
28620 + .prcm_offs = AM43XX_PRM_MPU_INST,
28621 + .prcm_partition = AM43XX_PRM_PARTITION,
28622 + .pwrsts = PWRSTS_OFF_RET_ON,
28623 + .pwrsts_logic_ret = PWRSTS_OFF_RET,
28624 + .banks = 3,
28625 + .pwrsts_mem_ret = {
28626 + [0] = PWRSTS_OFF_RET, /* mpu_l1 */
28627 + [1] = PWRSTS_OFF_RET, /* mpu_l2 */
28628 + [2] = PWRSTS_OFF_RET, /* mpu_ram */
28629 + },
28630 + .pwrsts_mem_on = {
28631 + [0] = PWRSTS_ON, /* mpu_l1 */
28632 + [1] = PWRSTS_ON, /* mpu_l2 */
28633 + [2] = PWRSTS_ON, /* mpu_ram */
28634 + },
28635 + .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
28636 +};
28637 +
28638 +static struct powerdomain rtc_43xx_pwrdm = {
28639 + .name = "rtc_pwrdm",
28640 + .voltdm = { .name = "rtc" },
28641 + .prcm_offs = AM43XX_PRM_RTC_INST,
28642 + .prcm_partition = AM43XX_PRM_PARTITION,
28643 + .pwrsts = PWRSTS_ON,
28644 +};
28645 +
28646 +static struct powerdomain wkup_43xx_pwrdm = {
28647 + .name = "wkup_pwrdm",
28648 + .voltdm = { .name = "core" },
28649 + .prcm_offs = AM43XX_PRM_WKUP_INST,
28650 + .prcm_partition = AM43XX_PRM_PARTITION,
28651 + .pwrsts = PWRSTS_ON,
28652 + .banks = 1,
28653 + .pwrsts_mem_ret = {
28654 + [0] = PWRSTS_OFF, /* debugss_mem */
28655 + },
28656 + .pwrsts_mem_on = {
28657 + [0] = PWRSTS_ON, /* debugss_mem */
28658 + },
28659 +};
28660 +
28661 +static struct powerdomain tamper_43xx_pwrdm = {
28662 + .name = "tamper_pwrdm",
28663 + .voltdm = { .name = "tamper" },
28664 + .prcm_offs = AM43XX_PRM_TAMPER_INST,
28665 + .prcm_partition = AM43XX_PRM_PARTITION,
28666 + .pwrsts = PWRSTS_ON,
28667 +};
28668 +
28669 +static struct powerdomain cefuse_43xx_pwrdm = {
28670 + .name = "cefuse_pwrdm",
28671 + .voltdm = { .name = "core" },
28672 + .prcm_offs = AM43XX_PRM_CEFUSE_INST,
28673 + .prcm_partition = AM43XX_PRM_PARTITION,
28674 + .pwrsts = PWRSTS_OFF_ON,
28675 + .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
28676 +};
28677 +
28678 +static struct powerdomain per_43xx_pwrdm = {
28679 + .name = "per_pwrdm",
28680 + .voltdm = { .name = "core" },
28681 + .prcm_offs = AM43XX_PRM_PER_INST,
28682 + .prcm_partition = AM43XX_PRM_PARTITION,
28683 + .pwrsts = PWRSTS_OFF_RET_ON,
28684 + .pwrsts_logic_ret = PWRSTS_OFF_RET,
28685 + .banks = 4,
28686 + .pwrsts_mem_ret = {
28687 + [0] = PWRSTS_OFF_RET, /* icss_mem */
28688 + [1] = PWRSTS_OFF_RET, /* per_mem */
28689 + [2] = PWRSTS_OFF_RET, /* ram1_mem */
28690 + [3] = PWRSTS_OFF_RET, /* ram2_mem */
28691 + },
28692 + .pwrsts_mem_on = {
28693 + [0] = PWRSTS_OFF_RET, /* icss_mem */
28694 + [1] = PWRSTS_ON, /* per_mem */
28695 + [2] = PWRSTS_OFF_RET, /* ram1_mem */
28696 + [3] = PWRSTS_OFF_RET, /* ram2_mem */
28697 + },
28698 + .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
28699 +};
28700 +
28701 +static struct powerdomain *powerdomains_am43xx[] __initdata = {
28702 + &gfx_43xx_pwrdm,
28703 + &mpu_43xx_pwrdm,
28704 + &rtc_43xx_pwrdm,
28705 + &wkup_43xx_pwrdm,
28706 + &tamper_43xx_pwrdm,
28707 + &cefuse_43xx_pwrdm,
28708 + &per_43xx_pwrdm,
28709 + NULL
28710 +};
28711 +
28712 +static int am43xx_check_vcvp(void)
28713 +{
28714 + return 0;
28715 +}
28716 +
28717 +void __init am43xx_powerdomains_init(void)
28718 +{
28719 + omap4_pwrdm_operations.pwrdm_has_voltdm = am43xx_check_vcvp;
28720 + pwrdm_register_platform_funcs(&omap4_pwrdm_operations);
28721 + pwrdm_register_pwrdms(powerdomains_am43xx);
28722 + pwrdm_complete_init();
28723 +}
28724 --- /dev/null
28725 +++ b/arch/arm/mach-omap2/prcm43xx.h
28726 @@ -0,0 +1,149 @@
28727 +/*
28728 + * AM43x PRCM defines
28729 + *
28730 + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
28731 + *
28732 + * This file is licensed under the terms of the GNU General Public License
28733 + * version 2. This program is licensed "as is" without any warranty of any
28734 + * kind, whether express or implied.
28735 + */
28736 +
28737 +#ifndef __ARCH_ARM_MACH_OMAP2_PRCM_43XX_H
28738 +#define __ARCH_ARM_MACH_OMAP2_PRCM_43XX_H
28739 +
28740 +#define AM43XX_PRM_PARTITION 1
28741 +#define AM43XX_CM_PARTITION 1
28742 +
28743 +/* PRM instances */
28744 +#define AM43XX_PRM_OCP_SOCKET_INST 0x0000
28745 +#define AM43XX_PRM_MPU_INST 0x0300
28746 +#define AM43XX_PRM_GFX_INST 0x0400
28747 +#define AM43XX_PRM_RTC_INST 0x0500
28748 +#define AM43XX_PRM_TAMPER_INST 0x0600
28749 +#define AM43XX_PRM_CEFUSE_INST 0x0700
28750 +#define AM43XX_PRM_PER_INST 0x0800
28751 +#define AM43XX_PRM_WKUP_INST 0x2000
28752 +#define AM43XX_PRM_DEVICE_INST 0x4000
28753 +
28754 +/* RM RSTCTRL offsets */
28755 +#define AM43XX_RM_PER_RSTCTRL_OFFSET 0x0010
28756 +#define AM43XX_RM_GFX_RSTCTRL_OFFSET 0x0010
28757 +#define AM43XX_RM_WKUP_RSTCTRL_OFFSET 0x0010
28758 +
28759 +/* RM RSTST offsets */
28760 +#define AM43XX_RM_GFX_RSTST_OFFSET 0x0014
28761 +#define AM43XX_RM_WKUP_RSTST_OFFSET 0x0014
28762 +
28763 +/* CM instances */
28764 +#define AM43XX_CM_WKUP_INST 0x2800
28765 +#define AM43XX_CM_DEVICE_INST 0x4100
28766 +#define AM43XX_CM_DPLL_INST 0x4200
28767 +#define AM43XX_CM_MPU_INST 0x8300
28768 +#define AM43XX_CM_GFX_INST 0x8400
28769 +#define AM43XX_CM_RTC_INST 0x8500
28770 +#define AM43XX_CM_TAMPER_INST 0x8600
28771 +#define AM43XX_CM_CEFUSE_INST 0x8700
28772 +#define AM43XX_CM_PER_INST 0x8800
28773 +
28774 +/* CD offsets */
28775 +#define AM43XX_CM_WKUP_L3_AON_CDOFFS 0x0000
28776 +#define AM43XX_CM_WKUP_L3S_TSC_CDOFFS 0x0100
28777 +#define AM43XX_CM_WKUP_L4_WKUP_AON_CDOFFS 0x0200
28778 +#define AM43XX_CM_WKUP_WKUP_CDOFFS 0x0300
28779 +#define AM43XX_CM_MPU_MPU_CDOFFS 0x0000
28780 +#define AM43XX_CM_GFX_GFX_L3_CDOFFS 0x0000
28781 +#define AM43XX_CM_RTC_RTC_CDOFFS 0x0000
28782 +#define AM43XX_CM_TAMPER_TAMPER_CDOFFS 0x0000
28783 +#define AM43XX_CM_CEFUSE_CEFUSE_CDOFFS 0x0000
28784 +#define AM43XX_CM_PER_L3_CDOFFS 0x0000
28785 +#define AM43XX_CM_PER_L3S_CDOFFS 0x0200
28786 +#define AM43XX_CM_PER_ICSS_CDOFFS 0x0300
28787 +#define AM43XX_CM_PER_L4LS_CDOFFS 0x0400
28788 +#define AM43XX_CM_PER_EMIF_CDOFFS 0x0700
28789 +#define AM43XX_CM_PER_DSS_CDOFFS 0x0a00
28790 +#define AM43XX_CM_PER_CPSW_CDOFFS 0x0b00
28791 +#define AM43XX_CM_PER_OCPWP_L3_CDOFFS 0x0c00
28792 +
28793 +/* CLK CTRL offsets */
28794 +#define AM43XX_CM_PER_UART1_CLKCTRL_OFFSET 0x0580
28795 +#define AM43XX_CM_PER_UART2_CLKCTRL_OFFSET 0x0588
28796 +#define AM43XX_CM_PER_UART3_CLKCTRL_OFFSET 0x0590
28797 +#define AM43XX_CM_PER_UART4_CLKCTRL_OFFSET 0x0598
28798 +#define AM43XX_CM_PER_UART5_CLKCTRL_OFFSET 0x05a0
28799 +#define AM43XX_CM_PER_DCAN0_CLKCTRL_OFFSET 0x0428
28800 +#define AM43XX_CM_PER_DCAN1_CLKCTRL_OFFSET 0x0430
28801 +#define AM43XX_CM_PER_ELM_CLKCTRL_OFFSET 0x0468
28802 +#define AM43XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET 0x0438
28803 +#define AM43XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET 0x0440
28804 +#define AM43XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET 0x0448
28805 +#define AM43XX_CM_PER_GPIO1_CLKCTRL_OFFSET 0x0478
28806 +#define AM43XX_CM_PER_GPIO2_CLKCTRL_OFFSET 0x0480
28807 +#define AM43XX_CM_PER_GPIO3_CLKCTRL_OFFSET 0x0488
28808 +#define AM43XX_CM_PER_I2C1_CLKCTRL_OFFSET 0x04a8
28809 +#define AM43XX_CM_PER_I2C2_CLKCTRL_OFFSET 0x04b0
28810 +#define AM43XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET 0x04b8
28811 +#define AM43XX_CM_PER_MMC0_CLKCTRL_OFFSET 0x04c0
28812 +#define AM43XX_CM_PER_MMC1_CLKCTRL_OFFSET 0x04c8
28813 +#define AM43XX_CM_PER_DES_CLKCTRL_OFFSET 0x0030
28814 +#define AM43XX_CM_PER_RNG_CLKCTRL_OFFSET 0x04e0
28815 +#define AM43XX_CM_PER_SPI0_CLKCTRL_OFFSET 0x0500
28816 +#define AM43XX_CM_PER_SPI1_CLKCTRL_OFFSET 0x0508
28817 +#define AM43XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET 0x0528
28818 +#define AM43XX_CM_PER_TIMER2_CLKCTRL_OFFSET 0x0530
28819 +#define AM43XX_CM_PER_TIMER3_CLKCTRL_OFFSET 0x0538
28820 +#define AM43XX_CM_PER_TIMER4_CLKCTRL_OFFSET 0x0540
28821 +#define AM43XX_CM_PER_TIMER5_CLKCTRL_OFFSET 0x0548
28822 +#define AM43XX_CM_PER_TIMER6_CLKCTRL_OFFSET 0x0550
28823 +#define AM43XX_CM_PER_TIMER7_CLKCTRL_OFFSET 0x0558
28824 +#define AM43XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET 0x0228
28825 +#define AM43XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET 0x0360
28826 +#define AM43XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET 0x0350
28827 +#define AM43XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET 0x0358
28828 +#define AM43XX_CM_WKUP_UART0_CLKCTRL_OFFSET 0x0348
28829 +#define AM43XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET 0x0328
28830 +#define AM43XX_CM_WKUP_I2C0_CLKCTRL_OFFSET 0x0340
28831 +#define AM43XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET 0x0368
28832 +#define AM43XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET 0x0120
28833 +#define AM43XX_CM_WKUP_WDT1_CLKCTRL_OFFSET 0x0338
28834 +#define AM43XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET 0x0220
28835 +#define AM43XX_CM_RTC_RTC_CLKCTRL_OFFSET 0x0020
28836 +#define AM43XX_CM_PER_MMC2_CLKCTRL_OFFSET 0x0248
28837 +#define AM43XX_CM_PER_QSPI_CLKCTRL_OFFSET 0x0258
28838 +#define AM43XX_CM_PER_USB_OTG_SS0_CLKCTRL_OFFSET 0x0260
28839 +#define AM43XX_CM_PER_USBPHYOCP2SCP0_CLKCTRL_OFFSET 0x05B8
28840 +#define AM43XX_CM_PER_USB_OTG_SS1_CLKCTRL_OFFSET 0x0268
28841 +#define AM43XX_CM_PER_USBPHYOCP2SCP1_CLKCTRL_OFFSET 0x05C0
28842 +#define AM43XX_CM_PER_GPMC_CLKCTRL_OFFSET 0x0220
28843 +#define AM43XX_CM_PER_MCASP0_CLKCTRL_OFFSET 0x0238
28844 +#define AM43XX_CM_PER_MCASP1_CLKCTRL_OFFSET 0x0240
28845 +#define AM43XX_CM_PER_L4LS_CLKCTRL_OFFSET 0x0420
28846 +#define AM43XX_CM_PER_L3_CLKCTRL_OFFSET 0x0020
28847 +#define AM43XX_CM_PER_TPCC_CLKCTRL_OFFSET 0x0078
28848 +#define AM43XX_CM_PER_TPTC0_CLKCTRL_OFFSET 0x0080
28849 +#define AM43XX_CM_PER_TPTC1_CLKCTRL_OFFSET 0x0088
28850 +#define AM43XX_CM_PER_TPTC2_CLKCTRL_OFFSET 0x0090
28851 +#define AM43XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET 0x0b20
28852 +#define AM43XX_CM_PER_PRUSS_CLKCTRL_OFFSET 0x0320
28853 +#define AM43XX_CM_GFX_GFX_CLKCTRL_OFFSET 0x0020
28854 +#define AM43XX_CM_PER_L4HS_CLKCTRL_OFFSET 0x00a0
28855 +#define AM43XX_CM_MPU_MPU_CLKCTRL_OFFSET 0x0020
28856 +#define AM43XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET 0x0040
28857 +#define AM43XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET 0x0050
28858 +#define AM43XX_CM_PER_SHA0_CLKCTRL_OFFSET 0x0058
28859 +#define AM43XX_CM_PER_AES0_CLKCTRL_OFFSET 0x0028
28860 +#define AM43XX_CM_PER_TIMER8_CLKCTRL_OFFSET 0x0560
28861 +#define AM43XX_CM_PER_TIMER9_CLKCTRL_OFFSET 0x0568
28862 +#define AM43XX_CM_PER_TIMER10_CLKCTRL_OFFSET 0x0570
28863 +#define AM43XX_CM_PER_TIMER11_CLKCTRL_OFFSET 0x0578
28864 +#define AM43XX_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET 0x0230
28865 +#define AM43XX_CM_PER_EPWMSS3_CLKCTRL_OFFSET 0x0450
28866 +#define AM43XX_CM_PER_EPWMSS4_CLKCTRL_OFFSET 0x0458
28867 +#define AM43XX_CM_PER_EPWMSS5_CLKCTRL_OFFSET 0x0460
28868 +#define AM43XX_CM_PER_SPI2_CLKCTRL_OFFSET 0x0510
28869 +#define AM43XX_CM_PER_SPI3_CLKCTRL_OFFSET 0x0518
28870 +#define AM43XX_CM_PER_SPI4_CLKCTRL_OFFSET 0x0520
28871 +#define AM43XX_CM_PER_GPIO4_CLKCTRL_OFFSET 0x0490
28872 +#define AM43XX_CM_PER_GPIO5_CLKCTRL_OFFSET 0x0498
28873 +#define AM43XX_CM_PER_DSS_CLKCTRL_OFFSET 0x0a20
28874 +
28875 +#endif
28876 --- a/arch/arm/mach-omap2/prminst44xx.c
28877 +++ b/arch/arm/mach-omap2/prminst44xx.c
28878 @@ -182,12 +182,10 @@ void omap4_prminst_global_warm_sw_reset(
28879 v = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION, dev_inst,
28880 OMAP4_PRM_RSTCTRL_OFFSET);
28881 v |= OMAP4430_RST_GLOBAL_WARM_SW_MASK;
28882 - omap4_prminst_write_inst_reg(v, OMAP4430_PRM_PARTITION,
28883 - OMAP4430_PRM_DEVICE_INST,
28884 + omap4_prminst_write_inst_reg(v, OMAP4430_PRM_PARTITION, dev_inst,
28885 OMAP4_PRM_RSTCTRL_OFFSET);
28886
28887 /* OCP barrier */
28888 - v = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
28889 - OMAP4430_PRM_DEVICE_INST,
28890 + v = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION, dev_inst,
28891 OMAP4_PRM_RSTCTRL_OFFSET);
28892 }
28893 --- /dev/null
28894 +++ b/arch/arm/mach-omap2/sleep33xx.S
28895 @@ -0,0 +1,362 @@
28896 +/*
28897 + * Low level suspend code for AM33XX SoCs
28898 + *
28899 + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
28900 + * Vaibhav Bedia <vaibhav.bedia@ti.com>
28901 + *
28902 + * This program is free software; you can redistribute it and/or
28903 + * modify it under the terms of the GNU General Public License as
28904 + * published by the Free Software Foundation version 2.
28905 + *
28906 + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
28907 + * kind, whether express or implied; without even the implied warranty
28908 + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28909 + * GNU General Public License for more details.
28910 + */
28911 +
28912 +#include <linux/linkage.h>
28913 +#include <linux/ti_emif.h>
28914 +#include <asm/memory.h>
28915 +#include <asm/assembler.h>
28916 +
28917 +#include "cm33xx.h"
28918 +#include "pm33xx.h"
28919 +#include "prm33xx.h"
28920 +
28921 +#define EMIF_POWER_MGMT_WAIT_SELF_REFRESH_8192_CYCLES 0x00a0
28922 +#define EMIF_POWER_MGMT_SR_TIMER_MASK 0x00f0
28923 +
28924 +#define EMIF_POWER_MGMT_SELF_REFRESH_MODE 0x0200
28925 +#define EMIF_POWER_MGMT_SELF_REFRESH_MODE_MASK 0x0700
28926 +#define EMIF_POWER_MGMT_DELAY_PERIOD 0x1000
28927 +
28928 +#define AM33XX_CM_CLKCTRL_MODULEMODE_DISABLE 0x0003
28929 +#define AM33XX_CM_CLKCTRL_MODULEMODE_ENABLE 0x0002
28930 +
28931 + .text
28932 + .align 3
28933 +
28934 +/*
28935 + * This routine is executed from internal RAM and expects some
28936 + * parameters to be passed in r0 _strictly_ in following order:
28937 + * 1) emif_addr_virt - ioremapped EMIF address
28938 + * 2) mem_type - 2 -> DDR2, 3-> DDR3
28939 + * 3) dram_sync_word - uncached word in SDRAM
28940 + *
28941 + * The code loads these values taking r0 value as reference to
28942 + * the array in registers starting from r0, i.e emif_addr_virt
28943 + * goes to r1, mem_type goes to r2 and and so on. These are
28944 + * then saved into memory locations before proceeding with the
28945 + * sleep sequence and hence registers r0, r1 etc can still be
28946 + * used in the rest of the sleep code.
28947 + */
28948 +
28949 +ENTRY(am33xx_do_wfi)
28950 + stmfd sp!, {r4 - r11, lr} @ save registers on stack
28951 +
28952 + ldm r0, {r1-r3} @ gather values passed
28953 +
28954 + /* Save the values passed */
28955 + str r1, emif_addr_virt
28956 + str r2, mem_type
28957 + str r3, dram_sync_word
28958 +
28959 + /*
28960 + * Flush all data from the L1 and L2 data cache before disabling
28961 + * SCTLR.C bit.
28962 + */
28963 + ldr r1, kernel_flush
28964 + blx r1
28965 +
28966 + /*
28967 + * Clear the SCTLR.C bit to prevent further data cache
28968 + * allocation. Clearing SCTLR.C would make all the data accesses
28969 + * strongly ordered and would not hit the cache.
28970 + */
28971 + mrc p15, 0, r0, c1, c0, 0
28972 + bic r0, r0, #(1 << 2) @ Disable the C bit
28973 + mcr p15, 0, r0, c1, c0, 0
28974 + isb
28975 +
28976 + /*
28977 + * Invalidate L1 and L2 data cache.
28978 + */
28979 + ldr r1, kernel_flush
28980 + blx r1
28981 +
28982 + ldr r0, emif_addr_virt
28983 + /* Save EMIF configuration */
28984 + ldr r1, [r0, #EMIF_SDRAM_CONFIG]
28985 + str r1, emif_sdcfg_val
28986 + ldr r1, [r0, #EMIF_SDRAM_REFRESH_CONTROL]
28987 + str r1, emif_ref_ctrl_val
28988 + ldr r1, [r0, #EMIF_SDRAM_TIMING_1]
28989 + str r1, emif_timing1_val
28990 + ldr r1, [r0, #EMIF_SDRAM_TIMING_2]
28991 + str r1, emif_timing2_val
28992 + ldr r1, [r0, #EMIF_SDRAM_TIMING_3]
28993 + str r1, emif_timing3_val
28994 + ldr r1, [r0, #EMIF_POWER_MANAGEMENT_CONTROL]
28995 + str r1, emif_pmcr_val
28996 + ldr r1, [r0, #EMIF_POWER_MANAGEMENT_CTRL_SHDW]
28997 + str r1, emif_pmcr_shdw_val
28998 + ldr r1, [r0, #EMIF_SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG]
28999 + str r1, emif_zqcfg_val
29000 + ldr r1, [r0, #EMIF_DDR_PHY_CTRL_1]
29001 + str r1, emif_rd_lat_val
29002 +
29003 + /* Put SDRAM in self-refresh */
29004 + ldr r1, [r0, #EMIF_POWER_MANAGEMENT_CONTROL]
29005 + bic r1, r1, #EMIF_POWER_MGMT_SR_TIMER_MASK
29006 + orr r1, r1, #EMIF_POWER_MGMT_WAIT_SELF_REFRESH_8192_CYCLES
29007 + str r1, [r0, #EMIF_POWER_MANAGEMENT_CONTROL]
29008 + str r1, [r0, #EMIF_POWER_MANAGEMENT_CTRL_SHDW]
29009 +
29010 + ldr r1, [r0, #EMIF_POWER_MANAGEMENT_CONTROL]
29011 + bic r1, r1, #EMIF_POWER_MGMT_SELF_REFRESH_MODE_MASK
29012 + orr r1, r1, #EMIF_POWER_MGMT_SELF_REFRESH_MODE
29013 + str r1, [r0, #EMIF_POWER_MANAGEMENT_CONTROL]
29014 +
29015 + ldr r1, dram_sync_word @ a dummy access to DDR as per spec
29016 + ldr r2, [r1, #0]
29017 +
29018 +
29019 + mov r1, #EMIF_POWER_MGMT_DELAY_PERIOD @ Wait for system
29020 +wait_self_refresh: @ to enter SR
29021 + subs r1, r1, #1
29022 + bne wait_self_refresh
29023 +
29024 + /* Disable EMIF */
29025 + ldr r1, virt_emif_clkctrl
29026 + ldr r2, [r1]
29027 + bic r2, r2, #AM33XX_CM_CLKCTRL_MODULEMODE_DISABLE
29028 + str r2, [r1]
29029 +
29030 + ldr r1, virt_emif_clkctrl
29031 +wait_emif_disable:
29032 + ldr r2, [r1]
29033 + ldr r3, module_disabled_val
29034 + cmp r2, r3
29035 + bne wait_emif_disable
29036 +
29037 + /*
29038 + * For the MPU WFI to be registered as an interrupt
29039 + * to WKUP_M3, MPU_CLKCTRL.MODULEMODE needs to be set
29040 + * to DISABLED
29041 + */
29042 + ldr r1, virt_mpu_clkctrl
29043 + ldr r2, [r1]
29044 + bic r2, r2, #AM33XX_CM_CLKCTRL_MODULEMODE_DISABLE
29045 + str r2, [r1]
29046 +
29047 + /*
29048 + * Execute an ISB instruction to ensure that all of the
29049 + * CP15 register changes have been committed.
29050 + */
29051 + isb
29052 +
29053 + /*
29054 + * Execute a barrier instruction to ensure that all cache,
29055 + * TLB and branch predictor maintenance operations issued
29056 + * have completed.
29057 + */
29058 + dsb
29059 + dmb
29060 +
29061 + /*
29062 + * Execute a WFI instruction and wait until the
29063 + * STANDBYWFI output is asserted to indicate that the
29064 + * CPU is in idle and low power state. CPU can specualatively
29065 + * prefetch the instructions so add NOPs after WFI. Thirteen
29066 + * NOPs as per Cortex-A8 pipeline.
29067 + */
29068 + wfi
29069 +
29070 + nop
29071 + nop
29072 + nop
29073 + nop
29074 + nop
29075 + nop
29076 + nop
29077 + nop
29078 + nop
29079 + nop
29080 + nop
29081 + nop
29082 + nop
29083 +
29084 + /* We come here in case of an abort due to a late interrupt */
29085 +
29086 + /* Set MPU_CLKCTRL.MODULEMODE back to ENABLE */
29087 + ldr r1, virt_mpu_clkctrl
29088 + mov r2, #AM33XX_CM_CLKCTRL_MODULEMODE_ENABLE
29089 + str r2, [r1]
29090 +
29091 + /* Re-enable EMIF */
29092 + ldr r1, virt_emif_clkctrl
29093 + mov r2, #AM33XX_CM_CLKCTRL_MODULEMODE_ENABLE
29094 + str r2, [r1]
29095 +wait_emif_enable:
29096 + ldr r3, [r1]
29097 + cmp r2, r3
29098 + bne wait_emif_enable
29099 +
29100 + /* Disable EMIF self-refresh */
29101 + ldr r0, emif_addr_virt
29102 + ldr r1, [r0, #EMIF_POWER_MANAGEMENT_CONTROL]
29103 + bic r1, r1, #LP_MODE_MASK
29104 + str r1, [r0, #EMIF_POWER_MANAGEMENT_CONTROL]
29105 + str r1, [r0, #EMIF_POWER_MANAGEMENT_CTRL_SHDW]
29106 +
29107 + /*
29108 + * A write to SDRAM CONFIG register triggers
29109 + * an init sequence and hence it must be done
29110 + * at the end for DDR2
29111 + */
29112 + ldr r0, emif_addr_virt
29113 + add r0, r0, #EMIF_SDRAM_CONFIG
29114 + ldr r4, emif_sdcfg_val
29115 + str r4, [r0]
29116 +
29117 + /*
29118 + * Set SCTLR.C bit to allow data cache allocation
29119 + */
29120 + mrc p15, 0, r0, c1, c0, 0
29121 + orr r0, r0, #(1 << 2) @ Enable the C bit
29122 + mcr p15, 0, r0, c1, c0, 0
29123 + isb
29124 +
29125 + /* EMIF needs some time before read/write possible */
29126 + mov r0, #EMIF_POWER_MGMT_DELAY_PERIOD
29127 +wait_abt:
29128 + subs r0, r0, #1
29129 + bne wait_abt
29130 +
29131 + /* Let the suspend code know about the abort */
29132 + mov r0, #1
29133 + ldmfd sp!, {r4 - r11, pc} @ restore regs and return
29134 +ENDPROC(am33xx_do_wfi)
29135 +
29136 + .align
29137 +ENTRY(am33xx_resume_offset)
29138 + .word . - am33xx_do_wfi
29139 +
29140 +ENTRY(am33xx_resume_from_deep_sleep)
29141 + /* Re-enable EMIF */
29142 + ldr r0, phys_emif_clkctrl
29143 + mov r1, #AM33XX_CM_CLKCTRL_MODULEMODE_ENABLE
29144 + str r1, [r0]
29145 +wait_emif_enable1:
29146 + ldr r2, [r0]
29147 + cmp r1, r2
29148 + bne wait_emif_enable1
29149 +
29150 + /* Config EMIF Timings */
29151 + ldr r0, emif_phys_addr
29152 + ldr r1, emif_rd_lat_val
29153 + str r1, [r0, #EMIF_DDR_PHY_CTRL_1]
29154 + str r1, [r0, #EMIF_DDR_PHY_CTRL_1_SHDW]
29155 + ldr r1, emif_timing1_val
29156 + str r1, [r0, #EMIF_SDRAM_TIMING_1]
29157 + str r1, [r0, #EMIF_SDRAM_TIMING_1_SHDW]
29158 + ldr r1, emif_timing2_val
29159 + str r1, [r0, #EMIF_SDRAM_TIMING_2]
29160 + str r1, [r0, #EMIF_SDRAM_TIMING_2_SHDW]
29161 + ldr r1, emif_timing3_val
29162 + str r1, [r0, #EMIF_SDRAM_TIMING_3]
29163 + str r1, [r0, #EMIF_SDRAM_TIMING_3_SHDW]
29164 + ldr r1, emif_ref_ctrl_val
29165 + str r1, [r0, #EMIF_SDRAM_REFRESH_CONTROL]
29166 + str r1, [r0, #EMIF_SDRAM_REFRESH_CTRL_SHDW]
29167 + ldr r1, emif_pmcr_val
29168 + str r1, [r0, #EMIF_POWER_MANAGEMENT_CONTROL]
29169 + ldr r1, emif_pmcr_shdw_val
29170 + str r1, [r0, #EMIF_POWER_MANAGEMENT_CTRL_SHDW]
29171 +
29172 + /*
29173 + * Output impedence calib needed only for DDR3
29174 + * but since the initial state of this will be
29175 + * disabled for DDR2 no harm in restoring the
29176 + * old configuration
29177 + */
29178 + ldr r1, emif_zqcfg_val
29179 + str r1, [r0, #EMIF_SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG]
29180 +
29181 + /* Write to SDRAM_CONFIG only for DDR2 */
29182 + ldr r2, mem_type
29183 + cmp r2, #MEM_TYPE_DDR2
29184 + bne resume_to_ddr
29185 +
29186 + /*
29187 + * A write to SDRAM CONFIG register triggers
29188 + * an init sequence and hence it must be done
29189 + * at the end for DDR2
29190 + */
29191 + ldr r1, emif_sdcfg_val
29192 + str r1, [r0, #EMIF_SDRAM_CONFIG]
29193 +
29194 +resume_to_ddr:
29195 + /* EMIF needs some time before read/write possible */
29196 + mov r0, #EMIF_POWER_MGMT_DELAY_PERIOD
29197 +wait_resume:
29198 + subs r0, r0, #1
29199 + bne wait_resume
29200 +
29201 + /* We are back. Branch to the common CPU resume routine */
29202 + mov r0, #0
29203 + ldr pc, resume_addr
29204 +ENDPROC(am33xx_resume_from_deep_sleep)
29205 +
29206 +
29207 +/*
29208 + * Local variables
29209 + */
29210 + .align
29211 +resume_addr:
29212 + .word cpu_resume - PAGE_OFFSET + 0x80000000
29213 +kernel_flush:
29214 + .word v7_flush_dcache_all
29215 +ddr_start:
29216 + .word PAGE_OFFSET
29217 +emif_phys_addr:
29218 + .word AM33XX_EMIF_BASE
29219 +virt_mpu_clkctrl:
29220 + .word AM33XX_CM_MPU_MPU_CLKCTRL
29221 +virt_emif_clkctrl:
29222 + .word AM33XX_CM_PER_EMIF_CLKCTRL
29223 +phys_emif_clkctrl:
29224 + .word (AM33XX_CM_BASE + AM33XX_CM_PER_MOD + \
29225 + AM33XX_CM_PER_EMIF_CLKCTRL_OFFSET)
29226 +module_disabled_val:
29227 + .word 0x30000
29228 +
29229 +/* DDR related defines */
29230 +dram_sync_word:
29231 + .word 0xDEADBEEF
29232 +mem_type:
29233 + .word 0xDEADBEEF
29234 +emif_addr_virt:
29235 + .word 0xDEADBEEF
29236 +emif_rd_lat_val:
29237 + .word 0xDEADBEEF
29238 +emif_timing1_val:
29239 + .word 0xDEADBEEF
29240 +emif_timing2_val:
29241 + .word 0xDEADBEEF
29242 +emif_timing3_val:
29243 + .word 0xDEADBEEF
29244 +emif_sdcfg_val:
29245 + .word 0xDEADBEEF
29246 +emif_ref_ctrl_val:
29247 + .word 0xDEADBEEF
29248 +emif_zqcfg_val:
29249 + .word 0xDEADBEEF
29250 +emif_pmcr_val:
29251 + .word 0xDEADBEEF
29252 +emif_pmcr_shdw_val:
29253 + .word 0xDEADBEEF
29254 +
29255 + .align 3
29256 +ENTRY(am33xx_do_wfi_sz)
29257 + .word . - am33xx_do_wfi
29258 --- a/arch/arm/mach-omap2/sleep44xx.S
29259 +++ b/arch/arm/mach-omap2/sleep44xx.S
29260 @@ -330,6 +330,141 @@ skip_l2en:
29261 ENDPROC(omap4_cpu_resume)
29262 #endif /* CONFIG_ARCH_OMAP4 */
29263
29264 +#ifdef CONFIG_SOC_OMAP5
29265 +/*
29266 + * ================================
29267 + * == OMAP5 CPU suspend finisher ==
29268 + * ================================
29269 + *
29270 + * OMAP5 MPUSS states for the context save:
29271 + * save_state =
29272 + * 0 - Nothing lost and no need to save: MPUSS INA/CSWR
29273 + * 1 - CPUx L1 and logic lost: CPU OFF, MPUSS INA/CSWR
29274 + * 2 - CPUx L1 and logic lost + GIC lost: MPUSS OSWR
29275 + * 3 - CPUx L1 and logic lost + GIC + L2 lost: DEVICE OFF
29276 + */
29277 +ENTRY(omap5_finish_suspend)
29278 + stmfd sp!, {r4-r12, lr}
29279 + cmp r0, #0x0
29280 + beq do_wfi @ No lowpower state, jump to WFI
29281 +
29282 + /*
29283 + * Flush all data from the L1 data cache before disabling
29284 + * SCTLR.C bit.
29285 + */
29286 + bl omap4_get_sar_ram_base
29287 + ldr r9, [r0, #OMAP_TYPE_OFFSET]
29288 + cmp r9, #0x1 @ Check for HS device
29289 + bne skip_secure_l1_clean_op
29290 + mov r0, #0 @ Clean secure L1
29291 + stmfd r13!, {r4-r12, r14}
29292 + ldr r12, =OMAP5_MON_CACHES_CLEAN_INDEX
29293 + DO_SMC
29294 + ldmfd r13!, {r4-r12, r14}
29295 +skip_secure_l1_clean_op:
29296 + bl v7_flush_dcache_louis
29297 +
29298 + /*
29299 + * Clear the SCTLR.C bit to prevent further data cache
29300 + * allocation. Clearing SCTLR.C would make all the data accesses
29301 + * strongly ordered and would not hit the cache.
29302 + */
29303 + mrc p15, 0, r0, c1, c0, 0
29304 + bic r0, r0, #(1 << 2) @ Disable the C bit
29305 + mcr p15, 0, r0, c1, c0, 0
29306 + isb
29307 +
29308 + /* Clean and Invalidate L1 data cache. */
29309 + bl v7_flush_dcache_louis
29310 +
29311 + /*
29312 + * Take CPU out of Symmetric Multiprocessing (SMP) mode and thus
29313 + * preventing the CPU from receiving cache, TLB, or BTB
29314 + * maintenance operations broadcast by other CPUs in the cluster.
29315 + */
29316 + mrc p15, 0, r0, c1, c1, 2 @ Read NSACR data
29317 + tst r0, #(1 << 18)
29318 + mrcne p15, 0, r0, c1, c0, 1
29319 + bicne r0, r0, #(1 << 6) @ Disable SMP bit
29320 + mcrne p15, 0, r0, c1, c0, 1
29321 + isb
29322 + dsb
29323 +
29324 + bl omap4_get_sar_ram_base
29325 + mov r8, r0
29326 + mrc p15, 0, r5, c0, c0, 5 @ Read MPIDR
29327 + ands r5, r5, #0x0f
29328 + ldreq r0, [r8, #L2X0_SAVE_OFFSET0] @ Retrieve L2 state
29329 + ldrne r0, [r8, #L2X0_SAVE_OFFSET1]
29330 + cmp r0, #3
29331 + bne do_wfi
29332 + bl omap4_get_sar_ram_base
29333 + ldr r9, [r0, #OMAP_TYPE_OFFSET]
29334 + cmp r9, #0x1 @ Check for HS device
29335 + bne skip_secure_l2_clean_op
29336 + mov r0, #1 @ Clean secure L2
29337 + stmfd r13!, {r4-r12, r14}
29338 + ldr r12, =OMAP5_MON_CACHES_CLEAN_INDEX
29339 + DO_SMC
29340 + ldmfd r13!, {r4-r12, r14}
29341 +skip_secure_l2_clean_op:
29342 + mov r0, #2 @ Flush L2
29343 + bl v7_flush_dcache_all
29344 +
29345 +do_wfi:
29346 + bl omap_do_wfi
29347 +
29348 + /*
29349 + * CPU is here when it failed to enter OFF/DORMANT or
29350 + * no low power state was attempted.
29351 + */
29352 + mrc p15, 0, r0, c1, c0, 0
29353 + tst r0, #(1 << 2) @ Check C bit enabled?
29354 + orreq r0, r0, #(1 << 2) @ Enable the C bit
29355 + mcreq p15, 0, r0, c1, c0, 0
29356 + isb
29357 + mrc p15, 0, r0, c1, c0, 1
29358 + tst r0, #(1 << 6) @ Check SMP bit enabled?
29359 + orreq r0, r0, #(1 << 6)
29360 + mcreq p15, 0, r0, c1, c0, 1
29361 + isb
29362 + dsb
29363 + ldmfd sp!, {r4-r12, pc}
29364 +ENDPROC(omap5_finish_suspend)
29365 +
29366 +ENTRY(omap5_cpu_resume)
29367 +#ifdef CONFIG_ARM_ERRATA_761171
29368 + /*
29369 + * Work around for errata for 761171. Streaming write that will not
29370 + * allocate in L2 could lead to data corruption.
29371 + */
29372 + mrc p15, 0, r0, c0, c0, 0 @ read main ID register
29373 + and r5, r0, #0x00f00000 @ variant
29374 + and r6, r0, #0x0000000f @ revision
29375 + orr r6, r6, r5, lsr #20-4 @ combine variant and revision
29376 + cmp r6, #0x03 @ Present before r0p3
29377 + bgt 1f
29378 + mrc p15, 0, r0, c1, c0, 1 @ Read Auxctrl
29379 + orr r0, r0, #0x3 << 27 @ bits[28:27]-L1_mode3_threshold
29380 + ldr r12, =OMAP5_MON_AUX_CTRL_INDEX
29381 + dsb
29382 + smc #0
29383 + dsb
29384 +1:
29385 +#endif
29386 + mrc p15, 1, r0, c15, c0, 0 @ Read L2 ACTLR
29387 + cmp r0, #0x118 @ Check if it is already set
29388 + beq skip_sec_l2
29389 + ldr r0, =0x118 @ Setup L2 ACTLR = 0x118
29390 + ldr r12, =OMAP5_MON_L2AUX_CTRL_INDEX
29391 + dsb
29392 + smc #0
29393 + dsb
29394 +skip_sec_l2:
29395 + b cpu_resume @ Jump to generic resume
29396 +ENDPROC(omap5_cpu_resume)
29397 +#endif /* CONFIG_SOC_OMAP5 */
29398 +
29399 #endif /* defined(CONFIG_SMP) && defined(CONFIG_PM) */
29400
29401 #ifndef CONFIG_OMAP4_ERRATA_I688
29402 --- a/arch/arm/mach-omap2/sram.c
29403 +++ b/arch/arm/mach-omap2/sram.c
29404 @@ -154,7 +154,7 @@ static void __init omap2_map_sram(void)
29405 omap_sram_size -= SZ_16K;
29406 }
29407 #endif
29408 - if (cpu_is_omap34xx()) {
29409 + if (cpu_is_omap34xx() || soc_is_am33xx()) {
29410 /*
29411 * SRAM must be marked as non-cached on OMAP3 since the
29412 * CORE DPLL M2 divider change code (in SRAM) runs with the
29413 @@ -285,10 +285,18 @@ static inline int omap34xx_sram_init(voi
29414 }
29415 #endif /* CONFIG_ARCH_OMAP3 */
29416
29417 +#ifdef CONFIG_SOC_AM33XX
29418 static inline int am33xx_sram_init(void)
29419 {
29420 + am33xx_push_sram_idle();
29421 return 0;
29422 }
29423 +#else
29424 +static inline int am33xx_sram_init(void)
29425 +{
29426 + return 0;
29427 +}
29428 +#endif
29429
29430 int __init omap_sram_init(void)
29431 {
29432 --- a/arch/arm/mach-omap2/sram.h
29433 +++ b/arch/arm/mach-omap2/sram.h
29434 @@ -62,8 +62,10 @@ extern unsigned long omap3_sram_configur
29435
29436 #ifdef CONFIG_PM
29437 extern void omap_push_sram_idle(void);
29438 +extern void am33xx_push_sram_idle(void);
29439 #else
29440 static inline void omap_push_sram_idle(void) {}
29441 +static inline void am33xx_push_sram_idle(void) {}
29442 #endif /* CONFIG_PM */
29443
29444 #endif /* __ASSEMBLY__ */
29445 --- a/arch/arm/mach-omap2/timer.c
29446 +++ b/arch/arm/mach-omap2/timer.c
29447 @@ -55,6 +55,7 @@
29448 #include "soc.h"
29449 #include "common.h"
29450 #include "powerdomain.h"
29451 +#include "omap-secure.h"
29452
29453 #define REALTIME_COUNTER_BASE 0x48243200
29454 #define INCREMENTER_NUMERATOR_OFFSET 0x10
29455 @@ -65,6 +66,7 @@
29456
29457 static struct omap_dm_timer clkev;
29458 static struct clock_event_device clockevent_gpt;
29459 +unsigned long arch_timer_freq;
29460
29461 static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
29462 {
29463 @@ -118,6 +120,29 @@ static void omap2_gp_timer_set_mode(enum
29464 }
29465 }
29466
29467 +static void omap_clkevt_suspend(struct clock_event_device *unused)
29468 +{
29469 + struct omap_hwmod *oh;
29470 +
29471 + oh = omap_hwmod_lookup(clockevent_gpt.name);
29472 + if (!oh)
29473 + return;
29474 +
29475 + omap_hwmod_idle(oh);
29476 +}
29477 +
29478 +static void omap_clkevt_resume(struct clock_event_device *unused)
29479 +{
29480 + struct omap_hwmod *oh;
29481 +
29482 + oh = omap_hwmod_lookup(clockevent_gpt.name);
29483 + if (!oh)
29484 + return;
29485 +
29486 + omap_hwmod_enable(oh);
29487 + __omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW);
29488 +}
29489 +
29490 static struct clock_event_device clockevent_gpt = {
29491 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
29492 .rating = 300,
29493 @@ -276,8 +301,13 @@ static int __init omap_dm_timer_init_one
29494 if (!timer->io_base)
29495 return -ENXIO;
29496
29497 + omap_hwmod_setup_one(oh_name);
29498 +
29499 /* After the dmtimer is using hwmod these clocks won't be needed */
29500 - timer->fclk = clk_get(NULL, omap_hwmod_get_main_clk(oh));
29501 + if (oh->_clk)
29502 + timer->fclk = oh->_clk;
29503 + else
29504 + timer->fclk = clk_get(NULL, omap_hwmod_get_main_clk(oh));
29505 if (IS_ERR(timer->fclk))
29506 return PTR_ERR(timer->fclk);
29507
29508 @@ -297,7 +327,6 @@ static int __init omap_dm_timer_init_one
29509
29510 clk_put(src);
29511
29512 - omap_hwmod_setup_one(oh_name);
29513 omap_hwmod_enable(oh);
29514 __omap_dm_timer_init_regs(timer);
29515
29516 @@ -323,6 +352,11 @@ static void __init omap2_gp_clockevent_i
29517 clkev.id = gptimer_id;
29518 clkev.errata = omap_dm_timer_get_errata();
29519
29520 + if (soc_is_am33xx()) {
29521 + clockevent_gpt.suspend = omap_clkevt_suspend;
29522 + clockevent_gpt.resume = omap_clkevt_resume;
29523 + }
29524 +
29525 /*
29526 * For clock-event timers we never read the timer counter and
29527 * so we are not impacted by errata i103 and i767. Therefore,
29528 @@ -515,6 +549,10 @@ static void __init realtime_counter_init
29529 num = 8;
29530 den = 25;
29531 break;
29532 + case 20000000:
29533 + num = 192;
29534 + den = 625;
29535 + break;
29536 case 2600000:
29537 num = 384;
29538 den = 1625;
29539 @@ -542,6 +580,9 @@ static void __init realtime_counter_init
29540 reg |= den;
29541 __raw_writel(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET);
29542
29543 + arch_timer_freq = (rate / den) * num;
29544 + omap_smc1(OMAP5_DRA7_MON_SET_CNTFRQ_INDEX, arch_timer_freq);
29545 +
29546 iounmap(base);
29547 }
29548 #else
29549 --- a/arch/arm/mach-omap2/twl-common.c
29550 +++ b/arch/arm/mach-omap2/twl-common.c
29551 @@ -24,6 +24,7 @@
29552 #include <linux/i2c/twl.h>
29553 #include <linux/gpio.h>
29554 #include <linux/string.h>
29555 +#include <linux/phy/phy.h>
29556 #include <linux/regulator/machine.h>
29557 #include <linux/regulator/fixed.h>
29558
29559 @@ -90,8 +91,18 @@ void __init omap_pmic_late_init(void)
29560 }
29561
29562 #if defined(CONFIG_ARCH_OMAP3)
29563 +struct phy_consumer consumers[] = {
29564 + PHY_CONSUMER("musb-hdrc.0", "usb"),
29565 +};
29566 +
29567 +struct phy_init_data init_data = {
29568 + .consumers = consumers,
29569 + .num_consumers = ARRAY_SIZE(consumers),
29570 +};
29571 +
29572 static struct twl4030_usb_data omap3_usb_pdata = {
29573 .usb_mode = T2_USB_MODE_ULPI,
29574 + .init_data = &init_data,
29575 };
29576
29577 static int omap3_batt_table[] = {
29578 --- a/arch/arm/mach-omap2/usb.h
29579 +++ b/arch/arm/mach-omap2/usb.h
29580 @@ -58,7 +58,6 @@ struct usbhs_phy_data {
29581 int reset_gpio;
29582 int vcc_gpio;
29583 bool vcc_polarity; /* 1 active high, 0 active low */
29584 - void *platform_data;
29585 };
29586
29587 extern void usb_musb_init(struct omap_musb_board_data *board_data);
29588 --- a/arch/arm/mach-omap2/usb-host.c
29589 +++ b/arch/arm/mach-omap2/usb-host.c
29590 @@ -435,6 +435,7 @@ int usbhs_init_phys(struct usbhs_phy_dat
29591 struct platform_device *pdev;
29592 char *phy_id;
29593 struct platform_device_info pdevinfo;
29594 + struct usb_phy_gen_xceiv_platform_data nop_pdata;
29595
29596 for (i = 0; i < num_phys; i++) {
29597
29598 @@ -455,11 +456,18 @@ int usbhs_init_phys(struct usbhs_phy_dat
29599 return -ENOMEM;
29600 }
29601
29602 + /* set platform data */
29603 + memset(&nop_pdata, 0, sizeof(nop_pdata));
29604 + if (gpio_is_valid(phy->vcc_gpio))
29605 + nop_pdata.needs_vcc = true;
29606 + nop_pdata.gpio_reset = phy->reset_gpio;
29607 + nop_pdata.type = USB_PHY_TYPE_USB2;
29608 +
29609 /* create a NOP PHY device */
29610 memset(&pdevinfo, 0, sizeof(pdevinfo));
29611 pdevinfo.name = nop_name;
29612 pdevinfo.id = phy->port;
29613 - pdevinfo.data = phy->platform_data;
29614 + pdevinfo.data = &nop_pdata;
29615 pdevinfo.size_data =
29616 sizeof(struct usb_phy_gen_xceiv_platform_data);
29617 scnprintf(phy_id, MAX_STR, "usb_phy_gen_xceiv.%d",
29618 @@ -474,14 +482,6 @@ int usbhs_init_phys(struct usbhs_phy_dat
29619
29620 usb_bind_phy("ehci-omap.0", phy->port - 1, phy_id);
29621
29622 - /* Do we need RESET regulator ? */
29623 - if (gpio_is_valid(phy->reset_gpio)) {
29624 - scnprintf(rail_name, MAX_STR,
29625 - "hsusb%d_reset", phy->port);
29626 - usbhs_add_regulator(rail_name, phy_id, "reset",
29627 - phy->reset_gpio, 1);
29628 - }
29629 -
29630 /* Do we need VCC regulator ? */
29631 if (gpio_is_valid(phy->vcc_gpio)) {
29632 scnprintf(rail_name, MAX_STR, "hsusb%d_vcc", phy->port);
29633 --- a/arch/arm/mach-omap2/wd_timer.c
29634 +++ b/arch/arm/mach-omap2/wd_timer.c
29635 @@ -123,6 +123,11 @@ static int __init omap_init_wdt(void)
29636
29637 pdata.read_reset_sources = prm_read_reset_sources;
29638
29639 + if (cpu_is_omap44xx() || soc_is_omap54xx())
29640 + pdata.ip_rev = WDTIMER2_IP4;
29641 + else
29642 + pdata.ip_rev = WDTIMER2_IP3;
29643 +
29644 pdev = omap_device_build(dev_name, id, oh, &pdata,
29645 sizeof(struct omap_wd_timer_platform_data));
29646 WARN(IS_ERR(pdev), "Can't build omap_device for %s:%s.\n",
29647 --- /dev/null
29648 +++ b/arch/arm/mach-omap2/wkup_m3.c
29649 @@ -0,0 +1,410 @@
29650 +/*
29651 +* AM33XX Power Management Routines
29652 + *
29653 + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
29654 + * Vaibhav Bedia <vaibhav.bedia@ti.com>
29655 + *
29656 + * This program is free software; you can redistribute it and/or
29657 + * modify it under the terms of the GNU General Public License as
29658 + * published by the Free Software Foundation version 2.
29659 + *
29660 + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
29661 + * kind, whether express or implied; without even the implied warranty
29662 + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
29663 + * GNU General Public License for more details.
29664 + */
29665 +
29666 +#include <linux/kernel.h>
29667 +#include <linux/init.h>
29668 +#include <linux/slab.h>
29669 +#include <linux/cpu.h>
29670 +#include <linux/err.h>
29671 +#include <linux/firmware.h>
29672 +#include <linux/io.h>
29673 +#include <linux/platform_device.h>
29674 +#include <linux/pm_runtime.h>
29675 +#include <linux/module.h>
29676 +#include <linux/interrupt.h>
29677 +#include <linux/of.h>
29678 +#include <linux/omap-mailbox.h>
29679 +
29680 +#include "pm33xx.h"
29681 +#include "omap_device.h"
29682 +
29683 +#define WKUP_M3_WAKE_SRC_MASK 0xFF
29684 +
29685 +#define WKUP_M3_STATUS_RESP_SHIFT 16
29686 +#define WKUP_M3_STATUS_RESP_MASK (0xffff << 16)
29687 +
29688 +#define WKUP_M3_FW_VERSION_SHIFT 0
29689 +#define WKUP_M3_FW_VERSION_MASK 0xffff
29690 +
29691 +/* AM33XX M3_TXEV_EOI register */
29692 +#define AM33XX_CONTROL_M3_TXEV_EOI 0x00
29693 +
29694 +#define AM33XX_M3_TXEV_ACK (0x1 << 0)
29695 +#define AM33XX_M3_TXEV_ENABLE (0x0 << 0)
29696 +
29697 +/* AM33XX IPC message registers */
29698 +#define AM33XX_CONTROL_IPC_MSG_REG0 0x04
29699 +#define AM33XX_CONTROL_IPC_MSG_REG1 0x08
29700 +#define AM33XX_CONTROL_IPC_MSG_REG2 0x0c
29701 +#define AM33XX_CONTROL_IPC_MSG_REG3 0x10
29702 +#define AM33XX_CONTROL_IPC_MSG_REG4 0x14
29703 +#define AM33XX_CONTROL_IPC_MSG_REG5 0x18
29704 +#define AM33XX_CONTROL_IPC_MSG_REG6 0x1c
29705 +#define AM33XX_CONTROL_IPC_MSG_REG7 0x20
29706 +
29707 +struct wkup_m3_context {
29708 + struct device *dev;
29709 + void __iomem *code;
29710 + void __iomem *ipc;
29711 + u8 is_valid;
29712 + struct wkup_m3_ops *ops;
29713 + struct omap_mbox *mbox;
29714 +};
29715 +
29716 +struct wkup_m3_wakeup_src wakeups[] = {
29717 + {.irq_nr = 35, .src = "USB0_PHY"},
29718 + {.irq_nr = 36, .src = "USB1_PHY"},
29719 + {.irq_nr = 40, .src = "I2C0"},
29720 + {.irq_nr = 41, .src = "RTC Timer"},
29721 + {.irq_nr = 42, .src = "RTC Alarm"},
29722 + {.irq_nr = 43, .src = "Timer0"},
29723 + {.irq_nr = 44, .src = "Timer1"},
29724 + {.irq_nr = 45, .src = "UART"},
29725 + {.irq_nr = 46, .src = "GPIO0"},
29726 + {.irq_nr = 48, .src = "MPU_WAKE"},
29727 + {.irq_nr = 49, .src = "WDT0"},
29728 + {.irq_nr = 50, .src = "WDT1"},
29729 + {.irq_nr = 51, .src = "ADC_TSC"},
29730 + {.irq_nr = 0, .src = "Unknown"},
29731 +};
29732 +
29733 +static struct wkup_m3_context *wkup_m3;
29734 +
29735 +static void am33xx_txev_eoi(void)
29736 +{
29737 + writel(AM33XX_M3_TXEV_ACK,
29738 + wkup_m3->ipc + AM33XX_CONTROL_M3_TXEV_EOI);
29739 +}
29740 +
29741 +static void am33xx_txev_enable(void)
29742 +{
29743 + writel(AM33XX_M3_TXEV_ENABLE,
29744 + wkup_m3->ipc + AM33XX_CONTROL_M3_TXEV_EOI);
29745 +}
29746 +
29747 +static void am33xx_ctrl_ipc_write(struct am33xx_ipc_regs *ipc_regs)
29748 +{
29749 + writel(ipc_regs->reg0,
29750 + wkup_m3->ipc + AM33XX_CONTROL_IPC_MSG_REG0);
29751 + writel(ipc_regs->reg1,
29752 + wkup_m3->ipc + AM33XX_CONTROL_IPC_MSG_REG1);
29753 + writel(ipc_regs->reg2,
29754 + wkup_m3->ipc + AM33XX_CONTROL_IPC_MSG_REG2);
29755 + writel(ipc_regs->reg3,
29756 + wkup_m3->ipc + AM33XX_CONTROL_IPC_MSG_REG3);
29757 + writel(ipc_regs->reg4,
29758 + wkup_m3->ipc + AM33XX_CONTROL_IPC_MSG_REG4);
29759 + writel(ipc_regs->reg5,
29760 + wkup_m3->ipc + AM33XX_CONTROL_IPC_MSG_REG5);
29761 + writel(ipc_regs->reg6,
29762 + wkup_m3->ipc + AM33XX_CONTROL_IPC_MSG_REG6);
29763 + writel(ipc_regs->reg7,
29764 + wkup_m3->ipc + AM33XX_CONTROL_IPC_MSG_REG7);
29765 +}
29766 +
29767 +static void am33xx_ctrl_ipc_read(struct am33xx_ipc_regs *ipc_regs)
29768 +{
29769 + ipc_regs->reg0 = readl(wkup_m3->ipc
29770 + + AM33XX_CONTROL_IPC_MSG_REG0);
29771 + ipc_regs->reg1 = readl(wkup_m3->ipc
29772 + + AM33XX_CONTROL_IPC_MSG_REG1);
29773 + ipc_regs->reg2 = readl(wkup_m3->ipc
29774 + + AM33XX_CONTROL_IPC_MSG_REG2);
29775 + ipc_regs->reg3 = readl(wkup_m3->ipc
29776 + + AM33XX_CONTROL_IPC_MSG_REG3);
29777 + ipc_regs->reg4 = readl(wkup_m3->ipc
29778 + + AM33XX_CONTROL_IPC_MSG_REG4);
29779 + ipc_regs->reg5 = readl(wkup_m3->ipc
29780 + + AM33XX_CONTROL_IPC_MSG_REG5);
29781 + ipc_regs->reg6 = readl(wkup_m3->ipc
29782 + + AM33XX_CONTROL_IPC_MSG_REG6);
29783 + ipc_regs->reg7 = readl(wkup_m3->ipc
29784 + + AM33XX_CONTROL_IPC_MSG_REG7);
29785 +}
29786 +
29787 +int wkup_m3_is_valid()
29788 +{
29789 + return wkup_m3->is_valid;
29790 +}
29791 +
29792 +int wkup_m3_ping(void)
29793 +{
29794 + int ret = 0;
29795 +
29796 + if (!wkup_m3->mbox) {
29797 + pr_err("PM: No IPC channel to communicate with wkup_m3!\n");
29798 + return -EIO;
29799 + }
29800 +
29801 + /*
29802 + * Write a dummy message to the mailbox in order to trigger the RX
29803 + * interrupt to alert the M3 that data is available in the IPC
29804 + * registers.
29805 + */
29806 + ret = omap_mbox_msg_send(wkup_m3->mbox, 0xABCDABCD);
29807 +
29808 + return ret;
29809 +}
29810 +
29811 +struct wkup_m3_wakeup_src wkup_m3_wake_src(void)
29812 +{
29813 + struct am33xx_ipc_regs ipc_regs;
29814 + unsigned int wakeup_src_idx;
29815 + int j;
29816 +
29817 + am33xx_ctrl_ipc_read(&ipc_regs);
29818 +
29819 + wakeup_src_idx = ipc_regs.reg6 & WKUP_M3_WAKE_SRC_MASK;
29820 +
29821 + for (j = 0; j < ARRAY_SIZE(wakeups)-1; j++) {
29822 + if (wakeups[j].irq_nr == wakeup_src_idx)
29823 + return wakeups[j];
29824 + }
29825 +
29826 + return wakeups[j];
29827 +}
29828 +
29829 +
29830 +int wkup_m3_pm_status(void)
29831 +{
29832 + unsigned int i;
29833 + struct am33xx_ipc_regs ipc_regs;
29834 +
29835 + am33xx_ctrl_ipc_read(&ipc_regs);
29836 +
29837 + i = WKUP_M3_STATUS_RESP_MASK & ipc_regs.reg1;
29838 + i >>= __ffs(WKUP_M3_STATUS_RESP_MASK);
29839 +
29840 + return i;
29841 +}
29842 +
29843 +/*
29844 + * Invalidate M3 firmware version before hardreset.
29845 + * Write invalid version in lower 4 nibbles of parameter
29846 + * register (ipc_regs + 0x8).
29847 + */
29848 +
29849 +static void wkup_m3_fw_version_clear(void)
29850 +{
29851 + struct am33xx_ipc_regs ipc_regs;
29852 +
29853 + am33xx_ctrl_ipc_read(&ipc_regs);
29854 + ipc_regs.reg2 = 0xFFFF0000;
29855 + am33xx_ctrl_ipc_write(&ipc_regs);
29856 +
29857 + return;
29858 +}
29859 +
29860 +int wkup_m3_fw_version_read(void)
29861 +{
29862 + struct am33xx_ipc_regs ipc_regs;
29863 +
29864 + am33xx_ctrl_ipc_read(&ipc_regs);
29865 +
29866 + return ipc_regs.reg2 & WKUP_M3_FW_VERSION_MASK;
29867 +}
29868 +
29869 +void wkup_m3_pm_set_cmd(struct am33xx_ipc_regs *ipc_regs)
29870 +{
29871 + am33xx_ctrl_ipc_write(ipc_regs);
29872 +}
29873 +
29874 +void wkup_m3_set_ops(struct wkup_m3_ops *ops)
29875 +{
29876 + wkup_m3->ops = ops;
29877 +}
29878 +
29879 +static irqreturn_t wkup_m3_txev_handler(int irq, void *unused)
29880 +{
29881 + am33xx_txev_eoi();
29882 +
29883 + if (wkup_m3->ops && wkup_m3->ops->firmware_loaded)
29884 + wkup_m3->ops->txev_handler();
29885 +
29886 + am33xx_txev_enable();
29887 +
29888 + return IRQ_HANDLED;
29889 +}
29890 +
29891 +int wkup_m3_prepare(void)
29892 +{
29893 + int ret = 0;
29894 + struct platform_device *pdev = to_platform_device(wkup_m3->dev);
29895 +
29896 + wkup_m3->mbox = omap_mbox_get("wkup_m3", NULL);
29897 +
29898 + if (IS_ERR(wkup_m3->mbox)) {
29899 + ret = -EBUSY;
29900 + pr_err("PM: IPC Request for A8->M3 Channel failed!\n");
29901 + return ret;
29902 + }
29903 +
29904 + wkup_m3_fw_version_clear();
29905 +
29906 + /* check that the code is loaded */
29907 + ret = omap_device_deassert_hardreset(pdev, "wkup_m3");
29908 +
29909 + return ret;
29910 +}
29911 +
29912 +static int wkup_m3_copy_code(const u8 *data, size_t size)
29913 +{
29914 + if (size > SZ_16K)
29915 + return -ENOMEM;
29916 +
29917 + memcpy_toio(wkup_m3->code, data, size);
29918 +
29919 + return 0;
29920 +}
29921 +
29922 +static void wkup_m3_firmware_cb(const struct firmware *fw, void *context)
29923 +{
29924 + int ret = 0;
29925 +
29926 + /* no firmware found */
29927 + if (!fw) {
29928 + pr_err("PM: request_firmware failed\n");
29929 + return;
29930 + }
29931 +
29932 + ret = wkup_m3_copy_code(fw->data, fw->size);
29933 +
29934 + if (ret) {
29935 + pr_info("PM: Failed to copy firmware for M3");
29936 + } else {
29937 + if (wkup_m3->ops && wkup_m3->ops->firmware_loaded)
29938 + wkup_m3->ops->firmware_loaded();
29939 +
29940 + wkup_m3->is_valid = true;
29941 + }
29942 +
29943 + return;
29944 +}
29945 +
29946 +static int wkup_m3_probe(struct platform_device *pdev)
29947 +{
29948 + int irq, ret = 0;
29949 + struct resource *res;
29950 +
29951 + pm_runtime_enable(&pdev->dev);
29952 +
29953 + ret = pm_runtime_get_sync(&pdev->dev);
29954 + if (IS_ERR_VALUE(ret)) {
29955 + dev_err(&pdev->dev, "pm_runtime_get_sync() failed\n");
29956 + return ret;
29957 + }
29958 +
29959 + irq = platform_get_irq(pdev, 0);
29960 + if (!irq) {
29961 + dev_err(&pdev->dev, "no irq resource\n");
29962 + ret = -ENXIO;
29963 + goto err;
29964 + }
29965 +
29966 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "m3_umem");
29967 + if (!res) {
29968 + dev_err(&pdev->dev, "no memory resource\n");
29969 + ret = -ENXIO;
29970 + goto err;
29971 + }
29972 +
29973 + wkup_m3 = devm_kzalloc(&pdev->dev, sizeof(*wkup_m3), GFP_KERNEL);
29974 + if (!wkup_m3) {
29975 + pr_err("Memory allocation failed\n");
29976 + ret = -ENOMEM;
29977 + goto err;
29978 + }
29979 +
29980 + wkup_m3->dev = &pdev->dev;
29981 +
29982 + wkup_m3->code = devm_request_and_ioremap(wkup_m3->dev, res);
29983 + if (!wkup_m3->code) {
29984 + dev_err(wkup_m3->dev, "could not ioremap\n");
29985 + ret = -EADDRNOTAVAIL;
29986 + goto err;
29987 + }
29988 +
29989 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ipc_regs");
29990 + if (!res) {
29991 + dev_err(&pdev->dev, "no memory resource for ipc\n");
29992 + ret = -ENXIO;
29993 + goto err;
29994 + }
29995 +
29996 + wkup_m3->ipc = devm_request_and_ioremap(wkup_m3->dev, res);
29997 + if (!wkup_m3->ipc) {
29998 + dev_err(wkup_m3->dev, "could not ioremap ipc_mem\n");
29999 + ret = -EADDRNOTAVAIL;
30000 + goto err;
30001 + }
30002 +
30003 + ret = devm_request_irq(wkup_m3->dev, irq, wkup_m3_txev_handler,
30004 + IRQF_DISABLED, "wkup_m3_txev", NULL);
30005 + if (ret) {
30006 + dev_err(wkup_m3->dev, "request_irq failed\n");
30007 + goto err;
30008 + }
30009 +
30010 + wkup_m3->is_valid = false;
30011 +
30012 + pr_info("PM: Loading am335x-pm-firmware.bin");
30013 +
30014 + /* We don't want to delay boot */
30015 + ret = request_firmware_nowait(THIS_MODULE, 0, "am335x-pm-firmware.bin",
30016 + &pdev->dev, GFP_KERNEL, NULL,
30017 + wkup_m3_firmware_cb);
30018 +
30019 +err:
30020 + return ret;
30021 +}
30022 +
30023 +static int wkup_m3_remove(struct platform_device *pdev)
30024 +{
30025 + return 0;
30026 +}
30027 +
30028 +static struct of_device_id wkup_m3_dt_ids[] = {
30029 + { .compatible = "ti,am3353-wkup-m3" },
30030 + { }
30031 +};
30032 +MODULE_DEVICE_TABLE(of, wkup_m3_dt_ids);
30033 +
30034 +static int wkup_m3_rpm_suspend(struct device *dev)
30035 +{
30036 + return -EBUSY;
30037 +}
30038 +
30039 +static int wkup_m3_rpm_resume(struct device *dev)
30040 +{
30041 + return 0;
30042 +}
30043 +
30044 +static const struct dev_pm_ops wkup_m3_ops = {
30045 + SET_RUNTIME_PM_OPS(wkup_m3_rpm_suspend, wkup_m3_rpm_resume, NULL)
30046 +};
30047 +
30048 +static struct platform_driver wkup_m3_driver = {
30049 + .probe = wkup_m3_probe,
30050 + .remove = wkup_m3_remove,
30051 + .driver = {
30052 + .name = "wkup_m3",
30053 + .owner = THIS_MODULE,
30054 + .of_match_table = of_match_ptr(wkup_m3_dt_ids),
30055 + .pm = &wkup_m3_ops,
30056 + },
30057 +};
30058 +
30059 +module_platform_driver(wkup_m3_driver);
30060 --- /dev/null
30061 +++ b/arch/arm/mach-omap2/wkup_m3.h
30062 @@ -0,0 +1,60 @@
30063 +/*
30064 + * TI Wakeup M3 Power Management Routines
30065 + *
30066 + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
30067 + * Dave Gerlach <d-gerlach@ti.com>
30068 + *
30069 + * This program is free software; you can redistribute it and/or
30070 + * modify it under the terms of the GNU General Public License as
30071 + * published by the Free Software Foundation version 2.
30072 + *
30073 + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
30074 + * kind, whether express or implied; without even the implied warranty
30075 + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
30076 + * GNU General Public License for more details.
30077 + */
30078 +
30079 +#ifndef __ASSEMBLER__
30080 +
30081 +/**
30082 + * struct wkup_m3_ops - Callbacks for allowing pm code to interact with wkup_m3.
30083 + *
30084 + * @txev_handler: Callback to allow pm code to react to response from wkup_m3
30085 + * after pinging it using wkup_m3_ping.
30086 + *
30087 + * @firmware_loaded: Callback invoked when the firmware has been loaded to the
30088 + * m3 to allow the pm code to enable suspend/resume ops.
30089 + */
30090 +
30091 +struct wkup_m3_ops {
30092 + void (*txev_handler)(void);
30093 + void (*firmware_loaded)(void);
30094 +};
30095 +
30096 +struct wkup_m3_wakeup_src {
30097 + int irq_nr;
30098 + char src[10];
30099 +};
30100 +
30101 +struct am33xx_ipc_regs {
30102 + u32 reg0;
30103 + u32 reg1;
30104 + u32 reg2;
30105 + u32 reg3;
30106 + u32 reg4;
30107 + u32 reg5;
30108 + u32 reg6;
30109 + u32 reg7;
30110 +};
30111 +
30112 +int wkup_m3_prepare(void);
30113 +void wkup_m3_set_ops(struct wkup_m3_ops *ops);
30114 +int wkup_m3_ping(void);
30115 +struct wkup_m3_wakeup_src wkup_m3_wake_src(void);
30116 +int wkup_m3_pm_status(void);
30117 +int wkup_m3_is_valid(void);
30118 +int wkup_m3_fw_version_read(void);
30119 +void wkup_m3_pm_set_cmd(struct am33xx_ipc_regs *ipc_regs);
30120 +
30121 +#endif
30122 +
30123 --- a/arch/arm/Makefile
30124 +++ b/arch/arm/Makefile
30125 @@ -314,6 +314,8 @@ $(INSTALL_TARGETS):
30126
30127 %.dtb: | scripts
30128 $(Q)$(MAKE) $(build)=$(boot)/dts MACHINE=$(MACHINE) $(boot)/dts/$@
30129 +uImage.%: uImage
30130 + $(Q)$(MAKE) $(build)=$(boot) MACHINE=$(MACHINE) $(boot)/$@
30131
30132 PHONY += dtbs
30133 dtbs: scripts
30134 --- a/arch/arm/plat-omap/include/plat/dmtimer.h
30135 +++ b/arch/arm/plat-omap/include/plat/dmtimer.h
30136 @@ -336,8 +336,11 @@ static inline void __omap_dm_timer_enabl
30137 if (timer->posted)
30138 return;
30139
30140 - if (timer->errata & OMAP_TIMER_ERRATA_I103_I767)
30141 + if (timer->errata & OMAP_TIMER_ERRATA_I103_I767) {
30142 + timer->posted = OMAP_TIMER_NONPOSTED;
30143 + __omap_dm_timer_write(timer, OMAP_TIMER_IF_CTRL_REG, 0, 0);
30144 return;
30145 + }
30146
30147 __omap_dm_timer_write(timer, OMAP_TIMER_IF_CTRL_REG,
30148 OMAP_TIMER_CTRL_POSTED, 0);
30149 --- /dev/null
30150 +++ b/Documentation/ABI/testing/configfs-usb-gadget-mass-storage
30151 @@ -0,0 +1,31 @@
30152 +What: /config/usb-gadget/gadget/functions/mass_storage.name
30153 +Date: Oct 2013
30154 +KenelVersion: 3.13
30155 +Description:
30156 + The attributes:
30157 +
30158 + stall - Set to permit function to halt bulk endpoints.
30159 + Disabled on some USB devices known not to work
30160 + correctly. You should set it to true.
30161 + num_buffers - Number of pipeline buffers. Valid numbers
30162 + are 2..4. Available only if
30163 + CONFIG_USB_GADGET_DEBUG_FILES is set.
30164 +
30165 +What: /config/usb-gadget/gadget/functions/mass_storage.name/lun.name
30166 +Date: Oct 2013
30167 +KenelVersion: 3.13
30168 +Description:
30169 + The attributes:
30170 +
30171 + file - The path to the backing file for the LUN.
30172 + Required if LUN is not marked as removable.
30173 + ro - Flag specifying access to the LUN shall be
30174 + read-only. This is implied if CD-ROM emulation
30175 + is enabled as well as when it was impossible
30176 + to open "filename" in R/W mode.
30177 + removable - Flag specifying that LUN shall be indicated as
30178 + being removable.
30179 + cdrom - Flag specifying that LUN shall be reported as
30180 + being a CD-ROM.
30181 + nofua - Flag specifying that FUA flag
30182 + in SCSI WRITE(10,12)
30183 --- /dev/null
30184 +++ b/Documentation/devicetree/bindings/arm/omap/crossbar.txt
30185 @@ -0,0 +1,24 @@
30186 +* TI - IRQ/DMA Crossbar
30187 +
30188 +This version is an implementation of the Crossbar IRQ/DMA IP
30189 +
30190 +Required properties:
30191 +- compatible : Should be "ti,dra-crossbar"
30192 +- crossbar-name: Name of the controller to which crossbar output is routed
30193 +- reg: Contains crossbar register address range
30194 +- reg-width: Represents the width of the individual registers
30195 +- crossbar-lines: Default mappings.Should contain the crossbar-name
30196 + device name, int/dma request number, crossbar number,
30197 + register offset in the same order.
30198 +
30199 +Examples:
30200 + crossbar_mpu: mpuirq@4a002a48 {
30201 + compatible = "crossbar";
30202 + crossbar-name = "mpu-irq";
30203 + reg = <0x4a002a48 0x0130>;
30204 + reg-width = <16>;
30205 + crossbar-lines = "mpu-irq", "rtc-ss-alarm", <0x9f 0xd9 0x12c>,
30206 + "mpu-irq", "mcasp3-arevt", <0x9e 0x96 0x12a>,
30207 + "mpu-irq", "mcasp3-axevt", <0x9d 0x97 0x128>;
30208 + };
30209 +
30210 --- /dev/null
30211 +++ b/Documentation/devicetree/bindings/arm/omap/dmm.txt
30212 @@ -0,0 +1,17 @@
30213 +OMAP Dynamic Memory Manager (DMM) bindings
30214 +
30215 +Required properties:
30216 +- compatible: Must be "ti,omap4-dmm" for OMAP4 family
30217 + Must be "ti,omap5-dmm" for OMAP5 family
30218 +- reg: Contains timer register address range (base address and length)
30219 +- interrupts: Contains interrupt information (source, etc) for the DMM IRQ
30220 +- ti,hwmods: Name of the hwmod associated to the counter, which is typically
30221 + "dmm"
30222 +
30223 +Example:
30224 +
30225 +dmm: dmm@4e000000 {
30226 + compatible = "ti,omap4-dmm";
30227 + reg = <0x4e000000 0x800>;
30228 + ti,hwmods = "dmm";
30229 +};
30230 --- a/Documentation/devicetree/bindings/arm/omap/omap.txt
30231 +++ b/Documentation/devicetree/bindings/arm/omap/omap.txt
30232 @@ -21,7 +21,8 @@ Required properties:
30233 Optional properties:
30234 - ti,no_idle_on_suspend: When present, it prevents the PM to idle the module
30235 during suspend.
30236 -
30237 +- ti,no-reset: When present, the module should not be reset
30238 +- ti,no-idle: When present, the module should not be idled
30239
30240 Example:
30241
30242 @@ -60,5 +61,8 @@ Boards:
30243 - AM43x EPOS EVM
30244 compatible = "ti,am43x-epos-evm", "ti,am4372", "ti,am43"
30245
30246 +- AM437x GP EVM
30247 + compatible = "ti,am437x-gp-evm", "ti,am4372", "ti,am43"
30248 +
30249 - DRA7 EVM: Software Developement Board for DRA7XX
30250 compatible = "ti,dra7-evm", "ti,dra7"
30251 --- /dev/null
30252 +++ b/Documentation/devicetree/bindings/arm/omap/prcm.txt
30253 @@ -0,0 +1,13 @@
30254 +TI Power Reset Clock Manager (PRCM)
30255 +
30256 +Properties:
30257 +- compatible: "ti,am4372-prcm" for prcm in am43x SoC's
30258 + "ti,am3352-prcm" for prcm in am335x SoC's
30259 +- #reset-cells: 1 (refer generic reset bindings for details)
30260 +
30261 +example:
30262 + prcm: prcm@44df0000 {
30263 + compatible = "ti,am4372-prcm";
30264 + reg = <0x44df0000 0xa000>;
30265 + #reset-cells = <1>;
30266 + };
30267 --- a/Documentation/devicetree/bindings/ata/ahci-platform.txt
30268 +++ b/Documentation/devicetree/bindings/ata/ahci-platform.txt
30269 @@ -4,7 +4,8 @@ SATA nodes are defined to describe on-ch
30270 Each SATA controller should have its own node.
30271
30272 Required properties:
30273 -- compatible : compatible list, contains "snps,spear-ahci"
30274 +- compatible : compatible list, contains "snps,spear-ahci",
30275 + snps,exynos5440-ahci or "snps,dwc-ahci"
30276 - interrupts : <interrupt mapping for SATA IRQ>
30277 - reg : <registers mapping>
30278
30279 --- /dev/null
30280 +++ b/Documentation/devicetree/bindings/ata/ti-sata.txt
30281 @@ -0,0 +1,31 @@
30282 +* Texas Instruments SATA Controller Wrapper
30283 +
30284 +Required properties:
30285 +- compatible : "ti,sata"
30286 +- ti,hwmods : "sata"
30287 +- reg : Register mapping
30288 +- #address-cells: <1>
30289 +- #size-cells : <1>
30290 +- ranges : allows valid translation between child's address space and parent's
30291 + address space.
30292 +- Must contain at least one child node for the SATA controller core
30293 +
30294 +Example:
30295 +
30296 + sata: sata@4a141100 {
30297 + compatible = "ti,sata";
30298 + ti,hwmods = "sata";
30299 + reg = <0x4a141100 0x7>;
30300 + #address-cells = <1>;
30301 + #size-cells = <1>;
30302 + ranges;
30303 + dwc-ahci@4a140000 {
30304 + compatible = "snps,dwc-ahci";
30305 + reg = <0x4a140000 0x1100>;
30306 + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
30307 + phys = <&sata_phy>;
30308 + phy-names = "sata-phy";
30309 + clocks = <&sata_ref_clk>;
30310 + clock-names = "optclk";
30311 + };
30312 + };
30313 --- /dev/null
30314 +++ b/Documentation/devicetree/bindings/clock/clk-palmas.txt
30315 @@ -0,0 +1,35 @@
30316 +* Palmas 32KHz clocks *
30317 +
30318 +Palmas device has two clock output pins for 32KHz, KG and KG_AUDIO.
30319 +
30320 +This binding uses the common clock binding ./clock-bindings.txt.
30321 +
30322 +Required properties:
30323 +- compatible : "ti,palmas-clk32kg" for clk32kg clock
30324 + "ti,palmas-clk32kgaudio" for clk32kgaudio clock
30325 +- #clock-cells : shall be set to 0.
30326 +
30327 +Optional property:
30328 +- ti,external-sleep-control: The external enable input pins controlled the
30329 + enable/disable of clocks. The external enable input pins ENABLE1,
30330 + ENABLE2 and NSLEEP. The valid values for the external pins are:
30331 + PALMAS_EXT_CONTROL_PIN_ENABLE1 for ENABLE1 pin
30332 + PALMAS_EXT_CONTROL_PIN_ENABLE2 for ENABLE2 pin
30333 + PALMAS_EXT_CONTROL_PIN_NSLEEP for NSLEEP pin
30334 + Option 0 or missing this property means the clock is enabled/disabled
30335 + via register access and these pins do not have any control.
30336 + The macros of external control pins for DTS is defined at
30337 + dt-bindings/mfd/palmas.h
30338 +
30339 +Example:
30340 + #include <dt-bindings/mfd/palmas.h>
30341 + ...
30342 + palmas: tps65913@58 {
30343 + ...
30344 + clk32kg: palmas_clk32k@0 {
30345 + compatible = "ti,palmas-clk32kg";
30346 + #clock-cells = <0>;
30347 + ti,external-sleep-control = <PALMAS_EXT_CONTROL_PIN_NSLEEP>;
30348 + };
30349 + ...
30350 + };
30351 --- /dev/null
30352 +++ b/Documentation/devicetree/bindings/clock/divider-clock.txt
30353 @@ -0,0 +1,90 @@
30354 +Binding for simple divider clock.
30355 +
30356 +This binding uses the common clock binding[1]. It assumes a
30357 +register-mapped adjustable clock rate divider that does not gate and has
30358 +only one input clock or parent. By default the value programmed into
30359 +the register is one less than the actual divisor value. E.g:
30360 +
30361 +register value actual divisor value
30362 +0 1
30363 +1 2
30364 +2 3
30365 +
30366 +This assumption may be modified by the following optional properties:
30367 +
30368 +index-starts-at-one - valid divisor values start at 1, not the default
30369 +of 0. E.g:
30370 +register value actual divisor value
30371 +1 1
30372 +2 2
30373 +3 3
30374 +
30375 +index-power-of-two - valid divisor values are powers of two. E.g:
30376 +register value actual divisor value
30377 +0 1
30378 +1 2
30379 +2 4
30380 +
30381 +index-allow-zero - same as index_one, but zero is divide-by-1. E.g:
30382 +register value actual divisor value
30383 +0 1
30384 +1 1
30385 +2 2
30386 +
30387 +Additionally a table of valid dividers may be supplied like so:
30388 +
30389 + table = <4 0>, <8, 1>;
30390 +
30391 +where the first value in the pair is the divider and the second value is
30392 +the programmed register bitfield.
30393 +
30394 +The binding must also provide the register to control the divider and
30395 +the mask for the corresponding control bits. Optionally the number of
30396 +bits to shift that mask, if necessary. If the shift value is missing it
30397 +is the same as supplying a zero shift.
30398 +
30399 +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
30400 +
30401 +Required properties:
30402 +- compatible : shall be "divider-clock".
30403 +- #clock-cells : from common clock binding; shall be set to 0.
30404 +- clocks : link to phandle of parent clock
30405 +- reg : base address for register controlling adjustable divider
30406 +- bit-mask : arbitrary bitmask for programming the adjustable divider
30407 +
30408 +Optional properties:
30409 +- clock-output-names : from common clock binding.
30410 +- table : array of integer pairs defining divisors & bitfield values
30411 +- bit-shift : number of bits to shift the bit-mask, defaults to
30412 + (ffs(mask) - 1) if not present
30413 +- minimum-divider : min divisor for dividing the input clock rate, only
30414 + needed if the first divisor is offset from the default value
30415 +- maximum-divider : max divisor for dividing the input clock rate, only
30416 + needed if the max divisor is less than (mask + 1).
30417 +- index-starts-at-one : valid divisor programming starts at 1, not zero
30418 +- index-power-of-two : valid divisor programming must be a power of two
30419 +- index-allow-zero : implies index-one, and programming zero results in
30420 + divide-by-one
30421 +- hiword-mask : lower half of the register programs the divider, upper
30422 + half of the register indicates bits that were updated in the lower
30423 + half
30424 +
30425 +Examples:
30426 + clock_foo: clock_foo@4a008100 {
30427 + compatible = "divider-clock";
30428 + #clock-cells = <0>;
30429 + clocks = <&clock_baz>;
30430 + reg = <0x4a008100 0x4>
30431 + mask = <0x3>
30432 + maximum-divider = <3>
30433 + };
30434 +
30435 + clock_bar: clock_bar@4a008108 {
30436 + #clock-cells = <0>;
30437 + compatible = "divider-clock";
30438 + clocks = <&clock_foo>;
30439 + reg = <0x4a008108 0x4>;
30440 + mask = <0x1>;
30441 + shift = <0>;
30442 + table = < 4 0 >, < 8 1 >;
30443 + };
30444 --- /dev/null
30445 +++ b/Documentation/devicetree/bindings/clock/gate-clock.txt
30446 @@ -0,0 +1,36 @@
30447 +Binding for simple gate clock.
30448 +
30449 +This binding uses the common clock binding[1]. It assumes a
30450 +register-mapped clock gate controlled by a single bit that has only one
30451 +input clock or parent. By default setting the specified bit gates the
30452 +clock signal and clearing the bit ungates it.
30453 +
30454 +The binding must provide the register to control the gate and the bit
30455 +shift for the corresponding gate control bit. Some clocks set the bit to
30456 +gate the clock signal, and clear it to ungate the clock signal. The
30457 +optional "set-bit-to-disable" specifies this behavior.
30458 +
30459 +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
30460 +
30461 +Required properties:
30462 +- compatible : shall be "gate-clock".
30463 +- #clock-cells : from common clock binding; shall be set to 0.
30464 +- clocks : link to phandle of parent clock
30465 +- reg : base address for register controlling adjustable gate
30466 +- bit-shift : bit shift for programming the clock gate
30467 +
30468 +Optional properties:
30469 +- clock-output-names : from common clock binding.
30470 +- set-bit-to-disable : inverts default gate programming. Setting the bit
30471 + gates the clock and clearing the bit ungates the clock.
30472 +- hiword-mask : lower half of the register controls the gate, upper half
30473 + of the register indicates bits that were updated in the lower half
30474 +
30475 +Examples:
30476 + clock_foo: clock_foo@4a008100 {
30477 + compatible = "gate-clock";
30478 + #clock-cells = <0>;
30479 + clocks = <&clock_bar>;
30480 + reg = <0x4a008100 0x4>
30481 + bit-shift = <3>
30482 + };
30483 --- /dev/null
30484 +++ b/Documentation/devicetree/bindings/clock/mux-clock.txt
30485 @@ -0,0 +1,79 @@
30486 +Binding for simple mux clock.
30487 +
30488 +This binding uses the common clock binding[1]. It assumes a
30489 +register-mapped multiplexer with multiple input clock signals or
30490 +parents, one of which can be selected as output. This clock does not
30491 +gate or adjust the parent rate via a divider or multiplier.
30492 +
30493 +By default the "clocks" property lists the parents in the same order
30494 +as they are programmed into the regster. E.g:
30495 +
30496 + clocks = <&foo_clock>, <&bar_clock>, <&baz_clock>;
30497 +
30498 +results in programming the register as follows:
30499 +
30500 +register value selected parent clock
30501 +0 foo_clock
30502 +1 bar_clock
30503 +2 baz_clock
30504 +
30505 +Some clock controller IPs do not allow a value of zero to be programmed
30506 +into the register, instead indexing begins at 1. The optional property
30507 +"index-starts-at-one" modified the scheme as follows:
30508 +
30509 +register value selected clock parent
30510 +1 foo_clock
30511 +2 bar_clock
30512 +3 baz_clock
30513 +
30514 +Additionally an optional table of bit and parent pairs may be supplied
30515 +like so:
30516 +
30517 + table = <&foo_clock 0x0>, <&bar_clock, 0x2>, <&baz_clock, 0x4>;
30518 +
30519 +where the first value in the pair is the parent clock and the second
30520 +value is the bitfield to be programmed into the register.
30521 +
30522 +The binding must provide the register to control the mux and the mask
30523 +for the corresponding control bits. Optionally the number of bits to
30524 +shift that mask if necessary. If the shift value is missing it is the
30525 +same as supplying a zero shift.
30526 +
30527 +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
30528 +
30529 +Required properties:
30530 +- compatible : shall be "mux-clock".
30531 +- #clock-cells : from common clock binding; shall be set to 0.
30532 +- clocks : link phandles of parent clocks
30533 +- reg : base address for register controlling adjustable mux
30534 +- bit-mask : arbitrary bitmask for programming the adjustable mux
30535 +
30536 +Optional properties:
30537 +- clock-output-names : From common clock binding.
30538 +- table : array of integer pairs defining parents & bitfield values
30539 +- bit-shift : number of bits to shift the bit-mask, defaults to
30540 + (ffs(mask) - 1) if not present
30541 +- index-starts-at-one : valid input select programming starts at 1, not
30542 + zero
30543 +- hiword-mask : lower half of the register programs the mux, upper half
30544 + of the register indicates bits that were updated in the lower half
30545 +
30546 +Examples:
30547 + clock: clock@4a008100 {
30548 + compatible = "mux-clock";
30549 + #clock-cells = <0>;
30550 + clocks = <&clock_foo>, <&clock_bar>, <&clock_baz>;
30551 + reg = <0x4a008100 0x4>
30552 + mask = <0x3>;
30553 + index-starts-at-one;
30554 + };
30555 +
30556 + clock: clock@4a008100 {
30557 + #clock-cells = <0>;
30558 + compatible = "mux-clock";
30559 + clocks = <&clock_foo>, <&clock_bar>, <&clock_baz>;
30560 + reg = <0x4a008100 0x4>;
30561 + mask = <0x3>;
30562 + shift = <0>;
30563 + table = <&clock_foo 1>, <&clock_bar 2>, <&clock_baz 3>;
30564 + };
30565 --- /dev/null
30566 +++ b/Documentation/devicetree/bindings/clock/ti/apll.txt
30567 @@ -0,0 +1,33 @@
30568 +Binding for Texas Instruments APLL clock.
30569 +
30570 +This binding uses the common clock binding[1]. It assumes a
30571 +register-mapped APLL with usually two selectable input clocks
30572 +(reference clock and bypass clock), with analog phase locked
30573 +loop logic for multiplying the input clock to a desired output
30574 +clock. This clock also typically supports different operation
30575 +modes (locked, low power stop etc.) APLL mostly behaves like
30576 +a subtype of a DPLL [2], although a simplified one at that.
30577 +
30578 +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
30579 +[2] Documentation/devicetree/bindings/clock/ti/dpll.txt
30580 +
30581 +Required properties:
30582 +- compatible : shall be "ti,dra7-apll-clock"
30583 +- #clock-cells : from common clock binding; shall be set to 0.
30584 +- clocks : link phandles of parent clocks (clk-ref and clk-bypass)
30585 +- reg : address and length of the register set for controlling the APLL.
30586 + It contains the information of registers in the same order as described by
30587 + reg-names.
30588 +- reg-names: array of the register names for controlling the device, sorted
30589 + in the same order as the reg property.
30590 + "control" - contains the control register base address
30591 + "idlest" - contains the idlest register base address
30592 +
30593 +Examples:
30594 + apll_pcie_ck: apll_pcie_ck@4a008200 {
30595 + #clock-cells = <0>;
30596 + clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>;
30597 + reg = <0x4a00821c 0x4>, <0x4a008220 0x4>;
30598 + reg-names = "control", "idlest";
30599 + compatible = "ti,dra7-apll-clock";
30600 + };
30601 --- /dev/null
30602 +++ b/Documentation/devicetree/bindings/clock/ti/autoidle.txt
30603 @@ -0,0 +1,48 @@
30604 +Binding for Texas Instruments autoidling clock.
30605 +
30606 +This binding uses the common clock binding[1]. Autoidle clocks
30607 +are inherited clocks from basic divider-clock [2] or
30608 +fixed-factor-clock [3] and just add autoidle support on top of
30609 +this. Autoidle is an OMAP clock feature, which allows the clock
30610 +to gate autonomously by hardware when they are no longer needed.
30611 +The autoidle feature must be enabled manually for these clocks.
30612 +Otherwise the clocks behave exactly as their base clock type.
30613 +
30614 +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
30615 +[2] Documentation/devicetree/bindings/clock/divider-clock.txt
30616 +[3] Documentation/devicetree/bindings/clock/fixed-factor-clock.txt
30617 +
30618 +Required properties:
30619 +- compatible : shall be one of:
30620 + "ti,divider-clock",
30621 + "ti,fixed-factor-clock"
30622 +- ti,autoidle-shift : bit shift of the autoidle enable bit for the clock
30623 +- reg : base address for the control register of this clock
30624 +
30625 +Optional properties:
30626 +- ti,autoidle-low : autoidle is enabled by setting the bit to 0
30627 +
30628 +Other properties as per the base clock type.
30629 +
30630 +Examples:
30631 + dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@4a0051f0 {
30632 + #clock-cells = <0>;
30633 + compatible = "ti,divider-clock";
30634 + clocks = <&dpll_abe_x2_ck>;
30635 + ti,autoidle-shift = <8>;
30636 + reg = <0x4a0051f0 0x4>;
30637 + bit-mask = <0x1f>;
30638 + index-starts-at-one;
30639 + ti,autoidle-low;
30640 + };
30641 +
30642 + dpll_usb_clkdcoldo_ck: dpll_usb_clkdcoldo_ck@4a0081b4 {
30643 + #clock-cells = <0>;
30644 + compatible = "ti,fixed-factor-clock";
30645 + clocks = <&dpll_usb_ck>;
30646 + ti,autoidle-shift = <8>;
30647 + clock-div = <1>;
30648 + reg = <0x4a0081b4 0x4>;
30649 + clock-mult = <1>;
30650 + ti,autoidle-low;
30651 + };
30652 --- /dev/null
30653 +++ b/Documentation/devicetree/bindings/clock/ti/clockdomain.txt
30654 @@ -0,0 +1,19 @@
30655 +Binding for Texas Instruments clockdomain.
30656 +
30657 +This binding uses the common clock binding[1]. Every clock on
30658 +TI SoC belongs to one clockdomain, but software only needs this
30659 +information for specific clocks which require their parent
30660 +clockdomain to be controlled when the clock is enabled/disabled.
30661 +
30662 +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
30663 +
30664 +Required properties:
30665 +- compatible : shall be "ti,clockdomain"
30666 +- #clock-cells : from common clock binding; shall be set to 0.
30667 +- clocks : link phandles of clocks within this domain
30668 +
30669 +Examples:
30670 + dss_clkdm: dss_clkdm {
30671 + compatible = "ti,clockdomain";
30672 + clocks = <&dss1_alwon_fck_3430es2>, <&dss_ick_3430es2>;
30673 + };
30674 --- /dev/null
30675 +++ b/Documentation/devicetree/bindings/clock/ti/dpll.txt
30676 @@ -0,0 +1,68 @@
30677 +Binding for Texas Instruments DPLL clock.
30678 +
30679 +This binding uses the common clock binding[1]. It assumes a
30680 +register-mapped DPLL with usually two selectable input clocks
30681 +(reference clock and bypass clock), with digital phase locked
30682 +loop logic for multiplying the input clock to a desired output
30683 +clock. This clock also typically supports different operation
30684 +modes (locked, low power stop etc.) This binding has several
30685 +sub-types, which effectively result in slightly different setup
30686 +for the actual DPLL clock.
30687 +
30688 +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
30689 +
30690 +Required properties:
30691 +- compatible : shall be one of:
30692 + "ti,omap4-dpll-x2-clock",
30693 + "ti,omap3-dpll-clock",
30694 + "ti,omap3-dpll-core-clock",
30695 + "ti,omap3-dpll-per-clock",
30696 + "ti,omap3-dpll-per-j-type-clock",
30697 + "ti,omap4-dpll-clock",
30698 + "ti,omap4-dpll-core-clock",
30699 + "ti,omap4-dpll-m4xen-clock",
30700 + "ti,omap4-dpll-j-type-clock",
30701 + "ti,omap4-dpll-no-gate-clock",
30702 + "ti,omap4-dpll-no-gate-j-type-clock",
30703 +
30704 +- #clock-cells : from common clock binding; shall be set to 0.
30705 +- clocks : link phandles of parent clocks, first entry lists reference clock
30706 + and second entry bypass clock
30707 +- reg : address and length of the register set for controlling the DPLL.
30708 + It contains the information of registers in the same order as described by
30709 + reg-names.
30710 +- reg-names : array of the register names for controlling the device, sorted
30711 + in the same order as the reg property.
30712 + "control" - contains the control register base address
30713 + "idlest" - contains the idle status register base address
30714 + "autoidle" - contains the autoidle register base address
30715 + "mult-div1" - contains the multiplier / divider register base address
30716 +
30717 +Optional properties:
30718 +- ti,modes : available modes for the DPLL, bitmask of:
30719 + 0x02 - DPLL supports low power stop mode
30720 + 0x20 - DPLL can be put to low power bypass mode
30721 + 0x80 - DPLL can be put to lock mode (running)
30722 + Other values currently unsupported.
30723 +- ti,clkdm-name : clockdomain name for the DPLL
30724 +
30725 +Examples:
30726 + dpll_core_ck: dpll_core_ck@44e00490 {
30727 + #clock-cells = <0>;
30728 + compatible = "ti,omap4-dpll-core-clock";
30729 + clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
30730 + reg = <0x44e00490 0x4>, <0x44e0045c 0x4>, <0x0 0x4>,
30731 + <0x44e00468 0x4>;
30732 + reg-names = "control", "idlest", "autoidle", "mult-div1";
30733 + };
30734 +
30735 + dpll2_ck: dpll2_ck@48004004 {
30736 + #clock-cells = <0>;
30737 + compatible = "ti,omap3-dpll-clock";
30738 + clocks = <&sys_ck>, <&dpll2_fck>;
30739 + ti,modes = <0xa2>;
30740 + reg = <0x48004004 0x4>, <0x48004024 0x4>, <0x48004034 0x4>,
30741 + <0x48004040 0x4>;
30742 + reg-names = "control", "idlest", "autoidle", "mult-div1";
30743 + ti,clkdm-name = "dpll2_clkdm";
30744 + };
30745 --- /dev/null
30746 +++ b/Documentation/devicetree/bindings/clock/ti/gate.txt
30747 @@ -0,0 +1,73 @@
30748 +Binding for Texas Instruments gate clock.
30749 +
30750 +This binding uses the common clock binding[1]. This clock is
30751 +quite much similar to the basic gate-clock [2], however,
30752 +it supports a number of additional features. If no register
30753 +is provided for this clock, the code assumes that a clockdomain
30754 +will be controlled instead and the corresponding hw-ops for
30755 +that is used.
30756 +
30757 +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
30758 +[2] Documentation/devicetree/bindings/clock/gate-clock.txt
30759 +[3] Documentation/devicetree/bindings/clock/ti/clockdomain.txt
30760 +
30761 +Required properties:
30762 +- compatible : shall be one of:
30763 + "ti,gate-clock" - basic gate clock
30764 + "ti,dss-gate-clock" - gate clock with DSS specific hardware handling
30765 + "ti,am35xx-gate-clock" - gate clock with AM35xx specific hardware handling
30766 + "ti,clkdm-gate-clock" - clockdomain gate clock, which derives its functional
30767 + clock directly from a clockdomain, see [3] how
30768 + to map clockdomains properly
30769 + "ti,hsdiv-gate-clock" - gate clock with OMAP36xx specific hardware handling,
30770 + required for a hardware errata
30771 +- #clock-cells : from common clock binding; shall be set to 0
30772 +- clocks : link to phandle of parent clock
30773 +- reg : base address for register controlling adjustable gate, not needed for
30774 + ti,clkdm-gate-clock type
30775 +- ti,enable-bit : bit shift for programming the clock gate, not needed for
30776 + ti,clkdm-gate-clock type
30777 +
30778 +Optional properties:
30779 +- ti,set-bit-to-disable : inverts default gate programming. Setting the bit
30780 + gates the clock and clearing the bit ungates the clock.
30781 +
30782 +Examples:
30783 + mmchs2_fck: mmchs2_fck@48004a00 {
30784 + #clock-cells = <0>;
30785 + compatible = "ti,gate-clock";
30786 + clocks = <&core_96m_fck>;
30787 + reg = <0x48004a00 0x4>;
30788 + ti,enable-bit = <25>;
30789 + };
30790 +
30791 + dss1_alwon_fck_3430es2: dss1_alwon_fck_3430es2@48004e00 {
30792 + #clock-cells = <0>;
30793 + compatible = "ti,dss-gate-clock";
30794 + clocks = <&dpll4_m4x2_ck>;
30795 + reg = <0x48004e00 0x4>;
30796 + ti,enable-bit = <0>;
30797 + };
30798 +
30799 + emac_ick: emac_ick@4800259c {
30800 + #clock-cells = <0>;
30801 + compatible = "ti,am35xx-gate-clock";
30802 + clocks = <&ipss_ick>;
30803 + reg = <0x4800259c 0x4>;
30804 + ti,enable-bit = <1>;
30805 + };
30806 +
30807 + emu_src_ck: emu_src_ck {
30808 + #clock-cells = <0>;
30809 + compatible = "ti,clkdm-gate-clock";
30810 + clocks = <&emu_src_mux_ck>;
30811 + };
30812 +
30813 + dpll4_m2x2_ck: dpll4_m2x2_ck@48004d00 {
30814 + #clock-cells = <0>;
30815 + compatible = "ti,hsdiv-gate-clock";
30816 + clocks = <&dpll4_m2x2_mul_ck>;
30817 + ti,enable-bit = <0x1b>;
30818 + reg = <0x48004d00 0x4>;
30819 + ti,set-bit-to-disable;
30820 + };
30821 --- /dev/null
30822 +++ b/Documentation/devicetree/bindings/clock/ti/interface.txt
30823 @@ -0,0 +1,53 @@
30824 +Binding for Texas Instruments interface clock.
30825 +
30826 +This binding uses the common clock binding[1]. This clock is
30827 +quite much similar to the basic gate-clock [2], however,
30828 +it supports a number of additional features, including
30829 +companion clock finding (match corresponding functional gate
30830 +clock) and hardware autoidle enable / disable.
30831 +
30832 +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
30833 +[2] Documentation/devicetree/bindings/clock/gate-clock.txt
30834 +
30835 +Required properties:
30836 +- compatible : shall be one of:
30837 + "ti,omap3-interface-clock" - basic OMAP3 interface clock
30838 + "ti,omap3-no-wait-interface-clock" - interface clock which has no hardware
30839 + capability for waiting clock to be ready
30840 + "ti,omap3-hsotgusb-interface-clock" - interface clock with USB specific HW
30841 + handling
30842 + "ti,omap3-dss-interface-clock" - interface clock with DSS specific HW handling
30843 + "ti,omap3-ssi-interface-clock" - interface clock with SSI specific HW handling
30844 + "ti,am35xx-interface-clock" - interface clock with AM35xx specific HW handling
30845 +- #clock-cells : from common clock binding; shall be set to 0
30846 +- clocks : link to phandle of parent clock
30847 +- reg : base address for the control register
30848 +
30849 +Optional properties:
30850 +- ti,enable-bit : bit shift for the bit enabling/disabling the clock
30851 + (default 0)
30852 +
30853 +Examples:
30854 + aes1_ick: aes1_ick@48004a14 {
30855 + #clock-cells = <0>;
30856 + compatible = "ti,omap3-interface-clock";
30857 + clocks = <&security_l4_ick2>;
30858 + reg = <0x48004a14 0x4>;
30859 + ti,enable-bit = <3>;
30860 + };
30861 +
30862 + cam_ick: cam_ick@48004f10 {
30863 + #clock-cells = <0>;
30864 + compatible = "ti,omap3-no-wait-interface-clock";
30865 + clocks = <&l4_ick>;
30866 + reg = <0x48004f10 0x4>;
30867 + ti,enable-bit = <0>;
30868 + };
30869 +
30870 + ssi_ick_3430es2: ssi_ick_3430es2@48004a10 {
30871 + #clock-cells = <0>;
30872 + compatible = "ti,omap3-ssi-interface-clock";
30873 + clocks = <&ssi_l4_ick>;
30874 + reg = <0x48004a10 0x4>;
30875 + ti,enable-bit = <0>;
30876 + };
30877 --- a/Documentation/devicetree/bindings/dma/atmel-dma.txt
30878 +++ b/Documentation/devicetree/bindings/dma/atmel-dma.txt
30879 @@ -28,7 +28,7 @@ The three cells in order are:
30880 dependent:
30881 - bit 7-0: peripheral identifier for the hardware handshaking interface. The
30882 identifier can be different for tx and rx.
30883 - - bit 11-8: FIFO configuration. 0 for half FIFO, 1 for ALAP, 1 for ASAP.
30884 + - bit 11-8: FIFO configuration. 0 for half FIFO, 1 for ALAP, 2 for ASAP.
30885
30886 Example:
30887
30888 --- /dev/null
30889 +++ b/Documentation/devicetree/bindings/extcon/extcon-gpio-usbvid.txt
30890 @@ -0,0 +1,20 @@
30891 +EXTCON FOR USB VIA GPIO
30892 +
30893 +Required Properties:
30894 + - compatible : Should be "ti,gpio-usb-vid" for USB VBUS-ID detector
30895 + using gpios or "ti,gpio-usb-id" for USB ID pin detector
30896 + - gpios : phandle and args ID pin gpio and VBUS gpio.
30897 + The first gpio used for ID pin detection
30898 + and the second used for VBUS detection.
30899 + ID pin gpio is mandatory and VBUS is optional
30900 + depending on implementation.
30901 +
30902 +Please refer to ../gpio/gpio.txt for details of the common GPIO bindings
30903 +
30904 +Example:
30905 +
30906 + gpio_usbvid_extcon1 {
30907 + compatible = "ti,gpio-usb-vid";
30908 + gpios = <&gpio1 1 0>,
30909 + <&gpio2 2 0>;
30910 + };
30911 --- a/Documentation/devicetree/bindings/extcon/extcon-palmas.txt
30912 +++ b/Documentation/devicetree/bindings/extcon/extcon-palmas.txt
30913 @@ -2,7 +2,8 @@ EXTCON FOR PALMAS/TWL CHIPS
30914
30915 PALMAS USB COMPARATOR
30916 Required Properties:
30917 - - compatible : Should be "ti,palmas-usb" or "ti,twl6035-usb"
30918 + - compatible : Should be "ti,palmas-usb-vid". "ti,twl6035-usb" and
30919 + "ti,palmas-usb" is deprecated and is kept for backward compatibility.
30920
30921 Optional Properties:
30922 - ti,wakeup : To enable the wakeup comparator in probe
30923 --- /dev/null
30924 +++ b/Documentation/devicetree/bindings/gpio/gpio-pcf857x.txt
30925 @@ -0,0 +1,71 @@
30926 +* PCF857x-compatible I/O expanders
30927 +
30928 +The PCF857x-compatible chips have "quasi-bidirectional" I/O lines that can be
30929 +driven high by a pull-up current source or driven low to ground. This combines
30930 +the direction and output level into a single bit per line, which can't be read
30931 +back. We can't actually know at initialization time whether a line is configured
30932 +(a) as output and driving the signal low/high, or (b) as input and reporting a
30933 +low/high value, without knowing the last value written since the chip came out
30934 +of reset (if any). The only reliable solution for setting up line direction is
30935 +thus to do it explicitly.
30936 +
30937 +Required Properties:
30938 +
30939 + - compatible: should be one of the following.
30940 + - "maxim,max7328": For the Maxim MAX7378
30941 + - "maxim,max7329": For the Maxim MAX7329
30942 + - "nxp,pca8574": For the NXP PCA8574
30943 + - "nxp,pca8575": For the NXP PCA8575
30944 + - "nxp,pca9670": For the NXP PCA9670
30945 + - "nxp,pca9671": For the NXP PCA9671
30946 + - "nxp,pca9672": For the NXP PCA9672
30947 + - "nxp,pca9673": For the NXP PCA9673
30948 + - "nxp,pca9674": For the NXP PCA9674
30949 + - "nxp,pca9675": For the NXP PCA9675
30950 + - "nxp,pcf8574": For the NXP PCF8574
30951 + - "nxp,pcf8574a": For the NXP PCF8574A
30952 + - "nxp,pcf8575": For the NXP PCF8575
30953 + - "ti,tca9554": For the TI TCA9554
30954 +
30955 + - reg: I2C slave address.
30956 +
30957 + - gpio-controller: Marks the device node as a gpio controller.
30958 + - #gpio-cells: Should be 2. The first cell is the GPIO number and the second
30959 + cell specifies GPIO flags, as defined in <dt-bindings/gpio/gpio.h>. Only the
30960 + GPIO_ACTIVE_HIGH and GPIO_ACTIVE_LOW flags are supported.
30961 +
30962 +Optional Properties:
30963 +
30964 + - lines-initial-states: Bitmask that specifies the initial state of each
30965 + line. When a bit is set to zero, the corresponding line will be initialized to
30966 + the input (pulled-up) state. When the bit is set to one, the line will be
30967 + initialized the the low-level output state. If the property is not specified
30968 + all lines will be initialized to the input state.
30969 +
30970 + The I/O expander can detect input state changes, and thus optionally act as
30971 + an interrupt controller. When the expander interrupt line is connected all the
30972 + following properties must be set. For more information please see the
30973 + interrupt controller device tree bindings documentation available at
30974 + Documentation/devicetree/bindings/interrupt-controller/interrupts.txt.
30975 +
30976 + - interrupt-controller: Identifies the node as an interrupt controller.
30977 + - #interrupt-cells: Number of cells to encode an interrupt source, shall be 2.
30978 + - interrupt-parent: phandle of the parent interrupt controller.
30979 + - interrupts: Interrupt specifier for the controllers interrupt.
30980 +
30981 +
30982 +Please refer to gpio.txt in this directory for details of the common GPIO
30983 +bindings used by client devices.
30984 +
30985 +Example: PCF8575 I/O expander node
30986 +
30987 + pcf8575: gpio@20 {
30988 + compatible = "nxp,pcf8575";
30989 + reg = <0x20>;
30990 + interrupt-parent = <&irqpin2>;
30991 + interrupts = <3 0>;
30992 + gpio-controller;
30993 + #gpio-cells = <2>;
30994 + interrupt-controller;
30995 + #interrupt-cells = <2>;
30996 + };
30997 --- /dev/null
30998 +++ b/Documentation/devicetree/bindings/hwrng/omap_rng.txt
30999 @@ -0,0 +1,22 @@
31000 +OMAP SoC HWRNG Module
31001 +
31002 +Required properties:
31003 +
31004 +- compatible : Should contain entries for this and backward compatible
31005 + RNG versions:
31006 + - "ti,omap2-rng" for OMAP2.
31007 + - "ti,omap4-rng" for OMAP4, OMAP5 and AM33XX.
31008 + Note that these two versions are incompatible.
31009 +- ti,hwmods: Name of the hwmod associated with the RNG module
31010 +- reg : Offset and length of the register set for the module
31011 +- interrupts : the interrupt number for the RNG module.
31012 + Only used for "ti,omap4-rng".
31013 +
31014 +Example:
31015 +/* AM335x */
31016 +rng: rng@48310000 {
31017 + compatible = "ti,omap4-rng";
31018 + ti,hwmods = "rng";
31019 + reg = <0x48310000 0x2000>;
31020 + interrupts = <111>;
31021 +};
31022 --- /dev/null
31023 +++ b/Documentation/devicetree/bindings/input/touchscreen/atmel_mxt_ts.txt
31024 @@ -0,0 +1,108 @@
31025 +Atmel MaxTouch Touchscreen
31026 +--------------------------
31027 +Required properties:
31028 + - compatible: "atmel,mXT244" or "atmel,qt602240_ts"
31029 + or "atmel,atmel_mxt_ts"
31030 + - reg: I2C address of the chip
31031 + - interrupts: interrupt signal to which the chip is connected
31032 + - atmel,x-line: Number of x lines the touch object occupies in pixels
31033 + - atmel,y-line: Number of y lines the touch object occupies in pixels
31034 + - atmel,x-size: Horizontal resolution of touchscreen in pixels
31035 + - atmel,y-size: Vertical resolution of touchscreen in pixels
31036 + - atmel,blen: Sets the gain of the analog circuit in front of ADC
31037 + Gain setting depends on package type. Range: 0-3
31038 + - atmel,threshold: Channel detection threshold value. Range: 0-255
31039 + Typical: 30-80. Lower the threshold, higher the
31040 + sensitivity
31041 + - atmel,voltage: Nominal AVdd in uV for analog circuitry, greater than
31042 + or less than base voltage of 2.7V, used for optimizing
31043 + capacitive sensing. For example, if you want to
31044 + program an optimum voltage of 2.8V in your design,
31045 + specify 2800000 for this parameter
31046 + - atmel,orientation: touchscreen orientation, must be one of following,
31047 + as defined inside include/linux/i2c/atmel_mxt_ts.h
31048 + - 0: MXT_NORMAL - normal
31049 + - 1: MXT_DIAGONAL - diagonal
31050 + - 2: MXT_HORIZONTAL_FLIP - horizonally flipped
31051 + - 3: MXT_ROTATED_90_COUNTER - rotated by 90 degrees
31052 + counter-clockwise
31053 + - 4: MXT_VERTICAL_FLIP - vertically flipped
31054 + - 5: MXT_ROTATED_90 - rotated by 90 degress clockwise
31055 + - 6: MXT_ROTATED_180 - rotated by 180 degrees
31056 + - 7: MXT_DIAGONAL_COUNTER - diagonal counter
31057 +
31058 +Optional properties:
31059 + - atmel,config: list of 8-bit register values for controller objects
31060 + in the following order. Number of objects and values depends on the
31061 + particular model of Atmel touch screen you are using. Please check
31062 + with your Atmel representative for helping you tune these values
31063 + GEN_COMMAND, GEN_POWER, GEN_ACQUIRE, TOUCH_MULTI
31064 + TOUCH_KEYARRAY, MXT244_COMMSCONFIG_T18, SPT_GPIOPWM, PROCI_GRIPFACE,
31065 + PROCG_NOISE, TOUCH_PROXIMITY, PROCI_ONETOUCH, SPT_SELFTEST,
31066 + PROCI_TWOTOUCH, SPT_CTECONFIG
31067 + Note: These register values can be specified here according to
31068 + the specific controller and platform configuration desired. The
31069 + driver does not configure these registers by default and leaves it
31070 + to the platform dts file to supply them
31071 +
31072 +Example:
31073 +
31074 + &i2c1 {
31075 + mXT244:mXT244@4a {
31076 + reg = <0x4a>;
31077 + };
31078 + };
31079 +
31080 + &mXT244 {
31081 + compatible = "atmel,mXT244";
31082 + interrupts = <0 119 0x4>;
31083 +
31084 + atmel,config = <
31085 + /* MXT244_GEN_COMMAND(6) */
31086 + 0x00 0x00 0x00 0x00 0x00 0x00
31087 + /* MXT244_GEN_POWER(7) */
31088 + 0x20 0xff 0x32
31089 + /* MXT244_GEN_ACQUIRE(8) */
31090 + 0x0a 0x00 0x05 0x00 0x00 0x00 0x09 0x23
31091 + /* MXT244_TOUCH_MULTI(9) */
31092 + 0x00 0x00 0x00 0x13 0x0b 0x00 0x00 0x00 0x02 0x00
31093 + 0x00 0x01 0x01 0x0e 0x0a 0x0a 0x0a 0x0a 0x00 0x00
31094 + 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
31095 + 0x00
31096 + /* MXT244_TOUCH_KEYARRAY(15) */
31097 + 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
31098 + 0x00
31099 + /* MXT244_COMMSCONFIG_T18(2) */
31100 + 0x00 0x00
31101 + /* MXT244_SPT_GPIOPWM(19) */
31102 + 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
31103 + 0x00 0x00 0x00 0x00 0x00 0x00
31104 + /* MXT244_PROCI_GRIPFACE(20) */
31105 + 0x07 0x00 0x00 0x00 0x00 0x00 0x00 0x50 0x28 0x04
31106 + 0x0f 0x0a
31107 + /* MXT244_PROCG_NOISE(22) */
31108 + 0x05 0x00 0x00 0x00 0x00 0x00 0x00 0x03 0x23 0x00
31109 + 0x00 0x05 0x0f 0x19 0x23 0x2d 0x03
31110 + /* MXT244_TOUCH_PROXIMITY(23) */
31111 + 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
31112 + 0x00 0x00 0x00 0x00 0x00
31113 + /* MXT244_PROCI_ONETOUCH(24) */
31114 + 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
31115 + 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
31116 + /* MXT244_SPT_SELFTEST(25) */
31117 + 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
31118 + 0x00 0x00 0x00 0x00
31119 + /* MXT244_PROCI_TWOTOUCH(27) */
31120 + 0x00 0x00 0x00 0x00 0x00 0x00 0x00
31121 + /* MXT244_SPT_CTECONFIG(28) */
31122 + 0x00 0x00 0x02 0x08 0x10 0x00 >;
31123 +
31124 + atmel,x_line = <18>;
31125 + atmel,y_line = <12>;
31126 + atmel,x_size = <800>;
31127 + atmel,y_size = <480>;
31128 + atmel,blen = <0x01>;
31129 + atmel,threshold = <30>;
31130 + atmel,voltage = <2800000>;
31131 + atmel,orient = <0x4>;
31132 + };
31133 --- /dev/null
31134 +++ b/Documentation/devicetree/bindings/input/touchscreen/pixcir_i2c_ts.txt
31135 @@ -0,0 +1,26 @@
31136 +* Pixcir I2C touchscreen controllers
31137 +
31138 +Required properties:
31139 +- compatible: must be "pixcir,pixcir_ts" or "pixcir,pixcir_tangoc"
31140 +- reg: I2C address of the chip
31141 +- interrupts: interrupt to which the chip is connected
31142 +- attb-gpio: GPIO connected to the ATTB line of the chip
31143 +- x-size: horizontal resolution of touchscreen
31144 +- y-size: vertical resolution of touchscreen
31145 +
31146 +Example:
31147 +
31148 + i2c@00000000 {
31149 + /* ... */
31150 +
31151 + pixcir_ts@5c {
31152 + compatible = "pixcir,pixcir_ts";
31153 + reg = <0x5c>;
31154 + interrupts = <2 0>;
31155 + attb-gpio = <&gpf 2 0 2>;
31156 + x-size = <800>;
31157 + y-size = <600>;
31158 + };
31159 +
31160 + /* ... */
31161 + };
31162 --- a/Documentation/devicetree/bindings/input/touchscreen/ti-tsc-adc.txt
31163 +++ b/Documentation/devicetree/bindings/input/touchscreen/ti-tsc-adc.txt
31164 @@ -6,7 +6,7 @@ Required properties:
31165 ti,wires: Wires refer to application modes i.e. 4/5/8 wire touchscreen
31166 support on the platform.
31167 ti,x-plate-resistance: X plate resistance
31168 - ti,coordiante-readouts: The sequencer supports a total of 16
31169 + ti,coordinate-readouts: The sequencer supports a total of 16
31170 programmable steps each step is used to
31171 read a single coordinate. A single
31172 readout is enough but multiple reads can
31173 --- /dev/null
31174 +++ b/Documentation/devicetree/bindings/mailbox/omap-mailbox.txt
31175 @@ -0,0 +1,76 @@
31176 +OMAP2+ Mailbox Driver
31177 +=====================
31178 +
31179 +The OMAP mailbox hardware facilitates communication between different
31180 +processors using a queued mailbox interrupt mechanism. The IP block is
31181 +external to the various processor subsystems and is connected on an
31182 +interconnect bus. The communication is achieved through a set of
31183 +registers for message storage and interrupt configuration registers.
31184 +
31185 +Each mailbox IP block has a certain number of h/w fifo queues and output
31186 +interrupt lines. An output interrupt line is routed to a specific interrupt
31187 +controller on a processor subsystem, and there can be more than one line
31188 +going to a specific processor's interrupt controller. The interrupt line
31189 +connections are fixed for an instance and are dictated by the IP integration
31190 +into the SoC. Each interrupt line is programmable through a set of interrupt
31191 +configuration registers, and have a rx and tx interrupt source per h/w fifo.
31192 +Communication between different processors is achieved through the appropriate
31193 +programming of the rx and tx interrupt sources on the appropriate interrupt
31194 +lines.
31195 +
31196 +The number of h/w fifo queues and interrupt lines dictate the usable registers.
31197 +All the current OMAP SoCs except for the newest DRA7xx SoC has a single IP
31198 +instance. DRA7xx has multiple instances with different number of h/w fifo
31199 +queues and interrupt lines between different instances. The interrupt lines
31200 +can also be routed to different processor sub-systems on DRA7xx as they are
31201 +routed through the Crossbar, a kind of interrupt router/multiplexer.
31202 +
31203 +The above two varying SoC IP integration parameters are defined specifically
31204 +through the "ti,mbox-num-users" and "ti,mbox-num-fifos" device-tree properties.
31205 +These are defined in the DT nodes since these design parameters can vary between
31206 +one instance to another in an SoC (eg: DRA7xx) even though the base IP design
31207 +is identical.
31208 +
31209 +Required properties:
31210 +--------------------
31211 +- compatible: Should be one of the following,
31212 + "ti,omap2-mailbox" for
31213 + OMAP2420, OMAP2430, OMAP3430, OMAP3630 SoCs
31214 + "ti,omap4-mailbox" for
31215 + OMAP44xx, OMAP54xx, AM33xx, AM43xx, DRA7xx SoCs
31216 +- reg: Contains the mailbox register address range (base address
31217 + and length)
31218 +- interrupts: Contains the interrupt information for the mailbox
31219 + device. The format is dependent on which interrupt
31220 + controller the OMAP device uses
31221 +- ti,hwmods: Name of the hwmod associated with the mailbox
31222 +- ti,mbox-num-users: Number of targets (processor devices) that the mailbox device
31223 + can interrupt
31224 +- ti,mbox-num-fifos: Number of h/w fifos within the mailbox device
31225 +- ti,mbox-names: Array of the names of the mailboxes
31226 +- ti,mbox-data: Mailbox descriptor data private to each mailbox. The 4
31227 + cells represent the following data,
31228 + Cell #1 (tx_id) - mailbox fifo id used for
31229 + transmitting messages
31230 + Cell #2 (rx_id) - mailbox fifo id on which messages
31231 + are received
31232 + Cell #3 (irq_id) - irq identifier index number to use
31233 + from the interrupts data
31234 + Cell #4 (usr_id) - mailbox user id for identifying the
31235 + interrupt into the MPU interrupt
31236 + controller.
31237 +
31238 +Example:
31239 +--------
31240 +
31241 +/* OMAP4 */
31242 +mailbox: mailbox@4a0f4000 {
31243 + compatible = "ti,omap4-mailbox";
31244 + reg = <0x4a0f4000 0x200>;
31245 + interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
31246 + ti,hwmods = "mailbox";
31247 + ti,mbox-num-users = <3>;
31248 + ti,mbox-num-fifos = <8>;
31249 + ti,mbox-names = "mbox-ipu", "mbox-dsp";
31250 + ti,mbox-data = <0 1 0 0>, <3 2 0 0>;
31251 +};
31252 --- /dev/null
31253 +++ b/Documentation/devicetree/bindings/mfd/tps65218.txt
31254 @@ -0,0 +1,27 @@
31255 +The TPS65218 Integrated Power Management Chips.
31256 +These chips are connected to an i2c bus.
31257 +
31258 +Required properties:
31259 +- compatible : Must be "ti,tps65218";
31260 +- interrupts : This i2c device has an IRQ line connected to the main SoC
31261 +- interrupt-controller : Since the tps65218 support several interrupts
31262 + internally, it is considered as an interrupt controller cascaded to the SoC.
31263 +- #interrupt-cells = <2>;
31264 +- interrupt-parent : The parent interrupt controller.
31265 +
31266 +Optional node:
31267 +- Child nodes contain in the tps65218.
31268 + It supports a number of features.
31269 + The children nodes will thus depend of the capability of the variant.
31270 +
31271 +Example:
31272 +/*
31273 + * Integrated Power Management Chip
31274 + */
31275 +tps@24 {
31276 + compatible = "ti,tps65218";
31277 + reg = <0x24>;
31278 + interrupt-controller;
31279 + #interrupt-cells = <2>;
31280 + interrupt-parent = <&gic>;
31281 +};
31282 --- a/Documentation/devicetree/bindings/mfd/twl6040.txt
31283 +++ b/Documentation/devicetree/bindings/mfd/twl6040.txt
31284 @@ -19,6 +19,8 @@ Required properties:
31285
31286 Optional properties, nodes:
31287 - enable-active-high: To power on the twl6040 during boot.
31288 +- clocks: phandle to the clk32k clock provider
31289 +- clock-names: Must be "clk32k"
31290
31291 Vibra functionality
31292 Required properties:
31293 --- a/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt
31294 +++ b/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt
31295 @@ -20,8 +20,29 @@ ti,dual-volt: boolean, supports dual vol
31296 ti,non-removable: non-removable slot (like eMMC)
31297 ti,needs-special-reset: Requires a special softreset sequence
31298 ti,needs-special-hs-handling: HSMMC IP needs special setting for handling High Speed
31299 +dmas: List of DMA specifiers with the controller specific format
31300 +as described in the generic DMA client binding. A tx and rx
31301 +specifier is required.
31302 +dma-names: List of DMA request names. These strings correspond
31303 +1:1 with the DMA specifiers listed in dmas. The string naming is
31304 +to be "rx" and "tx" for RX and TX DMA requests, respectively.
31305 +
31306 +Examples:
31307 +
31308 +[hwmod populated DMA resources]
31309 +
31310 + mmc1: mmc@0x4809c000 {
31311 + compatible = "ti,omap4-hsmmc";
31312 + reg = <0x4809c000 0x400>;
31313 + ti,hwmods = "mmc1";
31314 + ti,dual-volt;
31315 + bus-width = <4>;
31316 + vmmc-supply = <&vmmc>; /* phandle to regulator node */
31317 + ti,non-removable;
31318 + };
31319 +
31320 +[generic DMA request binding]
31321
31322 -Example:
31323 mmc1: mmc@0x4809c000 {
31324 compatible = "ti,omap4-hsmmc";
31325 reg = <0x4809c000 0x400>;
31326 @@ -30,4 +51,7 @@ Example:
31327 bus-width = <4>;
31328 vmmc-supply = <&vmmc>; /* phandle to regulator node */
31329 ti,non-removable;
31330 + dmas = <&edma 24
31331 + &edma 25>;
31332 + dma-names = "tx", "rx";
31333 };
31334 --- a/Documentation/devicetree/bindings/mtd/gpmc-nand.txt
31335 +++ b/Documentation/devicetree/bindings/mtd/gpmc-nand.txt
31336 @@ -21,13 +21,11 @@ Optional properties:
31337 is wired that way. If not specified, a bus
31338 width of 8 is assumed.
31339
31340 - - ti,nand-ecc-opt: A string setting the ECC layout to use. One of:
31341 -
31342 - "sw" Software method (default)
31343 - "hw" Hardware method
31344 - "hw-romcode" gpmc hamming mode method & romcode layout
31345 + - ti,nand-ecc-scheme: A string setting the ECC layout to use. One of:
31346 + "ham1" 1-bit Hamming ecc code
31347 "bch4" 4-bit BCH ecc code
31348 "bch8" 8-bit BCH ecc code
31349 + "bch16" 16-bit BCH ecc code
31350
31351 - ti,nand-xfer-type: A string setting the data transfer type. One of:
31352
31353 @@ -36,8 +34,11 @@ Optional properties:
31354 "prefetch-dma" Prefetch enabled sDMA mode
31355 "prefetch-irq" Prefetch enabled irq mode
31356
31357 - - elm_id: Specifies elm device node. This is required to support BCH
31358 - error correction using ELM module.
31359 + - ti,elm-id: Specifies pHandle of the ELM devicetree node.
31360 + ELM is an on-chip hardware engine on TI SoC which is used for
31361 + locating ECC errors for BCHx algorithms. SoC devices which have
31362 + ELM hardware engines should specify this device node in .dtsi
31363 + Using ELM for ECC error correction frees some CPU cycles.
31364
31365 For inline partiton table parsing (optional):
31366
31367 --- /dev/null
31368 +++ b/Documentation/devicetree/bindings/net/cpsw-phy-sel.txt
31369 @@ -0,0 +1,28 @@
31370 +TI CPSW Phy mode Selection Device Tree Bindings
31371 +-----------------------------------------------
31372 +
31373 +Required properties:
31374 +- compatible : Should be "ti,am3352-cpsw-phy-sel"
31375 +- reg : physical base address and size of the cpsw
31376 + registers map
31377 +- reg-names : names of the register map given in "reg" node
31378 +
31379 +Optional properties:
31380 +-rmii-clock-ext : If present, the driver will configure the RMII
31381 + interface to external clock usage
31382 +
31383 +Examples:
31384 +
31385 + phy_sel: cpsw-phy-sel@44e10650 {
31386 + compatible = "ti,am3352-cpsw-phy-sel";
31387 + reg= <0x44e10650 0x4>;
31388 + reg-names = "gmii-sel";
31389 + };
31390 +
31391 +(or)
31392 + phy_sel: cpsw-phy-sel@44e10650 {
31393 + compatible = "ti,am3352-cpsw-phy-sel";
31394 + reg= <0x44e10650 0x4>;
31395 + reg-names = "gmii-sel";
31396 + rmii-clock-ext;
31397 + };
31398 --- /dev/null
31399 +++ b/Documentation/devicetree/bindings/net/smsc95xx.txt
31400 @@ -0,0 +1,16 @@
31401 +* Smart Mixed-Signal Connectivity (SMSC) 95xx Controller
31402 +
31403 +Required properties:
31404 +None
31405 +
31406 +Optional properties:
31407 +- mac-address - Read the mac address that was stored by uBoot
31408 +- local-address - Read the mac address that was stored by uBoot
31409 +- address - Read the mac address that was stored by uBoot
31410 +
31411 +Examples:
31412 +
31413 +smsc0: smsc95xx@0 {
31414 + /* Filled in by U-Boot */
31415 + mac-address = [ 00 00 00 00 00 00 ];
31416 +};
31417 --- /dev/null
31418 +++ b/Documentation/devicetree/bindings/phy/omap-phy.txt
31419 @@ -0,0 +1,78 @@
31420 +OMAP PHY: DT DOCUMENTATION FOR PHYs in OMAP PLATFORM
31421 +
31422 +OMAP CONTROL PHY
31423 +
31424 +Required properties:
31425 + - compatible: Should be one of
31426 + "ti,control-phy-otghs" - if it has otghs_control mailbox register as on OMAP4.
31427 + "ti,control-phy-usb2" - if it has Power down bit in control_dev_conf register
31428 + e.g. USB2_PHY on OMAP5.
31429 + "ti,control-phy-pipe3" - if it has DPLL and individual Rx & Tx power control
31430 + e.g. USB3 PHY and SATA PHY on OMAP5.
31431 + "ti,control-phy-dra7usb2" - if it has power down register like USB2 PHY on
31432 + DRA7 platform.
31433 + "ti,control-phy-am437usb2" - if it has power down register like USB2 PHY on
31434 + AM437 platform.
31435 + - reg : Address and length of the register set for the device. It contains
31436 + the address of "otghs_control" for control-phy-otghs or "power" register
31437 + for other types.
31438 + - reg-names: should be "otghs_control" control-phy-otghs and "power" for
31439 + other types.
31440 +
31441 +omap_control_otghs: omap-control-phy@4a002300 {
31442 + compatible = "ti,control-phy-otghs";
31443 + reg = <0x4a00233c 0x4>;
31444 + reg-names = "otghs_control";
31445 +};
31446 +
31447 +OMAP USB2 PHY
31448 +
31449 +Required properties:
31450 + - compatible: Should be either of
31451 + * "ti,omap-usb2" for OMAP4,OMAP5,DRA7
31452 + * "ti,am437x-usb2" for AM437x
31453 + - reg : Address and length of the register set for the device.
31454 + - #phy-cells: determine the number of cells that should be given in the
31455 + phandle while referencing this phy.
31456 +
31457 +Optional properties:
31458 + - ctrl-module : phandle of the control module used by PHY driver to power on
31459 + the PHY.
31460 +
31461 +This is usually a subnode of ocp2scp to which it is connected.
31462 +
31463 +usb2phy@4a0ad080 {
31464 + compatible = "ti,omap-usb2";
31465 + reg = <0x4a0ad080 0x58>;
31466 + ctrl-module = <&omap_control_usb>;
31467 + #phy-cells = <0>;
31468 +};
31469 +
31470 +OMAP PIPE3 PHY
31471 +
31472 +Required properties:
31473 + - compatible: Should be "ti,phy-pipe3-usb3" or "ti,phy-pipe3-sata"
31474 + - reg : Address and length of the register set for the device.
31475 + - reg-names: The names of the register addresses corresponding to the registers
31476 + filled in "reg".
31477 + - #phy-cells: determine the number of cells that should be given in the
31478 + phandle while referencing this phy.
31479 + - clocks: phandle to PHY clocks i.e. 32KHz wakup clock, 960MHz clock and lfps clock.
31480 + Use as per Documentation/devicetree/bindings/clock/clock-bindings.txt
31481 + - clock-names: should contain "wkupclk", "refclk1" and "refclk2"
31482 +
31483 +Optional properties:
31484 + - ctrl-module : phandle of the control module used by PHY driver to power on
31485 + the PHY.
31486 +
31487 +This is usually a subnode of ocp2scp to which it is connected.
31488 +
31489 +usb3phy@4a084400 {
31490 + compatible = "ti,omap-usb3";
31491 + reg = <0x4a084400 0x80>,
31492 + <0x4a084800 0x64>,
31493 + <0x4a084c00 0x40>;
31494 + reg-names = "phy_rx", "phy_tx", "pll_ctrl";
31495 + ctrl-module = <&omap_control_usb>;
31496 + #phy-cells = <0>;
31497 +};
31498 --- /dev/null
31499 +++ b/Documentation/devicetree/bindings/phy/phy-bindings.txt
31500 @@ -0,0 +1,66 @@
31501 +This document explains only the device tree data binding. For general
31502 +information about PHY subsystem refer to Documentation/phy.txt
31503 +
31504 +PHY device node
31505 +===============
31506 +
31507 +Required Properties:
31508 +#phy-cells: Number of cells in a PHY specifier; The meaning of all those
31509 + cells is defined by the binding for the phy node. The PHY
31510 + provider can use the values in cells to find the appropriate
31511 + PHY.
31512 +
31513 +For example:
31514 +
31515 +phys: phy {
31516 + compatible = "xxx";
31517 + reg = <...>;
31518 + .
31519 + .
31520 + #phy-cells = <1>;
31521 + .
31522 + .
31523 +};
31524 +
31525 +That node describes an IP block (PHY provider) that implements 2 different PHYs.
31526 +In order to differentiate between these 2 PHYs, an additonal specifier should be
31527 +given while trying to get a reference to it.
31528 +
31529 +PHY user node
31530 +=============
31531 +
31532 +Required Properties:
31533 +phys : the phandle for the PHY device (used by the PHY subsystem)
31534 +phy-names : the names of the PHY corresponding to the PHYs present in the
31535 + *phys* phandle
31536 +
31537 +Example 1:
31538 +usb1: usb_otg_ss@xxx {
31539 + compatible = "xxx";
31540 + reg = <xxx>;
31541 + .
31542 + .
31543 + phys = <&usb2_phy>, <&usb3_phy>;
31544 + phy-names = "usb2phy", "usb3phy";
31545 + .
31546 + .
31547 +};
31548 +
31549 +This node represents a controller that uses two PHYs, one for usb2 and one for
31550 +usb3.
31551 +
31552 +Example 2:
31553 +usb2: usb_otg_ss@xxx {
31554 + compatible = "xxx";
31555 + reg = <xxx>;
31556 + .
31557 + .
31558 + phys = <&phys 1>;
31559 + phy-names = "usbphy";
31560 + .
31561 + .
31562 +};
31563 +
31564 +This node represents a controller that uses one of the PHYs of the PHY provider
31565 +device defined previously. Note that the phy handle has an additional specifier
31566 +"1" to differentiate between the two PHYs.
31567 --- /dev/null
31568 +++ b/Documentation/devicetree/bindings/regulator/ti-avs-class0.txt
31569 @@ -0,0 +1,66 @@
31570 +Texas Instrument SmartReflex AVS Class 0 Regulator
31571 +
31572 +Required properties:
31573 +- compatible: "ti,avsclass0"
31574 +- reg: Should contain Efuse registers location and length
31575 +- avs-supply: The supply for AVS block
31576 +- efuse-settings: An array of 2-tuples items, and each item consists
31577 + of Voltage index and efuse offset(from reg) like: <voltage offset>
31578 + voltage: Voltage index in microvolts (also called nominal voltage)
31579 + offset: ofset in bytes from base provided in reg
31580 + NOTE: min_uV, max_uV are pickedup from this list
31581 +
31582 +Optional properties:
31583 +- voltage-tolerance: Specify the voltage tolerance in percentage
31584 +- ti,avsclass0-microvolt-values: Boolean property indicating that the efuse
31585 + values are in microvolts
31586 +
31587 +Example #1: single rails:
31588 +soc.dtsi:
31589 +avs_mpu: regulator-avs@0x40200000 {
31590 + compatible = "ti,avsclass0";
31591 + reg = <0x40200000 0x20>;
31592 + efuse-settings = <975000 0
31593 + 1075000 4
31594 + 1200000 8>;
31595 +};
31596 +
31597 +avs_core: regulator-avs@0x40300000 {
31598 + compatible = "ti,avsclass0";
31599 + reg = <0x40300000 0x20>;
31600 + efuse-settings = <975000 0
31601 + 1050000 4>;
31602 +};
31603 +
31604 +board.dtsi:
31605 +&avs_mpu {
31606 + avs-supply = <&vcc>;
31607 +};
31608 +&avs_core {
31609 + avs-supply = <&smps2>;
31610 +};
31611 +
31612 +Example #2: Ganged (combined) rails:
31613 +soc.dtsi:
31614 +avs_mpu: regulator-avs@0x40200000 {
31615 + compatible = "ti,avsclass0";
31616 + reg = <0x40200000 0x20>;
31617 + efuse-settings = <975000 0
31618 + 1075000 4
31619 + 1200000 8>;
31620 +};
31621 +
31622 +avs_core: regulator-avs@0x40300000 {
31623 + compatible = "ti,avsclass0";
31624 + reg = <0x40300000 0x20>;
31625 + efuse-settings = <975000 0
31626 + 1050000 4>;
31627 +};
31628 +
31629 +board.dtsi:
31630 +&avs_mpu {
31631 + avs-supply = <&smps3>;
31632 +};
31633 +&avs_core {
31634 + avs-supply = <&smps3>;
31635 +};
31636 --- /dev/null
31637 +++ b/Documentation/devicetree/bindings/regulator/tps65218.txt
31638 @@ -0,0 +1,22 @@
31639 +TPS65218 family of regulators
31640 +
31641 +Required properties:
31642 +For tps65218 regulators/LDOs
31643 +- compatible:
31644 + - "ti,tps65218-dcdc1" for DCDC1
31645 + - "ti,tps65218-dcdc2" for DCDC2
31646 + - "ti,tps65218-dcdc3" for DCDC3
31647 + - "ti,tps65218-dcdc4" for DCDC4
31648 + - "ti,tps65218-dcdc5" for DCDC5
31649 + - "ti,tps65218-dcdc6" for DCDC6
31650 + - "ti,tps65218-ldo1" for LDO1 LDO
31651 +
31652 +Optional properties:
31653 +- Any optional property defined in bindings/regulator/regulator.txt
31654 +
31655 +Example:
31656 + xyz: regulator@0 {
31657 + compatible = "ti,tps65218-dcdc1";
31658 + regulator-min-microvolt = <1000000>;
31659 + regulator-max-microvolt = <3000000>;
31660 + };
31661 --- /dev/null
31662 +++ b/Documentation/devicetree/bindings/sound/davinci-evm-audio.txt
31663 @@ -0,0 +1,58 @@
31664 +* Texas Instruments SoC audio setups with TLV320AIC3X Codec
31665 +
31666 +Required properties:
31667 +- compatible : "ti,da830-evm-audio" : forDM365/DA8xx/OMAPL1x/AM33xx
31668 +- ti,model : The user-visible name of this sound complex.
31669 +- ti,audio-codec : The phandle of the TLV320AIC3x audio codec
31670 +- ti,mcasp-controller : The phandle of the McASP controller
31671 +- ti,codec-clock-rate : The Codec Clock rate (in Hz) applied to the Codec
31672 +- ti,audio-routing : A list of the connections between audio components.
31673 + Each entry is a pair of strings, the first being the connection's sink,
31674 + the second being the connection's source. Valid names for sources and
31675 + sinks are the codec's pins, and the jacks on the board:
31676 +
31677 + TLV320AIC3X pins:
31678 +
31679 + * LLOUT
31680 + * RLOUT
31681 + * MONO_LOUT
31682 + * HPLOUT
31683 + * HPROUT
31684 + * HPLCOM
31685 + * HPRCOM
31686 + * MIC3L
31687 + * MIC3R
31688 + * LINE1L
31689 + * LINE2L
31690 + * LINE1R
31691 + * LINE2R
31692 +
31693 + Board connectors:
31694 +
31695 + * Headphone Jack
31696 + * Line Out
31697 + * Mic Jack
31698 + * Line In
31699 +
31700 +
31701 +Example:
31702 +
31703 +sound {
31704 + compatible = "ti,da830-evm-audio";
31705 + ti,model = "DA830 EVM";
31706 + ti,audio-codec = <&tlv320aic3x>;
31707 + ti,mcasp-controller = <&mcasp1>;
31708 + ti,codec-clock-rate = <12000000>;
31709 + ti,audio-routing =
31710 + "Headphone Jack", "HPLOUT",
31711 + "Headphone Jack", "HPROUT",
31712 + "Line Out", "LLOUT",
31713 + "Line Out", "RLOUT",
31714 + "MIC3L", "Mic Bias 2V",
31715 + "MIC3R", "Mic Bias 2V",
31716 + "Mic Bias 2V", "Mic Jack",
31717 + "LINE1L", "Line In",
31718 + "LINE2L", "Line In",
31719 + "LINE1R", "Line In",
31720 + "LINE2R", "Line In";
31721 +};
31722 --- a/Documentation/devicetree/bindings/sound/davinci-mcasp-audio.txt
31723 +++ b/Documentation/devicetree/bindings/sound/davinci-mcasp-audio.txt
31724 @@ -6,15 +6,21 @@ Required properties:
31725 "ti,da830-mcasp-audio" : for both DA830 & DA850 platforms
31726 "ti,omap2-mcasp-audio" : for OMAP2 platforms (TI81xx, AM33xx)
31727
31728 -- reg : Should contain McASP registers offset and length
31729 -- interrupts : Interrupt number for McASP
31730 +- reg : Should contain McASP registers address and length for mpu and
31731 + optionally for dma controller access.
31732 +- reg-names : The mandatory reg-range must be named "mpu" and the optional DMA
31733 + reg-range must be named "dma". For backward compatibility it is
31734 + good to keep "mpu" first in the list.
31735 - op-mode : I2S/DIT ops mode.
31736 - tdm-slots : Slots for TDM operation.
31737 -- num-serializer : Serializers used by McASP.
31738 -- serial-dir : A list of serializer pin mode. The list number should be equal
31739 - to "num-serializer" parameter. Each entry is a number indication
31740 - serializer pin direction. (0 - INACTIVE, 1 - TX, 2 - RX)
31741 -
31742 +- serial-dir : A list of serializer configuration. Each entry is a number
31743 + indication serializer pin direction.
31744 + (0 - INACTIVE, 1 - TX, 2 - RX)
31745 +- dmas: two element list of DMA controller phandles and DMA request line
31746 + ordered pairs.
31747 +- dma-names: identifier string for each DMA request line in the dmas property.
31748 + These strings correspond 1:1 with the ordered pairs in dmas. The dma
31749 + identifiers must be "rx" and "tx".
31750
31751 Optional properties:
31752
31753 @@ -23,6 +29,8 @@ Optional properties:
31754 - rx-num-evt : FIFO levels.
31755 - sram-size-playback : size of sram to be allocated during playback
31756 - sram-size-capture : size of sram to be allocated during capture
31757 +- interrupts : Interrupt numbers for McASP, currently not used by the driver
31758 +- interrupt-names : Known interrupt names are "tx" and "rx"
31759
31760 Example:
31761
31762 @@ -31,10 +39,11 @@ mcasp0: mcasp0@1d00000 {
31763 #address-cells = <1>;
31764 #size-cells = <0>;
31765 reg = <0x100000 0x3000>;
31766 + reg-names "mpu";
31767 interrupts = <82 83>;
31768 + interrupts-names = "tx", "rx";
31769 op-mode = <0>; /* MCASP_IIS_MODE */
31770 tdm-slots = <2>;
31771 - num-serializer = <16>;
31772 serial-dir = <
31773 0 0 0 0 /* 0: INACTIVE, 1: TX, 2: RX */
31774 0 0 0 0
31775 --- a/Documentation/devicetree/bindings/sound/tlv320aic3x.txt
31776 +++ b/Documentation/devicetree/bindings/sound/tlv320aic3x.txt
31777 @@ -24,10 +24,36 @@ Optional properties:
31778 3 - MICBIAS output is connected to AVDD,
31779 If this node is not mentioned or if the value is incorrect, then MicBias
31780 is powered down.
31781 +- AVDD-supply, IOVDD-supply, DRVDD-supply, DVDD-supply : power supplies for the
31782 + device as covered in Documentation/devicetree/bindings/regulator/regulator.txt
31783 +
31784 +CODEC output pins:
31785 + * LLOUT
31786 + * RLOUT
31787 + * MONO_LOUT
31788 + * HPLOUT
31789 + * HPROUT
31790 + * HPLCOM
31791 + * HPRCOM
31792 +
31793 +CODEC input pins:
31794 + * MIC3L
31795 + * MIC3R
31796 + * LINE1L
31797 + * LINE2L
31798 + * LINE1R
31799 + * LINE2R
31800 +
31801 +The pins can be used in referring sound node's audio-routing property.
31802
31803 Example:
31804
31805 tlv320aic3x: tlv320aic3x@1b {
31806 compatible = "ti,tlv320aic3x";
31807 reg = <0x1b>;
31808 +
31809 + AVDD-supply = <&regulator>;
31810 + IOVDD-supply = <&regulator>;
31811 + DRVDD-supply = <&regulator>;
31812 + DVDD-supply = <&regulator>;
31813 };
31814 --- a/Documentation/devicetree/bindings/spi/omap-spi.txt
31815 +++ b/Documentation/devicetree/bindings/spi/omap-spi.txt
31816 @@ -2,8 +2,8 @@ OMAP2+ McSPI device
31817
31818 Required properties:
31819 - compatible :
31820 - - "ti,omap2-spi" for OMAP2 & OMAP3.
31821 - - "ti,omap4-spi" for OMAP4+.
31822 + - "ti,omap2-mcspi" for OMAP2 & OMAP3.
31823 + - "ti,omap4-mcspi" for OMAP4+.
31824 - ti,spi-num-cs : Number of chipselect supported by the instance.
31825 - ti,hwmods: Name of the hwmod associated to the McSPI
31826 - ti,pindir-d0-out-d1-in: Select the D0 pin as output and D1 as
31827 --- a/Documentation/devicetree/bindings/usb/dwc3.txt
31828 +++ b/Documentation/devicetree/bindings/usb/dwc3.txt
31829 @@ -6,11 +6,13 @@ Required properties:
31830 - compatible: must be "snps,dwc3"
31831 - reg : Address and length of the register set for the device
31832 - interrupts: Interrupts used by the dwc3 controller.
31833 +
31834 +Optional properties:
31835 - usb-phy : array of phandle for the PHY device. The first element
31836 in the array is expected to be a handle to the USB2/HS PHY and
31837 the second element is expected to be a handle to the USB3/SS PHY
31838 -
31839 -Optional properties:
31840 + - phys: from the *Generic PHY* bindings
31841 + - phy-names: from the *Generic PHY* bindings
31842 - tx-fifo-resize: determines if the FIFO *has* to be reallocated.
31843
31844 This is usually a subnode to DWC3 glue to which it is connected.
31845 --- a/Documentation/devicetree/bindings/usb/omap-usb.txt
31846 +++ b/Documentation/devicetree/bindings/usb/omap-usb.txt
31847 @@ -3,9 +3,6 @@ OMAP GLUE AND OTHER OMAP SPECIFIC COMPON
31848 OMAP MUSB GLUE
31849 - compatible : Should be "ti,omap4-musb" or "ti,omap3-musb"
31850 - ti,hwmods : must be "usb_otg_hs"
31851 - - ti,has-mailbox : to specify that omap uses an external mailbox
31852 - (in control module) to communicate with the musb core during device connect
31853 - and disconnect.
31854 - multipoint : Should be "1" indicating the musb controller supports
31855 multipoint. This is a MUSB configuration-specific setting.
31856 - num-eps : Specifies the number of endpoints. This is also a
31857 @@ -19,6 +16,9 @@ OMAP MUSB GLUE
31858 - power : Should be "50". This signifies the controller can supply up to
31859 100mA when operating in host mode.
31860 - usb-phy : the phandle for the PHY device
31861 + - phys : the phandle for the PHY device (used by generic PHY framework)
31862 + - phy-names : the names of the PHY corresponding to the PHYs present in the
31863 + *phy* phandle.
31864
31865 Optional properties:
31866 - ctrl-module : phandle of the control module this glue uses to write to
31867 @@ -28,11 +28,12 @@ SOC specific device node entry
31868 usb_otg_hs: usb_otg_hs@4a0ab000 {
31869 compatible = "ti,omap4-musb";
31870 ti,hwmods = "usb_otg_hs";
31871 - ti,has-mailbox;
31872 multipoint = <1>;
31873 num-eps = <16>;
31874 ram-bits = <12>;
31875 ctrl-module = <&omap_control_usb>;
31876 + phys = <&usb2_phy>;
31877 + phy-names = "usb2-phy";
31878 };
31879
31880 Board specific device node entry
31881 @@ -74,26 +75,3 @@ omap_dwc3 {
31882 utmi-mode = <2>;
31883 ranges;
31884 };
31885 -
31886 -OMAP CONTROL USB
31887 -
31888 -Required properties:
31889 - - compatible: Should be "ti,omap-control-usb"
31890 - - reg : Address and length of the register set for the device. It contains
31891 - the address of "control_dev_conf" and "otghs_control" or "phy_power_usb"
31892 - depending upon omap4 or omap5.
31893 - - reg-names: The names of the register addresses corresponding to the registers
31894 - filled in "reg".
31895 - - ti,type: This is used to differentiate whether the control module has
31896 - usb mailbox or usb3 phy power. omap4 has usb mailbox in control module to
31897 - notify events to the musb core and omap5 has usb3 phy power register to
31898 - power on usb3 phy. Should be "1" if it has mailbox and "2" if it has usb3
31899 - phy power.
31900 -
31901 -omap_control_usb: omap-control-usb@4a002300 {
31902 - compatible = "ti,omap-control-usb";
31903 - reg = <0x4a002300 0x4>,
31904 - <0x4a00233c 0x4>;
31905 - reg-names = "control_dev_conf", "otghs_control";
31906 - ti,type = <1>;
31907 -};
31908 --- a/Documentation/devicetree/bindings/usb/usb-nop-xceiv.txt
31909 +++ b/Documentation/devicetree/bindings/usb/usb-nop-xceiv.txt
31910 @@ -15,7 +15,7 @@ Optional properties:
31911
31912 - vcc-supply: phandle to the regulator that provides RESET to the PHY.
31913
31914 -- reset-supply: phandle to the regulator that provides power to the PHY.
31915 +- reset-gpios: Should specify the GPIO for reset.
31916
31917 Example:
31918
31919 @@ -25,10 +25,9 @@ Example:
31920 clocks = <&osc 0>;
31921 clock-names = "main_clk";
31922 vcc-supply = <&hsusb1_vcc_regulator>;
31923 - reset-supply = <&hsusb1_reset_regulator>;
31924 + reset-gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
31925 };
31926
31927 hsusb1_phy is a NOP USB PHY device that gets its clock from an oscillator
31928 and expects that clock to be configured to 19.2MHz by the NOP PHY driver.
31929 -hsusb1_vcc_regulator provides power to the PHY and hsusb1_reset_regulator
31930 -controls RESET.
31931 +hsusb1_vcc_regulator provides power to the PHY and GPIO 7 controls RESET.
31932 --- a/Documentation/devicetree/bindings/usb/usb-phy.txt
31933 +++ /dev/null
31934 @@ -1,42 +0,0 @@
31935 -USB PHY
31936 -
31937 -OMAP USB2 PHY
31938 -
31939 -Required properties:
31940 - - compatible: Should be "ti,omap-usb2"
31941 - - reg : Address and length of the register set for the device.
31942 -
31943 -Optional properties:
31944 - - ctrl-module : phandle of the control module used by PHY driver to power on
31945 - the PHY.
31946 -
31947 -This is usually a subnode of ocp2scp to which it is connected.
31948 -
31949 -usb2phy@4a0ad080 {
31950 - compatible = "ti,omap-usb2";
31951 - reg = <0x4a0ad080 0x58>;
31952 - ctrl-module = <&omap_control_usb>;
31953 -};
31954 -
31955 -OMAP USB3 PHY
31956 -
31957 -Required properties:
31958 - - compatible: Should be "ti,omap-usb3"
31959 - - reg : Address and length of the register set for the device.
31960 - - reg-names: The names of the register addresses corresponding to the registers
31961 - filled in "reg".
31962 -
31963 -Optional properties:
31964 - - ctrl-module : phandle of the control module used by PHY driver to power on
31965 - the PHY.
31966 -
31967 -This is usually a subnode of ocp2scp to which it is connected.
31968 -
31969 -usb3phy@4a084400 {
31970 - compatible = "ti,omap-usb3";
31971 - reg = <0x4a084400 0x80>,
31972 - <0x4a084800 0x64>,
31973 - <0x4a084c00 0x40>;
31974 - reg-names = "phy_rx", "phy_tx", "pll_ctrl";
31975 - ctrl-module = <&omap_control_usb>;
31976 -};
31977 --- /dev/null
31978 +++ b/Documentation/devicetree/bindings/video/da8xx-fb.txt
31979 @@ -0,0 +1,42 @@
31980 +TI LCD Controller on DA830/DA850/AM335x SoC's
31981 +
31982 +Required properties:
31983 +- compatible:
31984 + DA830, DA850 - "ti,da8xx-tilcdc"
31985 + AM335x SoC's - "ti,am33xx-tilcdc"
31986 +- reg: Address range of lcdc register set
31987 +- interrupts: lcdc interrupt
31988 +- display-timings: typical videomode of lcd panel, represented as child.
31989 + Refer Documentation/devicetree/bindings/video/display-timing.txt for
31990 + display timing binding details. If multiple videomodes are mentioned
31991 + in display timings node, typical videomode has to be mentioned as the
31992 + native mode or it has to be first child (driver cares only for native
31993 + videomode).
31994 +
31995 +Recommended properties:
31996 +- ti,hwmods: Name of the hwmod associated to the LCDC
31997 +
31998 +Example for am335x SoC's:
31999 +
32000 +lcdc@4830e000 {
32001 + compatible = "ti,am33xx-tilcdc";
32002 + reg = <0x4830e000 0x1000>;
32003 + interrupts = <36>;
32004 + ti,hwmods = "lcdc";
32005 + status = "okay";
32006 + display-timings {
32007 + 800x480p62 {
32008 + clock-frequency = <30000000>;
32009 + hactive = <800>;
32010 + vactive = <480>;
32011 + hfront-porch = <39>;
32012 + hback-porch = <39>;
32013 + hsync-len = <47>;
32014 + vback-porch = <29>;
32015 + vfront-porch = <13>;
32016 + vsync-len = <2>;
32017 + hsync-active = <1>;
32018 + vsync-active = <1>;
32019 + };
32020 + };
32021 +};
32022 --- /dev/null
32023 +++ b/Documentation/phy.txt
32024 @@ -0,0 +1,166 @@
32025 + PHY SUBSYSTEM
32026 + Kishon Vijay Abraham I <kishon@ti.com>
32027 +
32028 +This document explains the Generic PHY Framework along with the APIs provided,
32029 +and how-to-use.
32030 +
32031 +1. Introduction
32032 +
32033 +*PHY* is the abbreviation for physical layer. It is used to connect a device
32034 +to the physical medium e.g., the USB controller has a PHY to provide functions
32035 +such as serialization, de-serialization, encoding, decoding and is responsible
32036 +for obtaining the required data transmission rate. Note that some USB
32037 +controllers have PHY functionality embedded into it and others use an external
32038 +PHY. Other peripherals that use PHY include Wireless LAN, Ethernet,
32039 +SATA etc.
32040 +
32041 +The intention of creating this framework is to bring the PHY drivers spread
32042 +all over the Linux kernel to drivers/phy to increase code re-use and for
32043 +better code maintainability.
32044 +
32045 +This framework will be of use only to devices that use external PHY (PHY
32046 +functionality is not embedded within the controller).
32047 +
32048 +2. Registering/Unregistering the PHY provider
32049 +
32050 +PHY provider refers to an entity that implements one or more PHY instances.
32051 +For the simple case where the PHY provider implements only a single instance of
32052 +the PHY, the framework provides its own implementation of of_xlate in
32053 +of_phy_simple_xlate. If the PHY provider implements multiple instances, it
32054 +should provide its own implementation of of_xlate. of_xlate is used only for
32055 +dt boot case.
32056 +
32057 +#define of_phy_provider_register(dev, xlate) \
32058 + __of_phy_provider_register((dev), THIS_MODULE, (xlate))
32059 +
32060 +#define devm_of_phy_provider_register(dev, xlate) \
32061 + __devm_of_phy_provider_register((dev), THIS_MODULE, (xlate))
32062 +
32063 +of_phy_provider_register and devm_of_phy_provider_register macros can be used to
32064 +register the phy_provider and it takes device and of_xlate as
32065 +arguments. For the dt boot case, all PHY providers should use one of the above
32066 +2 macros to register the PHY provider.
32067 +
32068 +void devm_of_phy_provider_unregister(struct device *dev,
32069 + struct phy_provider *phy_provider);
32070 +void of_phy_provider_unregister(struct phy_provider *phy_provider);
32071 +
32072 +devm_of_phy_provider_unregister and of_phy_provider_unregister can be used to
32073 +unregister the PHY.
32074 +
32075 +3. Creating the PHY
32076 +
32077 +The PHY driver should create the PHY in order for other peripheral controllers
32078 +to make use of it. The PHY framework provides 2 APIs to create the PHY.
32079 +
32080 +struct phy *phy_create(struct device *dev, const struct phy_ops *ops,
32081 + struct phy_init_data *init_data);
32082 +struct phy *devm_phy_create(struct device *dev, const struct phy_ops *ops,
32083 + struct phy_init_data *init_data);
32084 +
32085 +The PHY drivers can use one of the above 2 APIs to create the PHY by passing
32086 +the device pointer, phy ops and init_data.
32087 +phy_ops is a set of function pointers for performing PHY operations such as
32088 +init, exit, power_on and power_off. *init_data* is mandatory to get a reference
32089 +to the PHY in the case of non-dt boot. See section *Board File Initialization*
32090 +on how init_data should be used.
32091 +
32092 +Inorder to dereference the private data (in phy_ops), the phy provider driver
32093 +can use phy_set_drvdata() after creating the PHY and use phy_get_drvdata() in
32094 +phy_ops to get back the private data.
32095 +
32096 +4. Getting a reference to the PHY
32097 +
32098 +Before the controller can make use of the PHY, it has to get a reference to
32099 +it. This framework provides the following APIs to get a reference to the PHY.
32100 +
32101 +struct phy *phy_get(struct device *dev, const char *string);
32102 +struct phy *devm_phy_get(struct device *dev, const char *string);
32103 +
32104 +phy_get and devm_phy_get can be used to get the PHY. In the case of dt boot,
32105 +the string arguments should contain the phy name as given in the dt data and
32106 +in the case of non-dt boot, it should contain the label of the PHY.
32107 +The only difference between the two APIs is that devm_phy_get associates the
32108 +device with the PHY using devres on successful PHY get. On driver detach,
32109 +release function is invoked on the the devres data and devres data is freed.
32110 +
32111 +5. Releasing a reference to the PHY
32112 +
32113 +When the controller no longer needs the PHY, it has to release the reference
32114 +to the PHY it has obtained using the APIs mentioned in the above section. The
32115 +PHY framework provides 2 APIs to release a reference to the PHY.
32116 +
32117 +void phy_put(struct phy *phy);
32118 +void devm_phy_put(struct device *dev, struct phy *phy);
32119 +
32120 +Both these APIs are used to release a reference to the PHY and devm_phy_put
32121 +destroys the devres associated with this PHY.
32122 +
32123 +6. Destroying the PHY
32124 +
32125 +When the driver that created the PHY is unloaded, it should destroy the PHY it
32126 +created using one of the following 2 APIs.
32127 +
32128 +void phy_destroy(struct phy *phy);
32129 +void devm_phy_destroy(struct device *dev, struct phy *phy);
32130 +
32131 +Both these APIs destroy the PHY and devm_phy_destroy destroys the devres
32132 +associated with this PHY.
32133 +
32134 +7. PM Runtime
32135 +
32136 +This subsystem is pm runtime enabled. So while creating the PHY,
32137 +pm_runtime_enable of the phy device created by this subsystem is called and
32138 +while destroying the PHY, pm_runtime_disable is called. Note that the phy
32139 +device created by this subsystem will be a child of the device that calls
32140 +phy_create (PHY provider device).
32141 +
32142 +So pm_runtime_get_sync of the phy_device created by this subsystem will invoke
32143 +pm_runtime_get_sync of PHY provider device because of parent-child relationship.
32144 +It should also be noted that phy_power_on and phy_power_off performs
32145 +phy_pm_runtime_get_sync and phy_pm_runtime_put respectively.
32146 +There are exported APIs like phy_pm_runtime_get, phy_pm_runtime_get_sync,
32147 +phy_pm_runtime_put, phy_pm_runtime_put_sync, phy_pm_runtime_allow and
32148 +phy_pm_runtime_forbid for performing PM operations.
32149 +
32150 +8. Board File Initialization
32151 +
32152 +Certain board file initialization is necessary in order to get a reference
32153 +to the PHY in the case of non-dt boot.
32154 +Say we have a single device that implements 3 PHYs that of USB, SATA and PCIe,
32155 +then in the board file the following initialization should be done.
32156 +
32157 +struct phy_consumer consumers[] = {
32158 + PHY_CONSUMER("dwc3.0", "usb"),
32159 + PHY_CONSUMER("pcie.0", "pcie"),
32160 + PHY_CONSUMER("sata.0", "sata"),
32161 +};
32162 +PHY_CONSUMER takes 2 parameters, first is the device name of the controller
32163 +(PHY consumer) and second is the port name.
32164 +
32165 +struct phy_init_data init_data = {
32166 + .consumers = consumers,
32167 + .num_consumers = ARRAY_SIZE(consumers),
32168 +};
32169 +
32170 +static const struct platform_device pipe3_phy_dev = {
32171 + .name = "pipe3-phy",
32172 + .id = -1,
32173 + .dev = {
32174 + .platform_data = {
32175 + .init_data = &init_data,
32176 + },
32177 + },
32178 +};
32179 +
32180 +then, while doing phy_create, the PHY driver should pass this init_data
32181 + phy_create(dev, ops, pdata->init_data);
32182 +
32183 +and the controller driver (phy consumer) should pass the port name along with
32184 +the device to get a reference to the PHY
32185 + phy_get(dev, "pcie");
32186 +
32187 +9. DeviceTree Binding
32188 +
32189 +The documentation for PHY dt binding can be found @
32190 +Documentation/devicetree/bindings/phy/phy-bindings.txt
32191 --- a/drivers/ata/ahci.h
32192 +++ b/drivers/ata/ahci.h
32193 @@ -322,6 +322,7 @@ struct ahci_host_priv {
32194 u32 em_buf_sz; /* EM buffer size in byte */
32195 u32 em_msg_type; /* EM message type */
32196 struct clk *clk; /* Only for platforms supporting clk */
32197 + struct phy *phy; /* If platforms use phy */
32198 void *plat_data; /* Other platform data */
32199 };
32200
32201 --- a/drivers/ata/ahci_platform.c
32202 +++ b/drivers/ata/ahci_platform.c
32203 @@ -23,6 +23,7 @@
32204 #include <linux/platform_device.h>
32205 #include <linux/libata.h>
32206 #include <linux/ahci_platform.h>
32207 +#include <linux/phy/phy.h>
32208 #include "ahci.h"
32209
32210 static void ahci_host_stop(struct ata_host *host);
32211 @@ -141,16 +142,32 @@ static int ahci_probe(struct platform_de
32212 }
32213 }
32214
32215 + hpriv->phy = devm_phy_get(dev, "sata-phy");
32216 + if (IS_ERR(hpriv->phy)) {
32217 + dev_dbg(dev, "can't get sata-phy\n");
32218 + /* return only if -EPROBE_DEFER */
32219 + if (PTR_ERR(hpriv->phy) == -EPROBE_DEFER) {
32220 + rc = -EPROBE_DEFER;
32221 + goto disable_unprepare_clk;
32222 + }
32223 + }
32224 +
32225 + if (!IS_ERR(hpriv->phy)) {
32226 + phy_init(hpriv->phy);
32227 + phy_power_on(hpriv->phy);
32228 + }
32229 +
32230 /*
32231 * Some platforms might need to prepare for mmio region access,
32232 * which could be done in the following init call. So, the mmio
32233 * region shouldn't be accessed before init (if provided) has
32234 * returned successfully.
32235 */
32236 +
32237 if (pdata && pdata->init) {
32238 rc = pdata->init(dev, hpriv->mmio);
32239 if (rc)
32240 - goto disable_unprepare_clk;
32241 + goto disable_phy;
32242 }
32243
32244 ahci_save_initial_config(dev, hpriv,
32245 @@ -220,6 +237,12 @@ static int ahci_probe(struct platform_de
32246 pdata_exit:
32247 if (pdata && pdata->exit)
32248 pdata->exit(dev);
32249 +disable_phy:
32250 + if (!IS_ERR(hpriv->phy)) {
32251 + phy_power_off(hpriv->phy);
32252 + phy_exit(hpriv->phy);
32253 + }
32254 +
32255 disable_unprepare_clk:
32256 if (!IS_ERR(hpriv->clk))
32257 clk_disable_unprepare(hpriv->clk);
32258 @@ -238,6 +261,11 @@ static void ahci_host_stop(struct ata_ho
32259 if (pdata && pdata->exit)
32260 pdata->exit(dev);
32261
32262 + if (!IS_ERR(hpriv->phy)) {
32263 + phy_power_off(hpriv->phy);
32264 + phy_exit(hpriv->phy);
32265 + }
32266 +
32267 if (!IS_ERR(hpriv->clk)) {
32268 clk_disable_unprepare(hpriv->clk);
32269 clk_put(hpriv->clk);
32270 @@ -328,6 +356,7 @@ static SIMPLE_DEV_PM_OPS(ahci_pm_ops, ah
32271 static const struct of_device_id ahci_of_match[] = {
32272 { .compatible = "snps,spear-ahci", },
32273 { .compatible = "snps,exynos5440-ahci", },
32274 + { .compatible = "snps,dwc-ahci", },
32275 {},
32276 };
32277 MODULE_DEVICE_TABLE(of, ahci_of_match);
32278 --- a/drivers/ata/Kconfig
32279 +++ b/drivers/ata/Kconfig
32280 @@ -137,6 +137,13 @@ config SATA_SIL24
32281
32282 If unsure, say N.
32283
32284 +config SATA_TI
32285 + tristate "Texas Instruments SATA Wrapper driver"
32286 + depends on ARCH_OMAP
32287 + help
32288 + This options enables SATA Wrapper driver for Texas Instruments SoCs.
32289 + It is found on OMAP5 and DRA7.
32290 +
32291 config ATA_SFF
32292 bool "ATA SFF support (for legacy IDE and PATA)"
32293 default y
32294 --- a/drivers/ata/Makefile
32295 +++ b/drivers/ata/Makefile
32296 @@ -11,6 +11,7 @@ obj-$(CONFIG_SATA_SIL24) += sata_sil24.o
32297 obj-$(CONFIG_SATA_DWC) += sata_dwc_460ex.o
32298 obj-$(CONFIG_SATA_HIGHBANK) += sata_highbank.o libahci.o
32299 obj-$(CONFIG_AHCI_IMX) += ahci_imx.o
32300 +obj-$(CONFIG_SATA_TI) += sata_ti.o
32301
32302 # SFF w/ custom DMA
32303 obj-$(CONFIG_PDC_ADMA) += pdc_adma.o
32304 --- /dev/null
32305 +++ b/drivers/ata/sata_ti.c
32306 @@ -0,0 +1,160 @@
32307 +/**
32308 + * sata-ti.c - Texas Instruments Specific SATA Glue layer
32309 + *
32310 + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
32311 + *
32312 + * Authors: Roger Quadros <rogerq@ti.com>
32313 + *
32314 + * This program is free software: you can redistribute it and/or modify
32315 + * it under the terms of the GNU General Public License version 2 of
32316 + * the License as published by the Free Software Foundation.
32317 + *
32318 + * This program is distributed in the hope that it will be useful,
32319 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
32320 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
32321 + * GNU General Public License for more details.
32322 + */
32323 +
32324 +#include <linux/module.h>
32325 +#include <linux/kernel.h>
32326 +#include <linux/slab.h>
32327 +#include <linux/platform_device.h>
32328 +#include <linux/ioport.h>
32329 +#include <linux/io.h>
32330 +#include <linux/pm_runtime.h>
32331 +#include <linux/of.h>
32332 +#include <linux/of_platform.h>
32333 +
32334 +/*
32335 + * All these registers belong to OMAP's Wrapper around the
32336 + * DesignWare SATA Core.
32337 + */
32338 +
32339 +#define SATA_SYSCONFIG 0x0000
32340 +#define SATA_CDRLOCK 0x0004
32341 +
32342 +struct ti_sata {
32343 + struct device *dev;
32344 + void __iomem *base;
32345 +};
32346 +
32347 +static int ti_sata_probe(struct platform_device *pdev)
32348 +{
32349 + struct device_node *np = pdev->dev.of_node;
32350 + struct device *dev = &pdev->dev;
32351 + struct ti_sata *sata;
32352 + struct resource *res;
32353 + void __iomem *base;
32354 + int ret;
32355 +
32356 + if (!np) {
32357 + dev_err(dev, "device node not found\n");
32358 + return -EINVAL;
32359 + }
32360 +
32361 + sata = devm_kzalloc(dev, sizeof(*sata), GFP_KERNEL);
32362 + if (!sata)
32363 + return -ENOMEM;
32364 +
32365 + platform_set_drvdata(pdev, sata);
32366 +
32367 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
32368 + if (!res) {
32369 + dev_err(dev, "missing memory base resource\n");
32370 + return -EINVAL;
32371 + }
32372 +
32373 + base = devm_ioremap_resource(dev, res);
32374 + if (IS_ERR(base))
32375 + return PTR_ERR(base);
32376 +
32377 + sata->dev = dev;
32378 + sata->base = base;
32379 +
32380 + pm_runtime_enable(dev);
32381 + ret = pm_runtime_get_sync(dev);
32382 + if (ret < 0) {
32383 + dev_err(dev, "pm_runtime_get_sync failed with err %d\n",
32384 + ret);
32385 + goto runtime_disable;
32386 + }
32387 +
32388 + ret = of_platform_populate(np, NULL, NULL, dev);
32389 + if (ret) {
32390 + dev_err(&pdev->dev, "failed to create TI SATA children\n");
32391 + goto runtime_put;
32392 + }
32393 +
32394 + return 0;
32395 +
32396 +runtime_put:
32397 + pm_runtime_put_sync(dev);
32398 +
32399 +runtime_disable:
32400 + pm_runtime_disable(dev);
32401 +
32402 + return ret;
32403 +}
32404 +
32405 +static int ti_sata_remove_child(struct device *dev, void *c)
32406 +{
32407 + struct platform_device *pdev = to_platform_device(dev);
32408 +
32409 + platform_device_unregister(pdev);
32410 +
32411 + return 0;
32412 +}
32413 +
32414 +static int ti_sata_remove(struct platform_device *pdev)
32415 +{
32416 + pm_runtime_put_sync(&pdev->dev);
32417 + pm_runtime_disable(&pdev->dev);
32418 + device_for_each_child(&pdev->dev, NULL, ti_sata_remove_child);
32419 +
32420 + return 0;
32421 +}
32422 +
32423 +static const struct of_device_id of_ti_sata_match[] = {
32424 + {
32425 + .compatible = "ti,sata"
32426 + },
32427 + { },
32428 +};
32429 +MODULE_DEVICE_TABLE(of, of_ti_sata_match);
32430 +
32431 +#ifdef CONFIG_PM
32432 +
32433 +static int ti_sata_resume(struct device *dev)
32434 +{
32435 + pm_runtime_disable(dev);
32436 + pm_runtime_set_active(dev);
32437 + pm_runtime_enable(dev);
32438 +
32439 + return 0;
32440 +}
32441 +
32442 +static const struct dev_pm_ops ti_sata_dev_pm_ops = {
32443 + .resume = ti_sata_resume,
32444 +};
32445 +
32446 +#define DEV_PM_OPS (&ti_sata_dev_pm_ops)
32447 +#else
32448 +#define DEV_PM_OPS NULL
32449 +#endif /* CONFIG_PM */
32450 +
32451 +static struct platform_driver ti_sata_driver = {
32452 + .probe = ti_sata_probe,
32453 + .remove = ti_sata_remove,
32454 + .driver = {
32455 + .name = "ti-sata",
32456 + .of_match_table = of_ti_sata_match,
32457 + .pm = DEV_PM_OPS,
32458 + },
32459 +};
32460 +
32461 +module_platform_driver(ti_sata_driver);
32462 +
32463 +MODULE_ALIAS("platform:ti-sata");
32464 +MODULE_AUTHOR("Roger Quadros <rogerq@ti.com>");
32465 +MODULE_LICENSE("GPL v2");
32466 +MODULE_DESCRIPTION("TI SATA Glue Layer");
32467 --- a/drivers/clk/clk.c
32468 +++ b/drivers/clk/clk.c
32469 @@ -2196,6 +2196,12 @@ struct clk *of_clk_get_from_provider(str
32470 return clk;
32471 }
32472
32473 +int of_clk_get_parent_count(struct device_node *np)
32474 +{
32475 + return of_count_phandle_with_args(np, "clocks", "#clock-cells");
32476 +}
32477 +EXPORT_SYMBOL_GPL(of_clk_get_parent_count);
32478 +
32479 const char *of_clk_get_parent_name(struct device_node *np, int index)
32480 {
32481 struct of_phandle_args clkspec;
32482 --- a/drivers/clk/clk-divider.c
32483 +++ b/drivers/clk/clk-divider.c
32484 @@ -1,7 +1,7 @@
32485 /*
32486 * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
32487 * Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao@linaro.org>
32488 - * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
32489 + * Copyright (C) 2011-2013 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
32490 *
32491 * This program is free software; you can redistribute it and/or modify
32492 * it under the terms of the GNU General Public License version 2 as
32493 @@ -17,6 +17,8 @@
32494 #include <linux/err.h>
32495 #include <linux/string.h>
32496 #include <linux/log2.h>
32497 +#include <linux/of.h>
32498 +#include <linux/of_address.h>
32499
32500 /*
32501 * DOC: basic adjustable divider clock that cannot gate
32502 @@ -30,8 +32,6 @@
32503
32504 #define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
32505
32506 -#define div_mask(d) ((1 << ((d)->width)) - 1)
32507 -
32508 static unsigned int _get_table_maxdiv(const struct clk_div_table *table)
32509 {
32510 unsigned int maxdiv = 0;
32511 @@ -46,12 +46,12 @@ static unsigned int _get_table_maxdiv(co
32512 static unsigned int _get_maxdiv(struct clk_divider *divider)
32513 {
32514 if (divider->flags & CLK_DIVIDER_ONE_BASED)
32515 - return div_mask(divider);
32516 + return divider->mask;
32517 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
32518 - return 1 << div_mask(divider);
32519 + return 1 << divider->mask;
32520 if (divider->table)
32521 return _get_table_maxdiv(divider->table);
32522 - return div_mask(divider) + 1;
32523 + return divider->mask + 1;
32524 }
32525
32526 static unsigned int _get_table_div(const struct clk_div_table *table,
32527 @@ -105,7 +105,7 @@ static unsigned long clk_divider_recalc_
32528 unsigned int div, val;
32529
32530 val = clk_readl(divider->reg) >> divider->shift;
32531 - val &= div_mask(divider);
32532 + val &= divider->mask;
32533
32534 div = _get_div(divider, val);
32535 if (!div) {
32536 @@ -221,17 +221,17 @@ static int clk_divider_set_rate(struct c
32537 div = parent_rate / rate;
32538 value = _get_val(divider, div);
32539
32540 - if (value > div_mask(divider))
32541 - value = div_mask(divider);
32542 + if (value > divider->mask)
32543 + value = divider->mask;
32544
32545 if (divider->lock)
32546 spin_lock_irqsave(divider->lock, flags);
32547
32548 if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
32549 - val = div_mask(divider) << (divider->shift + 16);
32550 + val = divider->mask << (divider->shift + 16);
32551 } else {
32552 val = clk_readl(divider->reg);
32553 - val &= ~(div_mask(divider) << divider->shift);
32554 + val &= ~(divider->mask << divider->shift);
32555 }
32556 val |= value << divider->shift;
32557 clk_writel(val, divider->reg);
32558 @@ -251,7 +251,7 @@ EXPORT_SYMBOL_GPL(clk_divider_ops);
32559
32560 static struct clk *_register_divider(struct device *dev, const char *name,
32561 const char *parent_name, unsigned long flags,
32562 - void __iomem *reg, u8 shift, u8 width,
32563 + void __iomem *reg, u8 shift, u32 mask,
32564 u8 clk_divider_flags, const struct clk_div_table *table,
32565 spinlock_t *lock)
32566 {
32567 @@ -260,8 +260,9 @@ static struct clk *_register_divider(str
32568 struct clk_init_data init;
32569
32570 if (clk_divider_flags & CLK_DIVIDER_HIWORD_MASK) {
32571 - if (width + shift > 16) {
32572 - pr_warn("divider value exceeds LOWORD field\n");
32573 + if ((mask << shift) & 0xffff0000) {
32574 + pr_warn("%s: divider value exceeds LOWORD field\n",
32575 + __func__);
32576 return ERR_PTR(-EINVAL);
32577 }
32578 }
32579 @@ -282,7 +283,7 @@ static struct clk *_register_divider(str
32580 /* struct clk_divider assignments */
32581 div->reg = reg;
32582 div->shift = shift;
32583 - div->width = width;
32584 + div->mask = mask;
32585 div->flags = clk_divider_flags;
32586 div->lock = lock;
32587 div->hw.init = &init;
32588 @@ -315,7 +316,7 @@ struct clk *clk_register_divider(struct
32589 u8 clk_divider_flags, spinlock_t *lock)
32590 {
32591 return _register_divider(dev, name, parent_name, flags, reg, shift,
32592 - width, clk_divider_flags, NULL, lock);
32593 + ((1 << width) - 1), clk_divider_flags, NULL, lock);
32594 }
32595 EXPORT_SYMBOL_GPL(clk_register_divider);
32596
32597 @@ -340,6 +341,103 @@ struct clk *clk_register_divider_table(s
32598 spinlock_t *lock)
32599 {
32600 return _register_divider(dev, name, parent_name, flags, reg, shift,
32601 - width, clk_divider_flags, table, lock);
32602 + ((1 << width) - 1), clk_divider_flags, table, lock);
32603 }
32604 EXPORT_SYMBOL_GPL(clk_register_divider_table);
32605 +
32606 +#ifdef CONFIG_OF
32607 +struct clk_div_table *of_clk_get_div_table(struct device_node *node)
32608 +{
32609 + int i;
32610 + u32 table_size;
32611 + struct clk_div_table *table;
32612 + const __be32 *tablespec;
32613 + u32 val;
32614 +
32615 + tablespec = of_get_property(node, "table", &table_size);
32616 +
32617 + if (!tablespec)
32618 + return NULL;
32619 +
32620 + table_size /= sizeof(struct clk_div_table);
32621 +
32622 + table = kzalloc(sizeof(struct clk_div_table) * table_size, GFP_KERNEL);
32623 + if (!table) {
32624 + pr_err("%s: unable to allocate memory for %s table\n", __func__, node->name);
32625 + return NULL;
32626 + }
32627 +
32628 + for (i = 0; i < table_size; i++) {
32629 + of_property_read_u32_index(node, "table", i * 2, &val);
32630 + table[i].div = val;
32631 + of_property_read_u32_index(node, "table", i * 2 + 1, &val);
32632 + table[i].val = val;
32633 + }
32634 +
32635 + return table;
32636 +}
32637 +
32638 +/**
32639 + * of_divider_clk_setup() - Setup function for simple div rate clock
32640 + */
32641 +void of_divider_clk_setup(struct device_node *node)
32642 +{
32643 + struct clk *clk;
32644 + const char *clk_name = node->name;
32645 + void __iomem *reg;
32646 + const char *parent_name;
32647 + u8 clk_divider_flags = 0;
32648 + u32 mask = 0;
32649 + u32 shift = 0;
32650 + struct clk_div_table *table;
32651 + u32 flags = 0;
32652 +
32653 + of_property_read_string(node, "clock-output-names", &clk_name);
32654 +
32655 + parent_name = of_clk_get_parent_name(node, 0);
32656 +
32657 + reg = of_iomap(node, 0);
32658 + if (!reg) {
32659 + pr_err("%s: no memory mapped for property reg\n", __func__);
32660 + return;
32661 + }
32662 +
32663 + if (of_property_read_u32(node, "bit-mask", &mask)) {
32664 + pr_err("%s: missing bit-mask property for %s\n", __func__, node->name);
32665 + return;
32666 + }
32667 +
32668 + if (of_property_read_u32(node, "bit-shift", &shift)) {
32669 + shift = __ffs(mask);
32670 + pr_debug("%s: bit-shift property defaults to 0x%x for %s\n",
32671 + __func__, shift, node->name);
32672 + }
32673 +
32674 + if (of_property_read_bool(node, "index-starts-at-one"))
32675 + clk_divider_flags |= CLK_DIVIDER_ONE_BASED;
32676 +
32677 + if (of_property_read_bool(node, "index-power-of-two"))
32678 + clk_divider_flags |= CLK_DIVIDER_POWER_OF_TWO;
32679 +
32680 + if (of_property_read_bool(node, "index-allow-zero"))
32681 + clk_divider_flags |= CLK_DIVIDER_ALLOW_ZERO;
32682 +
32683 + if (of_property_read_bool(node, "hiword-mask"))
32684 + clk_divider_flags |= CLK_DIVIDER_HIWORD_MASK;
32685 +
32686 + if (of_property_read_bool(node, "set-rate-parent"))
32687 + flags |= CLK_SET_RATE_PARENT;
32688 +
32689 + table = of_clk_get_div_table(node);
32690 + if (IS_ERR(table))
32691 + return;
32692 +
32693 + clk = _register_divider(NULL, clk_name, parent_name, flags, reg, shift,
32694 + mask, clk_divider_flags, table, NULL);
32695 +
32696 + if (!IS_ERR(clk))
32697 + of_clk_add_provider(node, of_clk_src_simple_get, clk);
32698 +}
32699 +EXPORT_SYMBOL_GPL(of_divider_clk_setup);
32700 +CLK_OF_DECLARE(divider_clk, "divider-clock", of_divider_clk_setup);
32701 +#endif
32702 --- a/drivers/clk/clk-fixed-factor.c
32703 +++ b/drivers/clk/clk-fixed-factor.c
32704 @@ -109,6 +109,7 @@ void __init of_fixed_factor_clk_setup(st
32705 const char *clk_name = node->name;
32706 const char *parent_name;
32707 u32 div, mult;
32708 + u32 flags = 0;
32709
32710 if (of_property_read_u32(node, "clock-div", &div)) {
32711 pr_err("%s Fixed factor clock <%s> must have a clock-div property\n",
32712 @@ -125,7 +126,10 @@ void __init of_fixed_factor_clk_setup(st
32713 of_property_read_string(node, "clock-output-names", &clk_name);
32714 parent_name = of_clk_get_parent_name(node, 0);
32715
32716 - clk = clk_register_fixed_factor(NULL, clk_name, parent_name, 0,
32717 + if (of_property_read_bool(node, "set-rate-parent"))
32718 + flags |= CLK_SET_RATE_PARENT;
32719 +
32720 + clk = clk_register_fixed_factor(NULL, clk_name, parent_name, flags,
32721 mult, div);
32722 if (!IS_ERR(clk))
32723 of_clk_add_provider(node, of_clk_src_simple_get, clk);
32724 --- a/drivers/clk/clk-gate.c
32725 +++ b/drivers/clk/clk-gate.c
32726 @@ -15,6 +15,8 @@
32727 #include <linux/io.h>
32728 #include <linux/err.h>
32729 #include <linux/string.h>
32730 +#include <linux/of.h>
32731 +#include <linux/of_address.h>
32732
32733 /**
32734 * DOC: basic gatable clock which can gate and ungate it's ouput
32735 @@ -162,3 +164,52 @@ struct clk *clk_register_gate(struct dev
32736 return clk;
32737 }
32738 EXPORT_SYMBOL_GPL(clk_register_gate);
32739 +
32740 +#ifdef CONFIG_OF
32741 +/**
32742 + * of_gate_clk_setup() - Setup function for simple gate rate clock
32743 + */
32744 +void of_gate_clk_setup(struct device_node *node)
32745 +{
32746 + struct clk *clk;
32747 + const char *clk_name = node->name;
32748 + void __iomem *reg;
32749 + const char *parent_name;
32750 + u8 clk_gate_flags = 0;
32751 + u32 bit_idx = 0;
32752 + u32 flags = 0;
32753 +
32754 + of_property_read_string(node, "clock-output-names", &clk_name);
32755 +
32756 + parent_name = of_clk_get_parent_name(node, 0);
32757 +
32758 + reg = of_iomap(node, 0);
32759 + if (!reg) {
32760 + pr_err("%s: no memory mapped for property reg\n", __func__);
32761 + return;
32762 + }
32763 +
32764 + if (of_property_read_u32(node, "bit-shift", &bit_idx)) {
32765 + pr_err("%s: missing bit-shift property for %s\n",
32766 + __func__, node->name);
32767 + return;
32768 + }
32769 +
32770 + if (of_property_read_bool(node, "set-bit-to-disable"))
32771 + clk_gate_flags |= CLK_GATE_SET_TO_DISABLE;
32772 +
32773 + if (of_property_read_bool(node, "hiword-mask"))
32774 + clk_gate_flags |= CLK_GATE_HIWORD_MASK;
32775 +
32776 + if (of_property_read_bool(node, "set-rate-parent"))
32777 + flags |= CLK_SET_RATE_PARENT;
32778 +
32779 + clk = clk_register_gate(NULL, clk_name, parent_name, flags, reg,
32780 + bit_idx, clk_gate_flags, NULL);
32781 +
32782 + if (!IS_ERR(clk))
32783 + of_clk_add_provider(node, of_clk_src_simple_get, clk);
32784 +}
32785 +EXPORT_SYMBOL_GPL(of_gate_clk_setup);
32786 +CLK_OF_DECLARE(gate_clk, "gate-clock", of_gate_clk_setup);
32787 +#endif
32788 --- a/drivers/clk/clk-mux.c
32789 +++ b/drivers/clk/clk-mux.c
32790 @@ -1,7 +1,7 @@
32791 /*
32792 * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
32793 * Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao@linaro.org>
32794 - * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
32795 + * Copyright (C) 2011-2013 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
32796 *
32797 * This program is free software; you can redistribute it and/or modify
32798 * it under the terms of the GNU General Public License version 2 as
32799 @@ -16,6 +16,8 @@
32800 #include <linux/slab.h>
32801 #include <linux/io.h>
32802 #include <linux/err.h>
32803 +#include <linux/of.h>
32804 +#include <linux/of_address.h>
32805
32806 /*
32807 * DOC: basic adjustable multiplexer clock that cannot gate
32808 @@ -177,3 +179,71 @@ struct clk *clk_register_mux(struct devi
32809 NULL, lock);
32810 }
32811 EXPORT_SYMBOL_GPL(clk_register_mux);
32812 +
32813 +#ifdef CONFIG_OF
32814 +/**
32815 + * of_mux_clk_setup() - Setup function for simple mux rate clock
32816 + */
32817 +void of_mux_clk_setup(struct device_node *node)
32818 +{
32819 + struct clk *clk;
32820 + const char *clk_name = node->name;
32821 + void __iomem *reg;
32822 + int num_parents;
32823 + const char **parent_names;
32824 + int i;
32825 + u8 clk_mux_flags = 0;
32826 + u32 mask = 0;
32827 + u32 shift = 0;
32828 + u32 flags = 0;
32829 +
32830 + of_property_read_string(node, "clock-output-names", &clk_name);
32831 +
32832 + num_parents = of_clk_get_parent_count(node);
32833 + if (num_parents < 1) {
32834 + pr_err("%s: mux-clock %s must have parent(s)\n",
32835 + __func__, node->name);
32836 + return;
32837 + }
32838 +
32839 + parent_names = kzalloc((sizeof(char*) * num_parents),
32840 + GFP_KERNEL);
32841 +
32842 + for (i = 0; i < num_parents; i++)
32843 + parent_names[i] = of_clk_get_parent_name(node, i);
32844 +
32845 + reg = of_iomap(node, 0);
32846 + if (!reg) {
32847 + pr_err("%s: no memory mapped for property reg\n", __func__);
32848 + return;
32849 + }
32850 +
32851 + if (of_property_read_u32(node, "bit-mask", &mask)) {
32852 + pr_err("%s: missing bit-mask property for %s\n", __func__, node->name);
32853 + return;
32854 + }
32855 +
32856 + if (of_property_read_u32(node, "bit-shift", &shift)) {
32857 + shift = __ffs(mask);
32858 + pr_debug("%s: bit-shift property defaults to 0x%x for %s\n",
32859 + __func__, shift, node->name);
32860 + }
32861 +
32862 + if (of_property_read_bool(node, "index-starts-at-one"))
32863 + clk_mux_flags |= CLK_MUX_INDEX_ONE;
32864 +
32865 + if (of_property_read_bool(node, "hiword-mask"))
32866 + clk_mux_flags |= CLK_MUX_HIWORD_MASK;
32867 +
32868 + if (of_property_read_bool(node, "set-rate-parent"))
32869 + flags |= CLK_SET_RATE_PARENT;
32870 +
32871 + clk = clk_register_mux_table(NULL, clk_name, parent_names, num_parents,
32872 + flags, reg, shift, mask, clk_mux_flags, NULL, NULL);
32873 +
32874 + if (!IS_ERR(clk))
32875 + of_clk_add_provider(node, of_clk_src_simple_get, clk);
32876 +}
32877 +EXPORT_SYMBOL_GPL(of_mux_clk_setup);
32878 +CLK_OF_DECLARE(mux_clk, "mux-clock", of_mux_clk_setup);
32879 +#endif
32880 --- /dev/null
32881 +++ b/drivers/clk/clk-palmas.c
32882 @@ -0,0 +1,305 @@
32883 +/*
32884 + * Clock driver for Palmas device.
32885 + *
32886 + * Copyright (c) 2013, NVIDIA Corporation.
32887 + *
32888 + * Author: Laxman Dewangan <ldewangan@nvidia.com>
32889 + *
32890 + * This program is free software; you can redistribute it and/or
32891 + * modify it under the terms of the GNU General Public License as
32892 + * published by the Free Software Foundation version 2.
32893 + *
32894 + * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind,
32895 + * whether express or implied; without even the implied warranty of
32896 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
32897 + * General Public License for more details.
32898 + *
32899 + * You should have received a copy of the GNU General Public License
32900 + * along with this program; if not, write to the Free Software
32901 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
32902 + * 02111-1307, USA
32903 + */
32904 +
32905 +#include <linux/clk.h>
32906 +#include <linux/clkdev.h>
32907 +#include <linux/clk-provider.h>
32908 +#include <linux/mfd/palmas.h>
32909 +#include <linux/module.h>
32910 +#include <linux/of.h>
32911 +#include <linux/of_device.h>
32912 +#include <linux/platform_device.h>
32913 +#include <linux/slab.h>
32914 +
32915 +#define PALMAS_CLOCK_DT_EXT_CONTROL_ENABLE1 1
32916 +#define PALMAS_CLOCK_DT_EXT_CONTROL_ENABLE2 2
32917 +#define PALMAS_CLOCK_DT_EXT_CONTROL_NSLEEP 3
32918 +
32919 +struct palmas_clk32k_desc {
32920 + const char *clk_name;
32921 + unsigned int control_reg;
32922 + unsigned int enable_mask;
32923 + unsigned int sleep_mask;
32924 + unsigned int sleep_reqstr_id;
32925 + int delay;
32926 +};
32927 +
32928 +struct palmas_clock_info {
32929 + struct device *dev;
32930 + struct clk *clk;
32931 + struct clk_hw hw;
32932 + struct palmas *palmas;
32933 + struct palmas_clk32k_desc *clk_desc;
32934 + int ext_control_pin;
32935 +};
32936 +
32937 +static inline struct palmas_clock_info *to_palmas_clks_info(struct clk_hw *hw)
32938 +{
32939 + return container_of(hw, struct palmas_clock_info, hw);
32940 +}
32941 +
32942 +static unsigned long palmas_clks_recalc_rate(struct clk_hw *hw,
32943 + unsigned long parent_rate)
32944 +{
32945 + return 32768;
32946 +}
32947 +
32948 +static int palmas_clks_prepare(struct clk_hw *hw)
32949 +{
32950 + struct palmas_clock_info *cinfo = to_palmas_clks_info(hw);
32951 + int ret;
32952 +
32953 + ret = palmas_update_bits(cinfo->palmas, PALMAS_RESOURCE_BASE,
32954 + cinfo->clk_desc->control_reg,
32955 + cinfo->clk_desc->enable_mask,
32956 + cinfo->clk_desc->enable_mask);
32957 + if (ret < 0)
32958 + dev_err(cinfo->dev, "Reg 0x%02x update failed, %d\n",
32959 + cinfo->clk_desc->control_reg, ret);
32960 + else if (cinfo->clk_desc->delay)
32961 + udelay(cinfo->clk_desc->delay);
32962 +
32963 + return ret;
32964 +}
32965 +
32966 +static void palmas_clks_unprepare(struct clk_hw *hw)
32967 +{
32968 + struct palmas_clock_info *cinfo = to_palmas_clks_info(hw);
32969 + int ret;
32970 +
32971 + /*
32972 + * Clock can be disabled through external pin if it is externally
32973 + * controlled.
32974 + */
32975 + if (cinfo->ext_control_pin)
32976 + return;
32977 +
32978 + ret = palmas_update_bits(cinfo->palmas, PALMAS_RESOURCE_BASE,
32979 + cinfo->clk_desc->control_reg,
32980 + cinfo->clk_desc->enable_mask, 0);
32981 + if (ret < 0)
32982 + dev_err(cinfo->dev, "Reg 0x%02x update failed, %d\n",
32983 + cinfo->clk_desc->control_reg, ret);
32984 +
32985 +}
32986 +
32987 +static int palmas_clks_is_prepared(struct clk_hw *hw)
32988 +{
32989 + struct palmas_clock_info *cinfo = to_palmas_clks_info(hw);
32990 + int ret;
32991 + u32 val;
32992 +
32993 + if (cinfo->ext_control_pin)
32994 + return 1;
32995 +
32996 + ret = palmas_read(cinfo->palmas, PALMAS_RESOURCE_BASE,
32997 + cinfo->clk_desc->control_reg, &val);
32998 + if (ret < 0) {
32999 + dev_err(cinfo->dev, "Reg 0x%02x read failed, %d\n",
33000 + cinfo->clk_desc->control_reg, ret);
33001 + return ret;
33002 + }
33003 + return !!(val & cinfo->clk_desc->enable_mask);
33004 +}
33005 +
33006 +static struct clk_ops palmas_clks_ops = {
33007 + .prepare = palmas_clks_prepare,
33008 + .unprepare = palmas_clks_unprepare,
33009 + .is_prepared = palmas_clks_is_prepared,
33010 + .recalc_rate = palmas_clks_recalc_rate,
33011 +};
33012 +
33013 +struct palmas_clks_of_match {
33014 + struct clk_init_data init;
33015 + struct palmas_clk32k_desc desc;
33016 +};
33017 +
33018 +static struct palmas_clks_of_match palmas_of_clk32kg = {
33019 + .init = {
33020 + .name = "clk32kg",
33021 + .ops = &palmas_clks_ops,
33022 + .flags = CLK_IS_ROOT | CLK_IGNORE_UNUSED,
33023 + },
33024 + .desc = {
33025 + .clk_name = "clk32kg",
33026 + .control_reg = PALMAS_CLK32KG_CTRL,
33027 + .enable_mask = PALMAS_CLK32KG_CTRL_MODE_ACTIVE,
33028 + .sleep_mask = PALMAS_CLK32KG_CTRL_MODE_SLEEP,
33029 + .sleep_reqstr_id = PALMAS_EXTERNAL_REQSTR_ID_CLK32KG,
33030 + .delay = 200,
33031 + },
33032 +};
33033 +
33034 +static struct palmas_clks_of_match palmas_of_clk32kgaudio = {
33035 + .init = {
33036 + .name = "clk32kgaudio",
33037 + .ops = &palmas_clks_ops,
33038 + .flags = CLK_IS_ROOT | CLK_IGNORE_UNUSED,
33039 + },
33040 + .desc = {
33041 + .clk_name = "clk32kgaudio",
33042 + .control_reg = PALMAS_CLK32KGAUDIO_CTRL,
33043 + .enable_mask = PALMAS_CLK32KG_CTRL_MODE_ACTIVE,
33044 + .sleep_mask = PALMAS_CLK32KG_CTRL_MODE_SLEEP,
33045 + .sleep_reqstr_id = PALMAS_EXTERNAL_REQSTR_ID_CLK32KGAUDIO,
33046 + .delay = 200,
33047 + },
33048 +};
33049 +
33050 +static struct of_device_id of_palmas_clks_match_tbl[] = {
33051 + { .compatible = "ti,palmas-clk32kg", .data = &palmas_of_clk32kg, },
33052 + { .compatible = "ti,palmas-clk32kgaudio", .data = &palmas_of_clk32kgaudio, },
33053 + {},
33054 +};
33055 +MODULE_DEVICE_TABLE(of, of_palmas_clks_match_tbl);
33056 +
33057 +static void palmas_clks_get_clk_data(struct platform_device *pdev,
33058 + struct palmas_clock_info *cinfo)
33059 +{
33060 + struct device_node *node = pdev->dev.of_node;
33061 + unsigned int prop;
33062 + int ret;
33063 +
33064 + ret = of_property_read_u32(node, "ti,external-sleep-control",
33065 + &prop);
33066 + if (ret)
33067 + return;
33068 +
33069 + switch (prop) {
33070 + case PALMAS_CLOCK_DT_EXT_CONTROL_ENABLE1:
33071 + prop = PALMAS_EXT_CONTROL_ENABLE1;
33072 + break;
33073 + case PALMAS_CLOCK_DT_EXT_CONTROL_ENABLE2:
33074 + prop = PALMAS_EXT_CONTROL_ENABLE2;
33075 + break;
33076 + case PALMAS_CLOCK_DT_EXT_CONTROL_NSLEEP:
33077 + prop = PALMAS_EXT_CONTROL_NSLEEP;
33078 + break;
33079 + default:
33080 + dev_warn(&pdev->dev, "%s: Invalid ext control option: %u\n",
33081 + node->name, prop);
33082 + prop = 0;
33083 + break;
33084 + }
33085 + cinfo->ext_control_pin = prop;
33086 +}
33087 +
33088 +static int palmas_clks_init_configure(struct palmas_clock_info *cinfo)
33089 +{
33090 + int ret;
33091 +
33092 + ret = palmas_update_bits(cinfo->palmas, PALMAS_RESOURCE_BASE,
33093 + cinfo->clk_desc->control_reg,
33094 + cinfo->clk_desc->sleep_mask, 0);
33095 + if (ret < 0) {
33096 + dev_err(cinfo->dev, "Reg 0x%02x update failed, %d\n",
33097 + cinfo->clk_desc->control_reg, ret);
33098 + return ret;
33099 + }
33100 +
33101 + if (cinfo->ext_control_pin) {
33102 + ret = clk_prepare(cinfo->clk);
33103 + if (ret < 0) {
33104 + dev_err(cinfo->dev, "Clock prep failed, %d\n", ret);
33105 + return ret;
33106 + }
33107 +
33108 + ret = palmas_ext_control_req_config(cinfo->palmas,
33109 + cinfo->clk_desc->sleep_reqstr_id,
33110 + cinfo->ext_control_pin, true);
33111 + if (ret < 0) {
33112 + dev_err(cinfo->dev, "Ext config for %s failed, %d\n",
33113 + cinfo->clk_desc->clk_name, ret);
33114 + return ret;
33115 + }
33116 + }
33117 +
33118 + return ret;
33119 +}
33120 +static int palmas_clks_probe(struct platform_device *pdev)
33121 +{
33122 + struct palmas *palmas = dev_get_drvdata(pdev->dev.parent);
33123 + struct device_node *node = pdev->dev.of_node;
33124 + struct palmas_clks_of_match *match_data;
33125 + const struct of_device_id *match;
33126 + struct palmas_clock_info *cinfo;
33127 + struct clk *clk;
33128 + int ret;
33129 +
33130 + match = of_match_device(of_palmas_clks_match_tbl, &pdev->dev);
33131 + match_data = (struct palmas_clks_of_match *) match->data;
33132 +
33133 + cinfo = devm_kzalloc(&pdev->dev, sizeof(*cinfo), GFP_KERNEL);
33134 + if (!cinfo)
33135 + return -ENOMEM;
33136 +
33137 + palmas_clks_get_clk_data(pdev, cinfo);
33138 + platform_set_drvdata(pdev, cinfo);
33139 +
33140 + cinfo->dev = &pdev->dev;
33141 + cinfo->palmas = palmas;
33142 +
33143 + cinfo->clk_desc = &match_data->desc;
33144 + cinfo->hw.init = &match_data->init;
33145 + clk = devm_clk_register(&pdev->dev, &cinfo->hw);
33146 + if (IS_ERR(clk)) {
33147 + ret = PTR_ERR(clk);
33148 + dev_err(&pdev->dev, "Fail to register clock %s, %d\n",
33149 + match_data->desc.clk_name, ret);
33150 + return ret;
33151 + }
33152 +
33153 + cinfo->clk = clk;
33154 + ret = palmas_clks_init_configure(cinfo);
33155 + if (ret < 0) {
33156 + dev_err(&pdev->dev, "Clock config failed, %d\n", ret);
33157 + return ret;
33158 + }
33159 +
33160 + ret = of_clk_add_provider(node, of_clk_src_simple_get, cinfo->clk);
33161 + if (ret < 0)
33162 + dev_err(&pdev->dev, "Fail to add clock driver, %d\n", ret);
33163 + return ret;
33164 +}
33165 +
33166 +static int palmas_clks_remove(struct platform_device *pdev)
33167 +{
33168 + of_clk_del_provider(pdev->dev.of_node);
33169 + return 0;
33170 +}
33171 +
33172 +static struct platform_driver palmas_clks_driver = {
33173 + .driver = {
33174 + .name = "palmas-clk",
33175 + .owner = THIS_MODULE,
33176 + .of_match_table = of_palmas_clks_match_tbl,
33177 + },
33178 + .probe = palmas_clks_probe,
33179 + .remove = palmas_clks_remove,
33180 +};
33181 +
33182 +module_platform_driver(palmas_clks_driver);
33183 +
33184 +MODULE_DESCRIPTION("Clock driver for Palmas Series Devices");
33185 +MODULE_ALIAS("platform:palmas-clk");
33186 +MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
33187 +MODULE_LICENSE("GPL v2");
33188 --- a/drivers/clk/Kconfig
33189 +++ b/drivers/clk/Kconfig
33190 @@ -93,6 +93,13 @@ config CLK_PPC_CORENET
33191 This adds the clock driver support for Freescale PowerPC corenet
33192 platforms using common clock framework.
33193
33194 +config COMMON_CLK_PALMAS
33195 + bool "Clock driver for TI Palmas devices"
33196 + depends on MFD_PALMAS
33197 + ---help---
33198 + This driver supports TI Palmas devices 32KHz output KG and KG_AUDIO
33199 + using common clock framework.
33200 +
33201 endmenu
33202
33203 source "drivers/clk/mvebu/Kconfig"
33204 --- a/drivers/clk/Makefile
33205 +++ b/drivers/clk/Makefile
33206 @@ -32,6 +32,7 @@ obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.
33207 obj-$(CONFIG_ARCH_ZYNQ) += zynq/
33208 obj-$(CONFIG_ARCH_TEGRA) += tegra/
33209 obj-$(CONFIG_PLAT_SAMSUNG) += samsung/
33210 +obj-$(CONFIG_ARCH_OMAP) += ti/
33211
33212 obj-$(CONFIG_X86) += x86/
33213
33214 @@ -43,3 +44,4 @@ obj-$(CONFIG_COMMON_CLK_SI5351) += clk-s
33215 obj-$(CONFIG_COMMON_CLK_S2MPS11) += clk-s2mps11.o
33216 obj-$(CONFIG_CLK_TWL6040) += clk-twl6040.o
33217 obj-$(CONFIG_CLK_PPC_CORENET) += clk-ppc-corenet.o
33218 +obj-$(CONFIG_COMMON_CLK_PALMAS) += clk-palmas.o
33219 --- /dev/null
33220 +++ b/drivers/clk/ti/apll.c
33221 @@ -0,0 +1,212 @@
33222 +/*
33223 + * OMAP APLL clock support
33224 + *
33225 + * Copyright (C) 2013 Texas Instruments, Inc.
33226 + *
33227 + * J Keerthy <j-keerthy@ti.com>
33228 + *
33229 + * This program is free software; you can redistribute it and/or modify
33230 + * it under the terms of the GNU General Public License version 2 as
33231 + * published by the Free Software Foundation.
33232 + *
33233 + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
33234 + * kind, whether express or implied; without even the implied warranty
33235 + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
33236 + * GNU General Public License for more details.
33237 + */
33238 +
33239 +#include <linux/clk-provider.h>
33240 +#include <linux/module.h>
33241 +#include <linux/slab.h>
33242 +#include <linux/io.h>
33243 +#include <linux/err.h>
33244 +#include <linux/string.h>
33245 +#include <linux/log2.h>
33246 +#include <linux/of.h>
33247 +#include <linux/of_address.h>
33248 +#include <linux/clk/ti.h>
33249 +#include <linux/delay.h>
33250 +
33251 +#define APLL_FORCE_LOCK 0x1
33252 +#define APLL_AUTO_IDLE 0x2
33253 +#define MAX_APLL_WAIT_TRIES 1000000
33254 +
33255 +static int dra7_apll_enable(struct clk_hw *hw)
33256 +{
33257 + struct clk_hw_omap *clk = to_clk_hw_omap(hw);
33258 + int r = 0, i = 0;
33259 + struct dpll_data *ad;
33260 + const char *clk_name;
33261 + u8 state = 1;
33262 + u32 v;
33263 +
33264 + ad = clk->dpll_data;
33265 + if (!ad)
33266 + return -EINVAL;
33267 +
33268 + clk_name = __clk_get_name(clk->hw.clk);
33269 +
33270 + state <<= __ffs(ad->idlest_mask);
33271 +
33272 + /* Check is already locked */
33273 + if ((readl(ad->idlest_reg) & ad->idlest_mask) == state)
33274 + return r;
33275 +
33276 + v = readl(ad->control_reg);
33277 + v &= ~ad->enable_mask;
33278 + v |= APLL_FORCE_LOCK << __ffs(ad->enable_mask);
33279 + writel(v, ad->control_reg);
33280 +
33281 + state <<= __ffs(ad->idlest_mask);
33282 +
33283 + while (((readl(ad->idlest_reg) & ad->idlest_mask) != state) &&
33284 + i < MAX_APLL_WAIT_TRIES) {
33285 + i++;
33286 + udelay(1);
33287 + }
33288 +
33289 + if (i == MAX_APLL_WAIT_TRIES) {
33290 + pr_warn("clock: %s failed transition to '%s'\n",
33291 + clk_name, (state) ? "locked" : "bypassed");
33292 + } else {
33293 + pr_debug("clock: %s transition to '%s' in %d loops\n",
33294 + clk_name, (state) ? "locked" : "bypassed", i);
33295 +
33296 + r = 0;
33297 + }
33298 +
33299 + return r;
33300 +}
33301 +
33302 +static void dra7_apll_disable(struct clk_hw *hw)
33303 +{
33304 + struct clk_hw_omap *clk = to_clk_hw_omap(hw);
33305 + struct dpll_data *ad;
33306 + u8 state = 1;
33307 + u32 v;
33308 +
33309 + ad = clk->dpll_data;
33310 +
33311 + state <<= __ffs(ad->idlest_mask);
33312 +
33313 + v = readl(ad->control_reg);
33314 + v &= ~ad->enable_mask;
33315 + v |= APLL_AUTO_IDLE << __ffs(ad->enable_mask);
33316 + writel(v, ad->control_reg);
33317 +}
33318 +
33319 +static u8 dra7_init_apll_parent(struct clk_hw *hw)
33320 +{
33321 + return 0;
33322 +}
33323 +
33324 +static const struct clk_ops apll_ck_ops = {
33325 + .enable = &dra7_apll_enable,
33326 + .disable = &dra7_apll_disable,
33327 + .get_parent = &dra7_init_apll_parent,
33328 +};
33329 +
33330 +static struct clk *omap_clk_register_apll(struct device *dev, const char *name,
33331 + const char **parent_names, int num_parents, unsigned long flags,
33332 + struct dpll_data *dpll_data, const char *clkdm_name,
33333 + const struct clk_ops *ops)
33334 +{
33335 + struct clk *clk;
33336 + struct clk_init_data init = { 0 };
33337 + struct clk_hw_omap *clk_hw;
33338 +
33339 + clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
33340 + if (!clk_hw) {
33341 + pr_err("%s: could not allocate clk_hw_omap\n", __func__);
33342 + return ERR_PTR(-ENOMEM);
33343 + }
33344 +
33345 + clk_hw->dpll_data = dpll_data;
33346 + clk_hw->hw.init = &init;
33347 +
33348 + init.name = name;
33349 + init.ops = ops;
33350 + init.flags = flags;
33351 + init.parent_names = parent_names;
33352 + init.num_parents = num_parents;
33353 +
33354 + /* register the clock */
33355 + clk = clk_register(dev, &clk_hw->hw);
33356 +
33357 + return clk;
33358 +}
33359 +
33360 +void __init of_dra7_apll_setup(struct device_node *node)
33361 +{
33362 + const struct clk_ops *ops;
33363 + struct clk *clk;
33364 + const char *clk_name = node->name;
33365 + int num_parents;
33366 + const char **parent_names = NULL;
33367 + u8 apll_flags = 0;
33368 + struct dpll_data *ad;
33369 + u32 idlest_mask = 0x1;
33370 + u32 autoidle_mask = 0x3;
33371 + int i;
33372 +
33373 + ops = &apll_ck_ops;
33374 + ad = kzalloc(sizeof(*ad), GFP_KERNEL);
33375 + if (!ad) {
33376 + pr_err("%s: could not allocate dpll_data\n", __func__);
33377 + return;
33378 + }
33379 +
33380 + of_property_read_string(node, "clock-output-names", &clk_name);
33381 +
33382 + num_parents = of_clk_get_parent_count(node);
33383 + if (num_parents < 1) {
33384 + pr_err("%s: omap dpll %s must have parent(s)\n",
33385 + __func__, node->name);
33386 + goto cleanup;
33387 + }
33388 +
33389 + parent_names = kzalloc(sizeof(char *) * num_parents, GFP_KERNEL);
33390 +
33391 + for (i = 0; i < num_parents; i++)
33392 + parent_names[i] = of_clk_get_parent_name(node, i);
33393 +
33394 + ad->clk_ref = of_clk_get(node, 0);
33395 + ad->clk_bypass = of_clk_get(node, 1);
33396 +
33397 + if (IS_ERR(ad->clk_ref)) {
33398 + pr_err("%s: ti,clk-ref for %s not found\n", __func__,
33399 + clk_name);
33400 + goto cleanup;
33401 + }
33402 +
33403 + if (IS_ERR(ad->clk_bypass)) {
33404 + pr_err("%s: ti,clk-bypass for %s not found\n", __func__,
33405 + clk_name);
33406 + goto cleanup;
33407 + }
33408 +
33409 + i = of_property_match_string(node, "reg-names", "control");
33410 + if (i >= 0)
33411 + ad->control_reg = of_iomap(node, i);
33412 +
33413 + i = of_property_match_string(node, "reg-names", "idlest");
33414 + if (i >= 0)
33415 + ad->idlest_reg = of_iomap(node, i);
33416 +
33417 + ad->idlest_mask = idlest_mask;
33418 + ad->enable_mask = autoidle_mask;
33419 +
33420 + clk = omap_clk_register_apll(NULL, clk_name, parent_names,
33421 + num_parents, apll_flags, ad,
33422 + NULL, ops);
33423 +
33424 + if (!IS_ERR(clk))
33425 + of_clk_add_provider(node, of_clk_src_simple_get, clk);
33426 + return;
33427 +
33428 +cleanup:
33429 + kfree(parent_names);
33430 + kfree(ad);
33431 + return;
33432 +}
33433 +CLK_OF_DECLARE(dra7_apll_clock, "ti,dra7-apll-clock", of_dra7_apll_setup);
33434 --- /dev/null
33435 +++ b/drivers/clk/ti/autoidle.c
33436 @@ -0,0 +1,121 @@
33437 +/*
33438 + * OMAP clock autoidle support
33439 + *
33440 + * Copyright (C) 2013 Texas Instruments, Inc.
33441 + *
33442 + * Tero Kristo <t-kristo@ti.com>
33443 + *
33444 + * This program is free software; you can redistribute it and/or modify
33445 + * it under the terms of the GNU General Public License version 2 as
33446 + * published by the Free Software Foundation.
33447 + *
33448 + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
33449 + * kind, whether express or implied; without even the implied warranty
33450 + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
33451 + * GNU General Public License for more details.
33452 + */
33453 +
33454 +#include <linux/clk-provider.h>
33455 +#include <linux/slab.h>
33456 +#include <linux/io.h>
33457 +#include <linux/of.h>
33458 +#include <linux/of_address.h>
33459 +
33460 +struct clk_omap_autoidle {
33461 + void __iomem *reg;
33462 + u8 shift;
33463 + u8 flags;
33464 + const char *name;
33465 + struct list_head node;
33466 +};
33467 +
33468 +#define AUTOIDLE_LOW 0x1
33469 +
33470 +static LIST_HEAD(autoidle_clks);
33471 +
33472 +static void omap_allow_autoidle(struct clk_omap_autoidle *clk)
33473 +{
33474 + u32 val;
33475 +
33476 + val = readl(clk->reg);
33477 +
33478 + if (clk->flags & AUTOIDLE_LOW)
33479 + val &= ~(1 << clk->shift);
33480 + else
33481 + val |= (1 << clk->shift);
33482 +
33483 + writel(val, clk->reg);
33484 +}
33485 +
33486 +static void omap_deny_autoidle(struct clk_omap_autoidle *clk)
33487 +{
33488 + u32 val;
33489 +
33490 + val = readl(clk->reg);
33491 +
33492 + if (clk->flags & AUTOIDLE_LOW)
33493 + val |= (1 << clk->shift);
33494 + else
33495 + val &= ~(1 << clk->shift);
33496 +
33497 + writel(val, clk->reg);
33498 +}
33499 +
33500 +void of_omap_clk_allow_autoidle_all(void)
33501 +{
33502 + struct clk_omap_autoidle *c;
33503 +
33504 + list_for_each_entry(c, &autoidle_clks, node)
33505 + omap_allow_autoidle(c);
33506 +}
33507 +
33508 +void of_omap_clk_deny_autoidle_all(void)
33509 +{
33510 + struct clk_omap_autoidle *c;
33511 +
33512 + list_for_each_entry(c, &autoidle_clks, node)
33513 + omap_deny_autoidle(c);
33514 +}
33515 +
33516 +static void __init of_omap_autoidle_setup(struct device_node *node)
33517 +{
33518 + u32 shift;
33519 + void __iomem *reg;
33520 + struct clk_omap_autoidle *clk;
33521 +
33522 + if (of_property_read_u32(node, "ti,autoidle-shift", &shift))
33523 + return;
33524 +
33525 + reg = of_iomap(node, 0);
33526 +
33527 + clk = kzalloc(sizeof(*clk), GFP_KERNEL);
33528 +
33529 + if (!clk) {
33530 + pr_err("%s: kzalloc failed\n", __func__);
33531 + return;
33532 + }
33533 +
33534 + clk->shift = shift;
33535 + clk->name = node->name;
33536 + clk->reg = reg;
33537 +
33538 + if (of_property_read_bool(node, "ti,autoidle-low"))
33539 + clk->flags |= AUTOIDLE_LOW;
33540 +
33541 + list_add(&clk->node, &autoidle_clks);
33542 +}
33543 +
33544 +static void __init of_omap_divider_setup(struct device_node *node)
33545 +{
33546 + of_divider_clk_setup(node);
33547 + of_omap_autoidle_setup(node);
33548 +}
33549 +CLK_OF_DECLARE(omap_divider_clock, "ti,divider-clock", of_omap_divider_setup);
33550 +
33551 +static void __init of_omap_fixed_factor_setup(struct device_node *node)
33552 +{
33553 + of_fixed_factor_clk_setup(node);
33554 + of_omap_autoidle_setup(node);
33555 +}
33556 +CLK_OF_DECLARE(omap_fixed_factor_clock, "ti,fixed-factor-clock",
33557 + of_omap_fixed_factor_setup);
33558 --- /dev/null
33559 +++ b/drivers/clk/ti/clk-33xx.c
33560 @@ -0,0 +1,163 @@
33561 +/*
33562 + * AM33XX Clock init
33563 + *
33564 + * Copyright (C) 2013 Texas Instruments, Inc
33565 + * Tero Kristo (t-kristo@ti.com)
33566 + *
33567 + * This program is free software; you can redistribute it and/or
33568 + * modify it under the terms of the GNU General Public License as
33569 + * published by the Free Software Foundation version 2.
33570 + *
33571 + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
33572 + * kind, whether express or implied; without even the implied warranty
33573 + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
33574 + * GNU General Public License for more details.
33575 + */
33576 +
33577 +#include <linux/kernel.h>
33578 +#include <linux/list.h>
33579 +#include <linux/clk-provider.h>
33580 +#include <linux/clk/ti.h>
33581 +
33582 +static struct omap_dt_clk am33xx_clks[] = {
33583 + DT_CLK(NULL, "clk_32768_ck", "clk_32768_ck"),
33584 + DT_CLK(NULL, "clk_rc32k_ck", "clk_rc32k_ck"),
33585 + DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"),
33586 + DT_CLK(NULL, "virt_24000000_ck", "virt_24000000_ck"),
33587 + DT_CLK(NULL, "virt_25000000_ck", "virt_25000000_ck"),
33588 + DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"),
33589 + DT_CLK(NULL, "sys_clkin_ck", "sys_clkin_ck"),
33590 + DT_CLK(NULL, "tclkin_ck", "tclkin_ck"),
33591 + DT_CLK(NULL, "dpll_core_ck", "dpll_core_ck"),
33592 + DT_CLK(NULL, "dpll_core_x2_ck", "dpll_core_x2_ck"),
33593 + DT_CLK(NULL, "dpll_core_m4_ck", "dpll_core_m4_ck"),
33594 + DT_CLK(NULL, "dpll_core_m5_ck", "dpll_core_m5_ck"),
33595 + DT_CLK(NULL, "dpll_core_m6_ck", "dpll_core_m6_ck"),
33596 + DT_CLK(NULL, "dpll_mpu_ck", "dpll_mpu_ck"),
33597 + DT_CLK("cpu0", NULL, "dpll_mpu_ck"),
33598 + DT_CLK(NULL, "dpll_mpu_m2_ck", "dpll_mpu_m2_ck"),
33599 + DT_CLK(NULL, "dpll_ddr_ck", "dpll_ddr_ck"),
33600 + DT_CLK(NULL, "dpll_ddr_m2_ck", "dpll_ddr_m2_ck"),
33601 + DT_CLK(NULL, "dpll_ddr_m2_div2_ck", "dpll_ddr_m2_div2_ck"),
33602 + DT_CLK(NULL, "dpll_disp_ck", "dpll_disp_ck"),
33603 + DT_CLK(NULL, "dpll_disp_m2_ck", "dpll_disp_m2_ck"),
33604 + DT_CLK(NULL, "dpll_per_ck", "dpll_per_ck"),
33605 + DT_CLK(NULL, "dpll_per_m2_ck", "dpll_per_m2_ck"),
33606 + DT_CLK(NULL, "dpll_per_m2_div4_wkupdm_ck", "dpll_per_m2_div4_wkupdm_ck"),
33607 + DT_CLK(NULL, "dpll_per_m2_div4_ck", "dpll_per_m2_div4_ck"),
33608 + DT_CLK(NULL, "adc_tsc_fck", "adc_tsc_fck"),
33609 + DT_CLK(NULL, "cefuse_fck", "cefuse_fck"),
33610 + DT_CLK(NULL, "clkdiv32k_ck", "clkdiv32k_ck"),
33611 + DT_CLK(NULL, "clkdiv32k_ick", "clkdiv32k_ick"),
33612 + DT_CLK(NULL, "dcan0_fck", "dcan0_fck"),
33613 + DT_CLK("481cc000.d_can", NULL, "dcan0_fck"),
33614 + DT_CLK(NULL, "dcan1_fck", "dcan1_fck"),
33615 + DT_CLK("481d0000.d_can", NULL, "dcan1_fck"),
33616 + DT_CLK(NULL, "pruss_ocp_gclk", "pruss_ocp_gclk"),
33617 + DT_CLK(NULL, "mcasp0_fck", "mcasp0_fck"),
33618 + DT_CLK(NULL, "mcasp1_fck", "mcasp1_fck"),
33619 + DT_CLK(NULL, "mmu_fck", "mmu_fck"),
33620 + DT_CLK(NULL, "smartreflex0_fck", "smartreflex0_fck"),
33621 + DT_CLK(NULL, "smartreflex1_fck", "smartreflex1_fck"),
33622 + DT_CLK(NULL, "sha0_fck", "sha0_fck"),
33623 + DT_CLK(NULL, "rng_fck", "rng_fck"),
33624 + DT_CLK(NULL, "aes0_fck", "aes0_fck"),
33625 + DT_CLK(NULL, "timer1_fck", "timer1_fck"),
33626 + DT_CLK(NULL, "timer2_fck", "timer2_fck"),
33627 + DT_CLK(NULL, "timer3_fck", "timer3_fck"),
33628 + DT_CLK(NULL, "timer4_fck", "timer4_fck"),
33629 + DT_CLK(NULL, "timer5_fck", "timer5_fck"),
33630 + DT_CLK(NULL, "timer6_fck", "timer6_fck"),
33631 + DT_CLK(NULL, "timer7_fck", "timer7_fck"),
33632 + DT_CLK(NULL, "usbotg_fck", "usbotg_fck"),
33633 + DT_CLK(NULL, "ieee5000_fck", "ieee5000_fck"),
33634 + DT_CLK(NULL, "wdt1_fck", "wdt1_fck"),
33635 + DT_CLK(NULL, "l4_rtc_gclk", "l4_rtc_gclk"),
33636 + DT_CLK(NULL, "l3_gclk", "l3_gclk"),
33637 + DT_CLK(NULL, "dpll_core_m4_div2_ck", "dpll_core_m4_div2_ck"),
33638 + DT_CLK(NULL, "l4hs_gclk", "l4hs_gclk"),
33639 + DT_CLK(NULL, "l3s_gclk", "l3s_gclk"),
33640 + DT_CLK(NULL, "l4fw_gclk", "l4fw_gclk"),
33641 + DT_CLK(NULL, "l4ls_gclk", "l4ls_gclk"),
33642 + DT_CLK(NULL, "clk_24mhz", "clk_24mhz"),
33643 + DT_CLK(NULL, "sysclk_div_ck", "sysclk_div_ck"),
33644 + DT_CLK(NULL, "cpsw_125mhz_gclk", "cpsw_125mhz_gclk"),
33645 + DT_CLK(NULL, "cpsw_cpts_rft_clk", "cpsw_cpts_rft_clk"),
33646 + DT_CLK(NULL, "gpio0_dbclk_mux_ck", "gpio0_dbclk_mux_ck"),
33647 + DT_CLK(NULL, "gpio0_dbclk", "gpio0_dbclk"),
33648 + DT_CLK(NULL, "gpio1_dbclk", "gpio1_dbclk"),
33649 + DT_CLK(NULL, "gpio2_dbclk", "gpio2_dbclk"),
33650 + DT_CLK(NULL, "gpio3_dbclk", "gpio3_dbclk"),
33651 + DT_CLK(NULL, "lcd_gclk", "lcd_gclk"),
33652 + DT_CLK(NULL, "mmc_clk", "mmc_clk"),
33653 + DT_CLK(NULL, "gfx_fclk_clksel_ck", "gfx_fclk_clksel_ck"),
33654 + DT_CLK(NULL, "gfx_fck_div_ck", "gfx_fck_div_ck"),
33655 + DT_CLK(NULL, "sysclkout_pre_ck", "sysclkout_pre_ck"),
33656 + DT_CLK(NULL, "clkout2_div_ck", "clkout2_div_ck"),
33657 + DT_CLK(NULL, "timer_32k_ck", "clkdiv32k_ick"),
33658 + DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"),
33659 + DT_CLK(NULL, "dbg_sysclk_ck", "dbg_sysclk_ck"),
33660 + DT_CLK(NULL, "dbg_clka_ck", "dbg_clka_ck"),
33661 + DT_CLK(NULL, "stm_pmd_clock_mux_ck", "stm_pmd_clock_mux_ck"),
33662 + DT_CLK(NULL, "trace_pmd_clk_mux_ck", "trace_pmd_clk_mux_ck"),
33663 + DT_CLK(NULL, "stm_clk_div_ck", "stm_clk_div_ck"),
33664 + DT_CLK(NULL, "trace_clk_div_ck", "trace_clk_div_ck"),
33665 + DT_CLK(NULL, "clkout2_ck", "clkout2_ck"),
33666 + DT_CLK("48300200.ehrpwm", "tbclk", "ehrpwm0_tbclk"),
33667 + DT_CLK("48302200.ehrpwm", "tbclk", "ehrpwm1_tbclk"),
33668 + DT_CLK("48304200.ehrpwm", "tbclk", "ehrpwm2_tbclk"),
33669 + { .node_name = NULL },
33670 +};
33671 +
33672 +static const char *enable_init_clks[] = {
33673 + "dpll_ddr_m2_ck",
33674 + "dpll_mpu_m2_ck",
33675 + "l3_gclk",
33676 + "l4hs_gclk",
33677 + "l4fw_gclk",
33678 + "l4ls_gclk",
33679 + /* Required for external peripherals like, Audio codecs */
33680 + "clkout2_ck",
33681 +};
33682 +
33683 +int __init am33xx_clk_init(void)
33684 +{
33685 + struct clk *clk1, *clk2;
33686 +
33687 + of_clk_init(NULL);
33688 +
33689 + omap_dt_clocks_register(am33xx_clks);
33690 +
33691 + omap2_clk_disable_autoidle_all();
33692 +
33693 + omap2_clk_enable_init_clocks(enable_init_clks,
33694 + ARRAY_SIZE(enable_init_clks));
33695 +
33696 + /* TRM ERRATA: Timer 3 & 6 default parent (TCLKIN) may not be always
33697 + * physically present, in such a case HWMOD enabling of
33698 + * clock would be failure with default parent. And timer
33699 + * probe thinks clock is already enabled, this leads to
33700 + * crash upon accessing timer 3 & 6 registers in probe.
33701 + * Fix by setting parent of both these timers to master
33702 + * oscillator clock.
33703 + */
33704 +
33705 + clk1 = clk_get_sys(NULL, "sys_clkin_ck");
33706 + clk2 = clk_get_sys(NULL, "timer3_fck");
33707 + clk_set_parent(clk2, clk1);
33708 +
33709 + clk2 = clk_get_sys(NULL, "timer6_fck");
33710 + clk_set_parent(clk2, clk1);
33711 + /*
33712 + * The On-Chip 32K RC Osc clock is not an accurate clock-source as per
33713 + * the design/spec, so as a result, for example, timer which supposed
33714 + * to get expired @60Sec, but will expire somewhere ~@40Sec, which is
33715 + * not expected by any use-case, so change WDT1 clock source to PRCM
33716 + * 32KHz clock.
33717 + */
33718 + clk1 = clk_get_sys(NULL, "wdt1_fck");
33719 + clk2 = clk_get_sys(NULL, "clkdiv32k_ick");
33720 + clk_set_parent(clk1, clk2);
33721 +
33722 + return 0;
33723 +}
33724 --- /dev/null
33725 +++ b/drivers/clk/ti/clk-3xxx.c
33726 @@ -0,0 +1,388 @@
33727 +/*
33728 + * OMAP3 Clock init
33729 + *
33730 + * Copyright (C) 2013 Texas Instruments, Inc
33731 + * Tero Kristo (t-kristo@ti.com)
33732 + *
33733 + * This program is free software; you can redistribute it and/or
33734 + * modify it under the terms of the GNU General Public License as
33735 + * published by the Free Software Foundation version 2.
33736 + *
33737 + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
33738 + * kind, whether express or implied; without even the implied warranty
33739 + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
33740 + * GNU General Public License for more details.
33741 + */
33742 +
33743 +#include <linux/kernel.h>
33744 +#include <linux/list.h>
33745 +#include <linux/clk-provider.h>
33746 +#include <linux/clk/ti.h>
33747 +
33748 +
33749 +static struct omap_dt_clk omap3xxx_clks[] = {
33750 + DT_CLK(NULL, "apb_pclk", "dummy_apb_pclk"),
33751 + DT_CLK(NULL, "omap_32k_fck", "omap_32k_fck"),
33752 + DT_CLK(NULL, "virt_12m_ck", "virt_12m_ck"),
33753 + DT_CLK(NULL, "virt_13m_ck", "virt_13m_ck"),
33754 + DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"),
33755 + DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"),
33756 + DT_CLK(NULL, "virt_38_4m_ck", "virt_38_4m_ck"),
33757 + DT_CLK(NULL, "osc_sys_ck", "osc_sys_ck"),
33758 + DT_CLK("twl", "fck", "osc_sys_ck"),
33759 + DT_CLK(NULL, "sys_ck", "sys_ck"),
33760 + DT_CLK(NULL, "omap_96m_alwon_fck", "omap_96m_alwon_fck"),
33761 + DT_CLK("etb", "emu_core_alwon_ck", "emu_core_alwon_ck"),
33762 + DT_CLK(NULL, "sys_altclk", "sys_altclk"),
33763 + DT_CLK(NULL, "mcbsp_clks", "mcbsp_clks"),
33764 + DT_CLK(NULL, "sys_clkout1", "sys_clkout1"),
33765 + DT_CLK(NULL, "dpll1_ck", "dpll1_ck"),
33766 + DT_CLK(NULL, "dpll1_x2_ck", "dpll1_x2_ck"),
33767 + DT_CLK(NULL, "dpll1_x2m2_ck", "dpll1_x2m2_ck"),
33768 + DT_CLK(NULL, "dpll3_ck", "dpll3_ck"),
33769 + DT_CLK(NULL, "core_ck", "core_ck"),
33770 + DT_CLK(NULL, "dpll3_x2_ck", "dpll3_x2_ck"),
33771 + DT_CLK(NULL, "dpll3_m2_ck", "dpll3_m2_ck"),
33772 + DT_CLK(NULL, "dpll3_m2x2_ck", "dpll3_m2x2_ck"),
33773 + DT_CLK(NULL, "dpll3_m3_ck", "dpll3_m3_ck"),
33774 + DT_CLK(NULL, "dpll3_m3x2_ck", "dpll3_m3x2_ck"),
33775 + DT_CLK(NULL, "dpll4_ck", "dpll4_ck"),
33776 + DT_CLK(NULL, "dpll4_x2_ck", "dpll4_x2_ck"),
33777 + DT_CLK(NULL, "omap_96m_fck", "omap_96m_fck"),
33778 + DT_CLK(NULL, "cm_96m_fck", "cm_96m_fck"),
33779 + DT_CLK(NULL, "omap_54m_fck", "omap_54m_fck"),
33780 + DT_CLK(NULL, "omap_48m_fck", "omap_48m_fck"),
33781 + DT_CLK(NULL, "omap_12m_fck", "omap_12m_fck"),
33782 + DT_CLK(NULL, "dpll4_m2_ck", "dpll4_m2_ck"),
33783 + DT_CLK(NULL, "dpll4_m2x2_ck", "dpll4_m2x2_ck"),
33784 + DT_CLK(NULL, "dpll4_m3_ck", "dpll4_m3_ck"),
33785 + DT_CLK(NULL, "dpll4_m3x2_ck", "dpll4_m3x2_ck"),
33786 + DT_CLK(NULL, "dpll4_m4_ck", "dpll4_m4_ck"),
33787 + DT_CLK(NULL, "dpll4_m4x2_ck", "dpll4_m4x2_ck"),
33788 + DT_CLK(NULL, "dpll4_m5_ck", "dpll4_m5_ck"),
33789 + DT_CLK(NULL, "dpll4_m5x2_ck", "dpll4_m5x2_ck"),
33790 + DT_CLK(NULL, "dpll4_m6_ck", "dpll4_m6_ck"),
33791 + DT_CLK(NULL, "dpll4_m6x2_ck", "dpll4_m6x2_ck"),
33792 + DT_CLK("etb", "emu_per_alwon_ck", "emu_per_alwon_ck"),
33793 + DT_CLK(NULL, "clkout2_src_ck", "clkout2_src_ck"),
33794 + DT_CLK(NULL, "sys_clkout2", "sys_clkout2"),
33795 + DT_CLK(NULL, "corex2_fck", "corex2_fck"),
33796 + DT_CLK(NULL, "dpll1_fck", "dpll1_fck"),
33797 + DT_CLK(NULL, "mpu_ck", "mpu_ck"),
33798 + DT_CLK(NULL, "arm_fck", "arm_fck"),
33799 + DT_CLK("etb", "emu_mpu_alwon_ck", "emu_mpu_alwon_ck"),
33800 + DT_CLK(NULL, "l3_ick", "l3_ick"),
33801 + DT_CLK(NULL, "l4_ick", "l4_ick"),
33802 + DT_CLK(NULL, "rm_ick", "rm_ick"),
33803 + DT_CLK(NULL, "gpt10_fck", "gpt10_fck"),
33804 + DT_CLK(NULL, "gpt11_fck", "gpt11_fck"),
33805 + DT_CLK(NULL, "core_96m_fck", "core_96m_fck"),
33806 + DT_CLK(NULL, "mmchs2_fck", "mmchs2_fck"),
33807 + DT_CLK(NULL, "mmchs1_fck", "mmchs1_fck"),
33808 + DT_CLK(NULL, "i2c3_fck", "i2c3_fck"),
33809 + DT_CLK(NULL, "i2c2_fck", "i2c2_fck"),
33810 + DT_CLK(NULL, "i2c1_fck", "i2c1_fck"),
33811 + DT_CLK(NULL, "mcbsp5_fck", "mcbsp5_fck"),
33812 + DT_CLK(NULL, "mcbsp1_fck", "mcbsp1_fck"),
33813 + DT_CLK(NULL, "core_48m_fck", "core_48m_fck"),
33814 + DT_CLK(NULL, "mcspi4_fck", "mcspi4_fck"),
33815 + DT_CLK(NULL, "mcspi3_fck", "mcspi3_fck"),
33816 + DT_CLK(NULL, "mcspi2_fck", "mcspi2_fck"),
33817 + DT_CLK(NULL, "mcspi1_fck", "mcspi1_fck"),
33818 + DT_CLK(NULL, "uart2_fck", "uart2_fck"),
33819 + DT_CLK(NULL, "uart1_fck", "uart1_fck"),
33820 + DT_CLK(NULL, "core_12m_fck", "core_12m_fck"),
33821 + DT_CLK("omap_hdq.0", "fck", "hdq_fck"),
33822 + DT_CLK(NULL, "hdq_fck", "hdq_fck"),
33823 + DT_CLK(NULL, "core_l3_ick", "core_l3_ick"),
33824 + DT_CLK(NULL, "sdrc_ick", "sdrc_ick"),
33825 + DT_CLK(NULL, "gpmc_fck", "gpmc_fck"),
33826 + DT_CLK(NULL, "core_l4_ick", "core_l4_ick"),
33827 + DT_CLK("omap_hsmmc.1", "ick", "mmchs2_ick"),
33828 + DT_CLK("omap_hsmmc.0", "ick", "mmchs1_ick"),
33829 + DT_CLK(NULL, "mmchs2_ick", "mmchs2_ick"),
33830 + DT_CLK(NULL, "mmchs1_ick", "mmchs1_ick"),
33831 + DT_CLK("omap_hdq.0", "ick", "hdq_ick"),
33832 + DT_CLK(NULL, "hdq_ick", "hdq_ick"),
33833 + DT_CLK("omap2_mcspi.4", "ick", "mcspi4_ick"),
33834 + DT_CLK("omap2_mcspi.3", "ick", "mcspi3_ick"),
33835 + DT_CLK("omap2_mcspi.2", "ick", "mcspi2_ick"),
33836 + DT_CLK("omap2_mcspi.1", "ick", "mcspi1_ick"),
33837 + DT_CLK(NULL, "mcspi4_ick", "mcspi4_ick"),
33838 + DT_CLK(NULL, "mcspi3_ick", "mcspi3_ick"),
33839 + DT_CLK(NULL, "mcspi2_ick", "mcspi2_ick"),
33840 + DT_CLK(NULL, "mcspi1_ick", "mcspi1_ick"),
33841 + DT_CLK("omap_i2c.3", "ick", "i2c3_ick"),
33842 + DT_CLK("omap_i2c.2", "ick", "i2c2_ick"),
33843 + DT_CLK("omap_i2c.1", "ick", "i2c1_ick"),
33844 + DT_CLK(NULL, "i2c3_ick", "i2c3_ick"),
33845 + DT_CLK(NULL, "i2c2_ick", "i2c2_ick"),
33846 + DT_CLK(NULL, "i2c1_ick", "i2c1_ick"),
33847 + DT_CLK(NULL, "uart2_ick", "uart2_ick"),
33848 + DT_CLK(NULL, "uart1_ick", "uart1_ick"),
33849 + DT_CLK(NULL, "gpt11_ick", "gpt11_ick"),
33850 + DT_CLK(NULL, "gpt10_ick", "gpt10_ick"),
33851 + DT_CLK("omap-mcbsp.5", "ick", "mcbsp5_ick"),
33852 + DT_CLK("omap-mcbsp.1", "ick", "mcbsp1_ick"),
33853 + DT_CLK(NULL, "mcbsp5_ick", "mcbsp5_ick"),
33854 + DT_CLK(NULL, "mcbsp1_ick", "mcbsp1_ick"),
33855 + DT_CLK(NULL, "omapctrl_ick", "omapctrl_ick"),
33856 + DT_CLK(NULL, "dss_tv_fck", "dss_tv_fck"),
33857 + DT_CLK(NULL, "dss_96m_fck", "dss_96m_fck"),
33858 + DT_CLK(NULL, "dss2_alwon_fck", "dss2_alwon_fck"),
33859 + DT_CLK(NULL, "gpt1_fck", "gpt1_fck"),
33860 + DT_CLK(NULL, "aes2_ick", "aes2_ick"),
33861 + DT_CLK(NULL, "wkup_32k_fck", "wkup_32k_fck"),
33862 + DT_CLK(NULL, "gpio1_dbck", "gpio1_dbck"),
33863 + DT_CLK(NULL, "sha12_ick", "sha12_ick"),
33864 + DT_CLK(NULL, "wdt2_fck", "wdt2_fck"),
33865 + DT_CLK("omap_wdt", "ick", "wdt2_ick"),
33866 + DT_CLK(NULL, "wdt2_ick", "wdt2_ick"),
33867 + DT_CLK(NULL, "wdt1_ick", "wdt1_ick"),
33868 + DT_CLK(NULL, "gpio1_ick", "gpio1_ick"),
33869 + DT_CLK(NULL, "omap_32ksync_ick", "omap_32ksync_ick"),
33870 + DT_CLK(NULL, "gpt12_ick", "gpt12_ick"),
33871 + DT_CLK(NULL, "gpt1_ick", "gpt1_ick"),
33872 + DT_CLK(NULL, "per_96m_fck", "per_96m_fck"),
33873 + DT_CLK(NULL, "per_48m_fck", "per_48m_fck"),
33874 + DT_CLK(NULL, "uart3_fck", "uart3_fck"),
33875 + DT_CLK(NULL, "gpt2_fck", "gpt2_fck"),
33876 + DT_CLK(NULL, "gpt3_fck", "gpt3_fck"),
33877 + DT_CLK(NULL, "gpt4_fck", "gpt4_fck"),
33878 + DT_CLK(NULL, "gpt5_fck", "gpt5_fck"),
33879 + DT_CLK(NULL, "gpt6_fck", "gpt6_fck"),
33880 + DT_CLK(NULL, "gpt7_fck", "gpt7_fck"),
33881 + DT_CLK(NULL, "gpt8_fck", "gpt8_fck"),
33882 + DT_CLK(NULL, "gpt9_fck", "gpt9_fck"),
33883 + DT_CLK(NULL, "per_32k_alwon_fck", "per_32k_alwon_fck"),
33884 + DT_CLK(NULL, "gpio6_dbck", "gpio6_dbck"),
33885 + DT_CLK(NULL, "gpio5_dbck", "gpio5_dbck"),
33886 + DT_CLK(NULL, "gpio4_dbck", "gpio4_dbck"),
33887 + DT_CLK(NULL, "gpio3_dbck", "gpio3_dbck"),
33888 + DT_CLK(NULL, "gpio2_dbck", "gpio2_dbck"),
33889 + DT_CLK(NULL, "wdt3_fck", "wdt3_fck"),
33890 + DT_CLK(NULL, "per_l4_ick", "per_l4_ick"),
33891 + DT_CLK(NULL, "gpio6_ick", "gpio6_ick"),
33892 + DT_CLK(NULL, "gpio5_ick", "gpio5_ick"),
33893 + DT_CLK(NULL, "gpio4_ick", "gpio4_ick"),
33894 + DT_CLK(NULL, "gpio3_ick", "gpio3_ick"),
33895 + DT_CLK(NULL, "gpio2_ick", "gpio2_ick"),
33896 + DT_CLK(NULL, "wdt3_ick", "wdt3_ick"),
33897 + DT_CLK(NULL, "uart3_ick", "uart3_ick"),
33898 + DT_CLK(NULL, "uart4_ick", "uart4_ick"),
33899 + DT_CLK(NULL, "gpt9_ick", "gpt9_ick"),
33900 + DT_CLK(NULL, "gpt8_ick", "gpt8_ick"),
33901 + DT_CLK(NULL, "gpt7_ick", "gpt7_ick"),
33902 + DT_CLK(NULL, "gpt6_ick", "gpt6_ick"),
33903 + DT_CLK(NULL, "gpt5_ick", "gpt5_ick"),
33904 + DT_CLK(NULL, "gpt4_ick", "gpt4_ick"),
33905 + DT_CLK(NULL, "gpt3_ick", "gpt3_ick"),
33906 + DT_CLK(NULL, "gpt2_ick", "gpt2_ick"),
33907 + DT_CLK("omap-mcbsp.2", "ick", "mcbsp2_ick"),
33908 + DT_CLK("omap-mcbsp.3", "ick", "mcbsp3_ick"),
33909 + DT_CLK("omap-mcbsp.4", "ick", "mcbsp4_ick"),
33910 + DT_CLK(NULL, "mcbsp4_ick", "mcbsp2_ick"),
33911 + DT_CLK(NULL, "mcbsp3_ick", "mcbsp3_ick"),
33912 + DT_CLK(NULL, "mcbsp2_ick", "mcbsp4_ick"),
33913 + DT_CLK(NULL, "mcbsp2_fck", "mcbsp2_fck"),
33914 + DT_CLK(NULL, "mcbsp3_fck", "mcbsp3_fck"),
33915 + DT_CLK(NULL, "mcbsp4_fck", "mcbsp4_fck"),
33916 + DT_CLK("etb", "emu_src_ck", "emu_src_ck"),
33917 + DT_CLK(NULL, "emu_src_ck", "emu_src_ck"),
33918 + DT_CLK(NULL, "pclk_fck", "pclk_fck"),
33919 + DT_CLK(NULL, "pclkx2_fck", "pclkx2_fck"),
33920 + DT_CLK(NULL, "atclk_fck", "atclk_fck"),
33921 + DT_CLK(NULL, "traceclk_src_fck", "traceclk_src_fck"),
33922 + DT_CLK(NULL, "traceclk_fck", "traceclk_fck"),
33923 + DT_CLK(NULL, "secure_32k_fck", "secure_32k_fck"),
33924 + DT_CLK(NULL, "gpt12_fck", "gpt12_fck"),
33925 + DT_CLK(NULL, "wdt1_fck", "wdt1_fck"),
33926 + DT_CLK(NULL, "timer_32k_ck", "omap_32k_fck"),
33927 + DT_CLK(NULL, "timer_sys_ck", "sys_ck"),
33928 + DT_CLK(NULL, "cpufreq_ck", "dpll1_ck"),
33929 + { .node_name = NULL },
33930 +};
33931 +
33932 +static struct omap_dt_clk omap34xx_omap36xx_clks[] = {
33933 + DT_CLK(NULL, "aes1_ick", "aes1_ick"),
33934 + DT_CLK("omap_rng", "ick", "rng_ick"),
33935 + DT_CLK(NULL, "sha11_ick", "sha11_ick"),
33936 + DT_CLK(NULL, "des1_ick", "des1_ick"),
33937 + DT_CLK(NULL, "cam_mclk", "cam_mclk"),
33938 + DT_CLK(NULL, "cam_ick", "cam_ick"),
33939 + DT_CLK(NULL, "csi2_96m_fck", "csi2_96m_fck"),
33940 + DT_CLK(NULL, "security_l3_ick", "security_l3_ick"),
33941 + DT_CLK(NULL, "pka_ick", "pka_ick"),
33942 + DT_CLK(NULL, "icr_ick", "icr_ick"),
33943 + DT_CLK("omap-aes", "ick", "aes2_ick"),
33944 + DT_CLK("omap-sham", "ick", "sha12_ick"),
33945 + DT_CLK(NULL, "des2_ick", "des2_ick"),
33946 + DT_CLK(NULL, "mspro_ick", "mspro_ick"),
33947 + DT_CLK(NULL, "mailboxes_ick", "mailboxes_ick"),
33948 + DT_CLK(NULL, "ssi_l4_ick", "ssi_l4_ick"),
33949 + DT_CLK(NULL, "sr1_fck", "sr1_fck"),
33950 + DT_CLK(NULL, "sr2_fck", "sr2_fck"),
33951 + DT_CLK(NULL, "sr_l4_ick", "sr_l4_ick"),
33952 + DT_CLK(NULL, "security_l4_ick2", "security_l4_ick2"),
33953 + DT_CLK(NULL, "wkup_l4_ick", "wkup_l4_ick"),
33954 + DT_CLK(NULL, "dpll2_fck", "dpll2_fck"),
33955 + DT_CLK(NULL, "iva2_ck", "iva2_ck"),
33956 + DT_CLK(NULL, "modem_fck", "modem_fck"),
33957 + DT_CLK(NULL, "sad2d_ick", "sad2d_ick"),
33958 + DT_CLK(NULL, "mad2d_ick", "mad2d_ick"),
33959 + DT_CLK(NULL, "mspro_fck", "mspro_fck"),
33960 + DT_CLK(NULL, "dpll2_ck", "dpll2_ck"),
33961 + DT_CLK(NULL, "dpll2_m2_ck", "dpll2_m2_ck"),
33962 + { .node_name = NULL },
33963 +};
33964 +
33965 +static struct omap_dt_clk omap36xx_omap3430es2plus_clks[] = {
33966 + DT_CLK(NULL, "ssi_ssr_fck", "ssi_ssr_fck_3430es2"),
33967 + DT_CLK(NULL, "ssi_sst_fck", "ssi_sst_fck_3430es2"),
33968 + DT_CLK("musb-omap2430", "ick", "hsotgusb_ick_3430es2"),
33969 + DT_CLK(NULL, "hsotgusb_ick", "hsotgusb_ick_3430es2"),
33970 + DT_CLK(NULL, "ssi_ick", "ssi_ick_3430es2"),
33971 + DT_CLK(NULL, "usim_fck", "usim_fck"),
33972 + DT_CLK(NULL, "usim_ick", "usim_ick"),
33973 + { .node_name = NULL },
33974 +};
33975 +
33976 +static struct omap_dt_clk omap3430es1_clks[] = {
33977 + DT_CLK(NULL, "gfx_l3_ck", "gfx_l3_ck"),
33978 + DT_CLK(NULL, "gfx_l3_fck", "gfx_l3_fck"),
33979 + DT_CLK(NULL, "gfx_l3_ick", "gfx_l3_ick"),
33980 + DT_CLK(NULL, "gfx_cg1_ck", "gfx_cg1_ck"),
33981 + DT_CLK(NULL, "gfx_cg2_ck", "gfx_cg2_ck"),
33982 + DT_CLK(NULL, "d2d_26m_fck", "d2d_26m_fck"),
33983 + DT_CLK(NULL, "fshostusb_fck", "fshostusb_fck"),
33984 + DT_CLK(NULL, "ssi_ssr_fck", "ssi_ssr_fck_3430es1"),
33985 + DT_CLK(NULL, "ssi_sst_fck", "ssi_sst_fck_3430es1"),
33986 + DT_CLK("musb-omap2430", "ick", "hsotgusb_ick_3430es1"),
33987 + DT_CLK(NULL, "hsotgusb_ick", "hsotgusb_ick_3430es1"),
33988 + DT_CLK(NULL, "fac_ick", "fac_ick"),
33989 + DT_CLK(NULL, "ssi_ick", "ssi_ick_3430es1"),
33990 + DT_CLK(NULL, "usb_l4_ick", "usb_l4_ick"),
33991 + DT_CLK(NULL, "dss1_alwon_fck", "dss1_alwon_fck_3430es1"),
33992 + DT_CLK("omapdss_dss", "ick", "dss_ick_3430es1"),
33993 + DT_CLK(NULL, "dss_ick", "dss_ick_3430es1"),
33994 + { .node_name = NULL },
33995 +};
33996 +
33997 +static struct omap_dt_clk omap36xx_am35xx_omap3430es2plus_clks[] = {
33998 + DT_CLK(NULL, "virt_16_8m_ck", "virt_16_8m_ck"),
33999 + DT_CLK(NULL, "dpll5_ck", "dpll5_ck"),
34000 + DT_CLK(NULL, "dpll5_m2_ck", "dpll5_m2_ck"),
34001 + DT_CLK(NULL, "sgx_fck", "sgx_fck"),
34002 + DT_CLK(NULL, "sgx_ick", "sgx_ick"),
34003 + DT_CLK(NULL, "cpefuse_fck", "cpefuse_fck"),
34004 + DT_CLK(NULL, "ts_fck", "ts_fck"),
34005 + DT_CLK(NULL, "usbtll_fck", "usbtll_fck"),
34006 + DT_CLK(NULL, "usbtll_ick", "usbtll_ick"),
34007 + DT_CLK("omap_hsmmc.2", "ick", "mmchs3_ick"),
34008 + DT_CLK(NULL, "mmchs3_ick", "mmchs3_ick"),
34009 + DT_CLK(NULL, "mmchs3_fck", "mmchs3_fck"),
34010 + DT_CLK(NULL, "dss1_alwon_fck", "dss1_alwon_fck_3430es2"),
34011 + DT_CLK("omapdss_dss", "ick", "dss_ick_3430es2"),
34012 + DT_CLK(NULL, "dss_ick", "dss_ick_3430es2"),
34013 + DT_CLK(NULL, "usbhost_120m_fck", "usbhost_120m_fck"),
34014 + DT_CLK(NULL, "usbhost_48m_fck", "usbhost_48m_fck"),
34015 + DT_CLK(NULL, "usbhost_ick", "usbhost_ick"),
34016 + { .node_name = NULL },
34017 +};
34018 +
34019 +static struct omap_dt_clk am35xx_clks[] = {
34020 + DT_CLK(NULL, "ipss_ick", "ipss_ick"),
34021 + DT_CLK(NULL, "rmii_ck", "rmii_ck"),
34022 + DT_CLK(NULL, "pclk_ck", "pclk_ck"),
34023 + DT_CLK(NULL, "emac_ick", "emac_ick"),
34024 + DT_CLK(NULL, "emac_fck", "emac_fck"),
34025 + DT_CLK("davinci_emac.0", NULL, "emac_ick"),
34026 + DT_CLK("davinci_mdio.0", NULL, "emac_fck"),
34027 + DT_CLK("vpfe-capture", "master", "vpfe_ick"),
34028 + DT_CLK("vpfe-capture", "slave", "vpfe_fck"),
34029 + DT_CLK(NULL, "hsotgusb_ick", "hsotgusb_ick_am35xx"),
34030 + DT_CLK(NULL, "hsotgusb_fck", "hsotgusb_fck_am35xx"),
34031 + DT_CLK(NULL, "hecc_ck", "hecc_ck"),
34032 + DT_CLK(NULL, "uart4_ick", "uart4_ick_am35xx"),
34033 + DT_CLK(NULL, "uart4_fck", "uart4_fck_am35xx"),
34034 + { .node_name = NULL },
34035 +};
34036 +
34037 +static const char *enable_init_clks[] = {
34038 + "sdrc_ick",
34039 + "gpmc_fck",
34040 + "omapctrl_ick",
34041 +};
34042 +
34043 +enum {
34044 + OMAP3_SOC_AM35XX,
34045 + OMAP3_SOC_OMAP3430_ES1,
34046 + OMAP3_SOC_OMAP3430_ES2_PLUS,
34047 + OMAP3_SOC_OMAP3630,
34048 + OMAP3_SOC_TI81XX,
34049 +};
34050 +
34051 +static int __init omap3xxx_clk_init(int soc_type)
34052 +{
34053 + of_clk_init(NULL);
34054 +
34055 + if (soc_type == OMAP3_SOC_AM35XX || soc_type == OMAP3_SOC_OMAP3630 ||
34056 + soc_type == OMAP3_SOC_OMAP3430_ES1 ||
34057 + soc_type == OMAP3_SOC_OMAP3430_ES2_PLUS)
34058 + omap_dt_clocks_register(omap3xxx_clks);
34059 +
34060 + if (soc_type == OMAP3_SOC_AM35XX)
34061 + omap_dt_clocks_register(am35xx_clks);
34062 +
34063 + if (soc_type == OMAP3_SOC_OMAP3630 || soc_type == OMAP3_SOC_AM35XX ||
34064 + soc_type == OMAP3_SOC_OMAP3430_ES2_PLUS)
34065 + omap_dt_clocks_register(omap36xx_am35xx_omap3430es2plus_clks);
34066 +
34067 + if (soc_type == OMAP3_SOC_OMAP3430_ES1)
34068 + omap_dt_clocks_register(omap3430es1_clks);
34069 +
34070 + if (soc_type == OMAP3_SOC_OMAP3430_ES2_PLUS ||
34071 + soc_type == OMAP3_SOC_OMAP3630)
34072 + omap_dt_clocks_register(omap36xx_omap3430es2plus_clks);
34073 +
34074 + if (soc_type == OMAP3_SOC_OMAP3430_ES1 ||
34075 + soc_type == OMAP3_SOC_OMAP3430_ES2_PLUS ||
34076 + soc_type == OMAP3_SOC_OMAP3630)
34077 + omap_dt_clocks_register(omap34xx_omap36xx_clks);
34078 +
34079 + omap2_clk_disable_autoidle_all();
34080 +
34081 + omap2_clk_enable_init_clocks(enable_init_clks,
34082 + ARRAY_SIZE(enable_init_clks));
34083 +
34084 + pr_info("Clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n",
34085 + (clk_get_rate(clk_get_sys(NULL, "osc_sys_ck")) / 1000000),
34086 + (clk_get_rate(clk_get_sys(NULL, "osc_sys_ck")) / 100000) % 10,
34087 + (clk_get_rate(clk_get_sys(NULL, "core_ck")) / 1000000),
34088 + (clk_get_rate(clk_get_sys(NULL, "arm_fck")) / 1000000));
34089 +
34090 + if (soc_type != OMAP3_SOC_TI81XX && soc_type != OMAP3_SOC_OMAP3430_ES1)
34091 + omap3_clk_lock_dpll5();
34092 +
34093 + return 0;
34094 +}
34095 +
34096 +int __init omap3430_clk_init(void)
34097 +{
34098 + return omap3xxx_clk_init(OMAP3_SOC_OMAP3430_ES2_PLUS);
34099 +}
34100 +
34101 +int __init omap3630_clk_init(void)
34102 +{
34103 + return omap3xxx_clk_init(OMAP3_SOC_OMAP3630);
34104 +}
34105 +
34106 +int __init am35xx_clk_init(void)
34107 +{
34108 + return omap3xxx_clk_init(OMAP3_SOC_AM35XX);
34109 +}
34110 +
34111 +int __init ti81xx_clk_init(void)
34112 +{
34113 + return omap3xxx_clk_init(OMAP3_SOC_TI81XX);
34114 +}
34115 --- /dev/null
34116 +++ b/drivers/clk/ti/clk-43xx.c
34117 @@ -0,0 +1,136 @@
34118 +/*
34119 + * AM43XX Clock init
34120 + *
34121 + * Copyright (C) 2013 Texas Instruments, Inc
34122 + * Tero Kristo (t-kristo@ti.com)
34123 + *
34124 + * This program is free software; you can redistribute it and/or
34125 + * modify it under the terms of the GNU General Public License as
34126 + * published by the Free Software Foundation version 2.
34127 + *
34128 + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
34129 + * kind, whether express or implied; without even the implied warranty
34130 + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
34131 + * GNU General Public License for more details.
34132 + */
34133 +
34134 +#include <linux/kernel.h>
34135 +#include <linux/list.h>
34136 +#include <linux/clk-provider.h>
34137 +#include <linux/clk/ti.h>
34138 +
34139 +
34140 +static struct omap_dt_clk am43xx_clks[] = {
34141 + DT_CLK(NULL, "clk_32768_ck", "clk_32768_ck"),
34142 + DT_CLK(NULL, "clk_rc32k_ck", "clk_rc32k_ck"),
34143 + DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"),
34144 + DT_CLK(NULL, "virt_24000000_ck", "virt_24000000_ck"),
34145 + DT_CLK(NULL, "virt_25000000_ck", "virt_25000000_ck"),
34146 + DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"),
34147 + DT_CLK(NULL, "sys_clkin_ck", "sys_clkin_ck"),
34148 + DT_CLK(NULL, "tclkin_ck", "tclkin_ck"),
34149 + DT_CLK(NULL, "dpll_core_ck", "dpll_core_ck"),
34150 + DT_CLK(NULL, "dpll_core_x2_ck", "dpll_core_x2_ck"),
34151 + DT_CLK(NULL, "dpll_core_m4_ck", "dpll_core_m4_ck"),
34152 + DT_CLK(NULL, "dpll_core_m5_ck", "dpll_core_m5_ck"),
34153 + DT_CLK(NULL, "dpll_core_m6_ck", "dpll_core_m6_ck"),
34154 + DT_CLK(NULL, "dpll_mpu_ck", "dpll_mpu_ck"),
34155 + DT_CLK(NULL, "dpll_mpu_m2_ck", "dpll_mpu_m2_ck"),
34156 + DT_CLK(NULL, "dpll_ddr_ck", "dpll_ddr_ck"),
34157 + DT_CLK(NULL, "dpll_ddr_m2_ck", "dpll_ddr_m2_ck"),
34158 + DT_CLK(NULL, "dpll_disp_ck", "dpll_disp_ck"),
34159 + DT_CLK(NULL, "dpll_disp_m2_ck", "dpll_disp_m2_ck"),
34160 + DT_CLK(NULL, "dpll_per_ck", "dpll_per_ck"),
34161 + DT_CLK(NULL, "dpll_per_m2_ck", "dpll_per_m2_ck"),
34162 + DT_CLK(NULL, "dpll_per_m2_div4_wkupdm_ck", "dpll_per_m2_div4_wkupdm_ck"),
34163 + DT_CLK(NULL, "dpll_per_m2_div4_ck", "dpll_per_m2_div4_ck"),
34164 + DT_CLK(NULL, "adc_tsc_fck", "adc_tsc_fck"),
34165 + DT_CLK(NULL, "clkdiv32k_ck", "clkdiv32k_ck"),
34166 + DT_CLK(NULL, "clkdiv32k_ick", "clkdiv32k_ick"),
34167 + DT_CLK(NULL, "dcan0_fck", "dcan0_fck"),
34168 + DT_CLK(NULL, "dcan1_fck", "dcan1_fck"),
34169 + DT_CLK(NULL, "pruss_ocp_gclk", "pruss_ocp_gclk"),
34170 + DT_CLK(NULL, "mcasp0_fck", "mcasp0_fck"),
34171 + DT_CLK(NULL, "mcasp1_fck", "mcasp1_fck"),
34172 + DT_CLK(NULL, "smartreflex0_fck", "smartreflex0_fck"),
34173 + DT_CLK(NULL, "smartreflex1_fck", "smartreflex1_fck"),
34174 + DT_CLK(NULL, "sha0_fck", "sha0_fck"),
34175 + DT_CLK(NULL, "rng_fck", "rng_fck"),
34176 + DT_CLK(NULL, "aes0_fck", "aes0_fck"),
34177 + DT_CLK(NULL, "timer1_fck", "timer1_fck"),
34178 + DT_CLK(NULL, "timer2_fck", "timer2_fck"),
34179 + DT_CLK(NULL, "timer3_fck", "timer3_fck"),
34180 + DT_CLK(NULL, "timer4_fck", "timer4_fck"),
34181 + DT_CLK(NULL, "timer5_fck", "timer5_fck"),
34182 + DT_CLK(NULL, "timer6_fck", "timer6_fck"),
34183 + DT_CLK(NULL, "timer7_fck", "timer7_fck"),
34184 + DT_CLK(NULL, "wdt1_fck", "wdt1_fck"),
34185 + DT_CLK(NULL, "l3_gclk", "l3_gclk"),
34186 + DT_CLK(NULL, "dpll_core_m4_div2_ck", "dpll_core_m4_div2_ck"),
34187 + DT_CLK(NULL, "l4hs_gclk", "l4hs_gclk"),
34188 + DT_CLK(NULL, "l3s_gclk", "l3s_gclk"),
34189 + DT_CLK(NULL, "l4ls_gclk", "l4ls_gclk"),
34190 + DT_CLK(NULL, "clk_24mhz", "clk_24mhz"),
34191 + DT_CLK(NULL, "cpsw_125mhz_gclk", "cpsw_125mhz_gclk"),
34192 + DT_CLK(NULL, "cpsw_cpts_rft_clk", "cpsw_cpts_rft_clk"),
34193 + DT_CLK(NULL, "gpio0_dbclk_mux_ck", "gpio0_dbclk_mux_ck"),
34194 + DT_CLK(NULL, "gpio0_dbclk", "gpio0_dbclk"),
34195 + DT_CLK(NULL, "gpio1_dbclk", "gpio1_dbclk"),
34196 + DT_CLK(NULL, "gpio2_dbclk", "gpio2_dbclk"),
34197 + DT_CLK(NULL, "gpio3_dbclk", "gpio3_dbclk"),
34198 + DT_CLK(NULL, "gpio4_dbclk", "gpio4_dbclk"),
34199 + DT_CLK(NULL, "gpio5_dbclk", "gpio5_dbclk"),
34200 + DT_CLK(NULL, "mmc_clk", "mmc_clk"),
34201 + DT_CLK(NULL, "gfx_fclk_clksel_ck", "gfx_fclk_clksel_ck"),
34202 + DT_CLK(NULL, "gfx_fck_div_ck", "gfx_fck_div_ck"),
34203 + DT_CLK(NULL, "timer_32k_ck", "clkdiv32k_ick"),
34204 + DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"),
34205 + DT_CLK(NULL, "sysclk_div", "sysclk_div"),
34206 + DT_CLK(NULL, "disp_clk", "disp_clk"),
34207 + DT_CLK(NULL, "clk_32k_mosc_ck", "clk_32k_mosc_ck"),
34208 + DT_CLK(NULL, "clk_32k_tpm_ck", "clk_32k_tpm_ck"),
34209 + DT_CLK(NULL, "dpll_extdev_ck", "dpll_extdev_ck"),
34210 + DT_CLK(NULL, "dpll_extdev_m2_ck", "dpll_extdev_m2_ck"),
34211 + DT_CLK(NULL, "mux_synctimer32k_ck", "mux_synctimer32k_ck"),
34212 + DT_CLK(NULL, "synctimer_32kclk", "synctimer_32kclk"),
34213 + DT_CLK(NULL, "timer8_fck", "timer8_fck"),
34214 + DT_CLK(NULL, "timer9_fck", "timer9_fck"),
34215 + DT_CLK(NULL, "timer10_fck", "timer10_fck"),
34216 + DT_CLK(NULL, "timer11_fck", "timer11_fck"),
34217 + DT_CLK(NULL, "cpsw_50m_clkdiv", "cpsw_50m_clkdiv"),
34218 + DT_CLK(NULL, "cpsw_5m_clkdiv", "cpsw_5m_clkdiv"),
34219 + DT_CLK(NULL, "dpll_ddr_x2_ck", "dpll_ddr_x2_ck"),
34220 + DT_CLK(NULL, "dpll_ddr_m4_ck", "dpll_ddr_m4_ck"),
34221 + DT_CLK(NULL, "dpll_per_clkdcoldo", "dpll_per_clkdcoldo"),
34222 + DT_CLK(NULL, "dll_aging_clk_div", "dll_aging_clk_div"),
34223 + DT_CLK(NULL, "div_core_25m_ck", "div_core_25m_ck"),
34224 + DT_CLK(NULL, "func_12m_clk", "func_12m_clk"),
34225 + DT_CLK(NULL, "vtp_clk_div", "vtp_clk_div"),
34226 + DT_CLK(NULL, "usbphy_32khz_clkmux", "usbphy_32khz_clkmux"),
34227 + { .node_name = NULL },
34228 +};
34229 +
34230 +int __init am43xx_clk_init(void)
34231 +{
34232 + struct clk *clk1, *clk2;
34233 +
34234 + of_clk_init(NULL);
34235 +
34236 + omap_dt_clocks_register(am43xx_clks);
34237 +
34238 + omap2_clk_disable_autoidle_all();
34239 +
34240 + /*
34241 + * The external 32KHz RTC clock source may not always be available
34242 + * on board like in the case of ePOS EVM. By default sync timer, which
34243 + * is used as clock source, feeds of this clock. This is a problem.
34244 + * Change the parent of sync timer to PER PLL 32KHz clock instead
34245 + * which is always present. This has a side effect that in low power
34246 + * modes, sync timer will stop.
34247 + */
34248 + clk1 = clk_get_sys(NULL, "mux_synctimer32k_ck");
34249 + clk2 = clk_get_sys(NULL, "clkdiv32k_ick");
34250 + clk_set_parent(clk1, clk2);
34251 +
34252 + return 0;
34253 +}
34254 --- /dev/null
34255 +++ b/drivers/clk/ti/clk-44xx.c
34256 @@ -0,0 +1,307 @@
34257 +/*
34258 + * OMAP4 Clock data
34259 + *
34260 + * Copyright (C) 2009-2012 Texas Instruments, Inc.
34261 + * Copyright (C) 2009-2010 Nokia Corporation
34262 + *
34263 + * Paul Walmsley (paul@pwsan.com)
34264 + * Rajendra Nayak (rnayak@ti.com)
34265 + * Benoit Cousson (b-cousson@ti.com)
34266 + * Mike Turquette (mturquette@ti.com)
34267 + *
34268 + * This program is free software; you can redistribute it and/or modify
34269 + * it under the terms of the GNU General Public License version 2 as
34270 + * published by the Free Software Foundation.
34271 + *
34272 + * XXX Some of the ES1 clocks have been removed/changed; once support
34273 + * is added for discriminating clocks by ES level, these should be added back
34274 + * in.
34275 + *
34276 + * XXX All of the remaining MODULEMODE clock nodes should be removed
34277 + * once the drivers are updated to use pm_runtime or to use the appropriate
34278 + * upstream clock node for rate/parent selection.
34279 + */
34280 +
34281 +#include <linux/kernel.h>
34282 +#include <linux/list.h>
34283 +#include <linux/clk-private.h>
34284 +#include <linux/clkdev.h>
34285 +#include <linux/clk/ti.h>
34286 +
34287 +/*
34288 + * OMAP4 ABE DPLL default frequency. In OMAP4460 TRM version V, section
34289 + * "3.6.3.2.3 CM1_ABE Clock Generator" states that the "DPLL_ABE_X2_CLK
34290 + * must be set to 196.608 MHz" and hence, the DPLL locked frequency is
34291 + * half of this value.
34292 + */
34293 +#define OMAP4_DPLL_ABE_DEFFREQ 98304000
34294 +
34295 +/*
34296 + * OMAP4 USB DPLL default frequency. In OMAP4430 TRM version V, section
34297 + * "3.6.3.9.5 DPLL_USB Preferred Settings" shows that the preferred
34298 + * locked frequency for the USB DPLL is 960MHz.
34299 + */
34300 +#define OMAP4_DPLL_USB_DEFFREQ 960000000
34301 +
34302 +static struct omap_dt_clk omap44xx_clks[] = {
34303 + DT_CLK(NULL, "extalt_clkin_ck", "extalt_clkin_ck"),
34304 + DT_CLK(NULL, "pad_clks_src_ck", "pad_clks_src_ck"),
34305 + DT_CLK(NULL, "pad_clks_ck", "pad_clks_ck"),
34306 + DT_CLK(NULL, "pad_slimbus_core_clks_ck", "pad_slimbus_core_clks_ck"),
34307 + DT_CLK(NULL, "secure_32k_clk_src_ck", "secure_32k_clk_src_ck"),
34308 + DT_CLK(NULL, "slimbus_src_clk", "slimbus_src_clk"),
34309 + DT_CLK(NULL, "slimbus_clk", "slimbus_clk"),
34310 + DT_CLK(NULL, "sys_32k_ck", "sys_32k_ck"),
34311 + DT_CLK(NULL, "virt_12000000_ck", "virt_12000000_ck"),
34312 + DT_CLK(NULL, "virt_13000000_ck", "virt_13000000_ck"),
34313 + DT_CLK(NULL, "virt_16800000_ck", "virt_16800000_ck"),
34314 + DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"),
34315 + DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"),
34316 + DT_CLK(NULL, "virt_27000000_ck", "virt_27000000_ck"),
34317 + DT_CLK(NULL, "virt_38400000_ck", "virt_38400000_ck"),
34318 + DT_CLK(NULL, "sys_clkin_ck", "sys_clkin_ck"),
34319 + DT_CLK(NULL, "tie_low_clock_ck", "tie_low_clock_ck"),
34320 + DT_CLK(NULL, "utmi_phy_clkout_ck", "utmi_phy_clkout_ck"),
34321 + DT_CLK(NULL, "xclk60mhsp1_ck", "xclk60mhsp1_ck"),
34322 + DT_CLK(NULL, "xclk60mhsp2_ck", "xclk60mhsp2_ck"),
34323 + DT_CLK(NULL, "xclk60motg_ck", "xclk60motg_ck"),
34324 + DT_CLK(NULL, "abe_dpll_bypass_clk_mux_ck", "abe_dpll_bypass_clk_mux_ck"),
34325 + DT_CLK(NULL, "abe_dpll_refclk_mux_ck", "abe_dpll_refclk_mux_ck"),
34326 + DT_CLK(NULL, "dpll_abe_ck", "dpll_abe_ck"),
34327 + DT_CLK(NULL, "dpll_abe_x2_ck", "dpll_abe_x2_ck"),
34328 + DT_CLK(NULL, "dpll_abe_m2x2_ck", "dpll_abe_m2x2_ck"),
34329 + DT_CLK(NULL, "abe_24m_fclk", "abe_24m_fclk"),
34330 + DT_CLK(NULL, "abe_clk", "abe_clk"),
34331 + DT_CLK(NULL, "aess_fclk", "aess_fclk"),
34332 + DT_CLK(NULL, "dpll_abe_m3x2_ck", "dpll_abe_m3x2_ck"),
34333 + DT_CLK(NULL, "core_hsd_byp_clk_mux_ck", "core_hsd_byp_clk_mux_ck"),
34334 + DT_CLK(NULL, "dpll_core_ck", "dpll_core_ck"),
34335 + DT_CLK(NULL, "dpll_core_x2_ck", "dpll_core_x2_ck"),
34336 + DT_CLK(NULL, "dpll_core_m6x2_ck", "dpll_core_m6x2_ck"),
34337 + DT_CLK(NULL, "dbgclk_mux_ck", "dbgclk_mux_ck"),
34338 + DT_CLK(NULL, "dpll_core_m2_ck", "dpll_core_m2_ck"),
34339 + DT_CLK(NULL, "ddrphy_ck", "ddrphy_ck"),
34340 + DT_CLK(NULL, "dpll_core_m5x2_ck", "dpll_core_m5x2_ck"),
34341 + DT_CLK(NULL, "div_core_ck", "div_core_ck"),
34342 + DT_CLK(NULL, "div_iva_hs_clk", "div_iva_hs_clk"),
34343 + DT_CLK(NULL, "div_mpu_hs_clk", "div_mpu_hs_clk"),
34344 + DT_CLK(NULL, "dpll_core_m4x2_ck", "dpll_core_m4x2_ck"),
34345 + DT_CLK(NULL, "dll_clk_div_ck", "dll_clk_div_ck"),
34346 + DT_CLK(NULL, "dpll_abe_m2_ck", "dpll_abe_m2_ck"),
34347 + DT_CLK(NULL, "dpll_core_m3x2_ck", "dpll_core_m3x2_ck"),
34348 + DT_CLK(NULL, "dpll_core_m7x2_ck", "dpll_core_m7x2_ck"),
34349 + DT_CLK(NULL, "iva_hsd_byp_clk_mux_ck", "iva_hsd_byp_clk_mux_ck"),
34350 + DT_CLK(NULL, "dpll_iva_ck", "dpll_iva_ck"),
34351 + DT_CLK(NULL, "dpll_iva_x2_ck", "dpll_iva_x2_ck"),
34352 + DT_CLK(NULL, "dpll_iva_m4x2_ck", "dpll_iva_m4x2_ck"),
34353 + DT_CLK(NULL, "dpll_iva_m5x2_ck", "dpll_iva_m5x2_ck"),
34354 + DT_CLK(NULL, "dpll_mpu_ck", "dpll_mpu_ck"),
34355 + DT_CLK(NULL, "dpll_mpu_m2_ck", "dpll_mpu_m2_ck"),
34356 + DT_CLK(NULL, "per_hs_clk_div_ck", "per_hs_clk_div_ck"),
34357 + DT_CLK(NULL, "per_hsd_byp_clk_mux_ck", "per_hsd_byp_clk_mux_ck"),
34358 + DT_CLK(NULL, "dpll_per_ck", "dpll_per_ck"),
34359 + DT_CLK(NULL, "dpll_per_m2_ck", "dpll_per_m2_ck"),
34360 + DT_CLK(NULL, "dpll_per_x2_ck", "dpll_per_x2_ck"),
34361 + DT_CLK(NULL, "dpll_per_m2x2_ck", "dpll_per_m2x2_ck"),
34362 + DT_CLK(NULL, "dpll_per_m3x2_ck", "dpll_per_m3x2_ck"),
34363 + DT_CLK(NULL, "dpll_per_m4x2_ck", "dpll_per_m4x2_ck"),
34364 + DT_CLK(NULL, "dpll_per_m5x2_ck", "dpll_per_m5x2_ck"),
34365 + DT_CLK(NULL, "dpll_per_m6x2_ck", "dpll_per_m6x2_ck"),
34366 + DT_CLK(NULL, "dpll_per_m7x2_ck", "dpll_per_m7x2_ck"),
34367 + DT_CLK(NULL, "usb_hs_clk_div_ck", "usb_hs_clk_div_ck"),
34368 + DT_CLK(NULL, "dpll_usb_ck", "dpll_usb_ck"),
34369 + DT_CLK(NULL, "dpll_usb_clkdcoldo_ck", "dpll_usb_clkdcoldo_ck"),
34370 + DT_CLK(NULL, "dpll_usb_m2_ck", "dpll_usb_m2_ck"),
34371 + DT_CLK(NULL, "ducati_clk_mux_ck", "ducati_clk_mux_ck"),
34372 + DT_CLK(NULL, "func_12m_fclk", "func_12m_fclk"),
34373 + DT_CLK(NULL, "func_24m_clk", "func_24m_clk"),
34374 + DT_CLK(NULL, "func_24mc_fclk", "func_24mc_fclk"),
34375 + DT_CLK(NULL, "func_48m_fclk", "func_48m_fclk"),
34376 + DT_CLK(NULL, "func_48mc_fclk", "func_48mc_fclk"),
34377 + DT_CLK(NULL, "func_64m_fclk", "func_64m_fclk"),
34378 + DT_CLK(NULL, "func_96m_fclk", "func_96m_fclk"),
34379 + DT_CLK(NULL, "init_60m_fclk", "init_60m_fclk"),
34380 + DT_CLK(NULL, "l3_div_ck", "l3_div_ck"),
34381 + DT_CLK(NULL, "l4_div_ck", "l4_div_ck"),
34382 + DT_CLK(NULL, "lp_clk_div_ck", "lp_clk_div_ck"),
34383 + DT_CLK(NULL, "l4_wkup_clk_mux_ck", "l4_wkup_clk_mux_ck"),
34384 + DT_CLK("smp_twd", NULL, "mpu_periphclk"),
34385 + DT_CLK(NULL, "ocp_abe_iclk", "ocp_abe_iclk"),
34386 + DT_CLK(NULL, "per_abe_24m_fclk", "per_abe_24m_fclk"),
34387 + DT_CLK(NULL, "per_abe_nc_fclk", "per_abe_nc_fclk"),
34388 + DT_CLK(NULL, "syc_clk_div_ck", "syc_clk_div_ck"),
34389 + DT_CLK(NULL, "aes1_fck", "aes1_fck"),
34390 + DT_CLK(NULL, "aes2_fck", "aes2_fck"),
34391 + DT_CLK(NULL, "dmic_sync_mux_ck", "dmic_sync_mux_ck"),
34392 + DT_CLK(NULL, "func_dmic_abe_gfclk", "func_dmic_abe_gfclk"),
34393 + DT_CLK(NULL, "dss_sys_clk", "dss_sys_clk"),
34394 + DT_CLK(NULL, "dss_tv_clk", "dss_tv_clk"),
34395 + DT_CLK(NULL, "dss_dss_clk", "dss_dss_clk"),
34396 + DT_CLK(NULL, "dss_48mhz_clk", "dss_48mhz_clk"),
34397 + DT_CLK(NULL, "dss_fck", "dss_fck"),
34398 + DT_CLK("omapdss_dss", "ick", "dss_fck"),
34399 + DT_CLK(NULL, "fdif_fck", "fdif_fck"),
34400 + DT_CLK(NULL, "gpio1_dbclk", "gpio1_dbclk"),
34401 + DT_CLK(NULL, "gpio2_dbclk", "gpio2_dbclk"),
34402 + DT_CLK(NULL, "gpio3_dbclk", "gpio3_dbclk"),
34403 + DT_CLK(NULL, "gpio4_dbclk", "gpio4_dbclk"),
34404 + DT_CLK(NULL, "gpio5_dbclk", "gpio5_dbclk"),
34405 + DT_CLK(NULL, "gpio6_dbclk", "gpio6_dbclk"),
34406 + DT_CLK(NULL, "sgx_clk_mux", "sgx_clk_mux"),
34407 + DT_CLK(NULL, "hsi_fck", "hsi_fck"),
34408 + DT_CLK(NULL, "iss_ctrlclk", "iss_ctrlclk"),
34409 + DT_CLK(NULL, "mcasp_sync_mux_ck", "mcasp_sync_mux_ck"),
34410 + DT_CLK(NULL, "func_mcasp_abe_gfclk", "func_mcasp_abe_gfclk"),
34411 + DT_CLK(NULL, "mcbsp1_sync_mux_ck", "mcbsp1_sync_mux_ck"),
34412 + DT_CLK(NULL, "func_mcbsp1_gfclk", "func_mcbsp1_gfclk"),
34413 + DT_CLK(NULL, "mcbsp2_sync_mux_ck", "mcbsp2_sync_mux_ck"),
34414 + DT_CLK(NULL, "func_mcbsp2_gfclk", "func_mcbsp2_gfclk"),
34415 + DT_CLK(NULL, "mcbsp3_sync_mux_ck", "mcbsp3_sync_mux_ck"),
34416 + DT_CLK(NULL, "func_mcbsp3_gfclk", "func_mcbsp3_gfclk"),
34417 + DT_CLK(NULL, "mcbsp4_sync_mux_ck", "mcbsp4_sync_mux_ck"),
34418 + DT_CLK(NULL, "per_mcbsp4_gfclk", "per_mcbsp4_gfclk"),
34419 + DT_CLK(NULL, "hsmmc1_fclk", "hsmmc1_fclk"),
34420 + DT_CLK(NULL, "hsmmc2_fclk", "hsmmc2_fclk"),
34421 + DT_CLK(NULL, "ocp2scp_usb_phy_phy_48m", "ocp2scp_usb_phy_phy_48m"),
34422 + DT_CLK(NULL, "sha2md5_fck", "sha2md5_fck"),
34423 + DT_CLK(NULL, "slimbus1_fclk_1", "slimbus1_fclk_1"),
34424 + DT_CLK(NULL, "slimbus1_fclk_0", "slimbus1_fclk_0"),
34425 + DT_CLK(NULL, "slimbus1_fclk_2", "slimbus1_fclk_2"),
34426 + DT_CLK(NULL, "slimbus1_slimbus_clk", "slimbus1_slimbus_clk"),
34427 + DT_CLK(NULL, "slimbus2_fclk_1", "slimbus2_fclk_1"),
34428 + DT_CLK(NULL, "slimbus2_fclk_0", "slimbus2_fclk_0"),
34429 + DT_CLK(NULL, "slimbus2_slimbus_clk", "slimbus2_slimbus_clk"),
34430 + DT_CLK(NULL, "smartreflex_core_fck", "smartreflex_core_fck"),
34431 + DT_CLK(NULL, "smartreflex_iva_fck", "smartreflex_iva_fck"),
34432 + DT_CLK(NULL, "smartreflex_mpu_fck", "smartreflex_mpu_fck"),
34433 + DT_CLK(NULL, "dmt1_clk_mux", "dmt1_clk_mux"),
34434 + DT_CLK(NULL, "cm2_dm10_mux", "cm2_dm10_mux"),
34435 + DT_CLK(NULL, "cm2_dm11_mux", "cm2_dm11_mux"),
34436 + DT_CLK(NULL, "cm2_dm2_mux", "cm2_dm2_mux"),
34437 + DT_CLK(NULL, "cm2_dm3_mux", "cm2_dm3_mux"),
34438 + DT_CLK(NULL, "cm2_dm4_mux", "cm2_dm4_mux"),
34439 + DT_CLK(NULL, "timer5_sync_mux", "timer5_sync_mux"),
34440 + DT_CLK(NULL, "timer6_sync_mux", "timer6_sync_mux"),
34441 + DT_CLK(NULL, "timer7_sync_mux", "timer7_sync_mux"),
34442 + DT_CLK(NULL, "timer8_sync_mux", "timer8_sync_mux"),
34443 + DT_CLK(NULL, "cm2_dm9_mux", "cm2_dm9_mux"),
34444 + DT_CLK(NULL, "usb_host_fs_fck", "usb_host_fs_fck"),
34445 + DT_CLK("usbhs_omap", "fs_fck", "usb_host_fs_fck"),
34446 + DT_CLK(NULL, "utmi_p1_gfclk", "utmi_p1_gfclk"),
34447 + DT_CLK(NULL, "usb_host_hs_utmi_p1_clk", "usb_host_hs_utmi_p1_clk"),
34448 + DT_CLK(NULL, "utmi_p2_gfclk", "utmi_p2_gfclk"),
34449 + DT_CLK(NULL, "usb_host_hs_utmi_p2_clk", "usb_host_hs_utmi_p2_clk"),
34450 + DT_CLK(NULL, "usb_host_hs_utmi_p3_clk", "usb_host_hs_utmi_p3_clk"),
34451 + DT_CLK(NULL, "usb_host_hs_hsic480m_p1_clk", "usb_host_hs_hsic480m_p1_clk"),
34452 + DT_CLK(NULL, "usb_host_hs_hsic60m_p1_clk", "usb_host_hs_hsic60m_p1_clk"),
34453 + DT_CLK(NULL, "usb_host_hs_hsic60m_p2_clk", "usb_host_hs_hsic60m_p2_clk"),
34454 + DT_CLK(NULL, "usb_host_hs_hsic480m_p2_clk", "usb_host_hs_hsic480m_p2_clk"),
34455 + DT_CLK(NULL, "usb_host_hs_func48mclk", "usb_host_hs_func48mclk"),
34456 + DT_CLK(NULL, "usb_host_hs_fck", "usb_host_hs_fck"),
34457 + DT_CLK("usbhs_omap", "hs_fck", "usb_host_hs_fck"),
34458 + DT_CLK(NULL, "otg_60m_gfclk", "otg_60m_gfclk"),
34459 + DT_CLK(NULL, "usb_otg_hs_xclk", "usb_otg_hs_xclk"),
34460 + DT_CLK(NULL, "usb_otg_hs_ick", "usb_otg_hs_ick"),
34461 + DT_CLK("musb-omap2430", "ick", "usb_otg_hs_ick"),
34462 + DT_CLK(NULL, "usb_phy_cm_clk32k", "usb_phy_cm_clk32k"),
34463 + DT_CLK(NULL, "usb_tll_hs_usb_ch2_clk", "usb_tll_hs_usb_ch2_clk"),
34464 + DT_CLK(NULL, "usb_tll_hs_usb_ch0_clk", "usb_tll_hs_usb_ch0_clk"),
34465 + DT_CLK(NULL, "usb_tll_hs_usb_ch1_clk", "usb_tll_hs_usb_ch1_clk"),
34466 + DT_CLK(NULL, "usb_tll_hs_ick", "usb_tll_hs_ick"),
34467 + DT_CLK("usbhs_omap", "usbtll_ick", "usb_tll_hs_ick"),
34468 + DT_CLK("usbhs_tll", "usbtll_ick", "usb_tll_hs_ick"),
34469 + DT_CLK(NULL, "usim_ck", "usim_ck"),
34470 + DT_CLK(NULL, "usim_fclk", "usim_fclk"),
34471 + DT_CLK(NULL, "pmd_stm_clock_mux_ck", "pmd_stm_clock_mux_ck"),
34472 + DT_CLK(NULL, "pmd_trace_clk_mux_ck", "pmd_trace_clk_mux_ck"),
34473 + DT_CLK(NULL, "stm_clk_div_ck", "stm_clk_div_ck"),
34474 + DT_CLK(NULL, "trace_clk_div_ck", "trace_clk_div_ck"),
34475 + DT_CLK(NULL, "auxclk0_src_ck", "auxclk0_src_ck"),
34476 + DT_CLK(NULL, "auxclk0_ck", "auxclk0_ck"),
34477 + DT_CLK(NULL, "auxclkreq0_ck", "auxclkreq0_ck"),
34478 + DT_CLK(NULL, "auxclk1_src_ck", "auxclk1_src_ck"),
34479 + DT_CLK(NULL, "auxclk1_ck", "auxclk1_ck"),
34480 + DT_CLK(NULL, "auxclkreq1_ck", "auxclkreq1_ck"),
34481 + DT_CLK(NULL, "auxclk2_src_ck", "auxclk2_src_ck"),
34482 + DT_CLK(NULL, "auxclk2_ck", "auxclk2_ck"),
34483 + DT_CLK(NULL, "auxclkreq2_ck", "auxclkreq2_ck"),
34484 + DT_CLK(NULL, "auxclk3_src_ck", "auxclk3_src_ck"),
34485 + DT_CLK(NULL, "auxclk3_ck", "auxclk3_ck"),
34486 + DT_CLK(NULL, "auxclkreq3_ck", "auxclkreq3_ck"),
34487 + DT_CLK(NULL, "auxclk4_src_ck", "auxclk4_src_ck"),
34488 + DT_CLK(NULL, "auxclk4_ck", "auxclk4_ck"),
34489 + DT_CLK(NULL, "auxclkreq4_ck", "auxclkreq4_ck"),
34490 + DT_CLK(NULL, "auxclk5_src_ck", "auxclk5_src_ck"),
34491 + DT_CLK(NULL, "auxclk5_ck", "auxclk5_ck"),
34492 + DT_CLK(NULL, "auxclkreq5_ck", "auxclkreq5_ck"),
34493 + DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"),
34494 + DT_CLK("omap_timer.1", "timer_sys_ck", "sys_clkin_ck"),
34495 + DT_CLK("omap_timer.2", "timer_sys_ck", "sys_clkin_ck"),
34496 + DT_CLK("omap_timer.3", "timer_sys_ck", "sys_clkin_ck"),
34497 + DT_CLK("omap_timer.4", "timer_sys_ck", "sys_clkin_ck"),
34498 + DT_CLK("omap_timer.9", "timer_sys_ck", "sys_clkin_ck"),
34499 + DT_CLK("omap_timer.10", "timer_sys_ck", "sys_clkin_ck"),
34500 + DT_CLK("omap_timer.11", "timer_sys_ck", "sys_clkin_ck"),
34501 + DT_CLK("omap_timer.5", "timer_sys_ck", "syc_clk_div_ck"),
34502 + DT_CLK("omap_timer.6", "timer_sys_ck", "syc_clk_div_ck"),
34503 + DT_CLK("omap_timer.7", "timer_sys_ck", "syc_clk_div_ck"),
34504 + DT_CLK("omap_timer.8", "timer_sys_ck", "syc_clk_div_ck"),
34505 + DT_CLK("4a318000.timer", "timer_sys_ck", "sys_clkin_ck"),
34506 + DT_CLK("48032000.timer", "timer_sys_ck", "sys_clkin_ck"),
34507 + DT_CLK("48034000.timer", "timer_sys_ck", "sys_clkin_ck"),
34508 + DT_CLK("48036000.timer", "timer_sys_ck", "sys_clkin_ck"),
34509 + DT_CLK("4803e000.timer", "timer_sys_ck", "sys_clkin_ck"),
34510 + DT_CLK("48086000.timer", "timer_sys_ck", "sys_clkin_ck"),
34511 + DT_CLK("48088000.timer", "timer_sys_ck", "sys_clkin_ck"),
34512 + DT_CLK("40138000.timer", "timer_sys_ck", "syc_clk_div_ck"),
34513 + DT_CLK("4013a000.timer", "timer_sys_ck", "syc_clk_div_ck"),
34514 + DT_CLK("4013c000.timer", "timer_sys_ck", "syc_clk_div_ck"),
34515 + DT_CLK("4013e000.timer", "timer_sys_ck", "syc_clk_div_ck"),
34516 + DT_CLK(NULL, "cpufreq_ck", "dpll_mpu_ck"),
34517 + DT_CLK(NULL, "bandgap_fclk", "bandgap_fclk"),
34518 + DT_CLK(NULL, "div_ts_ck", "div_ts_ck"),
34519 + DT_CLK(NULL, "bandgap_ts_fclk", "bandgap_ts_fclk"),
34520 + { .node_name = NULL },
34521 +};
34522 +
34523 +int __init omap4xxx_clk_init(void)
34524 +{
34525 + int rc;
34526 + struct clk *abe_dpll_ref, *abe_dpll, *sys_32k_ck, *usb_dpll;
34527 +
34528 + of_clk_init(NULL);
34529 +
34530 + omap_dt_clocks_register(omap44xx_clks);
34531 +
34532 + omap2_clk_disable_autoidle_all();
34533 +
34534 + /*
34535 + * A set rate of ABE DPLL inturn triggers a set rate of USB DPLL
34536 + * when its in bypass. So always lock USB before ABE DPLL.
34537 + */
34538 + /*
34539 + * Lock USB DPLL on OMAP4 devices so that the L3INIT power
34540 + * domain can transition to retention state when not in use.
34541 + */
34542 + usb_dpll = clk_get_sys(NULL, "dpll_usb_ck");
34543 + rc = clk_set_rate(usb_dpll, OMAP4_DPLL_USB_DEFFREQ);
34544 + if (rc)
34545 + pr_err("%s: failed to configure USB DPLL!\n", __func__);
34546 +
34547 + /*
34548 + * On OMAP4460 the ABE DPLL fails to turn on if in idle low-power
34549 + * state when turning the ABE clock domain. Workaround this by
34550 + * locking the ABE DPLL on boot.
34551 + * Lock the ABE DPLL in any case to avoid issues with audio.
34552 + */
34553 + abe_dpll_ref = clk_get_sys(NULL, "abe_dpll_refclk_mux_ck");
34554 + sys_32k_ck = clk_get_sys(NULL, "sys_32k_ck");
34555 + rc = clk_set_parent(abe_dpll_ref, sys_32k_ck);
34556 + abe_dpll = clk_get_sys(NULL, "dpll_abe_ck");
34557 + if (!rc)
34558 + rc = clk_set_rate(abe_dpll, OMAP4_DPLL_ABE_DEFFREQ);
34559 + if (rc)
34560 + pr_err("%s: failed to configure ABE DPLL!\n", __func__);
34561 +
34562 + return 0;
34563 +}
34564 --- /dev/null
34565 +++ b/drivers/clk/ti/clk-54xx.c
34566 @@ -0,0 +1,231 @@
34567 +/*
34568 + * OMAP5 Clock init
34569 + *
34570 + * Copyright (C) 2013 Texas Instruments, Inc.
34571 + *
34572 + * Tero Kristo (t-kristo@ti.com)
34573 + *
34574 + * This program is free software; you can redistribute it and/or modify
34575 + * it under the terms of the GNU General Public License version 2 as
34576 + * published by the Free Software Foundation.
34577 + */
34578 +
34579 +#include <linux/kernel.h>
34580 +#include <linux/list.h>
34581 +#include <linux/clk-private.h>
34582 +#include <linux/clkdev.h>
34583 +#include <linux/io.h>
34584 +#include <linux/clk/ti.h>
34585 +
34586 +#define OMAP5_DPLL_ABE_DEFFREQ 98304000
34587 +
34588 +/*
34589 + * OMAP543x TRM, section "3.6.3.9.5 DPLL_USB Preferred Settings"
34590 + * states it must be at 960MHz
34591 + */
34592 +#define OMAP5_DPLL_USB_DEFFREQ 960000000
34593 +
34594 +static struct omap_dt_clk omap54xx_clks[] = {
34595 + DT_CLK(NULL, "pad_clks_src_ck", "pad_clks_src_ck"),
34596 + DT_CLK(NULL, "pad_clks_ck", "pad_clks_ck"),
34597 + DT_CLK(NULL, "secure_32k_clk_src_ck", "secure_32k_clk_src_ck"),
34598 + DT_CLK(NULL, "slimbus_src_clk", "slimbus_src_clk"),
34599 + DT_CLK(NULL, "slimbus_clk", "slimbus_clk"),
34600 + DT_CLK(NULL, "sys_32k_ck", "sys_32k_ck"),
34601 + DT_CLK(NULL, "virt_12000000_ck", "virt_12000000_ck"),
34602 + DT_CLK(NULL, "virt_13000000_ck", "virt_13000000_ck"),
34603 + DT_CLK(NULL, "virt_16800000_ck", "virt_16800000_ck"),
34604 + DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"),
34605 + DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"),
34606 + DT_CLK(NULL, "virt_27000000_ck", "virt_27000000_ck"),
34607 + DT_CLK(NULL, "virt_38400000_ck", "virt_38400000_ck"),
34608 + DT_CLK(NULL, "sys_clkin", "sys_clkin"),
34609 + DT_CLK(NULL, "xclk60mhsp1_ck", "xclk60mhsp1_ck"),
34610 + DT_CLK(NULL, "xclk60mhsp2_ck", "xclk60mhsp2_ck"),
34611 + DT_CLK(NULL, "abe_dpll_bypass_clk_mux", "abe_dpll_bypass_clk_mux"),
34612 + DT_CLK(NULL, "abe_dpll_clk_mux", "abe_dpll_clk_mux"),
34613 + DT_CLK(NULL, "dpll_abe_ck", "dpll_abe_ck"),
34614 + DT_CLK(NULL, "dpll_abe_x2_ck", "dpll_abe_x2_ck"),
34615 + DT_CLK(NULL, "dpll_abe_m2x2_ck", "dpll_abe_m2x2_ck"),
34616 + DT_CLK(NULL, "abe_24m_fclk", "abe_24m_fclk"),
34617 + DT_CLK(NULL, "abe_clk", "abe_clk"),
34618 + DT_CLK(NULL, "abe_iclk", "abe_iclk"),
34619 + DT_CLK(NULL, "abe_lp_clk_div", "abe_lp_clk_div"),
34620 + DT_CLK(NULL, "dpll_abe_m3x2_ck", "dpll_abe_m3x2_ck"),
34621 + DT_CLK(NULL, "dpll_core_ck", "dpll_core_ck"),
34622 + DT_CLK(NULL, "dpll_core_x2_ck", "dpll_core_x2_ck"),
34623 + DT_CLK(NULL, "dpll_core_h21x2_ck", "dpll_core_h21x2_ck"),
34624 + DT_CLK(NULL, "c2c_fclk", "c2c_fclk"),
34625 + DT_CLK(NULL, "c2c_iclk", "c2c_iclk"),
34626 + DT_CLK(NULL, "custefuse_sys_gfclk_div", "custefuse_sys_gfclk_div"),
34627 + DT_CLK(NULL, "dpll_core_h11x2_ck", "dpll_core_h11x2_ck"),
34628 + DT_CLK(NULL, "dpll_core_h12x2_ck", "dpll_core_h12x2_ck"),
34629 + DT_CLK(NULL, "dpll_core_h13x2_ck", "dpll_core_h13x2_ck"),
34630 + DT_CLK(NULL, "dpll_core_h14x2_ck", "dpll_core_h14x2_ck"),
34631 + DT_CLK(NULL, "dpll_core_h22x2_ck", "dpll_core_h22x2_ck"),
34632 + DT_CLK(NULL, "dpll_core_h23x2_ck", "dpll_core_h23x2_ck"),
34633 + DT_CLK(NULL, "dpll_core_h24x2_ck", "dpll_core_h24x2_ck"),
34634 + DT_CLK(NULL, "dpll_core_m2_ck", "dpll_core_m2_ck"),
34635 + DT_CLK(NULL, "dpll_core_m3x2_ck", "dpll_core_m3x2_ck"),
34636 + DT_CLK(NULL, "iva_dpll_hs_clk_div", "iva_dpll_hs_clk_div"),
34637 + DT_CLK(NULL, "dpll_iva_ck", "dpll_iva_ck"),
34638 + DT_CLK(NULL, "dpll_iva_x2_ck", "dpll_iva_x2_ck"),
34639 + DT_CLK(NULL, "dpll_iva_h11x2_ck", "dpll_iva_h11x2_ck"),
34640 + DT_CLK(NULL, "dpll_iva_h12x2_ck", "dpll_iva_h12x2_ck"),
34641 + DT_CLK(NULL, "mpu_dpll_hs_clk_div", "mpu_dpll_hs_clk_div"),
34642 + DT_CLK(NULL, "dpll_mpu_ck", "dpll_mpu_ck"),
34643 + DT_CLK(NULL, "dpll_mpu_m2_ck", "dpll_mpu_m2_ck"),
34644 + DT_CLK(NULL, "per_dpll_hs_clk_div", "per_dpll_hs_clk_div"),
34645 + DT_CLK(NULL, "dpll_per_ck", "dpll_per_ck"),
34646 + DT_CLK(NULL, "dpll_per_x2_ck", "dpll_per_x2_ck"),
34647 + DT_CLK(NULL, "dpll_per_h11x2_ck", "dpll_per_h11x2_ck"),
34648 + DT_CLK(NULL, "dpll_per_h12x2_ck", "dpll_per_h12x2_ck"),
34649 + DT_CLK(NULL, "dpll_per_h14x2_ck", "dpll_per_h14x2_ck"),
34650 + DT_CLK(NULL, "dpll_per_m2_ck", "dpll_per_m2_ck"),
34651 + DT_CLK(NULL, "dpll_per_m2x2_ck", "dpll_per_m2x2_ck"),
34652 + DT_CLK(NULL, "dpll_per_m3x2_ck", "dpll_per_m3x2_ck"),
34653 + DT_CLK(NULL, "dpll_unipro1_ck", "dpll_unipro1_ck"),
34654 + DT_CLK(NULL, "dpll_unipro1_clkdcoldo", "dpll_unipro1_clkdcoldo"),
34655 + DT_CLK(NULL, "dpll_unipro1_m2_ck", "dpll_unipro1_m2_ck"),
34656 + DT_CLK(NULL, "dpll_unipro2_ck", "dpll_unipro2_ck"),
34657 + DT_CLK(NULL, "dpll_unipro2_clkdcoldo", "dpll_unipro2_clkdcoldo"),
34658 + DT_CLK(NULL, "dpll_unipro2_m2_ck", "dpll_unipro2_m2_ck"),
34659 + DT_CLK(NULL, "usb_dpll_hs_clk_div", "usb_dpll_hs_clk_div"),
34660 + DT_CLK(NULL, "dpll_usb_ck", "dpll_usb_ck"),
34661 + DT_CLK(NULL, "dpll_usb_clkdcoldo", "dpll_usb_clkdcoldo"),
34662 + DT_CLK(NULL, "dpll_usb_m2_ck", "dpll_usb_m2_ck"),
34663 + DT_CLK(NULL, "dss_syc_gfclk_div", "dss_syc_gfclk_div"),
34664 + DT_CLK(NULL, "func_128m_clk", "func_128m_clk"),
34665 + DT_CLK(NULL, "func_12m_fclk", "func_12m_fclk"),
34666 + DT_CLK(NULL, "func_24m_clk", "func_24m_clk"),
34667 + DT_CLK(NULL, "func_48m_fclk", "func_48m_fclk"),
34668 + DT_CLK(NULL, "func_96m_fclk", "func_96m_fclk"),
34669 + DT_CLK(NULL, "l3_iclk_div", "l3_iclk_div"),
34670 + DT_CLK(NULL, "gpu_l3_iclk", "gpu_l3_iclk"),
34671 + DT_CLK(NULL, "l3init_60m_fclk", "l3init_60m_fclk"),
34672 + DT_CLK(NULL, "wkupaon_iclk_mux", "wkupaon_iclk_mux"),
34673 + DT_CLK(NULL, "l3instr_ts_gclk_div", "l3instr_ts_gclk_div"),
34674 + DT_CLK(NULL, "l4_root_clk_div", "l4_root_clk_div"),
34675 + DT_CLK(NULL, "dss_32khz_clk", "dss_32khz_clk"),
34676 + DT_CLK(NULL, "dss_48mhz_clk", "dss_48mhz_clk"),
34677 + DT_CLK(NULL, "dss_dss_clk", "dss_dss_clk"),
34678 + DT_CLK(NULL, "dss_sys_clk", "dss_sys_clk"),
34679 + DT_CLK(NULL, "gpio1_dbclk", "gpio1_dbclk"),
34680 + DT_CLK(NULL, "gpio2_dbclk", "gpio2_dbclk"),
34681 + DT_CLK(NULL, "gpio3_dbclk", "gpio3_dbclk"),
34682 + DT_CLK(NULL, "gpio4_dbclk", "gpio4_dbclk"),
34683 + DT_CLK(NULL, "gpio5_dbclk", "gpio5_dbclk"),
34684 + DT_CLK(NULL, "gpio6_dbclk", "gpio6_dbclk"),
34685 + DT_CLK(NULL, "gpio7_dbclk", "gpio7_dbclk"),
34686 + DT_CLK(NULL, "gpio8_dbclk", "gpio8_dbclk"),
34687 + DT_CLK(NULL, "iss_ctrlclk", "iss_ctrlclk"),
34688 + DT_CLK(NULL, "lli_txphy_clk", "lli_txphy_clk"),
34689 + DT_CLK(NULL, "lli_txphy_ls_clk", "lli_txphy_ls_clk"),
34690 + DT_CLK(NULL, "mmc1_32khz_clk", "mmc1_32khz_clk"),
34691 + DT_CLK(NULL, "sata_ref_clk", "sata_ref_clk"),
34692 + DT_CLK(NULL, "slimbus1_slimbus_clk", "slimbus1_slimbus_clk"),
34693 + DT_CLK(NULL, "usb_host_hs_hsic480m_p1_clk", "usb_host_hs_hsic480m_p1_clk"),
34694 + DT_CLK(NULL, "usb_host_hs_hsic480m_p2_clk", "usb_host_hs_hsic480m_p2_clk"),
34695 + DT_CLK(NULL, "usb_host_hs_hsic480m_p3_clk", "usb_host_hs_hsic480m_p3_clk"),
34696 + DT_CLK(NULL, "usb_host_hs_hsic60m_p1_clk", "usb_host_hs_hsic60m_p1_clk"),
34697 + DT_CLK(NULL, "usb_host_hs_hsic60m_p2_clk", "usb_host_hs_hsic60m_p2_clk"),
34698 + DT_CLK(NULL, "usb_host_hs_hsic60m_p3_clk", "usb_host_hs_hsic60m_p3_clk"),
34699 + DT_CLK(NULL, "usb_host_hs_utmi_p1_clk", "usb_host_hs_utmi_p1_clk"),
34700 + DT_CLK(NULL, "usb_host_hs_utmi_p2_clk", "usb_host_hs_utmi_p2_clk"),
34701 + DT_CLK(NULL, "usb_host_hs_utmi_p3_clk", "usb_host_hs_utmi_p3_clk"),
34702 + DT_CLK(NULL, "usb_otg_ss_refclk960m", "usb_otg_ss_refclk960m"),
34703 + DT_CLK(NULL, "usb_phy_cm_clk32k", "usb_phy_cm_clk32k"),
34704 + DT_CLK(NULL, "usb_tll_hs_usb_ch0_clk", "usb_tll_hs_usb_ch0_clk"),
34705 + DT_CLK(NULL, "usb_tll_hs_usb_ch1_clk", "usb_tll_hs_usb_ch1_clk"),
34706 + DT_CLK(NULL, "usb_tll_hs_usb_ch2_clk", "usb_tll_hs_usb_ch2_clk"),
34707 + DT_CLK(NULL, "aess_fclk", "aess_fclk"),
34708 + DT_CLK(NULL, "dmic_sync_mux_ck", "dmic_sync_mux_ck"),
34709 + DT_CLK(NULL, "dmic_gfclk", "dmic_gfclk"),
34710 + DT_CLK(NULL, "fdif_fclk", "fdif_fclk"),
34711 + DT_CLK(NULL, "gpu_core_gclk_mux", "gpu_core_gclk_mux"),
34712 + DT_CLK(NULL, "gpu_hyd_gclk_mux", "gpu_hyd_gclk_mux"),
34713 + DT_CLK(NULL, "hsi_fclk", "hsi_fclk"),
34714 + DT_CLK(NULL, "mcasp_sync_mux_ck", "mcasp_sync_mux_ck"),
34715 + DT_CLK(NULL, "mcasp_gfclk", "mcasp_gfclk"),
34716 + DT_CLK(NULL, "mcbsp1_sync_mux_ck", "mcbsp1_sync_mux_ck"),
34717 + DT_CLK(NULL, "mcbsp1_gfclk", "mcbsp1_gfclk"),
34718 + DT_CLK(NULL, "mcbsp2_sync_mux_ck", "mcbsp2_sync_mux_ck"),
34719 + DT_CLK(NULL, "mcbsp2_gfclk", "mcbsp2_gfclk"),
34720 + DT_CLK(NULL, "mcbsp3_sync_mux_ck", "mcbsp3_sync_mux_ck"),
34721 + DT_CLK(NULL, "mcbsp3_gfclk", "mcbsp3_gfclk"),
34722 + DT_CLK(NULL, "mmc1_fclk_mux", "mmc1_fclk_mux"),
34723 + DT_CLK(NULL, "mmc1_fclk", "mmc1_fclk"),
34724 + DT_CLK(NULL, "mmc2_fclk_mux", "mmc2_fclk_mux"),
34725 + DT_CLK(NULL, "mmc2_fclk", "mmc2_fclk"),
34726 + DT_CLK(NULL, "timer10_gfclk_mux", "timer10_gfclk_mux"),
34727 + DT_CLK(NULL, "timer11_gfclk_mux", "timer11_gfclk_mux"),
34728 + DT_CLK(NULL, "timer1_gfclk_mux", "timer1_gfclk_mux"),
34729 + DT_CLK(NULL, "timer2_gfclk_mux", "timer2_gfclk_mux"),
34730 + DT_CLK(NULL, "timer3_gfclk_mux", "timer3_gfclk_mux"),
34731 + DT_CLK(NULL, "timer4_gfclk_mux", "timer4_gfclk_mux"),
34732 + DT_CLK(NULL, "timer5_gfclk_mux", "timer5_gfclk_mux"),
34733 + DT_CLK(NULL, "timer6_gfclk_mux", "timer6_gfclk_mux"),
34734 + DT_CLK(NULL, "timer7_gfclk_mux", "timer7_gfclk_mux"),
34735 + DT_CLK(NULL, "timer8_gfclk_mux", "timer8_gfclk_mux"),
34736 + DT_CLK(NULL, "timer9_gfclk_mux", "timer9_gfclk_mux"),
34737 + DT_CLK(NULL, "utmi_p1_gfclk", "utmi_p1_gfclk"),
34738 + DT_CLK(NULL, "utmi_p2_gfclk", "utmi_p2_gfclk"),
34739 + DT_CLK(NULL, "auxclk0_src_ck", "auxclk0_src_ck"),
34740 + DT_CLK(NULL, "auxclk0_ck", "auxclk0_ck"),
34741 + DT_CLK(NULL, "auxclkreq0_ck", "auxclkreq0_ck"),
34742 + DT_CLK(NULL, "auxclk1_src_ck", "auxclk1_src_ck"),
34743 + DT_CLK(NULL, "auxclk1_ck", "auxclk1_ck"),
34744 + DT_CLK(NULL, "auxclkreq1_ck", "auxclkreq1_ck"),
34745 + DT_CLK(NULL, "auxclk2_src_ck", "auxclk2_src_ck"),
34746 + DT_CLK(NULL, "auxclk2_ck", "auxclk2_ck"),
34747 + DT_CLK(NULL, "auxclkreq2_ck", "auxclkreq2_ck"),
34748 + DT_CLK(NULL, "auxclk3_src_ck", "auxclk3_src_ck"),
34749 + DT_CLK(NULL, "auxclk3_ck", "auxclk3_ck"),
34750 + DT_CLK(NULL, "auxclkreq3_ck", "auxclkreq3_ck"),
34751 + DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"),
34752 + DT_CLK("omap_timer.1", "sys_ck", "sys_clkin"),
34753 + DT_CLK("omap_timer.2", "sys_ck", "sys_clkin"),
34754 + DT_CLK("omap_timer.3", "sys_ck", "sys_clkin"),
34755 + DT_CLK("omap_timer.4", "sys_ck", "sys_clkin"),
34756 + DT_CLK("omap_timer.9", "sys_ck", "sys_clkin"),
34757 + DT_CLK("omap_timer.10", "sys_ck", "sys_clkin"),
34758 + DT_CLK("omap_timer.11", "sys_ck", "sys_clkin"),
34759 + DT_CLK("omap_timer.5", "sys_ck", "dss_syc_gfclk_div"),
34760 + DT_CLK("omap_timer.6", "sys_ck", "dss_syc_gfclk_div"),
34761 + DT_CLK("omap_timer.7", "sys_ck", "dss_syc_gfclk_div"),
34762 + DT_CLK("omap_timer.8", "sys_ck", "dss_syc_gfclk_div"),
34763 + { .node_name = NULL },
34764 +};
34765 +
34766 +int __init omap5xxx_clk_init(void)
34767 +{
34768 + int rc;
34769 + struct clk *abe_dpll_ref, *abe_dpll, *sys_32k_ck, *usb_dpll;
34770 +
34771 + of_clk_init(NULL);
34772 +
34773 + omap_dt_clocks_register(omap54xx_clks);
34774 +
34775 + omap2_clk_disable_autoidle_all();
34776 +
34777 + abe_dpll_ref = clk_get_sys(NULL, "abe_dpll_clk_mux");
34778 + sys_32k_ck = clk_get_sys(NULL, "sys_32k_ck");
34779 + rc = clk_set_parent(abe_dpll_ref, sys_32k_ck);
34780 + abe_dpll = clk_get_sys(NULL, "dpll_abe_ck");
34781 + if (!rc)
34782 + rc = clk_set_rate(abe_dpll, OMAP5_DPLL_ABE_DEFFREQ);
34783 + if (rc)
34784 + pr_err("%s: failed to configure ABE DPLL!\n", __func__);
34785 +
34786 + usb_dpll = clk_get_sys(NULL, "dpll_usb_ck");
34787 + rc = clk_set_rate(usb_dpll, OMAP5_DPLL_USB_DEFFREQ);
34788 + if (rc)
34789 + pr_err("%s: failed to configure USB DPLL!\n", __func__);
34790 +
34791 + usb_dpll = clk_get_sys(NULL, "dpll_usb_m2_ck");
34792 + rc = clk_set_rate(usb_dpll, OMAP5_DPLL_USB_DEFFREQ/2);
34793 + if (rc)
34794 + pr_err("%s: failed to set USB_DPLL M2 OUT\n", __func__);
34795 +
34796 + return 0;
34797 +}
34798 --- /dev/null
34799 +++ b/drivers/clk/ti/clk-7xx.c
34800 @@ -0,0 +1,325 @@
34801 +/*
34802 + * DRA7 Clock init
34803 + *
34804 + * Copyright (C) 2013 Texas Instruments, Inc.
34805 + *
34806 + * Tero Kristo (t-kristo@ti.com)
34807 + *
34808 + * This program is free software; you can redistribute it and/or modify
34809 + * it under the terms of the GNU General Public License version 2 as
34810 + * published by the Free Software Foundation.
34811 + */
34812 +
34813 +#include <linux/kernel.h>
34814 +#include <linux/list.h>
34815 +#include <linux/clk-private.h>
34816 +#include <linux/clkdev.h>
34817 +#include <linux/clk/ti.h>
34818 +
34819 +#define DRA7_DPLL_ABE_DEFFREQ 361267200
34820 +#define DRA7_DPLL_GMAC_DEFFREQ 1000000000
34821 +#define DRA7_DPLL_USB_DEFFREQ 960000000
34822 +
34823 +
34824 +static struct omap_dt_clk dra7xx_clks[] = {
34825 + DT_CLK(NULL, "atl_clkin0_ck", "atl_clkin0_ck"),
34826 + DT_CLK(NULL, "atl_clkin1_ck", "atl_clkin1_ck"),
34827 + DT_CLK(NULL, "atl_clkin2_ck", "atl_clkin2_ck"),
34828 + DT_CLK(NULL, "atlclkin3_ck", "atlclkin3_ck"),
34829 + DT_CLK(NULL, "hdmi_clkin_ck", "hdmi_clkin_ck"),
34830 + DT_CLK(NULL, "mlb_clkin_ck", "mlb_clkin_ck"),
34831 + DT_CLK(NULL, "mlbp_clkin_ck", "mlbp_clkin_ck"),
34832 + DT_CLK(NULL, "pciesref_acs_clk_ck", "pciesref_acs_clk_ck"),
34833 + DT_CLK(NULL, "ref_clkin0_ck", "ref_clkin0_ck"),
34834 + DT_CLK(NULL, "ref_clkin1_ck", "ref_clkin1_ck"),
34835 + DT_CLK(NULL, "ref_clkin2_ck", "ref_clkin2_ck"),
34836 + DT_CLK(NULL, "ref_clkin3_ck", "ref_clkin3_ck"),
34837 + DT_CLK(NULL, "rmii_clk_ck", "rmii_clk_ck"),
34838 + DT_CLK(NULL, "sdvenc_clkin_ck", "sdvenc_clkin_ck"),
34839 + DT_CLK(NULL, "secure_32k_clk_src_ck", "secure_32k_clk_src_ck"),
34840 + DT_CLK(NULL, "sys_32k_ck", "sys_32k_ck"),
34841 + DT_CLK(NULL, "virt_12000000_ck", "virt_12000000_ck"),
34842 + DT_CLK(NULL, "virt_13000000_ck", "virt_13000000_ck"),
34843 + DT_CLK(NULL, "virt_16800000_ck", "virt_16800000_ck"),
34844 + DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"),
34845 + DT_CLK(NULL, "virt_20000000_ck", "virt_20000000_ck"),
34846 + DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"),
34847 + DT_CLK(NULL, "virt_27000000_ck", "virt_27000000_ck"),
34848 + DT_CLK(NULL, "virt_38400000_ck", "virt_38400000_ck"),
34849 + DT_CLK(NULL, "sys_clkin1", "sys_clkin1"),
34850 + DT_CLK(NULL, "sys_clkin2", "sys_clkin2"),
34851 + DT_CLK(NULL, "usb_otg_clkin_ck", "usb_otg_clkin_ck"),
34852 + DT_CLK(NULL, "video1_clkin_ck", "video1_clkin_ck"),
34853 + DT_CLK(NULL, "video1_m2_clkin_ck", "video1_m2_clkin_ck"),
34854 + DT_CLK(NULL, "video2_clkin_ck", "video2_clkin_ck"),
34855 + DT_CLK(NULL, "video2_m2_clkin_ck", "video2_m2_clkin_ck"),
34856 + DT_CLK(NULL, "abe_dpll_sys_clk_mux", "abe_dpll_sys_clk_mux"),
34857 + DT_CLK(NULL, "abe_dpll_bypass_clk_mux", "abe_dpll_bypass_clk_mux"),
34858 + DT_CLK(NULL, "abe_dpll_clk_mux", "abe_dpll_clk_mux"),
34859 + DT_CLK(NULL, "dpll_abe_ck", "dpll_abe_ck"),
34860 + DT_CLK(NULL, "dpll_abe_x2_ck", "dpll_abe_x2_ck"),
34861 + DT_CLK(NULL, "dpll_abe_m2x2_ck", "dpll_abe_m2x2_ck"),
34862 + DT_CLK(NULL, "abe_24m_fclk", "abe_24m_fclk"),
34863 + DT_CLK(NULL, "abe_clk", "abe_clk"),
34864 + DT_CLK(NULL, "aess_fclk", "aess_fclk"),
34865 + DT_CLK(NULL, "abe_giclk_div", "abe_giclk_div"),
34866 + DT_CLK(NULL, "abe_lp_clk_div", "abe_lp_clk_div"),
34867 + DT_CLK(NULL, "abe_sys_clk_div", "abe_sys_clk_div"),
34868 + DT_CLK(NULL, "adc_gfclk_mux", "adc_gfclk_mux"),
34869 + DT_CLK(NULL, "dpll_pcie_ref_ck", "dpll_pcie_ref_ck"),
34870 + DT_CLK(NULL, "dpll_pcie_ref_m2ldo_ck", "dpll_pcie_ref_m2ldo_ck"),
34871 + DT_CLK(NULL, "apll_pcie_ck", "apll_pcie_ck"),
34872 + DT_CLK(NULL, "apll_pcie_clkvcoldo", "apll_pcie_clkvcoldo"),
34873 + DT_CLK(NULL, "apll_pcie_clkvcoldo_div", "apll_pcie_clkvcoldo_div"),
34874 + DT_CLK(NULL, "apll_pcie_m2_ck", "apll_pcie_m2_ck"),
34875 + DT_CLK(NULL, "sys_clk1_dclk_div", "sys_clk1_dclk_div"),
34876 + DT_CLK(NULL, "sys_clk2_dclk_div", "sys_clk2_dclk_div"),
34877 + DT_CLK(NULL, "dpll_abe_m2_ck", "dpll_abe_m2_ck"),
34878 + DT_CLK(NULL, "per_abe_x1_dclk_div", "per_abe_x1_dclk_div"),
34879 + DT_CLK(NULL, "dpll_abe_m3x2_ck", "dpll_abe_m3x2_ck"),
34880 + DT_CLK(NULL, "dpll_core_ck", "dpll_core_ck"),
34881 + DT_CLK(NULL, "dpll_core_x2_ck", "dpll_core_x2_ck"),
34882 + DT_CLK(NULL, "dpll_core_h12x2_ck", "dpll_core_h12x2_ck"),
34883 + DT_CLK(NULL, "mpu_dpll_hs_clk_div", "mpu_dpll_hs_clk_div"),
34884 + DT_CLK(NULL, "dpll_mpu_ck", "dpll_mpu_ck"),
34885 + DT_CLK(NULL, "dpll_mpu_m2_ck", "dpll_mpu_m2_ck"),
34886 + DT_CLK(NULL, "mpu_dclk_div", "mpu_dclk_div"),
34887 + DT_CLK(NULL, "dsp_dpll_hs_clk_div", "dsp_dpll_hs_clk_div"),
34888 + DT_CLK(NULL, "dpll_dsp_ck", "dpll_dsp_ck"),
34889 + DT_CLK(NULL, "dpll_dsp_m2_ck", "dpll_dsp_m2_ck"),
34890 + DT_CLK(NULL, "dsp_gclk_div", "dsp_gclk_div"),
34891 + DT_CLK(NULL, "iva_dpll_hs_clk_div", "iva_dpll_hs_clk_div"),
34892 + DT_CLK(NULL, "dpll_iva_ck", "dpll_iva_ck"),
34893 + DT_CLK(NULL, "dpll_iva_m2_ck", "dpll_iva_m2_ck"),
34894 + DT_CLK(NULL, "iva_dclk", "iva_dclk"),
34895 + DT_CLK(NULL, "dpll_gpu_ck", "dpll_gpu_ck"),
34896 + DT_CLK(NULL, "dpll_gpu_m2_ck", "dpll_gpu_m2_ck"),
34897 + DT_CLK(NULL, "gpu_dclk", "gpu_dclk"),
34898 + DT_CLK(NULL, "dpll_core_m2_ck", "dpll_core_m2_ck"),
34899 + DT_CLK(NULL, "core_dpll_out_dclk_div", "core_dpll_out_dclk_div"),
34900 + DT_CLK(NULL, "dpll_ddr_ck", "dpll_ddr_ck"),
34901 + DT_CLK(NULL, "dpll_ddr_m2_ck", "dpll_ddr_m2_ck"),
34902 + DT_CLK(NULL, "emif_phy_dclk_div", "emif_phy_dclk_div"),
34903 + DT_CLK(NULL, "dpll_gmac_ck", "dpll_gmac_ck"),
34904 + DT_CLK(NULL, "dpll_gmac_m2_ck", "dpll_gmac_m2_ck"),
34905 + DT_CLK(NULL, "gmac_250m_dclk_div", "gmac_250m_dclk_div"),
34906 + DT_CLK(NULL, "video2_dclk_div", "video2_dclk_div"),
34907 + DT_CLK(NULL, "video1_dclk_div", "video1_dclk_div"),
34908 + DT_CLK(NULL, "hdmi_dclk_div", "hdmi_dclk_div"),
34909 + DT_CLK(NULL, "per_dpll_hs_clk_div", "per_dpll_hs_clk_div"),
34910 + DT_CLK(NULL, "dpll_per_ck", "dpll_per_ck"),
34911 + DT_CLK(NULL, "dpll_per_m2_ck", "dpll_per_m2_ck"),
34912 + DT_CLK(NULL, "func_96m_aon_dclk_div", "func_96m_aon_dclk_div"),
34913 + DT_CLK(NULL, "usb_dpll_hs_clk_div", "usb_dpll_hs_clk_div"),
34914 + DT_CLK(NULL, "dpll_usb_ck", "dpll_usb_ck"),
34915 + DT_CLK(NULL, "dpll_usb_m2_ck", "dpll_usb_m2_ck"),
34916 + DT_CLK(NULL, "l3init_480m_dclk_div", "l3init_480m_dclk_div"),
34917 + DT_CLK(NULL, "usb_otg_dclk_div", "usb_otg_dclk_div"),
34918 + DT_CLK(NULL, "sata_dclk_div", "sata_dclk_div"),
34919 + DT_CLK(NULL, "dpll_pcie_ref_m2_ck", "dpll_pcie_ref_m2_ck"),
34920 + DT_CLK(NULL, "pcie2_dclk_div", "pcie2_dclk_div"),
34921 + DT_CLK(NULL, "pcie_dclk_div", "pcie_dclk_div"),
34922 + DT_CLK(NULL, "emu_dclk_div", "emu_dclk_div"),
34923 + DT_CLK(NULL, "secure_32k_dclk_div", "secure_32k_dclk_div"),
34924 + DT_CLK(NULL, "eve_dpll_hs_clk_div", "eve_dpll_hs_clk_div"),
34925 + DT_CLK(NULL, "dpll_eve_ck", "dpll_eve_ck"),
34926 + DT_CLK(NULL, "dpll_eve_m2_ck", "dpll_eve_m2_ck"),
34927 + DT_CLK(NULL, "eve_dclk_div", "eve_dclk_div"),
34928 + DT_CLK(NULL, "clkoutmux0_clk_mux", "clkoutmux0_clk_mux"),
34929 + DT_CLK(NULL, "clkoutmux1_clk_mux", "clkoutmux1_clk_mux"),
34930 + DT_CLK(NULL, "clkoutmux2_clk_mux", "clkoutmux2_clk_mux"),
34931 + DT_CLK(NULL, "custefuse_sys_gfclk_div", "custefuse_sys_gfclk_div"),
34932 + DT_CLK(NULL, "dpll_core_h13x2_ck", "dpll_core_h13x2_ck"),
34933 + DT_CLK(NULL, "dpll_core_h14x2_ck", "dpll_core_h14x2_ck"),
34934 + DT_CLK(NULL, "dpll_core_h22x2_ck", "dpll_core_h22x2_ck"),
34935 + DT_CLK(NULL, "dpll_core_h23x2_ck", "dpll_core_h23x2_ck"),
34936 + DT_CLK(NULL, "dpll_core_h24x2_ck", "dpll_core_h24x2_ck"),
34937 + DT_CLK(NULL, "dpll_ddr_x2_ck", "dpll_ddr_x2_ck"),
34938 + DT_CLK(NULL, "dpll_ddr_h11x2_ck", "dpll_ddr_h11x2_ck"),
34939 + DT_CLK(NULL, "dpll_dsp_x2_ck", "dpll_dsp_x2_ck"),
34940 + DT_CLK(NULL, "dpll_dsp_m3x2_ck", "dpll_dsp_m3x2_ck"),
34941 + DT_CLK(NULL, "dpll_gmac_x2_ck", "dpll_gmac_x2_ck"),
34942 + DT_CLK(NULL, "dpll_gmac_h11x2_ck", "dpll_gmac_h11x2_ck"),
34943 + DT_CLK(NULL, "dpll_gmac_h12x2_ck", "dpll_gmac_h12x2_ck"),
34944 + DT_CLK(NULL, "dpll_gmac_h13x2_ck", "dpll_gmac_h13x2_ck"),
34945 + DT_CLK(NULL, "dpll_gmac_m3x2_ck", "dpll_gmac_m3x2_ck"),
34946 + DT_CLK(NULL, "dpll_per_x2_ck", "dpll_per_x2_ck"),
34947 + DT_CLK(NULL, "dpll_per_h11x2_ck", "dpll_per_h11x2_ck"),
34948 + DT_CLK(NULL, "dpll_per_h12x2_ck", "dpll_per_h12x2_ck"),
34949 + DT_CLK(NULL, "dpll_per_h13x2_ck", "dpll_per_h13x2_ck"),
34950 + DT_CLK(NULL, "dpll_per_h14x2_ck", "dpll_per_h14x2_ck"),
34951 + DT_CLK(NULL, "dpll_per_m2x2_ck", "dpll_per_m2x2_ck"),
34952 + DT_CLK(NULL, "dpll_usb_clkdcoldo", "dpll_usb_clkdcoldo"),
34953 + DT_CLK(NULL, "eve_clk", "eve_clk"),
34954 + DT_CLK(NULL, "func_128m_clk", "func_128m_clk"),
34955 + DT_CLK(NULL, "func_12m_fclk", "func_12m_fclk"),
34956 + DT_CLK(NULL, "func_24m_clk", "func_24m_clk"),
34957 + DT_CLK(NULL, "func_48m_fclk", "func_48m_fclk"),
34958 + DT_CLK(NULL, "func_96m_fclk", "func_96m_fclk"),
34959 + DT_CLK(NULL, "gmii_m_clk_div", "gmii_m_clk_div"),
34960 + DT_CLK(NULL, "hdmi_clk2_div", "hdmi_clk2_div"),
34961 + DT_CLK(NULL, "hdmi_div_clk", "hdmi_div_clk"),
34962 + DT_CLK(NULL, "hdmi_dpll_clk_mux", "hdmi_dpll_clk_mux"),
34963 + DT_CLK(NULL, "l3_iclk_div", "l3_iclk_div"),
34964 + DT_CLK(NULL, "l3init_60m_fclk", "l3init_60m_fclk"),
34965 + DT_CLK(NULL, "l4_root_clk_div", "l4_root_clk_div"),
34966 + DT_CLK(NULL, "mlb_clk", "mlb_clk"),
34967 + DT_CLK(NULL, "mlbp_clk", "mlbp_clk"),
34968 + DT_CLK(NULL, "per_abe_x1_gfclk2_div", "per_abe_x1_gfclk2_div"),
34969 + DT_CLK(NULL, "timer_sys_clk_div", "timer_sys_clk_div"),
34970 + DT_CLK(NULL, "video1_clk2_div", "video1_clk2_div"),
34971 + DT_CLK(NULL, "video1_div_clk", "video1_div_clk"),
34972 + DT_CLK(NULL, "video1_dpll_clk_mux", "video1_dpll_clk_mux"),
34973 + DT_CLK(NULL, "video2_clk2_div", "video2_clk2_div"),
34974 + DT_CLK(NULL, "video2_div_clk", "video2_div_clk"),
34975 + DT_CLK(NULL, "video2_dpll_clk_mux", "video2_dpll_clk_mux"),
34976 + DT_CLK(NULL, "wkupaon_iclk_mux", "wkupaon_iclk_mux"),
34977 + DT_CLK(NULL, "dss_32khz_clk", "dss_32khz_clk"),
34978 + DT_CLK(NULL, "dss_48mhz_clk", "dss_48mhz_clk"),
34979 + DT_CLK(NULL, "dss_dss_clk", "dss_dss_clk"),
34980 + DT_CLK(NULL, "dss_hdmi_clk", "dss_hdmi_clk"),
34981 + DT_CLK(NULL, "dss_video1_clk", "dss_video1_clk"),
34982 + DT_CLK(NULL, "dss_video2_clk", "dss_video2_clk"),
34983 + DT_CLK(NULL, "dss_deshdcp_clk", "dss_deshdcp_clk"),
34984 + DT_CLK(NULL, "gpio1_dbclk", "gpio1_dbclk"),
34985 + DT_CLK(NULL, "gpio2_dbclk", "gpio2_dbclk"),
34986 + DT_CLK(NULL, "gpio3_dbclk", "gpio3_dbclk"),
34987 + DT_CLK(NULL, "gpio4_dbclk", "gpio4_dbclk"),
34988 + DT_CLK(NULL, "gpio5_dbclk", "gpio5_dbclk"),
34989 + DT_CLK(NULL, "gpio6_dbclk", "gpio6_dbclk"),
34990 + DT_CLK(NULL, "gpio7_dbclk", "gpio7_dbclk"),
34991 + DT_CLK(NULL, "gpio8_dbclk", "gpio8_dbclk"),
34992 + DT_CLK(NULL, "mmc1_clk32k", "mmc1_clk32k"),
34993 + DT_CLK(NULL, "mmc2_clk32k", "mmc2_clk32k"),
34994 + DT_CLK(NULL, "mmc3_clk32k", "mmc3_clk32k"),
34995 + DT_CLK(NULL, "mmc4_clk32k", "mmc4_clk32k"),
34996 + DT_CLK(NULL, "sata_ref_clk", "sata_ref_clk"),
34997 + DT_CLK(NULL, "usb_otg_ss1_refclk960m", "usb_otg_ss1_refclk960m"),
34998 + DT_CLK(NULL, "usb_otg_ss2_refclk960m", "usb_otg_ss2_refclk960m"),
34999 + DT_CLK(NULL, "usb_phy1_always_on_clk32k", "usb_phy1_always_on_clk32k"),
35000 + DT_CLK(NULL, "usb_phy2_always_on_clk32k", "usb_phy2_always_on_clk32k"),
35001 + DT_CLK(NULL, "usb_phy3_always_on_clk32k", "usb_phy3_always_on_clk32k"),
35002 + DT_CLK(NULL, "atl_dpll_clk_mux", "atl_dpll_clk_mux"),
35003 + DT_CLK(NULL, "atl_gfclk_mux", "atl_gfclk_mux"),
35004 + DT_CLK(NULL, "dcan1_sys_clk_mux", "dcan1_sys_clk_mux"),
35005 + DT_CLK(NULL, "gmac_gmii_ref_clk_div", "gmac_gmii_ref_clk_div"),
35006 + DT_CLK(NULL, "gmac_rft_clk_mux", "gmac_rft_clk_mux"),
35007 + DT_CLK(NULL, "gpu_core_gclk_mux", "gpu_core_gclk_mux"),
35008 + DT_CLK(NULL, "gpu_hyd_gclk_mux", "gpu_hyd_gclk_mux"),
35009 + DT_CLK(NULL, "ipu1_gfclk_mux", "ipu1_gfclk_mux"),
35010 + DT_CLK(NULL, "l3instr_ts_gclk_div", "l3instr_ts_gclk_div"),
35011 + DT_CLK(NULL, "mcasp1_ahclkr_mux", "mcasp1_ahclkr_mux"),
35012 + DT_CLK(NULL, "mcasp1_ahclkx_mux", "mcasp1_ahclkx_mux"),
35013 + DT_CLK(NULL, "mcasp1_aux_gfclk_mux", "mcasp1_aux_gfclk_mux"),
35014 + DT_CLK(NULL, "mcasp2_ahclkr_mux", "mcasp2_ahclkr_mux"),
35015 + DT_CLK(NULL, "mcasp2_ahclkx_mux", "mcasp2_ahclkx_mux"),
35016 + DT_CLK(NULL, "mcasp2_aux_gfclk_mux", "mcasp2_aux_gfclk_mux"),
35017 + DT_CLK(NULL, "mcasp3_ahclkx_mux", "mcasp3_ahclkx_mux"),
35018 + DT_CLK(NULL, "mcasp3_aux_gfclk_mux", "mcasp3_aux_gfclk_mux"),
35019 + DT_CLK(NULL, "mcasp4_ahclkx_mux", "mcasp4_ahclkx_mux"),
35020 + DT_CLK(NULL, "mcasp4_aux_gfclk_mux", "mcasp4_aux_gfclk_mux"),
35021 + DT_CLK(NULL, "mcasp5_ahclkx_mux", "mcasp5_ahclkx_mux"),
35022 + DT_CLK(NULL, "mcasp5_aux_gfclk_mux", "mcasp5_aux_gfclk_mux"),
35023 + DT_CLK(NULL, "mcasp6_ahclkx_mux", "mcasp6_ahclkx_mux"),
35024 + DT_CLK(NULL, "mcasp6_aux_gfclk_mux", "mcasp6_aux_gfclk_mux"),
35025 + DT_CLK(NULL, "mcasp7_ahclkx_mux", "mcasp7_ahclkx_mux"),
35026 + DT_CLK(NULL, "mcasp7_aux_gfclk_mux", "mcasp7_aux_gfclk_mux"),
35027 + DT_CLK(NULL, "mcasp8_ahclk_mux", "mcasp8_ahclk_mux"),
35028 + DT_CLK(NULL, "mcasp8_aux_gfclk_mux", "mcasp8_aux_gfclk_mux"),
35029 + DT_CLK(NULL, "mmc1_fclk_mux", "mmc1_fclk_mux"),
35030 + DT_CLK(NULL, "mmc1_fclk_div", "mmc1_fclk_div"),
35031 + DT_CLK(NULL, "mmc2_fclk_mux", "mmc2_fclk_mux"),
35032 + DT_CLK(NULL, "mmc2_fclk_div", "mmc2_fclk_div"),
35033 + DT_CLK(NULL, "mmc3_gfclk_mux", "mmc3_gfclk_mux"),
35034 + DT_CLK(NULL, "mmc3_gfclk_div", "mmc3_gfclk_div"),
35035 + DT_CLK(NULL, "mmc4_gfclk_mux", "mmc4_gfclk_mux"),
35036 + DT_CLK(NULL, "mmc4_gfclk_div", "mmc4_gfclk_div"),
35037 + DT_CLK(NULL, "qspi_gfclk_mux", "qspi_gfclk_mux"),
35038 + DT_CLK(NULL, "qspi_gfclk_div", "qspi_gfclk_div"),
35039 + DT_CLK(NULL, "timer10_gfclk_mux", "timer10_gfclk_mux"),
35040 + DT_CLK(NULL, "timer11_gfclk_mux", "timer11_gfclk_mux"),
35041 + DT_CLK(NULL, "timer13_gfclk_mux", "timer13_gfclk_mux"),
35042 + DT_CLK(NULL, "timer14_gfclk_mux", "timer14_gfclk_mux"),
35043 + DT_CLK(NULL, "timer15_gfclk_mux", "timer15_gfclk_mux"),
35044 + DT_CLK(NULL, "timer16_gfclk_mux", "timer16_gfclk_mux"),
35045 + DT_CLK(NULL, "timer1_gfclk_mux", "timer1_gfclk_mux"),
35046 + DT_CLK(NULL, "timer2_gfclk_mux", "timer2_gfclk_mux"),
35047 + DT_CLK(NULL, "timer3_gfclk_mux", "timer3_gfclk_mux"),
35048 + DT_CLK(NULL, "timer4_gfclk_mux", "timer4_gfclk_mux"),
35049 + DT_CLK(NULL, "timer5_gfclk_mux", "timer5_gfclk_mux"),
35050 + DT_CLK(NULL, "timer6_gfclk_mux", "timer6_gfclk_mux"),
35051 + DT_CLK(NULL, "timer7_gfclk_mux", "timer7_gfclk_mux"),
35052 + DT_CLK(NULL, "timer8_gfclk_mux", "timer8_gfclk_mux"),
35053 + DT_CLK(NULL, "timer9_gfclk_mux", "timer9_gfclk_mux"),
35054 + DT_CLK(NULL, "uart10_gfclk_mux", "uart10_gfclk_mux"),
35055 + DT_CLK(NULL, "uart1_gfclk_mux", "uart1_gfclk_mux"),
35056 + DT_CLK(NULL, "uart2_gfclk_mux", "uart2_gfclk_mux"),
35057 + DT_CLK(NULL, "uart3_gfclk_mux", "uart3_gfclk_mux"),
35058 + DT_CLK(NULL, "uart4_gfclk_mux", "uart4_gfclk_mux"),
35059 + DT_CLK(NULL, "uart5_gfclk_mux", "uart5_gfclk_mux"),
35060 + DT_CLK(NULL, "uart6_gfclk_mux", "uart6_gfclk_mux"),
35061 + DT_CLK(NULL, "uart7_gfclk_mux", "uart7_gfclk_mux"),
35062 + DT_CLK(NULL, "uart8_gfclk_mux", "uart8_gfclk_mux"),
35063 + DT_CLK(NULL, "uart9_gfclk_mux", "uart9_gfclk_mux"),
35064 + DT_CLK(NULL, "vip1_gclk_mux", "vip1_gclk_mux"),
35065 + DT_CLK(NULL, "vip2_gclk_mux", "vip2_gclk_mux"),
35066 + DT_CLK(NULL, "vip3_gclk_mux", "vip3_gclk_mux"),
35067 + DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"),
35068 + DT_CLK("4ae18000.timer", "timer_sys_ck", "sys_clkin2"),
35069 + DT_CLK("48032000.timer", "timer_sys_ck", "sys_clkin2"),
35070 + DT_CLK("48034000.timer", "timer_sys_ck", "sys_clkin2"),
35071 + DT_CLK("48036000.timer", "timer_sys_ck", "sys_clkin2"),
35072 + DT_CLK("4803e000.timer", "timer_sys_ck", "sys_clkin2"),
35073 + DT_CLK("48086000.timer", "timer_sys_ck", "sys_clkin2"),
35074 + DT_CLK("48088000.timer", "timer_sys_ck", "sys_clkin2"),
35075 + DT_CLK("48820000.timer", "timer_sys_ck", "timer_sys_clk_div"),
35076 + DT_CLK("48822000.timer", "timer_sys_ck", "timer_sys_clk_div"),
35077 + DT_CLK("48824000.timer", "timer_sys_ck", "timer_sys_clk_div"),
35078 + DT_CLK("48826000.timer", "timer_sys_ck", "timer_sys_clk_div"),
35079 + DT_CLK(NULL, "sys_clkin", "sys_clkin1"),
35080 + { .node_name = NULL },
35081 +};
35082 +
35083 +int __init dra7xx_clk_init(void)
35084 +{
35085 + int rc;
35086 + struct clk *abe_dpll_mux, *sys_clkin2, *dpll_ck, *deshdcp_clk;
35087 +
35088 + of_clk_init(NULL);
35089 +
35090 + omap_dt_clocks_register(dra7xx_clks);
35091 +
35092 + omap2_clk_disable_autoidle_all();
35093 +
35094 + abe_dpll_mux = clk_get_sys(NULL, "abe_dpll_sys_clk_mux");
35095 + sys_clkin2 = clk_get_sys(NULL, "sys_clkin2");
35096 + dpll_ck = clk_get_sys(NULL, "dpll_abe_ck");
35097 +
35098 + rc = clk_set_parent(abe_dpll_mux, sys_clkin2);
35099 + if (!rc)
35100 + rc = clk_set_rate(dpll_ck, DRA7_DPLL_ABE_DEFFREQ);
35101 + if (rc)
35102 + pr_err("%s: failed to configure ABE DPLL!\n", __func__);
35103 +
35104 + dpll_ck = clk_get_sys(NULL, "dpll_gmac_ck");
35105 + rc = clk_set_rate(dpll_ck, DRA7_DPLL_GMAC_DEFFREQ);
35106 + if (rc)
35107 + pr_err("%s: failed to configure GMAC DPLL!\n", __func__);
35108 +
35109 + dpll_ck = clk_get_sys(NULL, "dpll_usb_ck");
35110 + rc = clk_set_rate(dpll_ck, DRA7_DPLL_USB_DEFFREQ);
35111 + if (rc)
35112 + pr_err("%s: failed to configure USB DPLL!\n", __func__);
35113 +
35114 + dpll_ck = clk_get_sys(NULL, "dpll_usb_m2_ck");
35115 + rc = clk_set_rate(dpll_ck, DRA7_DPLL_USB_DEFFREQ/2);
35116 + if (rc)
35117 + pr_err("%s: failed to set USB_DPLL M2 OUT\n", __func__);
35118 +
35119 + deshdcp_clk = clk_get_sys(NULL, "dss_deshdcp_clk");
35120 + rc = clk_prepare_enable(deshdcp_clk);
35121 + if (rc)
35122 + pr_err("%s: failed to enable DESHDCP clock\n", __func__);
35123 +
35124 + return rc;
35125 +}
35126 --- /dev/null
35127 +++ b/drivers/clk/ti/clk.c
35128 @@ -0,0 +1,52 @@
35129 +/*
35130 + * TI clock support
35131 + *
35132 + * Copyright (C) 2013 Texas Instruments, Inc.
35133 + *
35134 + * Tero Kristo <t-kristo@ti.com>
35135 + *
35136 + * This program is free software; you can redistribute it and/or modify
35137 + * it under the terms of the GNU General Public License version 2 as
35138 + * published by the Free Software Foundation.
35139 + *
35140 + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
35141 + * kind, whether express or implied; without even the implied warranty
35142 + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
35143 + * GNU General Public License for more details.
35144 + */
35145 +
35146 +#include <linux/clk-provider.h>
35147 +#include <linux/clkdev.h>
35148 +#include <linux/clk/ti.h>
35149 +#include <linux/of.h>
35150 +
35151 +/**
35152 + * omap_dt_clocks_register - register DT duplicate clocks during boot
35153 + * @oclks: list of clocks to register
35154 + *
35155 + * Register duplicate or non-standard DT clock entries during boot. By
35156 + * default, DT clocks are found based on their node name. If any
35157 + * additional con-id / dev-id -> clock mapping is required, use this
35158 + * function to list these.
35159 + */
35160 +void __init omap_dt_clocks_register(struct omap_dt_clk oclks[])
35161 +{
35162 + struct omap_dt_clk *c;
35163 + struct device_node *node;
35164 + struct clk *clk;
35165 + struct of_phandle_args clkspec;
35166 +
35167 + for (c = oclks; c->node_name != NULL; c++) {
35168 + node = of_find_node_by_name(NULL, c->node_name);
35169 + clkspec.np = node;
35170 + clk = of_clk_get_from_provider(&clkspec);
35171 +
35172 + if (!IS_ERR(clk)) {
35173 + c->lk.clk = clk;
35174 + clkdev_add(&c->lk);
35175 + } else {
35176 + pr_warn("%s: failed to lookup clock node %s\n",
35177 + __func__, c->node_name);
35178 + }
35179 + }
35180 +}
35181 --- /dev/null
35182 +++ b/drivers/clk/ti/clockdomain.c
35183 @@ -0,0 +1,46 @@
35184 +/*
35185 + * OMAP clockdomain support
35186 + *
35187 + * Copyright (C) 2013 Texas Instruments, Inc.
35188 + *
35189 + * Tero Kristo <t-kristo@ti.com>
35190 + *
35191 + * This program is free software; you can redistribute it and/or modify
35192 + * it under the terms of the GNU General Public License version 2 as
35193 + * published by the Free Software Foundation.
35194 + *
35195 + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
35196 + * kind, whether express or implied; without even the implied warranty
35197 + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
35198 + * GNU General Public License for more details.
35199 + */
35200 +
35201 +#include <linux/clk-provider.h>
35202 +#include <linux/slab.h>
35203 +#include <linux/of.h>
35204 +#include <linux/of_address.h>
35205 +#include <linux/clk/ti.h>
35206 +
35207 +void __init of_omap_clockdomain_setup(struct device_node *node)
35208 +{
35209 + struct clk *clk;
35210 + struct clk_hw *clk_hw;
35211 + const char *clkdm_name = node->name;
35212 + int i;
35213 + int num_clks;
35214 +
35215 + num_clks = of_count_phandle_with_args(node, "clocks", "#clock-cells");
35216 +
35217 + for (i = 0; i < num_clks; i++) {
35218 + clk = of_clk_get(node, i);
35219 + if (__clk_get_flags(clk) & CLK_IS_BASIC) {
35220 + pr_warn("%s: can't setup clkdm for basic clk %s\n",
35221 + __func__, __clk_get_name(clk));
35222 + continue;
35223 + }
35224 + clk_hw = __clk_get_hw(clk);
35225 + to_clk_hw_omap(clk_hw)->clkdm_name = clkdm_name;
35226 + omap2_init_clk_clkdm(clk_hw);
35227 + }
35228 +}
35229 +CLK_OF_DECLARE(omap_clockdomain, "ti,clockdomain", of_omap_clockdomain_setup);
35230 --- /dev/null
35231 +++ b/drivers/clk/ti/dpll.c
35232 @@ -0,0 +1,476 @@
35233 +/*
35234 + * OMAP DPLL clock support
35235 + *
35236 + * Copyright (C) 2013 Texas Instruments, Inc.
35237 + *
35238 + * Tero Kristo <t-kristo@ti.com>
35239 + *
35240 + * This program is free software; you can redistribute it and/or modify
35241 + * it under the terms of the GNU General Public License version 2 as
35242 + * published by the Free Software Foundation.
35243 + *
35244 + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
35245 + * kind, whether express or implied; without even the implied warranty
35246 + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
35247 + * GNU General Public License for more details.
35248 + */
35249 +
35250 +#include <linux/clk-provider.h>
35251 +#include <linux/slab.h>
35252 +#include <linux/err.h>
35253 +#include <linux/of.h>
35254 +#include <linux/of_address.h>
35255 +#include <linux/clk/ti.h>
35256 +
35257 +static const struct clk_ops dpll_m4xen_ck_ops = {
35258 + .enable = &omap3_noncore_dpll_enable,
35259 + .disable = &omap3_noncore_dpll_disable,
35260 + .recalc_rate = &omap4_dpll_regm4xen_recalc,
35261 + .round_rate = &omap4_dpll_regm4xen_round_rate,
35262 + .set_rate = &omap3_noncore_dpll_set_rate,
35263 + .get_parent = &omap2_init_dpll_parent,
35264 +};
35265 +
35266 +static const struct clk_ops dpll_core_ck_ops = {
35267 + .recalc_rate = &omap3_dpll_recalc,
35268 + .get_parent = &omap2_init_dpll_parent,
35269 +};
35270 +
35271 +static const struct clk_ops omap3_dpll_core_ck_ops = {
35272 + .init = &omap2_init_clk_clkdm,
35273 + .get_parent = &omap2_init_dpll_parent,
35274 + .recalc_rate = &omap3_dpll_recalc,
35275 + .round_rate = &omap2_dpll_round_rate,
35276 +};
35277 +
35278 +static const struct clk_ops dpll_ck_ops = {
35279 + .enable = &omap3_noncore_dpll_enable,
35280 + .disable = &omap3_noncore_dpll_disable,
35281 + .recalc_rate = &omap3_dpll_recalc,
35282 + .round_rate = &omap2_dpll_round_rate,
35283 + .set_rate = &omap3_noncore_dpll_set_rate,
35284 + .get_parent = &omap2_init_dpll_parent,
35285 + .init = &omap2_init_clk_clkdm,
35286 +};
35287 +
35288 +static const struct clk_ops dpll_no_gate_ck_ops = {
35289 + .recalc_rate = &omap3_dpll_recalc,
35290 + .get_parent = &omap2_init_dpll_parent,
35291 + .round_rate = &omap2_dpll_round_rate,
35292 + .set_rate = &omap3_noncore_dpll_set_rate,
35293 +};
35294 +
35295 +static const struct clk_ops omap3_dpll_ck_ops = {
35296 + .init = &omap2_init_clk_clkdm,
35297 + .enable = &omap3_noncore_dpll_enable,
35298 + .disable = &omap3_noncore_dpll_disable,
35299 + .get_parent = &omap2_init_dpll_parent,
35300 + .recalc_rate = &omap3_dpll_recalc,
35301 + .set_rate = &omap3_noncore_dpll_set_rate,
35302 + .round_rate = &omap2_dpll_round_rate,
35303 +};
35304 +
35305 +static const struct clk_ops omap3_dpll_per_ck_ops = {
35306 + .init = &omap2_init_clk_clkdm,
35307 + .enable = &omap3_noncore_dpll_enable,
35308 + .disable = &omap3_noncore_dpll_disable,
35309 + .get_parent = &omap2_init_dpll_parent,
35310 + .recalc_rate = &omap3_dpll_recalc,
35311 + .set_rate = &omap3_dpll4_set_rate,
35312 + .round_rate = &omap2_dpll_round_rate,
35313 +};
35314 +
35315 +static const struct clk_ops dpll_x2_ck_ops = {
35316 + .recalc_rate = &omap3_clkoutx2_recalc,
35317 +};
35318 +
35319 +static struct clk *omap_clk_register_dpll(struct device *dev, const char *name,
35320 + const char **parent_names, int num_parents, unsigned long flags,
35321 + struct dpll_data *dpll_data, const char *clkdm_name,
35322 + const struct clk_ops *ops)
35323 +{
35324 + struct clk *clk;
35325 + struct clk_init_data init = { 0 };
35326 + struct clk_hw_omap *clk_hw;
35327 +
35328 + /* allocate the divider */
35329 + clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
35330 + if (!clk_hw) {
35331 + pr_err("%s: could not allocate clk_hw_omap\n", __func__);
35332 + return ERR_PTR(-ENOMEM);
35333 + }
35334 +
35335 + clk_hw->dpll_data = dpll_data;
35336 + clk_hw->ops = &clkhwops_omap3_dpll;
35337 + clk_hw->clkdm_name = clkdm_name;
35338 + clk_hw->hw.init = &init;
35339 +
35340 + init.name = name;
35341 + init.ops = ops;
35342 + init.flags = flags;
35343 + init.parent_names = parent_names;
35344 + init.num_parents = num_parents;
35345 +
35346 + /* register the clock */
35347 + clk = clk_register(dev, &clk_hw->hw);
35348 +
35349 + if (IS_ERR(clk))
35350 + kfree(clk_hw);
35351 + else
35352 + omap2_init_clk_hw_omap_clocks(clk);
35353 +
35354 + return clk;
35355 +}
35356 +
35357 +static struct clk *omap_clk_register_dpll_x2(struct device *dev,
35358 + const char *name, const char *parent_name, void __iomem *reg,
35359 + const struct clk_ops *ops)
35360 +{
35361 + struct clk *clk;
35362 + struct clk_init_data init = { 0 };
35363 + struct clk_hw_omap *clk_hw;
35364 +
35365 + if (!parent_name) {
35366 + pr_err("%s: dpll_x2 must have parent\n", __func__);
35367 + return ERR_PTR(-EINVAL);
35368 + }
35369 +
35370 + clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
35371 + if (!clk_hw) {
35372 + pr_err("%s: could not allocate clk_hw_omap\n", __func__);
35373 + return ERR_PTR(-ENOMEM);
35374 + }
35375 +
35376 + clk_hw->ops = &clkhwops_omap4_dpllmx;
35377 + clk_hw->clksel_reg = reg;
35378 + clk_hw->hw.init = &init;
35379 +
35380 + init.name = name;
35381 + init.ops = ops;
35382 + init.parent_names = &parent_name;
35383 + init.num_parents = 1;
35384 +
35385 + /* register the clock */
35386 + clk = clk_register(dev, &clk_hw->hw);
35387 +
35388 + if (IS_ERR(clk))
35389 + kfree(clk_hw);
35390 + else
35391 + omap2_init_clk_hw_omap_clocks(clk);
35392 +
35393 + return clk;
35394 +}
35395 +
35396 +/**
35397 + * of_omap_dpll_setup() - Setup function for OMAP DPLL clocks
35398 + *
35399 + * @node: device node containing the DPLL info
35400 + * @ops: ops for the DPLL
35401 + * @ddt: DPLL data template to use
35402 + */
35403 +static void __init of_omap_dpll_setup(struct device_node *node,
35404 + const struct clk_ops *ops,
35405 + const struct dpll_data *ddt)
35406 +{
35407 + struct clk *clk;
35408 + const char *clk_name = node->name;
35409 + int num_parents;
35410 + const char **parent_names = NULL;
35411 + const char *clkdm_name = NULL;
35412 + u8 dpll_flags = 0;
35413 + struct dpll_data *dd;
35414 + int i;
35415 + u32 val;
35416 +
35417 + dd = kzalloc(sizeof(*dd), GFP_KERNEL);
35418 + if (!dd) {
35419 + pr_err("%s: could not allocate dpll_data\n", __func__);
35420 + return;
35421 + }
35422 +
35423 + memcpy(dd, ddt, sizeof(*dd));
35424 +
35425 + of_property_read_string(node, "clock-output-names", &clk_name);
35426 +
35427 + num_parents = of_clk_get_parent_count(node);
35428 + if (num_parents < 1) {
35429 + pr_err("%s: omap dpll %s must have parent(s)\n",
35430 + __func__, node->name);
35431 + goto cleanup;
35432 + }
35433 +
35434 + parent_names = kzalloc(sizeof(char *) * num_parents, GFP_KERNEL);
35435 +
35436 + for (i = 0; i < num_parents; i++)
35437 + parent_names[i] = of_clk_get_parent_name(node, i);
35438 +
35439 + dd->clk_ref = of_clk_get(node, 0);
35440 + dd->clk_bypass = of_clk_get(node, 1);
35441 +
35442 + if (IS_ERR(dd->clk_ref)) {
35443 + pr_err("%s: ti,clk-ref for %s not found\n", __func__,
35444 + clk_name);
35445 + goto cleanup;
35446 + }
35447 +
35448 + if (IS_ERR(dd->clk_bypass)) {
35449 + pr_err("%s: ti,clk-bypass for %s not found\n", __func__,
35450 + clk_name);
35451 + goto cleanup;
35452 + }
35453 +
35454 + of_property_read_string(node, "ti,clkdm-name", &clkdm_name);
35455 +
35456 + i = of_property_match_string(node, "reg-names", "control");
35457 + if (i >= 0)
35458 + dd->control_reg = of_iomap(node, i);
35459 +
35460 + i = of_property_match_string(node, "reg-names", "idlest");
35461 + if (i >= 0)
35462 + dd->idlest_reg = of_iomap(node, i);
35463 +
35464 + i = of_property_match_string(node, "reg-names", "autoidle");
35465 + if (i >= 0)
35466 + dd->autoidle_reg = of_iomap(node, i);
35467 +
35468 + i = of_property_match_string(node, "reg-names", "mult-div1");
35469 + if (i >= 0)
35470 + dd->mult_div1_reg = of_iomap(node, i);
35471 +
35472 + if (!of_property_read_u32(node, "ti,modes", &val))
35473 + dd->modes = val;
35474 +
35475 + clk = omap_clk_register_dpll(NULL, clk_name, parent_names,
35476 + num_parents, dpll_flags, dd,
35477 + clkdm_name, ops);
35478 +
35479 + if (!IS_ERR(clk))
35480 + of_clk_add_provider(node, of_clk_src_simple_get, clk);
35481 + return;
35482 +
35483 +cleanup:
35484 + kfree(dd);
35485 + kfree(parent_names);
35486 + return;
35487 +}
35488 +
35489 +static void __init of_omap_dpll_x2_setup(struct device_node *node)
35490 +{
35491 + struct clk *clk;
35492 + const char *clk_name = node->name;
35493 + void __iomem *reg;
35494 + const char *parent_name;
35495 +
35496 + of_property_read_string(node, "clock-output-names", &clk_name);
35497 +
35498 + parent_name = of_clk_get_parent_name(node, 0);
35499 +
35500 + reg = of_iomap(node, 0);
35501 +
35502 + clk = omap_clk_register_dpll_x2(NULL, clk_name, parent_name,
35503 + reg, &dpll_x2_ck_ops);
35504 +
35505 + if (!IS_ERR(clk))
35506 + of_clk_add_provider(node, of_clk_src_simple_get, clk);
35507 +}
35508 +CLK_OF_DECLARE(omap_dpll_x2_clock, "ti,omap4-dpll-x2-clock",
35509 + of_omap_dpll_x2_setup);
35510 +
35511 +static void __init of_omap3_dpll_setup(struct device_node *node)
35512 +{
35513 + const struct dpll_data dd = {
35514 + .idlest_mask = 0x1,
35515 + .enable_mask = 0x7,
35516 + .autoidle_mask = 0x7,
35517 + .mult_mask = 0x7ff << 8,
35518 + .div1_mask = 0x7f,
35519 + .max_multiplier = 2047,
35520 + .max_divider = 128,
35521 + .min_divider = 1,
35522 + .freqsel_mask = 0xf0,
35523 + .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
35524 + };
35525 +
35526 + of_omap_dpll_setup(node, &omap3_dpll_ck_ops, &dd);
35527 +}
35528 +CLK_OF_DECLARE(omap3_dpll_clock, "ti,omap3-dpll-clock", of_omap3_dpll_setup);
35529 +
35530 +static void __init of_omap3_core_dpll_setup(struct device_node *node)
35531 +{
35532 + const struct dpll_data dd = {
35533 + .idlest_mask = 0x1,
35534 + .enable_mask = 0x7,
35535 + .autoidle_mask = 0x7,
35536 + .mult_mask = 0x7ff << 16,
35537 + .div1_mask = 0x7f << 8,
35538 + .max_multiplier = 2047,
35539 + .max_divider = 128,
35540 + .min_divider = 1,
35541 + .freqsel_mask = 0xf0,
35542 + };
35543 +
35544 + of_omap_dpll_setup(node, &omap3_dpll_core_ck_ops, &dd);
35545 +}
35546 +CLK_OF_DECLARE(omap3_core_dpll_clock, "ti,omap3-dpll-core-clock",
35547 + of_omap3_core_dpll_setup);
35548 +
35549 +static void __init of_omap3_per_dpll_setup(struct device_node *node)
35550 +{
35551 + const struct dpll_data dd = {
35552 + .idlest_mask = 0x1 << 1,
35553 + .enable_mask = 0x7 << 16,
35554 + .autoidle_mask = 0x7 << 3,
35555 + .mult_mask = 0x7ff << 8,
35556 + .div1_mask = 0x7f,
35557 + .max_multiplier = 2047,
35558 + .max_divider = 128,
35559 + .min_divider = 1,
35560 + .freqsel_mask = 0xf00000,
35561 + .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
35562 + };
35563 +
35564 + of_omap_dpll_setup(node, &omap3_dpll_per_ck_ops, &dd);
35565 +}
35566 +CLK_OF_DECLARE(omap3_per_dpll_clock, "ti,omap3-dpll-per-clock",
35567 + of_omap3_per_dpll_setup);
35568 +
35569 +static void __init of_omap3_per_jtype_dpll_setup(struct device_node *node)
35570 +{
35571 + const struct dpll_data dd = {
35572 + .idlest_mask = 0x1 << 1,
35573 + .enable_mask = 0x7 << 16,
35574 + .autoidle_mask = 0x7 << 3,
35575 + .mult_mask = 0xfff << 8,
35576 + .div1_mask = 0x7f,
35577 + .max_multiplier = 4095,
35578 + .max_divider = 128,
35579 + .min_divider = 1,
35580 + .sddiv_mask = 0xff << 24,
35581 + .dco_mask = 0xe << 20,
35582 + .flags = DPLL_J_TYPE,
35583 + .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
35584 + };
35585 +
35586 + of_omap_dpll_setup(node, &omap3_dpll_per_ck_ops, &dd);
35587 +}
35588 +CLK_OF_DECLARE(omap3_per_jtype_dpll_clock, "ti,omap3-dpll-per-j-type-clock",
35589 + of_omap3_per_jtype_dpll_setup);
35590 +
35591 +static void __init of_omap4_dpll_setup(struct device_node *node)
35592 +{
35593 + const struct dpll_data dd = {
35594 + .idlest_mask = 0x1,
35595 + .enable_mask = 0x7,
35596 + .autoidle_mask = 0x7,
35597 + .mult_mask = 0x7ff << 8,
35598 + .div1_mask = 0x7f,
35599 + .max_multiplier = 2047,
35600 + .max_divider = 128,
35601 + .min_divider = 1,
35602 + .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
35603 + };
35604 +
35605 + of_omap_dpll_setup(node, &dpll_ck_ops, &dd);
35606 +}
35607 +CLK_OF_DECLARE(omap4_dpll_clock, "ti,omap4-dpll-clock", of_omap4_dpll_setup);
35608 +
35609 +static void __init of_omap4_core_dpll_setup(struct device_node *node)
35610 +{
35611 + const struct dpll_data dd = {
35612 + .idlest_mask = 0x1,
35613 + .enable_mask = 0x7,
35614 + .autoidle_mask = 0x7,
35615 + .mult_mask = 0x7ff << 8,
35616 + .div1_mask = 0x7f,
35617 + .max_multiplier = 2047,
35618 + .max_divider = 128,
35619 + .min_divider = 1,
35620 + .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
35621 + };
35622 +
35623 + of_omap_dpll_setup(node, &dpll_core_ck_ops, &dd);
35624 +}
35625 +CLK_OF_DECLARE(omap4_core_dpll_clock, "ti,omap4-dpll-core-clock",
35626 + of_omap4_core_dpll_setup);
35627 +
35628 +static void __init of_omap4_m4xen_dpll_setup(struct device_node *node)
35629 +{
35630 + const struct dpll_data dd = {
35631 + .idlest_mask = 0x1,
35632 + .enable_mask = 0x7,
35633 + .autoidle_mask = 0x7,
35634 + .mult_mask = 0x7ff << 8,
35635 + .div1_mask = 0x7f,
35636 + .max_multiplier = 2047,
35637 + .max_divider = 128,
35638 + .min_divider = 1,
35639 + .m4xen_mask = 0x800,
35640 + .lpmode_mask = 1 << 10,
35641 + .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
35642 + };
35643 +
35644 + of_omap_dpll_setup(node, &dpll_m4xen_ck_ops, &dd);
35645 +}
35646 +CLK_OF_DECLARE(omap4_m4xen_dpll_clock, "ti,omap4-dpll-m4xen-clock",
35647 + of_omap4_m4xen_dpll_setup);
35648 +
35649 +static void __init of_omap4_jtype_dpll_setup(struct device_node *node)
35650 +{
35651 + const struct dpll_data dd = {
35652 + .idlest_mask = 0x1,
35653 + .enable_mask = 0x7,
35654 + .autoidle_mask = 0x7,
35655 + .mult_mask = 0xfff << 8,
35656 + .div1_mask = 0xff,
35657 + .max_multiplier = 4095,
35658 + .max_divider = 256,
35659 + .min_divider = 1,
35660 + .sddiv_mask = 0xff << 24,
35661 + .flags = DPLL_J_TYPE,
35662 + .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
35663 + };
35664 +
35665 + of_omap_dpll_setup(node, &dpll_m4xen_ck_ops, &dd);
35666 +}
35667 +CLK_OF_DECLARE(omap4_jtype_dpll_clock, "ti,omap4-dpll-j-type-clock",
35668 + of_omap4_jtype_dpll_setup);
35669 +
35670 +static void __init of_omap4_no_gate_dpll_setup(struct device_node *node)
35671 +{
35672 + const struct dpll_data dd = {
35673 + .idlest_mask = 0x1,
35674 + .enable_mask = 0x7,
35675 + .autoidle_mask = 0x7,
35676 + .mult_mask = 0x7ff << 8,
35677 + .div1_mask = 0x7f,
35678 + .max_multiplier = 2047,
35679 + .max_divider = 128,
35680 + .min_divider = 1,
35681 + .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
35682 + };
35683 +
35684 + of_omap_dpll_setup(node, &dpll_no_gate_ck_ops, &dd);
35685 +}
35686 +CLK_OF_DECLARE(omap4_no_gate_dpll_clock, "ti,omap4-dpll-no-gate-clock",
35687 + of_omap4_no_gate_dpll_setup);
35688 +
35689 +static void __init of_omap4_no_gate_jtype_dpll_setup(struct device_node *node)
35690 +{
35691 + const struct dpll_data dd = {
35692 + .idlest_mask = 0x1,
35693 + .enable_mask = 0x7,
35694 + .autoidle_mask = 0x7,
35695 + .mult_mask = 0x7ff << 8,
35696 + .div1_mask = 0x7f,
35697 + .max_multiplier = 2047,
35698 + .max_divider = 128,
35699 + .min_divider = 1,
35700 + .flags = DPLL_J_TYPE,
35701 + .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
35702 + };
35703 +
35704 + of_omap_dpll_setup(node, &dpll_no_gate_ck_ops, &dd);
35705 +}
35706 +CLK_OF_DECLARE(omap4_no_gate_jtype_dpll_clock,
35707 + "ti,omap4-dpll-no-gate-j-type-clock",
35708 + of_omap4_no_gate_jtype_dpll_setup);
35709 --- /dev/null
35710 +++ b/drivers/clk/ti/gate.c
35711 @@ -0,0 +1,174 @@
35712 +/*
35713 + * OMAP gate clock support
35714 + *
35715 + * Copyright (C) 2013 Texas Instruments, Inc.
35716 + *
35717 + * Tero Kristo <t-kristo@ti.com>
35718 + *
35719 + * This program is free software; you can redistribute it and/or modify
35720 + * it under the terms of the GNU General Public License version 2 as
35721 + * published by the Free Software Foundation.
35722 + *
35723 + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
35724 + * kind, whether express or implied; without even the implied warranty
35725 + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
35726 + * GNU General Public License for more details.
35727 + */
35728 +
35729 +#include <linux/clk-provider.h>
35730 +#include <linux/slab.h>
35731 +#include <linux/io.h>
35732 +#include <linux/of.h>
35733 +#include <linux/of_address.h>
35734 +#include <linux/clk/ti.h>
35735 +
35736 +#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
35737 +
35738 +static int omap36xx_gate_clk_enable_with_hsdiv_restore(struct clk_hw *clk);
35739 +
35740 +static const struct clk_ops omap_gate_clkdm_clk_ops = {
35741 + .init = &omap2_init_clk_clkdm,
35742 + .enable = &omap2_clkops_enable_clkdm,
35743 + .disable = &omap2_clkops_disable_clkdm,
35744 +};
35745 +
35746 +static const struct clk_ops omap_gate_clk_ops = {
35747 + .init = &omap2_init_clk_clkdm,
35748 + .enable = &omap2_dflt_clk_enable,
35749 + .disable = &omap2_dflt_clk_disable,
35750 + .is_enabled = &omap2_dflt_clk_is_enabled,
35751 +};
35752 +
35753 +static const struct clk_ops omap_gate_clk_hsdiv_restore_ops = {
35754 + .init = &omap2_init_clk_clkdm,
35755 + .enable = &omap36xx_gate_clk_enable_with_hsdiv_restore,
35756 + .disable = &omap2_dflt_clk_disable,
35757 + .is_enabled = &omap2_dflt_clk_is_enabled,
35758 +};
35759 +
35760 +/**
35761 + * omap36xx_gate_clk_enable_with_hsdiv_restore - enable clocks suffering
35762 + * from HSDivider PWRDN problem Implements Errata ID: i556.
35763 + * @clk: DPLL output struct clk
35764 + *
35765 + * 3630 only: dpll3_m3_ck, dpll4_m2_ck, dpll4_m3_ck, dpll4_m4_ck,
35766 + * dpll4_m5_ck & dpll4_m6_ck dividers gets loaded with reset
35767 + * valueafter their respective PWRDN bits are set. Any dummy write
35768 + * (Any other value different from the Read value) to the
35769 + * corresponding CM_CLKSEL register will refresh the dividers.
35770 + */
35771 +static int omap36xx_gate_clk_enable_with_hsdiv_restore(struct clk_hw *clk)
35772 +{
35773 + struct clk_divider *parent;
35774 + struct clk_hw *parent_hw;
35775 + u32 dummy_v, orig_v;
35776 + int ret;
35777 +
35778 + /* Clear PWRDN bit of HSDIVIDER */
35779 + ret = omap2_dflt_clk_enable(clk);
35780 +
35781 + /* Parent is the x2 node, get parent of parent for the m2 div */
35782 + parent_hw = __clk_get_hw(__clk_get_parent(__clk_get_parent(clk->clk)));
35783 + parent = to_clk_divider(parent_hw);
35784 +
35785 + /* Restore the dividers */
35786 + if (!ret) {
35787 + orig_v = __raw_readl(parent->reg);
35788 + dummy_v = orig_v;
35789 +
35790 + /* Write any other value different from the Read value */
35791 + dummy_v ^= (1 << parent->shift);
35792 + __raw_writel(dummy_v, parent->reg);
35793 +
35794 + /* Write the original divider */
35795 + __raw_writel(orig_v, parent->reg);
35796 + }
35797 +
35798 + return ret;
35799 +}
35800 +
35801 +static void __init _of_omap_gate_clk_setup(struct device_node *node,
35802 + void __iomem *reg,
35803 + const struct clk_ops *ops,
35804 + const struct clk_hw_omap_ops *hw_ops)
35805 +{
35806 + struct clk *clk;
35807 + struct clk_init_data init = { 0 };
35808 + struct clk_hw_omap *clk_hw;
35809 + const char *clk_name = node->name;
35810 + const char *parent_name;
35811 + u32 val;
35812 +
35813 + clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
35814 + if (!clk_hw) {
35815 + pr_err("%s: could not allocate clk_hw_omap\n", __func__);
35816 + return;
35817 + }
35818 +
35819 + clk_hw->hw.init = &init;
35820 +
35821 + of_property_read_string(node, "clock-output-names", &clk_name);
35822 +
35823 + init.name = clk_name;
35824 + init.ops = ops;
35825 + clk_hw->enable_reg = reg;
35826 + if (!of_property_read_u32(node, "ti,enable-bit", &val))
35827 + clk_hw->enable_bit = val;
35828 + clk_hw->ops = hw_ops;
35829 +
35830 + parent_name = of_clk_get_parent_name(node, 0);
35831 + init.parent_names = &parent_name;
35832 + init.num_parents = 1;
35833 +
35834 + if (of_property_read_bool(node, "ti,set-rate-parent"))
35835 + init.flags |= CLK_SET_RATE_PARENT;
35836 +
35837 + if (of_property_read_bool(node, "ti,set-bit-to-disable"))
35838 + clk_hw->flags |= INVERT_ENABLE;
35839 +
35840 + clk = clk_register(NULL, &clk_hw->hw);
35841 +
35842 + if (!IS_ERR(clk))
35843 + of_clk_add_provider(node, of_clk_src_simple_get, clk);
35844 +}
35845 +
35846 +static void __init of_omap_clkdm_gate_clk_setup(struct device_node *node)
35847 +{
35848 + _of_omap_gate_clk_setup(node, NULL, &omap_gate_clkdm_clk_ops, NULL);
35849 +}
35850 +CLK_OF_DECLARE(omap_clkdm_gate_clk, "ti,clkdm-gate-clock",
35851 + of_omap_clkdm_gate_clk_setup);
35852 +
35853 +static void __init of_omap_hsdiv_gate_clk_setup(struct device_node *node)
35854 +{
35855 + void __iomem *reg = of_iomap(node, 0);
35856 + _of_omap_gate_clk_setup(node, reg, &omap_gate_clk_hsdiv_restore_ops,
35857 + &clkhwops_wait);
35858 +}
35859 +CLK_OF_DECLARE(omap_hsdiv_gate_clk, "ti,hsdiv-gate-clock",
35860 + of_omap_hsdiv_gate_clk_setup);
35861 +
35862 +static void __init of_omap_gate_clk_setup(struct device_node *node)
35863 +{
35864 + void __iomem *reg = of_iomap(node, 0);
35865 + _of_omap_gate_clk_setup(node, reg, &omap_gate_clk_ops, &clkhwops_wait);
35866 +}
35867 +CLK_OF_DECLARE(omap_gate_clk, "ti,gate-clock", of_omap_gate_clk_setup);
35868 +
35869 +static void __init of_omap_am35xx_gate_clk_setup(struct device_node *node)
35870 +{
35871 + void __iomem *reg = of_iomap(node, 0);
35872 + _of_omap_gate_clk_setup(node, reg, &omap_gate_clk_ops,
35873 + &clkhwops_am35xx_ipss_module_wait);
35874 +}
35875 +CLK_OF_DECLARE(omap_am35xx_gate_clk, "ti,am35xx-gate-clock",
35876 + of_omap_am35xx_gate_clk_setup);
35877 +
35878 +static void __init of_omap_dss_gate_clk_setup(struct device_node *node)
35879 +{
35880 + void __iomem *reg = of_iomap(node, 0);
35881 + _of_omap_gate_clk_setup(node, reg, &omap_gate_clk_ops,
35882 + &clkhwops_omap3430es2_dss_usbhost_wait);
35883 +}
35884 +CLK_OF_DECLARE(omap_dss_gate_clk, "ti,dss-gate-clock",
35885 + of_omap_dss_gate_clk_setup);
35886 --- /dev/null
35887 +++ b/drivers/clk/ti/interface.c
35888 @@ -0,0 +1,124 @@
35889 +/*
35890 + * OMAP interface clock support
35891 + *
35892 + * Copyright (C) 2013 Texas Instruments, Inc.
35893 + *
35894 + * Tero Kristo <t-kristo@ti.com>
35895 + *
35896 + * This program is free software; you can redistribute it and/or modify
35897 + * it under the terms of the GNU General Public License version 2 as
35898 + * published by the Free Software Foundation.
35899 + *
35900 + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
35901 + * kind, whether express or implied; without even the implied warranty
35902 + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
35903 + * GNU General Public License for more details.
35904 + */
35905 +
35906 +#include <linux/clk-provider.h>
35907 +#include <linux/slab.h>
35908 +#include <linux/of.h>
35909 +#include <linux/of_address.h>
35910 +#include <linux/clk/ti.h>
35911 +
35912 +static const struct clk_ops omap_interface_clk_ops = {
35913 + .init = &omap2_init_clk_clkdm,
35914 + .enable = &omap2_dflt_clk_enable,
35915 + .disable = &omap2_dflt_clk_disable,
35916 + .is_enabled = &omap2_dflt_clk_is_enabled,
35917 +};
35918 +
35919 +void __init _of_omap_interface_clk_setup(struct device_node *node,
35920 + const struct clk_hw_omap_ops *ops)
35921 +{
35922 + struct clk *clk;
35923 + struct clk_init_data init = { 0 };
35924 + struct clk_hw_omap *clk_hw;
35925 + const char *clk_name = node->name;
35926 + const char *parent_name;
35927 + u32 val;
35928 +
35929 + clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
35930 + if (!clk_hw) {
35931 + pr_err("%s: could not allocate clk_hw_omap\n", __func__);
35932 + return;
35933 + }
35934 +
35935 + clk_hw->hw.init = &init;
35936 + clk_hw->ops = ops;
35937 + clk_hw->enable_reg = of_iomap(node, 0);
35938 +
35939 + if (!of_property_read_u32(node, "ti,enable-bit", &val))
35940 + clk_hw->enable_bit = val;
35941 +
35942 + of_property_read_string(node, "clock-output-names", &clk_name);
35943 +
35944 + init.name = clk_name;
35945 + init.ops = &omap_interface_clk_ops;
35946 + init.flags = 0;
35947 +
35948 + parent_name = of_clk_get_parent_name(node, 0);
35949 + if (!parent_name) {
35950 + pr_err("%s: %s must have a parent\n", __func__, clk_name);
35951 + goto cleanup;
35952 + }
35953 +
35954 + init.num_parents = 1;
35955 + init.parent_names = &parent_name;
35956 +
35957 + clk = clk_register(NULL, &clk_hw->hw);
35958 +
35959 + if (!IS_ERR(clk)) {
35960 + of_clk_add_provider(node, of_clk_src_simple_get, clk);
35961 + omap2_init_clk_hw_omap_clocks(clk);
35962 + return;
35963 + }
35964 +
35965 +cleanup:
35966 + kfree(clk_hw);
35967 +}
35968 +
35969 +static void __init of_omap_interface_clk_setup(struct device_node *node)
35970 +{
35971 + _of_omap_interface_clk_setup(node, &clkhwops_iclk_wait);
35972 +}
35973 +CLK_OF_DECLARE(omap_interface_clk, "ti,omap3-interface-clock",
35974 + of_omap_interface_clk_setup);
35975 +
35976 +static void __init of_omap_no_wait_interface_clk_setup(struct device_node *node)
35977 +{
35978 + _of_omap_interface_clk_setup(node, &clkhwops_iclk);
35979 +}
35980 +CLK_OF_DECLARE(omap_no_wait_interface_clk, "ti,omap3-no-wait-interface-clock",
35981 + of_omap_no_wait_interface_clk_setup);
35982 +
35983 +static void __init
35984 +of_omap_hsotgusb_interface_clk_setup(struct device_node *node)
35985 +{
35986 + _of_omap_interface_clk_setup(node,
35987 + &clkhwops_omap3430es2_iclk_hsotgusb_wait);
35988 +}
35989 +CLK_OF_DECLARE(omap_hsotgusb_interface_clk, "ti,omap3-hsotgusb-interface-clock",
35990 + of_omap_hsotgusb_interface_clk_setup);
35991 +
35992 +static void __init of_omap_dss_interface_clk_setup(struct device_node *node)
35993 +{
35994 + _of_omap_interface_clk_setup(node,
35995 + &clkhwops_omap3430es2_iclk_dss_usbhost_wait);
35996 +}
35997 +CLK_OF_DECLARE(omap_dss_interface_clk, "ti,omap3-dss-interface-clock",
35998 + of_omap_dss_interface_clk_setup);
35999 +
36000 +static void __init of_omap_ssi_interface_clk_setup(struct device_node *node)
36001 +{
36002 + _of_omap_interface_clk_setup(node, &clkhwops_omap3430es2_iclk_ssi_wait);
36003 +}
36004 +CLK_OF_DECLARE(omap_ssi_interface_clk, "ti,omap3-ssi-interface-clock",
36005 + of_omap_ssi_interface_clk_setup);
36006 +
36007 +static void __init of_omap_am35xx_interface_clk_setup(struct device_node *node)
36008 +{
36009 + _of_omap_interface_clk_setup(node, &clkhwops_am35xx_ipss_wait);
36010 +}
36011 +CLK_OF_DECLARE(omap_am35xx_interface_clk, "ti,am35xx-interface-clock",
36012 + of_omap_am35xx_interface_clk_setup);
36013 --- /dev/null
36014 +++ b/drivers/clk/ti/Makefile
36015 @@ -0,0 +1,6 @@
36016 +ifneq ($(CONFIG_OF),)
36017 +obj-y += clk.o dpll.o autoidle.o gate.o \
36018 + clockdomain.o apll.o clk-44xx.o \
36019 + clk-54xx.o clk-7xx.o clk-33xx.o \
36020 + clk-43xx.o interface.o clk-3xxx.o
36021 +endif
36022 --- a/drivers/cpufreq/cpufreq-cpu0.c
36023 +++ b/drivers/cpufreq/cpufreq-cpu0.c
36024 @@ -21,6 +21,7 @@
36025 #include <linux/platform_device.h>
36026 #include <linux/regulator/consumer.h>
36027 #include <linux/slab.h>
36028 +#include <linux/suspend.h>
36029
36030 static unsigned int transition_latency;
36031 static unsigned int voltage_tolerance; /* in percentage */
36032 @@ -29,6 +30,8 @@ static struct device *cpu_dev;
36033 static struct clk *cpu_clk;
36034 static struct regulator *cpu_reg;
36035 static struct cpufreq_frequency_table *freq_table;
36036 +static DEFINE_MUTEX(cpu_lock);
36037 +static bool is_suspended;
36038
36039 static int cpu0_verify_speed(struct cpufreq_policy *policy)
36040 {
36041 @@ -50,12 +53,19 @@ static int cpu0_set_target(struct cpufre
36042 unsigned int index;
36043 int ret;
36044
36045 + mutex_lock(&cpu_lock);
36046 +
36047 + if (is_suspended) {
36048 + ret = -EBUSY;
36049 + goto out;
36050 + }
36051 +
36052 ret = cpufreq_frequency_table_target(policy, freq_table, target_freq,
36053 relation, &index);
36054 if (ret) {
36055 pr_err("failed to match target freqency %d: %d\n",
36056 target_freq, ret);
36057 - return ret;
36058 + goto out;
36059 }
36060
36061 freq_Hz = clk_round_rate(cpu_clk, freq_table[index].frequency * 1000);
36062 @@ -65,8 +75,10 @@ static int cpu0_set_target(struct cpufre
36063 freqs.new = freq_Hz / 1000;
36064 freqs.old = clk_get_rate(cpu_clk) / 1000;
36065
36066 - if (freqs.old == freqs.new)
36067 - return 0;
36068 + if (freqs.old == freqs.new) {
36069 + ret = 0;
36070 + goto out;
36071 + }
36072
36073 cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE);
36074
36075 @@ -122,9 +134,32 @@ static int cpu0_set_target(struct cpufre
36076 post_notify:
36077 cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE);
36078
36079 +out:
36080 + mutex_unlock(&cpu_lock);
36081 return ret;
36082 }
36083
36084 +static int cpu0_pm_notify(struct notifier_block *nb, unsigned long event,
36085 + void *dummy)
36086 +{
36087 + mutex_lock(&cpu_lock);
36088 + switch (event) {
36089 + case PM_SUSPEND_PREPARE:
36090 + is_suspended = true;
36091 + break;
36092 + case PM_POST_SUSPEND:
36093 + is_suspended = false;
36094 + break;
36095 + }
36096 + mutex_unlock(&cpu_lock);
36097 +
36098 + return NOTIFY_OK;
36099 +}
36100 +
36101 +static struct notifier_block cpu_pm_notifier = {
36102 + .notifier_call = cpu0_pm_notify,
36103 +};
36104 +
36105 static int cpu0_cpufreq_init(struct cpufreq_policy *policy)
36106 {
36107 int ret;
36108 @@ -147,11 +182,17 @@ static int cpu0_cpufreq_init(struct cpuf
36109
36110 cpufreq_frequency_table_get_attr(freq_table, policy->cpu);
36111
36112 + if (!IS_ERR(cpu_reg))
36113 + register_pm_notifier(&cpu_pm_notifier);
36114 +
36115 return 0;
36116 }
36117
36118 static int cpu0_cpufreq_exit(struct cpufreq_policy *policy)
36119 {
36120 + if (!IS_ERR(cpu_reg))
36121 + unregister_pm_notifier(&cpu_pm_notifier);
36122 +
36123 cpufreq_frequency_table_put_attr(policy->cpu);
36124
36125 return 0;
36126 --- a/drivers/crypto/Kconfig
36127 +++ b/drivers/crypto/Kconfig
36128 @@ -263,6 +263,17 @@ config CRYPTO_DEV_OMAP_AES
36129 OMAP processors have AES module accelerator. Select this if you
36130 want to use the OMAP module for AES algorithms.
36131
36132 +config CRYPTO_DEV_OMAP_DES
36133 + tristate "Support for OMAP DES3DES hw engine"
36134 + depends on ARCH_OMAP2PLUS
36135 + select CRYPTO_DES
36136 + select CRYPTO_BLKCIPHER2
36137 + help
36138 + OMAP processors have DES/3DES module accelerator. Select this if you
36139 + want to use the OMAP module for DES and 3DES algorithms. Currently
36140 + the ECB and CBC modes of operation supported by the driver. Also
36141 + accesses made on unaligned boundaries are also supported.
36142 +
36143 config CRYPTO_DEV_PICOXCELL
36144 tristate "Support for picoXcell IPSEC and Layer2 crypto engines"
36145 depends on ARCH_PICOXCELL && HAVE_CLK
36146 --- a/drivers/crypto/Makefile
36147 +++ b/drivers/crypto/Makefile
36148 @@ -11,6 +11,7 @@ obj-$(CONFIG_CRYPTO_DEV_IXP4XX) += ixp4x
36149 obj-$(CONFIG_CRYPTO_DEV_PPC4XX) += amcc/
36150 obj-$(CONFIG_CRYPTO_DEV_OMAP_SHAM) += omap-sham.o
36151 obj-$(CONFIG_CRYPTO_DEV_OMAP_AES) += omap-aes.o
36152 +obj-$(CONFIG_CRYPTO_DEV_OMAP_DES) += omap-des.o
36153 obj-$(CONFIG_CRYPTO_DEV_PICOXCELL) += picoxcell_crypto.o
36154 obj-$(CONFIG_CRYPTO_DEV_SAHARA) += sahara.o
36155 obj-$(CONFIG_CRYPTO_DEV_DCP) += dcp.o
36156 --- a/drivers/crypto/omap-aes.c
36157 +++ b/drivers/crypto/omap-aes.c
36158 @@ -275,7 +275,7 @@ static int omap_aes_write_ctrl(struct om
36159 if (dd->flags & FLAGS_CBC)
36160 val |= AES_REG_CTRL_CBC;
36161 if (dd->flags & FLAGS_CTR) {
36162 - val |= AES_REG_CTRL_CTR | AES_REG_CTRL_CTR_WIDTH_32;
36163 + val |= AES_REG_CTRL_CTR | AES_REG_CTRL_CTR_WIDTH_128;
36164 mask = AES_REG_CTRL_CTR | AES_REG_CTRL_CTR_WIDTH_MASK;
36165 }
36166 if (dd->flags & FLAGS_ENCRYPT)
36167 --- /dev/null
36168 +++ b/drivers/crypto/omap-des.c
36169 @@ -0,0 +1,1239 @@
36170 +/*
36171 + * Cryptographic API.
36172 + *
36173 + * Support for OMAP DES and Triple DES HW acceleration.
36174 + *
36175 + * Copyright (c) 2012 Texas Instruments Incorporated
36176 + * Author: Joel Fernandes <joelf@ti.com>
36177 + *
36178 + * This program is free software; you can redistribute it and/or modify
36179 + * it under the terms of the GNU General Public License version 2 as published
36180 + * by the Free Software Foundation.
36181 + *
36182 + */
36183 +
36184 +#define pr_fmt(fmt) "%s: " fmt, __func__
36185 +
36186 +#ifdef DEBUG
36187 +#define prn(num) printk(#num "=%d\n", num)
36188 +#define prx(num) printk(#num "=%x\n", num)
36189 +#else
36190 +#define prn(num) do { } while (0)
36191 +#define prx(num) do { } while (0)
36192 +#endif
36193 +
36194 +#include <linux/err.h>
36195 +#include <linux/module.h>
36196 +#include <linux/init.h>
36197 +#include <linux/errno.h>
36198 +#include <linux/kernel.h>
36199 +#include <linux/platform_device.h>
36200 +#include <linux/scatterlist.h>
36201 +#include <linux/dma-mapping.h>
36202 +#include <linux/dmaengine.h>
36203 +#include <linux/omap-dma.h>
36204 +#include <linux/pm_runtime.h>
36205 +#include <linux/of.h>
36206 +#include <linux/of_device.h>
36207 +#include <linux/of_address.h>
36208 +#include <linux/io.h>
36209 +#include <linux/crypto.h>
36210 +#include <linux/interrupt.h>
36211 +#include <crypto/scatterwalk.h>
36212 +#include <crypto/des.h>
36213 +
36214 +#define DST_MAXBURST 2
36215 +
36216 +#define DES_BLOCK_WORDS (DES_BLOCK_SIZE >> 2)
36217 +
36218 +#define _calc_walked(inout) (dd->inout##_walk.offset - dd->inout##_sg->offset)
36219 +
36220 +#define DES_REG_KEY(dd, x) ((dd)->pdata->key_ofs - \
36221 + ((x ^ 0x01) * 0x04))
36222 +
36223 +#define DES_REG_IV(dd, x) ((dd)->pdata->iv_ofs + ((x) * 0x04))
36224 +
36225 +#define DES_REG_CTRL(dd) ((dd)->pdata->ctrl_ofs)
36226 +#define DES_REG_CTRL_CBC (1 << 4)
36227 +#define DES_REG_CTRL_TDES (1 << 3)
36228 +#define DES_REG_CTRL_DIRECTION (1 << 2)
36229 +#define DES_REG_CTRL_INPUT_READY (1 << 1)
36230 +#define DES_REG_CTRL_OUTPUT_READY (1 << 0)
36231 +
36232 +#define DES_REG_DATA_N(dd, x) ((dd)->pdata->data_ofs + ((x) * 0x04))
36233 +
36234 +#define DES_REG_REV(dd) ((dd)->pdata->rev_ofs)
36235 +
36236 +#define DES_REG_MASK(dd) ((dd)->pdata->mask_ofs)
36237 +
36238 +#define DES_REG_LENGTH_N(x) (0x24 + ((x) * 0x04))
36239 +
36240 +#define DES_REG_IRQ_STATUS(dd) ((dd)->pdata->irq_status_ofs)
36241 +#define DES_REG_IRQ_ENABLE(dd) ((dd)->pdata->irq_enable_ofs)
36242 +#define DES_REG_IRQ_DATA_IN BIT(1)
36243 +#define DES_REG_IRQ_DATA_OUT BIT(2)
36244 +
36245 +#define FLAGS_MODE_MASK 0x000f
36246 +#define FLAGS_ENCRYPT BIT(0)
36247 +#define FLAGS_CBC BIT(1)
36248 +#define FLAGS_INIT BIT(4)
36249 +#define FLAGS_BUSY BIT(6)
36250 +
36251 +struct omap_des_ctx {
36252 + struct omap_des_dev *dd;
36253 +
36254 + int keylen;
36255 + u32 key[(3 * DES_KEY_SIZE) / sizeof(u32)];
36256 + unsigned long flags;
36257 +};
36258 +
36259 +struct omap_des_reqctx {
36260 + unsigned long mode;
36261 +};
36262 +
36263 +#define OMAP_DES_QUEUE_LENGTH 1
36264 +#define OMAP_DES_CACHE_SIZE 0
36265 +
36266 +struct omap_des_algs_info {
36267 + struct crypto_alg *algs_list;
36268 + unsigned int size;
36269 + unsigned int registered;
36270 +};
36271 +
36272 +struct omap_des_pdata {
36273 + struct omap_des_algs_info *algs_info;
36274 + unsigned int algs_info_size;
36275 +
36276 + void (*trigger)(struct omap_des_dev *dd, int length);
36277 +
36278 + u32 key_ofs;
36279 + u32 iv_ofs;
36280 + u32 ctrl_ofs;
36281 + u32 data_ofs;
36282 + u32 rev_ofs;
36283 + u32 mask_ofs;
36284 + u32 irq_enable_ofs;
36285 + u32 irq_status_ofs;
36286 +
36287 + u32 dma_enable_in;
36288 + u32 dma_enable_out;
36289 + u32 dma_start;
36290 +
36291 + u32 major_mask;
36292 + u32 major_shift;
36293 + u32 minor_mask;
36294 + u32 minor_shift;
36295 +};
36296 +
36297 +struct omap_des_dev {
36298 + struct list_head list;
36299 + unsigned long phys_base;
36300 + void __iomem *io_base;
36301 + struct omap_des_ctx *ctx;
36302 + struct device *dev;
36303 + unsigned long flags;
36304 + int err;
36305 +
36306 + /* spinlock used for queues */
36307 + spinlock_t lock;
36308 + struct crypto_queue queue;
36309 +
36310 + struct tasklet_struct done_task;
36311 + struct tasklet_struct queue_task;
36312 +
36313 + struct ablkcipher_request *req;
36314 + /*
36315 + * total is used by PIO mode for book keeping so introduce
36316 + * variable total_save as need it to calc page_order
36317 + */
36318 + size_t total;
36319 + size_t total_save;
36320 +
36321 + struct scatterlist *in_sg;
36322 + struct scatterlist *out_sg;
36323 +
36324 + /* Buffers for copying for unaligned cases */
36325 + struct scatterlist in_sgl;
36326 + struct scatterlist out_sgl;
36327 + struct scatterlist *orig_out;
36328 + int sgs_copied;
36329 +
36330 + struct scatter_walk in_walk;
36331 + struct scatter_walk out_walk;
36332 + int dma_in;
36333 + struct dma_chan *dma_lch_in;
36334 + int dma_out;
36335 + struct dma_chan *dma_lch_out;
36336 + int in_sg_len;
36337 + int out_sg_len;
36338 + int pio_only;
36339 + const struct omap_des_pdata *pdata;
36340 +};
36341 +
36342 +/* keep registered devices data here */
36343 +static LIST_HEAD(dev_list);
36344 +static DEFINE_SPINLOCK(list_lock);
36345 +
36346 +#ifdef DEBUG
36347 +#define omap_des_read(dd, offset) \
36348 + ({ \
36349 + int _read_ret; \
36350 + _read_ret = __raw_readl(dd->io_base + offset); \
36351 + pr_err("omap_des_read(" #offset "=%#x)= %#x\n", \
36352 + offset, _read_ret); \
36353 + _read_ret; \
36354 + })
36355 +#else
36356 +static inline u32 omap_des_read(struct omap_des_dev *dd, u32 offset)
36357 +{
36358 + return __raw_readl(dd->io_base + offset);
36359 +}
36360 +#endif
36361 +
36362 +#ifdef DEBUG
36363 +#define omap_des_write(dd, offset, value) \
36364 + do { \
36365 + pr_err("omap_des_write(" #offset "=%#x) value=%#x\n", \
36366 + offset, value); \
36367 + __raw_writel(value, dd->io_base + offset); \
36368 + } while (0)
36369 +#else
36370 +static inline void omap_des_write(struct omap_des_dev *dd, u32 offset,
36371 + u32 value)
36372 +{
36373 + __raw_writel(value, dd->io_base + offset);
36374 +}
36375 +#endif
36376 +
36377 +static inline void omap_des_write_mask(struct omap_des_dev *dd, u32 offset,
36378 + u32 value, u32 mask)
36379 +{
36380 + u32 val;
36381 +
36382 + val = omap_des_read(dd, offset);
36383 + val &= ~mask;
36384 + val |= value;
36385 + omap_des_write(dd, offset, val);
36386 +}
36387 +
36388 +static void omap_des_write_n(struct omap_des_dev *dd, u32 offset,
36389 + u32 *value, int count)
36390 +{
36391 + for (; count--; value++, offset += 4)
36392 + omap_des_write(dd, offset, *value);
36393 +}
36394 +
36395 +static int omap_des_hw_init(struct omap_des_dev *dd)
36396 +{
36397 + /*
36398 + * clocks are enabled when request starts and disabled when finished.
36399 + * It may be long delays between requests.
36400 + * Device might go to off mode to save power.
36401 + */
36402 + pm_runtime_get_sync(dd->dev);
36403 +
36404 + if (!(dd->flags & FLAGS_INIT)) {
36405 + dd->flags |= FLAGS_INIT;
36406 + dd->err = 0;
36407 + }
36408 +
36409 + return 0;
36410 +}
36411 +
36412 +static int omap_des_write_ctrl(struct omap_des_dev *dd)
36413 +{
36414 + unsigned int key32;
36415 + int i, err;
36416 + u32 val = 0, mask = 0;
36417 +
36418 + err = omap_des_hw_init(dd);
36419 + if (err)
36420 + return err;
36421 +
36422 + key32 = dd->ctx->keylen / sizeof(u32);
36423 +
36424 + /* it seems a key should always be set even if it has not changed */
36425 + for (i = 0; i < key32; i++) {
36426 + omap_des_write(dd, DES_REG_KEY(dd, i),
36427 + __le32_to_cpu(dd->ctx->key[i]));
36428 + }
36429 +
36430 + if ((dd->flags & FLAGS_CBC) && dd->req->info)
36431 + omap_des_write_n(dd, DES_REG_IV(dd, 0), dd->req->info, 2);
36432 +
36433 + if (dd->flags & FLAGS_CBC)
36434 + val |= DES_REG_CTRL_CBC;
36435 + if (dd->flags & FLAGS_ENCRYPT)
36436 + val |= DES_REG_CTRL_DIRECTION;
36437 + if (key32 == 6)
36438 + val |= DES_REG_CTRL_TDES;
36439 +
36440 + mask |= DES_REG_CTRL_CBC | DES_REG_CTRL_DIRECTION | DES_REG_CTRL_TDES;
36441 +
36442 + omap_des_write_mask(dd, DES_REG_CTRL(dd), val, mask);
36443 +
36444 + return 0;
36445 +}
36446 +
36447 +static void omap_des_dma_trigger_omap4(struct omap_des_dev *dd, int length)
36448 +{
36449 + u32 mask, val;
36450 +
36451 + omap_des_write(dd, DES_REG_LENGTH_N(0), length);
36452 +
36453 + val = dd->pdata->dma_start;
36454 +
36455 + if (dd->dma_lch_out != NULL)
36456 + val |= dd->pdata->dma_enable_out;
36457 + if (dd->dma_lch_in != NULL)
36458 + val |= dd->pdata->dma_enable_in;
36459 +
36460 + mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in |
36461 + dd->pdata->dma_start;
36462 +
36463 + omap_des_write_mask(dd, DES_REG_MASK(dd), val, mask);
36464 +}
36465 +
36466 +static void omap_des_dma_stop(struct omap_des_dev *dd)
36467 +{
36468 + u32 mask;
36469 +
36470 + mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in |
36471 + dd->pdata->dma_start;
36472 +
36473 + omap_des_write_mask(dd, DES_REG_MASK(dd), 0, mask);
36474 +}
36475 +
36476 +static struct omap_des_dev *omap_des_find_dev(struct omap_des_ctx *ctx)
36477 +{
36478 + struct omap_des_dev *dd = NULL, *tmp;
36479 +
36480 + spin_lock_bh(&list_lock);
36481 + if (!ctx->dd) {
36482 + list_for_each_entry(tmp, &dev_list, list) {
36483 + /* FIXME: take fist available des core */
36484 + dd = tmp;
36485 + break;
36486 + }
36487 + ctx->dd = dd;
36488 + } else {
36489 + /* already found before */
36490 + dd = ctx->dd;
36491 + }
36492 + spin_unlock_bh(&list_lock);
36493 +
36494 + return dd;
36495 +}
36496 +
36497 +static void omap_des_dma_out_callback(void *data)
36498 +{
36499 + struct omap_des_dev *dd = data;
36500 +
36501 + /* dma_lch_out - completed */
36502 + tasklet_schedule(&dd->done_task);
36503 +}
36504 +
36505 +static int omap_des_dma_init(struct omap_des_dev *dd)
36506 +{
36507 + int err = -ENOMEM;
36508 + dma_cap_mask_t mask;
36509 +
36510 + dd->dma_lch_out = NULL;
36511 + dd->dma_lch_in = NULL;
36512 +
36513 + dma_cap_zero(mask);
36514 + dma_cap_set(DMA_SLAVE, mask);
36515 +
36516 + dd->dma_lch_in = dma_request_slave_channel_compat(mask,
36517 + omap_dma_filter_fn,
36518 + &dd->dma_in,
36519 + dd->dev, "rx");
36520 + if (!dd->dma_lch_in) {
36521 + dev_err(dd->dev, "Unable to request in DMA channel\n");
36522 + goto err_dma_in;
36523 + }
36524 +
36525 + dd->dma_lch_out = dma_request_slave_channel_compat(mask,
36526 + omap_dma_filter_fn,
36527 + &dd->dma_out,
36528 + dd->dev, "tx");
36529 + if (!dd->dma_lch_out) {
36530 + dev_err(dd->dev, "Unable to request out DMA channel\n");
36531 + goto err_dma_out;
36532 + }
36533 +
36534 + return 0;
36535 +
36536 +err_dma_out:
36537 + dma_release_channel(dd->dma_lch_in);
36538 +err_dma_in:
36539 + if (err)
36540 + pr_err("error: %d\n", err);
36541 + return err;
36542 +}
36543 +
36544 +static void omap_des_dma_cleanup(struct omap_des_dev *dd)
36545 +{
36546 + dma_release_channel(dd->dma_lch_out);
36547 + dma_release_channel(dd->dma_lch_in);
36548 +}
36549 +
36550 +static void sg_copy_buf(void *buf, struct scatterlist *sg,
36551 + unsigned int start, unsigned int nbytes, int out)
36552 +{
36553 + struct scatter_walk walk;
36554 +
36555 + if (!nbytes)
36556 + return;
36557 +
36558 + scatterwalk_start(&walk, sg);
36559 + scatterwalk_advance(&walk, start);
36560 + scatterwalk_copychunks(buf, &walk, nbytes, out);
36561 + scatterwalk_done(&walk, out, 0);
36562 +}
36563 +
36564 +static int omap_des_crypt_dma(struct crypto_tfm *tfm,
36565 + struct scatterlist *in_sg, struct scatterlist *out_sg,
36566 + int in_sg_len, int out_sg_len)
36567 +{
36568 + struct omap_des_ctx *ctx = crypto_tfm_ctx(tfm);
36569 + struct omap_des_dev *dd = ctx->dd;
36570 + struct dma_async_tx_descriptor *tx_in, *tx_out;
36571 + struct dma_slave_config cfg;
36572 + int ret;
36573 +
36574 + if (dd->pio_only) {
36575 + scatterwalk_start(&dd->in_walk, dd->in_sg);
36576 + scatterwalk_start(&dd->out_walk, dd->out_sg);
36577 +
36578 + /* Enable DATAIN interrupt and let it take
36579 + care of the rest */
36580 + omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x2);
36581 + return 0;
36582 + }
36583 +
36584 + dma_sync_sg_for_device(dd->dev, dd->in_sg, in_sg_len, DMA_TO_DEVICE);
36585 +
36586 + memset(&cfg, 0, sizeof(cfg));
36587 +
36588 + cfg.src_addr = dd->phys_base + DES_REG_DATA_N(dd, 0);
36589 + cfg.dst_addr = dd->phys_base + DES_REG_DATA_N(dd, 0);
36590 + cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
36591 + cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
36592 + cfg.src_maxburst = DST_MAXBURST;
36593 + cfg.dst_maxburst = DST_MAXBURST;
36594 +
36595 + /* IN */
36596 + ret = dmaengine_slave_config(dd->dma_lch_in, &cfg);
36597 + if (ret) {
36598 + dev_err(dd->dev, "can't configure IN dmaengine slave: %d\n",
36599 + ret);
36600 + return ret;
36601 + }
36602 +
36603 + tx_in = dmaengine_prep_slave_sg(dd->dma_lch_in, in_sg, in_sg_len,
36604 + DMA_MEM_TO_DEV,
36605 + DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
36606 + if (!tx_in) {
36607 + dev_err(dd->dev, "IN prep_slave_sg() failed\n");
36608 + return -EINVAL;
36609 + }
36610 +
36611 + /* No callback necessary */
36612 + tx_in->callback_param = dd;
36613 +
36614 + /* OUT */
36615 + ret = dmaengine_slave_config(dd->dma_lch_out, &cfg);
36616 + if (ret) {
36617 + dev_err(dd->dev, "can't configure OUT dmaengine slave: %d\n",
36618 + ret);
36619 + return ret;
36620 + }
36621 +
36622 + tx_out = dmaengine_prep_slave_sg(dd->dma_lch_out, out_sg, out_sg_len,
36623 + DMA_DEV_TO_MEM,
36624 + DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
36625 + if (!tx_out) {
36626 + dev_err(dd->dev, "OUT prep_slave_sg() failed\n");
36627 + return -EINVAL;
36628 + }
36629 +
36630 + tx_out->callback = omap_des_dma_out_callback;
36631 + tx_out->callback_param = dd;
36632 +
36633 + dmaengine_submit(tx_in);
36634 + dmaengine_submit(tx_out);
36635 +
36636 + dma_async_issue_pending(dd->dma_lch_in);
36637 + dma_async_issue_pending(dd->dma_lch_out);
36638 +
36639 + /* start DMA */
36640 + dd->pdata->trigger(dd, dd->total);
36641 +
36642 + return 0;
36643 +}
36644 +
36645 +static int omap_des_crypt_dma_start(struct omap_des_dev *dd)
36646 +{
36647 + struct crypto_tfm *tfm = crypto_ablkcipher_tfm(
36648 + crypto_ablkcipher_reqtfm(dd->req));
36649 + int err;
36650 +
36651 + pr_debug("total: %d\n", dd->total);
36652 +
36653 + if (!dd->pio_only) {
36654 + err = dma_map_sg(dd->dev, dd->in_sg, dd->in_sg_len,
36655 + DMA_TO_DEVICE);
36656 + if (!err) {
36657 + dev_err(dd->dev, "dma_map_sg() error\n");
36658 + return -EINVAL;
36659 + }
36660 +
36661 + err = dma_map_sg(dd->dev, dd->out_sg, dd->out_sg_len,
36662 + DMA_FROM_DEVICE);
36663 + if (!err) {
36664 + dev_err(dd->dev, "dma_map_sg() error\n");
36665 + return -EINVAL;
36666 + }
36667 + }
36668 +
36669 + err = omap_des_crypt_dma(tfm, dd->in_sg, dd->out_sg, dd->in_sg_len,
36670 + dd->out_sg_len);
36671 + if (err && !dd->pio_only) {
36672 + dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE);
36673 + dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len,
36674 + DMA_FROM_DEVICE);
36675 + }
36676 +
36677 + return err;
36678 +}
36679 +
36680 +static void omap_des_finish_req(struct omap_des_dev *dd, int err)
36681 +{
36682 + struct ablkcipher_request *req = dd->req;
36683 +
36684 + pr_debug("err: %d\n", err);
36685 +
36686 + pm_runtime_put(dd->dev);
36687 + dd->flags &= ~FLAGS_BUSY;
36688 +
36689 + req->base.complete(&req->base, err);
36690 +}
36691 +
36692 +static int omap_des_crypt_dma_stop(struct omap_des_dev *dd)
36693 +{
36694 + int err = 0;
36695 +
36696 + pr_debug("total: %d\n", dd->total);
36697 +
36698 + omap_des_dma_stop(dd);
36699 +
36700 + dmaengine_terminate_all(dd->dma_lch_in);
36701 + dmaengine_terminate_all(dd->dma_lch_out);
36702 +
36703 + dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE);
36704 + dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len, DMA_FROM_DEVICE);
36705 +
36706 + return err;
36707 +}
36708 +
36709 +int omap_des_copy_needed(struct scatterlist *sg)
36710 +{
36711 + while (sg) {
36712 + if (!IS_ALIGNED(sg->offset, 4))
36713 + return -1;
36714 + if (!IS_ALIGNED(sg->length, DES_BLOCK_SIZE))
36715 + return -1;
36716 + sg = sg_next(sg);
36717 + }
36718 + return 0;
36719 +}
36720 +
36721 +int omap_des_copy_sgs(struct omap_des_dev *dd)
36722 +{
36723 + void *buf_in, *buf_out;
36724 + int pages;
36725 +
36726 + pages = dd->total >> PAGE_SHIFT;
36727 +
36728 + if (dd->total & (PAGE_SIZE-1))
36729 + pages++;
36730 +
36731 + BUG_ON(!pages);
36732 +
36733 + buf_in = (void *)__get_free_pages(GFP_ATOMIC, pages);
36734 + buf_out = (void *)__get_free_pages(GFP_ATOMIC, pages);
36735 +
36736 + if (!buf_in || !buf_out) {
36737 + pr_err("Couldn't allocated pages for unaligned cases.\n");
36738 + return -1;
36739 + }
36740 +
36741 + dd->orig_out = dd->out_sg;
36742 +
36743 + sg_copy_buf(buf_in, dd->in_sg, 0, dd->total, 0);
36744 +
36745 + sg_init_table(&dd->in_sgl, 1);
36746 + sg_set_buf(&dd->in_sgl, buf_in, dd->total);
36747 + dd->in_sg = &dd->in_sgl;
36748 +
36749 + sg_init_table(&dd->out_sgl, 1);
36750 + sg_set_buf(&dd->out_sgl, buf_out, dd->total);
36751 + dd->out_sg = &dd->out_sgl;
36752 +
36753 + return 0;
36754 +}
36755 +
36756 +static int omap_des_handle_queue(struct omap_des_dev *dd,
36757 + struct ablkcipher_request *req)
36758 +{
36759 + struct crypto_async_request *async_req, *backlog;
36760 + struct omap_des_ctx *ctx;
36761 + struct omap_des_reqctx *rctx;
36762 + unsigned long flags;
36763 + int err, ret = 0;
36764 +
36765 + spin_lock_irqsave(&dd->lock, flags);
36766 + if (req)
36767 + ret = ablkcipher_enqueue_request(&dd->queue, req);
36768 + if (dd->flags & FLAGS_BUSY) {
36769 + spin_unlock_irqrestore(&dd->lock, flags);
36770 + return ret;
36771 + }
36772 + backlog = crypto_get_backlog(&dd->queue);
36773 + async_req = crypto_dequeue_request(&dd->queue);
36774 + if (async_req)
36775 + dd->flags |= FLAGS_BUSY;
36776 + spin_unlock_irqrestore(&dd->lock, flags);
36777 +
36778 + if (!async_req)
36779 + return ret;
36780 +
36781 + if (backlog)
36782 + backlog->complete(backlog, -EINPROGRESS);
36783 +
36784 + req = ablkcipher_request_cast(async_req);
36785 +
36786 + /* assign new request to device */
36787 + dd->req = req;
36788 + dd->total = req->nbytes;
36789 + dd->total_save = req->nbytes;
36790 + dd->in_sg = req->src;
36791 + dd->out_sg = req->dst;
36792 +
36793 + if (omap_des_copy_needed(dd->in_sg) ||
36794 + omap_des_copy_needed(dd->out_sg)) {
36795 + if (omap_des_copy_sgs(dd))
36796 + pr_err("Failed to copy SGs for unaligned cases\n");
36797 + dd->sgs_copied = 1;
36798 + } else {
36799 + dd->sgs_copied = 0;
36800 + }
36801 +
36802 + dd->in_sg_len = scatterwalk_bytes_sglen(dd->in_sg, dd->total);
36803 + dd->out_sg_len = scatterwalk_bytes_sglen(dd->out_sg, dd->total);
36804 + BUG_ON(dd->in_sg_len < 0 || dd->out_sg_len < 0);
36805 +
36806 + rctx = ablkcipher_request_ctx(req);
36807 + ctx = crypto_ablkcipher_ctx(crypto_ablkcipher_reqtfm(req));
36808 + rctx->mode &= FLAGS_MODE_MASK;
36809 + dd->flags = (dd->flags & ~FLAGS_MODE_MASK) | rctx->mode;
36810 +
36811 + dd->ctx = ctx;
36812 + ctx->dd = dd;
36813 +
36814 + err = omap_des_write_ctrl(dd);
36815 + if (!err)
36816 + err = omap_des_crypt_dma_start(dd);
36817 + if (err) {
36818 + /* des_task will not finish it, so do it here */
36819 + omap_des_finish_req(dd, err);
36820 + tasklet_schedule(&dd->queue_task);
36821 + }
36822 +
36823 + return ret; /* return ret, which is enqueue return value */
36824 +}
36825 +
36826 +static void omap_des_done_task(unsigned long data)
36827 +{
36828 + struct omap_des_dev *dd = (struct omap_des_dev *)data;
36829 + void *buf_in, *buf_out;
36830 + int pages;
36831 +
36832 + pr_debug("enter done_task\n");
36833 +
36834 + if (!dd->pio_only) {
36835 + dma_sync_sg_for_device(dd->dev, dd->out_sg, dd->out_sg_len,
36836 + DMA_FROM_DEVICE);
36837 + dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE);
36838 + dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len,
36839 + DMA_FROM_DEVICE);
36840 + omap_des_crypt_dma_stop(dd);
36841 + }
36842 +
36843 + if (dd->sgs_copied) {
36844 + buf_in = sg_virt(&dd->in_sgl);
36845 + buf_out = sg_virt(&dd->out_sgl);
36846 +
36847 + sg_copy_buf(buf_out, dd->orig_out, 0, dd->total_save, 1);
36848 +
36849 + pages = get_order(dd->total_save);
36850 + free_pages((unsigned long)buf_in, pages);
36851 + free_pages((unsigned long)buf_out, pages);
36852 + }
36853 +
36854 + omap_des_finish_req(dd, 0);
36855 + omap_des_handle_queue(dd, NULL);
36856 +
36857 + pr_debug("exit\n");
36858 +}
36859 +
36860 +static void omap_des_queue_task(unsigned long data)
36861 +{
36862 + struct omap_des_dev *dd = (struct omap_des_dev *)data;
36863 +
36864 + omap_des_handle_queue(dd, NULL);
36865 +}
36866 +
36867 +static int omap_des_crypt(struct ablkcipher_request *req, unsigned long mode)
36868 +{
36869 + struct omap_des_ctx *ctx = crypto_ablkcipher_ctx(
36870 + crypto_ablkcipher_reqtfm(req));
36871 + struct omap_des_reqctx *rctx = ablkcipher_request_ctx(req);
36872 + struct omap_des_dev *dd;
36873 +
36874 + pr_debug("nbytes: %d, enc: %d, cbc: %d\n", req->nbytes,
36875 + !!(mode & FLAGS_ENCRYPT),
36876 + !!(mode & FLAGS_CBC));
36877 +
36878 + if (!IS_ALIGNED(req->nbytes, DES_BLOCK_SIZE)) {
36879 + pr_err("request size is not exact amount of DES blocks\n");
36880 + return -EINVAL;
36881 + }
36882 +
36883 + dd = omap_des_find_dev(ctx);
36884 + if (!dd)
36885 + return -ENODEV;
36886 +
36887 + rctx->mode = mode;
36888 +
36889 + return omap_des_handle_queue(dd, req);
36890 +}
36891 +
36892 +/* ********************** ALG API ************************************ */
36893 +
36894 +static int omap_des_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
36895 + unsigned int keylen)
36896 +{
36897 + struct omap_des_ctx *ctx = crypto_ablkcipher_ctx(tfm);
36898 +
36899 + if (keylen != DES_KEY_SIZE && keylen != (3*DES_KEY_SIZE))
36900 + return -EINVAL;
36901 +
36902 + pr_debug("enter, keylen: %d\n", keylen);
36903 +
36904 + memcpy(ctx->key, key, keylen);
36905 + ctx->keylen = keylen;
36906 +
36907 + return 0;
36908 +}
36909 +
36910 +static int omap_des_ecb_encrypt(struct ablkcipher_request *req)
36911 +{
36912 + return omap_des_crypt(req, FLAGS_ENCRYPT);
36913 +}
36914 +
36915 +static int omap_des_ecb_decrypt(struct ablkcipher_request *req)
36916 +{
36917 + return omap_des_crypt(req, 0);
36918 +}
36919 +
36920 +static int omap_des_cbc_encrypt(struct ablkcipher_request *req)
36921 +{
36922 + return omap_des_crypt(req, FLAGS_ENCRYPT | FLAGS_CBC);
36923 +}
36924 +
36925 +static int omap_des_cbc_decrypt(struct ablkcipher_request *req)
36926 +{
36927 + return omap_des_crypt(req, FLAGS_CBC);
36928 +}
36929 +
36930 +static int omap_des_cra_init(struct crypto_tfm *tfm)
36931 +{
36932 + pr_debug("enter\n");
36933 +
36934 + tfm->crt_ablkcipher.reqsize = sizeof(struct omap_des_reqctx);
36935 +
36936 + return 0;
36937 +}
36938 +
36939 +static void omap_des_cra_exit(struct crypto_tfm *tfm)
36940 +{
36941 + pr_debug("enter\n");
36942 +}
36943 +
36944 +/* ********************** ALGS ************************************ */
36945 +
36946 +static struct crypto_alg algs_ecb_cbc[] = {
36947 +{
36948 + .cra_name = "ecb(des)",
36949 + .cra_driver_name = "ecb-des-omap",
36950 + .cra_priority = 100,
36951 + .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
36952 + CRYPTO_ALG_KERN_DRIVER_ONLY |
36953 + CRYPTO_ALG_ASYNC,
36954 + .cra_blocksize = DES_BLOCK_SIZE,
36955 + .cra_ctxsize = sizeof(struct omap_des_ctx),
36956 + .cra_alignmask = 0,
36957 + .cra_type = &crypto_ablkcipher_type,
36958 + .cra_module = THIS_MODULE,
36959 + .cra_init = omap_des_cra_init,
36960 + .cra_exit = omap_des_cra_exit,
36961 + .cra_u.ablkcipher = {
36962 + .min_keysize = DES_KEY_SIZE,
36963 + .max_keysize = DES_KEY_SIZE,
36964 + .setkey = omap_des_setkey,
36965 + .encrypt = omap_des_ecb_encrypt,
36966 + .decrypt = omap_des_ecb_decrypt,
36967 + }
36968 +},
36969 +{
36970 + .cra_name = "cbc(des)",
36971 + .cra_driver_name = "cbc-des-omap",
36972 + .cra_priority = 100,
36973 + .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
36974 + CRYPTO_ALG_KERN_DRIVER_ONLY |
36975 + CRYPTO_ALG_ASYNC,
36976 + .cra_blocksize = DES_BLOCK_SIZE,
36977 + .cra_ctxsize = sizeof(struct omap_des_ctx),
36978 + .cra_alignmask = 0,
36979 + .cra_type = &crypto_ablkcipher_type,
36980 + .cra_module = THIS_MODULE,
36981 + .cra_init = omap_des_cra_init,
36982 + .cra_exit = omap_des_cra_exit,
36983 + .cra_u.ablkcipher = {
36984 + .min_keysize = DES_KEY_SIZE,
36985 + .max_keysize = DES_KEY_SIZE,
36986 + .ivsize = DES_BLOCK_SIZE,
36987 + .setkey = omap_des_setkey,
36988 + .encrypt = omap_des_cbc_encrypt,
36989 + .decrypt = omap_des_cbc_decrypt,
36990 + }
36991 +},
36992 +{
36993 + .cra_name = "ecb(des3_ede)",
36994 + .cra_driver_name = "ecb-des3-omap",
36995 + .cra_priority = 100,
36996 + .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
36997 + CRYPTO_ALG_KERN_DRIVER_ONLY |
36998 + CRYPTO_ALG_ASYNC,
36999 + .cra_blocksize = DES_BLOCK_SIZE,
37000 + .cra_ctxsize = sizeof(struct omap_des_ctx),
37001 + .cra_alignmask = 0,
37002 + .cra_type = &crypto_ablkcipher_type,
37003 + .cra_module = THIS_MODULE,
37004 + .cra_init = omap_des_cra_init,
37005 + .cra_exit = omap_des_cra_exit,
37006 + .cra_u.ablkcipher = {
37007 + .min_keysize = 3*DES_KEY_SIZE,
37008 + .max_keysize = 3*DES_KEY_SIZE,
37009 + .setkey = omap_des_setkey,
37010 + .encrypt = omap_des_ecb_encrypt,
37011 + .decrypt = omap_des_ecb_decrypt,
37012 + }
37013 +},
37014 +{
37015 + .cra_name = "cbc(des3_ede)",
37016 + .cra_driver_name = "cbc-des3-omap",
37017 + .cra_priority = 100,
37018 + .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
37019 + CRYPTO_ALG_KERN_DRIVER_ONLY |
37020 + CRYPTO_ALG_ASYNC,
37021 + .cra_blocksize = DES_BLOCK_SIZE,
37022 + .cra_ctxsize = sizeof(struct omap_des_ctx),
37023 + .cra_alignmask = 0,
37024 + .cra_type = &crypto_ablkcipher_type,
37025 + .cra_module = THIS_MODULE,
37026 + .cra_init = omap_des_cra_init,
37027 + .cra_exit = omap_des_cra_exit,
37028 + .cra_u.ablkcipher = {
37029 + .min_keysize = 3*DES_KEY_SIZE,
37030 + .max_keysize = 3*DES_KEY_SIZE,
37031 + .ivsize = DES_BLOCK_SIZE,
37032 + .setkey = omap_des_setkey,
37033 + .encrypt = omap_des_cbc_encrypt,
37034 + .decrypt = omap_des_cbc_decrypt,
37035 + }
37036 +}
37037 +};
37038 +
37039 +static struct omap_des_algs_info omap_des_algs_info_ecb_cbc[] = {
37040 + {
37041 + .algs_list = algs_ecb_cbc,
37042 + .size = ARRAY_SIZE(algs_ecb_cbc),
37043 + },
37044 +};
37045 +
37046 +#ifdef CONFIG_OF
37047 +static const struct omap_des_pdata omap_des_pdata_omap4 = {
37048 + .algs_info = omap_des_algs_info_ecb_cbc,
37049 + .algs_info_size = ARRAY_SIZE(omap_des_algs_info_ecb_cbc),
37050 + .trigger = omap_des_dma_trigger_omap4,
37051 + .key_ofs = 0x14,
37052 + .iv_ofs = 0x18,
37053 + .ctrl_ofs = 0x20,
37054 + .data_ofs = 0x28,
37055 + .rev_ofs = 0x30,
37056 + .mask_ofs = 0x34,
37057 + .irq_status_ofs = 0x3c,
37058 + .irq_enable_ofs = 0x40,
37059 + .dma_enable_in = BIT(5),
37060 + .dma_enable_out = BIT(6),
37061 + .major_mask = 0x0700,
37062 + .major_shift = 8,
37063 + .minor_mask = 0x003f,
37064 + .minor_shift = 0,
37065 +};
37066 +
37067 +static irqreturn_t omap_des_irq(int irq, void *dev_id)
37068 +{
37069 + struct omap_des_dev *dd = dev_id;
37070 + u32 status, i;
37071 + u32 *src, *dst;
37072 +
37073 + status = omap_des_read(dd, DES_REG_IRQ_STATUS(dd));
37074 + if (status & DES_REG_IRQ_DATA_IN) {
37075 + omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x0);
37076 +
37077 + BUG_ON(!dd->in_sg);
37078 +
37079 + BUG_ON(_calc_walked(in) > dd->in_sg->length);
37080 +
37081 + src = sg_virt(dd->in_sg) + _calc_walked(in);
37082 +
37083 + for (i = 0; i < DES_BLOCK_WORDS; i++) {
37084 + omap_des_write(dd, DES_REG_DATA_N(dd, i), *src);
37085 +
37086 + scatterwalk_advance(&dd->in_walk, 4);
37087 + if (dd->in_sg->length == _calc_walked(in)) {
37088 + dd->in_sg = scatterwalk_sg_next(dd->in_sg);
37089 + if (dd->in_sg) {
37090 + scatterwalk_start(&dd->in_walk,
37091 + dd->in_sg);
37092 + src = sg_virt(dd->in_sg) +
37093 + _calc_walked(in);
37094 + }
37095 + } else {
37096 + src++;
37097 + }
37098 + }
37099 +
37100 + /* Clear IRQ status */
37101 + status &= ~DES_REG_IRQ_DATA_IN;
37102 + omap_des_write(dd, DES_REG_IRQ_STATUS(dd), status);
37103 +
37104 + /* Enable DATA_OUT interrupt */
37105 + omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x4);
37106 +
37107 + } else if (status & DES_REG_IRQ_DATA_OUT) {
37108 + omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x0);
37109 +
37110 + BUG_ON(!dd->out_sg);
37111 +
37112 + BUG_ON(_calc_walked(out) > dd->out_sg->length);
37113 +
37114 + dst = sg_virt(dd->out_sg) + _calc_walked(out);
37115 +
37116 + for (i = 0; i < DES_BLOCK_WORDS; i++) {
37117 + *dst = omap_des_read(dd, DES_REG_DATA_N(dd, i));
37118 + scatterwalk_advance(&dd->out_walk, 4);
37119 + if (dd->out_sg->length == _calc_walked(out)) {
37120 + dd->out_sg = scatterwalk_sg_next(dd->out_sg);
37121 + if (dd->out_sg) {
37122 + scatterwalk_start(&dd->out_walk,
37123 + dd->out_sg);
37124 + dst = sg_virt(dd->out_sg) +
37125 + _calc_walked(out);
37126 + }
37127 + } else {
37128 + dst++;
37129 + }
37130 + }
37131 +
37132 + dd->total -= DES_BLOCK_SIZE;
37133 +
37134 + BUG_ON(dd->total < 0);
37135 +
37136 + /* Clear IRQ status */
37137 + status &= ~DES_REG_IRQ_DATA_OUT;
37138 + omap_des_write(dd, DES_REG_IRQ_STATUS(dd), status);
37139 +
37140 + if (!dd->total)
37141 + /* All bytes read! */
37142 + tasklet_schedule(&dd->done_task);
37143 + else
37144 + /* Enable DATA_IN interrupt for next block */
37145 + omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x2);
37146 + }
37147 +
37148 + return IRQ_HANDLED;
37149 +}
37150 +
37151 +static const struct of_device_id omap_des_of_match[] = {
37152 + {
37153 + .compatible = "ti,omap4-des",
37154 + .data = &omap_des_pdata_omap4,
37155 + },
37156 + {},
37157 +};
37158 +MODULE_DEVICE_TABLE(of, omap_des_of_match);
37159 +
37160 +static int omap_des_get_res_of(struct omap_des_dev *dd,
37161 + struct device *dev, struct resource *res)
37162 +{
37163 + struct device_node *node = dev->of_node;
37164 + const struct of_device_id *match;
37165 + int err = 0;
37166 +
37167 + match = of_match_device(of_match_ptr(omap_des_of_match), dev);
37168 + if (!match) {
37169 + dev_err(dev, "no compatible OF match\n");
37170 + err = -EINVAL;
37171 + goto err;
37172 + }
37173 +
37174 + err = of_address_to_resource(node, 0, res);
37175 + if (err < 0) {
37176 + dev_err(dev, "can't translate OF node address\n");
37177 + err = -EINVAL;
37178 + goto err;
37179 + }
37180 +
37181 + dd->dma_out = -1; /* Dummy value that's unused */
37182 + dd->dma_in = -1; /* Dummy value that's unused */
37183 +
37184 + dd->pdata = match->data;
37185 +
37186 +err:
37187 + return err;
37188 +}
37189 +#else
37190 +static const struct of_device_id omap_des_of_match[] = {
37191 + {},
37192 +};
37193 +
37194 +static int omap_des_get_res_of(struct omap_des_dev *dd,
37195 + struct device *dev, struct resource *res)
37196 +{
37197 + return -EINVAL;
37198 +}
37199 +#endif
37200 +
37201 +static int omap_des_get_res_pdev(struct omap_des_dev *dd,
37202 + struct platform_device *pdev, struct resource *res)
37203 +{
37204 + struct device *dev = &pdev->dev;
37205 + struct resource *r;
37206 + int err = 0;
37207 +
37208 + /* Get the base address */
37209 + r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
37210 + if (!r) {
37211 + dev_err(dev, "no MEM resource info\n");
37212 + err = -ENODEV;
37213 + goto err;
37214 + }
37215 + memcpy(res, r, sizeof(*res));
37216 +
37217 + /* Get the DMA out channel */
37218 + r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
37219 + if (!r) {
37220 + dev_err(dev, "no DMA out resource info\n");
37221 + err = -ENODEV;
37222 + goto err;
37223 + }
37224 + dd->dma_out = r->start;
37225 +
37226 + /* Get the DMA in channel */
37227 + r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
37228 + if (!r) {
37229 + dev_err(dev, "no DMA in resource info\n");
37230 + err = -ENODEV;
37231 + goto err;
37232 + }
37233 + dd->dma_in = r->start;
37234 +
37235 + /* non-DT devices get pdata from pdev */
37236 + dd->pdata = pdev->dev.platform_data;
37237 +
37238 +err:
37239 + return err;
37240 +}
37241 +
37242 +static int omap_des_probe(struct platform_device *pdev)
37243 +{
37244 + struct device *dev = &pdev->dev;
37245 + struct omap_des_dev *dd;
37246 + struct crypto_alg *algp;
37247 + struct resource res;
37248 + int err = -ENOMEM, i, j, irq = -1;
37249 + u32 reg;
37250 +
37251 + dd = devm_kzalloc(dev, sizeof(struct omap_des_dev), GFP_KERNEL);
37252 + if (dd == NULL) {
37253 + dev_err(dev, "unable to alloc data struct.\n");
37254 + goto err_data;
37255 + }
37256 + dd->dev = dev;
37257 + platform_set_drvdata(pdev, dd);
37258 +
37259 + spin_lock_init(&dd->lock);
37260 + crypto_init_queue(&dd->queue, OMAP_DES_QUEUE_LENGTH);
37261 +
37262 + err = (dev->of_node) ? omap_des_get_res_of(dd, dev, &res) :
37263 + omap_des_get_res_pdev(dd, pdev, &res);
37264 + if (err)
37265 + goto err_res;
37266 +
37267 + dd->io_base = devm_request_and_ioremap(dev, &res);
37268 + if (!dd->io_base) {
37269 + dev_err(dev, "can't ioremap\n");
37270 + err = -ENOMEM;
37271 + goto err_res;
37272 + }
37273 + dd->phys_base = res.start;
37274 +
37275 + pm_runtime_enable(dev);
37276 + pm_runtime_get_sync(dev);
37277 +
37278 + omap_des_dma_stop(dd);
37279 +
37280 + reg = omap_des_read(dd, DES_REG_REV(dd));
37281 +
37282 + pm_runtime_put_sync(dev);
37283 +
37284 + dev_info(dev, "OMAP DES hw accel rev: %u.%u\n",
37285 + (reg & dd->pdata->major_mask) >> dd->pdata->major_shift,
37286 + (reg & dd->pdata->minor_mask) >> dd->pdata->minor_shift);
37287 +
37288 + tasklet_init(&dd->done_task, omap_des_done_task, (unsigned long)dd);
37289 + tasklet_init(&dd->queue_task, omap_des_queue_task, (unsigned long)dd);
37290 +
37291 + err = omap_des_dma_init(dd);
37292 + if (err && DES_REG_IRQ_STATUS(dd) && DES_REG_IRQ_ENABLE(dd)) {
37293 + dd->pio_only = 1;
37294 +
37295 + irq = platform_get_irq(pdev, 0);
37296 + if (irq < 0) {
37297 + dev_err(dev, "can't get IRQ resource\n");
37298 + goto err_irq;
37299 + }
37300 +
37301 + err = devm_request_irq(dev, irq, omap_des_irq, 0,
37302 + dev_name(dev), dd);
37303 + if (err) {
37304 + dev_err(dev, "Unable to grab omap-des IRQ\n");
37305 + goto err_irq;
37306 + }
37307 + }
37308 +
37309 +
37310 + INIT_LIST_HEAD(&dd->list);
37311 + spin_lock(&list_lock);
37312 + list_add_tail(&dd->list, &dev_list);
37313 + spin_unlock(&list_lock);
37314 +
37315 + for (i = 0; i < dd->pdata->algs_info_size; i++) {
37316 + for (j = 0; j < dd->pdata->algs_info[i].size; j++) {
37317 + algp = &dd->pdata->algs_info[i].algs_list[j];
37318 +
37319 + pr_debug("reg alg: %s\n", algp->cra_name);
37320 + INIT_LIST_HEAD(&algp->cra_list);
37321 +
37322 + err = crypto_register_alg(algp);
37323 + if (err)
37324 + goto err_algs;
37325 +
37326 + dd->pdata->algs_info[i].registered++;
37327 + }
37328 + }
37329 +
37330 + return 0;
37331 +err_algs:
37332 + for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
37333 + for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
37334 + crypto_unregister_alg(
37335 + &dd->pdata->algs_info[i].algs_list[j]);
37336 + if (!dd->pio_only)
37337 + omap_des_dma_cleanup(dd);
37338 +err_irq:
37339 + tasklet_kill(&dd->done_task);
37340 + tasklet_kill(&dd->queue_task);
37341 + pm_runtime_disable(dev);
37342 +err_res:
37343 + dd = NULL;
37344 +err_data:
37345 + dev_err(dev, "initialization failed.\n");
37346 + return err;
37347 +}
37348 +
37349 +static int omap_des_remove(struct platform_device *pdev)
37350 +{
37351 + struct omap_des_dev *dd = platform_get_drvdata(pdev);
37352 + int i, j;
37353 +
37354 + if (!dd)
37355 + return -ENODEV;
37356 +
37357 + spin_lock(&list_lock);
37358 + list_del(&dd->list);
37359 + spin_unlock(&list_lock);
37360 +
37361 + for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
37362 + for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
37363 + crypto_unregister_alg(
37364 + &dd->pdata->algs_info[i].algs_list[j]);
37365 +
37366 + tasklet_kill(&dd->done_task);
37367 + tasklet_kill(&dd->queue_task);
37368 + omap_des_dma_cleanup(dd);
37369 + pm_runtime_disable(dd->dev);
37370 + dd = NULL;
37371 +
37372 + return 0;
37373 +}
37374 +
37375 +#ifdef CONFIG_PM_SLEEP
37376 +static int omap_des_suspend(struct device *dev)
37377 +{
37378 + pm_runtime_put_sync(dev);
37379 + return 0;
37380 +}
37381 +
37382 +static int omap_des_resume(struct device *dev)
37383 +{
37384 + pm_runtime_get_sync(dev);
37385 + return 0;
37386 +}
37387 +#endif
37388 +
37389 +static const struct dev_pm_ops omap_des_pm_ops = {
37390 + SET_SYSTEM_SLEEP_PM_OPS(omap_des_suspend, omap_des_resume)
37391 +};
37392 +
37393 +static struct platform_driver omap_des_driver = {
37394 + .probe = omap_des_probe,
37395 + .remove = omap_des_remove,
37396 + .driver = {
37397 + .name = "omap-des",
37398 + .owner = THIS_MODULE,
37399 + .pm = &omap_des_pm_ops,
37400 + .of_match_table = omap_des_of_match,
37401 + },
37402 +};
37403 +
37404 +module_platform_driver(omap_des_driver);
37405 +
37406 +MODULE_DESCRIPTION("OMAP DES hw acceleration support.");
37407 +MODULE_LICENSE("GPL v2");
37408 +MODULE_AUTHOR("Joel Fernandes <joelf@ti.com>");
37409 --- a/drivers/dma/amba-pl08x.c
37410 +++ b/drivers/dma/amba-pl08x.c
37411 @@ -2133,8 +2133,7 @@ static int pl08x_probe(struct amba_devic
37412 writel(0x000000FF, pl08x->base + PL080_ERR_CLEAR);
37413 writel(0x000000FF, pl08x->base + PL080_TC_CLEAR);
37414
37415 - ret = request_irq(adev->irq[0], pl08x_irq, IRQF_DISABLED,
37416 - DRIVER_NAME, pl08x);
37417 + ret = request_irq(adev->irq[0], pl08x_irq, 0, DRIVER_NAME, pl08x);
37418 if (ret) {
37419 dev_err(&adev->dev, "%s failed to request interrupt %d\n",
37420 __func__, adev->irq[0]);
37421 --- a/drivers/dma/coh901318.c
37422 +++ b/drivers/dma/coh901318.c
37423 @@ -2694,7 +2694,7 @@ static int __init coh901318_probe(struct
37424 if (irq < 0)
37425 return irq;
37426
37427 - err = devm_request_irq(&pdev->dev, irq, dma_irq_handler, IRQF_DISABLED,
37428 + err = devm_request_irq(&pdev->dev, irq, dma_irq_handler, 0,
37429 "coh901318", base);
37430 if (err)
37431 return err;
37432 --- a/drivers/dma/cppi41.c
37433 +++ b/drivers/dma/cppi41.c
37434 @@ -141,6 +141,9 @@ struct cppi41_dd {
37435 const struct chan_queues *queues_rx;
37436 const struct chan_queues *queues_tx;
37437 struct chan_queues td_queue;
37438 +
37439 + /* context for suspend/resume */
37440 + unsigned int dma_tdfdq;
37441 };
37442
37443 #define FIST_COMPLETION_QUEUE 93
37444 @@ -263,6 +266,15 @@ static u32 pd_trans_len(u32 val)
37445 return val & ((1 << (DESC_LENGTH_BITS_NUM + 1)) - 1);
37446 }
37447
37448 +static u32 cppi41_pop_desc(struct cppi41_dd *cdd, unsigned queue_num)
37449 +{
37450 + u32 desc;
37451 +
37452 + desc = cppi_readl(cdd->qmgr_mem + QMGR_QUEUE_D(queue_num));
37453 + desc &= ~0x1f;
37454 + return desc;
37455 +}
37456 +
37457 static irqreturn_t cppi41_irq(int irq, void *data)
37458 {
37459 struct cppi41_dd *cdd = data;
37460 @@ -300,8 +312,7 @@ static irqreturn_t cppi41_irq(int irq, v
37461 q_num = __fls(val);
37462 val &= ~(1 << q_num);
37463 q_num += 32 * i;
37464 - desc = cppi_readl(cdd->qmgr_mem + QMGR_QUEUE_D(q_num));
37465 - desc &= ~0x1f;
37466 + desc = cppi41_pop_desc(cdd, q_num);
37467 c = desc_to_chan(cdd, desc);
37468 if (WARN_ON(!c)) {
37469 pr_err("%s() q %d desc %08x\n", __func__,
37470 @@ -517,15 +528,6 @@ static void cppi41_compute_td_desc(struc
37471 d->pd0 = DESC_TYPE_TEARD << DESC_TYPE;
37472 }
37473
37474 -static u32 cppi41_pop_desc(struct cppi41_dd *cdd, unsigned queue_num)
37475 -{
37476 - u32 desc;
37477 -
37478 - desc = cppi_readl(cdd->qmgr_mem + QMGR_QUEUE_D(queue_num));
37479 - desc &= ~0x1f;
37480 - return desc;
37481 -}
37482 -
37483 static int cppi41_tear_down_chan(struct cppi41_channel *c)
37484 {
37485 struct cppi41_dd *cdd = c->cdd;
37486 @@ -561,36 +563,26 @@ static int cppi41_tear_down_chan(struct
37487 c->td_retry = 100;
37488 }
37489
37490 - if (!c->td_seen) {
37491 - unsigned td_comp_queue;
37492 + if (!c->td_seen || !c->td_desc_seen) {
37493
37494 - if (c->is_tx)
37495 - td_comp_queue = cdd->td_queue.complete;
37496 - else
37497 - td_comp_queue = c->q_comp_num;
37498 + desc_phys = cppi41_pop_desc(cdd, cdd->td_queue.complete);
37499 + if (!desc_phys)
37500 + desc_phys = cppi41_pop_desc(cdd, c->q_comp_num);
37501
37502 - desc_phys = cppi41_pop_desc(cdd, td_comp_queue);
37503 - if (desc_phys) {
37504 - __iormb();
37505 + if (desc_phys == c->desc_phys) {
37506 + c->td_desc_seen = 1;
37507 +
37508 + } else if (desc_phys == td_desc_phys) {
37509 + u32 pd0;
37510
37511 - if (desc_phys == td_desc_phys) {
37512 - u32 pd0;
37513 - pd0 = td->pd0;
37514 - WARN_ON((pd0 >> DESC_TYPE) != DESC_TYPE_TEARD);
37515 - WARN_ON(!c->is_tx && !(pd0 & TD_DESC_IS_RX));
37516 - WARN_ON((pd0 & 0x1f) != c->port_num);
37517 - } else {
37518 - WARN_ON_ONCE(1);
37519 - }
37520 - c->td_seen = 1;
37521 - }
37522 - }
37523 - if (!c->td_desc_seen) {
37524 - desc_phys = cppi41_pop_desc(cdd, c->q_comp_num);
37525 - if (desc_phys) {
37526 __iormb();
37527 - WARN_ON(c->desc_phys != desc_phys);
37528 - c->td_desc_seen = 1;
37529 + pd0 = td->pd0;
37530 + WARN_ON((pd0 >> DESC_TYPE) != DESC_TYPE_TEARD);
37531 + WARN_ON(!c->is_tx && !(pd0 & TD_DESC_IS_RX));
37532 + WARN_ON((pd0 & 0x1f) != c->port_num);
37533 + c->td_seen = 1;
37534 + } else if (desc_phys) {
37535 + WARN_ON_ONCE(1);
37536 }
37537 }
37538 c->td_retry--;
37539 @@ -609,7 +601,7 @@ static int cppi41_tear_down_chan(struct
37540
37541 WARN_ON(!c->td_retry);
37542 if (!c->td_desc_seen) {
37543 - desc_phys = cppi_readl(cdd->qmgr_mem + QMGR_QUEUE_D(c->q_num));
37544 + desc_phys = cppi41_pop_desc(cdd, c->q_num);
37545 WARN_ON(!desc_phys);
37546 }
37547
37548 @@ -674,14 +666,14 @@ static void cleanup_chans(struct cppi41_
37549 }
37550 }
37551
37552 -static int cppi41_add_chans(struct platform_device *pdev, struct cppi41_dd *cdd)
37553 +static int cppi41_add_chans(struct device *dev, struct cppi41_dd *cdd)
37554 {
37555 struct cppi41_channel *cchan;
37556 int i;
37557 int ret;
37558 u32 n_chans;
37559
37560 - ret = of_property_read_u32(pdev->dev.of_node, "#dma-channels",
37561 + ret = of_property_read_u32(dev->of_node, "#dma-channels",
37562 &n_chans);
37563 if (ret)
37564 return ret;
37565 @@ -719,7 +711,7 @@ err:
37566 return -ENOMEM;
37567 }
37568
37569 -static void purge_descs(struct platform_device *pdev, struct cppi41_dd *cdd)
37570 +static void purge_descs(struct device *dev, struct cppi41_dd *cdd)
37571 {
37572 unsigned int mem_decs;
37573 int i;
37574 @@ -731,7 +723,7 @@ static void purge_descs(struct platform_
37575 cppi_writel(0, cdd->qmgr_mem + QMGR_MEMBASE(i));
37576 cppi_writel(0, cdd->qmgr_mem + QMGR_MEMCTRL(i));
37577
37578 - dma_free_coherent(&pdev->dev, mem_decs, cdd->cd,
37579 + dma_free_coherent(dev, mem_decs, cdd->cd,
37580 cdd->descs_phys);
37581 }
37582 }
37583 @@ -741,19 +733,19 @@ static void disable_sched(struct cppi41_
37584 cppi_writel(0, cdd->sched_mem + DMA_SCHED_CTRL);
37585 }
37586
37587 -static void deinit_cpii41(struct platform_device *pdev, struct cppi41_dd *cdd)
37588 +static void deinit_cppi41(struct device *dev, struct cppi41_dd *cdd)
37589 {
37590 disable_sched(cdd);
37591
37592 - purge_descs(pdev, cdd);
37593 + purge_descs(dev, cdd);
37594
37595 cppi_writel(0, cdd->qmgr_mem + QMGR_LRAM0_BASE);
37596 cppi_writel(0, cdd->qmgr_mem + QMGR_LRAM0_BASE);
37597 - dma_free_coherent(&pdev->dev, QMGR_SCRATCH_SIZE, cdd->qmgr_scratch,
37598 + dma_free_coherent(dev, QMGR_SCRATCH_SIZE, cdd->qmgr_scratch,
37599 cdd->scratch_phys);
37600 }
37601
37602 -static int init_descs(struct platform_device *pdev, struct cppi41_dd *cdd)
37603 +static int init_descs(struct device *dev, struct cppi41_dd *cdd)
37604 {
37605 unsigned int desc_size;
37606 unsigned int mem_decs;
37607 @@ -777,7 +769,7 @@ static int init_descs(struct platform_de
37608 reg |= ilog2(ALLOC_DECS_NUM) - 5;
37609
37610 BUILD_BUG_ON(DESCS_AREAS != 1);
37611 - cdd->cd = dma_alloc_coherent(&pdev->dev, mem_decs,
37612 + cdd->cd = dma_alloc_coherent(dev, mem_decs,
37613 &cdd->descs_phys, GFP_KERNEL);
37614 if (!cdd->cd)
37615 return -ENOMEM;
37616 @@ -813,12 +805,12 @@ static void init_sched(struct cppi41_dd
37617 cppi_writel(reg, cdd->sched_mem + DMA_SCHED_CTRL);
37618 }
37619
37620 -static int init_cppi41(struct platform_device *pdev, struct cppi41_dd *cdd)
37621 +static int init_cppi41(struct device *dev, struct cppi41_dd *cdd)
37622 {
37623 int ret;
37624
37625 BUILD_BUG_ON(QMGR_SCRATCH_SIZE > ((1 << 14) - 1));
37626 - cdd->qmgr_scratch = dma_alloc_coherent(&pdev->dev, QMGR_SCRATCH_SIZE,
37627 + cdd->qmgr_scratch = dma_alloc_coherent(dev, QMGR_SCRATCH_SIZE,
37628 &cdd->scratch_phys, GFP_KERNEL);
37629 if (!cdd->qmgr_scratch)
37630 return -ENOMEM;
37631 @@ -827,7 +819,7 @@ static int init_cppi41(struct platform_d
37632 cppi_writel(QMGR_SCRATCH_SIZE, cdd->qmgr_mem + QMGR_LRAM_SIZE);
37633 cppi_writel(0, cdd->qmgr_mem + QMGR_LRAM1_BASE);
37634
37635 - ret = init_descs(pdev, cdd);
37636 + ret = init_descs(dev, cdd);
37637 if (ret)
37638 goto err_td;
37639
37640 @@ -835,7 +827,7 @@ static int init_cppi41(struct platform_d
37641 init_sched(cdd);
37642 return 0;
37643 err_td:
37644 - deinit_cpii41(pdev, cdd);
37645 + deinit_cppi41(dev, cdd);
37646 return ret;
37647 }
37648
37649 @@ -914,11 +906,11 @@ static const struct of_device_id cppi41_
37650 };
37651 MODULE_DEVICE_TABLE(of, cppi41_dma_ids);
37652
37653 -static const struct cppi_glue_infos *get_glue_info(struct platform_device *pdev)
37654 +static const struct cppi_glue_infos *get_glue_info(struct device *dev)
37655 {
37656 const struct of_device_id *of_id;
37657
37658 - of_id = of_match_node(cppi41_dma_ids, pdev->dev.of_node);
37659 + of_id = of_match_node(cppi41_dma_ids, dev->of_node);
37660 if (!of_id)
37661 return NULL;
37662 return of_id->data;
37663 @@ -927,11 +919,12 @@ static const struct cppi_glue_infos *get
37664 static int cppi41_dma_probe(struct platform_device *pdev)
37665 {
37666 struct cppi41_dd *cdd;
37667 + struct device *dev = &pdev->dev;
37668 const struct cppi_glue_infos *glue_info;
37669 int irq;
37670 int ret;
37671
37672 - glue_info = get_glue_info(pdev);
37673 + glue_info = get_glue_info(dev);
37674 if (!glue_info)
37675 return -EINVAL;
37676
37677 @@ -946,14 +939,14 @@ static int cppi41_dma_probe(struct platf
37678 cdd->ddev.device_issue_pending = cppi41_dma_issue_pending;
37679 cdd->ddev.device_prep_slave_sg = cppi41_dma_prep_slave_sg;
37680 cdd->ddev.device_control = cppi41_dma_control;
37681 - cdd->ddev.dev = &pdev->dev;
37682 + cdd->ddev.dev = dev;
37683 INIT_LIST_HEAD(&cdd->ddev.channels);
37684 cpp41_dma_info.dma_cap = cdd->ddev.cap_mask;
37685
37686 - cdd->usbss_mem = of_iomap(pdev->dev.of_node, 0);
37687 - cdd->ctrl_mem = of_iomap(pdev->dev.of_node, 1);
37688 - cdd->sched_mem = of_iomap(pdev->dev.of_node, 2);
37689 - cdd->qmgr_mem = of_iomap(pdev->dev.of_node, 3);
37690 + cdd->usbss_mem = of_iomap(dev->of_node, 0);
37691 + cdd->ctrl_mem = of_iomap(dev->of_node, 1);
37692 + cdd->sched_mem = of_iomap(dev->of_node, 2);
37693 + cdd->qmgr_mem = of_iomap(dev->of_node, 3);
37694
37695 if (!cdd->usbss_mem || !cdd->ctrl_mem || !cdd->sched_mem ||
37696 !cdd->qmgr_mem) {
37697 @@ -961,31 +954,31 @@ static int cppi41_dma_probe(struct platf
37698 goto err_remap;
37699 }
37700
37701 - pm_runtime_enable(&pdev->dev);
37702 - ret = pm_runtime_get_sync(&pdev->dev);
37703 - if (ret)
37704 + pm_runtime_enable(dev);
37705 + ret = pm_runtime_get_sync(dev);
37706 + if (ret < 0)
37707 goto err_get_sync;
37708
37709 cdd->queues_rx = glue_info->queues_rx;
37710 cdd->queues_tx = glue_info->queues_tx;
37711 cdd->td_queue = glue_info->td_queue;
37712
37713 - ret = init_cppi41(pdev, cdd);
37714 + ret = init_cppi41(dev, cdd);
37715 if (ret)
37716 goto err_init_cppi;
37717
37718 - ret = cppi41_add_chans(pdev, cdd);
37719 + ret = cppi41_add_chans(dev, cdd);
37720 if (ret)
37721 goto err_chans;
37722
37723 - irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
37724 + irq = irq_of_parse_and_map(dev->of_node, 0);
37725 if (!irq)
37726 goto err_irq;
37727
37728 cppi_writel(USBSS_IRQ_PD_COMP, cdd->usbss_mem + USBSS_IRQ_ENABLER);
37729
37730 ret = request_irq(irq, glue_info->isr, IRQF_SHARED,
37731 - dev_name(&pdev->dev), cdd);
37732 + dev_name(dev), cdd);
37733 if (ret)
37734 goto err_irq;
37735 cdd->irq = irq;
37736 @@ -994,7 +987,7 @@ static int cppi41_dma_probe(struct platf
37737 if (ret)
37738 goto err_dma_reg;
37739
37740 - ret = of_dma_controller_register(pdev->dev.of_node,
37741 + ret = of_dma_controller_register(dev->of_node,
37742 cppi41_dma_xlate, &cpp41_dma_info);
37743 if (ret)
37744 goto err_of;
37745 @@ -1009,11 +1002,11 @@ err_irq:
37746 cppi_writel(0, cdd->usbss_mem + USBSS_IRQ_CLEARR);
37747 cleanup_chans(cdd);
37748 err_chans:
37749 - deinit_cpii41(pdev, cdd);
37750 + deinit_cppi41(dev, cdd);
37751 err_init_cppi:
37752 - pm_runtime_put(&pdev->dev);
37753 + pm_runtime_put(dev);
37754 err_get_sync:
37755 - pm_runtime_disable(&pdev->dev);
37756 + pm_runtime_disable(dev);
37757 iounmap(cdd->usbss_mem);
37758 iounmap(cdd->ctrl_mem);
37759 iounmap(cdd->sched_mem);
37760 @@ -1033,7 +1026,7 @@ static int cppi41_dma_remove(struct plat
37761 cppi_writel(0, cdd->usbss_mem + USBSS_IRQ_CLEARR);
37762 free_irq(cdd->irq, cdd);
37763 cleanup_chans(cdd);
37764 - deinit_cpii41(pdev, cdd);
37765 + deinit_cppi41(&pdev->dev, cdd);
37766 iounmap(cdd->usbss_mem);
37767 iounmap(cdd->ctrl_mem);
37768 iounmap(cdd->sched_mem);
37769 @@ -1044,12 +1037,53 @@ static int cppi41_dma_remove(struct plat
37770 return 0;
37771 }
37772
37773 +#ifdef CONFIG_PM_SLEEP
37774 +static int cppi41_suspend(struct device *dev)
37775 +{
37776 + struct cppi41_dd *cdd = dev_get_drvdata(dev);
37777 +
37778 + cdd->dma_tdfdq = cppi_readl(cdd->ctrl_mem + DMA_TDFDQ);
37779 + cppi_writel(0, cdd->usbss_mem + USBSS_IRQ_CLEARR);
37780 + disable_sched(cdd);
37781 +
37782 + return 0;
37783 +}
37784 +
37785 +static int cppi41_resume(struct device *dev)
37786 +{
37787 + struct cppi41_dd *cdd = dev_get_drvdata(dev);
37788 + struct cppi41_channel *c;
37789 + int i;
37790 +
37791 + for (i = 0; i < DESCS_AREAS; i++)
37792 + cppi_writel(cdd->descs_phys, cdd->qmgr_mem + QMGR_MEMBASE(i));
37793 +
37794 + list_for_each_entry(c, &cdd->ddev.channels, chan.device_node)
37795 + if (!c->is_tx)
37796 + cppi_writel(c->q_num, c->gcr_reg + RXHPCRA0);
37797 +
37798 + init_sched(cdd);
37799 +
37800 + cppi_writel(cdd->dma_tdfdq, cdd->ctrl_mem + DMA_TDFDQ);
37801 + cppi_writel(cdd->scratch_phys, cdd->qmgr_mem + QMGR_LRAM0_BASE);
37802 + cppi_writel(QMGR_SCRATCH_SIZE, cdd->qmgr_mem + QMGR_LRAM_SIZE);
37803 + cppi_writel(0, cdd->qmgr_mem + QMGR_LRAM1_BASE);
37804 +
37805 + cppi_writel(USBSS_IRQ_PD_COMP, cdd->usbss_mem + USBSS_IRQ_ENABLER);
37806 +
37807 + return 0;
37808 +}
37809 +#endif
37810 +
37811 +static SIMPLE_DEV_PM_OPS(cppi41_pm_ops, cppi41_suspend, cppi41_resume);
37812 +
37813 static struct platform_driver cpp41_dma_driver = {
37814 .probe = cppi41_dma_probe,
37815 .remove = cppi41_dma_remove,
37816 .driver = {
37817 .name = "cppi41-dma-engine",
37818 .owner = THIS_MODULE,
37819 + .pm = &cppi41_pm_ops,
37820 .of_match_table = of_match_ptr(cppi41_dma_ids),
37821 },
37822 };
37823 --- a/drivers/dma/edma.c
37824 +++ b/drivers/dma/edma.c
37825 @@ -46,8 +46,14 @@
37826 #define EDMA_CHANS 64
37827 #endif /* CONFIG_ARCH_DAVINCI_DA8XX */
37828
37829 -/* Max of 16 segments per channel to conserve PaRAM slots */
37830 -#define MAX_NR_SG 16
37831 +/*
37832 + * Max of 20 segments per channel to conserve PaRAM slots
37833 + * Also note that MAX_NR_SG should be atleast the no.of periods
37834 + * that are required for ASoC, otherwise DMA prep calls will
37835 + * fail. Today davinci-pcm is the only user of this driver and
37836 + * requires atleast 17 slots, so we setup the default to 20.
37837 + */
37838 +#define MAX_NR_SG 20
37839 #define EDMA_MAX_SLOTS MAX_NR_SG
37840 #define EDMA_DESCRIPTORS 16
37841
37842 @@ -250,6 +256,117 @@ static int edma_control(struct dma_chan
37843 return ret;
37844 }
37845
37846 +/*
37847 + * A PaRAM set configuration abstraction used by other modes
37848 + * @chan: Channel who's PaRAM set we're configuring
37849 + * @pset: PaRAM set to initialize and setup.
37850 + * @src_addr: Source address of the DMA
37851 + * @dst_addr: Destination address of the DMA
37852 + * @burst: In units of dev_width, how much to send
37853 + * @dev_width: How much is the dev_width
37854 + * @dma_length: Total length of the DMA transfer
37855 + * @direction: Direction of the transfer
37856 + */
37857 +static int edma_config_pset(struct dma_chan *chan, struct edmacc_param *pset,
37858 + dma_addr_t src_addr, dma_addr_t dst_addr, u32 burst,
37859 + enum dma_slave_buswidth dev_width, unsigned int dma_length,
37860 + enum dma_transfer_direction direction)
37861 +{
37862 + struct edma_chan *echan = to_edma_chan(chan);
37863 + struct device *dev = chan->device->dev;
37864 + int acnt, bcnt, ccnt, cidx;
37865 + int src_bidx, dst_bidx, src_cidx, dst_cidx;
37866 + int absync;
37867 +
37868 + acnt = dev_width;
37869 + /*
37870 + * If the maxburst is equal to the fifo width, use
37871 + * A-synced transfers. This allows for large contiguous
37872 + * buffer transfers using only one PaRAM set.
37873 + */
37874 + if (burst == 1) {
37875 + /*
37876 + * For the A-sync case, bcnt and ccnt are the remainder
37877 + * and quotient respectively of the division of:
37878 + * (dma_length / acnt) by (SZ_64K -1). This is so
37879 + * that in case bcnt over flows, we have ccnt to use.
37880 + * Note: In A-sync tranfer only, bcntrld is used, but it
37881 + * only applies for sg_dma_len(sg) >= SZ_64K.
37882 + * In this case, the best way adopted is- bccnt for the
37883 + * first frame will be the remainder below. Then for
37884 + * every successive frame, bcnt will be SZ_64K-1. This
37885 + * is assured as bcntrld = 0xffff in end of function.
37886 + */
37887 + absync = false;
37888 + ccnt = dma_length / acnt / (SZ_64K - 1);
37889 + bcnt = dma_length / acnt - ccnt * (SZ_64K - 1);
37890 + /*
37891 + * If bcnt is non-zero, we have a remainder and hence an
37892 + * extra frame to transfer, so increment ccnt.
37893 + */
37894 + if (bcnt)
37895 + ccnt++;
37896 + else
37897 + bcnt = SZ_64K - 1;
37898 + cidx = acnt;
37899 + } else {
37900 + /*
37901 + * If maxburst is greater than the fifo address_width,
37902 + * use AB-synced transfers where A count is the fifo
37903 + * address_width and B count is the maxburst. In this
37904 + * case, we are limited to transfers of C count frames
37905 + * of (address_width * maxburst) where C count is limited
37906 + * to SZ_64K-1. This places an upper bound on the length
37907 + * of an SG segment that can be handled.
37908 + */
37909 + absync = true;
37910 + bcnt = burst;
37911 + ccnt = dma_length / (acnt * bcnt);
37912 + if (ccnt > (SZ_64K - 1)) {
37913 + dev_err(dev, "Exceeded max SG segment size\n");
37914 + return -EINVAL;
37915 + }
37916 + cidx = acnt * bcnt;
37917 + }
37918 +
37919 + if (direction == DMA_MEM_TO_DEV) {
37920 + src_bidx = acnt;
37921 + src_cidx = cidx;
37922 + dst_bidx = 0;
37923 + dst_cidx = 0;
37924 + } else if (direction == DMA_DEV_TO_MEM) {
37925 + src_bidx = 0;
37926 + src_cidx = 0;
37927 + dst_bidx = acnt;
37928 + dst_cidx = cidx;
37929 + } else {
37930 + dev_err(dev, "%s: direction not implemented yet\n", __func__);
37931 + return -EINVAL;
37932 + }
37933 +
37934 + pset->opt = EDMA_TCC(EDMA_CHAN_SLOT(echan->ch_num));
37935 + /* Configure A or AB synchronized transfers */
37936 + if (absync)
37937 + pset->opt |= SYNCDIM;
37938 +
37939 + pset->src = src_addr;
37940 + pset->dst = dst_addr;
37941 +
37942 + pset->src_dst_bidx = (dst_bidx << 16) | src_bidx;
37943 + pset->src_dst_cidx = (dst_cidx << 16) | src_cidx;
37944 +
37945 + pset->a_b_cnt = bcnt << 16 | acnt;
37946 + pset->ccnt = ccnt;
37947 + /*
37948 + * Only time when (bcntrld) auto reload is required is for
37949 + * A-sync case, and in this case, a requirement of reload value
37950 + * of SZ_64K-1 only is assured. 'link' is initially set to NULL
37951 + * and then later will be populated by edma_execute.
37952 + */
37953 + pset->link_bcntrld = 0xffffffff;
37954 + return absync;
37955 +}
37956 +
37957 static struct dma_async_tx_descriptor *edma_prep_slave_sg(
37958 struct dma_chan *chan, struct scatterlist *sgl,
37959 unsigned int sg_len, enum dma_transfer_direction direction,
37960 @@ -258,23 +375,21 @@ static struct dma_async_tx_descriptor *e
37961 struct edma_chan *echan = to_edma_chan(chan);
37962 struct device *dev = chan->device->dev;
37963 struct edma_desc *edesc;
37964 - dma_addr_t dev_addr;
37965 + dma_addr_t src_addr = 0, dst_addr = 0;
37966 enum dma_slave_buswidth dev_width;
37967 u32 burst;
37968 struct scatterlist *sg;
37969 - int acnt, bcnt, ccnt, src, dst, cidx;
37970 - int src_bidx, dst_bidx, src_cidx, dst_cidx;
37971 - int i, nslots;
37972 + int i, nslots, ret;
37973
37974 if (unlikely(!echan || !sgl || !sg_len))
37975 return NULL;
37976
37977 if (direction == DMA_DEV_TO_MEM) {
37978 - dev_addr = echan->cfg.src_addr;
37979 + src_addr = echan->cfg.src_addr;
37980 dev_width = echan->cfg.src_addr_width;
37981 burst = echan->cfg.src_maxburst;
37982 } else if (direction == DMA_MEM_TO_DEV) {
37983 - dev_addr = echan->cfg.dst_addr;
37984 + dst_addr = echan->cfg.dst_addr;
37985 dev_width = echan->cfg.dst_addr_width;
37986 burst = echan->cfg.dst_maxburst;
37987 } else {
37988 @@ -315,64 +430,19 @@ static struct dma_async_tx_descriptor *e
37989
37990 /* Configure PaRAM sets for each SG */
37991 for_each_sg(sgl, sg, sg_len, i) {
37992 + /* Get address for each SG */
37993 + if (direction == DMA_DEV_TO_MEM)
37994 + dst_addr = sg_dma_address(sg);
37995 + else
37996 + src_addr = sg_dma_address(sg);
37997 +
37998 + ret = edma_config_pset(chan, &edesc->pset[i], src_addr,
37999 + dst_addr, burst, dev_width,
38000 + sg_dma_len(sg), direction);
38001 + if (ret < 0)
38002 + return NULL;
38003
38004 - acnt = dev_width;
38005 -
38006 - /*
38007 - * If the maxburst is equal to the fifo width, use
38008 - * A-synced transfers. This allows for large contiguous
38009 - * buffer transfers using only one PaRAM set.
38010 - */
38011 - if (burst == 1) {
38012 - edesc->absync = false;
38013 - ccnt = sg_dma_len(sg) / acnt / (SZ_64K - 1);
38014 - bcnt = sg_dma_len(sg) / acnt - ccnt * (SZ_64K - 1);
38015 - if (bcnt)
38016 - ccnt++;
38017 - else
38018 - bcnt = SZ_64K - 1;
38019 - cidx = acnt;
38020 - /*
38021 - * If maxburst is greater than the fifo address_width,
38022 - * use AB-synced transfers where A count is the fifo
38023 - * address_width and B count is the maxburst. In this
38024 - * case, we are limited to transfers of C count frames
38025 - * of (address_width * maxburst) where C count is limited
38026 - * to SZ_64K-1. This places an upper bound on the length
38027 - * of an SG segment that can be handled.
38028 - */
38029 - } else {
38030 - edesc->absync = true;
38031 - bcnt = burst;
38032 - ccnt = sg_dma_len(sg) / (acnt * bcnt);
38033 - if (ccnt > (SZ_64K - 1)) {
38034 - dev_err(dev, "Exceeded max SG segment size\n");
38035 - kfree(edesc);
38036 - return NULL;
38037 - }
38038 - cidx = acnt * bcnt;
38039 - }
38040 -
38041 - if (direction == DMA_MEM_TO_DEV) {
38042 - src = sg_dma_address(sg);
38043 - dst = dev_addr;
38044 - src_bidx = acnt;
38045 - src_cidx = cidx;
38046 - dst_bidx = 0;
38047 - dst_cidx = 0;
38048 - } else {
38049 - src = dev_addr;
38050 - dst = sg_dma_address(sg);
38051 - src_bidx = 0;
38052 - src_cidx = 0;
38053 - dst_bidx = acnt;
38054 - dst_cidx = cidx;
38055 - }
38056 -
38057 - edesc->pset[i].opt = EDMA_TCC(EDMA_CHAN_SLOT(echan->ch_num));
38058 - /* Configure A or AB synchronized transfers */
38059 - if (edesc->absync)
38060 - edesc->pset[i].opt |= SYNCDIM;
38061 + edesc->absync = ret;
38062
38063 /* If this is the last in a current SG set of transactions,
38064 enable interrupts so that next set is processed */
38065 @@ -382,17 +452,6 @@ static struct dma_async_tx_descriptor *e
38066 /* If this is the last set, enable completion interrupt flag */
38067 if (i == sg_len - 1)
38068 edesc->pset[i].opt |= TCINTEN;
38069 -
38070 - edesc->pset[i].src = src;
38071 - edesc->pset[i].dst = dst;
38072 -
38073 - edesc->pset[i].src_dst_bidx = (dst_bidx << 16) | src_bidx;
38074 - edesc->pset[i].src_dst_cidx = (dst_cidx << 16) | src_cidx;
38075 -
38076 - edesc->pset[i].a_b_cnt = bcnt << 16 | acnt;
38077 - edesc->pset[i].ccnt = ccnt;
38078 - edesc->pset[i].link_bcntrld = 0xffffffff;
38079 -
38080 }
38081
38082 return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags);
38083 --- a/drivers/dma/k3dma.c
38084 +++ b/drivers/dma/k3dma.c
38085 @@ -693,7 +693,7 @@ static int k3_dma_probe(struct platform_
38086
38087 irq = platform_get_irq(op, 0);
38088 ret = devm_request_irq(&op->dev, irq,
38089 - k3_dma_int_handler, IRQF_DISABLED, DRIVER_NAME, d);
38090 + k3_dma_int_handler, 0, DRIVER_NAME, d);
38091 if (ret)
38092 return ret;
38093
38094 --- a/drivers/dma/mmp_pdma.c
38095 +++ b/drivers/dma/mmp_pdma.c
38096 @@ -798,8 +798,7 @@ static void dma_do_tasklet(unsigned long
38097 * move the descriptors to a temporary list so we can drop
38098 * the lock during the entire cleanup operation
38099 */
38100 - list_del(&desc->node);
38101 - list_add(&desc->node, &chain_cleanup);
38102 + list_move(&desc->node, &chain_cleanup);
38103
38104 /*
38105 * Look for the first list entry which has the ENDIRQEN flag
38106 @@ -863,7 +862,7 @@ static int mmp_pdma_chan_init(struct mmp
38107
38108 if (irq) {
38109 ret = devm_request_irq(pdev->dev, irq,
38110 - mmp_pdma_chan_handler, IRQF_DISABLED, "pdma", phy);
38111 + mmp_pdma_chan_handler, 0, "pdma", phy);
38112 if (ret) {
38113 dev_err(pdev->dev, "channel request irq fail!\n");
38114 return ret;
38115 @@ -970,7 +969,7 @@ static int mmp_pdma_probe(struct platfor
38116 /* all chan share one irq, demux inside */
38117 irq = platform_get_irq(op, 0);
38118 ret = devm_request_irq(pdev->dev, irq,
38119 - mmp_pdma_int_handler, IRQF_DISABLED, "pdma", pdev);
38120 + mmp_pdma_int_handler, 0, "pdma", pdev);
38121 if (ret)
38122 return ret;
38123 }
38124 --- a/drivers/dma/mmp_tdma.c
38125 +++ b/drivers/dma/mmp_tdma.c
38126 @@ -62,6 +62,11 @@
38127 #define TDCR_BURSTSZ_16B (0x3 << 6)
38128 #define TDCR_BURSTSZ_32B (0x6 << 6)
38129 #define TDCR_BURSTSZ_64B (0x7 << 6)
38130 +#define TDCR_BURSTSZ_SQU_1B (0x5 << 6)
38131 +#define TDCR_BURSTSZ_SQU_2B (0x6 << 6)
38132 +#define TDCR_BURSTSZ_SQU_4B (0x0 << 6)
38133 +#define TDCR_BURSTSZ_SQU_8B (0x1 << 6)
38134 +#define TDCR_BURSTSZ_SQU_16B (0x3 << 6)
38135 #define TDCR_BURSTSZ_SQU_32B (0x7 << 6)
38136 #define TDCR_BURSTSZ_128B (0x5 << 6)
38137 #define TDCR_DSTDIR_MSK (0x3 << 4) /* Dst Direction */
38138 @@ -228,8 +233,31 @@ static int mmp_tdma_config_chan(struct m
38139 return -EINVAL;
38140 }
38141 } else if (tdmac->type == PXA910_SQU) {
38142 - tdcr |= TDCR_BURSTSZ_SQU_32B;
38143 tdcr |= TDCR_SSPMOD;
38144 +
38145 + switch (tdmac->burst_sz) {
38146 + case 1:
38147 + tdcr |= TDCR_BURSTSZ_SQU_1B;
38148 + break;
38149 + case 2:
38150 + tdcr |= TDCR_BURSTSZ_SQU_2B;
38151 + break;
38152 + case 4:
38153 + tdcr |= TDCR_BURSTSZ_SQU_4B;
38154 + break;
38155 + case 8:
38156 + tdcr |= TDCR_BURSTSZ_SQU_8B;
38157 + break;
38158 + case 16:
38159 + tdcr |= TDCR_BURSTSZ_SQU_16B;
38160 + break;
38161 + case 32:
38162 + tdcr |= TDCR_BURSTSZ_SQU_32B;
38163 + break;
38164 + default:
38165 + dev_err(tdmac->dev, "mmp_tdma: unknown burst size.\n");
38166 + return -EINVAL;
38167 + }
38168 }
38169
38170 writel(tdcr, tdmac->reg_base + TDCR);
38171 @@ -324,7 +352,7 @@ static int mmp_tdma_alloc_chan_resources
38172
38173 if (tdmac->irq) {
38174 ret = devm_request_irq(tdmac->dev, tdmac->irq,
38175 - mmp_tdma_chan_handler, IRQF_DISABLED, "tdma", tdmac);
38176 + mmp_tdma_chan_handler, 0, "tdma", tdmac);
38177 if (ret)
38178 return ret;
38179 }
38180 @@ -559,7 +587,7 @@ static int mmp_tdma_probe(struct platfor
38181 if (irq_num != chan_num) {
38182 irq = platform_get_irq(pdev, 0);
38183 ret = devm_request_irq(&pdev->dev, irq,
38184 - mmp_tdma_int_handler, IRQF_DISABLED, "tdma", tdev);
38185 + mmp_tdma_int_handler, 0, "tdma", tdev);
38186 if (ret)
38187 return ret;
38188 }
38189 --- a/drivers/dma/pl330.c
38190 +++ b/drivers/dma/pl330.c
38191 @@ -2922,16 +2922,23 @@ pl330_probe(struct amba_device *adev, co
38192
38193 amba_set_drvdata(adev, pdmac);
38194
38195 - irq = adev->irq[0];
38196 - ret = request_irq(irq, pl330_irq_handler, 0,
38197 - dev_name(&adev->dev), pi);
38198 - if (ret)
38199 - return ret;
38200 + for (i = 0; i <= AMBA_NR_IRQS; i++) {
38201 + irq = adev->irq[i];
38202 + if (irq) {
38203 + ret = devm_request_irq(&adev->dev, irq,
38204 + pl330_irq_handler, 0,
38205 + dev_name(&adev->dev), pi);
38206 + if (ret)
38207 + return ret;
38208 + } else {
38209 + break;
38210 + }
38211 + }
38212
38213 pi->pcfg.periph_id = adev->periphid;
38214 ret = pl330_add(pi);
38215 if (ret)
38216 - goto probe_err1;
38217 + return ret;
38218
38219 INIT_LIST_HEAD(&pdmac->desc_pool);
38220 spin_lock_init(&pdmac->pool_lock);
38221 @@ -3044,8 +3051,6 @@ probe_err3:
38222 }
38223 probe_err2:
38224 pl330_del(pi);
38225 -probe_err1:
38226 - free_irq(irq, pi);
38227
38228 return ret;
38229 }
38230 @@ -3055,7 +3060,6 @@ static int pl330_remove(struct amba_devi
38231 struct dma_pl330_dmac *pdmac = amba_get_drvdata(adev);
38232 struct dma_pl330_chan *pch, *_p;
38233 struct pl330_info *pi;
38234 - int irq;
38235
38236 if (!pdmac)
38237 return 0;
38238 @@ -3082,9 +3086,6 @@ static int pl330_remove(struct amba_devi
38239
38240 pl330_del(pi);
38241
38242 - irq = adev->irq[0];
38243 - free_irq(irq, pi);
38244 -
38245 return 0;
38246 }
38247
38248 --- a/drivers/dma/ste_dma40.c
38249 +++ b/drivers/dma/ste_dma40.c
38250 @@ -14,6 +14,7 @@
38251 #include <linux/platform_device.h>
38252 #include <linux/clk.h>
38253 #include <linux/delay.h>
38254 +#include <linux/log2.h>
38255 #include <linux/pm.h>
38256 #include <linux/pm_runtime.h>
38257 #include <linux/err.h>
38258 @@ -2796,8 +2797,8 @@ static int d40_set_runtime_config(struct
38259 src_addr_width > DMA_SLAVE_BUSWIDTH_8_BYTES ||
38260 dst_addr_width <= DMA_SLAVE_BUSWIDTH_UNDEFINED ||
38261 dst_addr_width > DMA_SLAVE_BUSWIDTH_8_BYTES ||
38262 - ((src_addr_width > 1) && (src_addr_width & 1)) ||
38263 - ((dst_addr_width > 1) && (dst_addr_width & 1)))
38264 + !is_power_of_2(src_addr_width) ||
38265 + !is_power_of_2(dst_addr_width))
38266 return -EINVAL;
38267
38268 cfg->src_info.data_width = src_addr_width;
38269 --- /dev/null
38270 +++ b/drivers/extcon/extcon-gpio-usbvid.c
38271 @@ -0,0 +1,281 @@
38272 +/*
38273 + * Generic USB VBUS-ID pin detection driver
38274 + *
38275 + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
38276 + * This program is free software; you can redistribute it and/or modify
38277 + * it under the terms of the GNU General Public License as published by
38278 + * the Free Software Foundation; either version 2 of the License, or
38279 + * (at your option) any later version.
38280 + *
38281 + * Author: George Cherian <george.cherian@ti.com>
38282 + *
38283 + * Based on extcon-palmas.c
38284 + *
38285 + * Author: Kishon Vijay Abraham I <kishon@ti.com>
38286 + *
38287 + * This program is distributed in the hope that it will be useful,
38288 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
38289 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
38290 + * GNU General Public License for more details.
38291 + */
38292 +
38293 +#include <linux/err.h>
38294 +#include <linux/extcon.h>
38295 +#include <linux/gpio.h>
38296 +#include <linux/interrupt.h>
38297 +#include <linux/module.h>
38298 +#include <linux/of.h>
38299 +#include <linux/of_gpio.h>
38300 +#include <linux/of_platform.h>
38301 +#include <linux/platform_device.h>
38302 +
38303 +struct gpio_usbvid {
38304 + struct device *dev;
38305 +
38306 + struct extcon_dev edev;
38307 +
38308 + /* GPIO pin */
38309 + int id_gpio;
38310 + int vbus_gpio;
38311 +
38312 + int id_irq;
38313 + int vbus_irq;
38314 + int type;
38315 +};
38316 +
38317 +static const char *dra7xx_extcon_cable[] = {
38318 + [0] = "USB",
38319 + [1] = "USB-HOST",
38320 + NULL,
38321 +};
38322 +
38323 +static const int mutually_exclusive[] = {0x3, 0x0};
38324 +
38325 +/* Two types of support are provided.
38326 + * Systems which has
38327 + * 1) VBUS and ID pin connected via GPIO
38328 + * 2) only ID pin connected via GPIO
38329 + * For Case 1 both the gpios should be provided via DT
38330 + * Always the first GPIO in dt is considered ID pin GPIO
38331 + */
38332 +
38333 +enum {
38334 + UNKNOWN = 0,
38335 + ID_DETECT,
38336 + VBUS_ID_DETECT,
38337 +};
38338 +
38339 +#define ID_GND 0
38340 +#define ID_FLOAT 1
38341 +#define VBUS_OFF 0
38342 +#define VBUS_ON 1
38343 +
38344 +static irqreturn_t id_irq_handler(int irq, void *data)
38345 +{
38346 + struct gpio_usbvid *gpio_usbvid = (struct gpio_usbvid *)data;
38347 + int id_current;
38348 +
38349 + id_current = gpio_get_value_cansleep(gpio_usbvid->id_gpio);
38350 + if (id_current == ID_GND) {
38351 + if (gpio_usbvid->type == ID_DETECT)
38352 + extcon_set_cable_state(&gpio_usbvid->edev,
38353 + "USB", false);
38354 + extcon_set_cable_state(&gpio_usbvid->edev, "USB-HOST", true);
38355 + } else {
38356 + extcon_set_cable_state(&gpio_usbvid->edev, "USB-HOST", false);
38357 + if (gpio_usbvid->type == ID_DETECT)
38358 + extcon_set_cable_state(&gpio_usbvid->edev,
38359 + "USB", true);
38360 + }
38361 +
38362 + return IRQ_HANDLED;
38363 +}
38364 +
38365 +static irqreturn_t vbus_irq_handler(int irq, void *data)
38366 +{
38367 + struct gpio_usbvid *gpio_usbvid = (struct gpio_usbvid *)data;
38368 + int vbus_current;
38369 +
38370 + vbus_current = gpio_get_value_cansleep(gpio_usbvid->vbus_gpio);
38371 + if (vbus_current == VBUS_OFF)
38372 + extcon_set_cable_state(&gpio_usbvid->edev, "USB", false);
38373 + else
38374 + extcon_set_cable_state(&gpio_usbvid->edev, "USB", true);
38375 +
38376 + return IRQ_HANDLED;
38377 +}
38378 +
38379 +static void gpio_usbvid_set_initial_state(struct gpio_usbvid *gpio_usbvid)
38380 +{
38381 + int id_current, vbus_current;
38382 +
38383 + switch (gpio_usbvid->type) {
38384 + case ID_DETECT:
38385 + id_current = gpio_get_value_cansleep(gpio_usbvid->id_gpio);
38386 + if (!!id_current == ID_FLOAT) {
38387 + extcon_set_cable_state(&gpio_usbvid->edev,
38388 + "USB-HOST", false);
38389 + extcon_set_cable_state(&gpio_usbvid->edev,
38390 + "USB", true);
38391 + } else {
38392 + extcon_set_cable_state(&gpio_usbvid->edev,
38393 + "USB", false);
38394 + extcon_set_cable_state(&gpio_usbvid->edev,
38395 + "USB-HOST", true);
38396 + }
38397 + break;
38398 +
38399 + case VBUS_ID_DETECT:
38400 + id_current = gpio_get_value_cansleep(gpio_usbvid->id_gpio);
38401 + if (!!id_current == ID_FLOAT)
38402 + extcon_set_cable_state(&gpio_usbvid->edev,
38403 + "USB-HOST", false);
38404 + else
38405 + extcon_set_cable_state(&gpio_usbvid->edev,
38406 + "USB-HOST", true);
38407 +
38408 + vbus_current = gpio_get_value_cansleep(gpio_usbvid->vbus_gpio);
38409 + if (!!vbus_current == VBUS_ON)
38410 + extcon_set_cable_state(&gpio_usbvid->edev,
38411 + "USB", true);
38412 + else
38413 + extcon_set_cable_state(&gpio_usbvid->edev,
38414 + "USB", false);
38415 + break;
38416 +
38417 + default:
38418 + dev_err(gpio_usbvid->dev, "Unknown VBUS-ID type\n");
38419 + }
38420 +}
38421 +
38422 +static int gpio_usbvid_request_irq(struct gpio_usbvid *gpio_usbvid)
38423 +{
38424 + int ret;
38425 +
38426 + ret = devm_request_threaded_irq(gpio_usbvid->dev, gpio_usbvid->id_irq,
38427 + NULL, id_irq_handler,
38428 + IRQF_ONESHOT | IRQF_TRIGGER_FALLING,
38429 + dev_name(gpio_usbvid->dev),
38430 + (void *) gpio_usbvid);
38431 + if (ret) {
38432 + dev_err(gpio_usbvid->dev, "failed to request id irq #%d\n",
38433 + gpio_usbvid->id_irq);
38434 + return ret;
38435 + }
38436 + if (gpio_usbvid->type == VBUS_ID_DETECT) {
38437 + ret = devm_request_threaded_irq(gpio_usbvid->dev,
38438 + gpio_usbvid->vbus_irq, NULL,
38439 + vbus_irq_handler,
38440 + IRQF_ONESHOT | IRQF_TRIGGER_FALLING,
38441 + dev_name(gpio_usbvid->dev),
38442 + (void *) gpio_usbvid);
38443 + if (ret)
38444 + dev_err(gpio_usbvid->dev, "failed to request vbus irq #%d\n",
38445 + gpio_usbvid->vbus_irq);
38446 + }
38447 +
38448 + return ret;
38449 +}
38450 +
38451 +static int gpio_usbvid_probe(struct platform_device *pdev)
38452 +{
38453 + struct device_node *node = pdev->dev.of_node;
38454 + struct gpio_usbvid *gpio_usbvid;
38455 + int ret, gpio;
38456 +
38457 + gpio_usbvid = devm_kzalloc(&pdev->dev, sizeof(*gpio_usbvid),
38458 + GFP_KERNEL);
38459 + if (!gpio_usbvid)
38460 + return -ENOMEM;
38461 +
38462 + gpio_usbvid->dev = &pdev->dev;
38463 +
38464 + platform_set_drvdata(pdev, gpio_usbvid);
38465 +
38466 + //gpio_usbvid->edev.name = dev_name(&pdev->dev);
38467 + gpio_usbvid->edev.supported_cable = dra7xx_extcon_cable;
38468 + gpio_usbvid->edev.mutually_exclusive = mutually_exclusive;
38469 +
38470 + if (of_device_is_compatible(node, "ti,gpio-usb-id"))
38471 + gpio_usbvid->type = ID_DETECT;
38472 +
38473 + gpio = of_get_gpio(node, 0);
38474 + if (gpio_is_valid(gpio)) {
38475 + gpio_usbvid->id_gpio = gpio;
38476 + ret = devm_gpio_request(&pdev->dev, gpio_usbvid->id_gpio,
38477 + "id_gpio");
38478 + if (ret)
38479 + return ret;
38480 +
38481 + gpio_usbvid->id_irq = gpio_to_irq(gpio_usbvid->id_gpio);
38482 + } else {
38483 + dev_err(&pdev->dev, "failed to get id gpio\n");
38484 + return -EPROBE_DEFER;
38485 + }
38486 +
38487 + if (of_device_is_compatible(node, "ti,gpio-usb-vid")) {
38488 + gpio_usbvid->type = VBUS_ID_DETECT;
38489 + gpio = of_get_gpio(node, 1);
38490 + if (gpio_is_valid(gpio)) {
38491 + gpio_usbvid->vbus_gpio = gpio;
38492 + ret = devm_gpio_request(&pdev->dev,
38493 + gpio_usbvid->vbus_gpio,
38494 + "vbus_gpio");
38495 + if (ret)
38496 + return ret;
38497 +
38498 + gpio_usbvid->vbus_irq =
38499 + gpio_to_irq(gpio_usbvid->vbus_gpio);
38500 + } else {
38501 + dev_err(&pdev->dev, "failed to get vbus gpio\n");
38502 + return -ENODEV;
38503 + }
38504 + }
38505 +
38506 + ret = gpio_usbvid_request_irq(gpio_usbvid);
38507 + if (ret)
38508 + return ret;
38509 +
38510 + ret = extcon_dev_register(&gpio_usbvid->edev, gpio_usbvid->dev);
38511 + if (ret) {
38512 + dev_err(&pdev->dev, "failed to register extcon device\n");
38513 + return ret;
38514 + }
38515 +
38516 + gpio_usbvid_set_initial_state(gpio_usbvid);
38517 +
38518 + return 0;
38519 +
38520 +}
38521 +
38522 +static int gpio_usbvid_remove(struct platform_device *pdev)
38523 +{
38524 + struct gpio_usbvid *gpio_usbvid = platform_get_drvdata(pdev);
38525 +
38526 + extcon_dev_unregister(&gpio_usbvid->edev);
38527 + return 0;
38528 +}
38529 +
38530 +static struct of_device_id of_gpio_usbvid_match_tbl[] = {
38531 + { .compatible = "ti,gpio-usb-vid", },
38532 + { .compatible = "ti,gpio-usb-id", },
38533 + { /* end */ }
38534 +};
38535 +
38536 +static struct platform_driver gpio_usbvid_driver = {
38537 + .probe = gpio_usbvid_probe,
38538 + .remove = gpio_usbvid_remove,
38539 + .driver = {
38540 + .name = "gpio-usbvid",
38541 + .of_match_table = of_gpio_usbvid_match_tbl,
38542 + .owner = THIS_MODULE,
38543 + },
38544 +};
38545 +
38546 +module_platform_driver(gpio_usbvid_driver);
38547 +
38548 +MODULE_ALIAS("platform:gpio-usbvid");
38549 +MODULE_AUTHOR("George Cherian <george.cherian@ti.com>");
38550 +MODULE_DESCRIPTION("GPIO based USB Connector driver");
38551 +MODULE_LICENSE("GPL");
38552 +MODULE_DEVICE_TABLE(of, of_gpio_usbvid_match_tbl);
38553 --- a/drivers/extcon/extcon-palmas.c
38554 +++ b/drivers/extcon/extcon-palmas.c
38555 @@ -78,20 +78,24 @@ static irqreturn_t palmas_vbus_irq_handl
38556
38557 static irqreturn_t palmas_id_irq_handler(int irq, void *_palmas_usb)
38558 {
38559 - unsigned int set;
38560 + unsigned int set, id_src;
38561 struct palmas_usb *palmas_usb = _palmas_usb;
38562
38563 palmas_read(palmas_usb->palmas, PALMAS_USB_OTG_BASE,
38564 PALMAS_USB_ID_INT_LATCH_SET, &set);
38565 + palmas_read(palmas_usb->palmas, PALMAS_USB_OTG_BASE,
38566 + PALMAS_USB_ID_INT_SRC, &id_src);
38567
38568 - if (set & PALMAS_USB_ID_INT_SRC_ID_GND) {
38569 + if ((set & PALMAS_USB_ID_INT_SRC_ID_GND) &&
38570 + (id_src & PALMAS_USB_ID_INT_SRC_ID_GND)) {
38571 palmas_write(palmas_usb->palmas, PALMAS_USB_OTG_BASE,
38572 PALMAS_USB_ID_INT_LATCH_CLR,
38573 PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND);
38574 palmas_usb->linkstat = PALMAS_USB_STATE_ID;
38575 extcon_set_cable_state(&palmas_usb->edev, "USB-HOST", true);
38576 dev_info(palmas_usb->dev, "USB-HOST cable is attached\n");
38577 - } else if (set & PALMAS_USB_ID_INT_SRC_ID_FLOAT) {
38578 + } else if ((set & PALMAS_USB_ID_INT_SRC_ID_FLOAT) &&
38579 + (id_src & PALMAS_USB_ID_INT_SRC_ID_FLOAT)) {
38580 palmas_write(palmas_usb->palmas, PALMAS_USB_OTG_BASE,
38581 PALMAS_USB_ID_INT_LATCH_CLR,
38582 PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT);
38583 @@ -103,6 +107,11 @@ static irqreturn_t palmas_id_irq_handler
38584 palmas_usb->linkstat = PALMAS_USB_STATE_DISCONNECT;
38585 extcon_set_cable_state(&palmas_usb->edev, "USB-HOST", false);
38586 dev_info(palmas_usb->dev, "USB-HOST cable is detached\n");
38587 + } else if ((palmas_usb->linkstat == PALMAS_USB_STATE_DISCONNECT) &&
38588 + (id_src & PALMAS_USB_ID_INT_SRC_ID_GND)) {
38589 + palmas_usb->linkstat = PALMAS_USB_STATE_ID;
38590 + extcon_set_cable_state(&palmas_usb->edev, "USB-HOST", true);
38591 + dev_info(palmas_usb->dev, " USB-HOST cable is attached\n");
38592 }
38593
38594 return IRQ_HANDLED;
38595 @@ -268,6 +277,7 @@ static const struct dev_pm_ops palmas_pm
38596
38597 static struct of_device_id of_palmas_match_tbl[] = {
38598 { .compatible = "ti,palmas-usb", },
38599 + { .compatible = "ti,palmas-usb-vid", },
38600 { .compatible = "ti,twl6035-usb", },
38601 { /* end */ }
38602 };
38603 --- a/drivers/extcon/Kconfig
38604 +++ b/drivers/extcon/Kconfig
38605 @@ -64,4 +64,9 @@ config EXTCON_PALMAS
38606 Say Y here to enable support for USB peripheral and USB host
38607 detection by palmas usb.
38608
38609 +config EXTCON_GPIO_USBVID
38610 + tristate "Generic USB VBUS/ID detection using GPIO EXTCON support"
38611 + help
38612 + Say Y here to enable support for USB VBUS/ID deetction by GPIO.
38613 +
38614 endif # MULTISTATE_SWITCH
38615 --- a/drivers/extcon/Makefile
38616 +++ b/drivers/extcon/Makefile
38617 @@ -11,3 +11,4 @@ obj-$(CONFIG_EXTCON_MAX77693) += extcon-
38618 obj-$(CONFIG_EXTCON_MAX8997) += extcon-max8997.o
38619 obj-$(CONFIG_EXTCON_ARIZONA) += extcon-arizona.o
38620 obj-$(CONFIG_EXTCON_PALMAS) += extcon-palmas.o
38621 +obj-$(CONFIG_EXTCON_GPIO_USBVID) += extcon-gpio-usbvid.o
38622 --- a/drivers/gpio/gpio-pcf857x.c
38623 +++ b/drivers/gpio/gpio-pcf857x.c
38624 @@ -26,9 +26,10 @@
38625 #include <linux/irqdomain.h>
38626 #include <linux/kernel.h>
38627 #include <linux/module.h>
38628 +#include <linux/of.h>
38629 +#include <linux/of_device.h>
38630 #include <linux/slab.h>
38631 #include <linux/spinlock.h>
38632 -#include <linux/workqueue.h>
38633
38634
38635 static const struct i2c_device_id pcf857x_id[] = {
38636 @@ -50,6 +51,27 @@ static const struct i2c_device_id pcf857
38637 };
38638 MODULE_DEVICE_TABLE(i2c, pcf857x_id);
38639
38640 +#ifdef CONFIG_OF
38641 +static const struct of_device_id pcf857x_of_table[] = {
38642 + { .compatible = "nxp,pcf8574" },
38643 + { .compatible = "nxp,pcf8574a" },
38644 + { .compatible = "nxp,pca8574" },
38645 + { .compatible = "nxp,pca9670" },
38646 + { .compatible = "nxp,pca9672" },
38647 + { .compatible = "nxp,pca9674" },
38648 + { .compatible = "nxp,pcf8575" },
38649 + { .compatible = "nxp,pca8575" },
38650 + { .compatible = "nxp,pca9671" },
38651 + { .compatible = "nxp,pca9673" },
38652 + { .compatible = "nxp,pca9675" },
38653 + { .compatible = "maxim,max7328" },
38654 + { .compatible = "maxim,max7329" },
38655 + { .compatible = "ti,tca9554" },
38656 + { }
38657 +};
38658 +MODULE_DEVICE_TABLE(of, pcf857x_of_table);
38659 +#endif
38660 +
38661 /*
38662 * The pcf857x, pca857x, and pca967x chips only expose one read and one
38663 * write register. Writing a "one" bit (to match the reset state) lets
38664 @@ -66,12 +88,11 @@ struct pcf857x {
38665 struct gpio_chip chip;
38666 struct i2c_client *client;
38667 struct mutex lock; /* protect 'out' */
38668 - struct work_struct work; /* irq demux work */
38669 struct irq_domain *irq_domain; /* for irq demux */
38670 spinlock_t slock; /* protect irq demux */
38671 unsigned out; /* software latch */
38672 unsigned status; /* current status */
38673 - int irq; /* real irq number */
38674 + unsigned irq_mapped; /* mapped gpio irqs */
38675
38676 int (*write)(struct i2c_client *client, unsigned data);
38677 int (*read)(struct i2c_client *client);
38678 @@ -164,48 +185,54 @@ static void pcf857x_set(struct gpio_chip
38679 static int pcf857x_to_irq(struct gpio_chip *chip, unsigned offset)
38680 {
38681 struct pcf857x *gpio = container_of(chip, struct pcf857x, chip);
38682 + int ret;
38683
38684 - return irq_create_mapping(gpio->irq_domain, offset);
38685 + ret = irq_create_mapping(gpio->irq_domain, offset);
38686 + if (ret > 0)
38687 + gpio->irq_mapped |= (1 << offset);
38688 +
38689 + return ret;
38690 }
38691
38692 -static void pcf857x_irq_demux_work(struct work_struct *work)
38693 +static irqreturn_t pcf857x_irq(int irq, void *data)
38694 {
38695 - struct pcf857x *gpio = container_of(work,
38696 - struct pcf857x,
38697 - work);
38698 + struct pcf857x *gpio = data;
38699 unsigned long change, i, status, flags;
38700
38701 status = gpio->read(gpio->client);
38702
38703 spin_lock_irqsave(&gpio->slock, flags);
38704
38705 - change = gpio->status ^ status;
38706 + /*
38707 + * call the interrupt handler iff gpio is used as
38708 + * interrupt source, just to avoid bad irqs
38709 + */
38710 +
38711 + change = ((gpio->status ^ status) & gpio->irq_mapped);
38712 for_each_set_bit(i, &change, gpio->chip.ngpio)
38713 generic_handle_irq(irq_find_mapping(gpio->irq_domain, i));
38714 gpio->status = status;
38715
38716 spin_unlock_irqrestore(&gpio->slock, flags);
38717 -}
38718 -
38719 -static irqreturn_t pcf857x_irq_demux(int irq, void *data)
38720 -{
38721 - struct pcf857x *gpio = data;
38722 -
38723 - /*
38724 - * pcf857x can't read/write data here,
38725 - * since i2c data access might go to sleep.
38726 - */
38727 - schedule_work(&gpio->work);
38728
38729 return IRQ_HANDLED;
38730 }
38731
38732 -static int pcf857x_irq_domain_map(struct irq_domain *domain, unsigned int virq,
38733 +static int pcf857x_irq_domain_map(struct irq_domain *domain, unsigned int irq,
38734 irq_hw_number_t hw)
38735 {
38736 - irq_set_chip_and_handler(virq,
38737 + struct pcf857x *gpio = domain->host_data;
38738 +
38739 + irq_set_chip_and_handler(irq,
38740 &dummy_irq_chip,
38741 handle_level_irq);
38742 +#ifdef CONFIG_ARM
38743 + set_irq_flags(irq, IRQF_VALID);
38744 +#else
38745 + irq_set_noprobe(irq);
38746 +#endif
38747 + gpio->irq_mapped |= (1 << hw);
38748 +
38749 return 0;
38750 }
38751
38752 @@ -218,8 +245,6 @@ static void pcf857x_irq_domain_cleanup(s
38753 if (gpio->irq_domain)
38754 irq_domain_remove(gpio->irq_domain);
38755
38756 - if (gpio->irq)
38757 - free_irq(gpio->irq, gpio);
38758 }
38759
38760 static int pcf857x_irq_domain_init(struct pcf857x *gpio,
38761 @@ -230,20 +255,21 @@ static int pcf857x_irq_domain_init(struc
38762 gpio->irq_domain = irq_domain_add_linear(client->dev.of_node,
38763 gpio->chip.ngpio,
38764 &pcf857x_irq_domain_ops,
38765 - NULL);
38766 + gpio);
38767 if (!gpio->irq_domain)
38768 goto fail;
38769
38770 /* enable real irq */
38771 - status = request_irq(client->irq, pcf857x_irq_demux, 0,
38772 - dev_name(&client->dev), gpio);
38773 + status = devm_request_threaded_irq(&client->dev, client->irq,
38774 + NULL, pcf857x_irq, IRQF_ONESHOT |
38775 + IRQF_TRIGGER_FALLING,
38776 + dev_name(&client->dev), gpio);
38777 +
38778 if (status)
38779 goto fail;
38780
38781 /* enable gpio_to_irq() */
38782 - INIT_WORK(&gpio->work, pcf857x_irq_demux_work);
38783 gpio->chip.to_irq = pcf857x_to_irq;
38784 - gpio->irq = client->irq;
38785
38786 return 0;
38787
38788 @@ -257,14 +283,18 @@ fail:
38789 static int pcf857x_probe(struct i2c_client *client,
38790 const struct i2c_device_id *id)
38791 {
38792 - struct pcf857x_platform_data *pdata;
38793 + struct pcf857x_platform_data *pdata = dev_get_platdata(&client->dev);
38794 + struct device_node *np = client->dev.of_node;
38795 struct pcf857x *gpio;
38796 + unsigned int n_latch = 0;
38797 int status;
38798
38799 - pdata = dev_get_platdata(&client->dev);
38800 - if (!pdata) {
38801 + if (IS_ENABLED(CONFIG_OF) && np)
38802 + of_property_read_u32(np, "lines-initial-states", &n_latch);
38803 + else if (pdata)
38804 + n_latch = pdata->n_latch;
38805 + else
38806 dev_dbg(&client->dev, "no platform data\n");
38807 - }
38808
38809 /* Allocate, initialize, and register this gpio_chip. */
38810 gpio = devm_kzalloc(&client->dev, sizeof(*gpio), GFP_KERNEL);
38811 @@ -357,11 +387,11 @@ static int pcf857x_probe(struct i2c_clie
38812 * may cause transient glitching since it can't know the last value
38813 * written (some pins may need to be driven low).
38814 *
38815 - * Using pdata->n_latch avoids that trouble. When left initialized
38816 - * to zero, our software copy of the "latch" then matches the chip's
38817 - * all-ones reset state. Otherwise it flags pins to be driven low.
38818 + * Using n_latch avoids that trouble. When left initialized to zero,
38819 + * our software copy of the "latch" then matches the chip's all-ones
38820 + * reset state. Otherwise it flags pins to be driven low.
38821 */
38822 - gpio->out = pdata ? ~pdata->n_latch : ~0;
38823 + gpio->out = ~n_latch;
38824 gpio->status = gpio->out;
38825
38826 status = gpiochip_add(&gpio->chip);
38827 @@ -423,6 +453,7 @@ static struct i2c_driver pcf857x_driver
38828 .driver = {
38829 .name = "pcf857x",
38830 .owner = THIS_MODULE,
38831 + .of_match_table = of_match_ptr(pcf857x_of_table),
38832 },
38833 .probe = pcf857x_probe,
38834 .remove = pcf857x_remove,
38835 --- a/drivers/gpu/drm/omapdrm/omap_crtc.c
38836 +++ b/drivers/gpu/drm/omapdrm/omap_crtc.c
38837 @@ -411,7 +411,7 @@ static void omap_crtc_error_irq(struct o
38838 struct drm_crtc *crtc = &omap_crtc->base;
38839 DRM_ERROR("%s: errors: %08x\n", omap_crtc->name, irqstatus);
38840 /* avoid getting in a flood, unregister the irq until next vblank */
38841 - omap_irq_unregister(crtc->dev, &omap_crtc->error_irq);
38842 + __omap_irq_unregister(crtc->dev, &omap_crtc->error_irq);
38843 }
38844
38845 static void omap_crtc_apply_irq(struct omap_drm_irq *irq, uint32_t irqstatus)
38846 @@ -421,13 +421,13 @@ static void omap_crtc_apply_irq(struct o
38847 struct drm_crtc *crtc = &omap_crtc->base;
38848
38849 if (!omap_crtc->error_irq.registered)
38850 - omap_irq_register(crtc->dev, &omap_crtc->error_irq);
38851 + __omap_irq_register(crtc->dev, &omap_crtc->error_irq);
38852
38853 if (!dispc_mgr_go_busy(omap_crtc->channel)) {
38854 struct omap_drm_private *priv =
38855 crtc->dev->dev_private;
38856 DBG("%s: apply done", omap_crtc->name);
38857 - omap_irq_unregister(crtc->dev, &omap_crtc->apply_irq);
38858 + __omap_irq_unregister(crtc->dev, &omap_crtc->apply_irq);
38859 queue_work(priv->wq, &omap_crtc->apply_work);
38860 }
38861 }
38862 @@ -623,6 +623,11 @@ void omap_crtc_pre_init(void)
38863 dss_install_mgr_ops(&mgr_ops);
38864 }
38865
38866 +void omap_crtc_pre_uninit(void)
38867 +{
38868 + dss_uninstall_mgr_ops();
38869 +}
38870 +
38871 /* initialize crtc */
38872 struct drm_crtc *omap_crtc_init(struct drm_device *dev,
38873 struct drm_plane *plane, enum omap_channel channel, int id)
38874 --- a/drivers/gpu/drm/omapdrm/omap_dmm_tiler.c
38875 +++ b/drivers/gpu/drm/omapdrm/omap_dmm_tiler.c
38876 @@ -968,12 +968,23 @@ static const struct dev_pm_ops omap_dmm_
38877 };
38878 #endif
38879
38880 +#if defined(CONFIG_OF)
38881 +static const struct of_device_id dmm_of_match[] = {
38882 + { .compatible = "ti,omap4-dmm", },
38883 + { .compatible = "ti,omap5-dmm", },
38884 + {},
38885 +};
38886 +#else
38887 +#define dmm_of_match NULL
38888 +#endif
38889 +
38890 struct platform_driver omap_dmm_driver = {
38891 .probe = omap_dmm_probe,
38892 .remove = omap_dmm_remove,
38893 .driver = {
38894 .owner = THIS_MODULE,
38895 .name = DMM_DRIVER_NAME,
38896 + .of_match_table = dmm_of_match,
38897 #ifdef CONFIG_PM
38898 .pm = &omap_dmm_pm_ops,
38899 #endif
38900 --- a/drivers/gpu/drm/omapdrm/omap_drv.c
38901 +++ b/drivers/gpu/drm/omapdrm/omap_drv.c
38902 @@ -86,6 +86,47 @@ static bool channel_used(struct drm_devi
38903
38904 return false;
38905 }
38906 +static void omap_disconnect_dssdevs(void)
38907 +{
38908 + struct omap_dss_device *dssdev = NULL;
38909 +
38910 + for_each_dss_dev(dssdev)
38911 + dssdev->driver->disconnect(dssdev);
38912 +}
38913 +
38914 +static int omap_connect_dssdevs(void)
38915 +{
38916 + int r;
38917 + struct omap_dss_device *dssdev = NULL;
38918 + bool no_displays = true;
38919 +
38920 + for_each_dss_dev(dssdev) {
38921 + r = dssdev->driver->connect(dssdev);
38922 + if (r == -EPROBE_DEFER) {
38923 + omap_dss_put_device(dssdev);
38924 + goto cleanup;
38925 + } else if (r) {
38926 + dev_warn(dssdev->dev, "could not connect display: %s\n",
38927 + dssdev->name);
38928 + } else {
38929 + no_displays = false;
38930 + }
38931 + }
38932 +
38933 + if (no_displays)
38934 + return -EPROBE_DEFER;
38935 +
38936 + return 0;
38937 +
38938 +cleanup:
38939 + /*
38940 + * if we are deferring probe, we disconnect the devices we previously
38941 + * connected
38942 + */
38943 + omap_disconnect_dssdevs();
38944 +
38945 + return r;
38946 +}
38947
38948 static int omap_modeset_init(struct drm_device *dev)
38949 {
38950 @@ -95,9 +136,6 @@ static int omap_modeset_init(struct drm_
38951 int num_mgrs = dss_feat_get_num_mgrs();
38952 int num_crtcs;
38953 int i, id = 0;
38954 - int r;
38955 -
38956 - omap_crtc_pre_init();
38957
38958 drm_mode_config_init(dev);
38959
38960 @@ -119,26 +157,8 @@ static int omap_modeset_init(struct drm_
38961 enum omap_channel channel;
38962 struct omap_overlay_manager *mgr;
38963
38964 - if (!dssdev->driver) {
38965 - dev_warn(dev->dev, "%s has no driver.. skipping it\n",
38966 - dssdev->name);
38967 - continue;
38968 - }
38969 -
38970 - if (!(dssdev->driver->get_timings ||
38971 - dssdev->driver->read_edid)) {
38972 - dev_warn(dev->dev, "%s driver does not support "
38973 - "get_timings or read_edid.. skipping it!\n",
38974 - dssdev->name);
38975 - continue;
38976 - }
38977 -
38978 - r = dssdev->driver->connect(dssdev);
38979 - if (r) {
38980 - dev_err(dev->dev, "could not connect display: %s\n",
38981 - dssdev->name);
38982 + if (!omapdss_device_is_connected(dssdev))
38983 continue;
38984 - }
38985
38986 encoder = omap_encoder_init(dev, dssdev);
38987
38988 @@ -656,9 +676,19 @@ static void pdev_shutdown(struct platfor
38989
38990 static int pdev_probe(struct platform_device *device)
38991 {
38992 + int r;
38993 +
38994 if (omapdss_is_initialized() == false)
38995 return -EPROBE_DEFER;
38996
38997 + omap_crtc_pre_init();
38998 +
38999 + r = omap_connect_dssdevs();
39000 + if (r) {
39001 + omap_crtc_pre_uninit();
39002 + return r;
39003 + }
39004 +
39005 DBG("%s", device->name);
39006 return drm_platform_init(&omap_drm_driver, device);
39007 }
39008 @@ -668,6 +698,8 @@ static int pdev_remove(struct platform_d
39009 DBG("");
39010 drm_platform_exit(&omap_drm_driver, device);
39011
39012 + omap_disconnect_dssdevs();
39013 +
39014 platform_driver_unregister(&omap_dmm_driver);
39015 return 0;
39016 }
39017 --- a/drivers/gpu/drm/omapdrm/omap_drv.h
39018 +++ b/drivers/gpu/drm/omapdrm/omap_drv.h
39019 @@ -145,6 +145,8 @@ irqreturn_t omap_irq_handler(DRM_IRQ_ARG
39020 void omap_irq_preinstall(struct drm_device *dev);
39021 int omap_irq_postinstall(struct drm_device *dev);
39022 void omap_irq_uninstall(struct drm_device *dev);
39023 +void __omap_irq_register(struct drm_device *dev, struct omap_drm_irq *irq);
39024 +void __omap_irq_unregister(struct drm_device *dev, struct omap_drm_irq *irq);
39025 void omap_irq_register(struct drm_device *dev, struct omap_drm_irq *irq);
39026 void omap_irq_unregister(struct drm_device *dev, struct omap_drm_irq *irq);
39027 int omap_drm_irq_uninstall(struct drm_device *dev);
39028 @@ -158,6 +160,7 @@ enum omap_channel omap_crtc_channel(stru
39029 int omap_crtc_apply(struct drm_crtc *crtc,
39030 struct omap_drm_apply *apply);
39031 void omap_crtc_pre_init(void);
39032 +void omap_crtc_pre_uninit(void);
39033 struct drm_crtc *omap_crtc_init(struct drm_device *dev,
39034 struct drm_plane *plane, enum omap_channel channel, int id);
39035
39036 --- a/drivers/gpu/drm/omapdrm/omap_encoder.c
39037 +++ b/drivers/gpu/drm/omapdrm/omap_encoder.c
39038 @@ -51,6 +51,10 @@ struct omap_dss_device *omap_encoder_get
39039 static void omap_encoder_destroy(struct drm_encoder *encoder)
39040 {
39041 struct omap_encoder *omap_encoder = to_omap_encoder(encoder);
39042 + struct omap_dss_device *dssdev = omap_encoder->dssdev;
39043 +
39044 + dssdev->driver->disable(dssdev);
39045 +
39046 drm_encoder_cleanup(encoder);
39047 kfree(omap_encoder);
39048 }
39049 --- a/drivers/gpu/drm/omapdrm/omap_irq.c
39050 +++ b/drivers/gpu/drm/omapdrm/omap_irq.c
39051 @@ -45,12 +45,11 @@ static void omap_irq_update(struct drm_d
39052 dispc_read_irqenable(); /* flush posted write */
39053 }
39054
39055 -void omap_irq_register(struct drm_device *dev, struct omap_drm_irq *irq)
39056 +void __omap_irq_register(struct drm_device *dev, struct omap_drm_irq *irq)
39057 {
39058 struct omap_drm_private *priv = dev->dev_private;
39059 unsigned long flags;
39060
39061 - dispc_runtime_get();
39062 spin_lock_irqsave(&list_lock, flags);
39063
39064 if (!WARN_ON(irq->registered)) {
39065 @@ -60,14 +59,21 @@ void omap_irq_register(struct drm_device
39066 }
39067
39068 spin_unlock_irqrestore(&list_lock, flags);
39069 +}
39070 +
39071 +void omap_irq_register(struct drm_device *dev, struct omap_drm_irq *irq)
39072 +{
39073 + dispc_runtime_get();
39074 +
39075 + __omap_irq_register(dev, irq);
39076 +
39077 dispc_runtime_put();
39078 }
39079
39080 -void omap_irq_unregister(struct drm_device *dev, struct omap_drm_irq *irq)
39081 +void __omap_irq_unregister(struct drm_device *dev, struct omap_drm_irq *irq)
39082 {
39083 unsigned long flags;
39084
39085 - dispc_runtime_get();
39086 spin_lock_irqsave(&list_lock, flags);
39087
39088 if (!WARN_ON(!irq->registered)) {
39089 @@ -77,6 +83,14 @@ void omap_irq_unregister(struct drm_devi
39090 }
39091
39092 spin_unlock_irqrestore(&list_lock, flags);
39093 +}
39094 +
39095 +void omap_irq_unregister(struct drm_device *dev, struct omap_drm_irq *irq)
39096 +{
39097 + dispc_runtime_get();
39098 +
39099 + __omap_irq_unregister(dev, irq);
39100 +
39101 dispc_runtime_put();
39102 }
39103
39104 --- a/drivers/gpu/drm/omapdrm/omap_plane.c
39105 +++ b/drivers/gpu/drm/omapdrm/omap_plane.c
39106 @@ -122,6 +122,7 @@ static void omap_plane_pre_apply(struct
39107 enum omap_channel channel;
39108 bool enabled = omap_plane->enabled && crtc;
39109 bool ilace, replication;
39110 + u32 low, high;
39111 int ret;
39112
39113 DBG("%s, enabled=%d", omap_plane->name, enabled);
39114 @@ -149,6 +150,10 @@ static void omap_plane_pre_apply(struct
39115 ilace = false;
39116 replication = false;
39117
39118 + dispc_ovl_compute_fifo_thresholds(omap_plane->id, &low, &high,
39119 + false, false);
39120 + dispc_ovl_set_fifo_threshold(omap_plane->id, low, high);
39121 +
39122 /* and finally, update omapdss: */
39123 ret = dispc_ovl_setup(omap_plane->id, info,
39124 replication, omap_crtc_timings(crtc), false);
39125 --- a/drivers/gpu/drm/tilcdc/tilcdc_drv.h
39126 +++ b/drivers/gpu/drm/tilcdc/tilcdc_drv.h
39127 @@ -43,7 +43,7 @@
39128 * with optimized DDR & EMIF settings tweaked 1920x1080@24 appears to
39129 * be supportable
39130 */
39131 -#define TILCDC_DEFAULT_MAX_BANDWIDTH (1280*1024*60)
39132 +#define TILCDC_DEFAULT_MAX_BANDWIDTH (1680*1050*60)
39133
39134
39135 struct tilcdc_drm_private {
39136 --- a/drivers/iio/adc/ti_am335x_adc.c
39137 +++ b/drivers/iio/adc/ti_am335x_adc.c
39138 @@ -154,7 +154,7 @@ static int tiadc_read_raw(struct iio_dev
39139 while (tiadc_readl(adc_dev, REG_ADCFSM) & SEQ_STATUS) {
39140 if (time_after(jiffies, timeout))
39141 return -EAGAIN;
39142 - }
39143 + }
39144 map_val = chan->channel + TOTAL_CHANNELS;
39145
39146 /*
39147 --- a/drivers/input/touchscreen/atmel_mxt_ts.c
39148 +++ b/drivers/input/touchscreen/atmel_mxt_ts.c
39149 @@ -20,6 +20,8 @@
39150 #include <linux/input/mt.h>
39151 #include <linux/interrupt.h>
39152 #include <linux/slab.h>
39153 +#include <linux/of.h>
39154 +#include <linux/of_device.h>
39155
39156 /* Version */
39157 #define MXT_VER_20 20
39158 @@ -335,6 +337,105 @@ static void mxt_dump_message(struct devi
39159 message->reportid, 7, message->message);
39160 }
39161
39162 +static int mxt_of_get_platform_info(struct i2c_client *client,
39163 + struct mxt_platform_data *pdata)
39164 +
39165 +{
39166 + int size, index = 0;
39167 + u32 val;
39168 + const __be32 *config_be;
39169 + u8 *config;
39170 + const char *pname;
39171 + struct device_node *node = client->dev.of_node;
39172 +
39173 + config_be = of_get_property(node, "atmel,config", &size);
39174 + if (config_be && size) {
39175 + size /= sizeof(*config_be);
39176 + config = devm_kzalloc(&client->dev, size, GFP_KERNEL);
39177 + if (!config) {
39178 + dev_err(&client->dev, "Failed to allocate memory\n");
39179 + return -ENOMEM;
39180 + }
39181 +
39182 + pdata->config = config;
39183 + pdata->config_length = size;
39184 +
39185 + while (index < size) {
39186 + config[index] = be32_to_cpup(config_be + index) & 0xFF;
39187 + index++;
39188 + }
39189 + } else {
39190 + dev_dbg(&client->dev, "%s:no config data specified\n",
39191 + __func__);
39192 + }
39193 +
39194 + pname = "atmel,x_line";
39195 + if (of_property_read_u32(node, pname, &pdata->x_line)) {
39196 + dev_err(&client->dev, "%s: Failed to read %s property\n",
39197 + __func__, pname);
39198 + return -EINVAL;
39199 + }
39200 +
39201 + pname = "atmel,y_line";
39202 + if (of_property_read_u32(node, pname, &pdata->y_line)) {
39203 + dev_err(&client->dev, "%s: Failed to read %s property\n",
39204 + __func__, pname);
39205 + return -EINVAL;
39206 + }
39207 +
39208 + pname = "atmel,x_size";
39209 + if (of_property_read_u32(node, pname, &pdata->x_size)) {
39210 + dev_err(&client->dev, "%s: Failed to read %s property\n",
39211 + __func__, pname);
39212 + return -EINVAL;
39213 + }
39214 +
39215 + pname = "atmel,y_size";
39216 + if (of_property_read_u32(node, pname, &pdata->y_size)) {
39217 + dev_err(&client->dev, "%s: Failed to read %s property\n",
39218 + __func__, pname);
39219 + return -EINVAL;
39220 + }
39221 +
39222 + pname = "atmel,blen";
39223 + if (of_property_read_u32(node, pname, &pdata->blen)) {
39224 + dev_err(&client->dev, "%s: Failed to read %s property\n",
39225 + __func__, pname);
39226 + return -EINVAL;
39227 + }
39228 +
39229 + pname = "atmel,threshold";
39230 + if (of_property_read_u32(node, pname, &pdata->threshold)) {
39231 + dev_err(&client->dev, "%s: Failed to read %s property\n",
39232 + __func__, pname);
39233 + return -EINVAL;
39234 + }
39235 +
39236 + pname = "atmel,voltage";
39237 + if (of_property_read_u32(node, pname, &pdata->voltage)) {
39238 + dev_err(&client->dev,
39239 + "%s: Failed to read %s property\n",
39240 + __func__, pname);
39241 + return -EINVAL;
39242 + }
39243 +
39244 + pname = "atmel,orient";
39245 + if (of_property_read_u32(node, pname, &val)) {
39246 + dev_err(&client->dev, "%s: Failed to read %s property\n",
39247 + __func__, pname);
39248 + return -EINVAL;
39249 + }
39250 +
39251 + if (val > 0xFF) {
39252 + dev_err(&client->dev, "%s: Bad %s property value %d\n",
39253 + __func__, pname, val);
39254 + return -EINVAL;
39255 + }
39256 + pdata->orient = val & 0xFF;
39257 +
39258 + return 0;
39259 +}
39260 +
39261 static int mxt_check_bootloader(struct i2c_client *client,
39262 unsigned int state)
39263 {
39264 @@ -1127,19 +1228,43 @@ static void mxt_input_close(struct input
39265 mxt_stop(data);
39266 }
39267
39268 +static const struct of_device_id mxt_dt_ids[] = {
39269 + { .compatible = "atmel,qt602240_ts", },
39270 + { .compatible = "atmel,atmel_mxt_ts", },
39271 + { .compatible = "atmel,mXT244", },
39272 + { /* sentinel */ }
39273 +};
39274 +MODULE_DEVICE_TABLE(of, mxt_dt_ids);
39275 +
39276 static int mxt_probe(struct i2c_client *client,
39277 const struct i2c_device_id *id)
39278 {
39279 - const struct mxt_platform_data *pdata = client->dev.platform_data;
39280 + struct mxt_platform_data *pdata;
39281 struct mxt_data *data;
39282 struct input_dev *input_dev;
39283 int error;
39284 unsigned int num_mt_slots;
39285 + const struct of_device_id *match;
39286
39287 - if (!pdata)
39288 - return -EINVAL;
39289 + match = of_match_device(of_match_ptr(mxt_dt_ids), &client->dev);
39290 + if (match) {
39291 + pdata = devm_kzalloc(&client->dev,
39292 + sizeof(struct mxt_platform_data),
39293 + GFP_KERNEL);
39294 + if (!pdata)
39295 + return -ENOMEM;
39296 + error = mxt_of_get_platform_info(client, pdata);
39297 + if (error)
39298 + return error;
39299 + } else {
39300 + pdata = client->dev.platform_data;
39301 + if (!pdata) {
39302 + dev_err(&client->dev, "Platform data not populated\n");
39303 + return -EINVAL;
39304 + }
39305 + }
39306
39307 - data = kzalloc(sizeof(struct mxt_data), GFP_KERNEL);
39308 + data = devm_kzalloc(&client->dev, sizeof(struct mxt_data), GFP_KERNEL);
39309 input_dev = input_allocate_device();
39310 if (!data || !input_dev) {
39311 dev_err(&client->dev, "Failed to allocate memory\n");
39312 @@ -1224,9 +1349,10 @@ static int mxt_probe(struct i2c_client *
39313 input_set_drvdata(input_dev, data);
39314 i2c_set_clientdata(client, data);
39315
39316 - error = request_threaded_irq(client->irq, NULL, mxt_interrupt,
39317 - pdata->irqflags | IRQF_ONESHOT,
39318 - client->name, data);
39319 + error = devm_request_threaded_irq(&client->dev, client->irq,
39320 + NULL, mxt_interrupt,
39321 + IRQF_ONESHOT,
39322 + dev_name(&client->dev), data);
39323 if (error) {
39324 dev_err(&client->dev, "Failed to register interrupt\n");
39325 goto err_free_object;
39326 @@ -1234,11 +1360,11 @@ static int mxt_probe(struct i2c_client *
39327
39328 error = mxt_make_highchg(data);
39329 if (error)
39330 - goto err_free_irq;
39331 + goto err_free_object;
39332
39333 error = input_register_device(input_dev);
39334 if (error)
39335 - goto err_free_irq;
39336 + goto err_free_object;
39337
39338 error = sysfs_create_group(&client->dev.kobj, &mxt_attr_group);
39339 if (error)
39340 @@ -1249,13 +1375,10 @@ static int mxt_probe(struct i2c_client *
39341 err_unregister_device:
39342 input_unregister_device(input_dev);
39343 input_dev = NULL;
39344 -err_free_irq:
39345 - free_irq(client->irq, data);
39346 err_free_object:
39347 kfree(data->object_table);
39348 err_free_mem:
39349 input_free_device(input_dev);
39350 - kfree(data);
39351 return error;
39352 }
39353
39354 @@ -1264,10 +1387,8 @@ static int mxt_remove(struct i2c_client
39355 struct mxt_data *data = i2c_get_clientdata(client);
39356
39357 sysfs_remove_group(&client->dev.kobj, &mxt_attr_group);
39358 - free_irq(data->irq, data);
39359 input_unregister_device(data->input_dev);
39360 kfree(data->object_table);
39361 - kfree(data);
39362
39363 return 0;
39364 }
39365 @@ -1328,6 +1449,7 @@ static struct i2c_driver mxt_driver = {
39366 .name = "atmel_mxt_ts",
39367 .owner = THIS_MODULE,
39368 .pm = &mxt_pm_ops,
39369 + .of_match_table = mxt_dt_ids,
39370 },
39371 .probe = mxt_probe,
39372 .remove = mxt_remove,
39373 --- a/drivers/input/touchscreen/pixcir_i2c_ts.c
39374 +++ b/drivers/input/touchscreen/pixcir_i2c_ts.c
39375 @@ -23,170 +23,490 @@
39376 #include <linux/slab.h>
39377 #include <linux/i2c.h>
39378 #include <linux/input.h>
39379 +#include <linux/input/mt.h>
39380 #include <linux/input/pixcir_ts.h>
39381 +#include <linux/gpio.h>
39382 +#include <linux/of.h>
39383 +#include <linux/of_gpio.h>
39384 +#include <linux/of_device.h>
39385 +
39386 +#define MAX_FINGERS 5 /* Maximum supported by the driver */
39387
39388 struct pixcir_i2c_ts_data {
39389 struct i2c_client *client;
39390 struct input_dev *input;
39391 - const struct pixcir_ts_platform_data *chip;
39392 + const struct pixcir_ts_platform_data *pdata;
39393 bool exiting;
39394 + u8 max_fingers; /* Maximum supported by the chip */
39395 };
39396
39397 -static void pixcir_ts_poscheck(struct pixcir_i2c_ts_data *data)
39398 +static void pixcir_ts_typea_report(struct pixcir_i2c_ts_data *tsdata)
39399 {
39400 - struct pixcir_i2c_ts_data *tsdata = data;
39401 + const struct pixcir_ts_platform_data *pdata = tsdata->pdata;
39402 u8 rdbuf[10], wrbuf[1] = { 0 };
39403 u8 touch;
39404 int ret;
39405
39406 - ret = i2c_master_send(tsdata->client, wrbuf, sizeof(wrbuf));
39407 - if (ret != sizeof(wrbuf)) {
39408 - dev_err(&tsdata->client->dev,
39409 - "%s: i2c_master_send failed(), ret=%d\n",
39410 - __func__, ret);
39411 - return;
39412 - }
39413 -
39414 - ret = i2c_master_recv(tsdata->client, rdbuf, sizeof(rdbuf));
39415 - if (ret != sizeof(rdbuf)) {
39416 - dev_err(&tsdata->client->dev,
39417 - "%s: i2c_master_recv failed(), ret=%d\n",
39418 - __func__, ret);
39419 - return;
39420 - }
39421 -
39422 - touch = rdbuf[0];
39423 - if (touch) {
39424 - u16 posx1 = (rdbuf[3] << 8) | rdbuf[2];
39425 - u16 posy1 = (rdbuf[5] << 8) | rdbuf[4];
39426 - u16 posx2 = (rdbuf[7] << 8) | rdbuf[6];
39427 - u16 posy2 = (rdbuf[9] << 8) | rdbuf[8];
39428 -
39429 - input_report_key(tsdata->input, BTN_TOUCH, 1);
39430 - input_report_abs(tsdata->input, ABS_X, posx1);
39431 - input_report_abs(tsdata->input, ABS_Y, posy1);
39432 -
39433 - input_report_abs(tsdata->input, ABS_MT_POSITION_X, posx1);
39434 - input_report_abs(tsdata->input, ABS_MT_POSITION_Y, posy1);
39435 - input_mt_sync(tsdata->input);
39436 -
39437 - if (touch == 2) {
39438 - input_report_abs(tsdata->input,
39439 - ABS_MT_POSITION_X, posx2);
39440 - input_report_abs(tsdata->input,
39441 - ABS_MT_POSITION_Y, posy2);
39442 + while (!tsdata->exiting) {
39443 +
39444 + ret = i2c_master_send(tsdata->client, wrbuf, sizeof(wrbuf));
39445 + if (ret != sizeof(wrbuf)) {
39446 + dev_err(&tsdata->client->dev,
39447 + "%s: i2c_master_send failed(), ret=%d\n",
39448 + __func__, ret);
39449 + return;
39450 + }
39451 +
39452 + ret = i2c_master_recv(tsdata->client, rdbuf, sizeof(rdbuf));
39453 + if (ret != sizeof(rdbuf)) {
39454 + dev_err(&tsdata->client->dev,
39455 + "%s: i2c_master_recv failed(), ret=%d\n",
39456 + __func__, ret);
39457 + return;
39458 + }
39459 +
39460 + touch = rdbuf[0];
39461 + if (touch) {
39462 + u16 posx1 = (rdbuf[3] << 8) | rdbuf[2];
39463 + u16 posy1 = (rdbuf[5] << 8) | rdbuf[4];
39464 + u16 posx2 = (rdbuf[7] << 8) | rdbuf[6];
39465 + u16 posy2 = (rdbuf[9] << 8) | rdbuf[8];
39466 +
39467 + input_report_key(tsdata->input, BTN_TOUCH, 1);
39468 + input_report_abs(tsdata->input, ABS_X, posx1);
39469 + input_report_abs(tsdata->input, ABS_Y, posy1);
39470 +
39471 + input_report_abs(tsdata->input, ABS_MT_POSITION_X,
39472 + posx1);
39473 + input_report_abs(tsdata->input, ABS_MT_POSITION_Y,
39474 + posy1);
39475 input_mt_sync(tsdata->input);
39476 +
39477 + if (touch == 2) {
39478 + input_report_abs(tsdata->input,
39479 + ABS_MT_POSITION_X, posx2);
39480 + input_report_abs(tsdata->input,
39481 + ABS_MT_POSITION_Y, posy2);
39482 + input_mt_sync(tsdata->input);
39483 + }
39484 + } else {
39485 + input_report_key(tsdata->input, BTN_TOUCH, 0);
39486 }
39487 - } else {
39488 - input_report_key(tsdata->input, BTN_TOUCH, 0);
39489 +
39490 + input_sync(tsdata->input);
39491 +
39492 + if (gpio_get_value(pdata->gpio_attb))
39493 + break;
39494 +
39495 + msleep(20);
39496 }
39497 +}
39498 +
39499 +static void pixcir_ts_typeb_report(struct pixcir_i2c_ts_data *ts)
39500 +{
39501 + const struct pixcir_ts_platform_data *pdata = ts->pdata;
39502 + struct device *dev = &ts->client->dev;
39503 + u8 rdbuf[32], wrbuf[1] = { 0 };
39504 + u8 *bufptr;
39505 + u8 num_fingers;
39506 + u8 unreliable;
39507 + int ret, i;
39508 +
39509 + while (!ts->exiting) {
39510 +
39511 + ret = i2c_master_send(ts->client, wrbuf, sizeof(wrbuf));
39512 + if (ret != sizeof(wrbuf)) {
39513 + dev_err(dev, "%s: i2c_master_send failed(), ret=%d\n",
39514 + __func__, ret);
39515 + return;
39516 + }
39517 +
39518 + ret = i2c_master_recv(ts->client, rdbuf, sizeof(rdbuf));
39519 + if (ret != sizeof(rdbuf)) {
39520 + dev_err(dev, "%s: i2c_master_recv failed(), ret=%d\n",
39521 + __func__, ret);
39522 + return;
39523 + }
39524
39525 - input_sync(tsdata->input);
39526 + unreliable = rdbuf[0] & 0xe0;
39527 +
39528 + if (unreliable)
39529 + goto next; /* ignore unreliable data */
39530 +
39531 + num_fingers = rdbuf[0] & 0x7;
39532 + bufptr = &rdbuf[2];
39533 +
39534 + if (num_fingers > ts->max_fingers) {
39535 + num_fingers = ts->max_fingers;
39536 + dev_dbg(dev, "limiting num_fingers to %d\n",
39537 + num_fingers);
39538 + }
39539 +
39540 + for (i = 0; i < num_fingers; i++) {
39541 + u8 id;
39542 + unsigned int x, y;
39543 + int slot;
39544 +
39545 + id = bufptr[4];
39546 + slot = input_mt_get_slot_by_key(ts->input, id);
39547 + if (slot < 0) {
39548 + dev_dbg(dev, "no free slot for id 0x%x\n", id);
39549 + continue;
39550 + }
39551 +
39552 +
39553 + x = bufptr[1] << 8 | bufptr[0];
39554 + y = bufptr[3] << 8 | bufptr[2];
39555 +
39556 + input_mt_slot(ts->input, slot);
39557 + input_mt_report_slot_state(ts->input,
39558 + MT_TOOL_FINGER, true);
39559 +
39560 + input_event(ts->input, EV_ABS, ABS_MT_POSITION_X, x);
39561 + input_event(ts->input, EV_ABS, ABS_MT_POSITION_Y, y);
39562 +
39563 + bufptr = &bufptr[5];
39564 + dev_dbg(dev, "%d: id 0x%x slot %d, x %d, y %d\n",
39565 + i, id, slot, x, y);
39566 + }
39567 +
39568 + /* One frame is complete so sync it */
39569 + input_mt_sync_frame(ts->input);
39570 + input_sync(ts->input);
39571 +
39572 +next:
39573 + if (gpio_get_value(pdata->gpio_attb))
39574 + break;
39575 +
39576 + usleep_range(2000, 5000);
39577 + }
39578 }
39579
39580 static irqreturn_t pixcir_ts_isr(int irq, void *dev_id)
39581 {
39582 struct pixcir_i2c_ts_data *tsdata = dev_id;
39583
39584 - while (!tsdata->exiting) {
39585 - pixcir_ts_poscheck(tsdata);
39586 + if (tsdata->input->mt)
39587 + pixcir_ts_typeb_report(tsdata);
39588 + else
39589 + pixcir_ts_typea_report(tsdata);
39590
39591 - if (tsdata->chip->attb_read_val())
39592 - break;
39593 + return IRQ_HANDLED;
39594 +}
39595
39596 - msleep(20);
39597 +static int pixcir_set_power_mode(struct pixcir_i2c_ts_data *ts,
39598 + enum pixcir_power_mode mode)
39599 +{
39600 + struct device *dev = &ts->client->dev;
39601 + int ret;
39602 +
39603 + ret = i2c_smbus_read_byte_data(ts->client, PIXCIR_REG_POWER_MODE);
39604 + if (ret < 0) {
39605 + dev_err(dev, "%s: can't read reg 0x%x : %d\n",
39606 + __func__, PIXCIR_REG_POWER_MODE, ret);
39607 + return ret;
39608 }
39609
39610 - return IRQ_HANDLED;
39611 + ret &= ~PIXCIR_POWER_MODE_MASK;
39612 + ret |= mode;
39613 +
39614 + /* Always AUTO_IDLE */
39615 + ret |= PIXCIR_POWER_ALLOW_IDLE;
39616 +
39617 + ret = i2c_smbus_write_byte_data(ts->client, PIXCIR_REG_POWER_MODE, ret);
39618 + if (ret < 0) {
39619 + dev_err(dev, "%s: can't write reg 0x%x : %d\n",
39620 + __func__, PIXCIR_REG_POWER_MODE, ret);
39621 + return ret;
39622 + }
39623 +
39624 + return 0;
39625 }
39626
39627 -#ifdef CONFIG_PM_SLEEP
39628 -static int pixcir_i2c_ts_suspend(struct device *dev)
39629 +/*
39630 + * Set the interrupt mode for the device i.e. ATTB line behaviour
39631 + *
39632 + * @polarity : 1 for active high, 0 for active low.
39633 + */
39634 +static int pixcir_set_int_mode(struct pixcir_i2c_ts_data *ts,
39635 + enum pixcir_int_mode mode,
39636 + bool polarity)
39637 {
39638 - struct i2c_client *client = to_i2c_client(dev);
39639 + struct device *dev = &ts->client->dev;
39640 + int ret;
39641
39642 - if (device_may_wakeup(&client->dev))
39643 - enable_irq_wake(client->irq);
39644 + ret = i2c_smbus_read_byte_data(ts->client, PIXCIR_REG_INT_MODE);
39645 + if (ret < 0) {
39646 + dev_err(dev, "%s: can't read reg 0x%x : %d\n",
39647 + __func__, PIXCIR_REG_INT_MODE, ret);
39648 + return ret;
39649 + }
39650 +
39651 + ret &= ~PIXCIR_INT_MODE_MASK;
39652 + ret |= mode;
39653 +
39654 + if (polarity)
39655 + ret |= PIXCIR_INT_POL_HIGH;
39656 + else
39657 + ret &= ~PIXCIR_INT_POL_HIGH;
39658 +
39659 + ret = i2c_smbus_write_byte_data(ts->client, PIXCIR_REG_INT_MODE, ret);
39660 + if (ret < 0) {
39661 + dev_err(dev, "%s: can't write reg 0x%x : %d\n",
39662 + __func__, PIXCIR_REG_INT_MODE, ret);
39663 + return ret;
39664 + }
39665
39666 return 0;
39667 }
39668
39669 -static int pixcir_i2c_ts_resume(struct device *dev)
39670 +/*
39671 + * Enable/disable interrupt generation
39672 + */
39673 +static int pixcir_int_enable(struct pixcir_i2c_ts_data *ts, bool enable)
39674 {
39675 - struct i2c_client *client = to_i2c_client(dev);
39676 + struct device *dev = &ts->client->dev;
39677 + int ret;
39678
39679 - if (device_may_wakeup(&client->dev))
39680 - disable_irq_wake(client->irq);
39681 + ret = i2c_smbus_read_byte_data(ts->client, PIXCIR_REG_INT_MODE);
39682 + if (ret < 0) {
39683 + dev_err(dev, "%s: can't read reg 0x%x : %d\n",
39684 + __func__, PIXCIR_REG_INT_MODE, ret);
39685 + return ret;
39686 + }
39687 +
39688 + if (enable)
39689 + ret |= PIXCIR_INT_ENABLE;
39690 + else
39691 + ret &= ~PIXCIR_INT_ENABLE;
39692 +
39693 + ret = i2c_smbus_write_byte_data(ts->client, PIXCIR_REG_INT_MODE, ret);
39694 + if (ret < 0) {
39695 + dev_err(dev, "%s: can't write reg 0x%x : %d\n",
39696 + __func__, PIXCIR_REG_INT_MODE, ret);
39697 + return ret;
39698 + }
39699
39700 return 0;
39701 }
39702 -#endif
39703
39704 -static SIMPLE_DEV_PM_OPS(pixcir_dev_pm_ops,
39705 - pixcir_i2c_ts_suspend, pixcir_i2c_ts_resume);
39706 +static int pixcir_start(struct pixcir_i2c_ts_data *ts)
39707 +{
39708 + struct device *dev = &ts->client->dev;
39709 + int ret;
39710 +
39711 + /* LEVEL_TOUCH interrupt with active low polarity */
39712 + ret = pixcir_set_int_mode(ts, PIXCIR_INT_LEVEL_TOUCH, 0);
39713 + if (ret) {
39714 + dev_err(dev, "Failed to set interrupt mode\n");
39715 + return ret;
39716 + }
39717 +
39718 + enable_irq(ts->client->irq);
39719 +
39720 + /* enable interrupt generation */
39721 + ret = pixcir_int_enable(ts, 1);
39722 + if (ret) {
39723 + dev_err(dev, "Failed to enable interrupt generation\n");
39724 + return ret;
39725 + }
39726 +
39727 + return 0;
39728 +}
39729 +
39730 +static int pixcir_stop(struct pixcir_i2c_ts_data *ts)
39731 +{
39732 + struct device *dev = &ts->client->dev;
39733 + int ret;
39734 +
39735 + /* disable interrupt generation */
39736 + ret = pixcir_int_enable(ts, 0);
39737 + if (ret) {
39738 + dev_err(dev, "Failed to disable interrupt generation\n");
39739 + return ret;
39740 + }
39741 +
39742 + disable_irq(ts->client->irq);
39743 +
39744 + return 0;
39745 +}
39746 +
39747 +static int pixcir_input_open(struct input_dev *dev)
39748 +{
39749 + struct pixcir_i2c_ts_data *ts = input_get_drvdata(dev);
39750 +
39751 + return pixcir_start(ts);
39752 +}
39753 +
39754 +static void pixcir_input_close(struct input_dev *dev)
39755 +{
39756 + struct pixcir_i2c_ts_data *ts = input_get_drvdata(dev);
39757 +
39758 + pixcir_stop(ts);
39759 +
39760 + return;
39761 +}
39762 +
39763 +#if defined(CONFIG_OF)
39764 +static const struct of_device_id pixcir_of_match[];
39765 +
39766 +static struct pixcir_ts_platform_data *pixcir_parse_dt(struct device *dev)
39767 +{
39768 + struct pixcir_ts_platform_data *pdata;
39769 + struct device_node *np = dev->of_node;
39770 + const struct of_device_id *match;
39771 +
39772 + match = of_match_device(of_match_ptr(pixcir_of_match), dev);
39773 + if (!match)
39774 + return ERR_PTR(-EINVAL);
39775 +
39776 + pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
39777 + if (!pdata)
39778 + return ERR_PTR(-ENOMEM);
39779 +
39780 + pdata->chip = *(const struct pixcir_i2c_chip_data *)match->data;
39781 +
39782 + pdata->gpio_attb = of_get_named_gpio(np, "attb-gpio", 0);
39783 + if (!gpio_is_valid(pdata->gpio_attb)) {
39784 + dev_err(dev, "Failed to get ATTB GPIO\n");
39785 + return ERR_PTR(-EINVAL);
39786 + }
39787 +
39788 + if (of_property_read_u32(np, "x-size", &pdata->x_size)) {
39789 + dev_err(dev, "Failed to get x-size property\n");
39790 + return ERR_PTR(-EINVAL);
39791 + }
39792 +
39793 + if (of_property_read_u32(np, "y-size", &pdata->y_size)) {
39794 + dev_err(dev, "Failed to get y-size property\n");
39795 + return ERR_PTR(-EINVAL);
39796 + }
39797 +
39798 + dev_dbg(dev, "%s: x %d, y %d, gpio %d\n", __func__,
39799 + pdata->x_size, pdata->y_size, pdata->gpio_attb);
39800 +
39801 + return pdata;
39802 +}
39803 +#else
39804 +static struct pixcir_ts_platform_data *pixcir_parse_dt(struct device *dev)
39805 +{
39806 + return NULL;
39807 +}
39808 +#endif
39809
39810 static int pixcir_i2c_ts_probe(struct i2c_client *client,
39811 const struct i2c_device_id *id)
39812 {
39813 const struct pixcir_ts_platform_data *pdata = client->dev.platform_data;
39814 + struct device *dev = &client->dev;
39815 + struct device_node *np = dev->of_node;
39816 struct pixcir_i2c_ts_data *tsdata;
39817 struct input_dev *input;
39818 int error;
39819
39820 - if (!pdata) {
39821 + if (np) {
39822 + pdata = pixcir_parse_dt(dev);
39823 + if (IS_ERR(pdata))
39824 + return PTR_ERR(pdata);
39825 +
39826 + } else if (!pdata) {
39827 dev_err(&client->dev, "platform data not defined\n");
39828 return -EINVAL;
39829 + } else {
39830 + if (!gpio_is_valid(pdata->gpio_attb)) {
39831 + dev_err(dev, "Invalid gpio_attb in pdata\n");
39832 + return -EINVAL;
39833 + }
39834 }
39835
39836 - tsdata = kzalloc(sizeof(*tsdata), GFP_KERNEL);
39837 - input = input_allocate_device();
39838 - if (!tsdata || !input) {
39839 - dev_err(&client->dev, "Failed to allocate driver data!\n");
39840 - error = -ENOMEM;
39841 - goto err_free_mem;
39842 + tsdata = devm_kzalloc(dev, sizeof(*tsdata), GFP_KERNEL);
39843 + if (!tsdata)
39844 + return -ENOMEM;
39845 +
39846 + input = devm_input_allocate_device(dev);
39847 + if (!input) {
39848 + dev_err(&client->dev, "Failed to allocate input device\n");
39849 + return -ENOMEM;
39850 }
39851
39852 tsdata->client = client;
39853 tsdata->input = input;
39854 - tsdata->chip = pdata;
39855 + tsdata->pdata = pdata;
39856
39857 input->name = client->name;
39858 input->id.bustype = BUS_I2C;
39859 input->dev.parent = &client->dev;
39860 + input->open = pixcir_input_open;
39861 + input->close = pixcir_input_close;
39862
39863 - __set_bit(EV_KEY, input->evbit);
39864 __set_bit(EV_ABS, input->evbit);
39865 __set_bit(BTN_TOUCH, input->keybit);
39866 - input_set_abs_params(input, ABS_X, 0, pdata->x_max, 0, 0);
39867 - input_set_abs_params(input, ABS_Y, 0, pdata->y_max, 0, 0);
39868 - input_set_abs_params(input, ABS_MT_POSITION_X, 0, pdata->x_max, 0, 0);
39869 - input_set_abs_params(input, ABS_MT_POSITION_Y, 0, pdata->y_max, 0, 0);
39870 +
39871 + input_set_abs_params(input, ABS_X,
39872 + 0, pdata->x_size - 1, 0, 0);
39873 + input_set_abs_params(input, ABS_Y,
39874 + 0, pdata->y_size - 1, 0, 0);
39875 + input_set_abs_params(input, ABS_MT_POSITION_X,
39876 + 0, pdata->x_size - 1, 0, 0);
39877 + input_set_abs_params(input, ABS_MT_POSITION_Y,
39878 + 0, pdata->y_size - 1, 0, 0);
39879 +
39880 + /* Type-B Multi-Touch support */
39881 + if (pdata->chip.num_report_ids) {
39882 + const struct pixcir_i2c_chip_data *chip = &pdata->chip;
39883 +
39884 + tsdata->max_fingers = chip->num_report_ids;
39885 + if (tsdata->max_fingers > MAX_FINGERS) {
39886 + dev_info(dev, "Limiting maximum fingers to %d\n",
39887 + MAX_FINGERS);
39888 + tsdata->max_fingers = MAX_FINGERS;
39889 + }
39890 +
39891 + error = input_mt_init_slots(input, tsdata->max_fingers,
39892 + INPUT_MT_DIRECT | INPUT_MT_DROP_UNUSED);
39893 + if (error) {
39894 + dev_err(dev, "Error initializing Multi-Touch slots\n");
39895 + return error;
39896 + }
39897 + }
39898
39899 input_set_drvdata(input, tsdata);
39900
39901 - error = request_threaded_irq(client->irq, NULL, pixcir_ts_isr,
39902 + error = devm_gpio_request_one(dev, pdata->gpio_attb,
39903 + GPIOF_DIR_IN, "pixcir_i2c_attb");
39904 + if (error) {
39905 + dev_err(dev, "Failed to request ATTB gpio\n");
39906 + return error;
39907 + }
39908 +
39909 + error = devm_request_threaded_irq(dev, client->irq, NULL, pixcir_ts_isr,
39910 IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
39911 client->name, tsdata);
39912 if (error) {
39913 - dev_err(&client->dev, "Unable to request touchscreen IRQ.\n");
39914 - goto err_free_mem;
39915 + dev_err(dev, "failed to request irq %d\n", client->irq);
39916 + return error;
39917 }
39918
39919 + /* Always be in IDLE mode to save power, device supports auto wake */
39920 + error = pixcir_set_power_mode(tsdata, PIXCIR_POWER_IDLE);
39921 + if (error) {
39922 + dev_err(dev, "Failed to set IDLE mode\n");
39923 + return error;
39924 + }
39925 +
39926 + /* Stop device till opened */
39927 + error = pixcir_stop(tsdata);
39928 + if (error)
39929 + return error;
39930 +
39931 error = input_register_device(input);
39932 if (error)
39933 - goto err_free_irq;
39934 + return error;
39935
39936 i2c_set_clientdata(client, tsdata);
39937 device_init_wakeup(&client->dev, 1);
39938
39939 return 0;
39940 -
39941 -err_free_irq:
39942 - free_irq(client->irq, tsdata);
39943 -err_free_mem:
39944 - input_free_device(input);
39945 - kfree(tsdata);
39946 - return error;
39947 }
39948
39949 static int pixcir_i2c_ts_remove(struct i2c_client *client)
39950 @@ -197,25 +517,99 @@ static int pixcir_i2c_ts_remove(struct i
39951
39952 tsdata->exiting = true;
39953 mb();
39954 - free_irq(client->irq, tsdata);
39955 -
39956 - input_unregister_device(tsdata->input);
39957 - kfree(tsdata);
39958
39959 return 0;
39960 }
39961
39962 +#ifdef CONFIG_PM_SLEEP
39963 +static int pixcir_i2c_ts_suspend(struct device *dev)
39964 +{
39965 + struct i2c_client *client = to_i2c_client(dev);
39966 + struct pixcir_i2c_ts_data *ts = i2c_get_clientdata(client);
39967 + struct input_dev *input = ts->input;
39968 + int ret = 0;
39969 +
39970 + mutex_lock(&input->mutex);
39971 +
39972 + if (device_may_wakeup(&client->dev)) {
39973 + /* need to start device if not open, to be wakeup source */
39974 + if (!input->users) {
39975 + ret = pixcir_start(ts);
39976 + if (ret)
39977 + goto unlock;
39978 + }
39979 +
39980 + enable_irq_wake(client->irq);
39981 +
39982 + } else if (input->users) {
39983 + ret = pixcir_stop(ts);
39984 + }
39985 +
39986 +unlock:
39987 + mutex_unlock(&input->mutex);
39988 +
39989 + return ret;
39990 +}
39991 +
39992 +static int pixcir_i2c_ts_resume(struct device *dev)
39993 +{
39994 + struct i2c_client *client = to_i2c_client(dev);
39995 + struct pixcir_i2c_ts_data *ts = i2c_get_clientdata(client);
39996 + struct input_dev *input = ts->input;
39997 + int ret = 0;
39998 +
39999 + mutex_lock(&input->mutex);
40000 +
40001 + if (device_may_wakeup(&client->dev)) {
40002 + disable_irq_wake(client->irq);
40003 +
40004 + /* need to stop device if it was not open on suspend */
40005 + if (!input->users) {
40006 + ret = pixcir_stop(ts);
40007 + if (ret)
40008 + goto unlock;
40009 + }
40010 +
40011 + } else if (input->users) {
40012 + ret = pixcir_start(ts);
40013 + }
40014 +
40015 +unlock:
40016 + mutex_unlock(&input->mutex);
40017 +
40018 + return ret;
40019 +}
40020 +#endif
40021 +
40022 +static SIMPLE_DEV_PM_OPS(pixcir_dev_pm_ops,
40023 + pixcir_i2c_ts_suspend, pixcir_i2c_ts_resume);
40024 +
40025 static const struct i2c_device_id pixcir_i2c_ts_id[] = {
40026 { "pixcir_ts", 0 },
40027 + { "pixcir_tangoc", 0},
40028 { }
40029 };
40030 MODULE_DEVICE_TABLE(i2c, pixcir_i2c_ts_id);
40031
40032 +#if defined(CONFIG_OF)
40033 +static const struct pixcir_i2c_chip_data tangoc_data = {
40034 + .num_report_ids = 5,
40035 +};
40036 +
40037 +static const struct of_device_id pixcir_of_match[] = {
40038 + { .compatible = "pixcir,pixcir_ts", },
40039 + { .compatible = "pixcir,pixcir_tangoc", .data = &tangoc_data, },
40040 + { }
40041 +};
40042 +MODULE_DEVICE_TABLE(of, pixcir_of_match);
40043 +#endif
40044 +
40045 static struct i2c_driver pixcir_i2c_ts_driver = {
40046 .driver = {
40047 .owner = THIS_MODULE,
40048 .name = "pixcir_ts",
40049 .pm = &pixcir_dev_pm_ops,
40050 + .of_match_table = of_match_ptr(pixcir_of_match),
40051 },
40052 .probe = pixcir_i2c_ts_probe,
40053 .remove = pixcir_i2c_ts_remove,
40054 --- a/drivers/input/touchscreen/ti_am335x_tsc.c
40055 +++ b/drivers/input/touchscreen/ti_am335x_tsc.c
40056 @@ -348,9 +348,16 @@ static int titsc_parse_dt(struct platfor
40057 if (err < 0)
40058 return err;
40059
40060 - err = of_property_read_u32(node, "ti,coordiante-readouts",
40061 + /*
40062 + * try with new binding first. If it fails, still try with
40063 + * bogus, miss-spelled version.
40064 + */
40065 + err = of_property_read_u32(node, "ti,coordinate-readouts",
40066 &ts_dev->coordinate_readouts);
40067 if (err < 0)
40068 + err = of_property_read_u32(node, "ti,coordiante-readouts",
40069 + &ts_dev->coordinate_readouts);
40070 + if (err < 0)
40071 return err;
40072
40073 return of_property_read_u32_array(node, "ti,wire-config",
40074 --- a/drivers/Kconfig
40075 +++ b/drivers/Kconfig
40076 @@ -166,4 +166,6 @@ source "drivers/reset/Kconfig"
40077
40078 source "drivers/fmc/Kconfig"
40079
40080 +source "drivers/phy/Kconfig"
40081 +
40082 endmenu
40083 --- a/drivers/mailbox/mailbox-omap1.c
40084 +++ b/drivers/mailbox/mailbox-omap1.c
40085 @@ -13,6 +13,7 @@
40086 #include <linux/interrupt.h>
40087 #include <linux/platform_device.h>
40088 #include <linux/io.h>
40089 +#include <linux/delay.h>
40090
40091 #include "omap-mbox.h"
40092
40093 @@ -26,7 +27,7 @@
40094 #define MAILBOX_DSP2ARM1_Flag 0x1c
40095 #define MAILBOX_DSP2ARM2_Flag 0x20
40096
40097 -static void __iomem *mbox_base;
40098 +static struct omap_mbox_device omap1_mbox_device;
40099
40100 struct omap_mbox1_fifo {
40101 unsigned long cmd;
40102 @@ -37,16 +38,17 @@ struct omap_mbox1_fifo {
40103 struct omap_mbox1_priv {
40104 struct omap_mbox1_fifo tx_fifo;
40105 struct omap_mbox1_fifo rx_fifo;
40106 + bool empty_flag;
40107 };
40108
40109 static inline int mbox_read_reg(size_t ofs)
40110 {
40111 - return __raw_readw(mbox_base + ofs);
40112 + return __raw_readw(omap1_mbox_device.mbox_base + ofs);
40113 }
40114
40115 static inline void mbox_write_reg(u32 val, size_t ofs)
40116 {
40117 - __raw_writew(val, mbox_base + ofs);
40118 + __raw_writew(val, omap1_mbox_device.mbox_base + ofs);
40119 }
40120
40121 /* msg */
40122 @@ -59,6 +61,7 @@ static mbox_msg_t omap1_mbox_fifo_read(s
40123 msg = mbox_read_reg(fifo->data);
40124 msg |= ((mbox_msg_t) mbox_read_reg(fifo->cmd)) << 16;
40125
40126 + (struct omap_mbox1_priv *)(mbox->priv)->empty_flag = false;
40127 return msg;
40128 }
40129
40130 @@ -74,7 +77,9 @@ omap1_mbox_fifo_write(struct omap_mbox *
40131
40132 static int omap1_mbox_fifo_empty(struct omap_mbox *mbox)
40133 {
40134 - return 0;
40135 + struct omap_mbox1_priv *priv = (struct omap_mbox1_priv *)mbox->priv;
40136 +
40137 + return priv->empty_flag ? 0 : 1;
40138 }
40139
40140 static int omap1_mbox_fifo_full(struct omap_mbox *mbox)
40141 @@ -85,6 +90,18 @@ static int omap1_mbox_fifo_full(struct o
40142 return mbox_read_reg(fifo->flag);
40143 }
40144
40145 +static int omap1_mbox_poll_for_space(struct omap_mbox *mbox)
40146 +{
40147 + int i = 1000;
40148 +
40149 + while (omap1_mbox_fifo_full(mbox)) {
40150 + if (--i == 0)
40151 + return -1;
40152 + udelay(1);
40153 + }
40154 + return 0;
40155 +}
40156 +
40157 /* irq */
40158 static void
40159 omap1_mbox_enable_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
40160 @@ -103,17 +120,21 @@ omap1_mbox_disable_irq(struct omap_mbox
40161 static int
40162 omap1_mbox_is_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
40163 {
40164 + struct omap_mbox1_priv *priv = (struct omap_mbox1_priv *)mbox->priv;
40165 +
40166 if (irq == IRQ_TX)
40167 return 0;
40168 + if (irq == IRQ_RX)
40169 + priv->empty_flag = true;
40170 +
40171 return 1;
40172 }
40173
40174 static struct omap_mbox_ops omap1_mbox_ops = {
40175 - .type = OMAP_MBOX_TYPE1,
40176 .fifo_read = omap1_mbox_fifo_read,
40177 .fifo_write = omap1_mbox_fifo_write,
40178 .fifo_empty = omap1_mbox_fifo_empty,
40179 - .fifo_full = omap1_mbox_fifo_full,
40180 + .poll_for_space = omap1_mbox_poll_for_space,
40181 .enable_irq = omap1_mbox_enable_irq,
40182 .disable_irq = omap1_mbox_disable_irq,
40183 .is_irq = omap1_mbox_is_irq,
40184 @@ -139,6 +160,7 @@ static struct omap_mbox mbox_dsp_info =
40185 .name = "dsp",
40186 .ops = &omap1_mbox_ops,
40187 .priv = &omap1_mbox_dsp_priv,
40188 + .parent = &omap1_mbox_device,
40189 };
40190
40191 static struct omap_mbox *omap1_mboxes[] = { &mbox_dsp_info, NULL };
40192 @@ -148,6 +170,7 @@ static int omap1_mbox_probe(struct platf
40193 struct resource *mem;
40194 int ret;
40195 struct omap_mbox **list;
40196 + struct omap_mbox_device *mdev = &omap1_mbox_device;
40197
40198 list = omap1_mboxes;
40199 list[0]->irq = platform_get_irq_byname(pdev, "dsp");
40200 @@ -156,13 +179,18 @@ static int omap1_mbox_probe(struct platf
40201 if (!mem)
40202 return -ENOENT;
40203
40204 - mbox_base = ioremap(mem->start, resource_size(mem));
40205 - if (!mbox_base)
40206 + mdev->mbox_base = ioremap(mem->start, resource_size(mem));
40207 + if (!mdev->mbox_base)
40208 return -ENOMEM;
40209 + mutex_init(&mdev->cfg_lock);
40210 + mdev->dev = &pdev->dev;
40211 + mdev->mboxes = omap1_mboxes;
40212 + mdev->num_users = 2;
40213 + mdev->num_fifos = 4;
40214
40215 - ret = omap_mbox_register(&pdev->dev, list);
40216 + ret = omap_mbox_register(mdev);
40217 if (ret) {
40218 - iounmap(mbox_base);
40219 + iounmap(mdev->mbox_base);
40220 return ret;
40221 }
40222
40223 @@ -171,8 +199,14 @@ static int omap1_mbox_probe(struct platf
40224
40225 static int omap1_mbox_remove(struct platform_device *pdev)
40226 {
40227 - omap_mbox_unregister();
40228 - iounmap(mbox_base);
40229 + struct omap_mbox_device *mdev = &omap1_mbox_device;
40230 +
40231 + omap_mbox_unregister(mdev);
40232 + iounmap(mdev->mbox_base);
40233 + mdev->mbox_base = NULL;
40234 + mdev->mboxes = NULL;
40235 + mdev->dev = NULL;
40236 +
40237 return 0;
40238 }
40239
40240 --- a/drivers/mailbox/mailbox-omap2.c
40241 +++ b/drivers/mailbox/mailbox-omap2.c
40242 @@ -14,6 +14,7 @@
40243 #include <linux/slab.h>
40244 #include <linux/clk.h>
40245 #include <linux/err.h>
40246 +#include <linux/of_device.h>
40247 #include <linux/platform_device.h>
40248 #include <linux/io.h>
40249 #include <linux/pm_runtime.h>
40250 @@ -35,6 +36,8 @@
40251 #define MAILBOX_IRQ_NEWMSG(m) (1 << (2 * (m)))
40252 #define MAILBOX_IRQ_NOTFULL(m) (1 << (2 * (m) + 1))
40253
40254 +#define AM33X_MBOX_WKUPM3_USR 3
40255 +
40256 #define MBOX_REG_SIZE 0x120
40257
40258 #define OMAP4_MBOX_REG_SIZE 0x130
40259 @@ -42,8 +45,6 @@
40260 #define MBOX_NR_REGS (MBOX_REG_SIZE / sizeof(u32))
40261 #define OMAP4_MBOX_NR_REGS (OMAP4_MBOX_REG_SIZE / sizeof(u32))
40262
40263 -static void __iomem *mbox_base;
40264 -
40265 struct omap_mbox2_fifo {
40266 unsigned long msg;
40267 unsigned long fifo_stat;
40268 @@ -62,34 +63,38 @@ struct omap_mbox2_priv {
40269 u32 intr_type;
40270 };
40271
40272 -static inline unsigned int mbox_read_reg(size_t ofs)
40273 +static inline
40274 +unsigned int mbox_read_reg(struct omap_mbox_device *mdev, size_t ofs)
40275 {
40276 - return __raw_readl(mbox_base + ofs);
40277 + return __raw_readl(mdev->mbox_base + ofs);
40278 }
40279
40280 -static inline void mbox_write_reg(u32 val, size_t ofs)
40281 +static inline
40282 +void mbox_write_reg(struct omap_mbox_device *mdev, u32 val, size_t ofs)
40283 {
40284 - __raw_writel(val, mbox_base + ofs);
40285 + __raw_writel(val, mdev->mbox_base + ofs);
40286 }
40287
40288 /* Mailbox H/W preparations */
40289 static int omap2_mbox_startup(struct omap_mbox *mbox)
40290 {
40291 - u32 l;
40292 -
40293 - pm_runtime_enable(mbox->dev->parent);
40294 - pm_runtime_get_sync(mbox->dev->parent);
40295 + pm_runtime_get_sync(mbox->parent->dev);
40296
40297 - l = mbox_read_reg(MAILBOX_REVISION);
40298 - pr_debug("omap mailbox rev %d.%d\n", (l & 0xf0) >> 4, (l & 0x0f));
40299 + /*
40300 + * just print the raw revision register, the format is not
40301 + * uniform across all SoCs
40302 + */
40303 + if (!mbox->use_count) {
40304 + u32 l = mbox_read_reg(mbox->parent, MAILBOX_REVISION);
40305 + pr_debug("omap mailbox rev 0x%x\n", l);
40306 + }
40307
40308 return 0;
40309 }
40310
40311 static void omap2_mbox_shutdown(struct omap_mbox *mbox)
40312 {
40313 - pm_runtime_put_sync(mbox->dev->parent);
40314 - pm_runtime_disable(mbox->dev->parent);
40315 + pm_runtime_put_sync(mbox->parent->dev);
40316 }
40317
40318 /* Mailbox FIFO handle functions */
40319 @@ -97,28 +102,36 @@ static mbox_msg_t omap2_mbox_fifo_read(s
40320 {
40321 struct omap_mbox2_fifo *fifo =
40322 &((struct omap_mbox2_priv *)mbox->priv)->rx_fifo;
40323 - return (mbox_msg_t) mbox_read_reg(fifo->msg);
40324 + return (mbox_msg_t) mbox_read_reg(mbox->parent, fifo->msg);
40325 }
40326
40327 static void omap2_mbox_fifo_write(struct omap_mbox *mbox, mbox_msg_t msg)
40328 {
40329 struct omap_mbox2_fifo *fifo =
40330 &((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
40331 - mbox_write_reg(msg, fifo->msg);
40332 + mbox_write_reg(mbox->parent, msg, fifo->msg);
40333 }
40334
40335 static int omap2_mbox_fifo_empty(struct omap_mbox *mbox)
40336 {
40337 struct omap_mbox2_fifo *fifo =
40338 &((struct omap_mbox2_priv *)mbox->priv)->rx_fifo;
40339 - return (mbox_read_reg(fifo->msg_stat) == 0);
40340 + return (mbox_read_reg(mbox->parent, fifo->msg_stat) == 0);
40341 }
40342
40343 static int omap2_mbox_fifo_full(struct omap_mbox *mbox)
40344 {
40345 struct omap_mbox2_fifo *fifo =
40346 &((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
40347 - return mbox_read_reg(fifo->fifo_stat);
40348 + return mbox_read_reg(mbox->parent, fifo->fifo_stat);
40349 +}
40350 +
40351 +static int omap2_mbox_poll_for_space(struct omap_mbox *mbox)
40352 +{
40353 + if (omap2_mbox_fifo_full(mbox))
40354 + return -1;
40355 +
40356 + return 0;
40357 }
40358
40359 /* Mailbox IRQ handle functions */
40360 @@ -127,9 +140,9 @@ static void omap2_mbox_enable_irq(struct
40361 struct omap_mbox2_priv *p = mbox->priv;
40362 u32 l, bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
40363
40364 - l = mbox_read_reg(p->irqenable);
40365 + l = mbox_read_reg(mbox->parent, p->irqenable);
40366 l |= bit;
40367 - mbox_write_reg(l, p->irqenable);
40368 + mbox_write_reg(mbox->parent, l, p->irqenable);
40369 }
40370
40371 static void omap2_mbox_disable_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
40372 @@ -142,9 +155,9 @@ static void omap2_mbox_disable_irq(struc
40373 * OMAP4 and later SoCs have a dedicated interrupt disabling register.
40374 */
40375 if (!p->intr_type)
40376 - bit = mbox_read_reg(p->irqdisable) & ~bit;
40377 + bit = mbox_read_reg(mbox->parent, p->irqdisable) & ~bit;
40378
40379 - mbox_write_reg(bit, p->irqdisable);
40380 + mbox_write_reg(mbox->parent, bit, p->irqdisable);
40381 }
40382
40383 static void omap2_mbox_ack_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
40384 @@ -152,18 +165,69 @@ static void omap2_mbox_ack_irq(struct om
40385 struct omap_mbox2_priv *p = mbox->priv;
40386 u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
40387
40388 - mbox_write_reg(bit, p->irqstatus);
40389 + mbox_write_reg(mbox->parent, bit, p->irqstatus);
40390
40391 /* Flush posted write for irq status to avoid spurious interrupts */
40392 - mbox_read_reg(p->irqstatus);
40393 + mbox_read_reg(mbox->parent, p->irqstatus);
40394 }
40395
40396 static int omap2_mbox_is_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
40397 {
40398 struct omap_mbox2_priv *p = mbox->priv;
40399 u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
40400 - u32 enable = mbox_read_reg(p->irqenable);
40401 - u32 status = mbox_read_reg(p->irqstatus);
40402 + u32 enable = mbox_read_reg(mbox->parent, p->irqenable);
40403 + u32 status = mbox_read_reg(mbox->parent, p->irqstatus);
40404 +
40405 + return (int)(enable & status & bit);
40406 +}
40407 +
40408 +static void wkupm3_mbox_enable_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
40409 +{
40410 + struct omap_mbox2_priv *p = mbox->priv;
40411 + u32 l, bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
40412 + unsigned long irqenable = ((irq == IRQ_RX) ?
40413 + OMAP4_MAILBOX_IRQENABLE(AM33X_MBOX_WKUPM3_USR) : p->irqenable);
40414 +
40415 + l = mbox_read_reg(mbox->parent, irqenable);
40416 + l |= bit;
40417 + mbox_write_reg(mbox->parent, l, irqenable);
40418 +}
40419 +
40420 +static void wkupm3_mbox_disable_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
40421 +{
40422 + struct omap_mbox2_priv *p = mbox->priv;
40423 + u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
40424 + unsigned long irqdisable = ((irq == IRQ_RX) ?
40425 + OMAP4_MAILBOX_IRQENABLE_CLR(AM33X_MBOX_WKUPM3_USR) : p->irqdisable);
40426 +
40427 + mbox_write_reg(mbox->parent, bit, irqdisable);
40428 +}
40429 +
40430 +static void wkupm3_mbox_ack_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
40431 +{
40432 + struct omap_mbox2_priv *p = mbox->priv;
40433 + u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
40434 + unsigned long irqstatus = ((irq == IRQ_RX) ?
40435 + OMAP4_MAILBOX_IRQSTATUS(AM33X_MBOX_WKUPM3_USR) : p->irqstatus);
40436 +
40437 + mbox_write_reg(mbox->parent, bit, irqstatus);
40438 +
40439 + /* Flush posted write for irq status to avoid spurious interrupts */
40440 + mbox_read_reg(mbox->parent, irqstatus);
40441 +}
40442 +
40443 +static int wkupm3_mbox_is_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
40444 +{
40445 + struct omap_mbox2_priv *p = mbox->priv;
40446 + u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
40447 + u32 enable, status;
40448 +
40449 + /* WkupM3 mailbox does not use a receive queue */
40450 + if (irq == IRQ_RX)
40451 + return 0;
40452 +
40453 + enable = mbox_read_reg(mbox->parent, p->irqenable);
40454 + status = mbox_read_reg(mbox->parent, p->irqstatus);
40455
40456 return (int)(enable & status & bit);
40457 }
40458 @@ -179,7 +243,7 @@ static void omap2_mbox_save_ctx(struct o
40459 else
40460 nr_regs = MBOX_NR_REGS;
40461 for (i = 0; i < nr_regs; i++) {
40462 - p->ctx[i] = mbox_read_reg(i * sizeof(u32));
40463 + p->ctx[i] = mbox_read_reg(mbox->parent, i * sizeof(u32));
40464
40465 dev_dbg(mbox->dev, "%s: [%02x] %08x\n", __func__,
40466 i, p->ctx[i]);
40467 @@ -197,21 +261,34 @@ static void omap2_mbox_restore_ctx(struc
40468 else
40469 nr_regs = MBOX_NR_REGS;
40470 for (i = 0; i < nr_regs; i++) {
40471 - mbox_write_reg(p->ctx[i], i * sizeof(u32));
40472 + mbox_write_reg(mbox->parent, p->ctx[i], i * sizeof(u32));
40473
40474 dev_dbg(mbox->dev, "%s: [%02x] %08x\n", __func__,
40475 i, p->ctx[i]);
40476 }
40477 }
40478
40479 +static void wkupm3_mbox_send_data(struct omap_mbox *mbox, mbox_msg_t msg)
40480 +{
40481 + mbox_msg_t rmsg;
40482 +
40483 + /* enable the mbox Rx interrupt for WkupM3 only briefly */
40484 + wkupm3_mbox_enable_irq(mbox, IRQ_RX);
40485 + omap2_mbox_fifo_write(mbox, msg);
40486 + wkupm3_mbox_disable_irq(mbox, IRQ_RX);
40487 +
40488 + /* read back the message and ack the interrupt on behalf of WkupM3 */
40489 + rmsg = omap2_mbox_fifo_read(mbox);
40490 + wkupm3_mbox_ack_irq(mbox, IRQ_RX);
40491 +}
40492 +
40493 static struct omap_mbox_ops omap2_mbox_ops = {
40494 - .type = OMAP_MBOX_TYPE2,
40495 .startup = omap2_mbox_startup,
40496 .shutdown = omap2_mbox_shutdown,
40497 .fifo_read = omap2_mbox_fifo_read,
40498 .fifo_write = omap2_mbox_fifo_write,
40499 .fifo_empty = omap2_mbox_fifo_empty,
40500 - .fifo_full = omap2_mbox_fifo_full,
40501 + .poll_for_space = omap2_mbox_poll_for_space,
40502 .enable_irq = omap2_mbox_enable_irq,
40503 .disable_irq = omap2_mbox_disable_irq,
40504 .ack_irq = omap2_mbox_ack_irq,
40505 @@ -220,6 +297,36 @@ static struct omap_mbox_ops omap2_mbox_o
40506 .restore_ctx = omap2_mbox_restore_ctx,
40507 };
40508
40509 +static struct omap_mbox_ops wkupm3_mbox_ops = {
40510 + .startup = omap2_mbox_startup,
40511 + .shutdown = omap2_mbox_shutdown,
40512 + .fifo_read = omap2_mbox_fifo_read,
40513 + .fifo_write = wkupm3_mbox_send_data,
40514 + .fifo_empty = omap2_mbox_fifo_empty,
40515 + .poll_for_space = omap2_mbox_poll_for_space,
40516 + .enable_irq = wkupm3_mbox_enable_irq,
40517 + .disable_irq = wkupm3_mbox_disable_irq,
40518 + .ack_irq = wkupm3_mbox_ack_irq,
40519 + .is_irq = wkupm3_mbox_is_irq,
40520 + .save_ctx = omap2_mbox_save_ctx,
40521 + .restore_ctx = omap2_mbox_restore_ctx,
40522 +};
40523 +
40524 +static const struct of_device_id omap_mailbox_of_match[] = {
40525 + {
40526 + .compatible = "ti,omap2-mailbox",
40527 + .data = (void *) MBOX_INTR_CFG_TYPE1,
40528 + },
40529 + {
40530 + .compatible = "ti,omap4-mailbox",
40531 + .data = (void *) MBOX_INTR_CFG_TYPE2,
40532 + },
40533 + {
40534 + /* end */
40535 + },
40536 +};
40537 +MODULE_DEVICE_TABLE(of, omap_mailbox_of_match);
40538 +
40539 static int omap2_mbox_probe(struct platform_device *pdev)
40540 {
40541 struct resource *mem;
40542 @@ -227,40 +334,127 @@ static int omap2_mbox_probe(struct platf
40543 struct omap_mbox **list, *mbox, *mboxblk;
40544 struct omap_mbox2_priv *priv, *privblk;
40545 struct omap_mbox_pdata *pdata = pdev->dev.platform_data;
40546 - struct omap_mbox_dev_info *info;
40547 - int i;
40548 + struct omap_mbox_device *mdev;
40549 + struct omap_mbox_dev_info *info, *of_info = NULL;
40550 + struct device_node *node = pdev->dev.of_node;
40551 + int i, j;
40552 + u32 info_count = 0, intr_type = 0;
40553 + u32 num_users = 0, num_fifos = 0;
40554 + u32 dlen, dsize = 4;
40555 + u32 *tmp;
40556 + const __be32 *mbox_data;
40557
40558 - if (!pdata || !pdata->info_cnt || !pdata->info) {
40559 + if (!node && (!pdata || !pdata->info_cnt || !pdata->info)) {
40560 pr_err("%s: platform not supported\n", __func__);
40561 return -ENODEV;
40562 }
40563
40564 + if (node) {
40565 + intr_type = (u32)of_match_device(omap_mailbox_of_match,
40566 + &pdev->dev)->data;
40567 + if (intr_type != 0 && intr_type != 1) {
40568 + dev_err(&pdev->dev, "invalid match data value\n");
40569 + return -EINVAL;
40570 + }
40571 +
40572 + if (of_property_read_u32(node, "ti,mbox-num-users",
40573 + &num_users)) {
40574 + dev_err(&pdev->dev,
40575 + "no ti,mbox-num-users configuration found\n");
40576 + return -ENODEV;
40577 + }
40578 +
40579 + if (of_property_read_u32(node, "ti,mbox-num-fifos",
40580 + &num_fifos)) {
40581 + dev_err(&pdev->dev,
40582 + "no ti,mbox-num-fifos configuration found\n");
40583 + return -ENODEV;
40584 + }
40585 +
40586 + info_count = of_property_count_strings(node, "ti,mbox-names");
40587 + if (!info_count) {
40588 + dev_err(&pdev->dev, "no mbox devices found\n");
40589 + return -ENODEV;
40590 + }
40591 +
40592 + mbox_data = of_get_property(node, "ti,mbox-data", &dlen);
40593 + if (!mbox_data) {
40594 + dev_err(&pdev->dev, "no mbox device data found\n");
40595 + return -ENODEV;
40596 + }
40597 + dlen /= sizeof(dsize);
40598 + if (dlen != dsize * info_count) {
40599 + dev_err(&pdev->dev, "mbox device data is truncated\n");
40600 + return -ENODEV;
40601 + }
40602 +
40603 + of_info = kzalloc(info_count * sizeof(*of_info), GFP_KERNEL);
40604 + if (!of_info)
40605 + return -ENOMEM;
40606 +
40607 + i = 0;
40608 + while (i < info_count) {
40609 + info = of_info + i;
40610 + if (of_property_read_string_index(node,
40611 + "ti,mbox-names", i, &info->name)) {
40612 + dev_err(&pdev->dev,
40613 + "mbox_name [%d] read failed\n", i);
40614 + ret = -ENODEV;
40615 + goto free_of;
40616 + }
40617 +
40618 + tmp = &info->tx_id;
40619 + for (j = 0; j < dsize; j++) {
40620 + tmp[j] = of_read_number(
40621 + mbox_data + j + (i * dsize), 1);
40622 + }
40623 + i++;
40624 + }
40625 + }
40626 +
40627 + if (!node) { /* non-DT device creation */
40628 + info_count = pdata->info_cnt;
40629 + info = pdata->info;
40630 + intr_type = pdata->intr_type;
40631 + num_users = pdata->num_users;
40632 + num_fifos = pdata->num_fifos;
40633 + } else {
40634 + info = of_info;
40635 + }
40636 +
40637 + mdev = kzalloc(sizeof(*mdev), GFP_KERNEL);
40638 + if (!mdev) {
40639 + ret = -ENOMEM;
40640 + goto free_of;
40641 + }
40642 +
40643 /* allocate one extra for marking end of list */
40644 - list = kzalloc((pdata->info_cnt + 1) * sizeof(*list), GFP_KERNEL);
40645 - if (!list)
40646 - return -ENOMEM;
40647 + list = kzalloc((info_count + 1) * sizeof(*list), GFP_KERNEL);
40648 + if (!list) {
40649 + ret = -ENOMEM;
40650 + goto free_mdev;
40651 + }
40652
40653 - mboxblk = mbox = kzalloc(pdata->info_cnt * sizeof(*mbox), GFP_KERNEL);
40654 + mboxblk = mbox = kzalloc(info_count * sizeof(*mbox), GFP_KERNEL);
40655 if (!mboxblk) {
40656 ret = -ENOMEM;
40657 goto free_list;
40658 }
40659
40660 - privblk = priv = kzalloc(pdata->info_cnt * sizeof(*priv), GFP_KERNEL);
40661 + privblk = priv = kzalloc(info_count * sizeof(*priv), GFP_KERNEL);
40662 if (!privblk) {
40663 ret = -ENOMEM;
40664 goto free_mboxblk;
40665 }
40666
40667 - info = pdata->info;
40668 - for (i = 0; i < pdata->info_cnt; i++, info++, priv++) {
40669 + for (i = 0; i < info_count; i++, info++, priv++) {
40670 priv->tx_fifo.msg = MAILBOX_MESSAGE(info->tx_id);
40671 priv->tx_fifo.fifo_stat = MAILBOX_FIFOSTATUS(info->tx_id);
40672 priv->rx_fifo.msg = MAILBOX_MESSAGE(info->rx_id);
40673 priv->rx_fifo.msg_stat = MAILBOX_MSGSTATUS(info->rx_id);
40674 priv->notfull_bit = MAILBOX_IRQ_NOTFULL(info->tx_id);
40675 priv->newmsg_bit = MAILBOX_IRQ_NEWMSG(info->rx_id);
40676 - if (pdata->intr_type) {
40677 + if (intr_type) {
40678 priv->irqenable = OMAP4_MAILBOX_IRQENABLE(info->usr_id);
40679 priv->irqstatus = OMAP4_MAILBOX_IRQSTATUS(info->usr_id);
40680 priv->irqdisable =
40681 @@ -270,11 +464,15 @@ static int omap2_mbox_probe(struct platf
40682 priv->irqstatus = MAILBOX_IRQSTATUS(info->usr_id);
40683 priv->irqdisable = MAILBOX_IRQENABLE(info->usr_id);
40684 }
40685 - priv->intr_type = pdata->intr_type;
40686 + priv->intr_type = intr_type;
40687
40688 mbox->priv = priv;
40689 + mbox->parent = mdev;
40690 mbox->name = info->name;
40691 - mbox->ops = &omap2_mbox_ops;
40692 + if (!strcmp(mbox->name, "wkup_m3"))
40693 + mbox->ops = &wkupm3_mbox_ops;
40694 + else
40695 + mbox->ops = &omap2_mbox_ops;
40696 mbox->irq = platform_get_irq(pdev, info->irq_id);
40697 if (mbox->irq < 0) {
40698 ret = mbox->irq;
40699 @@ -289,42 +487,58 @@ static int omap2_mbox_probe(struct platf
40700 goto free_privblk;
40701 }
40702
40703 - mbox_base = ioremap(mem->start, resource_size(mem));
40704 - if (!mbox_base) {
40705 + mdev->mbox_base = ioremap(mem->start, resource_size(mem));
40706 + if (!mdev->mbox_base) {
40707 ret = -ENOMEM;
40708 goto free_privblk;
40709 }
40710
40711 - ret = omap_mbox_register(&pdev->dev, list);
40712 + mutex_init(&mdev->cfg_lock);
40713 + mdev->dev = &pdev->dev;
40714 + mdev->num_users = num_users;
40715 + mdev->num_fifos = num_fifos;
40716 + mdev->mboxes = list;
40717 + ret = omap_mbox_register(mdev);
40718 if (ret)
40719 goto unmap_mbox;
40720 - platform_set_drvdata(pdev, list);
40721 + platform_set_drvdata(pdev, mdev);
40722
40723 + pm_runtime_enable(mdev->dev);
40724 +
40725 + kfree(of_info);
40726 return 0;
40727
40728 unmap_mbox:
40729 - iounmap(mbox_base);
40730 + iounmap(mdev->mbox_base);
40731 free_privblk:
40732 kfree(privblk);
40733 free_mboxblk:
40734 kfree(mboxblk);
40735 free_list:
40736 kfree(list);
40737 +free_mdev:
40738 + kfree(mdev);
40739 +free_of:
40740 + kfree(of_info);
40741 return ret;
40742 }
40743
40744 static int omap2_mbox_remove(struct platform_device *pdev)
40745 {
40746 struct omap_mbox2_priv *privblk;
40747 - struct omap_mbox **list = platform_get_drvdata(pdev);
40748 + struct omap_mbox_device *mdev = platform_get_drvdata(pdev);
40749 + struct omap_mbox **list = mdev->mboxes;
40750 struct omap_mbox *mboxblk = list[0];
40751
40752 + pm_runtime_disable(mdev->dev);
40753 +
40754 privblk = mboxblk->priv;
40755 - omap_mbox_unregister();
40756 - iounmap(mbox_base);
40757 + omap_mbox_unregister(mdev);
40758 + iounmap(mdev->mbox_base);
40759 kfree(privblk);
40760 kfree(mboxblk);
40761 kfree(list);
40762 + kfree(mdev);
40763
40764 return 0;
40765 }
40766 @@ -334,6 +548,7 @@ static struct platform_driver omap2_mbox
40767 .remove = omap2_mbox_remove,
40768 .driver = {
40769 .name = "omap-mailbox",
40770 + .of_match_table = omap_mailbox_of_match,
40771 },
40772 };
40773
40774 --- a/drivers/mailbox/omap-mailbox.c
40775 +++ b/drivers/mailbox/omap-mailbox.c
40776 @@ -24,7 +24,6 @@
40777 #include <linux/interrupt.h>
40778 #include <linux/spinlock.h>
40779 #include <linux/mutex.h>
40780 -#include <linux/delay.h>
40781 #include <linux/slab.h>
40782 #include <linux/kfifo.h>
40783 #include <linux/err.h>
40784 @@ -33,16 +32,16 @@
40785
40786 #include "omap-mbox.h"
40787
40788 -static struct omap_mbox **mboxes;
40789 -
40790 -static int mbox_configured;
40791 -static DEFINE_MUTEX(mbox_configured_lock);
40792 +/* global variables for the mailbox devices */
40793 +static DEFINE_MUTEX(omap_mbox_devices_lock);
40794 +static LIST_HEAD(omap_mbox_devices);
40795
40796 +/* default size for the fifos, configured through kernel menuconfig */
40797 static unsigned int mbox_kfifo_size = CONFIG_OMAP_MBOX_KFIFO_SIZE;
40798 module_param(mbox_kfifo_size, uint, S_IRUGO);
40799 MODULE_PARM_DESC(mbox_kfifo_size, "Size of omap's mailbox kfifo (bytes)");
40800
40801 -/* Mailbox FIFO handle functions */
40802 +/* mailbox h/w transport communication handler helper functions */
40803 static inline mbox_msg_t mbox_fifo_read(struct omap_mbox *mbox)
40804 {
40805 return mbox->ops->fifo_read(mbox);
40806 @@ -55,12 +54,16 @@ static inline int mbox_fifo_empty(struct
40807 {
40808 return mbox->ops->fifo_empty(mbox);
40809 }
40810 -static inline int mbox_fifo_full(struct omap_mbox *mbox)
40811 +/*
40812 + * local helper to check if the h/w transport is busy or free.
40813 + * Returns 0 if free, and non-zero otherwise
40814 + */
40815 +static inline int mbox_poll_for_space(struct omap_mbox *mbox)
40816 {
40817 - return mbox->ops->fifo_full(mbox);
40818 + return mbox->ops->poll_for_space(mbox);
40819 }
40820
40821 -/* Mailbox IRQ handle functions */
40822 +/* mailbox h/w irq handler helper functions */
40823 static inline void ack_mbox_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
40824 {
40825 if (mbox->ops->ack_irq)
40826 @@ -71,23 +74,21 @@ static inline int is_mbox_irq(struct oma
40827 return mbox->ops->is_irq(mbox, irq);
40828 }
40829
40830 -/*
40831 - * message sender
40832 +/**
40833 + * omap_mbox_msg_send() - send a mailbox message
40834 + * @mbox: handle to the acquired mailbox on which to send the message
40835 + * @msg: the mailbox message to be sent
40836 + *
40837 + * This API is called by a client user to send a mailbox message on an
40838 + * acquired mailbox. The API transmits the message immediately on the h/w
40839 + * communication transport if it is available, otherwise buffers the
40840 + * message for transmission as soon as the h/w transport is ready.
40841 + *
40842 + * The only failure from this function is when neither the h/w transport
40843 + * is available nor the s/w buffer fifo is empty.
40844 + *
40845 + * Returns 0 on success, or an error otherwise
40846 */
40847 -static int __mbox_poll_for_space(struct omap_mbox *mbox)
40848 -{
40849 - int ret = 0, i = 1000;
40850 -
40851 - while (mbox_fifo_full(mbox)) {
40852 - if (mbox->ops->type == OMAP_MBOX_TYPE2)
40853 - return -1;
40854 - if (--i == 0)
40855 - return -1;
40856 - udelay(1);
40857 - }
40858 - return ret;
40859 -}
40860 -
40861 int omap_mbox_msg_send(struct omap_mbox *mbox, mbox_msg_t msg)
40862 {
40863 struct omap_mbox_queue *mq = mbox->txq;
40864 @@ -100,7 +101,7 @@ int omap_mbox_msg_send(struct omap_mbox
40865 goto out;
40866 }
40867
40868 - if (kfifo_is_empty(&mq->fifo) && !__mbox_poll_for_space(mbox)) {
40869 + if (kfifo_is_empty(&mq->fifo) && !mbox_poll_for_space(mbox)) {
40870 mbox_fifo_write(mbox, msg);
40871 goto out;
40872 }
40873 @@ -116,6 +117,17 @@ out:
40874 }
40875 EXPORT_SYMBOL(omap_mbox_msg_send);
40876
40877 +/**
40878 + * omap_mbox_save_ctx: save the context of a mailbox
40879 + * @mbox: handle to the acquired mailbox
40880 + *
40881 + * This allows a client (controlling a remote) to request a mailbox to
40882 + * save its context when it is powering down the remote.
40883 + *
40884 + * NOTE: This will be eventually deprecated, new clients should not use this.
40885 + * The same feature can be enabled through runtime_pm enablement of
40886 + * mailbox.
40887 + */
40888 void omap_mbox_save_ctx(struct omap_mbox *mbox)
40889 {
40890 if (!mbox->ops->save_ctx) {
40891 @@ -127,6 +139,18 @@ void omap_mbox_save_ctx(struct omap_mbox
40892 }
40893 EXPORT_SYMBOL(omap_mbox_save_ctx);
40894
40895 +/**
40896 + * omap_mbox_restore_ctx: restore the context of a mailbox
40897 + * @mbox: handle to the acquired mailbox
40898 + *
40899 + * This allows a client (controlling a remote) to request a mailbox to
40900 + * restore its context after restoring the remote, so that it can
40901 + * communicate with the remote as it would normally.
40902 + *
40903 + * NOTE: This will be deprecated, new clients should not use this.
40904 + * The same feature can be enabled through runtime_pm enablement
40905 + * of mailbox.
40906 + */
40907 void omap_mbox_restore_ctx(struct omap_mbox *mbox)
40908 {
40909 if (!mbox->ops->restore_ctx) {
40910 @@ -138,18 +162,48 @@ void omap_mbox_restore_ctx(struct omap_m
40911 }
40912 EXPORT_SYMBOL(omap_mbox_restore_ctx);
40913
40914 +/**
40915 + * omap_mbox_enable_irq: enable a specific mailbox Rx or Tx interrupt source
40916 + * @mbox: handle to the acquired mailbox
40917 + * @irq: interrupt type associated with either the Rx or Tx
40918 + *
40919 + * This allows a client (having its own shared memory communication protocol
40920 + * with the remote) to request a mailbox to enable a particular interrupt
40921 + * signal source of the mailbox, as part of its communication state machine.
40922 + *
40923 + * NOTE: This will be deprecated, new clients should not use this. It is
40924 + * being exported for TI DSP/Bridge driver.
40925 + */
40926 void omap_mbox_enable_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
40927 {
40928 mbox->ops->enable_irq(mbox, irq);
40929 }
40930 EXPORT_SYMBOL(omap_mbox_enable_irq);
40931
40932 +/**
40933 + * omap_mbox_disable_irq: disable a specific mailbox Rx or Tx interrupt source
40934 + * @mbox: handle to the acquired mailbox
40935 + * @irq: interrupt type associated with either the Rx or Tx
40936 + *
40937 + * This allows a client (having its own shared memory communication protocal
40938 + * with the remote) to request a mailbox to disable a particular interrupt
40939 + * signal source of the mailbox, as part of its communication state machine.
40940 + *
40941 + * NOTE: This will be deprecated, new clients should not use this. It is
40942 + * being exported for TI DSP/Bridge driver.
40943 + */
40944 void omap_mbox_disable_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
40945 {
40946 mbox->ops->disable_irq(mbox, irq);
40947 }
40948 EXPORT_SYMBOL(omap_mbox_disable_irq);
40949
40950 +/*
40951 + * This is the tasklet function in which all the buffered messages are
40952 + * sent until the h/w transport is busy again. The tasklet is scheduled
40953 + * upon receiving an interrupt indicating the availability of the h/w
40954 + * transport.
40955 + */
40956 static void mbox_tx_tasklet(unsigned long tx_data)
40957 {
40958 struct omap_mbox *mbox = (struct omap_mbox *)tx_data;
40959 @@ -158,7 +212,7 @@ static void mbox_tx_tasklet(unsigned lon
40960 int ret;
40961
40962 while (kfifo_len(&mq->fifo)) {
40963 - if (__mbox_poll_for_space(mbox)) {
40964 + if (mbox_poll_for_space(mbox)) {
40965 omap_mbox_enable_irq(mbox, IRQ_TX);
40966 break;
40967 }
40968 @@ -172,7 +226,12 @@ static void mbox_tx_tasklet(unsigned lon
40969 }
40970
40971 /*
40972 - * Message receiver(workqueue)
40973 + * This is the message receiver workqueue function, which is responsible
40974 + * for delivering all the received messages stored in the receive kfifo
40975 + * to the clients. Each message is delivered to all the registered mailbox
40976 + * clients. It also re-enables the receive interrupt on the mailbox (disabled
40977 + * when the s/w kfifo is full) after emptying atleast a message from the
40978 + * fifo.
40979 */
40980 static void mbox_rx_work(struct work_struct *work)
40981 {
40982 @@ -197,7 +256,9 @@ static void mbox_rx_work(struct work_str
40983 }
40984
40985 /*
40986 - * Mailbox interrupt handler
40987 + * Interrupt handler for Tx interrupt source for each of the mailboxes.
40988 + * This schedules the tasklet to transmit the messages buffered in the
40989 + * Tx fifo.
40990 */
40991 static void __mbox_tx_interrupt(struct omap_mbox *mbox)
40992 {
40993 @@ -206,6 +267,12 @@ static void __mbox_tx_interrupt(struct o
40994 tasklet_schedule(&mbox->txq->tasklet);
40995 }
40996
40997 +/*
40998 + * Interrupt handler for Rx interrupt source for each of the mailboxes.
40999 + * This performs the read from the h/w mailbox until the transport is
41000 + * free of any incoming messages, and buffers the read message. The
41001 + * buffers are delivered to clients by scheduling a work-queue.
41002 + */
41003 static void __mbox_rx_interrupt(struct omap_mbox *mbox)
41004 {
41005 struct omap_mbox_queue *mq = mbox->rxq;
41006 @@ -223,9 +290,6 @@ static void __mbox_rx_interrupt(struct o
41007
41008 len = kfifo_in(&mq->fifo, (unsigned char *)&msg, sizeof(msg));
41009 WARN_ON(len != sizeof(msg));
41010 -
41011 - if (mbox->ops->type == OMAP_MBOX_TYPE1)
41012 - break;
41013 }
41014
41015 /* no more messages in the fifo. clear IRQ source. */
41016 @@ -234,6 +298,10 @@ nomem:
41017 schedule_work(&mbox->rxq->work);
41018 }
41019
41020 +/*
41021 + * The core mailbox interrupt handler function. The interrupt core would
41022 + * call this for each of the mailboxes the interrupt is configured.
41023 + */
41024 static irqreturn_t mbox_interrupt(int irq, void *p)
41025 {
41026 struct omap_mbox *mbox = p;
41027 @@ -247,6 +315,12 @@ static irqreturn_t mbox_interrupt(int ir
41028 return IRQ_HANDLED;
41029 }
41030
41031 +/*
41032 + * Helper function to allocate a mailbox queue object. This function
41033 + * also creates either or both of the work-queue or tasklet to
41034 + * deal with processing of messages on the kfifo associated with
41035 + * the mailbox queue object.
41036 + */
41037 static struct omap_mbox_queue *mbox_queue_alloc(struct omap_mbox *mbox,
41038 void (*work) (struct work_struct *),
41039 void (*tasklet)(unsigned long))
41040 @@ -273,24 +347,31 @@ error:
41041 return NULL;
41042 }
41043
41044 +/*
41045 + * Helper function to free a mailbox queue object.
41046 + */
41047 static void mbox_queue_free(struct omap_mbox_queue *q)
41048 {
41049 kfifo_free(&q->fifo);
41050 kfree(q);
41051 }
41052
41053 +/*
41054 + * Helper function to initialize a mailbox. This function creates
41055 + * the mailbox queue objects associated with the mailbox h/w channel
41056 + * and plugs-in the interrupt associated with the mailbox, when the
41057 + * mailbox h/w channel is requested for the first time.
41058 + */
41059 static int omap_mbox_startup(struct omap_mbox *mbox)
41060 {
41061 int ret = 0;
41062 struct omap_mbox_queue *mq;
41063 + struct omap_mbox_device *mdev = mbox->parent;
41064
41065 - mutex_lock(&mbox_configured_lock);
41066 - if (!mbox_configured++) {
41067 - if (likely(mbox->ops->startup)) {
41068 - ret = mbox->ops->startup(mbox);
41069 - if (unlikely(ret))
41070 - goto fail_startup;
41071 - } else
41072 + mutex_lock(&mdev->cfg_lock);
41073 + if (mbox->ops->startup) {
41074 + ret = mbox->ops->startup(mbox);
41075 + if (ret)
41076 goto fail_startup;
41077 }
41078
41079 @@ -319,7 +400,7 @@ static int omap_mbox_startup(struct omap
41080
41081 omap_mbox_enable_irq(mbox, IRQ_RX);
41082 }
41083 - mutex_unlock(&mbox_configured_lock);
41084 + mutex_unlock(&mdev->cfg_lock);
41085 return 0;
41086
41087 fail_request_irq:
41088 @@ -331,14 +412,18 @@ fail_alloc_txq:
41089 mbox->ops->shutdown(mbox);
41090 mbox->use_count--;
41091 fail_startup:
41092 - mbox_configured--;
41093 - mutex_unlock(&mbox_configured_lock);
41094 + mutex_unlock(&mdev->cfg_lock);
41095 return ret;
41096 }
41097
41098 +/*
41099 + * Helper function to de-initialize a mailbox
41100 + */
41101 static void omap_mbox_fini(struct omap_mbox *mbox)
41102 {
41103 - mutex_lock(&mbox_configured_lock);
41104 + struct omap_mbox_device *mdev = mbox->parent;
41105 +
41106 + mutex_lock(&mdev->cfg_lock);
41107
41108 if (!--mbox->use_count) {
41109 omap_mbox_disable_irq(mbox, IRQ_RX);
41110 @@ -349,28 +434,66 @@ static void omap_mbox_fini(struct omap_m
41111 mbox_queue_free(mbox->rxq);
41112 }
41113
41114 - if (likely(mbox->ops->shutdown)) {
41115 - if (!--mbox_configured)
41116 - mbox->ops->shutdown(mbox);
41117 - }
41118 + if (mbox->ops->shutdown)
41119 + mbox->ops->shutdown(mbox);
41120
41121 - mutex_unlock(&mbox_configured_lock);
41122 + mutex_unlock(&mdev->cfg_lock);
41123 }
41124
41125 -struct omap_mbox *omap_mbox_get(const char *name, struct notifier_block *nb)
41126 +/*
41127 + * Helper function to find a mailbox. It is currently assumed that all the
41128 + * mailbox names are unique among all the mailbox devices. This can be
41129 + * easily extended if only a particular mailbox device is to searched.
41130 + */
41131 +static struct omap_mbox *omap_mbox_device_find(struct omap_mbox_device *mdev,
41132 + const char *mbox_name)
41133 {
41134 struct omap_mbox *_mbox, *mbox = NULL;
41135 - int i, ret;
41136 + struct omap_mbox **mboxes = mdev->mboxes;
41137 + int i;
41138
41139 if (!mboxes)
41140 - return ERR_PTR(-EINVAL);
41141 + return NULL;
41142
41143 for (i = 0; (_mbox = mboxes[i]); i++) {
41144 - if (!strcmp(_mbox->name, name)) {
41145 + if (!strcmp(_mbox->name, mbox_name)) {
41146 mbox = _mbox;
41147 break;
41148 }
41149 }
41150 + return mbox;
41151 +}
41152 +
41153 +/**
41154 + * omap_mbox_get() - acquire a mailbox
41155 + * @name: name of the mailbox to acquire
41156 + * @nb: notifier block to be invoked on received messages
41157 + *
41158 + * This API is called by a client user to use a mailbox. The returned handle
41159 + * needs to be used by the client for invoking any other mailbox API. Any
41160 + * message received on the mailbox is delivered to the client through the
41161 + * 'nb' notifier. There are currently no restrictions on multiple clients
41162 + * acquiring the same mailbox - the same message is delivered to each of the
41163 + * clients through their respective notifiers.
41164 + *
41165 + * The function ensures that the mailbox is put into an operational state
41166 + * before the function returns.
41167 + *
41168 + * Returns a usable mailbox handle on success, or NULL otherwise
41169 + */
41170 +struct omap_mbox *omap_mbox_get(const char *name, struct notifier_block *nb)
41171 +{
41172 + struct omap_mbox *mbox = NULL;
41173 + struct omap_mbox_device *mdev;
41174 + int ret;
41175 +
41176 + mutex_lock(&omap_mbox_devices_lock);
41177 + list_for_each_entry(mdev, &omap_mbox_devices, elem) {
41178 + mbox = omap_mbox_device_find(mdev, name);
41179 + if (mbox)
41180 + break;
41181 + }
41182 + mutex_unlock(&omap_mbox_devices_lock);
41183
41184 if (!mbox)
41185 return ERR_PTR(-ENOENT);
41186 @@ -388,6 +511,18 @@ struct omap_mbox *omap_mbox_get(const ch
41187 }
41188 EXPORT_SYMBOL(omap_mbox_get);
41189
41190 +/**
41191 + * omap_mbox_put() - release a mailbox
41192 + * @mbox: handle to the acquired mailbox
41193 + * @nb: notifier block used while acquiring the mailbox
41194 + *
41195 + * This API is to be called by a client user once it is done using the
41196 + * mailbox. The particular user's notifier function is removed from the
41197 + * notifier list of received messages on this mailbox. It also undoes
41198 + * any h/w configuration done during the acquisition of the mailbox.
41199 + *
41200 + * No return value
41201 + */
41202 void omap_mbox_put(struct omap_mbox *mbox, struct notifier_block *nb)
41203 {
41204 blocking_notifier_chain_unregister(&mbox->notifier, nb);
41205 @@ -397,19 +532,35 @@ EXPORT_SYMBOL(omap_mbox_put);
41206
41207 static struct class omap_mbox_class = { .name = "mbox", };
41208
41209 -int omap_mbox_register(struct device *parent, struct omap_mbox **list)
41210 +/**
41211 + * omap_mbox_register() - register the list of mailboxes
41212 + * @mdev: mailbox device handle containing the mailboxes that need to be
41213 + * with the mailbox core
41214 + *
41215 + * This API is to be called by individual mailbox driver implementations
41216 + * for registering the set of mailboxes contained in a h/w communication
41217 + * block with the mailbox core. Each of the mailbox represents a h/w
41218 + * communication channel, contained within the h/w communication block or ip.
41219 + *
41220 + * An associated device is also created for each of the mailboxes, and the
41221 + * mailbox device is added to a global list of registered mailbox devices.
41222 + *
41223 + * Return 0 on success, or a failure code otherwise
41224 + */
41225 +int omap_mbox_register(struct omap_mbox_device *mdev)
41226 {
41227 int ret;
41228 int i;
41229 + struct omap_mbox **mboxes;
41230
41231 - mboxes = list;
41232 - if (!mboxes)
41233 + if (!mdev || !mdev->mboxes)
41234 return -EINVAL;
41235
41236 + mboxes = mdev->mboxes;
41237 for (i = 0; mboxes[i]; i++) {
41238 struct omap_mbox *mbox = mboxes[i];
41239 mbox->dev = device_create(&omap_mbox_class,
41240 - parent, 0, mbox, "%s", mbox->name);
41241 + mdev->dev, 0, mbox, "%s", mbox->name);
41242 if (IS_ERR(mbox->dev)) {
41243 ret = PTR_ERR(mbox->dev);
41244 goto err_out;
41245 @@ -417,6 +568,11 @@ int omap_mbox_register(struct device *pa
41246
41247 BLOCKING_INIT_NOTIFIER_HEAD(&mbox->notifier);
41248 }
41249 +
41250 + mutex_lock(&omap_mbox_devices_lock);
41251 + list_add(&mdev->elem, &omap_mbox_devices);
41252 + mutex_unlock(&omap_mbox_devices_lock);
41253 +
41254 return 0;
41255
41256 err_out:
41257 @@ -426,16 +582,33 @@ err_out:
41258 }
41259 EXPORT_SYMBOL(omap_mbox_register);
41260
41261 -int omap_mbox_unregister(void)
41262 +/**
41263 + * omap_mbox_unregister() - unregister the list of mailboxes
41264 + * @mdev: parent mailbox device handle containing the mailboxes that need
41265 + * to be unregistered
41266 + *
41267 + * This API is to be called by individual mailbox driver implementations
41268 + * for unregistering the set of mailboxes contained in a h/w communication
41269 + * block. Once unregistered, these mailboxes are not available for any
41270 + * client users/drivers.
41271 + *
41272 + * Return 0 on success, or a failure code otherwise
41273 + */
41274 +int omap_mbox_unregister(struct omap_mbox_device *mdev)
41275 {
41276 int i;
41277 + struct omap_mbox **mboxes;
41278
41279 - if (!mboxes)
41280 + if (!mdev || !mdev->mboxes)
41281 return -EINVAL;
41282
41283 + mutex_lock(&omap_mbox_devices_lock);
41284 + list_del(&mdev->elem);
41285 + mutex_unlock(&omap_mbox_devices_lock);
41286 +
41287 + mboxes = mdev->mboxes;
41288 for (i = 0; mboxes[i]; i++)
41289 device_unregister(mboxes[i]->dev);
41290 - mboxes = NULL;
41291 return 0;
41292 }
41293 EXPORT_SYMBOL(omap_mbox_unregister);
41294 --- a/drivers/mailbox/omap-mbox.h
41295 +++ b/drivers/mailbox/omap-mbox.h
41296 @@ -16,19 +16,58 @@
41297 #include <linux/workqueue.h>
41298 #include <linux/omap-mailbox.h>
41299
41300 -typedef int __bitwise omap_mbox_type_t;
41301 -#define OMAP_MBOX_TYPE1 ((__force omap_mbox_type_t) 1)
41302 -#define OMAP_MBOX_TYPE2 ((__force omap_mbox_type_t) 2)
41303 -
41304 +/**
41305 + * struct omap_mbox_ops - function ops specific to a mailbox implementation
41306 + * @startup: the startup function, essential for making the mailbox active.
41307 + * This will be called when a client acquires the mailbox. The driver
41308 + * implementation needs to take care of any refcounting if the same
41309 + * mailbox is requested by multiple clients.
41310 + * @shutdown: the shutdown function, essential for making the mailbox inactive
41311 + * after usage. This will be called when a client releases the
41312 + * mailbox. The driver implementation needs to take care of any
41313 + * refcounting if the same mailbox is requested by multiple clients.
41314 + * @fifo_read: read and return the h/w transport payload message. This hook
41315 + * provides the omap mailbox core to read all the available messages
41316 + * upon a Rx interrupt and buffer them. The messages are delivered
41317 + * to the clients in a workqueue.
41318 + * @fifo_write: send a mailbox message packet on the h/w transport channel. The
41319 + * individual drivers are responsible for configuring the h/w
41320 + * accordingly.
41321 + * @fifo_empty: check if the h/w Rx transport has more messages. The function
41322 + * should return 0 if there are no more messages to be read from
41323 + * the transport, and non-zero if there are available messages.
41324 + * @poll_for_space: check if the h/w Tx transport is busy. This hook should
41325 + * return non-zero if the h/w Tx transport is busy, and 0 when
41326 + * the h/w communication channel is free.
41327 + * @enable_irq: This hook allows the mailbox core to allow a specific Rx or Tx
41328 + * interrupt signal to interrupt the processor, based on its state
41329 + * machine.
41330 + * @disable_irq: This hooks allows the mailbox core to disable a specific Rx or
41331 + * Tx interrupt signal from interrupting the processor, based on
41332 + * its state machine.
41333 + * @ack_irq: acknowledge the Tx or Rx interrupt signal internal to the mailbox.
41334 + * This allows the h/w communication block to clear any internal
41335 + * interrupt source status registers.
41336 + * @is_irq: check if a particular Tx or Rx interrupt signal on the corresponding
41337 + * mailbox is set. This hook is used by the mailbox core to process the
41338 + * interrupt accordingly.
41339 + * @save_ctx: Called by a client or the mailbox core to allow the individual
41340 + * driver implementation to save the context of the mailbox registers
41341 + * before the domain containing the h/w communication block can be
41342 + * put into a low-power state.
41343 + * @restore_ctx: Called by a client or the mailbox core to allow the individual
41344 + * driver implementation to restore the context of the mailbox
41345 + * registers after the domain containing the h/w communication block
41346 + * is powered back to active state.
41347 + */
41348 struct omap_mbox_ops {
41349 - omap_mbox_type_t type;
41350 int (*startup)(struct omap_mbox *mbox);
41351 void (*shutdown)(struct omap_mbox *mbox);
41352 - /* fifo */
41353 + /* mailbox access */
41354 mbox_msg_t (*fifo_read)(struct omap_mbox *mbox);
41355 void (*fifo_write)(struct omap_mbox *mbox, mbox_msg_t msg);
41356 int (*fifo_empty)(struct omap_mbox *mbox);
41357 - int (*fifo_full)(struct omap_mbox *mbox);
41358 + int (*poll_for_space)(struct omap_mbox *mbox);
41359 /* irq */
41360 void (*enable_irq)(struct omap_mbox *mbox,
41361 omap_mbox_irq_t irq);
41362 @@ -36,11 +75,28 @@ struct omap_mbox_ops {
41363 omap_mbox_irq_t irq);
41364 void (*ack_irq)(struct omap_mbox *mbox, omap_mbox_irq_t irq);
41365 int (*is_irq)(struct omap_mbox *mbox, omap_mbox_irq_t irq);
41366 - /* ctx */
41367 + /* context */
41368 void (*save_ctx)(struct omap_mbox *mbox);
41369 void (*restore_ctx)(struct omap_mbox *mbox);
41370 };
41371
41372 +/**
41373 + * struct omap_mbox_queue - A queue object used for buffering messages
41374 + * @lock: a spinlock providing synchronization in atomic context
41375 + * @fifo: a kfifo object for buffering the messages. The size of the kfifo is
41376 + * is currently configured either at build time using kernel menu
41377 + * configuration or at runtime through a module parameter. The usage of
41378 + * the kfifo depends on whether the queue object is for Rx or Tx. For Tx,
41379 + * a message is buffered into the kfifo if the h/w transport is busy, and
41380 + * is taken out when the h/w signals Tx readiness. For Rx, the messages
41381 + * are buffered into the kfifo in the bottom-half processing of a Rx
41382 + * interrupt, and taken out during the top-half processing.
41383 + * @work: a workqueue object for scheduling top-half processing of rx messages
41384 + * @tasklet: a tasklet object for processing tx messages in an atomic context
41385 + * @mbox: reference to the containing parent mailbox
41386 + * full: indicates the status of the fifo, and is set to true when there is no
41387 + * room in the fifo.
41388 + */
41389 struct omap_mbox_queue {
41390 spinlock_t lock;
41391 struct kfifo fifo;
41392 @@ -50,18 +106,65 @@ struct omap_mbox_queue {
41393 bool full;
41394 };
41395
41396 +/**
41397 + * struct omap_mbox_device - device structure for storing h/w mailbox block
41398 + * @dev: reference device pointer of the h/w mailbox block
41399 + * @cfg_lock: a configuration mutex lock used for protecting the mailbox
41400 + * device configuration operations
41401 + * @mbox_base: ioremapped base address of the h/w mailbox block
41402 + * @num_users: number of output interrupts from the h/w mailbox block, multiple
41403 + * interrupts can be routed to a particular processor sub-system
41404 + * @num_fifos: number of individual h/w fifo queues supported within a h/w
41405 + * mailbox block
41406 + * @mboxes: array of containing mailboxes within the h/w mailbox block
41407 + * @elem: list node
41408 + */
41409 +struct omap_mbox_device {
41410 + struct device *dev;
41411 + struct mutex cfg_lock;
41412 + void __iomem *mbox_base;
41413 + u32 num_users;
41414 + u32 num_fifos;
41415 + struct omap_mbox **mboxes;
41416 + struct list_head elem;
41417 +};
41418 +
41419 +/**
41420 + * struct omap_mbox - the base object describing a h/w communication channel.
41421 + * there can be more than one object in a h/w communication block
41422 + * @name: a unique name for the mailbox object. Client users acquire a
41423 + * mailbox object using this name
41424 + * @irq: IRQ number that the mailbox uses to interrupt the host processor.
41425 + * the same IRQ number may be shared between different mailboxes
41426 + * @txq: the mailbox queue object pertaining to Tx
41427 + * @rxq: the mailbox queue object pertaining to Rx
41428 + * @ops: function ops specific to the mailbox
41429 + * @dev: the device pointer representing the mailbox object
41430 + * @parent: back reference to the containing parent mailbox device object
41431 + * @priv: a private structure specific to the driver implementation, this will
41432 + * not be touched by the mailbox core
41433 + * @use_count: number of current references to the mailbox, useful in
41434 + * controlling the mailbox state
41435 + * @notifier: notifier chain of clients, to which a received message is
41436 + * communicated
41437 + */
41438 struct omap_mbox {
41439 const char *name;
41440 unsigned int irq;
41441 struct omap_mbox_queue *txq, *rxq;
41442 struct omap_mbox_ops *ops;
41443 struct device *dev;
41444 + struct omap_mbox_device *parent;
41445 void *priv;
41446 int use_count;
41447 struct blocking_notifier_head notifier;
41448 };
41449
41450 -int omap_mbox_register(struct device *parent, struct omap_mbox **);
41451 -int omap_mbox_unregister(void);
41452 +/*
41453 + * mailbox objects registration and de-registration functions with the
41454 + * mailbox core.
41455 + */
41456 +int omap_mbox_register(struct omap_mbox_device *device);
41457 +int omap_mbox_unregister(struct omap_mbox_device *device);
41458
41459 #endif /* OMAP_MBOX_H */
41460 --- a/drivers/Makefile
41461 +++ b/drivers/Makefile
41462 @@ -8,6 +8,8 @@
41463 obj-y += irqchip/
41464 obj-y += bus/
41465
41466 +obj-$(CONFIG_GENERIC_PHY) += phy/
41467 +
41468 # GPIO must come after pinctrl as gpios may need to mux pins etc
41469 obj-y += pinctrl/
41470 obj-y += gpio/
41471 --- a/drivers/media/platform/Kconfig
41472 +++ b/drivers/media/platform/Kconfig
41473 @@ -220,6 +220,22 @@ config VIDEO_RENESAS_VSP1
41474 To compile this driver as a module, choose M here: the module
41475 will be called vsp1.
41476
41477 +config VIDEO_TI_VPE
41478 + tristate "TI VPE (Video Processing Engine) driver"
41479 + depends on VIDEO_DEV && VIDEO_V4L2 && SOC_DRA7XX
41480 + select VIDEOBUF2_DMA_CONTIG
41481 + select V4L2_MEM2MEM_DEV
41482 + default n
41483 + ---help---
41484 + Support for the TI VPE(Video Processing Engine) block
41485 + found on DRA7XX SoC.
41486 +
41487 +config VIDEO_TI_VPE_DEBUG
41488 + bool "VPE debug messages"
41489 + depends on VIDEO_TI_VPE
41490 + ---help---
41491 + Enable debug messages on VPE driver.
41492 +
41493 endif # V4L_MEM2MEM_DRIVERS
41494
41495 menuconfig V4L_TEST_DRIVERS
41496 --- a/drivers/media/platform/Makefile
41497 +++ b/drivers/media/platform/Makefile
41498 @@ -22,6 +22,8 @@ obj-$(CONFIG_VIDEO_VIVI) += vivi.o
41499
41500 obj-$(CONFIG_VIDEO_MEM2MEM_TESTDEV) += mem2mem_testdev.o
41501
41502 +obj-$(CONFIG_VIDEO_TI_VPE) += ti-vpe/
41503 +
41504 obj-$(CONFIG_VIDEO_MX2_EMMAPRP) += mx2_emmaprp.o
41505 obj-$(CONFIG_VIDEO_CODA) += coda.o
41506
41507 --- /dev/null
41508 +++ b/drivers/media/platform/ti-vpe/Makefile
41509 @@ -0,0 +1,5 @@
41510 +obj-$(CONFIG_VIDEO_TI_VPE) += ti-vpe.o
41511 +
41512 +ti-vpe-y := vpe.o vpdma.o
41513 +
41514 +ccflags-$(CONFIG_VIDEO_TI_VPE_DEBUG) += -DDEBUG
41515 --- /dev/null
41516 +++ b/drivers/media/platform/ti-vpe/vpdma.c
41517 @@ -0,0 +1,846 @@
41518 +/*
41519 + * VPDMA helper library
41520 + *
41521 + * Copyright (c) 2013 Texas Instruments Inc.
41522 + *
41523 + * David Griego, <dagriego@biglakesoftware.com>
41524 + * Dale Farnsworth, <dale@farnsworth.org>
41525 + * Archit Taneja, <archit@ti.com>
41526 + *
41527 + * This program is free software; you can redistribute it and/or modify it
41528 + * under the terms of the GNU General Public License version 2 as published by
41529 + * the Free Software Foundation.
41530 + */
41531 +
41532 +#include <linux/delay.h>
41533 +#include <linux/dma-mapping.h>
41534 +#include <linux/err.h>
41535 +#include <linux/firmware.h>
41536 +#include <linux/io.h>
41537 +#include <linux/module.h>
41538 +#include <linux/platform_device.h>
41539 +#include <linux/sched.h>
41540 +#include <linux/slab.h>
41541 +#include <linux/videodev2.h>
41542 +
41543 +#include "vpdma.h"
41544 +#include "vpdma_priv.h"
41545 +
41546 +#define VPDMA_FIRMWARE "vpdma-1b8.bin"
41547 +
41548 +const struct vpdma_data_format vpdma_yuv_fmts[] = {
41549 + [VPDMA_DATA_FMT_Y444] = {
41550 + .data_type = DATA_TYPE_Y444,
41551 + .depth = 8,
41552 + },
41553 + [VPDMA_DATA_FMT_Y422] = {
41554 + .data_type = DATA_TYPE_Y422,
41555 + .depth = 8,
41556 + },
41557 + [VPDMA_DATA_FMT_Y420] = {
41558 + .data_type = DATA_TYPE_Y420,
41559 + .depth = 8,
41560 + },
41561 + [VPDMA_DATA_FMT_C444] = {
41562 + .data_type = DATA_TYPE_C444,
41563 + .depth = 8,
41564 + },
41565 + [VPDMA_DATA_FMT_C422] = {
41566 + .data_type = DATA_TYPE_C422,
41567 + .depth = 8,
41568 + },
41569 + [VPDMA_DATA_FMT_C420] = {
41570 + .data_type = DATA_TYPE_C420,
41571 + .depth = 4,
41572 + },
41573 + [VPDMA_DATA_FMT_YC422] = {
41574 + .data_type = DATA_TYPE_YC422,
41575 + .depth = 16,
41576 + },
41577 + [VPDMA_DATA_FMT_YC444] = {
41578 + .data_type = DATA_TYPE_YC444,
41579 + .depth = 24,
41580 + },
41581 + [VPDMA_DATA_FMT_CY422] = {
41582 + .data_type = DATA_TYPE_CY422,
41583 + .depth = 16,
41584 + },
41585 +};
41586 +
41587 +const struct vpdma_data_format vpdma_rgb_fmts[] = {
41588 + [VPDMA_DATA_FMT_RGB565] = {
41589 + .data_type = DATA_TYPE_RGB16_565,
41590 + .depth = 16,
41591 + },
41592 + [VPDMA_DATA_FMT_ARGB16_1555] = {
41593 + .data_type = DATA_TYPE_ARGB_1555,
41594 + .depth = 16,
41595 + },
41596 + [VPDMA_DATA_FMT_ARGB16] = {
41597 + .data_type = DATA_TYPE_ARGB_4444,
41598 + .depth = 16,
41599 + },
41600 + [VPDMA_DATA_FMT_RGBA16_5551] = {
41601 + .data_type = DATA_TYPE_RGBA_5551,
41602 + .depth = 16,
41603 + },
41604 + [VPDMA_DATA_FMT_RGBA16] = {
41605 + .data_type = DATA_TYPE_RGBA_4444,
41606 + .depth = 16,
41607 + },
41608 + [VPDMA_DATA_FMT_ARGB24] = {
41609 + .data_type = DATA_TYPE_ARGB24_6666,
41610 + .depth = 24,
41611 + },
41612 + [VPDMA_DATA_FMT_RGB24] = {
41613 + .data_type = DATA_TYPE_RGB24_888,
41614 + .depth = 24,
41615 + },
41616 + [VPDMA_DATA_FMT_ARGB32] = {
41617 + .data_type = DATA_TYPE_ARGB32_8888,
41618 + .depth = 32,
41619 + },
41620 + [VPDMA_DATA_FMT_RGBA24] = {
41621 + .data_type = DATA_TYPE_RGBA24_6666,
41622 + .depth = 24,
41623 + },
41624 + [VPDMA_DATA_FMT_RGBA32] = {
41625 + .data_type = DATA_TYPE_RGBA32_8888,
41626 + .depth = 32,
41627 + },
41628 + [VPDMA_DATA_FMT_BGR565] = {
41629 + .data_type = DATA_TYPE_BGR16_565,
41630 + .depth = 16,
41631 + },
41632 + [VPDMA_DATA_FMT_ABGR16_1555] = {
41633 + .data_type = DATA_TYPE_ABGR_1555,
41634 + .depth = 16,
41635 + },
41636 + [VPDMA_DATA_FMT_ABGR16] = {
41637 + .data_type = DATA_TYPE_ABGR_4444,
41638 + .depth = 16,
41639 + },
41640 + [VPDMA_DATA_FMT_BGRA16_5551] = {
41641 + .data_type = DATA_TYPE_BGRA_5551,
41642 + .depth = 16,
41643 + },
41644 + [VPDMA_DATA_FMT_BGRA16] = {
41645 + .data_type = DATA_TYPE_BGRA_4444,
41646 + .depth = 16,
41647 + },
41648 + [VPDMA_DATA_FMT_ABGR24] = {
41649 + .data_type = DATA_TYPE_ABGR24_6666,
41650 + .depth = 24,
41651 + },
41652 + [VPDMA_DATA_FMT_BGR24] = {
41653 + .data_type = DATA_TYPE_BGR24_888,
41654 + .depth = 24,
41655 + },
41656 + [VPDMA_DATA_FMT_ABGR32] = {
41657 + .data_type = DATA_TYPE_ABGR32_8888,
41658 + .depth = 32,
41659 + },
41660 + [VPDMA_DATA_FMT_BGRA24] = {
41661 + .data_type = DATA_TYPE_BGRA24_6666,
41662 + .depth = 24,
41663 + },
41664 + [VPDMA_DATA_FMT_BGRA32] = {
41665 + .data_type = DATA_TYPE_BGRA32_8888,
41666 + .depth = 32,
41667 + },
41668 +};
41669 +
41670 +const struct vpdma_data_format vpdma_misc_fmts[] = {
41671 + [VPDMA_DATA_FMT_MV] = {
41672 + .data_type = DATA_TYPE_MV,
41673 + .depth = 4,
41674 + },
41675 +};
41676 +
41677 +struct vpdma_channel_info {
41678 + int num; /* VPDMA channel number */
41679 + int cstat_offset; /* client CSTAT register offset */
41680 +};
41681 +
41682 +static const struct vpdma_channel_info chan_info[] = {
41683 + [VPE_CHAN_LUMA1_IN] = {
41684 + .num = VPE_CHAN_NUM_LUMA1_IN,
41685 + .cstat_offset = VPDMA_DEI_LUMA1_CSTAT,
41686 + },
41687 + [VPE_CHAN_CHROMA1_IN] = {
41688 + .num = VPE_CHAN_NUM_CHROMA1_IN,
41689 + .cstat_offset = VPDMA_DEI_CHROMA1_CSTAT,
41690 + },
41691 + [VPE_CHAN_LUMA2_IN] = {
41692 + .num = VPE_CHAN_NUM_LUMA2_IN,
41693 + .cstat_offset = VPDMA_DEI_LUMA2_CSTAT,
41694 + },
41695 + [VPE_CHAN_CHROMA2_IN] = {
41696 + .num = VPE_CHAN_NUM_CHROMA2_IN,
41697 + .cstat_offset = VPDMA_DEI_CHROMA2_CSTAT,
41698 + },
41699 + [VPE_CHAN_LUMA3_IN] = {
41700 + .num = VPE_CHAN_NUM_LUMA3_IN,
41701 + .cstat_offset = VPDMA_DEI_LUMA3_CSTAT,
41702 + },
41703 + [VPE_CHAN_CHROMA3_IN] = {
41704 + .num = VPE_CHAN_NUM_CHROMA3_IN,
41705 + .cstat_offset = VPDMA_DEI_CHROMA3_CSTAT,
41706 + },
41707 + [VPE_CHAN_MV_IN] = {
41708 + .num = VPE_CHAN_NUM_MV_IN,
41709 + .cstat_offset = VPDMA_DEI_MV_IN_CSTAT,
41710 + },
41711 + [VPE_CHAN_MV_OUT] = {
41712 + .num = VPE_CHAN_NUM_MV_OUT,
41713 + .cstat_offset = VPDMA_DEI_MV_OUT_CSTAT,
41714 + },
41715 + [VPE_CHAN_LUMA_OUT] = {
41716 + .num = VPE_CHAN_NUM_LUMA_OUT,
41717 + .cstat_offset = VPDMA_VIP_UP_Y_CSTAT,
41718 + },
41719 + [VPE_CHAN_CHROMA_OUT] = {
41720 + .num = VPE_CHAN_NUM_CHROMA_OUT,
41721 + .cstat_offset = VPDMA_VIP_UP_UV_CSTAT,
41722 + },
41723 + [VPE_CHAN_RGB_OUT] = {
41724 + .num = VPE_CHAN_NUM_RGB_OUT,
41725 + .cstat_offset = VPDMA_VIP_UP_Y_CSTAT,
41726 + },
41727 +};
41728 +
41729 +static u32 read_reg(struct vpdma_data *vpdma, int offset)
41730 +{
41731 + return ioread32(vpdma->base + offset);
41732 +}
41733 +
41734 +static void write_reg(struct vpdma_data *vpdma, int offset, u32 value)
41735 +{
41736 + iowrite32(value, vpdma->base + offset);
41737 +}
41738 +
41739 +static int read_field_reg(struct vpdma_data *vpdma, int offset,
41740 + u32 mask, int shift)
41741 +{
41742 + return (read_reg(vpdma, offset) & (mask << shift)) >> shift;
41743 +}
41744 +
41745 +static void write_field_reg(struct vpdma_data *vpdma, int offset, u32 field,
41746 + u32 mask, int shift)
41747 +{
41748 + u32 val = read_reg(vpdma, offset);
41749 +
41750 + val &= ~(mask << shift);
41751 + val |= (field & mask) << shift;
41752 +
41753 + write_reg(vpdma, offset, val);
41754 +}
41755 +
41756 +void vpdma_dump_regs(struct vpdma_data *vpdma)
41757 +{
41758 + struct device *dev = &vpdma->pdev->dev;
41759 +
41760 +#define DUMPREG(r) dev_dbg(dev, "%-35s %08x\n", #r, read_reg(vpdma, VPDMA_##r))
41761 +
41762 + dev_dbg(dev, "VPDMA Registers:\n");
41763 +
41764 + DUMPREG(PID);
41765 + DUMPREG(LIST_ADDR);
41766 + DUMPREG(LIST_ATTR);
41767 + DUMPREG(LIST_STAT_SYNC);
41768 + DUMPREG(BG_RGB);
41769 + DUMPREG(BG_YUV);
41770 + DUMPREG(SETUP);
41771 + DUMPREG(MAX_SIZE1);
41772 + DUMPREG(MAX_SIZE2);
41773 + DUMPREG(MAX_SIZE3);
41774 +
41775 + /*
41776 + * dumping registers of only group0 and group3, because VPE channels
41777 + * lie within group0 and group3 registers
41778 + */
41779 + DUMPREG(INT_CHAN_STAT(0));
41780 + DUMPREG(INT_CHAN_MASK(0));
41781 + DUMPREG(INT_CHAN_STAT(3));
41782 + DUMPREG(INT_CHAN_MASK(3));
41783 + DUMPREG(INT_CLIENT0_STAT);
41784 + DUMPREG(INT_CLIENT0_MASK);
41785 + DUMPREG(INT_CLIENT1_STAT);
41786 + DUMPREG(INT_CLIENT1_MASK);
41787 + DUMPREG(INT_LIST0_STAT);
41788 + DUMPREG(INT_LIST0_MASK);
41789 +
41790 + /*
41791 + * these are registers specific to VPE clients, we can make this
41792 + * function dump client registers specific to VPE or VIP based on
41793 + * who is using it
41794 + */
41795 + DUMPREG(DEI_CHROMA1_CSTAT);
41796 + DUMPREG(DEI_LUMA1_CSTAT);
41797 + DUMPREG(DEI_CHROMA2_CSTAT);
41798 + DUMPREG(DEI_LUMA2_CSTAT);
41799 + DUMPREG(DEI_CHROMA3_CSTAT);
41800 + DUMPREG(DEI_LUMA3_CSTAT);
41801 + DUMPREG(DEI_MV_IN_CSTAT);
41802 + DUMPREG(DEI_MV_OUT_CSTAT);
41803 + DUMPREG(VIP_UP_Y_CSTAT);
41804 + DUMPREG(VIP_UP_UV_CSTAT);
41805 + DUMPREG(VPI_CTL_CSTAT);
41806 +}
41807 +
41808 +/*
41809 + * Allocate a DMA buffer
41810 + */
41811 +int vpdma_alloc_desc_buf(struct vpdma_buf *buf, size_t size)
41812 +{
41813 + buf->size = size;
41814 + buf->mapped = false;
41815 + buf->addr = kzalloc(size, GFP_KERNEL);
41816 + if (!buf->addr)
41817 + return -ENOMEM;
41818 +
41819 + WARN_ON((u32) buf->addr & VPDMA_DESC_ALIGN);
41820 +
41821 + return 0;
41822 +}
41823 +
41824 +void vpdma_free_desc_buf(struct vpdma_buf *buf)
41825 +{
41826 + WARN_ON(buf->mapped);
41827 + kfree(buf->addr);
41828 + buf->addr = NULL;
41829 + buf->size = 0;
41830 +}
41831 +
41832 +/*
41833 + * map descriptor/payload DMA buffer, enabling DMA access
41834 + */
41835 +int vpdma_map_desc_buf(struct vpdma_data *vpdma, struct vpdma_buf *buf)
41836 +{
41837 + struct device *dev = &vpdma->pdev->dev;
41838 +
41839 + WARN_ON(buf->mapped);
41840 + buf->dma_addr = dma_map_single(dev, buf->addr, buf->size,
41841 + DMA_TO_DEVICE);
41842 + if (dma_mapping_error(dev, buf->dma_addr)) {
41843 + dev_err(dev, "failed to map buffer\n");
41844 + return -EINVAL;
41845 + }
41846 +
41847 + buf->mapped = true;
41848 +
41849 + return 0;
41850 +}
41851 +
41852 +/*
41853 + * unmap descriptor/payload DMA buffer, disabling DMA access and
41854 + * allowing the main processor to acces the data
41855 + */
41856 +void vpdma_unmap_desc_buf(struct vpdma_data *vpdma, struct vpdma_buf *buf)
41857 +{
41858 + struct device *dev = &vpdma->pdev->dev;
41859 +
41860 + if (buf->mapped)
41861 + dma_unmap_single(dev, buf->dma_addr, buf->size, DMA_TO_DEVICE);
41862 +
41863 + buf->mapped = false;
41864 +}
41865 +
41866 +/*
41867 + * create a descriptor list, the user of this list will append configuration,
41868 + * control and data descriptors to this list, this list will be submitted to
41869 + * VPDMA. VPDMA's list parser will go through each descriptor and perform the
41870 + * required DMA operations
41871 + */
41872 +int vpdma_create_desc_list(struct vpdma_desc_list *list, size_t size, int type)
41873 +{
41874 + int r;
41875 +
41876 + r = vpdma_alloc_desc_buf(&list->buf, size);
41877 + if (r)
41878 + return r;
41879 +
41880 + list->next = list->buf.addr;
41881 +
41882 + list->type = type;
41883 +
41884 + return 0;
41885 +}
41886 +
41887 +/*
41888 + * once a descriptor list is parsed by VPDMA, we reset the list by emptying it,
41889 + * to allow new descriptors to be added to the list.
41890 + */
41891 +void vpdma_reset_desc_list(struct vpdma_desc_list *list)
41892 +{
41893 + list->next = list->buf.addr;
41894 +}
41895 +
41896 +/*
41897 + * free the buffer allocated fot the VPDMA descriptor list, this should be
41898 + * called when the user doesn't want to use VPDMA any more.
41899 + */
41900 +void vpdma_free_desc_list(struct vpdma_desc_list *list)
41901 +{
41902 + vpdma_free_desc_buf(&list->buf);
41903 +
41904 + list->next = NULL;
41905 +}
41906 +
41907 +static bool vpdma_list_busy(struct vpdma_data *vpdma, int list_num)
41908 +{
41909 + return read_reg(vpdma, VPDMA_LIST_STAT_SYNC) & BIT(list_num + 16);
41910 +}
41911 +
41912 +/*
41913 + * submit a list of DMA descriptors to the VPE VPDMA, do not wait for completion
41914 + */
41915 +int vpdma_submit_descs(struct vpdma_data *vpdma, struct vpdma_desc_list *list)
41916 +{
41917 + /* we always use the first list */
41918 + int list_num = 0;
41919 + int list_size;
41920 +
41921 + if (vpdma_list_busy(vpdma, list_num))
41922 + return -EBUSY;
41923 +
41924 + /* 16-byte granularity */
41925 + list_size = (list->next - list->buf.addr) >> 4;
41926 +
41927 + write_reg(vpdma, VPDMA_LIST_ADDR, (u32) list->buf.dma_addr);
41928 +
41929 + write_reg(vpdma, VPDMA_LIST_ATTR,
41930 + (list_num << VPDMA_LIST_NUM_SHFT) |
41931 + (list->type << VPDMA_LIST_TYPE_SHFT) |
41932 + list_size);
41933 +
41934 + return 0;
41935 +}
41936 +
41937 +static void dump_cfd(struct vpdma_cfd *cfd)
41938 +{
41939 + int class;
41940 +
41941 + class = cfd_get_class(cfd);
41942 +
41943 + pr_debug("config descriptor of payload class: %s\n",
41944 + class == CFD_CLS_BLOCK ? "simple block" :
41945 + "address data block");
41946 +
41947 + if (class == CFD_CLS_BLOCK)
41948 + pr_debug("word0: dst_addr_offset = 0x%08x\n",
41949 + cfd->dest_addr_offset);
41950 +
41951 + if (class == CFD_CLS_BLOCK)
41952 + pr_debug("word1: num_data_wrds = %d\n", cfd->block_len);
41953 +
41954 + pr_debug("word2: payload_addr = 0x%08x\n", cfd->payload_addr);
41955 +
41956 + pr_debug("word3: pkt_type = %d, direct = %d, class = %d, dest = %d, "
41957 + "payload_len = %d\n", cfd_get_pkt_type(cfd),
41958 + cfd_get_direct(cfd), class, cfd_get_dest(cfd),
41959 + cfd_get_payload_len(cfd));
41960 +}
41961 +
41962 +/*
41963 + * append a configuration descriptor to the given descriptor list, where the
41964 + * payload is in the form of a simple data block specified in the descriptor
41965 + * header, this is used to upload scaler coefficients to the scaler module
41966 + */
41967 +void vpdma_add_cfd_block(struct vpdma_desc_list *list, int client,
41968 + struct vpdma_buf *blk, u32 dest_offset)
41969 +{
41970 + struct vpdma_cfd *cfd;
41971 + int len = blk->size;
41972 +
41973 + WARN_ON(blk->dma_addr & VPDMA_DESC_ALIGN);
41974 +
41975 + cfd = list->next;
41976 + WARN_ON((void *)(cfd + 1) > (list->buf.addr + list->buf.size));
41977 +
41978 + cfd->dest_addr_offset = dest_offset;
41979 + cfd->block_len = len;
41980 + cfd->payload_addr = (u32) blk->dma_addr;
41981 + cfd->ctl_payload_len = cfd_pkt_payload_len(CFD_INDIRECT, CFD_CLS_BLOCK,
41982 + client, len >> 4);
41983 +
41984 + list->next = cfd + 1;
41985 +
41986 + dump_cfd(cfd);
41987 +}
41988 +
41989 +/*
41990 + * append a configuration descriptor to the given descriptor list, where the
41991 + * payload is in the address data block format, this is used to a configure a
41992 + * discontiguous set of MMRs
41993 + */
41994 +void vpdma_add_cfd_adb(struct vpdma_desc_list *list, int client,
41995 + struct vpdma_buf *adb)
41996 +{
41997 + struct vpdma_cfd *cfd;
41998 + unsigned int len = adb->size;
41999 +
42000 + WARN_ON(len & VPDMA_ADB_SIZE_ALIGN);
42001 + WARN_ON(adb->dma_addr & VPDMA_DESC_ALIGN);
42002 +
42003 + cfd = list->next;
42004 + BUG_ON((void *)(cfd + 1) > (list->buf.addr + list->buf.size));
42005 +
42006 + cfd->w0 = 0;
42007 + cfd->w1 = 0;
42008 + cfd->payload_addr = (u32) adb->dma_addr;
42009 + cfd->ctl_payload_len = cfd_pkt_payload_len(CFD_INDIRECT, CFD_CLS_ADB,
42010 + client, len >> 4);
42011 +
42012 + list->next = cfd + 1;
42013 +
42014 + dump_cfd(cfd);
42015 +};
42016 +
42017 +/*
42018 + * control descriptor format change based on what type of control descriptor it
42019 + * is, we only use 'sync on channel' control descriptors for now, so assume it's
42020 + * that
42021 + */
42022 +static void dump_ctd(struct vpdma_ctd *ctd)
42023 +{
42024 + pr_debug("control descriptor\n");
42025 +
42026 + pr_debug("word3: pkt_type = %d, source = %d, ctl_type = %d\n",
42027 + ctd_get_pkt_type(ctd), ctd_get_source(ctd), ctd_get_ctl(ctd));
42028 +}
42029 +
42030 +/*
42031 + * append a 'sync on channel' type control descriptor to the given descriptor
42032 + * list, this descriptor stalls the VPDMA list till the time DMA is completed
42033 + * on the specified channel
42034 + */
42035 +void vpdma_add_sync_on_channel_ctd(struct vpdma_desc_list *list,
42036 + enum vpdma_channel chan)
42037 +{
42038 + struct vpdma_ctd *ctd;
42039 +
42040 + ctd = list->next;
42041 + WARN_ON((void *)(ctd + 1) > (list->buf.addr + list->buf.size));
42042 +
42043 + ctd->w0 = 0;
42044 + ctd->w1 = 0;
42045 + ctd->w2 = 0;
42046 + ctd->type_source_ctl = ctd_type_source_ctl(chan_info[chan].num,
42047 + CTD_TYPE_SYNC_ON_CHANNEL);
42048 +
42049 + list->next = ctd + 1;
42050 +
42051 + dump_ctd(ctd);
42052 +}
42053 +
42054 +static void dump_dtd(struct vpdma_dtd *dtd)
42055 +{
42056 + int dir, chan;
42057 +
42058 + dir = dtd_get_dir(dtd);
42059 + chan = dtd_get_chan(dtd);
42060 +
42061 + pr_debug("%s data transfer descriptor for channel %d\n",
42062 + dir == DTD_DIR_OUT ? "outbound" : "inbound", chan);
42063 +
42064 + pr_debug("word0: data_type = %d, notify = %d, field = %d, 1D = %d, "
42065 + "even_ln_skp = %d, odd_ln_skp = %d, line_stride = %d\n",
42066 + dtd_get_data_type(dtd), dtd_get_notify(dtd), dtd_get_field(dtd),
42067 + dtd_get_1d(dtd), dtd_get_even_line_skip(dtd),
42068 + dtd_get_odd_line_skip(dtd), dtd_get_line_stride(dtd));
42069 +
42070 + if (dir == DTD_DIR_IN)
42071 + pr_debug("word1: line_length = %d, xfer_height = %d\n",
42072 + dtd_get_line_length(dtd), dtd_get_xfer_height(dtd));
42073 +
42074 + pr_debug("word2: start_addr = 0x%08x\n", dtd->start_addr);
42075 +
42076 + pr_debug("word3: pkt_type = %d, mode = %d, dir = %d, chan = %d, "
42077 + "pri = %d, next_chan = %d\n", dtd_get_pkt_type(dtd),
42078 + dtd_get_mode(dtd), dir, chan, dtd_get_priority(dtd),
42079 + dtd_get_next_chan(dtd));
42080 +
42081 + if (dir == DTD_DIR_IN)
42082 + pr_debug("word4: frame_width = %d, frame_height = %d\n",
42083 + dtd_get_frame_width(dtd), dtd_get_frame_height(dtd));
42084 + else
42085 + pr_debug("word4: desc_write_addr = 0x%08x, write_desc = %d, "
42086 + "drp_data = %d, use_desc_reg = %d\n",
42087 + dtd_get_desc_write_addr(dtd), dtd_get_write_desc(dtd),
42088 + dtd_get_drop_data(dtd), dtd_get_use_desc(dtd));
42089 +
42090 + if (dir == DTD_DIR_IN)
42091 + pr_debug("word5: hor_start = %d, ver_start = %d\n",
42092 + dtd_get_h_start(dtd), dtd_get_v_start(dtd));
42093 + else
42094 + pr_debug("word5: max_width %d, max_height %d\n",
42095 + dtd_get_max_width(dtd), dtd_get_max_height(dtd));
42096 +
42097 + pr_debug("word6: client specfic attr0 = 0x%08x\n", dtd->client_attr0);
42098 + pr_debug("word7: client specfic attr1 = 0x%08x\n", dtd->client_attr1);
42099 +}
42100 +
42101 +/*
42102 + * append an outbound data transfer descriptor to the given descriptor list,
42103 + * this sets up a 'client to memory' VPDMA transfer for the given VPDMA channel
42104 + */
42105 +void vpdma_add_out_dtd(struct vpdma_desc_list *list, struct v4l2_rect *c_rect,
42106 + const struct vpdma_data_format *fmt, dma_addr_t dma_addr,
42107 + enum vpdma_channel chan, u32 flags)
42108 +{
42109 + int priority = 0;
42110 + int field = 0;
42111 + int notify = 1;
42112 + int channel, next_chan;
42113 + int depth = fmt->depth;
42114 + int stride;
42115 + struct vpdma_dtd *dtd;
42116 +
42117 + channel = next_chan = chan_info[chan].num;
42118 +
42119 + if (fmt->data_type == DATA_TYPE_C420)
42120 + depth = 8;
42121 +
42122 + stride = (depth * c_rect->width) >> 3;
42123 + dma_addr += (c_rect->left * depth) >> 3;
42124 +
42125 + dtd = list->next;
42126 + WARN_ON((void *)(dtd + 1) > (list->buf.addr + list->buf.size));
42127 +
42128 + dtd->type_ctl_stride = dtd_type_ctl_stride(fmt->data_type,
42129 + notify,
42130 + field,
42131 + !!(flags & VPDMA_DATA_FRAME_1D),
42132 + !!(flags & VPDMA_DATA_EVEN_LINE_SKIP),
42133 + !!(flags & VPDMA_DATA_ODD_LINE_SKIP),
42134 + stride);
42135 + dtd->w1 = 0;
42136 + dtd->start_addr = (u32) dma_addr;
42137 + dtd->pkt_ctl = dtd_pkt_ctl(!!(flags & VPDMA_DATA_MODE_TILED),
42138 + DTD_DIR_OUT, channel, priority, next_chan);
42139 + dtd->desc_write_addr = dtd_desc_write_addr(0, 0, 0, 0);
42140 + dtd->max_width_height = dtd_max_width_height(MAX_OUT_WIDTH_1920,
42141 + MAX_OUT_HEIGHT_1080);
42142 + dtd->client_attr0 = 0;
42143 + dtd->client_attr1 = 0;
42144 +
42145 + list->next = dtd + 1;
42146 +
42147 + dump_dtd(dtd);
42148 +}
42149 +
42150 +/*
42151 + * append an inbound data transfer descriptor to the given descriptor list,
42152 + * this sets up a 'memory to client' VPDMA transfer for the given VPDMA channel
42153 + */
42154 +void vpdma_add_in_dtd(struct vpdma_desc_list *list, int frame_width,
42155 + int frame_height, struct v4l2_rect *c_rect,
42156 + const struct vpdma_data_format *fmt, dma_addr_t dma_addr,
42157 + enum vpdma_channel chan, int field, u32 flags)
42158 +{
42159 + int priority = 0;
42160 + int notify = 1;
42161 + int depth = fmt->depth;
42162 + int channel, next_chan;
42163 + int stride;
42164 + int height = c_rect->height;
42165 + struct vpdma_dtd *dtd;
42166 +
42167 + channel = next_chan = chan_info[chan].num;
42168 +
42169 + if (fmt->data_type == DATA_TYPE_C420) {
42170 + height >>= 1;
42171 + frame_height >>= 1;
42172 + depth = 8;
42173 + }
42174 +
42175 + stride = (depth * c_rect->width) >> 3;
42176 + dma_addr += (c_rect->left * depth) >> 3;
42177 +
42178 + dtd = list->next;
42179 + WARN_ON((void *)(dtd + 1) > (list->buf.addr + list->buf.size));
42180 +
42181 + dtd->type_ctl_stride = dtd_type_ctl_stride(fmt->data_type,
42182 + notify,
42183 + field,
42184 + !!(flags & VPDMA_DATA_FRAME_1D),
42185 + !!(flags & VPDMA_DATA_EVEN_LINE_SKIP),
42186 + !!(flags & VPDMA_DATA_ODD_LINE_SKIP),
42187 + stride);
42188 +
42189 + dtd->xfer_length_height = dtd_xfer_length_height(c_rect->width, height);
42190 + dtd->start_addr = (u32) dma_addr;
42191 + dtd->pkt_ctl = dtd_pkt_ctl(!!(flags & VPDMA_DATA_MODE_TILED),
42192 + DTD_DIR_IN, channel, priority, next_chan);
42193 + dtd->frame_width_height = dtd_frame_width_height(frame_width,
42194 + frame_height);
42195 + dtd->start_h_v = dtd_start_h_v(c_rect->left, c_rect->top);
42196 + dtd->client_attr0 = 0;
42197 + dtd->client_attr1 = 0;
42198 +
42199 + list->next = dtd + 1;
42200 +
42201 + dump_dtd(dtd);
42202 +}
42203 +
42204 +/* set or clear the mask for list complete interrupt */
42205 +void vpdma_enable_list_complete_irq(struct vpdma_data *vpdma, int list_num,
42206 + bool enable)
42207 +{
42208 + u32 val;
42209 +
42210 + val = read_reg(vpdma, VPDMA_INT_LIST0_MASK);
42211 + if (enable)
42212 + val |= (1 << (list_num * 2));
42213 + else
42214 + val &= ~(1 << (list_num * 2));
42215 + write_reg(vpdma, VPDMA_INT_LIST0_MASK, val);
42216 +}
42217 +
42218 +/* clear previosuly occured list intterupts in the LIST_STAT register */
42219 +void vpdma_clear_list_stat(struct vpdma_data *vpdma)
42220 +{
42221 + write_reg(vpdma, VPDMA_INT_LIST0_STAT,
42222 + read_reg(vpdma, VPDMA_INT_LIST0_STAT));
42223 +}
42224 +
42225 +/*
42226 + * configures the output mode of the line buffer for the given client, the
42227 + * line buffer content can either be mirrored(each line repeated twice) or
42228 + * passed to the client as is
42229 + */
42230 +void vpdma_set_line_mode(struct vpdma_data *vpdma, int line_mode,
42231 + enum vpdma_channel chan)
42232 +{
42233 + int client_cstat = chan_info[chan].cstat_offset;
42234 +
42235 + write_field_reg(vpdma, client_cstat, line_mode,
42236 + VPDMA_CSTAT_LINE_MODE_MASK, VPDMA_CSTAT_LINE_MODE_SHIFT);
42237 +}
42238 +
42239 +/*
42240 + * configures the event which should trigger VPDMA transfer for the given
42241 + * client
42242 + */
42243 +void vpdma_set_frame_start_event(struct vpdma_data *vpdma,
42244 + enum vpdma_frame_start_event fs_event,
42245 + enum vpdma_channel chan)
42246 +{
42247 + int client_cstat = chan_info[chan].cstat_offset;
42248 +
42249 + write_field_reg(vpdma, client_cstat, fs_event,
42250 + VPDMA_CSTAT_FRAME_START_MASK, VPDMA_CSTAT_FRAME_START_SHIFT);
42251 +}
42252 +
42253 +static void vpdma_firmware_cb(const struct firmware *f, void *context)
42254 +{
42255 + struct vpdma_data *vpdma = context;
42256 + struct vpdma_buf fw_dma_buf;
42257 + int i, r;
42258 +
42259 + dev_dbg(&vpdma->pdev->dev, "firmware callback\n");
42260 +
42261 + if (!f || !f->data) {
42262 + dev_err(&vpdma->pdev->dev, "couldn't get firmware\n");
42263 + return;
42264 + }
42265 +
42266 + /* already initialized */
42267 + if (read_field_reg(vpdma, VPDMA_LIST_ATTR, VPDMA_LIST_RDY_MASK,
42268 + VPDMA_LIST_RDY_SHFT)) {
42269 + vpdma->ready = true;
42270 + return;
42271 + }
42272 +
42273 + r = vpdma_alloc_desc_buf(&fw_dma_buf, f->size);
42274 + if (r) {
42275 + dev_err(&vpdma->pdev->dev,
42276 + "failed to allocate dma buffer for firmware\n");
42277 + goto rel_fw;
42278 + }
42279 +
42280 + memcpy(fw_dma_buf.addr, f->data, f->size);
42281 +
42282 + vpdma_map_desc_buf(vpdma, &fw_dma_buf);
42283 +
42284 + write_reg(vpdma, VPDMA_LIST_ADDR, (u32) fw_dma_buf.dma_addr);
42285 +
42286 + for (i = 0; i < 100; i++) { /* max 1 second */
42287 + msleep_interruptible(10);
42288 +
42289 + if (read_field_reg(vpdma, VPDMA_LIST_ATTR, VPDMA_LIST_RDY_MASK,
42290 + VPDMA_LIST_RDY_SHFT))
42291 + break;
42292 + }
42293 +
42294 + if (i == 100) {
42295 + dev_err(&vpdma->pdev->dev, "firmware upload failed\n");
42296 + goto free_buf;
42297 + }
42298 +
42299 + vpdma->ready = true;
42300 +
42301 +free_buf:
42302 + vpdma_unmap_desc_buf(vpdma, &fw_dma_buf);
42303 +
42304 + vpdma_free_desc_buf(&fw_dma_buf);
42305 +rel_fw:
42306 + release_firmware(f);
42307 +}
42308 +
42309 +static int vpdma_load_firmware(struct vpdma_data *vpdma)
42310 +{
42311 + int r;
42312 + struct device *dev = &vpdma->pdev->dev;
42313 +
42314 + r = request_firmware_nowait(THIS_MODULE, 1,
42315 + (const char *) VPDMA_FIRMWARE, dev, GFP_KERNEL, vpdma,
42316 + vpdma_firmware_cb);
42317 + if (r) {
42318 + dev_err(dev, "firmware not available %s\n", VPDMA_FIRMWARE);
42319 + return r;
42320 + } else {
42321 + dev_info(dev, "loading firmware %s\n", VPDMA_FIRMWARE);
42322 + }
42323 +
42324 + return 0;
42325 +}
42326 +
42327 +struct vpdma_data *vpdma_create(struct platform_device *pdev)
42328 +{
42329 + struct resource *res;
42330 + struct vpdma_data *vpdma;
42331 + int r;
42332 +
42333 + dev_dbg(&pdev->dev, "vpdma_create\n");
42334 +
42335 + vpdma = devm_kzalloc(&pdev->dev, sizeof(*vpdma), GFP_KERNEL);
42336 + if (!vpdma) {
42337 + dev_err(&pdev->dev, "couldn't alloc vpdma_dev\n");
42338 + return ERR_PTR(-ENOMEM);
42339 + }
42340 +
42341 + vpdma->pdev = pdev;
42342 +
42343 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "vpdma");
42344 + if (res == NULL) {
42345 + dev_err(&pdev->dev, "missing platform resources data\n");
42346 + return ERR_PTR(-ENODEV);
42347 + }
42348 +
42349 + vpdma->base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
42350 + if (!vpdma->base) {
42351 + dev_err(&pdev->dev, "failed to ioremap\n");
42352 + return ERR_PTR(-ENOMEM);
42353 + }
42354 +
42355 + r = vpdma_load_firmware(vpdma);
42356 + if (r) {
42357 + pr_err("failed to load firmware %s\n", VPDMA_FIRMWARE);
42358 + return ERR_PTR(r);
42359 + }
42360 +
42361 + return vpdma;
42362 +}
42363 +MODULE_FIRMWARE(VPDMA_FIRMWARE);
42364 --- /dev/null
42365 +++ b/drivers/media/platform/ti-vpe/vpdma.h
42366 @@ -0,0 +1,203 @@
42367 +/*
42368 + * Copyright (c) 2013 Texas Instruments Inc.
42369 + *
42370 + * David Griego, <dagriego@biglakesoftware.com>
42371 + * Dale Farnsworth, <dale@farnsworth.org>
42372 + * Archit Taneja, <archit@ti.com>
42373 + *
42374 + * This program is free software; you can redistribute it and/or modify it
42375 + * under the terms of the GNU General Public License version 2 as published by
42376 + * the Free Software Foundation.
42377 + */
42378 +
42379 +#ifndef __TI_VPDMA_H_
42380 +#define __TI_VPDMA_H_
42381 +
42382 +/*
42383 + * A vpdma_buf tracks the size, DMA address and mapping status of each
42384 + * driver DMA area.
42385 + */
42386 +struct vpdma_buf {
42387 + void *addr;
42388 + dma_addr_t dma_addr;
42389 + size_t size;
42390 + bool mapped;
42391 +};
42392 +
42393 +struct vpdma_desc_list {
42394 + struct vpdma_buf buf;
42395 + void *next;
42396 + int type;
42397 +};
42398 +
42399 +struct vpdma_data {
42400 + void __iomem *base;
42401 +
42402 + struct platform_device *pdev;
42403 +
42404 + /* tells whether vpdma firmware is loaded or not */
42405 + bool ready;
42406 +};
42407 +
42408 +struct vpdma_data_format {
42409 + int data_type;
42410 + u8 depth;
42411 +};
42412 +
42413 +#define VPDMA_DESC_ALIGN 16 /* 16-byte descriptor alignment */
42414 +
42415 +#define VPDMA_DTD_DESC_SIZE 32 /* 8 words */
42416 +#define VPDMA_CFD_CTD_DESC_SIZE 16 /* 4 words */
42417 +
42418 +#define VPDMA_LIST_TYPE_NORMAL 0
42419 +#define VPDMA_LIST_TYPE_SELF_MODIFYING 1
42420 +#define VPDMA_LIST_TYPE_DOORBELL 2
42421 +
42422 +enum vpdma_yuv_formats {
42423 + VPDMA_DATA_FMT_Y444 = 0,
42424 + VPDMA_DATA_FMT_Y422,
42425 + VPDMA_DATA_FMT_Y420,
42426 + VPDMA_DATA_FMT_C444,
42427 + VPDMA_DATA_FMT_C422,
42428 + VPDMA_DATA_FMT_C420,
42429 + VPDMA_DATA_FMT_YC422,
42430 + VPDMA_DATA_FMT_YC444,
42431 + VPDMA_DATA_FMT_CY422,
42432 +};
42433 +
42434 +enum vpdma_rgb_formats {
42435 + VPDMA_DATA_FMT_RGB565 = 0,
42436 + VPDMA_DATA_FMT_ARGB16_1555,
42437 + VPDMA_DATA_FMT_ARGB16,
42438 + VPDMA_DATA_FMT_RGBA16_5551,
42439 + VPDMA_DATA_FMT_RGBA16,
42440 + VPDMA_DATA_FMT_ARGB24,
42441 + VPDMA_DATA_FMT_RGB24,
42442 + VPDMA_DATA_FMT_ARGB32,
42443 + VPDMA_DATA_FMT_RGBA24,
42444 + VPDMA_DATA_FMT_RGBA32,
42445 + VPDMA_DATA_FMT_BGR565,
42446 + VPDMA_DATA_FMT_ABGR16_1555,
42447 + VPDMA_DATA_FMT_ABGR16,
42448 + VPDMA_DATA_FMT_BGRA16_5551,
42449 + VPDMA_DATA_FMT_BGRA16,
42450 + VPDMA_DATA_FMT_ABGR24,
42451 + VPDMA_DATA_FMT_BGR24,
42452 + VPDMA_DATA_FMT_ABGR32,
42453 + VPDMA_DATA_FMT_BGRA24,
42454 + VPDMA_DATA_FMT_BGRA32,
42455 +};
42456 +
42457 +enum vpdma_misc_formats {
42458 + VPDMA_DATA_FMT_MV = 0,
42459 +};
42460 +
42461 +extern const struct vpdma_data_format vpdma_yuv_fmts[];
42462 +extern const struct vpdma_data_format vpdma_rgb_fmts[];
42463 +extern const struct vpdma_data_format vpdma_misc_fmts[];
42464 +
42465 +enum vpdma_frame_start_event {
42466 + VPDMA_FSEVENT_HDMI_FID = 0,
42467 + VPDMA_FSEVENT_DVO2_FID,
42468 + VPDMA_FSEVENT_HDCOMP_FID,
42469 + VPDMA_FSEVENT_SD_FID,
42470 + VPDMA_FSEVENT_LM_FID0,
42471 + VPDMA_FSEVENT_LM_FID1,
42472 + VPDMA_FSEVENT_LM_FID2,
42473 + VPDMA_FSEVENT_CHANNEL_ACTIVE,
42474 +};
42475 +
42476 +/*
42477 + * VPDMA channel numbers
42478 + */
42479 +enum vpdma_channel {
42480 + VPE_CHAN_LUMA1_IN,
42481 + VPE_CHAN_CHROMA1_IN,
42482 + VPE_CHAN_LUMA2_IN,
42483 + VPE_CHAN_CHROMA2_IN,
42484 + VPE_CHAN_LUMA3_IN,
42485 + VPE_CHAN_CHROMA3_IN,
42486 + VPE_CHAN_MV_IN,
42487 + VPE_CHAN_MV_OUT,
42488 + VPE_CHAN_LUMA_OUT,
42489 + VPE_CHAN_CHROMA_OUT,
42490 + VPE_CHAN_RGB_OUT,
42491 +};
42492 +
42493 +/* flags for VPDMA data descriptors */
42494 +#define VPDMA_DATA_ODD_LINE_SKIP (1 << 0)
42495 +#define VPDMA_DATA_EVEN_LINE_SKIP (1 << 1)
42496 +#define VPDMA_DATA_FRAME_1D (1 << 2)
42497 +#define VPDMA_DATA_MODE_TILED (1 << 3)
42498 +
42499 +/*
42500 + * client identifiers used for configuration descriptors
42501 + */
42502 +#define CFD_MMR_CLIENT 0
42503 +#define CFD_SC_CLIENT 4
42504 +
42505 +/* Address data block header format */
42506 +struct vpdma_adb_hdr {
42507 + u32 offset;
42508 + u32 nwords;
42509 + u32 reserved0;
42510 + u32 reserved1;
42511 +};
42512 +
42513 +/* helpers for creating ADB headers for config descriptors MMRs as client */
42514 +#define ADB_ADDR(dma_buf, str, fld) ((dma_buf)->addr + offsetof(str, fld))
42515 +#define MMR_ADB_ADDR(buf, str, fld) ADB_ADDR(&(buf), struct str, fld)
42516 +
42517 +#define VPDMA_SET_MMR_ADB_HDR(buf, str, hdr, regs, offset_a) \
42518 + do { \
42519 + struct vpdma_adb_hdr *h; \
42520 + struct str *adb = NULL; \
42521 + h = MMR_ADB_ADDR(buf, str, hdr); \
42522 + h->offset = (offset_a); \
42523 + h->nwords = sizeof(adb->regs) >> 2; \
42524 + } while (0)
42525 +
42526 +/* vpdma descriptor buffer allocation and management */
42527 +int vpdma_alloc_desc_buf(struct vpdma_buf *buf, size_t size);
42528 +void vpdma_free_desc_buf(struct vpdma_buf *buf);
42529 +int vpdma_map_desc_buf(struct vpdma_data *vpdma, struct vpdma_buf *buf);
42530 +void vpdma_unmap_desc_buf(struct vpdma_data *vpdma, struct vpdma_buf *buf);
42531 +
42532 +/* vpdma descriptor list funcs */
42533 +int vpdma_create_desc_list(struct vpdma_desc_list *list, size_t size, int type);
42534 +void vpdma_reset_desc_list(struct vpdma_desc_list *list);
42535 +void vpdma_free_desc_list(struct vpdma_desc_list *list);
42536 +int vpdma_submit_descs(struct vpdma_data *vpdma, struct vpdma_desc_list *list);
42537 +
42538 +/* helpers for creating vpdma descriptors */
42539 +void vpdma_add_cfd_block(struct vpdma_desc_list *list, int client,
42540 + struct vpdma_buf *blk, u32 dest_offset);
42541 +void vpdma_add_cfd_adb(struct vpdma_desc_list *list, int client,
42542 + struct vpdma_buf *adb);
42543 +void vpdma_add_sync_on_channel_ctd(struct vpdma_desc_list *list,
42544 + enum vpdma_channel chan);
42545 +void vpdma_add_out_dtd(struct vpdma_desc_list *list, struct v4l2_rect *c_rect,
42546 + const struct vpdma_data_format *fmt, dma_addr_t dma_addr,
42547 + enum vpdma_channel chan, u32 flags);
42548 +void vpdma_add_in_dtd(struct vpdma_desc_list *list, int frame_width,
42549 + int frame_height, struct v4l2_rect *c_rect,
42550 + const struct vpdma_data_format *fmt, dma_addr_t dma_addr,
42551 + enum vpdma_channel chan, int field, u32 flags);
42552 +
42553 +/* vpdma list interrupt management */
42554 +void vpdma_enable_list_complete_irq(struct vpdma_data *vpdma, int list_num,
42555 + bool enable);
42556 +void vpdma_clear_list_stat(struct vpdma_data *vpdma);
42557 +
42558 +/* vpdma client configuration */
42559 +void vpdma_set_line_mode(struct vpdma_data *vpdma, int line_mode,
42560 + enum vpdma_channel chan);
42561 +void vpdma_set_frame_start_event(struct vpdma_data *vpdma,
42562 + enum vpdma_frame_start_event fs_event, enum vpdma_channel chan);
42563 +
42564 +void vpdma_dump_regs(struct vpdma_data *vpdma);
42565 +
42566 +/* initialize vpdma, passed with VPE's platform device pointer */
42567 +struct vpdma_data *vpdma_create(struct platform_device *pdev);
42568 +
42569 +#endif
42570 --- /dev/null
42571 +++ b/drivers/media/platform/ti-vpe/vpdma_priv.h
42572 @@ -0,0 +1,641 @@
42573 +/*
42574 + * Copyright (c) 2013 Texas Instruments Inc.
42575 + *
42576 + * David Griego, <dagriego@biglakesoftware.com>
42577 + * Dale Farnsworth, <dale@farnsworth.org>
42578 + * Archit Taneja, <archit@ti.com>
42579 + *
42580 + * This program is free software; you can redistribute it and/or modify it
42581 + * under the terms of the GNU General Public License version 2 as published by
42582 + * the Free Software Foundation.
42583 + */
42584 +
42585 +#ifndef _TI_VPDMA_PRIV_H_
42586 +#define _TI_VPDMA_PRIV_H_
42587 +
42588 +/*
42589 + * VPDMA Register offsets
42590 + */
42591 +
42592 +/* Top level */
42593 +#define VPDMA_PID 0x00
42594 +#define VPDMA_LIST_ADDR 0x04
42595 +#define VPDMA_LIST_ATTR 0x08
42596 +#define VPDMA_LIST_STAT_SYNC 0x0c
42597 +#define VPDMA_BG_RGB 0x18
42598 +#define VPDMA_BG_YUV 0x1c
42599 +#define VPDMA_SETUP 0x30
42600 +#define VPDMA_MAX_SIZE1 0x34
42601 +#define VPDMA_MAX_SIZE2 0x38
42602 +#define VPDMA_MAX_SIZE3 0x3c
42603 +
42604 +/* Interrupts */
42605 +#define VPDMA_INT_CHAN_STAT(grp) (0x40 + grp * 8)
42606 +#define VPDMA_INT_CHAN_MASK(grp) (VPDMA_INT_CHAN_STAT(grp) + 4)
42607 +#define VPDMA_INT_CLIENT0_STAT 0x78
42608 +#define VPDMA_INT_CLIENT0_MASK 0x7c
42609 +#define VPDMA_INT_CLIENT1_STAT 0x80
42610 +#define VPDMA_INT_CLIENT1_MASK 0x84
42611 +#define VPDMA_INT_LIST0_STAT 0x88
42612 +#define VPDMA_INT_LIST0_MASK 0x8c
42613 +
42614 +#define VPDMA_PERFMON(i) (0x200 + i * 4)
42615 +
42616 +/* VPE specific client registers */
42617 +#define VPDMA_DEI_CHROMA1_CSTAT 0x0300
42618 +#define VPDMA_DEI_LUMA1_CSTAT 0x0304
42619 +#define VPDMA_DEI_LUMA2_CSTAT 0x0308
42620 +#define VPDMA_DEI_CHROMA2_CSTAT 0x030c
42621 +#define VPDMA_DEI_LUMA3_CSTAT 0x0310
42622 +#define VPDMA_DEI_CHROMA3_CSTAT 0x0314
42623 +#define VPDMA_DEI_MV_IN_CSTAT 0x0330
42624 +#define VPDMA_DEI_MV_OUT_CSTAT 0x033c
42625 +#define VPDMA_VIP_UP_Y_CSTAT 0x0390
42626 +#define VPDMA_VIP_UP_UV_CSTAT 0x0394
42627 +#define VPDMA_VPI_CTL_CSTAT 0x03d0
42628 +
42629 +/* Reg field info for VPDMA_CLIENT_CSTAT registers */
42630 +#define VPDMA_CSTAT_LINE_MODE_MASK 0x03
42631 +#define VPDMA_CSTAT_LINE_MODE_SHIFT 8
42632 +#define VPDMA_CSTAT_FRAME_START_MASK 0xf
42633 +#define VPDMA_CSTAT_FRAME_START_SHIFT 10
42634 +
42635 +#define VPDMA_LIST_NUM_MASK 0x07
42636 +#define VPDMA_LIST_NUM_SHFT 24
42637 +#define VPDMA_LIST_STOP_SHFT 20
42638 +#define VPDMA_LIST_RDY_MASK 0x01
42639 +#define VPDMA_LIST_RDY_SHFT 19
42640 +#define VPDMA_LIST_TYPE_MASK 0x03
42641 +#define VPDMA_LIST_TYPE_SHFT 16
42642 +#define VPDMA_LIST_SIZE_MASK 0xffff
42643 +
42644 +/* VPDMA data type values for data formats */
42645 +#define DATA_TYPE_Y444 0x0
42646 +#define DATA_TYPE_Y422 0x1
42647 +#define DATA_TYPE_Y420 0x2
42648 +#define DATA_TYPE_C444 0x4
42649 +#define DATA_TYPE_C422 0x5
42650 +#define DATA_TYPE_C420 0x6
42651 +#define DATA_TYPE_YC422 0x7
42652 +#define DATA_TYPE_YC444 0x8
42653 +#define DATA_TYPE_CY422 0x23
42654 +
42655 +#define DATA_TYPE_RGB16_565 0x0
42656 +#define DATA_TYPE_ARGB_1555 0x1
42657 +#define DATA_TYPE_ARGB_4444 0x2
42658 +#define DATA_TYPE_RGBA_5551 0x3
42659 +#define DATA_TYPE_RGBA_4444 0x4
42660 +#define DATA_TYPE_ARGB24_6666 0x5
42661 +#define DATA_TYPE_RGB24_888 0x6
42662 +#define DATA_TYPE_ARGB32_8888 0x7
42663 +#define DATA_TYPE_RGBA24_6666 0x8
42664 +#define DATA_TYPE_RGBA32_8888 0x9
42665 +#define DATA_TYPE_BGR16_565 0x10
42666 +#define DATA_TYPE_ABGR_1555 0x11
42667 +#define DATA_TYPE_ABGR_4444 0x12
42668 +#define DATA_TYPE_BGRA_5551 0x13
42669 +#define DATA_TYPE_BGRA_4444 0x14
42670 +#define DATA_TYPE_ABGR24_6666 0x15
42671 +#define DATA_TYPE_BGR24_888 0x16
42672 +#define DATA_TYPE_ABGR32_8888 0x17
42673 +#define DATA_TYPE_BGRA24_6666 0x18
42674 +#define DATA_TYPE_BGRA32_8888 0x19
42675 +
42676 +#define DATA_TYPE_MV 0x3
42677 +
42678 +/* VPDMA channel numbers(only VPE channels for now) */
42679 +#define VPE_CHAN_NUM_LUMA1_IN 0
42680 +#define VPE_CHAN_NUM_CHROMA1_IN 1
42681 +#define VPE_CHAN_NUM_LUMA2_IN 2
42682 +#define VPE_CHAN_NUM_CHROMA2_IN 3
42683 +#define VPE_CHAN_NUM_LUMA3_IN 4
42684 +#define VPE_CHAN_NUM_CHROMA3_IN 5
42685 +#define VPE_CHAN_NUM_MV_IN 12
42686 +#define VPE_CHAN_NUM_MV_OUT 15
42687 +#define VPE_CHAN_NUM_LUMA_OUT 102
42688 +#define VPE_CHAN_NUM_CHROMA_OUT 103
42689 +#define VPE_CHAN_NUM_RGB_OUT 106
42690 +
42691 +/*
42692 + * a VPDMA address data block payload for a configuration descriptor needs to
42693 + * have each sub block length as a multiple of 16 bytes. Therefore, the overall
42694 + * size of the payload also needs to be a multiple of 16 bytes. The sub block
42695 + * lengths should be ensured to be aligned by the VPDMA user.
42696 + */
42697 +#define VPDMA_ADB_SIZE_ALIGN 0x0f
42698 +
42699 +/*
42700 + * data transfer descriptor
42701 + */
42702 +struct vpdma_dtd {
42703 + u32 type_ctl_stride;
42704 + union {
42705 + u32 xfer_length_height;
42706 + u32 w1;
42707 + };
42708 + dma_addr_t start_addr;
42709 + u32 pkt_ctl;
42710 + union {
42711 + u32 frame_width_height; /* inbound */
42712 + dma_addr_t desc_write_addr; /* outbound */
42713 + };
42714 + union {
42715 + u32 start_h_v; /* inbound */
42716 + u32 max_width_height; /* outbound */
42717 + };
42718 + u32 client_attr0;
42719 + u32 client_attr1;
42720 +};
42721 +
42722 +/* Data Transfer Descriptor specifics */
42723 +#define DTD_NO_NOTIFY 0
42724 +#define DTD_NOTIFY 1
42725 +
42726 +#define DTD_PKT_TYPE 0xa
42727 +#define DTD_DIR_IN 0
42728 +#define DTD_DIR_OUT 1
42729 +
42730 +/* type_ctl_stride */
42731 +#define DTD_DATA_TYPE_MASK 0x3f
42732 +#define DTD_DATA_TYPE_SHFT 26
42733 +#define DTD_NOTIFY_MASK 0x01
42734 +#define DTD_NOTIFY_SHFT 25
42735 +#define DTD_FIELD_MASK 0x01
42736 +#define DTD_FIELD_SHFT 24
42737 +#define DTD_1D_MASK 0x01
42738 +#define DTD_1D_SHFT 23
42739 +#define DTD_EVEN_LINE_SKIP_MASK 0x01
42740 +#define DTD_EVEN_LINE_SKIP_SHFT 20
42741 +#define DTD_ODD_LINE_SKIP_MASK 0x01
42742 +#define DTD_ODD_LINE_SKIP_SHFT 16
42743 +#define DTD_LINE_STRIDE_MASK 0xffff
42744 +#define DTD_LINE_STRIDE_SHFT 0
42745 +
42746 +/* xfer_length_height */
42747 +#define DTD_LINE_LENGTH_MASK 0xffff
42748 +#define DTD_LINE_LENGTH_SHFT 16
42749 +#define DTD_XFER_HEIGHT_MASK 0xffff
42750 +#define DTD_XFER_HEIGHT_SHFT 0
42751 +
42752 +/* pkt_ctl */
42753 +#define DTD_PKT_TYPE_MASK 0x1f
42754 +#define DTD_PKT_TYPE_SHFT 27
42755 +#define DTD_MODE_MASK 0x01
42756 +#define DTD_MODE_SHFT 26
42757 +#define DTD_DIR_MASK 0x01
42758 +#define DTD_DIR_SHFT 25
42759 +#define DTD_CHAN_MASK 0x01ff
42760 +#define DTD_CHAN_SHFT 16
42761 +#define DTD_PRI_MASK 0x0f
42762 +#define DTD_PRI_SHFT 9
42763 +#define DTD_NEXT_CHAN_MASK 0x01ff
42764 +#define DTD_NEXT_CHAN_SHFT 0
42765 +
42766 +/* frame_width_height */
42767 +#define DTD_FRAME_WIDTH_MASK 0xffff
42768 +#define DTD_FRAME_WIDTH_SHFT 16
42769 +#define DTD_FRAME_HEIGHT_MASK 0xffff
42770 +#define DTD_FRAME_HEIGHT_SHFT 0
42771 +
42772 +/* start_h_v */
42773 +#define DTD_H_START_MASK 0xffff
42774 +#define DTD_H_START_SHFT 16
42775 +#define DTD_V_START_MASK 0xffff
42776 +#define DTD_V_START_SHFT 0
42777 +
42778 +#define DTD_DESC_START_SHIFT 5
42779 +#define DTD_WRITE_DESC_MASK 0x01
42780 +#define DTD_WRITE_DESC_SHIFT 2
42781 +#define DTD_DROP_DATA_MASK 0x01
42782 +#define DTD_DROP_DATA_SHIFT 1
42783 +#define DTD_USE_DESC_MASK 0x01
42784 +#define DTD_USE_DESC_SHIFT 0
42785 +
42786 +/* max_width_height */
42787 +#define DTD_MAX_WIDTH_MASK 0x07
42788 +#define DTD_MAX_WIDTH_SHFT 4
42789 +#define DTD_MAX_HEIGHT_MASK 0x07
42790 +#define DTD_MAX_HEIGHT_SHFT 0
42791 +
42792 +/* max width configurations */
42793 + /* unlimited width */
42794 +#define MAX_OUT_WIDTH_UNLIMITED 0
42795 +/* as specified in max_size1 reg */
42796 +#define MAX_OUT_WIDTH_REG1 1
42797 +/* as specified in max_size2 reg */
42798 +#define MAX_OUT_WIDTH_REG2 2
42799 +/* as specified in max_size3 reg */
42800 +#define MAX_OUT_WIDTH_REG3 3
42801 +/* maximum of 352 pixels as width */
42802 +#define MAX_OUT_WIDTH_352 4
42803 +/* maximum of 768 pixels as width */
42804 +#define MAX_OUT_WIDTH_768 5
42805 +/* maximum of 1280 pixels width */
42806 +#define MAX_OUT_WIDTH_1280 6
42807 +/* maximum of 1920 pixels as width */
42808 +#define MAX_OUT_WIDTH_1920 7
42809 +
42810 +/* max height configurations */
42811 + /* unlimited height */
42812 +#define MAX_OUT_HEIGHT_UNLIMITED 0
42813 +/* as specified in max_size1 reg */
42814 +#define MAX_OUT_HEIGHT_REG1 1
42815 +/* as specified in max_size2 reg */
42816 +#define MAX_OUT_HEIGHT_REG2 2
42817 +/* as specified in max_size3 reg */
42818 +#define MAX_OUT_HEIGHT_REG3 3
42819 +/* maximum of 288 lines as height */
42820 +#define MAX_OUT_HEIGHT_288 4
42821 +/* maximum of 576 lines as height */
42822 +#define MAX_OUT_HEIGHT_576 5
42823 +/* maximum of 720 lines as height */
42824 +#define MAX_OUT_HEIGHT_720 6
42825 +/* maximum of 1080 lines as height */
42826 +#define MAX_OUT_HEIGHT_1080 7
42827 +
42828 +static inline u32 dtd_type_ctl_stride(int type, bool notify, int field,
42829 + bool one_d, bool even_line_skip, bool odd_line_skip,
42830 + int line_stride)
42831 +{
42832 + return (type << DTD_DATA_TYPE_SHFT) | (notify << DTD_NOTIFY_SHFT) |
42833 + (field << DTD_FIELD_SHFT) | (one_d << DTD_1D_SHFT) |
42834 + (even_line_skip << DTD_EVEN_LINE_SKIP_SHFT) |
42835 + (odd_line_skip << DTD_ODD_LINE_SKIP_SHFT) |
42836 + line_stride;
42837 +}
42838 +
42839 +static inline u32 dtd_xfer_length_height(int line_length, int xfer_height)
42840 +{
42841 + return (line_length << DTD_LINE_LENGTH_SHFT) | xfer_height;
42842 +}
42843 +
42844 +static inline u32 dtd_pkt_ctl(bool mode, bool dir, int chan, int pri,
42845 + int next_chan)
42846 +{
42847 + return (DTD_PKT_TYPE << DTD_PKT_TYPE_SHFT) | (mode << DTD_MODE_SHFT) |
42848 + (dir << DTD_DIR_SHFT) | (chan << DTD_CHAN_SHFT) |
42849 + (pri << DTD_PRI_SHFT) | next_chan;
42850 +}
42851 +
42852 +static inline u32 dtd_frame_width_height(int width, int height)
42853 +{
42854 + return (width << DTD_FRAME_WIDTH_SHFT) | height;
42855 +}
42856 +
42857 +static inline u32 dtd_desc_write_addr(unsigned int addr, bool write_desc,
42858 + bool drop_data, bool use_desc)
42859 +{
42860 + return (addr << DTD_DESC_START_SHIFT) |
42861 + (write_desc << DTD_WRITE_DESC_SHIFT) |
42862 + (drop_data << DTD_DROP_DATA_SHIFT) |
42863 + use_desc;
42864 +}
42865 +
42866 +static inline u32 dtd_start_h_v(int h_start, int v_start)
42867 +{
42868 + return (h_start << DTD_H_START_SHFT) | v_start;
42869 +}
42870 +
42871 +static inline u32 dtd_max_width_height(int max_width, int max_height)
42872 +{
42873 + return (max_width << DTD_MAX_WIDTH_SHFT) | max_height;
42874 +}
42875 +
42876 +static inline int dtd_get_data_type(struct vpdma_dtd *dtd)
42877 +{
42878 + return dtd->type_ctl_stride >> DTD_DATA_TYPE_SHFT;
42879 +}
42880 +
42881 +static inline bool dtd_get_notify(struct vpdma_dtd *dtd)
42882 +{
42883 + return (dtd->type_ctl_stride >> DTD_NOTIFY_SHFT) & DTD_NOTIFY_MASK;
42884 +}
42885 +
42886 +static inline int dtd_get_field(struct vpdma_dtd *dtd)
42887 +{
42888 + return (dtd->type_ctl_stride >> DTD_FIELD_SHFT) & DTD_FIELD_MASK;
42889 +}
42890 +
42891 +static inline bool dtd_get_1d(struct vpdma_dtd *dtd)
42892 +{
42893 + return (dtd->type_ctl_stride >> DTD_1D_SHFT) & DTD_1D_MASK;
42894 +}
42895 +
42896 +static inline bool dtd_get_even_line_skip(struct vpdma_dtd *dtd)
42897 +{
42898 + return (dtd->type_ctl_stride >> DTD_EVEN_LINE_SKIP_SHFT)
42899 + & DTD_EVEN_LINE_SKIP_MASK;
42900 +}
42901 +
42902 +static inline bool dtd_get_odd_line_skip(struct vpdma_dtd *dtd)
42903 +{
42904 + return (dtd->type_ctl_stride >> DTD_ODD_LINE_SKIP_SHFT)
42905 + & DTD_ODD_LINE_SKIP_MASK;
42906 +}
42907 +
42908 +static inline int dtd_get_line_stride(struct vpdma_dtd *dtd)
42909 +{
42910 + return dtd->type_ctl_stride & DTD_LINE_STRIDE_MASK;
42911 +}
42912 +
42913 +static inline int dtd_get_line_length(struct vpdma_dtd *dtd)
42914 +{
42915 + return dtd->xfer_length_height >> DTD_LINE_LENGTH_SHFT;
42916 +}
42917 +
42918 +static inline int dtd_get_xfer_height(struct vpdma_dtd *dtd)
42919 +{
42920 + return dtd->xfer_length_height & DTD_XFER_HEIGHT_MASK;
42921 +}
42922 +
42923 +static inline int dtd_get_pkt_type(struct vpdma_dtd *dtd)
42924 +{
42925 + return dtd->pkt_ctl >> DTD_PKT_TYPE_SHFT;
42926 +}
42927 +
42928 +static inline bool dtd_get_mode(struct vpdma_dtd *dtd)
42929 +{
42930 + return (dtd->pkt_ctl >> DTD_MODE_SHFT) & DTD_MODE_MASK;
42931 +}
42932 +
42933 +static inline bool dtd_get_dir(struct vpdma_dtd *dtd)
42934 +{
42935 + return (dtd->pkt_ctl >> DTD_DIR_SHFT) & DTD_DIR_MASK;
42936 +}
42937 +
42938 +static inline int dtd_get_chan(struct vpdma_dtd *dtd)
42939 +{
42940 + return (dtd->pkt_ctl >> DTD_CHAN_SHFT) & DTD_CHAN_MASK;
42941 +}
42942 +
42943 +static inline int dtd_get_priority(struct vpdma_dtd *dtd)
42944 +{
42945 + return (dtd->pkt_ctl >> DTD_PRI_SHFT) & DTD_PRI_MASK;
42946 +}
42947 +
42948 +static inline int dtd_get_next_chan(struct vpdma_dtd *dtd)
42949 +{
42950 + return (dtd->pkt_ctl >> DTD_NEXT_CHAN_SHFT) & DTD_NEXT_CHAN_MASK;
42951 +}
42952 +
42953 +static inline int dtd_get_frame_width(struct vpdma_dtd *dtd)
42954 +{
42955 + return dtd->frame_width_height >> DTD_FRAME_WIDTH_SHFT;
42956 +}
42957 +
42958 +static inline int dtd_get_frame_height(struct vpdma_dtd *dtd)
42959 +{
42960 + return dtd->frame_width_height & DTD_FRAME_HEIGHT_MASK;
42961 +}
42962 +
42963 +static inline int dtd_get_desc_write_addr(struct vpdma_dtd *dtd)
42964 +{
42965 + return dtd->desc_write_addr >> DTD_DESC_START_SHIFT;
42966 +}
42967 +
42968 +static inline bool dtd_get_write_desc(struct vpdma_dtd *dtd)
42969 +{
42970 + return (dtd->desc_write_addr >> DTD_WRITE_DESC_SHIFT) &
42971 + DTD_WRITE_DESC_MASK;
42972 +}
42973 +
42974 +static inline bool dtd_get_drop_data(struct vpdma_dtd *dtd)
42975 +{
42976 + return (dtd->desc_write_addr >> DTD_DROP_DATA_SHIFT) &
42977 + DTD_DROP_DATA_MASK;
42978 +}
42979 +
42980 +static inline bool dtd_get_use_desc(struct vpdma_dtd *dtd)
42981 +{
42982 + return dtd->desc_write_addr & DTD_USE_DESC_MASK;
42983 +}
42984 +
42985 +static inline int dtd_get_h_start(struct vpdma_dtd *dtd)
42986 +{
42987 + return dtd->start_h_v >> DTD_H_START_SHFT;
42988 +}
42989 +
42990 +static inline int dtd_get_v_start(struct vpdma_dtd *dtd)
42991 +{
42992 + return dtd->start_h_v & DTD_V_START_MASK;
42993 +}
42994 +
42995 +static inline int dtd_get_max_width(struct vpdma_dtd *dtd)
42996 +{
42997 + return (dtd->max_width_height >> DTD_MAX_WIDTH_SHFT) &
42998 + DTD_MAX_WIDTH_MASK;
42999 +}
43000 +
43001 +static inline int dtd_get_max_height(struct vpdma_dtd *dtd)
43002 +{
43003 + return (dtd->max_width_height >> DTD_MAX_HEIGHT_SHFT) &
43004 + DTD_MAX_HEIGHT_MASK;
43005 +}
43006 +
43007 +/*
43008 + * configuration descriptor
43009 + */
43010 +struct vpdma_cfd {
43011 + union {
43012 + u32 dest_addr_offset;
43013 + u32 w0;
43014 + };
43015 + union {
43016 + u32 block_len; /* in words */
43017 + u32 w1;
43018 + };
43019 + u32 payload_addr;
43020 + u32 ctl_payload_len; /* in words */
43021 +};
43022 +
43023 +/* Configuration descriptor specifics */
43024 +
43025 +#define CFD_PKT_TYPE 0xb
43026 +
43027 +#define CFD_DIRECT 1
43028 +#define CFD_INDIRECT 0
43029 +#define CFD_CLS_ADB 0
43030 +#define CFD_CLS_BLOCK 1
43031 +
43032 +/* block_len */
43033 +#define CFD__BLOCK_LEN_MASK 0xffff
43034 +#define CFD__BLOCK_LEN_SHFT 0
43035 +
43036 +/* ctl_payload_len */
43037 +#define CFD_PKT_TYPE_MASK 0x1f
43038 +#define CFD_PKT_TYPE_SHFT 27
43039 +#define CFD_DIRECT_MASK 0x01
43040 +#define CFD_DIRECT_SHFT 26
43041 +#define CFD_CLASS_MASK 0x03
43042 +#define CFD_CLASS_SHFT 24
43043 +#define CFD_DEST_MASK 0xff
43044 +#define CFD_DEST_SHFT 16
43045 +#define CFD_PAYLOAD_LEN_MASK 0xffff
43046 +#define CFD_PAYLOAD_LEN_SHFT 0
43047 +
43048 +static inline u32 cfd_pkt_payload_len(bool direct, int cls, int dest,
43049 + int payload_len)
43050 +{
43051 + return (CFD_PKT_TYPE << CFD_PKT_TYPE_SHFT) |
43052 + (direct << CFD_DIRECT_SHFT) |
43053 + (cls << CFD_CLASS_SHFT) |
43054 + (dest << CFD_DEST_SHFT) |
43055 + payload_len;
43056 +}
43057 +
43058 +static inline int cfd_get_pkt_type(struct vpdma_cfd *cfd)
43059 +{
43060 + return cfd->ctl_payload_len >> CFD_PKT_TYPE_SHFT;
43061 +}
43062 +
43063 +static inline bool cfd_get_direct(struct vpdma_cfd *cfd)
43064 +{
43065 + return (cfd->ctl_payload_len >> CFD_DIRECT_SHFT) & CFD_DIRECT_MASK;
43066 +}
43067 +
43068 +static inline bool cfd_get_class(struct vpdma_cfd *cfd)
43069 +{
43070 + return (cfd->ctl_payload_len >> CFD_CLASS_SHFT) & CFD_CLASS_MASK;
43071 +}
43072 +
43073 +static inline int cfd_get_dest(struct vpdma_cfd *cfd)
43074 +{
43075 + return (cfd->ctl_payload_len >> CFD_DEST_SHFT) & CFD_DEST_MASK;
43076 +}
43077 +
43078 +static inline int cfd_get_payload_len(struct vpdma_cfd *cfd)
43079 +{
43080 + return cfd->ctl_payload_len & CFD_PAYLOAD_LEN_MASK;
43081 +}
43082 +
43083 +/*
43084 + * control descriptor
43085 + */
43086 +struct vpdma_ctd {
43087 + union {
43088 + u32 timer_value;
43089 + u32 list_addr;
43090 + u32 w0;
43091 + };
43092 + union {
43093 + u32 pixel_line_count;
43094 + u32 list_size;
43095 + u32 w1;
43096 + };
43097 + union {
43098 + u32 event;
43099 + u32 fid_ctl;
43100 + u32 w2;
43101 + };
43102 + u32 type_source_ctl;
43103 +};
43104 +
43105 +/* control descriptor types */
43106 +#define CTD_TYPE_SYNC_ON_CLIENT 0
43107 +#define CTD_TYPE_SYNC_ON_LIST 1
43108 +#define CTD_TYPE_SYNC_ON_EXT 2
43109 +#define CTD_TYPE_SYNC_ON_LM_TIMER 3
43110 +#define CTD_TYPE_SYNC_ON_CHANNEL 4
43111 +#define CTD_TYPE_CHNG_CLIENT_IRQ 5
43112 +#define CTD_TYPE_SEND_IRQ 6
43113 +#define CTD_TYPE_RELOAD_LIST 7
43114 +#define CTD_TYPE_ABORT_CHANNEL 8
43115 +
43116 +#define CTD_PKT_TYPE 0xc
43117 +
43118 +/* timer_value */
43119 +#define CTD_TIMER_VALUE_MASK 0xffff
43120 +#define CTD_TIMER_VALUE_SHFT 0
43121 +
43122 +/* pixel_line_count */
43123 +#define CTD_PIXEL_COUNT_MASK 0xffff
43124 +#define CTD_PIXEL_COUNT_SHFT 16
43125 +#define CTD_LINE_COUNT_MASK 0xffff
43126 +#define CTD_LINE_COUNT_SHFT 0
43127 +
43128 +/* list_size */
43129 +#define CTD_LIST_SIZE_MASK 0xffff
43130 +#define CTD_LIST_SIZE_SHFT 0
43131 +
43132 +/* event */
43133 +#define CTD_EVENT_MASK 0x0f
43134 +#define CTD_EVENT_SHFT 0
43135 +
43136 +/* fid_ctl */
43137 +#define CTD_FID2_MASK 0x03
43138 +#define CTD_FID2_SHFT 4
43139 +#define CTD_FID1_MASK 0x03
43140 +#define CTD_FID1_SHFT 2
43141 +#define CTD_FID0_MASK 0x03
43142 +#define CTD_FID0_SHFT 0
43143 +
43144 +/* type_source_ctl */
43145 +#define CTD_PKT_TYPE_MASK 0x1f
43146 +#define CTD_PKT_TYPE_SHFT 27
43147 +#define CTD_SOURCE_MASK 0xff
43148 +#define CTD_SOURCE_SHFT 16
43149 +#define CTD_CONTROL_MASK 0x0f
43150 +#define CTD_CONTROL_SHFT 0
43151 +
43152 +static inline u32 ctd_pixel_line_count(int pixel_count, int line_count)
43153 +{
43154 + return (pixel_count << CTD_PIXEL_COUNT_SHFT) | line_count;
43155 +}
43156 +
43157 +static inline u32 ctd_set_fid_ctl(int fid0, int fid1, int fid2)
43158 +{
43159 + return (fid2 << CTD_FID2_SHFT) | (fid1 << CTD_FID1_SHFT) | fid0;
43160 +}
43161 +
43162 +static inline u32 ctd_type_source_ctl(int source, int control)
43163 +{
43164 + return (CTD_PKT_TYPE << CTD_PKT_TYPE_SHFT) |
43165 + (source << CTD_SOURCE_SHFT) | control;
43166 +}
43167 +
43168 +static inline u32 ctd_get_pixel_count(struct vpdma_ctd *ctd)
43169 +{
43170 + return ctd->pixel_line_count >> CTD_PIXEL_COUNT_SHFT;
43171 +}
43172 +
43173 +static inline int ctd_get_line_count(struct vpdma_ctd *ctd)
43174 +{
43175 + return ctd->pixel_line_count & CTD_LINE_COUNT_MASK;
43176 +}
43177 +
43178 +static inline int ctd_get_event(struct vpdma_ctd *ctd)
43179 +{
43180 + return ctd->event & CTD_EVENT_MASK;
43181 +}
43182 +
43183 +static inline int ctd_get_fid2_ctl(struct vpdma_ctd *ctd)
43184 +{
43185 + return (ctd->fid_ctl >> CTD_FID2_SHFT) & CTD_FID2_MASK;
43186 +}
43187 +
43188 +static inline int ctd_get_fid1_ctl(struct vpdma_ctd *ctd)
43189 +{
43190 + return (ctd->fid_ctl >> CTD_FID1_SHFT) & CTD_FID1_MASK;
43191 +}
43192 +
43193 +static inline int ctd_get_fid0_ctl(struct vpdma_ctd *ctd)
43194 +{
43195 + return ctd->fid_ctl & CTD_FID2_MASK;
43196 +}
43197 +
43198 +static inline int ctd_get_pkt_type(struct vpdma_ctd *ctd)
43199 +{
43200 + return ctd->type_source_ctl >> CTD_PKT_TYPE_SHFT;
43201 +}
43202 +
43203 +static inline int ctd_get_source(struct vpdma_ctd *ctd)
43204 +{
43205 + return (ctd->type_source_ctl >> CTD_SOURCE_SHFT) & CTD_SOURCE_MASK;
43206 +}
43207 +
43208 +static inline int ctd_get_ctl(struct vpdma_ctd *ctd)
43209 +{
43210 + return ctd->type_source_ctl & CTD_CONTROL_MASK;
43211 +}
43212 +
43213 +#endif
43214 --- /dev/null
43215 +++ b/drivers/media/platform/ti-vpe/vpe.c
43216 @@ -0,0 +1,2074 @@
43217 +/*
43218 + * TI VPE mem2mem driver, based on the virtual v4l2-mem2mem example driver
43219 + *
43220 + * Copyright (c) 2013 Texas Instruments Inc.
43221 + * David Griego, <dagriego@biglakesoftware.com>
43222 + * Dale Farnsworth, <dale@farnsworth.org>
43223 + * Archit Taneja, <archit@ti.com>
43224 + *
43225 + * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
43226 + * Pawel Osciak, <pawel@osciak.com>
43227 + * Marek Szyprowski, <m.szyprowski@samsung.com>
43228 + *
43229 + * Based on the virtual v4l2-mem2mem example device
43230 + *
43231 + * This program is free software; you can redistribute it and/or modify it
43232 + * under the terms of the GNU General Public License version 2 as published by
43233 + * the Free Software Foundation
43234 + */
43235 +
43236 +#include <linux/delay.h>
43237 +#include <linux/dma-mapping.h>
43238 +#include <linux/err.h>
43239 +#include <linux/fs.h>
43240 +#include <linux/interrupt.h>
43241 +#include <linux/io.h>
43242 +#include <linux/ioctl.h>
43243 +#include <linux/module.h>
43244 +#include <linux/platform_device.h>
43245 +#include <linux/pm_runtime.h>
43246 +#include <linux/sched.h>
43247 +#include <linux/slab.h>
43248 +#include <linux/videodev2.h>
43249 +
43250 +#include <media/v4l2-common.h>
43251 +#include <media/v4l2-ctrls.h>
43252 +#include <media/v4l2-device.h>
43253 +#include <media/v4l2-event.h>
43254 +#include <media/v4l2-ioctl.h>
43255 +#include <media/v4l2-mem2mem.h>
43256 +#include <media/videobuf2-core.h>
43257 +#include <media/videobuf2-dma-contig.h>
43258 +
43259 +#include "vpdma.h"
43260 +#include "vpe_regs.h"
43261 +
43262 +#define VPE_MODULE_NAME "vpe"
43263 +
43264 +/* minimum and maximum frame sizes */
43265 +#define MIN_W 128
43266 +#define MIN_H 128
43267 +#define MAX_W 1920
43268 +#define MAX_H 1080
43269 +
43270 +/* required alignments */
43271 +#define S_ALIGN 0 /* multiple of 1 */
43272 +#define H_ALIGN 1 /* multiple of 2 */
43273 +#define W_ALIGN 1 /* multiple of 2 */
43274 +
43275 +/* multiple of 128 bits, line stride, 16 bytes */
43276 +#define L_ALIGN 4
43277 +
43278 +/* flags that indicate a format can be used for capture/output */
43279 +#define VPE_FMT_TYPE_CAPTURE (1 << 0)
43280 +#define VPE_FMT_TYPE_OUTPUT (1 << 1)
43281 +
43282 +/* used as plane indices */
43283 +#define VPE_MAX_PLANES 2
43284 +#define VPE_LUMA 0
43285 +#define VPE_CHROMA 1
43286 +
43287 +/* per m2m context info */
43288 +#define VPE_MAX_SRC_BUFS 3 /* need 3 src fields to de-interlace */
43289 +
43290 +#define VPE_DEF_BUFS_PER_JOB 1 /* default one buffer per batch job */
43291 +
43292 +/*
43293 + * each VPE context can need up to 3 config desciptors, 7 input descriptors,
43294 + * 3 output descriptors, and 10 control descriptors
43295 + */
43296 +#define VPE_DESC_LIST_SIZE (10 * VPDMA_DTD_DESC_SIZE + \
43297 + 13 * VPDMA_CFD_CTD_DESC_SIZE)
43298 +
43299 +#define vpe_dbg(vpedev, fmt, arg...) \
43300 + dev_dbg((vpedev)->v4l2_dev.dev, fmt, ##arg)
43301 +#define vpe_err(vpedev, fmt, arg...) \
43302 + dev_err((vpedev)->v4l2_dev.dev, fmt, ##arg)
43303 +
43304 +struct vpe_us_coeffs {
43305 + unsigned short anchor_fid0_c0;
43306 + unsigned short anchor_fid0_c1;
43307 + unsigned short anchor_fid0_c2;
43308 + unsigned short anchor_fid0_c3;
43309 + unsigned short interp_fid0_c0;
43310 + unsigned short interp_fid0_c1;
43311 + unsigned short interp_fid0_c2;
43312 + unsigned short interp_fid0_c3;
43313 + unsigned short anchor_fid1_c0;
43314 + unsigned short anchor_fid1_c1;
43315 + unsigned short anchor_fid1_c2;
43316 + unsigned short anchor_fid1_c3;
43317 + unsigned short interp_fid1_c0;
43318 + unsigned short interp_fid1_c1;
43319 + unsigned short interp_fid1_c2;
43320 + unsigned short interp_fid1_c3;
43321 +};
43322 +
43323 +/*
43324 + * Default upsampler coefficients
43325 + */
43326 +static const struct vpe_us_coeffs us_coeffs[] = {
43327 + {
43328 + /* Coefficients for progressive input */
43329 + 0x00C8, 0x0348, 0x0018, 0x3FD8, 0x3FB8, 0x0378, 0x00E8, 0x3FE8,
43330 + 0x00C8, 0x0348, 0x0018, 0x3FD8, 0x3FB8, 0x0378, 0x00E8, 0x3FE8,
43331 + },
43332 + {
43333 + /* Coefficients for Top Field Interlaced input */
43334 + 0x0051, 0x03D5, 0x3FE3, 0x3FF7, 0x3FB5, 0x02E9, 0x018F, 0x3FD3,
43335 + /* Coefficients for Bottom Field Interlaced input */
43336 + 0x016B, 0x0247, 0x00B1, 0x3F9D, 0x3FCF, 0x03DB, 0x005D, 0x3FF9,
43337 + },
43338 +};
43339 +
43340 +/*
43341 + * the following registers are for configuring some of the parameters of the
43342 + * motion and edge detection blocks inside DEI, these generally remain the same,
43343 + * these could be passed later via userspace if some one needs to tweak these.
43344 + */
43345 +struct vpe_dei_regs {
43346 + unsigned long mdt_spacial_freq_thr_reg; /* VPE_DEI_REG2 */
43347 + unsigned long edi_config_reg; /* VPE_DEI_REG3 */
43348 + unsigned long edi_lut_reg0; /* VPE_DEI_REG4 */
43349 + unsigned long edi_lut_reg1; /* VPE_DEI_REG5 */
43350 + unsigned long edi_lut_reg2; /* VPE_DEI_REG6 */
43351 + unsigned long edi_lut_reg3; /* VPE_DEI_REG7 */
43352 +};
43353 +
43354 +/*
43355 + * default expert DEI register values, unlikely to be modified.
43356 + */
43357 +static const struct vpe_dei_regs dei_regs = {
43358 + 0x020C0804u,
43359 + 0x0118100Fu,
43360 + 0x08040200u,
43361 + 0x1010100Cu,
43362 + 0x10101010u,
43363 + 0x10101010u,
43364 +};
43365 +
43366 +/*
43367 + * The port_data structure contains per-port data.
43368 + */
43369 +struct vpe_port_data {
43370 + enum vpdma_channel channel; /* VPDMA channel */
43371 + u8 vb_index; /* input frame f, f-1, f-2 index */
43372 + u8 vb_part; /* plane index for co-panar formats */
43373 +};
43374 +
43375 +/*
43376 + * Define indices into the port_data tables
43377 + */
43378 +#define VPE_PORT_LUMA1_IN 0
43379 +#define VPE_PORT_CHROMA1_IN 1
43380 +#define VPE_PORT_LUMA2_IN 2
43381 +#define VPE_PORT_CHROMA2_IN 3
43382 +#define VPE_PORT_LUMA3_IN 4
43383 +#define VPE_PORT_CHROMA3_IN 5
43384 +#define VPE_PORT_MV_IN 6
43385 +#define VPE_PORT_MV_OUT 7
43386 +#define VPE_PORT_LUMA_OUT 8
43387 +#define VPE_PORT_CHROMA_OUT 9
43388 +#define VPE_PORT_RGB_OUT 10
43389 +
43390 +static const struct vpe_port_data port_data[11] = {
43391 + [VPE_PORT_LUMA1_IN] = {
43392 + .channel = VPE_CHAN_LUMA1_IN,
43393 + .vb_index = 0,
43394 + .vb_part = VPE_LUMA,
43395 + },
43396 + [VPE_PORT_CHROMA1_IN] = {
43397 + .channel = VPE_CHAN_CHROMA1_IN,
43398 + .vb_index = 0,
43399 + .vb_part = VPE_CHROMA,
43400 + },
43401 + [VPE_PORT_LUMA2_IN] = {
43402 + .channel = VPE_CHAN_LUMA2_IN,
43403 + .vb_index = 1,
43404 + .vb_part = VPE_LUMA,
43405 + },
43406 + [VPE_PORT_CHROMA2_IN] = {
43407 + .channel = VPE_CHAN_CHROMA2_IN,
43408 + .vb_index = 1,
43409 + .vb_part = VPE_CHROMA,
43410 + },
43411 + [VPE_PORT_LUMA3_IN] = {
43412 + .channel = VPE_CHAN_LUMA3_IN,
43413 + .vb_index = 2,
43414 + .vb_part = VPE_LUMA,
43415 + },
43416 + [VPE_PORT_CHROMA3_IN] = {
43417 + .channel = VPE_CHAN_CHROMA3_IN,
43418 + .vb_index = 2,
43419 + .vb_part = VPE_CHROMA,
43420 + },
43421 + [VPE_PORT_MV_IN] = {
43422 + .channel = VPE_CHAN_MV_IN,
43423 + },
43424 + [VPE_PORT_MV_OUT] = {
43425 + .channel = VPE_CHAN_MV_OUT,
43426 + },
43427 + [VPE_PORT_LUMA_OUT] = {
43428 + .channel = VPE_CHAN_LUMA_OUT,
43429 + .vb_part = VPE_LUMA,
43430 + },
43431 + [VPE_PORT_CHROMA_OUT] = {
43432 + .channel = VPE_CHAN_CHROMA_OUT,
43433 + .vb_part = VPE_CHROMA,
43434 + },
43435 + [VPE_PORT_RGB_OUT] = {
43436 + .channel = VPE_CHAN_RGB_OUT,
43437 + .vb_part = VPE_LUMA,
43438 + },
43439 +};
43440 +
43441 +
43442 +/* driver info for each of the supported video formats */
43443 +struct vpe_fmt {
43444 + char *name; /* human-readable name */
43445 + u32 fourcc; /* standard format identifier */
43446 + u8 types; /* CAPTURE and/or OUTPUT */
43447 + u8 coplanar; /* set for unpacked Luma and Chroma */
43448 + /* vpdma format info for each plane */
43449 + struct vpdma_data_format const *vpdma_fmt[VPE_MAX_PLANES];
43450 +};
43451 +
43452 +static struct vpe_fmt vpe_formats[] = {
43453 + {
43454 + .name = "YUV 422 co-planar",
43455 + .fourcc = V4L2_PIX_FMT_NV16,
43456 + .types = VPE_FMT_TYPE_CAPTURE | VPE_FMT_TYPE_OUTPUT,
43457 + .coplanar = 1,
43458 + .vpdma_fmt = { &vpdma_yuv_fmts[VPDMA_DATA_FMT_Y444],
43459 + &vpdma_yuv_fmts[VPDMA_DATA_FMT_C444],
43460 + },
43461 + },
43462 + {
43463 + .name = "YUV 420 co-planar",
43464 + .fourcc = V4L2_PIX_FMT_NV12,
43465 + .types = VPE_FMT_TYPE_CAPTURE | VPE_FMT_TYPE_OUTPUT,
43466 + .coplanar = 1,
43467 + .vpdma_fmt = { &vpdma_yuv_fmts[VPDMA_DATA_FMT_Y420],
43468 + &vpdma_yuv_fmts[VPDMA_DATA_FMT_C420],
43469 + },
43470 + },
43471 + {
43472 + .name = "YUYV 422 packed",
43473 + .fourcc = V4L2_PIX_FMT_YUYV,
43474 + .types = VPE_FMT_TYPE_CAPTURE | VPE_FMT_TYPE_OUTPUT,
43475 + .coplanar = 0,
43476 + .vpdma_fmt = { &vpdma_yuv_fmts[VPDMA_DATA_FMT_YC422],
43477 + },
43478 + },
43479 + {
43480 + .name = "UYVY 422 packed",
43481 + .fourcc = V4L2_PIX_FMT_UYVY,
43482 + .types = VPE_FMT_TYPE_CAPTURE | VPE_FMT_TYPE_OUTPUT,
43483 + .coplanar = 0,
43484 + .vpdma_fmt = { &vpdma_yuv_fmts[VPDMA_DATA_FMT_CY422],
43485 + },
43486 + },
43487 +};
43488 +
43489 +/*
43490 + * per-queue, driver-specific private data.
43491 + * there is one source queue and one destination queue for each m2m context.
43492 + */
43493 +struct vpe_q_data {
43494 + unsigned int width; /* frame width */
43495 + unsigned int height; /* frame height */
43496 + unsigned int bytesperline[VPE_MAX_PLANES]; /* bytes per line in memory */
43497 + enum v4l2_colorspace colorspace;
43498 + enum v4l2_field field; /* supported field value */
43499 + unsigned int flags;
43500 + unsigned int sizeimage[VPE_MAX_PLANES]; /* image size in memory */
43501 + struct v4l2_rect c_rect; /* crop/compose rectangle */
43502 + struct vpe_fmt *fmt; /* format info */
43503 +};
43504 +
43505 +/* vpe_q_data flag bits */
43506 +#define Q_DATA_FRAME_1D (1 << 0)
43507 +#define Q_DATA_MODE_TILED (1 << 1)
43508 +#define Q_DATA_INTERLACED (1 << 2)
43509 +
43510 +enum {
43511 + Q_DATA_SRC = 0,
43512 + Q_DATA_DST = 1,
43513 +};
43514 +
43515 +/* find our format description corresponding to the passed v4l2_format */
43516 +static struct vpe_fmt *find_format(struct v4l2_format *f)
43517 +{
43518 + struct vpe_fmt *fmt;
43519 + unsigned int k;
43520 +
43521 + for (k = 0; k < ARRAY_SIZE(vpe_formats); k++) {
43522 + fmt = &vpe_formats[k];
43523 + if (fmt->fourcc == f->fmt.pix.pixelformat)
43524 + return fmt;
43525 + }
43526 +
43527 + return NULL;
43528 +}
43529 +
43530 +/*
43531 + * there is one vpe_dev structure in the driver, it is shared by
43532 + * all instances.
43533 + */
43534 +struct vpe_dev {
43535 + struct v4l2_device v4l2_dev;
43536 + struct video_device vfd;
43537 + struct v4l2_m2m_dev *m2m_dev;
43538 +
43539 + atomic_t num_instances; /* count of driver instances */
43540 + dma_addr_t loaded_mmrs; /* shadow mmrs in device */
43541 + struct mutex dev_mutex;
43542 + spinlock_t lock;
43543 +
43544 + int irq;
43545 + void __iomem *base;
43546 +
43547 + struct vb2_alloc_ctx *alloc_ctx;
43548 + struct vpdma_data *vpdma; /* vpdma data handle */
43549 +};
43550 +
43551 +/*
43552 + * There is one vpe_ctx structure for each m2m context.
43553 + */
43554 +struct vpe_ctx {
43555 + struct v4l2_fh fh;
43556 + struct vpe_dev *dev;
43557 + struct v4l2_m2m_ctx *m2m_ctx;
43558 + struct v4l2_ctrl_handler hdl;
43559 +
43560 + unsigned int field; /* current field */
43561 + unsigned int sequence; /* current frame/field seq */
43562 + unsigned int aborting; /* abort after next irq */
43563 +
43564 + unsigned int bufs_per_job; /* input buffers per batch */
43565 + unsigned int bufs_completed; /* bufs done in this batch */
43566 +
43567 + struct vpe_q_data q_data[2]; /* src & dst queue data */
43568 + struct vb2_buffer *src_vbs[VPE_MAX_SRC_BUFS];
43569 + struct vb2_buffer *dst_vb;
43570 +
43571 + dma_addr_t mv_buf_dma[2]; /* dma addrs of motion vector in/out bufs */
43572 + void *mv_buf[2]; /* virtual addrs of motion vector bufs */
43573 + size_t mv_buf_size; /* current motion vector buffer size */
43574 + struct vpdma_buf mmr_adb; /* shadow reg addr/data block */
43575 + struct vpdma_desc_list desc_list; /* DMA descriptor list */
43576 +
43577 + bool deinterlacing; /* using de-interlacer */
43578 + bool load_mmrs; /* have new shadow reg values */
43579 +
43580 + unsigned int src_mv_buf_selector;
43581 +};
43582 +
43583 +
43584 +/*
43585 + * M2M devices get 2 queues.
43586 + * Return the queue given the type.
43587 + */
43588 +static struct vpe_q_data *get_q_data(struct vpe_ctx *ctx,
43589 + enum v4l2_buf_type type)
43590 +{
43591 + switch (type) {
43592 + case V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE:
43593 + return &ctx->q_data[Q_DATA_SRC];
43594 + case V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE:
43595 + return &ctx->q_data[Q_DATA_DST];
43596 + default:
43597 + BUG();
43598 + }
43599 + return NULL;
43600 +}
43601 +
43602 +static u32 read_reg(struct vpe_dev *dev, int offset)
43603 +{
43604 + return ioread32(dev->base + offset);
43605 +}
43606 +
43607 +static void write_reg(struct vpe_dev *dev, int offset, u32 value)
43608 +{
43609 + iowrite32(value, dev->base + offset);
43610 +}
43611 +
43612 +/* register field read/write helpers */
43613 +static int get_field(u32 value, u32 mask, int shift)
43614 +{
43615 + return (value & (mask << shift)) >> shift;
43616 +}
43617 +
43618 +static int read_field_reg(struct vpe_dev *dev, int offset, u32 mask, int shift)
43619 +{
43620 + return get_field(read_reg(dev, offset), mask, shift);
43621 +}
43622 +
43623 +static void write_field(u32 *valp, u32 field, u32 mask, int shift)
43624 +{
43625 + u32 val = *valp;
43626 +
43627 + val &= ~(mask << shift);
43628 + val |= (field & mask) << shift;
43629 + *valp = val;
43630 +}
43631 +
43632 +static void write_field_reg(struct vpe_dev *dev, int offset, u32 field,
43633 + u32 mask, int shift)
43634 +{
43635 + u32 val = read_reg(dev, offset);
43636 +
43637 + write_field(&val, field, mask, shift);
43638 +
43639 + write_reg(dev, offset, val);
43640 +}
43641 +
43642 +/*
43643 + * DMA address/data block for the shadow registers
43644 + */
43645 +struct vpe_mmr_adb {
43646 + struct vpdma_adb_hdr out_fmt_hdr;
43647 + u32 out_fmt_reg[1];
43648 + u32 out_fmt_pad[3];
43649 + struct vpdma_adb_hdr us1_hdr;
43650 + u32 us1_regs[8];
43651 + struct vpdma_adb_hdr us2_hdr;
43652 + u32 us2_regs[8];
43653 + struct vpdma_adb_hdr us3_hdr;
43654 + u32 us3_regs[8];
43655 + struct vpdma_adb_hdr dei_hdr;
43656 + u32 dei_regs[8];
43657 + struct vpdma_adb_hdr sc_hdr;
43658 + u32 sc_regs[1];
43659 + u32 sc_pad[3];
43660 + struct vpdma_adb_hdr csc_hdr;
43661 + u32 csc_regs[6];
43662 + u32 csc_pad[2];
43663 +};
43664 +
43665 +#define VPE_SET_MMR_ADB_HDR(ctx, hdr, regs, offset_a) \
43666 + VPDMA_SET_MMR_ADB_HDR(ctx->mmr_adb, vpe_mmr_adb, hdr, regs, offset_a)
43667 +/*
43668 + * Set the headers for all of the address/data block structures.
43669 + */
43670 +static void init_adb_hdrs(struct vpe_ctx *ctx)
43671 +{
43672 + VPE_SET_MMR_ADB_HDR(ctx, out_fmt_hdr, out_fmt_reg, VPE_CLK_FORMAT_SELECT);
43673 + VPE_SET_MMR_ADB_HDR(ctx, us1_hdr, us1_regs, VPE_US1_R0);
43674 + VPE_SET_MMR_ADB_HDR(ctx, us2_hdr, us2_regs, VPE_US2_R0);
43675 + VPE_SET_MMR_ADB_HDR(ctx, us3_hdr, us3_regs, VPE_US3_R0);
43676 + VPE_SET_MMR_ADB_HDR(ctx, dei_hdr, dei_regs, VPE_DEI_FRAME_SIZE);
43677 + VPE_SET_MMR_ADB_HDR(ctx, sc_hdr, sc_regs, VPE_SC_MP_SC0);
43678 + VPE_SET_MMR_ADB_HDR(ctx, csc_hdr, csc_regs, VPE_CSC_CSC00);
43679 +};
43680 +
43681 +/*
43682 + * Allocate or re-allocate the motion vector DMA buffers
43683 + * There are two buffers, one for input and one for output.
43684 + * However, the roles are reversed after each field is processed.
43685 + * In other words, after each field is processed, the previous
43686 + * output (dst) MV buffer becomes the new input (src) MV buffer.
43687 + */
43688 +static int realloc_mv_buffers(struct vpe_ctx *ctx, size_t size)
43689 +{
43690 + struct device *dev = ctx->dev->v4l2_dev.dev;
43691 +
43692 + if (ctx->mv_buf_size == size)
43693 + return 0;
43694 +
43695 + if (ctx->mv_buf[0])
43696 + dma_free_coherent(dev, ctx->mv_buf_size, ctx->mv_buf[0],
43697 + ctx->mv_buf_dma[0]);
43698 +
43699 + if (ctx->mv_buf[1])
43700 + dma_free_coherent(dev, ctx->mv_buf_size, ctx->mv_buf[1],
43701 + ctx->mv_buf_dma[1]);
43702 +
43703 + if (size == 0)
43704 + return 0;
43705 +
43706 + ctx->mv_buf[0] = dma_alloc_coherent(dev, size, &ctx->mv_buf_dma[0],
43707 + GFP_KERNEL);
43708 + if (!ctx->mv_buf[0]) {
43709 + vpe_err(ctx->dev, "failed to allocate motion vector buffer\n");
43710 + return -ENOMEM;
43711 + }
43712 +
43713 + ctx->mv_buf[1] = dma_alloc_coherent(dev, size, &ctx->mv_buf_dma[1],
43714 + GFP_KERNEL);
43715 + if (!ctx->mv_buf[1]) {
43716 + vpe_err(ctx->dev, "failed to allocate motion vector buffer\n");
43717 + dma_free_coherent(dev, size, ctx->mv_buf[0],
43718 + ctx->mv_buf_dma[0]);
43719 +
43720 + return -ENOMEM;
43721 + }
43722 +
43723 + ctx->mv_buf_size = size;
43724 + ctx->src_mv_buf_selector = 0;
43725 +
43726 + return 0;
43727 +}
43728 +
43729 +static void free_mv_buffers(struct vpe_ctx *ctx)
43730 +{
43731 + realloc_mv_buffers(ctx, 0);
43732 +}
43733 +
43734 +/*
43735 + * While de-interlacing, we keep the two most recent input buffers
43736 + * around. This function frees those two buffers when we have
43737 + * finished processing the current stream.
43738 + */
43739 +static void free_vbs(struct vpe_ctx *ctx)
43740 +{
43741 + struct vpe_dev *dev = ctx->dev;
43742 + unsigned long flags;
43743 +
43744 + if (ctx->src_vbs[2] == NULL)
43745 + return;
43746 +
43747 + spin_lock_irqsave(&dev->lock, flags);
43748 + if (ctx->src_vbs[2]) {
43749 + v4l2_m2m_buf_done(ctx->src_vbs[2], VB2_BUF_STATE_DONE);
43750 + v4l2_m2m_buf_done(ctx->src_vbs[1], VB2_BUF_STATE_DONE);
43751 + }
43752 + spin_unlock_irqrestore(&dev->lock, flags);
43753 +}
43754 +
43755 +/*
43756 + * Enable or disable the VPE clocks
43757 + */
43758 +static void vpe_set_clock_enable(struct vpe_dev *dev, bool on)
43759 +{
43760 + u32 val = 0;
43761 +
43762 + if (on)
43763 + val = VPE_DATA_PATH_CLK_ENABLE | VPE_VPEDMA_CLK_ENABLE;
43764 + write_reg(dev, VPE_CLK_ENABLE, val);
43765 +}
43766 +
43767 +static void vpe_top_reset(struct vpe_dev *dev)
43768 +{
43769 +
43770 + write_field_reg(dev, VPE_CLK_RESET, 1, VPE_DATA_PATH_CLK_RESET_MASK,
43771 + VPE_DATA_PATH_CLK_RESET_SHIFT);
43772 +
43773 + usleep_range(100, 150);
43774 +
43775 + write_field_reg(dev, VPE_CLK_RESET, 0, VPE_DATA_PATH_CLK_RESET_MASK,
43776 + VPE_DATA_PATH_CLK_RESET_SHIFT);
43777 +}
43778 +
43779 +static void vpe_top_vpdma_reset(struct vpe_dev *dev)
43780 +{
43781 + write_field_reg(dev, VPE_CLK_RESET, 1, VPE_VPDMA_CLK_RESET_MASK,
43782 + VPE_VPDMA_CLK_RESET_SHIFT);
43783 +
43784 + usleep_range(100, 150);
43785 +
43786 + write_field_reg(dev, VPE_CLK_RESET, 0, VPE_VPDMA_CLK_RESET_MASK,
43787 + VPE_VPDMA_CLK_RESET_SHIFT);
43788 +}
43789 +
43790 +/*
43791 + * Load the correct of upsampler coefficients into the shadow MMRs
43792 + */
43793 +static void set_us_coefficients(struct vpe_ctx *ctx)
43794 +{
43795 + struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr;
43796 + struct vpe_q_data *s_q_data = &ctx->q_data[Q_DATA_SRC];
43797 + u32 *us1_reg = &mmr_adb->us1_regs[0];
43798 + u32 *us2_reg = &mmr_adb->us2_regs[0];
43799 + u32 *us3_reg = &mmr_adb->us3_regs[0];
43800 + const unsigned short *cp, *end_cp;
43801 +
43802 + cp = &us_coeffs[0].anchor_fid0_c0;
43803 +
43804 + if (s_q_data->flags & Q_DATA_INTERLACED) /* interlaced */
43805 + cp += sizeof(us_coeffs[0]) / sizeof(*cp);
43806 +
43807 + end_cp = cp + sizeof(us_coeffs[0]) / sizeof(*cp);
43808 +
43809 + while (cp < end_cp) {
43810 + write_field(us1_reg, *cp++, VPE_US_C0_MASK, VPE_US_C0_SHIFT);
43811 + write_field(us1_reg, *cp++, VPE_US_C1_MASK, VPE_US_C1_SHIFT);
43812 + *us2_reg++ = *us1_reg;
43813 + *us3_reg++ = *us1_reg++;
43814 + }
43815 + ctx->load_mmrs = true;
43816 +}
43817 +
43818 +/*
43819 + * Set the upsampler config mode and the VPDMA line mode in the shadow MMRs.
43820 + */
43821 +static void set_cfg_and_line_modes(struct vpe_ctx *ctx)
43822 +{
43823 + struct vpe_fmt *fmt = ctx->q_data[Q_DATA_SRC].fmt;
43824 + struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr;
43825 + u32 *us1_reg0 = &mmr_adb->us1_regs[0];
43826 + u32 *us2_reg0 = &mmr_adb->us2_regs[0];
43827 + u32 *us3_reg0 = &mmr_adb->us3_regs[0];
43828 + int line_mode = 1;
43829 + int cfg_mode = 1;
43830 +
43831 + /*
43832 + * Cfg Mode 0: YUV420 source, enable upsampler, DEI is de-interlacing.
43833 + * Cfg Mode 1: YUV422 source, disable upsampler, DEI is de-interlacing.
43834 + */
43835 +
43836 + if (fmt->fourcc == V4L2_PIX_FMT_NV12) {
43837 + cfg_mode = 0;
43838 + line_mode = 0; /* double lines to line buffer */
43839 + }
43840 +
43841 + write_field(us1_reg0, cfg_mode, VPE_US_MODE_MASK, VPE_US_MODE_SHIFT);
43842 + write_field(us2_reg0, cfg_mode, VPE_US_MODE_MASK, VPE_US_MODE_SHIFT);
43843 + write_field(us3_reg0, cfg_mode, VPE_US_MODE_MASK, VPE_US_MODE_SHIFT);
43844 +
43845 + /* regs for now */
43846 + vpdma_set_line_mode(ctx->dev->vpdma, line_mode, VPE_CHAN_CHROMA1_IN);
43847 + vpdma_set_line_mode(ctx->dev->vpdma, line_mode, VPE_CHAN_CHROMA2_IN);
43848 + vpdma_set_line_mode(ctx->dev->vpdma, line_mode, VPE_CHAN_CHROMA3_IN);
43849 +
43850 + /* frame start for input luma */
43851 + vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE,
43852 + VPE_CHAN_LUMA1_IN);
43853 + vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE,
43854 + VPE_CHAN_LUMA2_IN);
43855 + vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE,
43856 + VPE_CHAN_LUMA3_IN);
43857 +
43858 + /* frame start for input chroma */
43859 + vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE,
43860 + VPE_CHAN_CHROMA1_IN);
43861 + vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE,
43862 + VPE_CHAN_CHROMA2_IN);
43863 + vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE,
43864 + VPE_CHAN_CHROMA3_IN);
43865 +
43866 + /* frame start for MV in client */
43867 + vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE,
43868 + VPE_CHAN_MV_IN);
43869 +
43870 + ctx->load_mmrs = true;
43871 +}
43872 +
43873 +/*
43874 + * Set the shadow registers that are modified when the source
43875 + * format changes.
43876 + */
43877 +static void set_src_registers(struct vpe_ctx *ctx)
43878 +{
43879 + set_us_coefficients(ctx);
43880 +}
43881 +
43882 +/*
43883 + * Set the shadow registers that are modified when the destination
43884 + * format changes.
43885 + */
43886 +static void set_dst_registers(struct vpe_ctx *ctx)
43887 +{
43888 + struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr;
43889 + struct vpe_fmt *fmt = ctx->q_data[Q_DATA_DST].fmt;
43890 + u32 val = 0;
43891 +
43892 + /* select RGB path when color space conversion is supported in future */
43893 + if (fmt->fourcc == V4L2_PIX_FMT_RGB24)
43894 + val |= VPE_RGB_OUT_SELECT | VPE_CSC_SRC_DEI_SCALER;
43895 + else if (fmt->fourcc == V4L2_PIX_FMT_NV16)
43896 + val |= VPE_COLOR_SEPARATE_422;
43897 +
43898 + /* The source of CHR_DS is always the scaler, whether it's used or not */
43899 + val |= VPE_DS_SRC_DEI_SCALER;
43900 +
43901 + if (fmt->fourcc != V4L2_PIX_FMT_NV12)
43902 + val |= VPE_DS_BYPASS;
43903 +
43904 + mmr_adb->out_fmt_reg[0] = val;
43905 +
43906 + ctx->load_mmrs = true;
43907 +}
43908 +
43909 +/*
43910 + * Set the de-interlacer shadow register values
43911 + */
43912 +static void set_dei_regs(struct vpe_ctx *ctx)
43913 +{
43914 + struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr;
43915 + struct vpe_q_data *s_q_data = &ctx->q_data[Q_DATA_SRC];
43916 + unsigned int src_h = s_q_data->c_rect.height;
43917 + unsigned int src_w = s_q_data->c_rect.width;
43918 + u32 *dei_mmr0 = &mmr_adb->dei_regs[0];
43919 + bool deinterlace = true;
43920 + u32 val = 0;
43921 +
43922 + /*
43923 + * according to TRM, we should set DEI in progressive bypass mode when
43924 + * the input content is progressive, however, DEI is bypassed correctly
43925 + * for both progressive and interlace content in interlace bypass mode.
43926 + * It has been recommended not to use progressive bypass mode.
43927 + */
43928 + if ((!ctx->deinterlacing && (s_q_data->flags & Q_DATA_INTERLACED)) ||
43929 + !(s_q_data->flags & Q_DATA_INTERLACED)) {
43930 + deinterlace = false;
43931 + val = VPE_DEI_INTERLACE_BYPASS;
43932 + }
43933 +
43934 + src_h = deinterlace ? src_h * 2 : src_h;
43935 +
43936 + val |= (src_h << VPE_DEI_HEIGHT_SHIFT) |
43937 + (src_w << VPE_DEI_WIDTH_SHIFT) |
43938 + VPE_DEI_FIELD_FLUSH;
43939 +
43940 + *dei_mmr0 = val;
43941 +
43942 + ctx->load_mmrs = true;
43943 +}
43944 +
43945 +static void set_dei_shadow_registers(struct vpe_ctx *ctx)
43946 +{
43947 + struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr;
43948 + u32 *dei_mmr = &mmr_adb->dei_regs[0];
43949 + const struct vpe_dei_regs *cur = &dei_regs;
43950 +
43951 + dei_mmr[2] = cur->mdt_spacial_freq_thr_reg;
43952 + dei_mmr[3] = cur->edi_config_reg;
43953 + dei_mmr[4] = cur->edi_lut_reg0;
43954 + dei_mmr[5] = cur->edi_lut_reg1;
43955 + dei_mmr[6] = cur->edi_lut_reg2;
43956 + dei_mmr[7] = cur->edi_lut_reg3;
43957 +
43958 + ctx->load_mmrs = true;
43959 +}
43960 +
43961 +static void set_csc_coeff_bypass(struct vpe_ctx *ctx)
43962 +{
43963 + struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr;
43964 + u32 *shadow_csc_reg5 = &mmr_adb->csc_regs[5];
43965 +
43966 + *shadow_csc_reg5 |= VPE_CSC_BYPASS;
43967 +
43968 + ctx->load_mmrs = true;
43969 +}
43970 +
43971 +static void set_sc_regs_bypass(struct vpe_ctx *ctx)
43972 +{
43973 + struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr;
43974 + u32 *sc_reg0 = &mmr_adb->sc_regs[0];
43975 + u32 val = 0;
43976 +
43977 + val |= VPE_SC_BYPASS;
43978 + *sc_reg0 = val;
43979 +
43980 + ctx->load_mmrs = true;
43981 +}
43982 +
43983 +/*
43984 + * Set the shadow registers whose values are modified when either the
43985 + * source or destination format is changed.
43986 + */
43987 +static int set_srcdst_params(struct vpe_ctx *ctx)
43988 +{
43989 + struct vpe_q_data *s_q_data = &ctx->q_data[Q_DATA_SRC];
43990 + struct vpe_q_data *d_q_data = &ctx->q_data[Q_DATA_DST];
43991 + size_t mv_buf_size;
43992 + int ret;
43993 +
43994 + ctx->sequence = 0;
43995 + ctx->field = V4L2_FIELD_TOP;
43996 +
43997 + if ((s_q_data->flags & Q_DATA_INTERLACED) &&
43998 + !(d_q_data->flags & Q_DATA_INTERLACED)) {
43999 + const struct vpdma_data_format *mv =
44000 + &vpdma_misc_fmts[VPDMA_DATA_FMT_MV];
44001 +
44002 + ctx->deinterlacing = 1;
44003 + mv_buf_size =
44004 + (s_q_data->width * s_q_data->height * mv->depth) >> 3;
44005 + } else {
44006 + ctx->deinterlacing = 0;
44007 + mv_buf_size = 0;
44008 + }
44009 +
44010 + free_vbs(ctx);
44011 +
44012 + ret = realloc_mv_buffers(ctx, mv_buf_size);
44013 + if (ret)
44014 + return ret;
44015 +
44016 + set_cfg_and_line_modes(ctx);
44017 + set_dei_regs(ctx);
44018 + set_csc_coeff_bypass(ctx);
44019 + set_sc_regs_bypass(ctx);
44020 +
44021 + return 0;
44022 +}
44023 +
44024 +/*
44025 + * Return the vpe_ctx structure for a given struct file
44026 + */
44027 +static struct vpe_ctx *file2ctx(struct file *file)
44028 +{
44029 + return container_of(file->private_data, struct vpe_ctx, fh);
44030 +}
44031 +
44032 +/*
44033 + * mem2mem callbacks
44034 + */
44035 +
44036 +/**
44037 + * job_ready() - check whether an instance is ready to be scheduled to run
44038 + */
44039 +static int job_ready(void *priv)
44040 +{
44041 + struct vpe_ctx *ctx = priv;
44042 + int needed = ctx->bufs_per_job;
44043 +
44044 + if (ctx->deinterlacing && ctx->src_vbs[2] == NULL)
44045 + needed += 2; /* need additional two most recent fields */
44046 +
44047 + if (v4l2_m2m_num_src_bufs_ready(ctx->m2m_ctx) < needed)
44048 + return 0;
44049 +
44050 + return 1;
44051 +}
44052 +
44053 +static void job_abort(void *priv)
44054 +{
44055 + struct vpe_ctx *ctx = priv;
44056 +
44057 + /* Will cancel the transaction in the next interrupt handler */
44058 + ctx->aborting = 1;
44059 +}
44060 +
44061 +/*
44062 + * Lock access to the device
44063 + */
44064 +static void vpe_lock(void *priv)
44065 +{
44066 + struct vpe_ctx *ctx = priv;
44067 + struct vpe_dev *dev = ctx->dev;
44068 + mutex_lock(&dev->dev_mutex);
44069 +}
44070 +
44071 +static void vpe_unlock(void *priv)
44072 +{
44073 + struct vpe_ctx *ctx = priv;
44074 + struct vpe_dev *dev = ctx->dev;
44075 + mutex_unlock(&dev->dev_mutex);
44076 +}
44077 +
44078 +static void vpe_dump_regs(struct vpe_dev *dev)
44079 +{
44080 +#define DUMPREG(r) vpe_dbg(dev, "%-35s %08x\n", #r, read_reg(dev, VPE_##r))
44081 +
44082 + vpe_dbg(dev, "VPE Registers:\n");
44083 +
44084 + DUMPREG(PID);
44085 + DUMPREG(SYSCONFIG);
44086 + DUMPREG(INT0_STATUS0_RAW);
44087 + DUMPREG(INT0_STATUS0);
44088 + DUMPREG(INT0_ENABLE0);
44089 + DUMPREG(INT0_STATUS1_RAW);
44090 + DUMPREG(INT0_STATUS1);
44091 + DUMPREG(INT0_ENABLE1);
44092 + DUMPREG(CLK_ENABLE);
44093 + DUMPREG(CLK_RESET);
44094 + DUMPREG(CLK_FORMAT_SELECT);
44095 + DUMPREG(CLK_RANGE_MAP);
44096 + DUMPREG(US1_R0);
44097 + DUMPREG(US1_R1);
44098 + DUMPREG(US1_R2);
44099 + DUMPREG(US1_R3);
44100 + DUMPREG(US1_R4);
44101 + DUMPREG(US1_R5);
44102 + DUMPREG(US1_R6);
44103 + DUMPREG(US1_R7);
44104 + DUMPREG(US2_R0);
44105 + DUMPREG(US2_R1);
44106 + DUMPREG(US2_R2);
44107 + DUMPREG(US2_R3);
44108 + DUMPREG(US2_R4);
44109 + DUMPREG(US2_R5);
44110 + DUMPREG(US2_R6);
44111 + DUMPREG(US2_R7);
44112 + DUMPREG(US3_R0);
44113 + DUMPREG(US3_R1);
44114 + DUMPREG(US3_R2);
44115 + DUMPREG(US3_R3);
44116 + DUMPREG(US3_R4);
44117 + DUMPREG(US3_R5);
44118 + DUMPREG(US3_R6);
44119 + DUMPREG(US3_R7);
44120 + DUMPREG(DEI_FRAME_SIZE);
44121 + DUMPREG(MDT_BYPASS);
44122 + DUMPREG(MDT_SF_THRESHOLD);
44123 + DUMPREG(EDI_CONFIG);
44124 + DUMPREG(DEI_EDI_LUT_R0);
44125 + DUMPREG(DEI_EDI_LUT_R1);
44126 + DUMPREG(DEI_EDI_LUT_R2);
44127 + DUMPREG(DEI_EDI_LUT_R3);
44128 + DUMPREG(DEI_FMD_WINDOW_R0);
44129 + DUMPREG(DEI_FMD_WINDOW_R1);
44130 + DUMPREG(DEI_FMD_CONTROL_R0);
44131 + DUMPREG(DEI_FMD_CONTROL_R1);
44132 + DUMPREG(DEI_FMD_STATUS_R0);
44133 + DUMPREG(DEI_FMD_STATUS_R1);
44134 + DUMPREG(DEI_FMD_STATUS_R2);
44135 + DUMPREG(SC_MP_SC0);
44136 + DUMPREG(SC_MP_SC1);
44137 + DUMPREG(SC_MP_SC2);
44138 + DUMPREG(SC_MP_SC3);
44139 + DUMPREG(SC_MP_SC4);
44140 + DUMPREG(SC_MP_SC5);
44141 + DUMPREG(SC_MP_SC6);
44142 + DUMPREG(SC_MP_SC8);
44143 + DUMPREG(SC_MP_SC9);
44144 + DUMPREG(SC_MP_SC10);
44145 + DUMPREG(SC_MP_SC11);
44146 + DUMPREG(SC_MP_SC12);
44147 + DUMPREG(SC_MP_SC13);
44148 + DUMPREG(SC_MP_SC17);
44149 + DUMPREG(SC_MP_SC18);
44150 + DUMPREG(SC_MP_SC19);
44151 + DUMPREG(SC_MP_SC20);
44152 + DUMPREG(SC_MP_SC21);
44153 + DUMPREG(SC_MP_SC22);
44154 + DUMPREG(SC_MP_SC23);
44155 + DUMPREG(SC_MP_SC24);
44156 + DUMPREG(SC_MP_SC25);
44157 + DUMPREG(CSC_CSC00);
44158 + DUMPREG(CSC_CSC01);
44159 + DUMPREG(CSC_CSC02);
44160 + DUMPREG(CSC_CSC03);
44161 + DUMPREG(CSC_CSC04);
44162 + DUMPREG(CSC_CSC05);
44163 +#undef DUMPREG
44164 +}
44165 +
44166 +static void add_out_dtd(struct vpe_ctx *ctx, int port)
44167 +{
44168 + struct vpe_q_data *q_data = &ctx->q_data[Q_DATA_DST];
44169 + const struct vpe_port_data *p_data = &port_data[port];
44170 + struct vb2_buffer *vb = ctx->dst_vb;
44171 + struct v4l2_rect *c_rect = &q_data->c_rect;
44172 + struct vpe_fmt *fmt = q_data->fmt;
44173 + const struct vpdma_data_format *vpdma_fmt;
44174 + int mv_buf_selector = !ctx->src_mv_buf_selector;
44175 + dma_addr_t dma_addr;
44176 + u32 flags = 0;
44177 +
44178 + if (port == VPE_PORT_MV_OUT) {
44179 + vpdma_fmt = &vpdma_misc_fmts[VPDMA_DATA_FMT_MV];
44180 + dma_addr = ctx->mv_buf_dma[mv_buf_selector];
44181 + } else {
44182 + /* to incorporate interleaved formats */
44183 + int plane = fmt->coplanar ? p_data->vb_part : 0;
44184 +
44185 + vpdma_fmt = fmt->vpdma_fmt[plane];
44186 + dma_addr = vb2_dma_contig_plane_dma_addr(vb, plane);
44187 + if (!dma_addr) {
44188 + vpe_err(ctx->dev,
44189 + "acquiring output buffer(%d) dma_addr failed\n",
44190 + port);
44191 + return;
44192 + }
44193 + }
44194 +
44195 + if (q_data->flags & Q_DATA_FRAME_1D)
44196 + flags |= VPDMA_DATA_FRAME_1D;
44197 + if (q_data->flags & Q_DATA_MODE_TILED)
44198 + flags |= VPDMA_DATA_MODE_TILED;
44199 +
44200 + vpdma_add_out_dtd(&ctx->desc_list, c_rect, vpdma_fmt, dma_addr,
44201 + p_data->channel, flags);
44202 +}
44203 +
44204 +static void add_in_dtd(struct vpe_ctx *ctx, int port)
44205 +{
44206 + struct vpe_q_data *q_data = &ctx->q_data[Q_DATA_SRC];
44207 + const struct vpe_port_data *p_data = &port_data[port];
44208 + struct vb2_buffer *vb = ctx->src_vbs[p_data->vb_index];
44209 + struct v4l2_rect *c_rect = &q_data->c_rect;
44210 + struct vpe_fmt *fmt = q_data->fmt;
44211 + const struct vpdma_data_format *vpdma_fmt;
44212 + int mv_buf_selector = ctx->src_mv_buf_selector;
44213 + int field = vb->v4l2_buf.field == V4L2_FIELD_BOTTOM;
44214 + dma_addr_t dma_addr;
44215 + u32 flags = 0;
44216 +
44217 + if (port == VPE_PORT_MV_IN) {
44218 + vpdma_fmt = &vpdma_misc_fmts[VPDMA_DATA_FMT_MV];
44219 + dma_addr = ctx->mv_buf_dma[mv_buf_selector];
44220 + } else {
44221 + /* to incorporate interleaved formats */
44222 + int plane = fmt->coplanar ? p_data->vb_part : 0;
44223 +
44224 + vpdma_fmt = fmt->vpdma_fmt[plane];
44225 +
44226 + dma_addr = vb2_dma_contig_plane_dma_addr(vb, plane);
44227 + if (!dma_addr) {
44228 + vpe_err(ctx->dev,
44229 + "acquiring input buffer(%d) dma_addr failed\n",
44230 + port);
44231 + return;
44232 + }
44233 + }
44234 +
44235 + if (q_data->flags & Q_DATA_FRAME_1D)
44236 + flags |= VPDMA_DATA_FRAME_1D;
44237 + if (q_data->flags & Q_DATA_MODE_TILED)
44238 + flags |= VPDMA_DATA_MODE_TILED;
44239 +
44240 + vpdma_add_in_dtd(&ctx->desc_list, q_data->width, q_data->height,
44241 + c_rect, vpdma_fmt, dma_addr, p_data->channel, field, flags);
44242 +}
44243 +
44244 +/*
44245 + * Enable the expected IRQ sources
44246 + */
44247 +static void enable_irqs(struct vpe_ctx *ctx)
44248 +{
44249 + write_reg(ctx->dev, VPE_INT0_ENABLE0_SET, VPE_INT0_LIST0_COMPLETE);
44250 + write_reg(ctx->dev, VPE_INT0_ENABLE1_SET, VPE_DEI_ERROR_INT |
44251 + VPE_DS1_UV_ERROR_INT);
44252 +
44253 + vpdma_enable_list_complete_irq(ctx->dev->vpdma, 0, true);
44254 +}
44255 +
44256 +static void disable_irqs(struct vpe_ctx *ctx)
44257 +{
44258 + write_reg(ctx->dev, VPE_INT0_ENABLE0_CLR, 0xffffffff);
44259 + write_reg(ctx->dev, VPE_INT0_ENABLE1_CLR, 0xffffffff);
44260 +
44261 + vpdma_enable_list_complete_irq(ctx->dev->vpdma, 0, false);
44262 +}
44263 +
44264 +/* device_run() - prepares and starts the device
44265 + *
44266 + * This function is only called when both the source and destination
44267 + * buffers are in place.
44268 + */
44269 +static void device_run(void *priv)
44270 +{
44271 + struct vpe_ctx *ctx = priv;
44272 + struct vpe_q_data *d_q_data = &ctx->q_data[Q_DATA_DST];
44273 +
44274 + if (ctx->deinterlacing && ctx->src_vbs[2] == NULL) {
44275 + ctx->src_vbs[2] = v4l2_m2m_src_buf_remove(ctx->m2m_ctx);
44276 + WARN_ON(ctx->src_vbs[2] == NULL);
44277 + ctx->src_vbs[1] = v4l2_m2m_src_buf_remove(ctx->m2m_ctx);
44278 + WARN_ON(ctx->src_vbs[1] == NULL);
44279 + }
44280 +
44281 + ctx->src_vbs[0] = v4l2_m2m_src_buf_remove(ctx->m2m_ctx);
44282 + WARN_ON(ctx->src_vbs[0] == NULL);
44283 + ctx->dst_vb = v4l2_m2m_dst_buf_remove(ctx->m2m_ctx);
44284 + WARN_ON(ctx->dst_vb == NULL);
44285 +
44286 + /* config descriptors */
44287 + if (ctx->dev->loaded_mmrs != ctx->mmr_adb.dma_addr || ctx->load_mmrs) {
44288 + vpdma_map_desc_buf(ctx->dev->vpdma, &ctx->mmr_adb);
44289 + vpdma_add_cfd_adb(&ctx->desc_list, CFD_MMR_CLIENT, &ctx->mmr_adb);
44290 + ctx->dev->loaded_mmrs = ctx->mmr_adb.dma_addr;
44291 + ctx->load_mmrs = false;
44292 + }
44293 +
44294 + /* output data descriptors */
44295 + if (ctx->deinterlacing)
44296 + add_out_dtd(ctx, VPE_PORT_MV_OUT);
44297 +
44298 + add_out_dtd(ctx, VPE_PORT_LUMA_OUT);
44299 + if (d_q_data->fmt->coplanar)
44300 + add_out_dtd(ctx, VPE_PORT_CHROMA_OUT);
44301 +
44302 + /* input data descriptors */
44303 + if (ctx->deinterlacing) {
44304 + add_in_dtd(ctx, VPE_PORT_LUMA3_IN);
44305 + add_in_dtd(ctx, VPE_PORT_CHROMA3_IN);
44306 +
44307 + add_in_dtd(ctx, VPE_PORT_LUMA2_IN);
44308 + add_in_dtd(ctx, VPE_PORT_CHROMA2_IN);
44309 + }
44310 +
44311 + add_in_dtd(ctx, VPE_PORT_LUMA1_IN);
44312 + add_in_dtd(ctx, VPE_PORT_CHROMA1_IN);
44313 +
44314 + if (ctx->deinterlacing)
44315 + add_in_dtd(ctx, VPE_PORT_MV_IN);
44316 +
44317 + /* sync on channel control descriptors for input ports */
44318 + vpdma_add_sync_on_channel_ctd(&ctx->desc_list, VPE_CHAN_LUMA1_IN);
44319 + vpdma_add_sync_on_channel_ctd(&ctx->desc_list, VPE_CHAN_CHROMA1_IN);
44320 +
44321 + if (ctx->deinterlacing) {
44322 + vpdma_add_sync_on_channel_ctd(&ctx->desc_list,
44323 + VPE_CHAN_LUMA2_IN);
44324 + vpdma_add_sync_on_channel_ctd(&ctx->desc_list,
44325 + VPE_CHAN_CHROMA2_IN);
44326 +
44327 + vpdma_add_sync_on_channel_ctd(&ctx->desc_list,
44328 + VPE_CHAN_LUMA3_IN);
44329 + vpdma_add_sync_on_channel_ctd(&ctx->desc_list,
44330 + VPE_CHAN_CHROMA3_IN);
44331 +
44332 + vpdma_add_sync_on_channel_ctd(&ctx->desc_list, VPE_CHAN_MV_IN);
44333 + }
44334 +
44335 + /* sync on channel control descriptors for output ports */
44336 + vpdma_add_sync_on_channel_ctd(&ctx->desc_list, VPE_CHAN_LUMA_OUT);
44337 + if (d_q_data->fmt->coplanar)
44338 + vpdma_add_sync_on_channel_ctd(&ctx->desc_list, VPE_CHAN_CHROMA_OUT);
44339 +
44340 + if (ctx->deinterlacing)
44341 + vpdma_add_sync_on_channel_ctd(&ctx->desc_list, VPE_CHAN_MV_OUT);
44342 +
44343 + enable_irqs(ctx);
44344 +
44345 + vpdma_map_desc_buf(ctx->dev->vpdma, &ctx->desc_list.buf);
44346 + vpdma_submit_descs(ctx->dev->vpdma, &ctx->desc_list);
44347 +}
44348 +
44349 +static void dei_error(struct vpe_ctx *ctx)
44350 +{
44351 + dev_warn(ctx->dev->v4l2_dev.dev,
44352 + "received DEI error interrupt\n");
44353 +}
44354 +
44355 +static void ds1_uv_error(struct vpe_ctx *ctx)
44356 +{
44357 + dev_warn(ctx->dev->v4l2_dev.dev,
44358 + "received downsampler error interrupt\n");
44359 +}
44360 +
44361 +static irqreturn_t vpe_irq(int irq_vpe, void *data)
44362 +{
44363 + struct vpe_dev *dev = (struct vpe_dev *)data;
44364 + struct vpe_ctx *ctx;
44365 + struct vpe_q_data *d_q_data;
44366 + struct vb2_buffer *s_vb, *d_vb;
44367 + struct v4l2_buffer *s_buf, *d_buf;
44368 + unsigned long flags;
44369 + u32 irqst0, irqst1;
44370 +
44371 + irqst0 = read_reg(dev, VPE_INT0_STATUS0);
44372 + if (irqst0) {
44373 + write_reg(dev, VPE_INT0_STATUS0_CLR, irqst0);
44374 + vpe_dbg(dev, "INT0_STATUS0 = 0x%08x\n", irqst0);
44375 + }
44376 +
44377 + irqst1 = read_reg(dev, VPE_INT0_STATUS1);
44378 + if (irqst1) {
44379 + write_reg(dev, VPE_INT0_STATUS1_CLR, irqst1);
44380 + vpe_dbg(dev, "INT0_STATUS1 = 0x%08x\n", irqst1);
44381 + }
44382 +
44383 + ctx = v4l2_m2m_get_curr_priv(dev->m2m_dev);
44384 + if (!ctx) {
44385 + vpe_err(dev, "instance released before end of transaction\n");
44386 + goto handled;
44387 + }
44388 +
44389 + if (irqst1) {
44390 + if (irqst1 & VPE_DEI_ERROR_INT) {
44391 + irqst1 &= ~VPE_DEI_ERROR_INT;
44392 + dei_error(ctx);
44393 + }
44394 + if (irqst1 & VPE_DS1_UV_ERROR_INT) {
44395 + irqst1 &= ~VPE_DS1_UV_ERROR_INT;
44396 + ds1_uv_error(ctx);
44397 + }
44398 + }
44399 +
44400 + if (irqst0) {
44401 + if (irqst0 & VPE_INT0_LIST0_COMPLETE)
44402 + vpdma_clear_list_stat(ctx->dev->vpdma);
44403 +
44404 + irqst0 &= ~(VPE_INT0_LIST0_COMPLETE);
44405 + }
44406 +
44407 + if (irqst0 | irqst1) {
44408 + dev_warn(dev->v4l2_dev.dev, "Unexpected interrupt: "
44409 + "INT0_STATUS0 = 0x%08x, INT0_STATUS1 = 0x%08x\n",
44410 + irqst0, irqst1);
44411 + }
44412 +
44413 + disable_irqs(ctx);
44414 +
44415 + vpdma_unmap_desc_buf(dev->vpdma, &ctx->desc_list.buf);
44416 + vpdma_unmap_desc_buf(dev->vpdma, &ctx->mmr_adb);
44417 +
44418 + vpdma_reset_desc_list(&ctx->desc_list);
44419 +
44420 + /* the previous dst mv buffer becomes the next src mv buffer */
44421 + ctx->src_mv_buf_selector = !ctx->src_mv_buf_selector;
44422 +
44423 + if (ctx->aborting)
44424 + goto finished;
44425 +
44426 + s_vb = ctx->src_vbs[0];
44427 + d_vb = ctx->dst_vb;
44428 + s_buf = &s_vb->v4l2_buf;
44429 + d_buf = &d_vb->v4l2_buf;
44430 +
44431 + d_buf->timestamp = s_buf->timestamp;
44432 + if (s_buf->flags & V4L2_BUF_FLAG_TIMECODE) {
44433 + d_buf->flags |= V4L2_BUF_FLAG_TIMECODE;
44434 + d_buf->timecode = s_buf->timecode;
44435 + }
44436 + d_buf->sequence = ctx->sequence;
44437 + d_buf->field = ctx->field;
44438 +
44439 + d_q_data = &ctx->q_data[Q_DATA_DST];
44440 + if (d_q_data->flags & Q_DATA_INTERLACED) {
44441 + if (ctx->field == V4L2_FIELD_BOTTOM) {
44442 + ctx->sequence++;
44443 + ctx->field = V4L2_FIELD_TOP;
44444 + } else {
44445 + WARN_ON(ctx->field != V4L2_FIELD_TOP);
44446 + ctx->field = V4L2_FIELD_BOTTOM;
44447 + }
44448 + } else {
44449 + ctx->sequence++;
44450 + }
44451 +
44452 + if (ctx->deinterlacing)
44453 + s_vb = ctx->src_vbs[2];
44454 +
44455 + spin_lock_irqsave(&dev->lock, flags);
44456 + v4l2_m2m_buf_done(s_vb, VB2_BUF_STATE_DONE);
44457 + v4l2_m2m_buf_done(d_vb, VB2_BUF_STATE_DONE);
44458 + spin_unlock_irqrestore(&dev->lock, flags);
44459 +
44460 + if (ctx->deinterlacing) {
44461 + ctx->src_vbs[2] = ctx->src_vbs[1];
44462 + ctx->src_vbs[1] = ctx->src_vbs[0];
44463 + }
44464 +
44465 + ctx->bufs_completed++;
44466 + if (ctx->bufs_completed < ctx->bufs_per_job) {
44467 + device_run(ctx);
44468 + goto handled;
44469 + }
44470 +
44471 +finished:
44472 + vpe_dbg(ctx->dev, "finishing transaction\n");
44473 + ctx->bufs_completed = 0;
44474 + v4l2_m2m_job_finish(dev->m2m_dev, ctx->m2m_ctx);
44475 +handled:
44476 + return IRQ_HANDLED;
44477 +}
44478 +
44479 +/*
44480 + * video ioctls
44481 + */
44482 +static int vpe_querycap(struct file *file, void *priv,
44483 + struct v4l2_capability *cap)
44484 +{
44485 + strncpy(cap->driver, VPE_MODULE_NAME, sizeof(cap->driver) - 1);
44486 + strncpy(cap->card, VPE_MODULE_NAME, sizeof(cap->card) - 1);
44487 + strlcpy(cap->bus_info, VPE_MODULE_NAME, sizeof(cap->bus_info));
44488 + cap->device_caps = V4L2_CAP_VIDEO_M2M | V4L2_CAP_STREAMING;
44489 + cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS;
44490 + return 0;
44491 +}
44492 +
44493 +static int __enum_fmt(struct v4l2_fmtdesc *f, u32 type)
44494 +{
44495 + int i, index;
44496 + struct vpe_fmt *fmt = NULL;
44497 +
44498 + index = 0;
44499 + for (i = 0; i < ARRAY_SIZE(vpe_formats); ++i) {
44500 + if (vpe_formats[i].types & type) {
44501 + if (index == f->index) {
44502 + fmt = &vpe_formats[i];
44503 + break;
44504 + }
44505 + index++;
44506 + }
44507 + }
44508 +
44509 + if (!fmt)
44510 + return -EINVAL;
44511 +
44512 + strncpy(f->description, fmt->name, sizeof(f->description) - 1);
44513 + f->pixelformat = fmt->fourcc;
44514 + return 0;
44515 +}
44516 +
44517 +static int vpe_enum_fmt(struct file *file, void *priv,
44518 + struct v4l2_fmtdesc *f)
44519 +{
44520 + if (V4L2_TYPE_IS_OUTPUT(f->type))
44521 + return __enum_fmt(f, VPE_FMT_TYPE_OUTPUT);
44522 +
44523 + return __enum_fmt(f, VPE_FMT_TYPE_CAPTURE);
44524 +}
44525 +
44526 +static int vpe_g_fmt(struct file *file, void *priv, struct v4l2_format *f)
44527 +{
44528 + struct v4l2_pix_format_mplane *pix = &f->fmt.pix_mp;
44529 + struct vpe_ctx *ctx = file2ctx(file);
44530 + struct vb2_queue *vq;
44531 + struct vpe_q_data *q_data;
44532 + int i;
44533 +
44534 + vq = v4l2_m2m_get_vq(ctx->m2m_ctx, f->type);
44535 + if (!vq)
44536 + return -EINVAL;
44537 +
44538 + q_data = get_q_data(ctx, f->type);
44539 +
44540 + pix->width = q_data->width;
44541 + pix->height = q_data->height;
44542 + pix->pixelformat = q_data->fmt->fourcc;
44543 + pix->field = q_data->field;
44544 + pix->colorspace = q_data->colorspace;
44545 + pix->num_planes = q_data->fmt->coplanar ? 2 : 1;
44546 +
44547 + for (i = 0; i < pix->num_planes; i++) {
44548 + pix->plane_fmt[i].bytesperline = q_data->bytesperline[i];
44549 + pix->plane_fmt[i].sizeimage = q_data->sizeimage[i];
44550 + }
44551 +
44552 + return 0;
44553 +}
44554 +
44555 +static int __vpe_try_fmt(struct vpe_ctx *ctx, struct v4l2_format *f,
44556 + struct vpe_fmt *fmt, int type)
44557 +{
44558 + struct v4l2_pix_format_mplane *pix = &f->fmt.pix_mp;
44559 + struct v4l2_plane_pix_format *plane_fmt;
44560 + int i;
44561 +
44562 + if (!fmt || !(fmt->types & type)) {
44563 + vpe_err(ctx->dev, "Fourcc format (0x%08x) invalid.\n",
44564 + pix->pixelformat);
44565 + return -EINVAL;
44566 + }
44567 +
44568 + if (pix->field != V4L2_FIELD_NONE && pix->field != V4L2_FIELD_ALTERNATE)
44569 + pix->field = V4L2_FIELD_NONE;
44570 +
44571 + v4l_bound_align_image(&pix->width, MIN_W, MAX_W, W_ALIGN,
44572 + &pix->height, MIN_H, MAX_H, H_ALIGN,
44573 + S_ALIGN);
44574 +
44575 + pix->num_planes = fmt->coplanar ? 2 : 1;
44576 + pix->pixelformat = fmt->fourcc;
44577 + pix->colorspace = fmt->fourcc == V4L2_PIX_FMT_RGB24 ?
44578 + V4L2_COLORSPACE_SRGB : V4L2_COLORSPACE_SMPTE170M;
44579 +
44580 + for (i = 0; i < pix->num_planes; i++) {
44581 + int depth;
44582 +
44583 + plane_fmt = &pix->plane_fmt[i];
44584 + depth = fmt->vpdma_fmt[i]->depth;
44585 +
44586 + if (i == VPE_LUMA)
44587 + plane_fmt->bytesperline =
44588 + round_up((pix->width * depth) >> 3,
44589 + 1 << L_ALIGN);
44590 + else
44591 + plane_fmt->bytesperline = pix->width;
44592 +
44593 + plane_fmt->sizeimage =
44594 + (pix->height * pix->width * depth) >> 3;
44595 + }
44596 +
44597 + return 0;
44598 +}
44599 +
44600 +static int vpe_try_fmt(struct file *file, void *priv, struct v4l2_format *f)
44601 +{
44602 + struct vpe_ctx *ctx = file2ctx(file);
44603 + struct vpe_fmt *fmt = find_format(f);
44604 +
44605 + if (V4L2_TYPE_IS_OUTPUT(f->type))
44606 + return __vpe_try_fmt(ctx, f, fmt, VPE_FMT_TYPE_OUTPUT);
44607 + else
44608 + return __vpe_try_fmt(ctx, f, fmt, VPE_FMT_TYPE_CAPTURE);
44609 +}
44610 +
44611 +static int __vpe_s_fmt(struct vpe_ctx *ctx, struct v4l2_format *f)
44612 +{
44613 + struct v4l2_pix_format_mplane *pix = &f->fmt.pix_mp;
44614 + struct v4l2_plane_pix_format *plane_fmt;
44615 + struct vpe_q_data *q_data;
44616 + struct vb2_queue *vq;
44617 + int i;
44618 +
44619 + vq = v4l2_m2m_get_vq(ctx->m2m_ctx, f->type);
44620 + if (!vq)
44621 + return -EINVAL;
44622 +
44623 + if (vb2_is_busy(vq)) {
44624 + vpe_err(ctx->dev, "queue busy\n");
44625 + return -EBUSY;
44626 + }
44627 +
44628 + q_data = get_q_data(ctx, f->type);
44629 + if (!q_data)
44630 + return -EINVAL;
44631 +
44632 + q_data->fmt = find_format(f);
44633 + q_data->width = pix->width;
44634 + q_data->height = pix->height;
44635 + q_data->colorspace = pix->colorspace;
44636 + q_data->field = pix->field;
44637 +
44638 + for (i = 0; i < pix->num_planes; i++) {
44639 + plane_fmt = &pix->plane_fmt[i];
44640 +
44641 + q_data->bytesperline[i] = plane_fmt->bytesperline;
44642 + q_data->sizeimage[i] = plane_fmt->sizeimage;
44643 + }
44644 +
44645 + q_data->c_rect.left = 0;
44646 + q_data->c_rect.top = 0;
44647 + q_data->c_rect.width = q_data->width;
44648 + q_data->c_rect.height = q_data->height;
44649 +
44650 + if (q_data->field == V4L2_FIELD_ALTERNATE)
44651 + q_data->flags |= Q_DATA_INTERLACED;
44652 + else
44653 + q_data->flags &= ~Q_DATA_INTERLACED;
44654 +
44655 + vpe_dbg(ctx->dev, "Setting format for type %d, wxh: %dx%d, fmt: %d bpl_y %d",
44656 + f->type, q_data->width, q_data->height, q_data->fmt->fourcc,
44657 + q_data->bytesperline[VPE_LUMA]);
44658 + if (q_data->fmt->coplanar)
44659 + vpe_dbg(ctx->dev, " bpl_uv %d\n",
44660 + q_data->bytesperline[VPE_CHROMA]);
44661 +
44662 + return 0;
44663 +}
44664 +
44665 +static int vpe_s_fmt(struct file *file, void *priv, struct v4l2_format *f)
44666 +{
44667 + int ret;
44668 + struct vpe_ctx *ctx = file2ctx(file);
44669 +
44670 + ret = vpe_try_fmt(file, priv, f);
44671 + if (ret)
44672 + return ret;
44673 +
44674 + ret = __vpe_s_fmt(ctx, f);
44675 + if (ret)
44676 + return ret;
44677 +
44678 + if (V4L2_TYPE_IS_OUTPUT(f->type))
44679 + set_src_registers(ctx);
44680 + else
44681 + set_dst_registers(ctx);
44682 +
44683 + return set_srcdst_params(ctx);
44684 +}
44685 +
44686 +static int vpe_reqbufs(struct file *file, void *priv,
44687 + struct v4l2_requestbuffers *reqbufs)
44688 +{
44689 + struct vpe_ctx *ctx = file2ctx(file);
44690 +
44691 + return v4l2_m2m_reqbufs(file, ctx->m2m_ctx, reqbufs);
44692 +}
44693 +
44694 +static int vpe_querybuf(struct file *file, void *priv, struct v4l2_buffer *buf)
44695 +{
44696 + struct vpe_ctx *ctx = file2ctx(file);
44697 +
44698 + return v4l2_m2m_querybuf(file, ctx->m2m_ctx, buf);
44699 +}
44700 +
44701 +static int vpe_qbuf(struct file *file, void *priv, struct v4l2_buffer *buf)
44702 +{
44703 + struct vpe_ctx *ctx = file2ctx(file);
44704 +
44705 + return v4l2_m2m_qbuf(file, ctx->m2m_ctx, buf);
44706 +}
44707 +
44708 +static int vpe_dqbuf(struct file *file, void *priv, struct v4l2_buffer *buf)
44709 +{
44710 + struct vpe_ctx *ctx = file2ctx(file);
44711 +
44712 + return v4l2_m2m_dqbuf(file, ctx->m2m_ctx, buf);
44713 +}
44714 +
44715 +static int vpe_streamon(struct file *file, void *priv, enum v4l2_buf_type type)
44716 +{
44717 + struct vpe_ctx *ctx = file2ctx(file);
44718 +
44719 + return v4l2_m2m_streamon(file, ctx->m2m_ctx, type);
44720 +}
44721 +
44722 +static int vpe_streamoff(struct file *file, void *priv, enum v4l2_buf_type type)
44723 +{
44724 + struct vpe_ctx *ctx = file2ctx(file);
44725 +
44726 + vpe_dump_regs(ctx->dev);
44727 + vpdma_dump_regs(ctx->dev->vpdma);
44728 +
44729 + return v4l2_m2m_streamoff(file, ctx->m2m_ctx, type);
44730 +}
44731 +
44732 +#define V4L2_CID_VPE_BUFS_PER_JOB (V4L2_CID_USER_TI_VPE_BASE + 0)
44733 +
44734 +static int vpe_s_ctrl(struct v4l2_ctrl *ctrl)
44735 +{
44736 + struct vpe_ctx *ctx =
44737 + container_of(ctrl->handler, struct vpe_ctx, hdl);
44738 +
44739 + switch (ctrl->id) {
44740 + case V4L2_CID_VPE_BUFS_PER_JOB:
44741 + ctx->bufs_per_job = ctrl->val;
44742 + break;
44743 +
44744 + default:
44745 + vpe_err(ctx->dev, "Invalid control\n");
44746 + return -EINVAL;
44747 + }
44748 +
44749 + return 0;
44750 +}
44751 +
44752 +static const struct v4l2_ctrl_ops vpe_ctrl_ops = {
44753 + .s_ctrl = vpe_s_ctrl,
44754 +};
44755 +
44756 +static const struct v4l2_ioctl_ops vpe_ioctl_ops = {
44757 + .vidioc_querycap = vpe_querycap,
44758 +
44759 + .vidioc_enum_fmt_vid_cap_mplane = vpe_enum_fmt,
44760 + .vidioc_g_fmt_vid_cap_mplane = vpe_g_fmt,
44761 + .vidioc_try_fmt_vid_cap_mplane = vpe_try_fmt,
44762 + .vidioc_s_fmt_vid_cap_mplane = vpe_s_fmt,
44763 +
44764 + .vidioc_enum_fmt_vid_out_mplane = vpe_enum_fmt,
44765 + .vidioc_g_fmt_vid_out_mplane = vpe_g_fmt,
44766 + .vidioc_try_fmt_vid_out_mplane = vpe_try_fmt,
44767 + .vidioc_s_fmt_vid_out_mplane = vpe_s_fmt,
44768 +
44769 + .vidioc_reqbufs = vpe_reqbufs,
44770 + .vidioc_querybuf = vpe_querybuf,
44771 +
44772 + .vidioc_qbuf = vpe_qbuf,
44773 + .vidioc_dqbuf = vpe_dqbuf,
44774 +
44775 + .vidioc_streamon = vpe_streamon,
44776 + .vidioc_streamoff = vpe_streamoff,
44777 + .vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
44778 + .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
44779 +};
44780 +
44781 +/*
44782 + * Queue operations
44783 + */
44784 +static int vpe_queue_setup(struct vb2_queue *vq,
44785 + const struct v4l2_format *fmt,
44786 + unsigned int *nbuffers, unsigned int *nplanes,
44787 + unsigned int sizes[], void *alloc_ctxs[])
44788 +{
44789 + int i;
44790 + struct vpe_ctx *ctx = vb2_get_drv_priv(vq);
44791 + struct vpe_q_data *q_data;
44792 +
44793 + q_data = get_q_data(ctx, vq->type);
44794 +
44795 + *nplanes = q_data->fmt->coplanar ? 2 : 1;
44796 +
44797 + for (i = 0; i < *nplanes; i++) {
44798 + sizes[i] = q_data->sizeimage[i];
44799 + alloc_ctxs[i] = ctx->dev->alloc_ctx;
44800 + }
44801 +
44802 + vpe_dbg(ctx->dev, "get %d buffer(s) of size %d", *nbuffers,
44803 + sizes[VPE_LUMA]);
44804 + if (q_data->fmt->coplanar)
44805 + vpe_dbg(ctx->dev, " and %d\n", sizes[VPE_CHROMA]);
44806 +
44807 + return 0;
44808 +}
44809 +
44810 +static int vpe_buf_prepare(struct vb2_buffer *vb)
44811 +{
44812 + struct vpe_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
44813 + struct vpe_q_data *q_data;
44814 + int i, num_planes;
44815 +
44816 + vpe_dbg(ctx->dev, "type: %d\n", vb->vb2_queue->type);
44817 +
44818 + q_data = get_q_data(ctx, vb->vb2_queue->type);
44819 + num_planes = q_data->fmt->coplanar ? 2 : 1;
44820 +
44821 + for (i = 0; i < num_planes; i++) {
44822 + if (vb2_plane_size(vb, i) < q_data->sizeimage[i]) {
44823 + vpe_err(ctx->dev,
44824 + "data will not fit into plane (%lu < %lu)\n",
44825 + vb2_plane_size(vb, i),
44826 + (long) q_data->sizeimage[i]);
44827 + return -EINVAL;
44828 + }
44829 + }
44830 +
44831 + for (i = 0; i < num_planes; i++)
44832 + vb2_set_plane_payload(vb, i, q_data->sizeimage[i]);
44833 +
44834 + return 0;
44835 +}
44836 +
44837 +static void vpe_buf_queue(struct vb2_buffer *vb)
44838 +{
44839 + struct vpe_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
44840 + v4l2_m2m_buf_queue(ctx->m2m_ctx, vb);
44841 +}
44842 +
44843 +static void vpe_wait_prepare(struct vb2_queue *q)
44844 +{
44845 + struct vpe_ctx *ctx = vb2_get_drv_priv(q);
44846 + vpe_unlock(ctx);
44847 +}
44848 +
44849 +static void vpe_wait_finish(struct vb2_queue *q)
44850 +{
44851 + struct vpe_ctx *ctx = vb2_get_drv_priv(q);
44852 + vpe_lock(ctx);
44853 +}
44854 +
44855 +static struct vb2_ops vpe_qops = {
44856 + .queue_setup = vpe_queue_setup,
44857 + .buf_prepare = vpe_buf_prepare,
44858 + .buf_queue = vpe_buf_queue,
44859 + .wait_prepare = vpe_wait_prepare,
44860 + .wait_finish = vpe_wait_finish,
44861 +};
44862 +
44863 +static int queue_init(void *priv, struct vb2_queue *src_vq,
44864 + struct vb2_queue *dst_vq)
44865 +{
44866 + struct vpe_ctx *ctx = priv;
44867 + int ret;
44868 +
44869 + memset(src_vq, 0, sizeof(*src_vq));
44870 + src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
44871 + src_vq->io_modes = VB2_MMAP;
44872 + src_vq->drv_priv = ctx;
44873 + src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
44874 + src_vq->ops = &vpe_qops;
44875 + src_vq->mem_ops = &vb2_dma_contig_memops;
44876 + src_vq->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_COPY;
44877 +
44878 + ret = vb2_queue_init(src_vq);
44879 + if (ret)
44880 + return ret;
44881 +
44882 + memset(dst_vq, 0, sizeof(*dst_vq));
44883 + dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
44884 + dst_vq->io_modes = VB2_MMAP;
44885 + dst_vq->drv_priv = ctx;
44886 + dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
44887 + dst_vq->ops = &vpe_qops;
44888 + dst_vq->mem_ops = &vb2_dma_contig_memops;
44889 + dst_vq->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_COPY;
44890 +
44891 + return vb2_queue_init(dst_vq);
44892 +}
44893 +
44894 +static const struct v4l2_ctrl_config vpe_bufs_per_job = {
44895 + .ops = &vpe_ctrl_ops,
44896 + .id = V4L2_CID_VPE_BUFS_PER_JOB,
44897 + .name = "Buffers Per Transaction",
44898 + .type = V4L2_CTRL_TYPE_INTEGER,
44899 + .def = VPE_DEF_BUFS_PER_JOB,
44900 + .min = 1,
44901 + .max = VIDEO_MAX_FRAME,
44902 + .step = 1,
44903 +};
44904 +
44905 +/*
44906 + * File operations
44907 + */
44908 +static int vpe_open(struct file *file)
44909 +{
44910 + struct vpe_dev *dev = video_drvdata(file);
44911 + struct vpe_ctx *ctx = NULL;
44912 + struct vpe_q_data *s_q_data;
44913 + struct v4l2_ctrl_handler *hdl;
44914 + int ret;
44915 +
44916 + vpe_dbg(dev, "vpe_open\n");
44917 +
44918 + if (!dev->vpdma->ready) {
44919 + vpe_err(dev, "vpdma firmware not loaded\n");
44920 + return -ENODEV;
44921 + }
44922 +
44923 + ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
44924 + if (!ctx)
44925 + return -ENOMEM;
44926 +
44927 + ctx->dev = dev;
44928 +
44929 + if (mutex_lock_interruptible(&dev->dev_mutex)) {
44930 + ret = -ERESTARTSYS;
44931 + goto free_ctx;
44932 + }
44933 +
44934 + ret = vpdma_create_desc_list(&ctx->desc_list, VPE_DESC_LIST_SIZE,
44935 + VPDMA_LIST_TYPE_NORMAL);
44936 + if (ret != 0)
44937 + goto unlock;
44938 +
44939 + ret = vpdma_alloc_desc_buf(&ctx->mmr_adb, sizeof(struct vpe_mmr_adb));
44940 + if (ret != 0)
44941 + goto free_desc_list;
44942 +
44943 + init_adb_hdrs(ctx);
44944 +
44945 + v4l2_fh_init(&ctx->fh, video_devdata(file));
44946 + file->private_data = &ctx->fh;
44947 +
44948 + hdl = &ctx->hdl;
44949 + v4l2_ctrl_handler_init(hdl, 1);
44950 + v4l2_ctrl_new_custom(hdl, &vpe_bufs_per_job, NULL);
44951 + if (hdl->error) {
44952 + ret = hdl->error;
44953 + goto exit_fh;
44954 + }
44955 + ctx->fh.ctrl_handler = hdl;
44956 + v4l2_ctrl_handler_setup(hdl);
44957 +
44958 + s_q_data = &ctx->q_data[Q_DATA_SRC];
44959 + s_q_data->fmt = &vpe_formats[2];
44960 + s_q_data->width = 1920;
44961 + s_q_data->height = 1080;
44962 + s_q_data->sizeimage[VPE_LUMA] = (s_q_data->width * s_q_data->height *
44963 + s_q_data->fmt->vpdma_fmt[VPE_LUMA]->depth) >> 3;
44964 + s_q_data->colorspace = V4L2_COLORSPACE_SMPTE240M;
44965 + s_q_data->field = V4L2_FIELD_NONE;
44966 + s_q_data->c_rect.left = 0;
44967 + s_q_data->c_rect.top = 0;
44968 + s_q_data->c_rect.width = s_q_data->width;
44969 + s_q_data->c_rect.height = s_q_data->height;
44970 + s_q_data->flags = 0;
44971 +
44972 + ctx->q_data[Q_DATA_DST] = *s_q_data;
44973 +
44974 + set_dei_shadow_registers(ctx);
44975 + set_src_registers(ctx);
44976 + set_dst_registers(ctx);
44977 + ret = set_srcdst_params(ctx);
44978 + if (ret)
44979 + goto exit_fh;
44980 +
44981 + ctx->m2m_ctx = v4l2_m2m_ctx_init(dev->m2m_dev, ctx, &queue_init);
44982 +
44983 + if (IS_ERR(ctx->m2m_ctx)) {
44984 + ret = PTR_ERR(ctx->m2m_ctx);
44985 + goto exit_fh;
44986 + }
44987 +
44988 + v4l2_fh_add(&ctx->fh);
44989 +
44990 + /*
44991 + * for now, just report the creation of the first instance, we can later
44992 + * optimize the driver to enable or disable clocks when the first
44993 + * instance is created or the last instance released
44994 + */
44995 + if (atomic_inc_return(&dev->num_instances) == 1)
44996 + vpe_dbg(dev, "first instance created\n");
44997 +
44998 + ctx->bufs_per_job = VPE_DEF_BUFS_PER_JOB;
44999 +
45000 + ctx->load_mmrs = true;
45001 +
45002 + vpe_dbg(dev, "created instance %p, m2m_ctx: %p\n",
45003 + ctx, ctx->m2m_ctx);
45004 +
45005 + mutex_unlock(&dev->dev_mutex);
45006 +
45007 + return 0;
45008 +exit_fh:
45009 + v4l2_ctrl_handler_free(hdl);
45010 + v4l2_fh_exit(&ctx->fh);
45011 + vpdma_free_desc_buf(&ctx->mmr_adb);
45012 +free_desc_list:
45013 + vpdma_free_desc_list(&ctx->desc_list);
45014 +unlock:
45015 + mutex_unlock(&dev->dev_mutex);
45016 +free_ctx:
45017 + kfree(ctx);
45018 + return ret;
45019 +}
45020 +
45021 +static int vpe_release(struct file *file)
45022 +{
45023 + struct vpe_dev *dev = video_drvdata(file);
45024 + struct vpe_ctx *ctx = file2ctx(file);
45025 +
45026 + vpe_dbg(dev, "releasing instance %p\n", ctx);
45027 +
45028 + mutex_lock(&dev->dev_mutex);
45029 + free_vbs(ctx);
45030 + free_mv_buffers(ctx);
45031 + vpdma_free_desc_list(&ctx->desc_list);
45032 + vpdma_free_desc_buf(&ctx->mmr_adb);
45033 +
45034 + v4l2_fh_del(&ctx->fh);
45035 + v4l2_fh_exit(&ctx->fh);
45036 + v4l2_ctrl_handler_free(&ctx->hdl);
45037 + v4l2_m2m_ctx_release(ctx->m2m_ctx);
45038 +
45039 + kfree(ctx);
45040 +
45041 + /*
45042 + * for now, just report the release of the last instance, we can later
45043 + * optimize the driver to enable or disable clocks when the first
45044 + * instance is created or the last instance released
45045 + */
45046 + if (atomic_dec_return(&dev->num_instances) == 0)
45047 + vpe_dbg(dev, "last instance released\n");
45048 +
45049 + mutex_unlock(&dev->dev_mutex);
45050 +
45051 + return 0;
45052 +}
45053 +
45054 +static unsigned int vpe_poll(struct file *file,
45055 + struct poll_table_struct *wait)
45056 +{
45057 + struct vpe_ctx *ctx = file2ctx(file);
45058 + struct vpe_dev *dev = ctx->dev;
45059 + int ret;
45060 +
45061 + mutex_lock(&dev->dev_mutex);
45062 + ret = v4l2_m2m_poll(file, ctx->m2m_ctx, wait);
45063 + mutex_unlock(&dev->dev_mutex);
45064 + return ret;
45065 +}
45066 +
45067 +static int vpe_mmap(struct file *file, struct vm_area_struct *vma)
45068 +{
45069 + struct vpe_ctx *ctx = file2ctx(file);
45070 + struct vpe_dev *dev = ctx->dev;
45071 + int ret;
45072 +
45073 + if (mutex_lock_interruptible(&dev->dev_mutex))
45074 + return -ERESTARTSYS;
45075 + ret = v4l2_m2m_mmap(file, ctx->m2m_ctx, vma);
45076 + mutex_unlock(&dev->dev_mutex);
45077 + return ret;
45078 +}
45079 +
45080 +static const struct v4l2_file_operations vpe_fops = {
45081 + .owner = THIS_MODULE,
45082 + .open = vpe_open,
45083 + .release = vpe_release,
45084 + .poll = vpe_poll,
45085 + .unlocked_ioctl = video_ioctl2,
45086 + .mmap = vpe_mmap,
45087 +};
45088 +
45089 +static struct video_device vpe_videodev = {
45090 + .name = VPE_MODULE_NAME,
45091 + .fops = &vpe_fops,
45092 + .ioctl_ops = &vpe_ioctl_ops,
45093 + .minor = -1,
45094 + .release = video_device_release,
45095 + .vfl_dir = VFL_DIR_M2M,
45096 +};
45097 +
45098 +static struct v4l2_m2m_ops m2m_ops = {
45099 + .device_run = device_run,
45100 + .job_ready = job_ready,
45101 + .job_abort = job_abort,
45102 + .lock = vpe_lock,
45103 + .unlock = vpe_unlock,
45104 +};
45105 +
45106 +static int vpe_runtime_get(struct platform_device *pdev)
45107 +{
45108 + int r;
45109 +
45110 + dev_dbg(&pdev->dev, "vpe_runtime_get\n");
45111 +
45112 + r = pm_runtime_get_sync(&pdev->dev);
45113 + WARN_ON(r < 0);
45114 + return r < 0 ? r : 0;
45115 +}
45116 +
45117 +static void vpe_runtime_put(struct platform_device *pdev)
45118 +{
45119 +
45120 + int r;
45121 +
45122 + dev_dbg(&pdev->dev, "vpe_runtime_put\n");
45123 +
45124 + r = pm_runtime_put_sync(&pdev->dev);
45125 + WARN_ON(r < 0 && r != -ENOSYS);
45126 +}
45127 +
45128 +static int vpe_probe(struct platform_device *pdev)
45129 +{
45130 + struct vpe_dev *dev;
45131 + struct video_device *vfd;
45132 + struct resource *res;
45133 + int ret, irq, func;
45134 +
45135 + dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
45136 + if (IS_ERR(dev))
45137 + return PTR_ERR(dev);
45138 +
45139 + spin_lock_init(&dev->lock);
45140 +
45141 + ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);
45142 + if (ret)
45143 + return ret;
45144 +
45145 + atomic_set(&dev->num_instances, 0);
45146 + mutex_init(&dev->dev_mutex);
45147 +
45148 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "vpe_top");
45149 + /*
45150 + * HACK: we get resource info from device tree in the form of a list of
45151 + * VPE sub blocks, the driver currently uses only the base of vpe_top
45152 + * for register access, the driver should be changed later to access
45153 + * registers based on the sub block base addresses
45154 + */
45155 + dev->base = devm_ioremap(&pdev->dev, res->start, SZ_32K);
45156 + if (IS_ERR(dev->base)) {
45157 + ret = PTR_ERR(dev->base);
45158 + goto v4l2_dev_unreg;
45159 + }
45160 +
45161 + irq = platform_get_irq(pdev, 0);
45162 + ret = devm_request_irq(&pdev->dev, irq, vpe_irq, 0, VPE_MODULE_NAME,
45163 + dev);
45164 + if (ret)
45165 + goto v4l2_dev_unreg;
45166 +
45167 + platform_set_drvdata(pdev, dev);
45168 +
45169 + dev->alloc_ctx = vb2_dma_contig_init_ctx(&pdev->dev);
45170 + if (IS_ERR(dev->alloc_ctx)) {
45171 + vpe_err(dev, "Failed to alloc vb2 context\n");
45172 + ret = PTR_ERR(dev->alloc_ctx);
45173 + goto v4l2_dev_unreg;
45174 + }
45175 +
45176 + dev->m2m_dev = v4l2_m2m_init(&m2m_ops);
45177 + if (IS_ERR(dev->m2m_dev)) {
45178 + vpe_err(dev, "Failed to init mem2mem device\n");
45179 + ret = PTR_ERR(dev->m2m_dev);
45180 + goto rel_ctx;
45181 + }
45182 +
45183 + pm_runtime_enable(&pdev->dev);
45184 +
45185 + ret = vpe_runtime_get(pdev);
45186 + if (ret)
45187 + goto rel_m2m;
45188 +
45189 + /* Perform clk enable followed by reset */
45190 + vpe_set_clock_enable(dev, 1);
45191 +
45192 + vpe_top_reset(dev);
45193 +
45194 + func = read_field_reg(dev, VPE_PID, VPE_PID_FUNC_MASK,
45195 + VPE_PID_FUNC_SHIFT);
45196 + vpe_dbg(dev, "VPE PID function %x\n", func);
45197 +
45198 + vpe_top_vpdma_reset(dev);
45199 +
45200 + dev->vpdma = vpdma_create(pdev);
45201 + if (IS_ERR(dev->vpdma))
45202 + goto runtime_put;
45203 +
45204 + vfd = &dev->vfd;
45205 + *vfd = vpe_videodev;
45206 + vfd->lock = &dev->dev_mutex;
45207 + vfd->v4l2_dev = &dev->v4l2_dev;
45208 +
45209 + ret = video_register_device(vfd, VFL_TYPE_GRABBER, 0);
45210 + if (ret) {
45211 + vpe_err(dev, "Failed to register video device\n");
45212 + goto runtime_put;
45213 + }
45214 +
45215 + video_set_drvdata(vfd, dev);
45216 + snprintf(vfd->name, sizeof(vfd->name), "%s", vpe_videodev.name);
45217 + dev_info(dev->v4l2_dev.dev, "Device registered as /dev/video%d\n",
45218 + vfd->num);
45219 +
45220 + return 0;
45221 +
45222 +runtime_put:
45223 + vpe_runtime_put(pdev);
45224 +rel_m2m:
45225 + pm_runtime_disable(&pdev->dev);
45226 + v4l2_m2m_release(dev->m2m_dev);
45227 +rel_ctx:
45228 + vb2_dma_contig_cleanup_ctx(dev->alloc_ctx);
45229 +v4l2_dev_unreg:
45230 + v4l2_device_unregister(&dev->v4l2_dev);
45231 +
45232 + return ret;
45233 +}
45234 +
45235 +static int vpe_remove(struct platform_device *pdev)
45236 +{
45237 + struct vpe_dev *dev =
45238 + (struct vpe_dev *) platform_get_drvdata(pdev);
45239 +
45240 + v4l2_info(&dev->v4l2_dev, "Removing " VPE_MODULE_NAME);
45241 +
45242 + v4l2_m2m_release(dev->m2m_dev);
45243 + video_unregister_device(&dev->vfd);
45244 + v4l2_device_unregister(&dev->v4l2_dev);
45245 + vb2_dma_contig_cleanup_ctx(dev->alloc_ctx);
45246 +
45247 + vpe_set_clock_enable(dev, 0);
45248 + vpe_runtime_put(pdev);
45249 + pm_runtime_disable(&pdev->dev);
45250 +
45251 + return 0;
45252 +}
45253 +
45254 +#if defined(CONFIG_OF)
45255 +static const struct of_device_id vpe_of_match[] = {
45256 + {
45257 + .compatible = "ti,vpe",
45258 + },
45259 + {},
45260 +};
45261 +#else
45262 +#define vpe_of_match NULL
45263 +#endif
45264 +
45265 +static struct platform_driver vpe_pdrv = {
45266 + .probe = vpe_probe,
45267 + .remove = vpe_remove,
45268 + .driver = {
45269 + .name = VPE_MODULE_NAME,
45270 + .owner = THIS_MODULE,
45271 + .of_match_table = vpe_of_match,
45272 + },
45273 +};
45274 +
45275 +static void __exit vpe_exit(void)
45276 +{
45277 + platform_driver_unregister(&vpe_pdrv);
45278 +}
45279 +
45280 +static int __init vpe_init(void)
45281 +{
45282 + return platform_driver_register(&vpe_pdrv);
45283 +}
45284 +
45285 +module_init(vpe_init);
45286 +module_exit(vpe_exit);
45287 +
45288 +MODULE_DESCRIPTION("TI VPE driver");
45289 +MODULE_AUTHOR("Dale Farnsworth, <dale@farnsworth.org>");
45290 +MODULE_LICENSE("GPL");
45291 --- /dev/null
45292 +++ b/drivers/media/platform/ti-vpe/vpe_regs.h
45293 @@ -0,0 +1,496 @@
45294 +/*
45295 + * Copyright (c) 2013 Texas Instruments Inc.
45296 + *
45297 + * David Griego, <dagriego@biglakesoftware.com>
45298 + * Dale Farnsworth, <dale@farnsworth.org>
45299 + * Archit Taneja, <archit@ti.com>
45300 + *
45301 + * This program is free software; you can redistribute it and/or modify it
45302 + * under the terms of the GNU General Public License version 2 as published by
45303 + * the Free Software Foundation.
45304 + */
45305 +
45306 +#ifndef __TI_VPE_REGS_H
45307 +#define __TI_VPE_REGS_H
45308 +
45309 +/* VPE register offsets and field selectors */
45310 +
45311 +/* VPE top level regs */
45312 +#define VPE_PID 0x0000
45313 +#define VPE_PID_MINOR_MASK 0x3f
45314 +#define VPE_PID_MINOR_SHIFT 0
45315 +#define VPE_PID_CUSTOM_MASK 0x03
45316 +#define VPE_PID_CUSTOM_SHIFT 6
45317 +#define VPE_PID_MAJOR_MASK 0x07
45318 +#define VPE_PID_MAJOR_SHIFT 8
45319 +#define VPE_PID_RTL_MASK 0x1f
45320 +#define VPE_PID_RTL_SHIFT 11
45321 +#define VPE_PID_FUNC_MASK 0xfff
45322 +#define VPE_PID_FUNC_SHIFT 16
45323 +#define VPE_PID_SCHEME_MASK 0x03
45324 +#define VPE_PID_SCHEME_SHIFT 30
45325 +
45326 +#define VPE_SYSCONFIG 0x0010
45327 +#define VPE_SYSCONFIG_IDLE_MASK 0x03
45328 +#define VPE_SYSCONFIG_IDLE_SHIFT 2
45329 +#define VPE_SYSCONFIG_STANDBY_MASK 0x03
45330 +#define VPE_SYSCONFIG_STANDBY_SHIFT 4
45331 +#define VPE_FORCE_IDLE_MODE 0
45332 +#define VPE_NO_IDLE_MODE 1
45333 +#define VPE_SMART_IDLE_MODE 2
45334 +#define VPE_SMART_IDLE_WAKEUP_MODE 3
45335 +#define VPE_FORCE_STANDBY_MODE 0
45336 +#define VPE_NO_STANDBY_MODE 1
45337 +#define VPE_SMART_STANDBY_MODE 2
45338 +#define VPE_SMART_STANDBY_WAKEUP_MODE 3
45339 +
45340 +#define VPE_INT0_STATUS0_RAW_SET 0x0020
45341 +#define VPE_INT0_STATUS0_RAW VPE_INT0_STATUS0_RAW_SET
45342 +#define VPE_INT0_STATUS0_CLR 0x0028
45343 +#define VPE_INT0_STATUS0 VPE_INT0_STATUS0_CLR
45344 +#define VPE_INT0_ENABLE0_SET 0x0030
45345 +#define VPE_INT0_ENABLE0 VPE_INT0_ENABLE0_SET
45346 +#define VPE_INT0_ENABLE0_CLR 0x0038
45347 +#define VPE_INT0_LIST0_COMPLETE (1 << 0)
45348 +#define VPE_INT0_LIST0_NOTIFY (1 << 1)
45349 +#define VPE_INT0_LIST1_COMPLETE (1 << 2)
45350 +#define VPE_INT0_LIST1_NOTIFY (1 << 3)
45351 +#define VPE_INT0_LIST2_COMPLETE (1 << 4)
45352 +#define VPE_INT0_LIST2_NOTIFY (1 << 5)
45353 +#define VPE_INT0_LIST3_COMPLETE (1 << 6)
45354 +#define VPE_INT0_LIST3_NOTIFY (1 << 7)
45355 +#define VPE_INT0_LIST4_COMPLETE (1 << 8)
45356 +#define VPE_INT0_LIST4_NOTIFY (1 << 9)
45357 +#define VPE_INT0_LIST5_COMPLETE (1 << 10)
45358 +#define VPE_INT0_LIST5_NOTIFY (1 << 11)
45359 +#define VPE_INT0_LIST6_COMPLETE (1 << 12)
45360 +#define VPE_INT0_LIST6_NOTIFY (1 << 13)
45361 +#define VPE_INT0_LIST7_COMPLETE (1 << 14)
45362 +#define VPE_INT0_LIST7_NOTIFY (1 << 15)
45363 +#define VPE_INT0_DESCRIPTOR (1 << 16)
45364 +#define VPE_DEI_FMD_INT (1 << 18)
45365 +
45366 +#define VPE_INT0_STATUS1_RAW_SET 0x0024
45367 +#define VPE_INT0_STATUS1_RAW VPE_INT0_STATUS1_RAW_SET
45368 +#define VPE_INT0_STATUS1_CLR 0x002c
45369 +#define VPE_INT0_STATUS1 VPE_INT0_STATUS1_CLR
45370 +#define VPE_INT0_ENABLE1_SET 0x0034
45371 +#define VPE_INT0_ENABLE1 VPE_INT0_ENABLE1_SET
45372 +#define VPE_INT0_ENABLE1_CLR 0x003c
45373 +#define VPE_INT0_CHANNEL_GROUP0 (1 << 0)
45374 +#define VPE_INT0_CHANNEL_GROUP1 (1 << 1)
45375 +#define VPE_INT0_CHANNEL_GROUP2 (1 << 2)
45376 +#define VPE_INT0_CHANNEL_GROUP3 (1 << 3)
45377 +#define VPE_INT0_CHANNEL_GROUP4 (1 << 4)
45378 +#define VPE_INT0_CHANNEL_GROUP5 (1 << 5)
45379 +#define VPE_INT0_CLIENT (1 << 7)
45380 +#define VPE_DEI_ERROR_INT (1 << 16)
45381 +#define VPE_DS1_UV_ERROR_INT (1 << 22)
45382 +
45383 +#define VPE_INTC_EOI 0x00a0
45384 +
45385 +#define VPE_CLK_ENABLE 0x0100
45386 +#define VPE_VPEDMA_CLK_ENABLE (1 << 0)
45387 +#define VPE_DATA_PATH_CLK_ENABLE (1 << 1)
45388 +
45389 +#define VPE_CLK_RESET 0x0104
45390 +#define VPE_VPDMA_CLK_RESET_MASK 0x1
45391 +#define VPE_VPDMA_CLK_RESET_SHIFT 0
45392 +#define VPE_DATA_PATH_CLK_RESET_MASK 0x1
45393 +#define VPE_DATA_PATH_CLK_RESET_SHIFT 1
45394 +#define VPE_MAIN_RESET_MASK 0x1
45395 +#define VPE_MAIN_RESET_SHIFT 31
45396 +
45397 +#define VPE_CLK_FORMAT_SELECT 0x010c
45398 +#define VPE_CSC_SRC_SELECT_MASK 0x03
45399 +#define VPE_CSC_SRC_SELECT_SHIFT 0
45400 +#define VPE_RGB_OUT_SELECT (1 << 8)
45401 +#define VPE_DS_SRC_SELECT_MASK 0x07
45402 +#define VPE_DS_SRC_SELECT_SHIFT 9
45403 +#define VPE_DS_BYPASS (1 << 16)
45404 +#define VPE_COLOR_SEPARATE_422 (1 << 18)
45405 +
45406 +#define VPE_DS_SRC_DEI_SCALER (5 << VPE_DS_SRC_SELECT_SHIFT)
45407 +#define VPE_CSC_SRC_DEI_SCALER (3 << VPE_CSC_SRC_SELECT_SHIFT)
45408 +
45409 +#define VPE_CLK_RANGE_MAP 0x011c
45410 +#define VPE_RANGE_RANGE_MAP_Y_MASK 0x07
45411 +#define VPE_RANGE_RANGE_MAP_Y_SHIFT 0
45412 +#define VPE_RANGE_RANGE_MAP_UV_MASK 0x07
45413 +#define VPE_RANGE_RANGE_MAP_UV_SHIFT 3
45414 +#define VPE_RANGE_MAP_ON (1 << 6)
45415 +#define VPE_RANGE_REDUCTION_ON (1 << 28)
45416 +
45417 +/* VPE chrominance upsampler regs */
45418 +#define VPE_US1_R0 0x0304
45419 +#define VPE_US2_R0 0x0404
45420 +#define VPE_US3_R0 0x0504
45421 +#define VPE_US_C1_MASK 0x3fff
45422 +#define VPE_US_C1_SHIFT 2
45423 +#define VPE_US_C0_MASK 0x3fff
45424 +#define VPE_US_C0_SHIFT 18
45425 +#define VPE_US_MODE_MASK 0x03
45426 +#define VPE_US_MODE_SHIFT 16
45427 +#define VPE_ANCHOR_FID0_C1_MASK 0x3fff
45428 +#define VPE_ANCHOR_FID0_C1_SHIFT 2
45429 +#define VPE_ANCHOR_FID0_C0_MASK 0x3fff
45430 +#define VPE_ANCHOR_FID0_C0_SHIFT 18
45431 +
45432 +#define VPE_US1_R1 0x0308
45433 +#define VPE_US2_R1 0x0408
45434 +#define VPE_US3_R1 0x0508
45435 +#define VPE_ANCHOR_FID0_C3_MASK 0x3fff
45436 +#define VPE_ANCHOR_FID0_C3_SHIFT 2
45437 +#define VPE_ANCHOR_FID0_C2_MASK 0x3fff
45438 +#define VPE_ANCHOR_FID0_C2_SHIFT 18
45439 +
45440 +#define VPE_US1_R2 0x030c
45441 +#define VPE_US2_R2 0x040c
45442 +#define VPE_US3_R2 0x050c
45443 +#define VPE_INTERP_FID0_C1_MASK 0x3fff
45444 +#define VPE_INTERP_FID0_C1_SHIFT 2
45445 +#define VPE_INTERP_FID0_C0_MASK 0x3fff
45446 +#define VPE_INTERP_FID0_C0_SHIFT 18
45447 +
45448 +#define VPE_US1_R3 0x0310
45449 +#define VPE_US2_R3 0x0410
45450 +#define VPE_US3_R3 0x0510
45451 +#define VPE_INTERP_FID0_C3_MASK 0x3fff
45452 +#define VPE_INTERP_FID0_C3_SHIFT 2
45453 +#define VPE_INTERP_FID0_C2_MASK 0x3fff
45454 +#define VPE_INTERP_FID0_C2_SHIFT 18
45455 +
45456 +#define VPE_US1_R4 0x0314
45457 +#define VPE_US2_R4 0x0414
45458 +#define VPE_US3_R4 0x0514
45459 +#define VPE_ANCHOR_FID1_C1_MASK 0x3fff
45460 +#define VPE_ANCHOR_FID1_C1_SHIFT 2
45461 +#define VPE_ANCHOR_FID1_C0_MASK 0x3fff
45462 +#define VPE_ANCHOR_FID1_C0_SHIFT 18
45463 +
45464 +#define VPE_US1_R5 0x0318
45465 +#define VPE_US2_R5 0x0418
45466 +#define VPE_US3_R5 0x0518
45467 +#define VPE_ANCHOR_FID1_C3_MASK 0x3fff
45468 +#define VPE_ANCHOR_FID1_C3_SHIFT 2
45469 +#define VPE_ANCHOR_FID1_C2_MASK 0x3fff
45470 +#define VPE_ANCHOR_FID1_C2_SHIFT 18
45471 +
45472 +#define VPE_US1_R6 0x031c
45473 +#define VPE_US2_R6 0x041c
45474 +#define VPE_US3_R6 0x051c
45475 +#define VPE_INTERP_FID1_C1_MASK 0x3fff
45476 +#define VPE_INTERP_FID1_C1_SHIFT 2
45477 +#define VPE_INTERP_FID1_C0_MASK 0x3fff
45478 +#define VPE_INTERP_FID1_C0_SHIFT 18
45479 +
45480 +#define VPE_US1_R7 0x0320
45481 +#define VPE_US2_R7 0x0420
45482 +#define VPE_US3_R7 0x0520
45483 +#define VPE_INTERP_FID0_C3_MASK 0x3fff
45484 +#define VPE_INTERP_FID0_C3_SHIFT 2
45485 +#define VPE_INTERP_FID0_C2_MASK 0x3fff
45486 +#define VPE_INTERP_FID0_C2_SHIFT 18
45487 +
45488 +/* VPE de-interlacer regs */
45489 +#define VPE_DEI_FRAME_SIZE 0x0600
45490 +#define VPE_DEI_WIDTH_MASK 0x07ff
45491 +#define VPE_DEI_WIDTH_SHIFT 0
45492 +#define VPE_DEI_HEIGHT_MASK 0x07ff
45493 +#define VPE_DEI_HEIGHT_SHIFT 16
45494 +#define VPE_DEI_INTERLACE_BYPASS (1 << 29)
45495 +#define VPE_DEI_FIELD_FLUSH (1 << 30)
45496 +#define VPE_DEI_PROGRESSIVE (1 << 31)
45497 +
45498 +#define VPE_MDT_BYPASS 0x0604
45499 +#define VPE_MDT_TEMPMAX_BYPASS (1 << 0)
45500 +#define VPE_MDT_SPATMAX_BYPASS (1 << 1)
45501 +
45502 +#define VPE_MDT_SF_THRESHOLD 0x0608
45503 +#define VPE_MDT_SF_SC_THR1_MASK 0xff
45504 +#define VPE_MDT_SF_SC_THR1_SHIFT 0
45505 +#define VPE_MDT_SF_SC_THR2_MASK 0xff
45506 +#define VPE_MDT_SF_SC_THR2_SHIFT 0
45507 +#define VPE_MDT_SF_SC_THR3_MASK 0xff
45508 +#define VPE_MDT_SF_SC_THR3_SHIFT 0
45509 +
45510 +#define VPE_EDI_CONFIG 0x060c
45511 +#define VPE_EDI_INP_MODE_MASK 0x03
45512 +#define VPE_EDI_INP_MODE_SHIFT 0
45513 +#define VPE_EDI_ENABLE_3D (1 << 2)
45514 +#define VPE_EDI_ENABLE_CHROMA_3D (1 << 3)
45515 +#define VPE_EDI_CHROMA3D_COR_THR_MASK 0xff
45516 +#define VPE_EDI_CHROMA3D_COR_THR_SHIFT 8
45517 +#define VPE_EDI_DIR_COR_LOWER_THR_MASK 0xff
45518 +#define VPE_EDI_DIR_COR_LOWER_THR_SHIFT 16
45519 +#define VPE_EDI_COR_SCALE_FACTOR_MASK 0xff
45520 +#define VPE_EDI_COR_SCALE_FACTOR_SHIFT 23
45521 +
45522 +#define VPE_DEI_EDI_LUT_R0 0x0610
45523 +#define VPE_EDI_LUT0_MASK 0x1f
45524 +#define VPE_EDI_LUT0_SHIFT 0
45525 +#define VPE_EDI_LUT1_MASK 0x1f
45526 +#define VPE_EDI_LUT1_SHIFT 8
45527 +#define VPE_EDI_LUT2_MASK 0x1f
45528 +#define VPE_EDI_LUT2_SHIFT 16
45529 +#define VPE_EDI_LUT3_MASK 0x1f
45530 +#define VPE_EDI_LUT3_SHIFT 24
45531 +
45532 +#define VPE_DEI_EDI_LUT_R1 0x0614
45533 +#define VPE_EDI_LUT0_MASK 0x1f
45534 +#define VPE_EDI_LUT0_SHIFT 0
45535 +#define VPE_EDI_LUT1_MASK 0x1f
45536 +#define VPE_EDI_LUT1_SHIFT 8
45537 +#define VPE_EDI_LUT2_MASK 0x1f
45538 +#define VPE_EDI_LUT2_SHIFT 16
45539 +#define VPE_EDI_LUT3_MASK 0x1f
45540 +#define VPE_EDI_LUT3_SHIFT 24
45541 +
45542 +#define VPE_DEI_EDI_LUT_R2 0x0618
45543 +#define VPE_EDI_LUT4_MASK 0x1f
45544 +#define VPE_EDI_LUT4_SHIFT 0
45545 +#define VPE_EDI_LUT5_MASK 0x1f
45546 +#define VPE_EDI_LUT5_SHIFT 8
45547 +#define VPE_EDI_LUT6_MASK 0x1f
45548 +#define VPE_EDI_LUT6_SHIFT 16
45549 +#define VPE_EDI_LUT7_MASK 0x1f
45550 +#define VPE_EDI_LUT7_SHIFT 24
45551 +
45552 +#define VPE_DEI_EDI_LUT_R3 0x061c
45553 +#define VPE_EDI_LUT8_MASK 0x1f
45554 +#define VPE_EDI_LUT8_SHIFT 0
45555 +#define VPE_EDI_LUT9_MASK 0x1f
45556 +#define VPE_EDI_LUT9_SHIFT 8
45557 +#define VPE_EDI_LUT10_MASK 0x1f
45558 +#define VPE_EDI_LUT10_SHIFT 16
45559 +#define VPE_EDI_LUT11_MASK 0x1f
45560 +#define VPE_EDI_LUT11_SHIFT 24
45561 +
45562 +#define VPE_DEI_FMD_WINDOW_R0 0x0620
45563 +#define VPE_FMD_WINDOW_MINX_MASK 0x07ff
45564 +#define VPE_FMD_WINDOW_MINX_SHIFT 0
45565 +#define VPE_FMD_WINDOW_MAXX_MASK 0x07ff
45566 +#define VPE_FMD_WINDOW_MAXX_SHIFT 16
45567 +#define VPE_FMD_WINDOW_ENABLE (1 << 31)
45568 +
45569 +#define VPE_DEI_FMD_WINDOW_R1 0x0624
45570 +#define VPE_FMD_WINDOW_MINY_MASK 0x07ff
45571 +#define VPE_FMD_WINDOW_MINY_SHIFT 0
45572 +#define VPE_FMD_WINDOW_MAXY_MASK 0x07ff
45573 +#define VPE_FMD_WINDOW_MAXY_SHIFT 16
45574 +
45575 +#define VPE_DEI_FMD_CONTROL_R0 0x0628
45576 +#define VPE_FMD_ENABLE (1 << 0)
45577 +#define VPE_FMD_LOCK (1 << 1)
45578 +#define VPE_FMD_JAM_DIR (1 << 2)
45579 +#define VPE_FMD_BED_ENABLE (1 << 3)
45580 +#define VPE_FMD_CAF_FIELD_THR_MASK 0xff
45581 +#define VPE_FMD_CAF_FIELD_THR_SHIFT 16
45582 +#define VPE_FMD_CAF_LINE_THR_MASK 0xff
45583 +#define VPE_FMD_CAF_LINE_THR_SHIFT 24
45584 +
45585 +#define VPE_DEI_FMD_CONTROL_R1 0x062c
45586 +#define VPE_FMD_CAF_THR_MASK 0x000fffff
45587 +#define VPE_FMD_CAF_THR_SHIFT 0
45588 +
45589 +#define VPE_DEI_FMD_STATUS_R0 0x0630
45590 +#define VPE_FMD_CAF_MASK 0x000fffff
45591 +#define VPE_FMD_CAF_SHIFT 0
45592 +#define VPE_FMD_RESET (1 << 24)
45593 +
45594 +#define VPE_DEI_FMD_STATUS_R1 0x0634
45595 +#define VPE_FMD_FIELD_DIFF_MASK 0x0fffffff
45596 +#define VPE_FMD_FIELD_DIFF_SHIFT 0
45597 +
45598 +#define VPE_DEI_FMD_STATUS_R2 0x0638
45599 +#define VPE_FMD_FRAME_DIFF_MASK 0x000fffff
45600 +#define VPE_FMD_FRAME_DIFF_SHIFT 0
45601 +
45602 +/* VPE scaler regs */
45603 +#define VPE_SC_MP_SC0 0x0700
45604 +#define VPE_INTERLACE_O (1 << 0)
45605 +#define VPE_LINEAR (1 << 1)
45606 +#define VPE_SC_BYPASS (1 << 2)
45607 +#define VPE_INVT_FID (1 << 3)
45608 +#define VPE_USE_RAV (1 << 4)
45609 +#define VPE_ENABLE_EV (1 << 5)
45610 +#define VPE_AUTO_HS (1 << 6)
45611 +#define VPE_DCM_2X (1 << 7)
45612 +#define VPE_DCM_4X (1 << 8)
45613 +#define VPE_HP_BYPASS (1 << 9)
45614 +#define VPE_INTERLACE_I (1 << 10)
45615 +#define VPE_ENABLE_SIN2_VER_INTP (1 << 11)
45616 +#define VPE_Y_PK_EN (1 << 14)
45617 +#define VPE_TRIM (1 << 15)
45618 +#define VPE_SELFGEN_FID (1 << 16)
45619 +
45620 +#define VPE_SC_MP_SC1 0x0704
45621 +#define VPE_ROW_ACC_INC_MASK 0x07ffffff
45622 +#define VPE_ROW_ACC_INC_SHIFT 0
45623 +
45624 +#define VPE_SC_MP_SC2 0x0708
45625 +#define VPE_ROW_ACC_OFFSET_MASK 0x0fffffff
45626 +#define VPE_ROW_ACC_OFFSET_SHIFT 0
45627 +
45628 +#define VPE_SC_MP_SC3 0x070c
45629 +#define VPE_ROW_ACC_OFFSET_B_MASK 0x0fffffff
45630 +#define VPE_ROW_ACC_OFFSET_B_SHIFT 0
45631 +
45632 +#define VPE_SC_MP_SC4 0x0710
45633 +#define VPE_TAR_H_MASK 0x07ff
45634 +#define VPE_TAR_H_SHIFT 0
45635 +#define VPE_TAR_W_MASK 0x07ff
45636 +#define VPE_TAR_W_SHIFT 12
45637 +#define VPE_LIN_ACC_INC_U_MASK 0x07
45638 +#define VPE_LIN_ACC_INC_U_SHIFT 24
45639 +#define VPE_NLIN_ACC_INIT_U_MASK 0x07
45640 +#define VPE_NLIN_ACC_INIT_U_SHIFT 28
45641 +
45642 +#define VPE_SC_MP_SC5 0x0714
45643 +#define VPE_SRC_H_MASK 0x07ff
45644 +#define VPE_SRC_H_SHIFT 0
45645 +#define VPE_SRC_W_MASK 0x07ff
45646 +#define VPE_SRC_W_SHIFT 12
45647 +#define VPE_NLIN_ACC_INC_U_MASK 0x07
45648 +#define VPE_NLIN_ACC_INC_U_SHIFT 24
45649 +
45650 +#define VPE_SC_MP_SC6 0x0718
45651 +#define VPE_ROW_ACC_INIT_RAV_MASK 0x03ff
45652 +#define VPE_ROW_ACC_INIT_RAV_SHIFT 0
45653 +#define VPE_ROW_ACC_INIT_RAV_B_MASK 0x03ff
45654 +#define VPE_ROW_ACC_INIT_RAV_B_SHIFT 10
45655 +
45656 +#define VPE_SC_MP_SC8 0x0720
45657 +#define VPE_NLIN_LEFT_MASK 0x07ff
45658 +#define VPE_NLIN_LEFT_SHIFT 0
45659 +#define VPE_NLIN_RIGHT_MASK 0x07ff
45660 +#define VPE_NLIN_RIGHT_SHIFT 12
45661 +
45662 +#define VPE_SC_MP_SC9 0x0724
45663 +#define VPE_LIN_ACC_INC VPE_SC_MP_SC9
45664 +
45665 +#define VPE_SC_MP_SC10 0x0728
45666 +#define VPE_NLIN_ACC_INIT VPE_SC_MP_SC10
45667 +
45668 +#define VPE_SC_MP_SC11 0x072c
45669 +#define VPE_NLIN_ACC_INC VPE_SC_MP_SC11
45670 +
45671 +#define VPE_SC_MP_SC12 0x0730
45672 +#define VPE_COL_ACC_OFFSET_MASK 0x01ffffff
45673 +#define VPE_COL_ACC_OFFSET_SHIFT 0
45674 +
45675 +#define VPE_SC_MP_SC13 0x0734
45676 +#define VPE_SC_FACTOR_RAV_MASK 0x03ff
45677 +#define VPE_SC_FACTOR_RAV_SHIFT 0
45678 +#define VPE_CHROMA_INTP_THR_MASK 0x03ff
45679 +#define VPE_CHROMA_INTP_THR_SHIFT 12
45680 +#define VPE_DELTA_CHROMA_THR_MASK 0x0f
45681 +#define VPE_DELTA_CHROMA_THR_SHIFT 24
45682 +
45683 +#define VPE_SC_MP_SC17 0x0744
45684 +#define VPE_EV_THR_MASK 0x03ff
45685 +#define VPE_EV_THR_SHIFT 12
45686 +#define VPE_DELTA_LUMA_THR_MASK 0x0f
45687 +#define VPE_DELTA_LUMA_THR_SHIFT 24
45688 +#define VPE_DELTA_EV_THR_MASK 0x0f
45689 +#define VPE_DELTA_EV_THR_SHIFT 28
45690 +
45691 +#define VPE_SC_MP_SC18 0x0748
45692 +#define VPE_HS_FACTOR_MASK 0x03ff
45693 +#define VPE_HS_FACTOR_SHIFT 0
45694 +#define VPE_CONF_DEFAULT_MASK 0x01ff
45695 +#define VPE_CONF_DEFAULT_SHIFT 16
45696 +
45697 +#define VPE_SC_MP_SC19 0x074c
45698 +#define VPE_HPF_COEFF0_MASK 0xff
45699 +#define VPE_HPF_COEFF0_SHIFT 0
45700 +#define VPE_HPF_COEFF1_MASK 0xff
45701 +#define VPE_HPF_COEFF1_SHIFT 8
45702 +#define VPE_HPF_COEFF2_MASK 0xff
45703 +#define VPE_HPF_COEFF2_SHIFT 16
45704 +#define VPE_HPF_COEFF3_MASK 0xff
45705 +#define VPE_HPF_COEFF3_SHIFT 23
45706 +
45707 +#define VPE_SC_MP_SC20 0x0750
45708 +#define VPE_HPF_COEFF4_MASK 0xff
45709 +#define VPE_HPF_COEFF4_SHIFT 0
45710 +#define VPE_HPF_COEFF5_MASK 0xff
45711 +#define VPE_HPF_COEFF5_SHIFT 8
45712 +#define VPE_HPF_NORM_SHIFT_MASK 0x07
45713 +#define VPE_HPF_NORM_SHIFT_SHIFT 16
45714 +#define VPE_NL_LIMIT_MASK 0x1ff
45715 +#define VPE_NL_LIMIT_SHIFT 20
45716 +
45717 +#define VPE_SC_MP_SC21 0x0754
45718 +#define VPE_NL_LO_THR_MASK 0x01ff
45719 +#define VPE_NL_LO_THR_SHIFT 0
45720 +#define VPE_NL_LO_SLOPE_MASK 0xff
45721 +#define VPE_NL_LO_SLOPE_SHIFT 16
45722 +
45723 +#define VPE_SC_MP_SC22 0x0758
45724 +#define VPE_NL_HI_THR_MASK 0x01ff
45725 +#define VPE_NL_HI_THR_SHIFT 0
45726 +#define VPE_NL_HI_SLOPE_SH_MASK 0x07
45727 +#define VPE_NL_HI_SLOPE_SH_SHIFT 16
45728 +
45729 +#define VPE_SC_MP_SC23 0x075c
45730 +#define VPE_GRADIENT_THR_MASK 0x07ff
45731 +#define VPE_GRADIENT_THR_SHIFT 0
45732 +#define VPE_GRADIENT_THR_RANGE_MASK 0x0f
45733 +#define VPE_GRADIENT_THR_RANGE_SHIFT 12
45734 +#define VPE_MIN_GY_THR_MASK 0xff
45735 +#define VPE_MIN_GY_THR_SHIFT 16
45736 +#define VPE_MIN_GY_THR_RANGE_MASK 0x0f
45737 +#define VPE_MIN_GY_THR_RANGE_SHIFT 28
45738 +
45739 +#define VPE_SC_MP_SC24 0x0760
45740 +#define VPE_ORG_H_MASK 0x07ff
45741 +#define VPE_ORG_H_SHIFT 0
45742 +#define VPE_ORG_W_MASK 0x07ff
45743 +#define VPE_ORG_W_SHIFT 16
45744 +
45745 +#define VPE_SC_MP_SC25 0x0764
45746 +#define VPE_OFF_H_MASK 0x07ff
45747 +#define VPE_OFF_H_SHIFT 0
45748 +#define VPE_OFF_W_MASK 0x07ff
45749 +#define VPE_OFF_W_SHIFT 16
45750 +
45751 +/* VPE color space converter regs */
45752 +#define VPE_CSC_CSC00 0x5700
45753 +#define VPE_CSC_A0_MASK 0x1fff
45754 +#define VPE_CSC_A0_SHIFT 0
45755 +#define VPE_CSC_B0_MASK 0x1fff
45756 +#define VPE_CSC_B0_SHIFT 16
45757 +
45758 +#define VPE_CSC_CSC01 0x5704
45759 +#define VPE_CSC_C0_MASK 0x1fff
45760 +#define VPE_CSC_C0_SHIFT 0
45761 +#define VPE_CSC_A1_MASK 0x1fff
45762 +#define VPE_CSC_A1_SHIFT 16
45763 +
45764 +#define VPE_CSC_CSC02 0x5708
45765 +#define VPE_CSC_B1_MASK 0x1fff
45766 +#define VPE_CSC_B1_SHIFT 0
45767 +#define VPE_CSC_C1_MASK 0x1fff
45768 +#define VPE_CSC_C1_SHIFT 16
45769 +
45770 +#define VPE_CSC_CSC03 0x570c
45771 +#define VPE_CSC_A2_MASK 0x1fff
45772 +#define VPE_CSC_A2_SHIFT 0
45773 +#define VPE_CSC_B2_MASK 0x1fff
45774 +#define VPE_CSC_B2_SHIFT 16
45775 +
45776 +#define VPE_CSC_CSC04 0x5710
45777 +#define VPE_CSC_C2_MASK 0x1fff
45778 +#define VPE_CSC_C2_SHIFT 0
45779 +#define VPE_CSC_D0_MASK 0x0fff
45780 +#define VPE_CSC_D0_SHIFT 16
45781 +
45782 +#define VPE_CSC_CSC05 0x5714
45783 +#define VPE_CSC_D1_MASK 0x0fff
45784 +#define VPE_CSC_D1_SHIFT 0
45785 +#define VPE_CSC_D2_MASK 0x0fff
45786 +#define VPE_CSC_D2_SHIFT 16
45787 +#define VPE_CSC_BYPASS (1 << 28)
45788 +
45789 +#endif
45790 --- a/drivers/memory/emif.h
45791 +++ b/drivers/memory/emif.h
45792 @@ -12,548 +12,7 @@
45793 #ifndef __EMIF_H
45794 #define __EMIF_H
45795
45796 -/*
45797 - * Maximum number of different frequencies supported by EMIF driver
45798 - * Determines the number of entries in the pointer array for register
45799 - * cache
45800 - */
45801 -#define EMIF_MAX_NUM_FREQUENCIES 6
45802 -
45803 -/* State of the core voltage */
45804 -#define DDR_VOLTAGE_STABLE 0
45805 -#define DDR_VOLTAGE_RAMPING 1
45806 -
45807 -/* Defines for timing De-rating */
45808 -#define EMIF_NORMAL_TIMINGS 0
45809 -#define EMIF_DERATED_TIMINGS 1
45810 -
45811 -/* Length of the forced read idle period in terms of cycles */
45812 -#define EMIF_READ_IDLE_LEN_VAL 5
45813 -
45814 -/*
45815 - * forced read idle interval to be used when voltage
45816 - * is changed as part of DVFS/DPS - 1ms
45817 - */
45818 -#define READ_IDLE_INTERVAL_DVFS (1*1000000)
45819 -
45820 -/*
45821 - * Forced read idle interval to be used when voltage is stable
45822 - * 50us - or maximum value will do
45823 - */
45824 -#define READ_IDLE_INTERVAL_NORMAL (50*1000000)
45825 -
45826 -/* DLL calibration interval when voltage is NOT stable - 1us */
45827 -#define DLL_CALIB_INTERVAL_DVFS (1*1000000)
45828 -
45829 -#define DLL_CALIB_ACK_WAIT_VAL 5
45830 -
45831 -/* Interval between ZQCS commands - hw team recommended value */
45832 -#define EMIF_ZQCS_INTERVAL_US (50*1000)
45833 -/* Enable ZQ Calibration on exiting Self-refresh */
45834 -#define ZQ_SFEXITEN_ENABLE 1
45835 -/*
45836 - * ZQ Calibration simultaneously on both chip-selects:
45837 - * Needs one calibration resistor per CS
45838 - */
45839 -#define ZQ_DUALCALEN_DISABLE 0
45840 -#define ZQ_DUALCALEN_ENABLE 1
45841 -
45842 -#define T_ZQCS_DEFAULT_NS 90
45843 -#define T_ZQCL_DEFAULT_NS 360
45844 -#define T_ZQINIT_DEFAULT_NS 1000
45845 -
45846 -/* DPD_EN */
45847 -#define DPD_DISABLE 0
45848 -#define DPD_ENABLE 1
45849 -
45850 -/*
45851 - * Default values for the low-power entry to be used if not provided by user.
45852 - * OMAP4/5 has a hw bug(i735) due to which this value can not be less than 512
45853 - * Timeout values are in DDR clock 'cycles' and frequency threshold in Hz
45854 - */
45855 -#define EMIF_LP_MODE_TIMEOUT_PERFORMANCE 2048
45856 -#define EMIF_LP_MODE_TIMEOUT_POWER 512
45857 -#define EMIF_LP_MODE_FREQ_THRESHOLD 400000000
45858 -
45859 -/* DDR_PHY_CTRL_1 values for EMIF4D - ATTILA PHY combination */
45860 -#define EMIF_DDR_PHY_CTRL_1_BASE_VAL_ATTILAPHY 0x049FF000
45861 -#define EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ_ATTILAPHY 0x41
45862 -#define EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ_ATTILAPHY 0x80
45863 -#define EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS_ATTILAPHY 0xFF
45864 -
45865 -/* DDR_PHY_CTRL_1 values for EMIF4D5 INTELLIPHY combination */
45866 -#define EMIF_DDR_PHY_CTRL_1_BASE_VAL_INTELLIPHY 0x0E084200
45867 -#define EMIF_PHY_TOTAL_READ_LATENCY_INTELLIPHY_PS 10000
45868 -
45869 -/* TEMP_ALERT_CONFIG - corresponding to temp gradient 5 C/s */
45870 -#define TEMP_ALERT_POLL_INTERVAL_DEFAULT_MS 360
45871 -
45872 -#define EMIF_T_CSTA 3
45873 -#define EMIF_T_PDLL_UL 128
45874 -
45875 -/* External PHY control registers magic values */
45876 -#define EMIF_EXT_PHY_CTRL_1_VAL 0x04020080
45877 -#define EMIF_EXT_PHY_CTRL_5_VAL 0x04010040
45878 -#define EMIF_EXT_PHY_CTRL_6_VAL 0x01004010
45879 -#define EMIF_EXT_PHY_CTRL_7_VAL 0x00001004
45880 -#define EMIF_EXT_PHY_CTRL_8_VAL 0x04010040
45881 -#define EMIF_EXT_PHY_CTRL_9_VAL 0x01004010
45882 -#define EMIF_EXT_PHY_CTRL_10_VAL 0x00001004
45883 -#define EMIF_EXT_PHY_CTRL_11_VAL 0x00000000
45884 -#define EMIF_EXT_PHY_CTRL_12_VAL 0x00000000
45885 -#define EMIF_EXT_PHY_CTRL_13_VAL 0x00000000
45886 -#define EMIF_EXT_PHY_CTRL_14_VAL 0x80080080
45887 -#define EMIF_EXT_PHY_CTRL_15_VAL 0x00800800
45888 -#define EMIF_EXT_PHY_CTRL_16_VAL 0x08102040
45889 -#define EMIF_EXT_PHY_CTRL_17_VAL 0x00000001
45890 -#define EMIF_EXT_PHY_CTRL_18_VAL 0x540A8150
45891 -#define EMIF_EXT_PHY_CTRL_19_VAL 0xA81502A0
45892 -#define EMIF_EXT_PHY_CTRL_20_VAL 0x002A0540
45893 -#define EMIF_EXT_PHY_CTRL_21_VAL 0x00000000
45894 -#define EMIF_EXT_PHY_CTRL_22_VAL 0x00000000
45895 -#define EMIF_EXT_PHY_CTRL_23_VAL 0x00000000
45896 -#define EMIF_EXT_PHY_CTRL_24_VAL 0x00000077
45897 -
45898 -#define EMIF_INTELLI_PHY_DQS_GATE_OPENING_DELAY_PS 1200
45899 -
45900 -/* Registers offset */
45901 -#define EMIF_MODULE_ID_AND_REVISION 0x0000
45902 -#define EMIF_STATUS 0x0004
45903 -#define EMIF_SDRAM_CONFIG 0x0008
45904 -#define EMIF_SDRAM_CONFIG_2 0x000c
45905 -#define EMIF_SDRAM_REFRESH_CONTROL 0x0010
45906 -#define EMIF_SDRAM_REFRESH_CTRL_SHDW 0x0014
45907 -#define EMIF_SDRAM_TIMING_1 0x0018
45908 -#define EMIF_SDRAM_TIMING_1_SHDW 0x001c
45909 -#define EMIF_SDRAM_TIMING_2 0x0020
45910 -#define EMIF_SDRAM_TIMING_2_SHDW 0x0024
45911 -#define EMIF_SDRAM_TIMING_3 0x0028
45912 -#define EMIF_SDRAM_TIMING_3_SHDW 0x002c
45913 -#define EMIF_LPDDR2_NVM_TIMING 0x0030
45914 -#define EMIF_LPDDR2_NVM_TIMING_SHDW 0x0034
45915 -#define EMIF_POWER_MANAGEMENT_CONTROL 0x0038
45916 -#define EMIF_POWER_MANAGEMENT_CTRL_SHDW 0x003c
45917 -#define EMIF_LPDDR2_MODE_REG_DATA 0x0040
45918 -#define EMIF_LPDDR2_MODE_REG_CONFIG 0x0050
45919 -#define EMIF_OCP_CONFIG 0x0054
45920 -#define EMIF_OCP_CONFIG_VALUE_1 0x0058
45921 -#define EMIF_OCP_CONFIG_VALUE_2 0x005c
45922 -#define EMIF_IODFT_TEST_LOGIC_GLOBAL_CONTROL 0x0060
45923 -#define EMIF_IODFT_TEST_LOGIC_CTRL_MISR_RESULT 0x0064
45924 -#define EMIF_IODFT_TEST_LOGIC_ADDRESS_MISR_RESULT 0x0068
45925 -#define EMIF_IODFT_TEST_LOGIC_DATA_MISR_RESULT_1 0x006c
45926 -#define EMIF_IODFT_TEST_LOGIC_DATA_MISR_RESULT_2 0x0070
45927 -#define EMIF_IODFT_TEST_LOGIC_DATA_MISR_RESULT_3 0x0074
45928 -#define EMIF_PERFORMANCE_COUNTER_1 0x0080
45929 -#define EMIF_PERFORMANCE_COUNTER_2 0x0084
45930 -#define EMIF_PERFORMANCE_COUNTER_CONFIG 0x0088
45931 -#define EMIF_PERFORMANCE_COUNTER_MASTER_REGION_SELECT 0x008c
45932 -#define EMIF_PERFORMANCE_COUNTER_TIME 0x0090
45933 -#define EMIF_MISC_REG 0x0094
45934 -#define EMIF_DLL_CALIB_CTRL 0x0098
45935 -#define EMIF_DLL_CALIB_CTRL_SHDW 0x009c
45936 -#define EMIF_END_OF_INTERRUPT 0x00a0
45937 -#define EMIF_SYSTEM_OCP_INTERRUPT_RAW_STATUS 0x00a4
45938 -#define EMIF_LL_OCP_INTERRUPT_RAW_STATUS 0x00a8
45939 -#define EMIF_SYSTEM_OCP_INTERRUPT_STATUS 0x00ac
45940 -#define EMIF_LL_OCP_INTERRUPT_STATUS 0x00b0
45941 -#define EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_SET 0x00b4
45942 -#define EMIF_LL_OCP_INTERRUPT_ENABLE_SET 0x00b8
45943 -#define EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_CLEAR 0x00bc
45944 -#define EMIF_LL_OCP_INTERRUPT_ENABLE_CLEAR 0x00c0
45945 -#define EMIF_SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG 0x00c8
45946 -#define EMIF_TEMPERATURE_ALERT_CONFIG 0x00cc
45947 -#define EMIF_OCP_ERROR_LOG 0x00d0
45948 -#define EMIF_READ_WRITE_LEVELING_RAMP_WINDOW 0x00d4
45949 -#define EMIF_READ_WRITE_LEVELING_RAMP_CONTROL 0x00d8
45950 -#define EMIF_READ_WRITE_LEVELING_CONTROL 0x00dc
45951 -#define EMIF_DDR_PHY_CTRL_1 0x00e4
45952 -#define EMIF_DDR_PHY_CTRL_1_SHDW 0x00e8
45953 -#define EMIF_DDR_PHY_CTRL_2 0x00ec
45954 -#define EMIF_PRIORITY_TO_CLASS_OF_SERVICE_MAPPING 0x0100
45955 -#define EMIF_CONNECTION_ID_TO_CLASS_OF_SERVICE_1_MAPPING 0x0104
45956 -#define EMIF_CONNECTION_ID_TO_CLASS_OF_SERVICE_2_MAPPING 0x0108
45957 -#define EMIF_READ_WRITE_EXECUTION_THRESHOLD 0x0120
45958 -#define EMIF_COS_CONFIG 0x0124
45959 -#define EMIF_PHY_STATUS_1 0x0140
45960 -#define EMIF_PHY_STATUS_2 0x0144
45961 -#define EMIF_PHY_STATUS_3 0x0148
45962 -#define EMIF_PHY_STATUS_4 0x014c
45963 -#define EMIF_PHY_STATUS_5 0x0150
45964 -#define EMIF_PHY_STATUS_6 0x0154
45965 -#define EMIF_PHY_STATUS_7 0x0158
45966 -#define EMIF_PHY_STATUS_8 0x015c
45967 -#define EMIF_PHY_STATUS_9 0x0160
45968 -#define EMIF_PHY_STATUS_10 0x0164
45969 -#define EMIF_PHY_STATUS_11 0x0168
45970 -#define EMIF_PHY_STATUS_12 0x016c
45971 -#define EMIF_PHY_STATUS_13 0x0170
45972 -#define EMIF_PHY_STATUS_14 0x0174
45973 -#define EMIF_PHY_STATUS_15 0x0178
45974 -#define EMIF_PHY_STATUS_16 0x017c
45975 -#define EMIF_PHY_STATUS_17 0x0180
45976 -#define EMIF_PHY_STATUS_18 0x0184
45977 -#define EMIF_PHY_STATUS_19 0x0188
45978 -#define EMIF_PHY_STATUS_20 0x018c
45979 -#define EMIF_PHY_STATUS_21 0x0190
45980 -#define EMIF_EXT_PHY_CTRL_1 0x0200
45981 -#define EMIF_EXT_PHY_CTRL_1_SHDW 0x0204
45982 -#define EMIF_EXT_PHY_CTRL_2 0x0208
45983 -#define EMIF_EXT_PHY_CTRL_2_SHDW 0x020c
45984 -#define EMIF_EXT_PHY_CTRL_3 0x0210
45985 -#define EMIF_EXT_PHY_CTRL_3_SHDW 0x0214
45986 -#define EMIF_EXT_PHY_CTRL_4 0x0218
45987 -#define EMIF_EXT_PHY_CTRL_4_SHDW 0x021c
45988 -#define EMIF_EXT_PHY_CTRL_5 0x0220
45989 -#define EMIF_EXT_PHY_CTRL_5_SHDW 0x0224
45990 -#define EMIF_EXT_PHY_CTRL_6 0x0228
45991 -#define EMIF_EXT_PHY_CTRL_6_SHDW 0x022c
45992 -#define EMIF_EXT_PHY_CTRL_7 0x0230
45993 -#define EMIF_EXT_PHY_CTRL_7_SHDW 0x0234
45994 -#define EMIF_EXT_PHY_CTRL_8 0x0238
45995 -#define EMIF_EXT_PHY_CTRL_8_SHDW 0x023c
45996 -#define EMIF_EXT_PHY_CTRL_9 0x0240
45997 -#define EMIF_EXT_PHY_CTRL_9_SHDW 0x0244
45998 -#define EMIF_EXT_PHY_CTRL_10 0x0248
45999 -#define EMIF_EXT_PHY_CTRL_10_SHDW 0x024c
46000 -#define EMIF_EXT_PHY_CTRL_11 0x0250
46001 -#define EMIF_EXT_PHY_CTRL_11_SHDW 0x0254
46002 -#define EMIF_EXT_PHY_CTRL_12 0x0258
46003 -#define EMIF_EXT_PHY_CTRL_12_SHDW 0x025c
46004 -#define EMIF_EXT_PHY_CTRL_13 0x0260
46005 -#define EMIF_EXT_PHY_CTRL_13_SHDW 0x0264
46006 -#define EMIF_EXT_PHY_CTRL_14 0x0268
46007 -#define EMIF_EXT_PHY_CTRL_14_SHDW 0x026c
46008 -#define EMIF_EXT_PHY_CTRL_15 0x0270
46009 -#define EMIF_EXT_PHY_CTRL_15_SHDW 0x0274
46010 -#define EMIF_EXT_PHY_CTRL_16 0x0278
46011 -#define EMIF_EXT_PHY_CTRL_16_SHDW 0x027c
46012 -#define EMIF_EXT_PHY_CTRL_17 0x0280
46013 -#define EMIF_EXT_PHY_CTRL_17_SHDW 0x0284
46014 -#define EMIF_EXT_PHY_CTRL_18 0x0288
46015 -#define EMIF_EXT_PHY_CTRL_18_SHDW 0x028c
46016 -#define EMIF_EXT_PHY_CTRL_19 0x0290
46017 -#define EMIF_EXT_PHY_CTRL_19_SHDW 0x0294
46018 -#define EMIF_EXT_PHY_CTRL_20 0x0298
46019 -#define EMIF_EXT_PHY_CTRL_20_SHDW 0x029c
46020 -#define EMIF_EXT_PHY_CTRL_21 0x02a0
46021 -#define EMIF_EXT_PHY_CTRL_21_SHDW 0x02a4
46022 -#define EMIF_EXT_PHY_CTRL_22 0x02a8
46023 -#define EMIF_EXT_PHY_CTRL_22_SHDW 0x02ac
46024 -#define EMIF_EXT_PHY_CTRL_23 0x02b0
46025 -#define EMIF_EXT_PHY_CTRL_23_SHDW 0x02b4
46026 -#define EMIF_EXT_PHY_CTRL_24 0x02b8
46027 -#define EMIF_EXT_PHY_CTRL_24_SHDW 0x02bc
46028 -#define EMIF_EXT_PHY_CTRL_25 0x02c0
46029 -#define EMIF_EXT_PHY_CTRL_25_SHDW 0x02c4
46030 -#define EMIF_EXT_PHY_CTRL_26 0x02c8
46031 -#define EMIF_EXT_PHY_CTRL_26_SHDW 0x02cc
46032 -#define EMIF_EXT_PHY_CTRL_27 0x02d0
46033 -#define EMIF_EXT_PHY_CTRL_27_SHDW 0x02d4
46034 -#define EMIF_EXT_PHY_CTRL_28 0x02d8
46035 -#define EMIF_EXT_PHY_CTRL_28_SHDW 0x02dc
46036 -#define EMIF_EXT_PHY_CTRL_29 0x02e0
46037 -#define EMIF_EXT_PHY_CTRL_29_SHDW 0x02e4
46038 -#define EMIF_EXT_PHY_CTRL_30 0x02e8
46039 -#define EMIF_EXT_PHY_CTRL_30_SHDW 0x02ec
46040 -
46041 -/* Registers shifts and masks */
46042 -
46043 -/* EMIF_MODULE_ID_AND_REVISION */
46044 -#define SCHEME_SHIFT 30
46045 -#define SCHEME_MASK (0x3 << 30)
46046 -#define MODULE_ID_SHIFT 16
46047 -#define MODULE_ID_MASK (0xfff << 16)
46048 -#define RTL_VERSION_SHIFT 11
46049 -#define RTL_VERSION_MASK (0x1f << 11)
46050 -#define MAJOR_REVISION_SHIFT 8
46051 -#define MAJOR_REVISION_MASK (0x7 << 8)
46052 -#define MINOR_REVISION_SHIFT 0
46053 -#define MINOR_REVISION_MASK (0x3f << 0)
46054 -
46055 -/* STATUS */
46056 -#define BE_SHIFT 31
46057 -#define BE_MASK (1 << 31)
46058 -#define DUAL_CLK_MODE_SHIFT 30
46059 -#define DUAL_CLK_MODE_MASK (1 << 30)
46060 -#define FAST_INIT_SHIFT 29
46061 -#define FAST_INIT_MASK (1 << 29)
46062 -#define RDLVLGATETO_SHIFT 6
46063 -#define RDLVLGATETO_MASK (1 << 6)
46064 -#define RDLVLTO_SHIFT 5
46065 -#define RDLVLTO_MASK (1 << 5)
46066 -#define WRLVLTO_SHIFT 4
46067 -#define WRLVLTO_MASK (1 << 4)
46068 -#define PHY_DLL_READY_SHIFT 2
46069 -#define PHY_DLL_READY_MASK (1 << 2)
46070 -
46071 -/* SDRAM_CONFIG */
46072 -#define SDRAM_TYPE_SHIFT 29
46073 -#define SDRAM_TYPE_MASK (0x7 << 29)
46074 -#define IBANK_POS_SHIFT 27
46075 -#define IBANK_POS_MASK (0x3 << 27)
46076 -#define DDR_TERM_SHIFT 24
46077 -#define DDR_TERM_MASK (0x7 << 24)
46078 -#define DDR2_DDQS_SHIFT 23
46079 -#define DDR2_DDQS_MASK (1 << 23)
46080 -#define DYN_ODT_SHIFT 21
46081 -#define DYN_ODT_MASK (0x3 << 21)
46082 -#define DDR_DISABLE_DLL_SHIFT 20
46083 -#define DDR_DISABLE_DLL_MASK (1 << 20)
46084 -#define SDRAM_DRIVE_SHIFT 18
46085 -#define SDRAM_DRIVE_MASK (0x3 << 18)
46086 -#define CWL_SHIFT 16
46087 -#define CWL_MASK (0x3 << 16)
46088 -#define NARROW_MODE_SHIFT 14
46089 -#define NARROW_MODE_MASK (0x3 << 14)
46090 -#define CL_SHIFT 10
46091 -#define CL_MASK (0xf << 10)
46092 -#define ROWSIZE_SHIFT 7
46093 -#define ROWSIZE_MASK (0x7 << 7)
46094 -#define IBANK_SHIFT 4
46095 -#define IBANK_MASK (0x7 << 4)
46096 -#define EBANK_SHIFT 3
46097 -#define EBANK_MASK (1 << 3)
46098 -#define PAGESIZE_SHIFT 0
46099 -#define PAGESIZE_MASK (0x7 << 0)
46100 -
46101 -/* SDRAM_CONFIG_2 */
46102 -#define CS1NVMEN_SHIFT 30
46103 -#define CS1NVMEN_MASK (1 << 30)
46104 -#define EBANK_POS_SHIFT 27
46105 -#define EBANK_POS_MASK (1 << 27)
46106 -#define RDBNUM_SHIFT 4
46107 -#define RDBNUM_MASK (0x3 << 4)
46108 -#define RDBSIZE_SHIFT 0
46109 -#define RDBSIZE_MASK (0x7 << 0)
46110 -
46111 -/* SDRAM_REFRESH_CONTROL */
46112 -#define INITREF_DIS_SHIFT 31
46113 -#define INITREF_DIS_MASK (1 << 31)
46114 -#define SRT_SHIFT 29
46115 -#define SRT_MASK (1 << 29)
46116 -#define ASR_SHIFT 28
46117 -#define ASR_MASK (1 << 28)
46118 -#define PASR_SHIFT 24
46119 -#define PASR_MASK (0x7 << 24)
46120 -#define REFRESH_RATE_SHIFT 0
46121 -#define REFRESH_RATE_MASK (0xffff << 0)
46122 -
46123 -/* SDRAM_TIMING_1 */
46124 -#define T_RTW_SHIFT 29
46125 -#define T_RTW_MASK (0x7 << 29)
46126 -#define T_RP_SHIFT 25
46127 -#define T_RP_MASK (0xf << 25)
46128 -#define T_RCD_SHIFT 21
46129 -#define T_RCD_MASK (0xf << 21)
46130 -#define T_WR_SHIFT 17
46131 -#define T_WR_MASK (0xf << 17)
46132 -#define T_RAS_SHIFT 12
46133 -#define T_RAS_MASK (0x1f << 12)
46134 -#define T_RC_SHIFT 6
46135 -#define T_RC_MASK (0x3f << 6)
46136 -#define T_RRD_SHIFT 3
46137 -#define T_RRD_MASK (0x7 << 3)
46138 -#define T_WTR_SHIFT 0
46139 -#define T_WTR_MASK (0x7 << 0)
46140 -
46141 -/* SDRAM_TIMING_2 */
46142 -#define T_XP_SHIFT 28
46143 -#define T_XP_MASK (0x7 << 28)
46144 -#define T_ODT_SHIFT 25
46145 -#define T_ODT_MASK (0x7 << 25)
46146 -#define T_XSNR_SHIFT 16
46147 -#define T_XSNR_MASK (0x1ff << 16)
46148 -#define T_XSRD_SHIFT 6
46149 -#define T_XSRD_MASK (0x3ff << 6)
46150 -#define T_RTP_SHIFT 3
46151 -#define T_RTP_MASK (0x7 << 3)
46152 -#define T_CKE_SHIFT 0
46153 -#define T_CKE_MASK (0x7 << 0)
46154 -
46155 -/* SDRAM_TIMING_3 */
46156 -#define T_PDLL_UL_SHIFT 28
46157 -#define T_PDLL_UL_MASK (0xf << 28)
46158 -#define T_CSTA_SHIFT 24
46159 -#define T_CSTA_MASK (0xf << 24)
46160 -#define T_CKESR_SHIFT 21
46161 -#define T_CKESR_MASK (0x7 << 21)
46162 -#define ZQ_ZQCS_SHIFT 15
46163 -#define ZQ_ZQCS_MASK (0x3f << 15)
46164 -#define T_TDQSCKMAX_SHIFT 13
46165 -#define T_TDQSCKMAX_MASK (0x3 << 13)
46166 -#define T_RFC_SHIFT 4
46167 -#define T_RFC_MASK (0x1ff << 4)
46168 -#define T_RAS_MAX_SHIFT 0
46169 -#define T_RAS_MAX_MASK (0xf << 0)
46170 -
46171 -/* POWER_MANAGEMENT_CONTROL */
46172 -#define PD_TIM_SHIFT 12
46173 -#define PD_TIM_MASK (0xf << 12)
46174 -#define DPD_EN_SHIFT 11
46175 -#define DPD_EN_MASK (1 << 11)
46176 -#define LP_MODE_SHIFT 8
46177 -#define LP_MODE_MASK (0x7 << 8)
46178 -#define SR_TIM_SHIFT 4
46179 -#define SR_TIM_MASK (0xf << 4)
46180 -#define CS_TIM_SHIFT 0
46181 -#define CS_TIM_MASK (0xf << 0)
46182 -
46183 -/* LPDDR2_MODE_REG_DATA */
46184 -#define VALUE_0_SHIFT 0
46185 -#define VALUE_0_MASK (0x7f << 0)
46186 -
46187 -/* LPDDR2_MODE_REG_CONFIG */
46188 -#define CS_SHIFT 31
46189 -#define CS_MASK (1 << 31)
46190 -#define REFRESH_EN_SHIFT 30
46191 -#define REFRESH_EN_MASK (1 << 30)
46192 -#define ADDRESS_SHIFT 0
46193 -#define ADDRESS_MASK (0xff << 0)
46194 -
46195 -/* OCP_CONFIG */
46196 -#define SYS_THRESH_MAX_SHIFT 24
46197 -#define SYS_THRESH_MAX_MASK (0xf << 24)
46198 -#define MPU_THRESH_MAX_SHIFT 20
46199 -#define MPU_THRESH_MAX_MASK (0xf << 20)
46200 -#define LL_THRESH_MAX_SHIFT 16
46201 -#define LL_THRESH_MAX_MASK (0xf << 16)
46202 -
46203 -/* PERFORMANCE_COUNTER_1 */
46204 -#define COUNTER1_SHIFT 0
46205 -#define COUNTER1_MASK (0xffffffff << 0)
46206 -
46207 -/* PERFORMANCE_COUNTER_2 */
46208 -#define COUNTER2_SHIFT 0
46209 -#define COUNTER2_MASK (0xffffffff << 0)
46210 -
46211 -/* PERFORMANCE_COUNTER_CONFIG */
46212 -#define CNTR2_MCONNID_EN_SHIFT 31
46213 -#define CNTR2_MCONNID_EN_MASK (1 << 31)
46214 -#define CNTR2_REGION_EN_SHIFT 30
46215 -#define CNTR2_REGION_EN_MASK (1 << 30)
46216 -#define CNTR2_CFG_SHIFT 16
46217 -#define CNTR2_CFG_MASK (0xf << 16)
46218 -#define CNTR1_MCONNID_EN_SHIFT 15
46219 -#define CNTR1_MCONNID_EN_MASK (1 << 15)
46220 -#define CNTR1_REGION_EN_SHIFT 14
46221 -#define CNTR1_REGION_EN_MASK (1 << 14)
46222 -#define CNTR1_CFG_SHIFT 0
46223 -#define CNTR1_CFG_MASK (0xf << 0)
46224 -
46225 -/* PERFORMANCE_COUNTER_MASTER_REGION_SELECT */
46226 -#define MCONNID2_SHIFT 24
46227 -#define MCONNID2_MASK (0xff << 24)
46228 -#define REGION_SEL2_SHIFT 16
46229 -#define REGION_SEL2_MASK (0x3 << 16)
46230 -#define MCONNID1_SHIFT 8
46231 -#define MCONNID1_MASK (0xff << 8)
46232 -#define REGION_SEL1_SHIFT 0
46233 -#define REGION_SEL1_MASK (0x3 << 0)
46234 -
46235 -/* PERFORMANCE_COUNTER_TIME */
46236 -#define TOTAL_TIME_SHIFT 0
46237 -#define TOTAL_TIME_MASK (0xffffffff << 0)
46238 -
46239 -/* DLL_CALIB_CTRL */
46240 -#define ACK_WAIT_SHIFT 16
46241 -#define ACK_WAIT_MASK (0xf << 16)
46242 -#define DLL_CALIB_INTERVAL_SHIFT 0
46243 -#define DLL_CALIB_INTERVAL_MASK (0x1ff << 0)
46244 -
46245 -/* END_OF_INTERRUPT */
46246 -#define EOI_SHIFT 0
46247 -#define EOI_MASK (1 << 0)
46248 -
46249 -/* SYSTEM_OCP_INTERRUPT_RAW_STATUS */
46250 -#define DNV_SYS_SHIFT 2
46251 -#define DNV_SYS_MASK (1 << 2)
46252 -#define TA_SYS_SHIFT 1
46253 -#define TA_SYS_MASK (1 << 1)
46254 -#define ERR_SYS_SHIFT 0
46255 -#define ERR_SYS_MASK (1 << 0)
46256 -
46257 -/* LOW_LATENCY_OCP_INTERRUPT_RAW_STATUS */
46258 -#define DNV_LL_SHIFT 2
46259 -#define DNV_LL_MASK (1 << 2)
46260 -#define TA_LL_SHIFT 1
46261 -#define TA_LL_MASK (1 << 1)
46262 -#define ERR_LL_SHIFT 0
46263 -#define ERR_LL_MASK (1 << 0)
46264 -
46265 -/* SYSTEM_OCP_INTERRUPT_ENABLE_SET */
46266 -#define EN_DNV_SYS_SHIFT 2
46267 -#define EN_DNV_SYS_MASK (1 << 2)
46268 -#define EN_TA_SYS_SHIFT 1
46269 -#define EN_TA_SYS_MASK (1 << 1)
46270 -#define EN_ERR_SYS_SHIFT 0
46271 -#define EN_ERR_SYS_MASK (1 << 0)
46272 -
46273 -/* LOW_LATENCY_OCP_INTERRUPT_ENABLE_SET */
46274 -#define EN_DNV_LL_SHIFT 2
46275 -#define EN_DNV_LL_MASK (1 << 2)
46276 -#define EN_TA_LL_SHIFT 1
46277 -#define EN_TA_LL_MASK (1 << 1)
46278 -#define EN_ERR_LL_SHIFT 0
46279 -#define EN_ERR_LL_MASK (1 << 0)
46280 -
46281 -/* SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG */
46282 -#define ZQ_CS1EN_SHIFT 31
46283 -#define ZQ_CS1EN_MASK (1 << 31)
46284 -#define ZQ_CS0EN_SHIFT 30
46285 -#define ZQ_CS0EN_MASK (1 << 30)
46286 -#define ZQ_DUALCALEN_SHIFT 29
46287 -#define ZQ_DUALCALEN_MASK (1 << 29)
46288 -#define ZQ_SFEXITEN_SHIFT 28
46289 -#define ZQ_SFEXITEN_MASK (1 << 28)
46290 -#define ZQ_ZQINIT_MULT_SHIFT 18
46291 -#define ZQ_ZQINIT_MULT_MASK (0x3 << 18)
46292 -#define ZQ_ZQCL_MULT_SHIFT 16
46293 -#define ZQ_ZQCL_MULT_MASK (0x3 << 16)
46294 -#define ZQ_REFINTERVAL_SHIFT 0
46295 -#define ZQ_REFINTERVAL_MASK (0xffff << 0)
46296 -
46297 -/* TEMPERATURE_ALERT_CONFIG */
46298 -#define TA_CS1EN_SHIFT 31
46299 -#define TA_CS1EN_MASK (1 << 31)
46300 -#define TA_CS0EN_SHIFT 30
46301 -#define TA_CS0EN_MASK (1 << 30)
46302 -#define TA_SFEXITEN_SHIFT 28
46303 -#define TA_SFEXITEN_MASK (1 << 28)
46304 -#define TA_DEVWDT_SHIFT 26
46305 -#define TA_DEVWDT_MASK (0x3 << 26)
46306 -#define TA_DEVCNT_SHIFT 24
46307 -#define TA_DEVCNT_MASK (0x3 << 24)
46308 -#define TA_REFINTERVAL_SHIFT 0
46309 -#define TA_REFINTERVAL_MASK (0x3fffff << 0)
46310 -
46311 -/* OCP_ERROR_LOG */
46312 -#define MADDRSPACE_SHIFT 14
46313 -#define MADDRSPACE_MASK (0x3 << 14)
46314 -#define MBURSTSEQ_SHIFT 11
46315 -#define MBURSTSEQ_MASK (0x7 << 11)
46316 -#define MCMD_SHIFT 8
46317 -#define MCMD_MASK (0x7 << 8)
46318 -#define MCONNID_SHIFT 0
46319 -#define MCONNID_MASK (0xff << 0)
46320 -
46321 -/* DDR_PHY_CTRL_1 - EMIF4D */
46322 -#define DLL_SLAVE_DLY_CTRL_SHIFT_4D 4
46323 -#define DLL_SLAVE_DLY_CTRL_MASK_4D (0xFF << 4)
46324 -#define READ_LATENCY_SHIFT_4D 0
46325 -#define READ_LATENCY_MASK_4D (0xf << 0)
46326 -
46327 -/* DDR_PHY_CTRL_1 - EMIF4D5 */
46328 -#define DLL_HALF_DELAY_SHIFT_4D5 21
46329 -#define DLL_HALF_DELAY_MASK_4D5 (1 << 21)
46330 -#define READ_LATENCY_SHIFT_4D5 0
46331 -#define READ_LATENCY_MASK_4D5 (0x1f << 0)
46332 -
46333 -/* DDR_PHY_CTRL_1_SHDW */
46334 -#define DDR_PHY_CTRL_1_SHDW_SHIFT 5
46335 -#define DDR_PHY_CTRL_1_SHDW_MASK (0x7ffffff << 5)
46336 -#define READ_LATENCY_SHDW_SHIFT 0
46337 -#define READ_LATENCY_SHDW_MASK (0x1f << 0)
46338 +#include <linux/ti_emif.h>
46339
46340 #ifndef __ASSEMBLY__
46341 /*
46342 --- a/drivers/mfd/Kconfig
46343 +++ b/drivers/mfd/Kconfig
46344 @@ -821,6 +821,17 @@ config MFD_TPS65217
46345 This driver can also be built as a module. If so, the module
46346 will be called tps65217.
46347
46348 +config MFD_TPS65218
46349 + bool "TI TPS65218 Power Management chips"
46350 + depends on I2C
46351 + select MFD_CORE
46352 + select REGMAP_I2C
46353 + help
46354 + If you say yes here you get support for the TPS65218 series of
46355 + Power Management chips.
46356 + These include voltage regulators, gpio and other features
46357 + that are often used in portable devices.
46358 +
46359 config MFD_TPS6586X
46360 bool "TI TPS6586x Power Management chips"
46361 depends on I2C=y
46362 --- a/drivers/mfd/Makefile
46363 +++ b/drivers/mfd/Makefile
46364 @@ -62,6 +62,7 @@ obj-$(CONFIG_TPS6105X) += tps6105x.o
46365 obj-$(CONFIG_TPS65010) += tps65010.o
46366 obj-$(CONFIG_TPS6507X) += tps6507x.o
46367 obj-$(CONFIG_MFD_TPS65217) += tps65217.o
46368 +obj-$(CONFIG_MFD_TPS65218) += tps65218.o
46369 obj-$(CONFIG_MFD_TPS65910) += tps65910.o
46370 tps65912-objs := tps65912-core.o tps65912-irq.o
46371 obj-$(CONFIG_MFD_TPS65912) += tps65912.o
46372 --- a/drivers/mfd/omap-usb-host.c
46373 +++ b/drivers/mfd/omap-usb-host.c
46374 @@ -328,13 +328,13 @@ static int usbhs_runtime_resume(struct d
46375 omap_tll_enable(pdata);
46376
46377 if (!IS_ERR(omap->ehci_logic_fck))
46378 - clk_enable(omap->ehci_logic_fck);
46379 + clk_prepare_enable(omap->ehci_logic_fck);
46380
46381 for (i = 0; i < omap->nports; i++) {
46382 switch (pdata->port_mode[i]) {
46383 case OMAP_EHCI_PORT_MODE_HSIC:
46384 if (!IS_ERR(omap->hsic60m_clk[i])) {
46385 - r = clk_enable(omap->hsic60m_clk[i]);
46386 + r = clk_prepare_enable(omap->hsic60m_clk[i]);
46387 if (r) {
46388 dev_err(dev,
46389 "Can't enable port %d hsic60m clk:%d\n",
46390 @@ -343,7 +343,7 @@ static int usbhs_runtime_resume(struct d
46391 }
46392
46393 if (!IS_ERR(omap->hsic480m_clk[i])) {
46394 - r = clk_enable(omap->hsic480m_clk[i]);
46395 + r = clk_prepare_enable(omap->hsic480m_clk[i]);
46396 if (r) {
46397 dev_err(dev,
46398 "Can't enable port %d hsic480m clk:%d\n",
46399 @@ -354,7 +354,7 @@ static int usbhs_runtime_resume(struct d
46400
46401 case OMAP_EHCI_PORT_MODE_TLL:
46402 if (!IS_ERR(omap->utmi_clk[i])) {
46403 - r = clk_enable(omap->utmi_clk[i]);
46404 + r = clk_prepare_enable(omap->utmi_clk[i]);
46405 if (r) {
46406 dev_err(dev,
46407 "Can't enable port %d clk : %d\n",
46408 @@ -382,15 +382,15 @@ static int usbhs_runtime_suspend(struct
46409 switch (pdata->port_mode[i]) {
46410 case OMAP_EHCI_PORT_MODE_HSIC:
46411 if (!IS_ERR(omap->hsic60m_clk[i]))
46412 - clk_disable(omap->hsic60m_clk[i]);
46413 + clk_disable_unprepare(omap->hsic60m_clk[i]);
46414
46415 if (!IS_ERR(omap->hsic480m_clk[i]))
46416 - clk_disable(omap->hsic480m_clk[i]);
46417 + clk_disable_unprepare(omap->hsic480m_clk[i]);
46418 /* Fall through as utmi_clks were used in HSIC mode */
46419
46420 case OMAP_EHCI_PORT_MODE_TLL:
46421 if (!IS_ERR(omap->utmi_clk[i]))
46422 - clk_disable(omap->utmi_clk[i]);
46423 + clk_disable_unprepare(omap->utmi_clk[i]);
46424 break;
46425 default:
46426 break;
46427 @@ -398,7 +398,7 @@ static int usbhs_runtime_suspend(struct
46428 }
46429
46430 if (!IS_ERR(omap->ehci_logic_fck))
46431 - clk_disable(omap->ehci_logic_fck);
46432 + clk_disable_unprepare(omap->ehci_logic_fck);
46433
46434 omap_tll_disable(pdata);
46435
46436 --- a/drivers/mfd/omap-usb-tll.c
46437 +++ b/drivers/mfd/omap-usb-tll.c
46438 @@ -429,7 +429,7 @@ int omap_tll_enable(struct usbhs_omap_pl
46439 if (IS_ERR(tll->ch_clk[i]))
46440 continue;
46441
46442 - r = clk_enable(tll->ch_clk[i]);
46443 + r = clk_prepare_enable(tll->ch_clk[i]);
46444 if (r) {
46445 dev_err(tll_dev,
46446 "Error enabling ch %d clock: %d\n", i, r);
46447 @@ -460,7 +460,7 @@ int omap_tll_disable(struct usbhs_omap_p
46448 for (i = 0; i < tll->nch; i++) {
46449 if (omap_usb_mode_needs_tll(pdata->port_mode[i])) {
46450 if (!IS_ERR(tll->ch_clk[i]))
46451 - clk_disable(tll->ch_clk[i]);
46452 + clk_disable_unprepare(tll->ch_clk[i]);
46453 }
46454 }
46455
46456 --- a/drivers/mfd/ti_am335x_tscadc.c
46457 +++ b/drivers/mfd/ti_am335x_tscadc.c
46458 @@ -56,21 +56,25 @@ EXPORT_SYMBOL_GPL(am335x_tsc_se_update);
46459
46460 void am335x_tsc_se_set(struct ti_tscadc_dev *tsadc, u32 val)
46461 {
46462 - spin_lock(&tsadc->reg_lock);
46463 + unsigned long flags;
46464 +
46465 + spin_lock_irqsave(&tsadc->reg_lock, flags);
46466 tsadc->reg_se_cache = tscadc_readl(tsadc, REG_SE);
46467 tsadc->reg_se_cache |= val;
46468 am335x_tsc_se_update(tsadc);
46469 - spin_unlock(&tsadc->reg_lock);
46470 + spin_unlock_irqrestore(&tsadc->reg_lock, flags);
46471 }
46472 EXPORT_SYMBOL_GPL(am335x_tsc_se_set);
46473
46474 void am335x_tsc_se_clr(struct ti_tscadc_dev *tsadc, u32 val)
46475 {
46476 - spin_lock(&tsadc->reg_lock);
46477 + unsigned long flags;
46478 +
46479 + spin_lock_irqsave(&tsadc->reg_lock, flags);
46480 tsadc->reg_se_cache = tscadc_readl(tsadc, REG_SE);
46481 tsadc->reg_se_cache &= ~val;
46482 am335x_tsc_se_update(tsadc);
46483 - spin_unlock(&tsadc->reg_lock);
46484 + spin_unlock_irqrestore(&tsadc->reg_lock, flags);
46485 }
46486 EXPORT_SYMBOL_GPL(am335x_tsc_se_clr);
46487
46488 --- /dev/null
46489 +++ b/drivers/mfd/tps65218.c
46490 @@ -0,0 +1,275 @@
46491 +/*
46492 + * TPS65218 chip family multi-function driver
46493 + *
46494 + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
46495 + *
46496 + * This program is free software; you can redistribute it and/or
46497 + * modify it under the terms of the GNU General Public License version 2 as
46498 + * published by the Free Software Foundation.
46499 + *
46500 + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
46501 + * kind, whether expressed or implied; without even the implied warranty
46502 + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
46503 + * GNU General Public License version 2 for more details.
46504 + */
46505 +
46506 +#include <linux/kernel.h>
46507 +#include <linux/device.h>
46508 +#include <linux/module.h>
46509 +#include <linux/platform_device.h>
46510 +#include <linux/init.h>
46511 +#include <linux/i2c.h>
46512 +#include <linux/slab.h>
46513 +#include <linux/regmap.h>
46514 +#include <linux/err.h>
46515 +#include <linux/of.h>
46516 +#include <linux/of_device.h>
46517 +#include <linux/irq.h>
46518 +#include <linux/interrupt.h>
46519 +#include <linux/mutex.h>
46520 +
46521 +#include <linux/mfd/core.h>
46522 +#include <linux/mfd/tps65218.h>
46523 +
46524 +#define TPS65218_PASSWORD_REGS_UNLOCK 0x7D
46525 +
46526 +/**
46527 + * tps65218_reg_read: Read a single tps65218 register.
46528 + *
46529 + * @tps: Device to read from.
46530 + * @reg: Register to read.
46531 + * @val: Contians the value
46532 + */
46533 +int tps65218_reg_read(struct tps65218 *tps, unsigned int reg,
46534 + unsigned int *val)
46535 +{
46536 + return regmap_read(tps->regmap, reg, val);
46537 +}
46538 +EXPORT_SYMBOL_GPL(tps65218_reg_read);
46539 +
46540 +/**
46541 + * tps65218_reg_write: Write a single tps65218 register.
46542 + *
46543 + * @tps65218: Device to write to.
46544 + * @reg: Register to write to.
46545 + * @val: Value to write.
46546 + * @level: Password protected level
46547 + */
46548 +int tps65218_reg_write(struct tps65218 *tps, unsigned int reg,
46549 + unsigned int val, unsigned int level)
46550 +{
46551 + int ret;
46552 + unsigned int xor_reg_val;
46553 +
46554 + switch (level) {
46555 + case TPS65218_PROTECT_NONE:
46556 + return regmap_write(tps->regmap, reg, val);
46557 + case TPS65218_PROTECT_L1:
46558 + xor_reg_val = reg ^ TPS65218_PASSWORD_REGS_UNLOCK;
46559 + ret = regmap_write(tps->regmap, TPS65218_REG_PASSWORD,
46560 + xor_reg_val);
46561 + if (ret < 0)
46562 + return ret;
46563 +
46564 + return regmap_write(tps->regmap, reg, val);
46565 + default:
46566 + return -EINVAL;
46567 + }
46568 +}
46569 +EXPORT_SYMBOL_GPL(tps65218_reg_write);
46570 +
46571 +/**
46572 + * tps65218_update_bits: Modify bits w.r.t mask, val and level.
46573 + *
46574 + * @tps65218: Device to write to.
46575 + * @reg: Register to read-write to.
46576 + * @mask: Mask.
46577 + * @val: Value to write.
46578 + * @level: Password protected level
46579 + */
46580 +static int tps65218_update_bits(struct tps65218 *tps, unsigned int reg,
46581 + unsigned int mask, unsigned int val, unsigned int level)
46582 +{
46583 + int ret;
46584 + unsigned int data;
46585 +
46586 + ret = tps65218_reg_read(tps, reg, &data);
46587 + if (ret) {
46588 + dev_err(tps->dev, "Read from reg 0x%x failed\n", reg);
46589 + return ret;
46590 + }
46591 +
46592 + data &= ~mask;
46593 + data |= val & mask;
46594 +
46595 + mutex_lock(&tps->tps_lock);
46596 + ret = tps65218_reg_write(tps, reg, data, level);
46597 + if (ret)
46598 + dev_err(tps->dev, "Write for reg 0x%x failed\n", reg);
46599 + mutex_unlock(&tps->tps_lock);
46600 +
46601 + return ret;
46602 +}
46603 +
46604 +int tps65218_set_bits(struct tps65218 *tps, unsigned int reg,
46605 + unsigned int mask, unsigned int val, unsigned int level)
46606 +{
46607 + return tps65218_update_bits(tps, reg, mask, val, level);
46608 +}
46609 +EXPORT_SYMBOL_GPL(tps65218_set_bits);
46610 +
46611 +int tps65218_clear_bits(struct tps65218 *tps, unsigned int reg,
46612 + unsigned int mask, unsigned int level)
46613 +{
46614 + return tps65218_update_bits(tps, reg, mask, 0, level);
46615 +}
46616 +EXPORT_SYMBOL_GPL(tps65218_clear_bits);
46617 +
46618 +static struct regmap_config tps65218_regmap_config = {
46619 + .reg_bits = 8,
46620 + .val_bits = 8,
46621 +};
46622 +
46623 +static const struct regmap_irq tps65218_irqs[] = {
46624 + /* INT1 IRQs */
46625 + [TPS65218_PRGC_IRQ] = {
46626 + .mask = TPS65218_INT1_PRGC,
46627 + },
46628 + [TPS65218_CC_AQC_IRQ] = {
46629 + .mask = TPS65218_INT1_CC_AQC,
46630 + },
46631 + [TPS65218_HOT_IRQ] = {
46632 + .mask = TPS65218_INT1_HOT,
46633 + },
46634 + [TPS65218_PB_IRQ] = {
46635 + .mask = TPS65218_INT1_PB,
46636 + },
46637 + [TPS65218_AC_IRQ] = {
46638 + .mask = TPS65218_INT1_AC,
46639 + },
46640 + [TPS65218_VPRG_IRQ] = {
46641 + .mask = TPS65218_INT1_VPRG,
46642 + },
46643 + [TPS65218_INVALID1_IRQ] = {
46644 + },
46645 + [TPS65218_INVALID2_IRQ] = {
46646 + },
46647 + /* INT2 IRQs*/
46648 + [TPS65218_LS1_I_IRQ] = {
46649 + .mask = TPS65218_INT2_LS1_I,
46650 + .reg_offset = 1,
46651 + },
46652 + [TPS65218_LS2_I_IRQ] = {
46653 + .mask = TPS65218_INT2_LS2_I,
46654 + .reg_offset = 1,
46655 + },
46656 + [TPS65218_LS3_I_IRQ] = {
46657 + .mask = TPS65218_INT2_LS3_I,
46658 + .reg_offset = 1,
46659 + },
46660 + [TPS65218_LS1_F_IRQ] = {
46661 + .mask = TPS65218_INT2_LS1_F,
46662 + .reg_offset = 1,
46663 + },
46664 + [TPS65218_LS2_F_IRQ] = {
46665 + .mask = TPS65218_INT2_LS2_F,
46666 + .reg_offset = 1,
46667 + },
46668 + [TPS65218_LS3_F_IRQ] = {
46669 + .mask = TPS65218_INT2_LS3_F,
46670 + .reg_offset = 1,
46671 + },
46672 + [TPS65218_INVALID3_IRQ] = {
46673 + },
46674 + [TPS65218_INVALID4_IRQ] = {
46675 + },
46676 +};
46677 +
46678 +static struct regmap_irq_chip tps65218_irq_chip = {
46679 + .name = "tps65218",
46680 + .irqs = tps65218_irqs,
46681 + .num_irqs = ARRAY_SIZE(tps65218_irqs),
46682 +
46683 + .num_regs = 2,
46684 + .mask_base = TPS65218_REG_INT_MASK1,
46685 +};
46686 +
46687 +static const struct of_device_id of_tps65218_match_table[] = {
46688 + { .compatible = "ti,tps65218", },
46689 + { /* end */ }
46690 +};
46691 +
46692 +static int tps65218_probe(struct i2c_client *client,
46693 + const struct i2c_device_id *ids)
46694 +{
46695 + struct tps65218 *tps;
46696 + const struct of_device_id *match;
46697 + int ret;
46698 +
46699 + match = of_match_device(of_tps65218_match_table, &client->dev);
46700 + if (!match) {
46701 + dev_err(&client->dev,
46702 + "Failed to find matching dt id\n");
46703 + return -EINVAL;
46704 + }
46705 +
46706 + tps = devm_kzalloc(&client->dev, sizeof(*tps), GFP_KERNEL);
46707 + if (!tps)
46708 + return -ENOMEM;
46709 +
46710 + i2c_set_clientdata(client, tps);
46711 + tps->dev = &client->dev;
46712 +
46713 + tps->regmap = devm_regmap_init_i2c(client, &tps65218_regmap_config);
46714 + if (IS_ERR(tps->regmap)) {
46715 + ret = PTR_ERR(tps->regmap);
46716 + dev_err(tps->dev, "Failed to allocate register map: %d\n",
46717 + ret);
46718 + return ret;
46719 + }
46720 +
46721 + mutex_init(&tps->tps_lock);
46722 +
46723 + ret = regmap_add_irq_chip(tps->regmap, tps->irq,
46724 + IRQF_ONESHOT, 0, &tps65218_irq_chip,
46725 + &tps->irq_data);
46726 + if (ret < 0)
46727 + return ret;
46728 +
46729 + ret = of_platform_populate(client->dev.of_node, NULL, NULL,
46730 + &client->dev);
46731 + if (ret < 0)
46732 + goto err_irq;
46733 +
46734 + return 0;
46735 +
46736 +err_irq:
46737 + regmap_del_irq_chip(tps->irq, tps->irq_data);
46738 +
46739 + return ret;
46740 +}
46741 +
46742 +static int tps65218_remove(struct i2c_client *client)
46743 +{
46744 + struct tps65218 *tps = i2c_get_clientdata(client);
46745 +
46746 + regmap_del_irq_chip(tps->irq, tps->irq_data);
46747 +
46748 + return 0;
46749 +}
46750 +
46751 +static struct i2c_driver tps65218_driver = {
46752 + .driver = {
46753 + .name = "tps65218",
46754 + .owner = THIS_MODULE,
46755 + .of_match_table = of_tps65218_match_table,
46756 + },
46757 + .probe = tps65218_probe,
46758 + .remove = tps65218_remove,
46759 +};
46760 +
46761 +module_i2c_driver(tps65218_driver);
46762 +
46763 +MODULE_AUTHOR("J Keerthy <j-keerthy@ti.com>");
46764 +MODULE_DESCRIPTION("TPS65218 chip family multi-function driver");
46765 +MODULE_LICENSE("GPL v2");
46766 --- a/drivers/mfd/twl6040.c
46767 +++ b/drivers/mfd/twl6040.c
46768 @@ -238,6 +238,8 @@ int twl6040_power(struct twl6040 *twl604
46769 if (twl6040->power_count++)
46770 goto out;
46771
46772 + clk_prepare_enable(twl6040->clk32k);
46773 +
46774 if (gpio_is_valid(twl6040->audpwron)) {
46775 /* use automatic power-up sequence */
46776 ret = twl6040_power_up_automatic(twl6040);
46777 @@ -281,6 +283,8 @@ int twl6040_power(struct twl6040 *twl604
46778 }
46779 twl6040->sysclk = 0;
46780 twl6040->mclk = 0;
46781 +
46782 + clk_disable_unprepare(twl6040->clk32k);
46783 }
46784
46785 out:
46786 @@ -559,6 +563,12 @@ static int twl6040_probe(struct i2c_clie
46787
46788 i2c_set_clientdata(client, twl6040);
46789
46790 + twl6040->clk32k = devm_clk_get(&client->dev, "clk32k");
46791 + if (IS_ERR(twl6040->clk32k)) {
46792 + dev_info(&client->dev, "clk32k is not handled\n");
46793 + twl6040->clk32k = NULL;
46794 + }
46795 +
46796 twl6040->supplies[0].supply = "vio";
46797 twl6040->supplies[1].supply = "v2v1";
46798 ret = devm_regulator_bulk_get(&client->dev, TWL6040_NUM_SUPPLIES,
46799 --- /dev/null
46800 +++ b/drivers/misc/crossbar.c
46801 @@ -0,0 +1,258 @@
46802 +/*
46803 + * IRQ/DMA CROSSBAR DRIVER
46804 + *
46805 + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
46806 + * Sricharan R <r.sricharan@ti.com>
46807 + *
46808 + * This program is free software; you can redistribute it and/or modify
46809 + * it under the terms of the GNU General Public License as published by
46810 + * the Free Software Foundation; either version 2 of the License, or
46811 + * (at your option) any later version.
46812 + *
46813 + * This program is distributed in the hope that it will be useful,
46814 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
46815 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
46816 + * GNU General Public License for more details.
46817 + *
46818 + * You should have received a copy of the GNU General Public License
46819 + * along with this program; if not, write to the Free Software
46820 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
46821 + * USA
46822 + */
46823 +#include <linux/crossbar.h>
46824 +#include <linux/regmap.h>
46825 +
46826 +static LIST_HEAD(cb_devlist);
46827 +
46828 +static struct regmap_config cb_regmap_config = {
46829 + .reg_bits = 32,
46830 +};
46831 +
46832 +static unsigned cb_entry_read(struct cb_line *tmp, const void *cbs)
46833 +{
46834 + unsigned index = 0;
46835 +
46836 + tmp->cb_name = cbs;
46837 + index = strlen(tmp->cb_name) + 1;
46838 +
46839 + tmp->dev_name = cbs + index;
46840 + index += strlen(tmp->dev_name) + 1;
46841 +
46842 + tmp->int_no = be32_to_cpup(cbs + index);
46843 + index += sizeof(tmp->int_no);
46844 +
46845 + tmp->cb_no = be32_to_cpup(cbs + index);
46846 + index += sizeof(tmp->cb_no);
46847 +
46848 + tmp->offset = be32_to_cpup(cbs + index);
46849 + index += sizeof(tmp->offset);
46850 +
46851 + return index;
46852 +}
46853 +
46854 +int crossbar_unmap(struct device_node *cbdev_node, unsigned index)
46855 +{
46856 + const void *cbs;
46857 + unsigned size = 0, i = 0;
46858 + struct cb_line tmp;
46859 + struct cb_device *cbdev;
46860 + struct cb_entry *cbentry, *p;
46861 +
46862 + cbs = of_get_property(cbdev_node, "crossbar-lines", &size);
46863 + if (!cbs)
46864 + return -ENOENT;
46865 +
46866 + size = 0;
46867 +
46868 + while (i++ < index)
46869 + size += cb_entry_read(&tmp, cbs + size);
46870 +
46871 + cb_entry_read(&tmp, cbs + size);
46872 +
46873 + list_for_each_entry(cbdev, &cb_devlist, node) {
46874 + if (strcmp(cbdev->name, tmp.cb_name))
46875 + continue;
46876 +
46877 + mutex_lock(&cbdev->cb_lock);
46878 + list_for_each_entry_safe(cbentry, p, &cbdev->cb_entries,
46879 + cb_list) {
46880 + if ((cbentry->line.cb_no == tmp.cb_no) &&
46881 + (cbentry->line.int_no == tmp.int_no)) {
46882 + list_del(&cbentry->cb_list);
46883 + mutex_unlock(&cbdev->cb_lock);
46884 + dev_warn(cbdev->dev,
46885 + "unmapped int_no %x mapped to cb %x\n",
46886 + tmp.int_no, tmp.cb_no);
46887 + return 0;
46888 + }
46889 + }
46890 + mutex_unlock(&cbdev->cb_lock);
46891 + break;
46892 + }
46893 +
46894 + dev_warn(cbdev->dev, "%s cb entry %d not found\n",
46895 + __func__, tmp.cb_no);
46896 + return -ENOENT;
46897 +}
46898 +EXPORT_SYMBOL(crossbar_unmap);
46899 +
46900 +const int cb_map(struct cb_line cbl)
46901 +{
46902 + struct cb_device *cbdev;
46903 + struct cb_entry *cbentry, *tmp;
46904 + unsigned val;
46905 +
46906 + /* Get corresponding device pointer */
46907 + list_for_each_entry(cbdev, &cb_devlist, node) {
46908 + if (strcmp(cbdev->name, cbl.cb_name))
46909 + continue;
46910 +
46911 + mutex_lock(&cbdev->cb_lock);
46912 +
46913 + /* Check for invalid and duplicate mapping */
46914 + list_for_each_entry_safe(cbentry, tmp, &cbdev->cb_entries,
46915 + cb_list) {
46916 + if ((cbentry->line.cb_no == cbl.cb_no) &&
46917 + (cbentry->line.int_no != cbl.int_no)) {
46918 + dev_warn(cbdev->dev,
46919 + "%s irq already mapped to irq no %d",
46920 + cbentry->line.dev_name,
46921 + cbentry->line.int_no);
46922 + mutex_unlock(&cbdev->cb_lock);
46923 + return -EINVAL;
46924 + }
46925 + if ((cbentry->line.cb_no == cbl.cb_no) &&
46926 + (cbentry->line.int_no == cbl.int_no)) {
46927 + mutex_unlock(&cbdev->cb_lock);
46928 + return 0;
46929 + }
46930 + if ((cbentry->line.int_no == cbl.int_no) &&
46931 + (cbentry->line.cb_no != cbl.cb_no)) {
46932 + dev_warn(cbdev->dev,
46933 + "%s irq replaced by %s irq\n",
46934 + cbentry->line.dev_name,
46935 + cbl.dev_name);
46936 + list_del(&(cbentry->cb_list));
46937 + break;
46938 + }
46939 + }
46940 +
46941 + cbentry = devm_kzalloc(cbdev->dev, sizeof(struct cb_entry),
46942 + GFP_KERNEL);
46943 + cbentry->line = cbl;
46944 + list_add_tail(&(cbentry->cb_list), &cbdev->cb_entries);
46945 +
46946 + regmap_read(cbdev->cb_regmap, cbl.offset, &val);
46947 +
46948 + /* Print the replaced entry and map the new one */
46949 + dev_warn(cbdev->dev,
46950 + "replacing irq %d mapped to cb input %d with cb input %d\n",
46951 + cbl.int_no, val, cbl.cb_no);
46952 +
46953 + regmap_write(cbdev->cb_regmap, cbl.offset, cbl.cb_no);
46954 + mutex_unlock(&cbdev->cb_lock);
46955 + return 0;
46956 + }
46957 +
46958 + dev_warn(cbdev->dev, "crossbar device %s not found", cbl.cb_name);
46959 + return -ENODEV;
46960 +}
46961 +
46962 +int crossbar_map(struct device_node *cbdev_node)
46963 +{
46964 + const void *cbs;
46965 + unsigned size = 0, index = 0;
46966 + int err;
46967 +
46968 + cbs = of_get_property(cbdev_node, "crossbar-lines", &size);
46969 + if (!cbs)
46970 + return -ENOENT;
46971 +
46972 + while (index < size) {
46973 + struct cb_line tmp;
46974 +
46975 + index += cb_entry_read(&tmp, cbs + index);
46976 +
46977 + err = cb_map(tmp);
46978 + if (IS_ERR_VALUE(err))
46979 + return err;
46980 + }
46981 +
46982 + return 0;
46983 +}
46984 +EXPORT_SYMBOL(crossbar_map);
46985 +
46986 +static int crossbar_probe(struct platform_device *pdev)
46987 +{
46988 + struct cb_device *cbdev;
46989 + unsigned width;
46990 + struct device_node *cbdev_node = pdev->dev.of_node;
46991 + int err;
46992 + struct resource *res;
46993 +
46994 + cbdev = devm_kzalloc(&pdev->dev, sizeof(struct cb_device), GFP_KERNEL);
46995 + if (!cbdev)
46996 + return -ENOMEM;
46997 +
46998 + /* Get the device resources */
46999 + of_property_read_string(cbdev_node, "crossbar-name", &(cbdev->name));
47000 +
47001 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
47002 + if (res == NULL)
47003 + return -ENOENT;
47004 +
47005 + cbdev->base = devm_ioremap_resource(&pdev->dev, res);
47006 + if (!cbdev->base)
47007 + return -ENOMEM;
47008 +
47009 + cbdev->dev = &pdev->dev;
47010 +
47011 + of_property_read_u32(cbdev_node, "reg-width", &width);
47012 +
47013 + cb_regmap_config.val_bits = width;
47014 + cb_regmap_config.reg_stride = width >> 3;
47015 +
47016 + cbdev->cb_regmap = devm_regmap_init_mmio(cbdev->dev, cbdev->base,
47017 + &cb_regmap_config);
47018 +
47019 + if (IS_ERR(cbdev->cb_regmap)) {
47020 + dev_err(&pdev->dev, "regmap init failed\n");
47021 + err = PTR_ERR(cbdev->cb_regmap);
47022 + return err;
47023 + }
47024 +
47025 + platform_set_drvdata(pdev, cbdev);
47026 + list_add_tail(&cbdev->node, &cb_devlist);
47027 +
47028 + /* INIT LIST HEAD */
47029 + INIT_LIST_HEAD(&cbdev->cb_entries);
47030 +
47031 + mutex_init(&cbdev->cb_lock);
47032 +
47033 + /* map the cross bar entries passed as default from DT */
47034 + err = crossbar_map(cbdev_node);
47035 +
47036 + return err;
47037 +}
47038 +
47039 +#ifdef CONFIG_OF
47040 +static const struct of_device_id crossbar_match[] = {
47041 + {.compatible = "crossbar", },
47042 + {},
47043 +};
47044 +#endif
47045 +
47046 +static struct platform_driver crossbar_driver = {
47047 + .probe = crossbar_probe,
47048 + .driver = {
47049 + .name = "crossbar",
47050 + .owner = THIS_MODULE,
47051 + .of_match_table = crossbar_match,
47052 + },
47053 +};
47054 +
47055 +static int __init crossbar_init(void)
47056 +{
47057 + return platform_driver_register(&crossbar_driver);
47058 +}
47059 +postcore_initcall(crossbar_init);
47060 --- a/drivers/misc/Kconfig
47061 +++ b/drivers/misc/Kconfig
47062 @@ -528,6 +528,14 @@ config SRAM
47063 the genalloc API. It is supposed to be used for small on-chip SRAM
47064 areas found on many SoCs.
47065
47066 +config CROSSBAR
47067 + bool "on-chip crossbar driver"
47068 + select REGMAP_MMIO
47069 + help
47070 + This driver is for IRQ/DMA crossbar devices which is responsible for
47071 + muxing the irq/dma requests from external peripherals to the corresponding
47072 + controller's inputs.
47073 +
47074 source "drivers/misc/c2port/Kconfig"
47075 source "drivers/misc/eeprom/Kconfig"
47076 source "drivers/misc/cb710/Kconfig"
47077 --- a/drivers/misc/Makefile
47078 +++ b/drivers/misc/Makefile
47079 @@ -53,3 +53,4 @@ obj-$(CONFIG_INTEL_MEI) += mei/
47080 obj-$(CONFIG_VMWARE_VMCI) += vmw_vmci/
47081 obj-$(CONFIG_LATTICE_ECP3_CONFIG) += lattice-ecp3-config.o
47082 obj-$(CONFIG_SRAM) += sram.o
47083 +obj-$(CONFIG_CROSSBAR) += crossbar.o
47084 --- a/drivers/mmc/core/mmc.c
47085 +++ b/drivers/mmc/core/mmc.c
47086 @@ -1512,14 +1512,6 @@ static int mmc_suspend(struct mmc_host *
47087 }
47088
47089 /*
47090 - * Shutdown callback
47091 - */
47092 -static int mmc_shutdown(struct mmc_host *host)
47093 -{
47094 - return _mmc_suspend(host, false);
47095 -}
47096 -
47097 -/*
47098 * Resume callback from host.
47099 *
47100 * This function tries to determine if the same card is still present
47101 @@ -1608,7 +1600,6 @@ static const struct mmc_bus_ops mmc_ops
47102 .resume = NULL,
47103 .power_restore = mmc_power_restore,
47104 .alive = mmc_alive,
47105 - .shutdown = mmc_shutdown,
47106 };
47107
47108 static const struct mmc_bus_ops mmc_ops_unsafe = {
47109 @@ -1620,7 +1611,6 @@ static const struct mmc_bus_ops mmc_ops_
47110 .runtime_resume = mmc_runtime_resume,
47111 .power_restore = mmc_power_restore,
47112 .alive = mmc_alive,
47113 - .shutdown = mmc_shutdown,
47114 };
47115
47116 static void mmc_attach_bus_ops(struct mmc_host *host)
47117 --- a/drivers/mmc/core/sd.c
47118 +++ b/drivers/mmc/core/sd.c
47119 @@ -1173,7 +1173,6 @@ static const struct mmc_bus_ops mmc_sd_o
47120 .resume = NULL,
47121 .power_restore = mmc_sd_power_restore,
47122 .alive = mmc_sd_alive,
47123 - .shutdown = mmc_sd_suspend,
47124 };
47125
47126 static const struct mmc_bus_ops mmc_sd_ops_unsafe = {
47127 @@ -1185,7 +1184,6 @@ static const struct mmc_bus_ops mmc_sd_o
47128 .resume = mmc_sd_resume,
47129 .power_restore = mmc_sd_power_restore,
47130 .alive = mmc_sd_alive,
47131 - .shutdown = mmc_sd_suspend,
47132 };
47133
47134 static void mmc_sd_attach_bus_ops(struct mmc_host *host)
47135 --- a/drivers/mmc/host/omap_hsmmc.c
47136 +++ b/drivers/mmc/host/omap_hsmmc.c
47137 @@ -45,6 +45,7 @@
47138 /* OMAP HSMMC Host Controller Registers */
47139 #define OMAP_HSMMC_SYSSTATUS 0x0014
47140 #define OMAP_HSMMC_CON 0x002C
47141 +#define OMAP_HSMMC_SDMASA 0x0100
47142 #define OMAP_HSMMC_BLK 0x0104
47143 #define OMAP_HSMMC_ARG 0x0108
47144 #define OMAP_HSMMC_CMD 0x010C
47145 @@ -58,7 +59,9 @@
47146 #define OMAP_HSMMC_STAT 0x0130
47147 #define OMAP_HSMMC_IE 0x0134
47148 #define OMAP_HSMMC_ISE 0x0138
47149 +#define OMAP_HSMMC_AC12 0x013C
47150 #define OMAP_HSMMC_CAPA 0x0140
47151 +#define OMAP_HSMMC_REV 0x01FC
47152
47153 #define VS18 (1 << 26)
47154 #define VS30 (1 << 25)
47155 @@ -75,11 +78,14 @@
47156 #define ICE 0x1
47157 #define ICS 0x2
47158 #define CEN (1 << 2)
47159 +#define CLKD_MAX 0x3FF /* max clock divisor: 1023 */
47160 #define CLKD_MASK 0x0000FFC0
47161 #define CLKD_SHIFT 6
47162 #define DTO_MASK 0x000F0000
47163 #define DTO_SHIFT 16
47164 #define INIT_STREAM (1 << 1)
47165 +#define ACEN_ACMD12 (1 << 2)
47166 +#define ACEN_ACMD23 (2 << 2)
47167 #define DP_SELECT (1 << 21)
47168 #define DDIR (1 << 4)
47169 #define DMAE 0x1
47170 @@ -111,6 +117,7 @@
47171 #define DTO_EN (1 << 20)
47172 #define DCRC_EN (1 << 21)
47173 #define DEB_EN (1 << 22)
47174 +#define ACE_EN (1 << 24)
47175 #define CERR_EN (1 << 28)
47176 #define BADA_EN (1 << 29)
47177
47178 @@ -118,12 +125,27 @@
47179 DTO_EN | CIE_EN | CEB_EN | CCRC_EN | CTO_EN | \
47180 BRR_EN | BWR_EN | TC_EN | CC_EN)
47181
47182 +#define CNI (1 << 7)
47183 +#define ACIE (1 << 4)
47184 +#define ACEB (1 << 3)
47185 +#define ACCE (1 << 2)
47186 +#define ACTO (1 << 1)
47187 +#define ACNE (1 << 0)
47188 +
47189 #define MMC_AUTOSUSPEND_DELAY 100
47190 #define MMC_TIMEOUT_MS 20
47191 +#define MMC_TIMEOUT_US 20000
47192 #define OMAP_MMC_MIN_CLOCK 400000
47193 #define OMAP_MMC_MAX_CLOCK 52000000
47194 #define DRIVER_NAME "omap_hsmmc"
47195
47196 +#define AUTO_CMD12 (1 << 0) /* Auto CMD12 support */
47197 +#define AUTO_CMD23 (1 << 1) /* Auto CMD23 support */
47198 +
47199 +#define OMAP_HSMMC_REV_SHIFT 24
47200 +/* HSMMC controller revision on OMAP5, DRA7 */
47201 +#define OMAP_HSMMC_REV_33 0x33
47202 +
47203 /*
47204 * One controller can have multiple slots, like on some omap boards using
47205 * omap.c controller driver. Luckily this is not currently done on any known
47206 @@ -171,6 +193,10 @@ struct omap_hsmmc_host {
47207 unsigned char bus_mode;
47208 unsigned char power_mode;
47209 int suspended;
47210 + u32 con;
47211 + u32 hctl;
47212 + u32 sysctl;
47213 + u32 capa;
47214 int irq;
47215 int use_dma, dma_ch;
47216 struct dma_chan *tx_chan;
47217 @@ -182,11 +208,19 @@ struct omap_hsmmc_host {
47218 int reqs_blocked;
47219 int use_reg;
47220 int req_in_progress;
47221 + unsigned long clk_rate;
47222 + unsigned int flags;
47223 struct omap_hsmmc_next next_data;
47224 -
47225 struct omap_mmc_platform_data *pdata;
47226 };
47227
47228 +static int
47229 +omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req);
47230 +
47231 +static void set_data_timeout(struct omap_hsmmc_host *host,
47232 + unsigned int timeout_ns,
47233 + unsigned int timeout_clks);
47234 +
47235 static int omap_hsmmc_card_detect(struct device *dev, int slot)
47236 {
47237 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
47238 @@ -407,6 +441,9 @@ static int omap_hsmmc_gpio_init(struct o
47239 ret = gpio_direction_input(pdata->slots[0].switch_pin);
47240 if (ret)
47241 goto err_free_sp;
47242 + ret = gpio_set_debounce(pdata->slots[0].switch_pin, 50000);
47243 + if (ret)
47244 + goto err_free_sp;
47245 } else
47246 pdata->slots[0].switch_pin = -EINVAL;
47247
47248 @@ -493,8 +530,8 @@ static u16 calc_divisor(struct omap_hsmm
47249
47250 if (ios->clock) {
47251 dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock);
47252 - if (dsor > 250)
47253 - dsor = 250;
47254 + if (dsor > CLKD_MAX)
47255 + dsor = CLKD_MAX;
47256 }
47257
47258 return dsor;
47259 @@ -597,25 +634,20 @@ static void omap_hsmmc_set_bus_mode(stru
47260 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
47261 {
47262 struct mmc_ios *ios = &host->mmc->ios;
47263 - struct omap_mmc_platform_data *pdata = host->pdata;
47264 - int context_loss = 0;
47265 u32 hctl, capa;
47266 unsigned long timeout;
47267
47268 - if (pdata->get_context_loss_count) {
47269 - context_loss = pdata->get_context_loss_count(host->dev);
47270 - if (context_loss < 0)
47271 - return 1;
47272 - }
47273 -
47274 - dev_dbg(mmc_dev(host->mmc), "context was %slost\n",
47275 - context_loss == host->context_loss ? "not " : "");
47276 - if (host->context_loss == context_loss)
47277 - return 1;
47278 -
47279 if (!OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE)
47280 return 1;
47281
47282 + if (host->con == OMAP_HSMMC_READ(host->base, CON) &&
47283 + host->hctl == OMAP_HSMMC_READ(host->base, HCTL) &&
47284 + host->sysctl == OMAP_HSMMC_READ(host->base, SYSCTL) &&
47285 + host->capa == OMAP_HSMMC_READ(host->base, CAPA))
47286 + return 0;
47287 +
47288 + host->context_loss++;
47289 +
47290 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
47291 if (host->power_mode != MMC_POWER_OFF &&
47292 (1 << ios->vdd) <= MMC_VDD_23_24)
47293 @@ -655,9 +687,8 @@ static int omap_hsmmc_context_restore(st
47294 omap_hsmmc_set_bus_mode(host);
47295
47296 out:
47297 - host->context_loss = context_loss;
47298 -
47299 - dev_dbg(mmc_dev(host->mmc), "context is restored\n");
47300 + dev_dbg(mmc_dev(host->mmc), "context is restored: restore count %d\n",
47301 + host->context_loss);
47302 return 0;
47303 }
47304
47305 @@ -666,15 +697,10 @@ out:
47306 */
47307 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
47308 {
47309 - struct omap_mmc_platform_data *pdata = host->pdata;
47310 - int context_loss;
47311 -
47312 - if (pdata->get_context_loss_count) {
47313 - context_loss = pdata->get_context_loss_count(host->dev);
47314 - if (context_loss < 0)
47315 - return;
47316 - host->context_loss = context_loss;
47317 - }
47318 + host->con = OMAP_HSMMC_READ(host->base, CON);
47319 + host->hctl = OMAP_HSMMC_READ(host->base, HCTL);
47320 + host->sysctl = OMAP_HSMMC_READ(host->base, SYSCTL);
47321 + host->capa = OMAP_HSMMC_READ(host->base, CAPA);
47322 }
47323
47324 #else
47325 @@ -762,7 +788,7 @@ static DEVICE_ATTR(slot_name, S_IRUGO, o
47326 */
47327 static void
47328 omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
47329 - struct mmc_data *data)
47330 + struct mmc_data *data, bool autocmd12)
47331 {
47332 int cmdreg = 0, resptype = 0, cmdtype = 0;
47333
47334 @@ -792,6 +818,13 @@ omap_hsmmc_start_command(struct omap_hsm
47335 cmdtype = 0x3;
47336
47337 cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
47338 + if ((host->flags & AUTO_CMD23) && mmc_op_multi(cmd->opcode) &&
47339 + host->mrq->sbc) {
47340 + cmdreg |= ACEN_ACMD23;
47341 + OMAP_HSMMC_WRITE(host->base, SDMASA, host->mrq->sbc->arg);
47342 + } else if ((host->flags & AUTO_CMD12) && mmc_op_multi(cmd->opcode) &&
47343 + autocmd12)
47344 + cmdreg |= ACEN_ACMD12;
47345
47346 if (data) {
47347 cmdreg |= DP_SELECT | MSBS | BCE;
47348 @@ -870,11 +903,38 @@ omap_hsmmc_xfer_done(struct omap_hsmmc_h
47349 else
47350 data->bytes_xfered = 0;
47351
47352 - if (!data->stop) {
47353 + if (data->stop && (data->error || (!(host->flags & AUTO_CMD12) &&
47354 + !host->mrq->sbc))) {
47355 + /*
47356 + * If there is any error or open-end read/write with autocmd12
47357 + * disabled
47358 + */
47359 + omap_hsmmc_start_command(host, data->stop, NULL, 0);
47360 + } else {
47361 + /* status update for autocmd12 of open-end read/write */
47362 + if (data->stop && !host->mrq->sbc)
47363 + data->stop->resp[0] = OMAP_HSMMC_READ(host->base,
47364 + RSP76);
47365 omap_hsmmc_request_done(host, data->mrq);
47366 - return;
47367 }
47368 - omap_hsmmc_start_command(host, data->stop, NULL);
47369 +
47370 + return;
47371 +}
47372 +
47373 +static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host)
47374 +{
47375 + struct mmc_request *req;
47376 + struct dma_chan *chan;
47377 + req = host->mrq;
47378 +
47379 + if (!req->data)
47380 + return;
47381 + OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
47382 + | (req->data->blocks << 16));
47383 + set_data_timeout(host, req->data->timeout_ns,
47384 + req->data->timeout_clks);
47385 + chan = omap_hsmmc_get_dma_chan(host, req->data);
47386 + dma_async_issue_pending(chan);
47387 }
47388
47389 /*
47390 @@ -883,6 +943,18 @@ omap_hsmmc_xfer_done(struct omap_hsmmc_h
47391 static void
47392 omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
47393 {
47394 + struct mmc_request *req;
47395 + req = host->mrq;
47396 +
47397 + if (host->mrq->sbc && (host->cmd == host->mrq->sbc) &&
47398 + !host->mrq->sbc->error && !(host->flags & AUTO_CMD23)) {
47399 + host->cmd = NULL;
47400 + omap_hsmmc_start_dma_transfer(host);
47401 + omap_hsmmc_start_command(host, host->mrq->cmd,
47402 + host->mrq->data, 0);
47403 + return;
47404 + }
47405 +
47406 host->cmd = NULL;
47407
47408 if (cmd->flags & MMC_RSP_PRESENT) {
47409 @@ -975,8 +1047,7 @@ static inline void omap_hsmmc_reset_cont
47410 unsigned long bit)
47411 {
47412 unsigned long i = 0;
47413 - unsigned long limit = (loops_per_jiffy *
47414 - msecs_to_jiffies(MMC_TIMEOUT_MS));
47415 + unsigned long limit = MMC_TIMEOUT_US;
47416
47417 OMAP_HSMMC_WRITE(host->base, SYSCTL,
47418 OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
47419 @@ -988,13 +1059,14 @@ static inline void omap_hsmmc_reset_cont
47420 if (mmc_slot(host).features & HSMMC_HAS_UPDATED_RESET) {
47421 while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit))
47422 && (i++ < limit))
47423 - cpu_relax();
47424 + udelay(1);
47425 }
47426 +
47427 i = 0;
47428
47429 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
47430 (i++ < limit))
47431 - cpu_relax();
47432 + udelay(1);
47433
47434 if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
47435 dev_err(mmc_dev(host->mmc),
47436 @@ -1022,6 +1094,7 @@ static void omap_hsmmc_do_irq(struct oma
47437 {
47438 struct mmc_data *data;
47439 int end_cmd = 0, end_trans = 0;
47440 + int error = 0;
47441
47442 data = host->data;
47443 dev_vdbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
47444 @@ -1036,6 +1109,29 @@ static void omap_hsmmc_do_irq(struct oma
47445 else if (status & (CCRC_EN | DCRC_EN))
47446 hsmmc_command_incomplete(host, -EILSEQ, end_cmd);
47447
47448 + if (status & ACE_EN) {
47449 + u32 ac12;
47450 + ac12 = OMAP_HSMMC_READ(host->base, AC12);
47451 + if (!(ac12 & ACNE) && host->mrq->sbc) {
47452 + end_cmd = 1;
47453 + if (ac12 & ACTO)
47454 + error = -ETIMEDOUT;
47455 + else if (ac12 & (ACCE | ACEB | ACIE))
47456 + error = -EILSEQ;
47457 + host->mrq->sbc->error = error;
47458 + hsmmc_command_incomplete(host, error, end_cmd);
47459 + }
47460 + if (!(ac12 & ACNE) && !host->mrq->sbc &&
47461 + host->mrq->data) {
47462 + end_trans = 1;
47463 + if (ac12 & ACTO)
47464 + host->mrq->data->error = -ETIMEDOUT;
47465 + else if (ac12 & (ACCE | ACEB | ACIE))
47466 + host->mrq->data->error = -EILSEQ;
47467 + omap_hsmmc_reset_controller_fsm(host, SRC);
47468 + }
47469 + dev_dbg(mmc_dev(host->mmc), "AC12 err: 0x%x\n", ac12);
47470 + }
47471 if (host->data || host->response_busy) {
47472 end_trans = !end_cmd;
47473 host->response_busy = 0;
47474 @@ -1272,7 +1368,7 @@ static int omap_hsmmc_pre_dma_transfer(s
47475 /*
47476 * Routine to configure and start DMA for the MMC card
47477 */
47478 -static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host,
47479 +static int omap_hsmmc_setup_dma_transfer(struct omap_hsmmc_host *host,
47480 struct mmc_request *req)
47481 {
47482 struct dma_slave_config cfg;
47483 @@ -1331,8 +1427,6 @@ static int omap_hsmmc_start_dma_transfer
47484
47485 host->dma_ch = 1;
47486
47487 - dma_async_issue_pending(chan);
47488 -
47489 return 0;
47490 }
47491
47492 @@ -1348,7 +1442,7 @@ static void set_data_timeout(struct omap
47493 if (clkd == 0)
47494 clkd = 1;
47495
47496 - cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
47497 + cycle_ns = 1000000000 / (host->clk_rate / clkd);
47498 timeout = timeout_ns / cycle_ns;
47499 timeout += timeout_clks;
47500 if (timeout) {
47501 @@ -1393,12 +1487,8 @@ omap_hsmmc_prepare_data(struct omap_hsmm
47502 return 0;
47503 }
47504
47505 - OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
47506 - | (req->data->blocks << 16));
47507 - set_data_timeout(host, req->data->timeout_ns, req->data->timeout_clks);
47508 -
47509 if (host->use_dma) {
47510 - ret = omap_hsmmc_start_dma_transfer(host, req);
47511 + ret = omap_hsmmc_setup_dma_transfer(host, req);
47512 if (ret != 0) {
47513 dev_err(mmc_dev(host->mmc), "MMC start dma failure\n");
47514 return ret;
47515 @@ -1472,6 +1562,7 @@ static void omap_hsmmc_request(struct mm
47516 host->reqs_blocked = 0;
47517 WARN_ON(host->mrq != NULL);
47518 host->mrq = req;
47519 + host->clk_rate = clk_get_rate(host->fclk);
47520 err = omap_hsmmc_prepare_data(host, req);
47521 if (err) {
47522 req->cmd->error = err;
47523 @@ -1481,8 +1572,12 @@ static void omap_hsmmc_request(struct mm
47524 mmc_request_done(mmc, req);
47525 return;
47526 }
47527 -
47528 - omap_hsmmc_start_command(host, req->cmd, req->data);
47529 + if (req->sbc && !(host->flags & AUTO_CMD23)) {
47530 + omap_hsmmc_start_command(host, req->sbc, NULL, 0);
47531 + return;
47532 + }
47533 + omap_hsmmc_start_dma_transfer(host);
47534 + omap_hsmmc_start_command(host, req->cmd, req->data, 1);
47535 }
47536
47537 /* Routine to configure clock values. Exposed API to core */
47538 @@ -1635,13 +1730,9 @@ static int omap_hsmmc_regs_show(struct s
47539 {
47540 struct mmc_host *mmc = s->private;
47541 struct omap_hsmmc_host *host = mmc_priv(mmc);
47542 - int context_loss = 0;
47543
47544 - if (host->pdata->get_context_loss_count)
47545 - context_loss = host->pdata->get_context_loss_count(host->dev);
47546 -
47547 - seq_printf(s, "mmc%d:\n ctx_loss:\t%d:%d\n\nregs:\n",
47548 - mmc->index, host->context_loss, context_loss);
47549 + seq_printf(s, "mmc%d:\n ctx_loss:\t%d\n\nregs:\n",
47550 + mmc->index, host->context_loss);
47551
47552 if (host->suspended) {
47553 seq_printf(s, "host suspended, can't read registers\n");
47554 @@ -1778,6 +1869,7 @@ static int omap_hsmmc_probe(struct platf
47555 dma_cap_mask_t mask;
47556 unsigned tx_req, rx_req;
47557 struct pinctrl *pinctrl;
47558 + u32 revision;
47559
47560 match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev);
47561 if (match) {
47562 @@ -1874,7 +1966,7 @@ static int omap_hsmmc_probe(struct platf
47563 omap_hsmmc_context_save(host);
47564
47565 /* This can be removed once we support PBIAS with DT */
47566 - if (host->dev->of_node && host->mapbase == 0x4809c000)
47567 + if (host->dev->of_node && res->start == 0x4809c000)
47568 host->pbias_disable = 1;
47569
47570 host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
47571 @@ -1976,6 +2068,12 @@ static int omap_hsmmc_probe(struct platf
47572 host->use_reg = 1;
47573 }
47574
47575 + revision = OMAP_HSMMC_READ(host->base, REV);
47576 + if ((revision >> OMAP_HSMMC_REV_SHIFT) >= OMAP_HSMMC_REV_33) {
47577 + mmc->caps |= MMC_CAP_CMD23;
47578 + host->flags |= AUTO_CMD23;
47579 + }
47580 +
47581 mmc->ocr_avail = mmc_slot(host).ocr_mask;
47582
47583 /* Request IRQ for card detect */
47584 --- a/drivers/mtd/devices/elm.c
47585 +++ b/drivers/mtd/devices/elm.c
47586 @@ -22,8 +22,11 @@
47587 #include <linux/of.h>
47588 #include <linux/sched.h>
47589 #include <linux/pm_runtime.h>
47590 +#include <linux/mtd/mtd.h>
47591 +#include <linux/mtd/nand.h>
47592 #include <linux/platform_data/elm.h>
47593
47594 +#define DRIVER_NAME "omap-elm"
47595 #define ELM_SYSCONFIG 0x010
47596 #define ELM_IRQSTATUS 0x018
47597 #define ELM_IRQENABLE 0x01c
47598 @@ -82,8 +85,10 @@ struct elm_info {
47599 void __iomem *elm_base;
47600 struct completion elm_completion;
47601 struct list_head list;
47602 + struct mtd_info *mtd;
47603 enum bch_ecc bch_type;
47604 struct elm_registers elm_regs;
47605 + int eccsteps;
47606 };
47607
47608 static LIST_HEAD(elm_devices);
47609 @@ -103,19 +108,42 @@ static u32 elm_read_reg(struct elm_info
47610 * @dev: ELM device
47611 * @bch_type: Type of BCH ecc
47612 */
47613 -int elm_config(struct device *dev, enum bch_ecc bch_type)
47614 +int elm_config(struct device *dev, struct mtd_info *mtd,
47615 + enum bch_ecc bch_type)
47616 {
47617 u32 reg_val;
47618 - struct elm_info *info = dev_get_drvdata(dev);
47619 -
47620 + struct elm_info *info;
47621 + struct nand_chip *chip;
47622 + if (!dev) {
47623 + pr_err("%s: ELM device not found\n", DRIVER_NAME);
47624 + return -ENODEV;
47625 + }
47626 + info = dev_get_drvdata(dev);
47627 if (!info) {
47628 - dev_err(dev, "Unable to configure elm - device not probed?\n");
47629 + pr_err("%s: ELM device data not found\n", DRIVER_NAME);
47630 return -ENODEV;
47631 }
47632 -
47633 + if (!mtd) {
47634 + pr_err("%s: MTD device not found\n", DRIVER_NAME);
47635 + return -ENODEV;
47636 + }
47637 + chip = mtd->priv;
47638 + /* ELM supports error correction in chunks of 512bytes of data only
47639 + * where each 512bytes of data has its own ECC syndrome */
47640 + if (chip->ecc.size != 512) {
47641 + pr_err("%s: invalid ecc_size configuration", DRIVER_NAME);
47642 + return -EINVAL;
47643 + }
47644 + if (mtd->writesize > 4096) {
47645 + pr_err("%s: page-size > 4096 is not supported", DRIVER_NAME);
47646 + return -EINVAL;
47647 + }
47648 + /* ELM eccsteps required to decode complete NAND page */
47649 + info->mtd = mtd;
47650 + info->bch_type = bch_type;
47651 + info->eccsteps = mtd->writesize / chip->ecc.size;
47652 reg_val = (bch_type & ECC_BCH_LEVEL_MASK) | (ELM_ECC_SIZE << 16);
47653 elm_write_reg(info, ELM_LOCATION_CONFIG, reg_val);
47654 - info->bch_type = bch_type;
47655
47656 return 0;
47657 }
47658 @@ -152,55 +180,80 @@ static void elm_configure_page_mode(stru
47659 * Load syndrome fragment registers with calculated ecc in reverse order.
47660 */
47661 static void elm_load_syndrome(struct elm_info *info,
47662 - struct elm_errorvec *err_vec, u8 *ecc)
47663 + struct elm_errorvec *err_vec, u8 *ecc_calc)
47664 {
47665 + struct nand_chip *chip = info->mtd->priv;
47666 + unsigned int eccbytes = chip->ecc.bytes;
47667 + u8 *ecc = ecc_calc;
47668 int i, offset;
47669 u32 val;
47670
47671 - for (i = 0; i < ERROR_VECTOR_MAX; i++) {
47672 -
47673 + for (i = 0; i < info->eccsteps; i++) {
47674 /* Check error reported */
47675 if (err_vec[i].error_reported) {
47676 elm_configure_page_mode(info, i, true);
47677 - offset = ELM_SYNDROME_FRAGMENT_0 +
47678 - SYNDROME_FRAGMENT_REG_SIZE * i;
47679 -
47680 - /* BCH8 */
47681 - if (info->bch_type) {
47682 -
47683 - /* syndrome fragment 0 = ecc[9-12B] */
47684 - val = cpu_to_be32(*(u32 *) &ecc[9]);
47685 - elm_write_reg(info, offset, val);
47686 -
47687 - /* syndrome fragment 1 = ecc[5-8B] */
47688 - offset += 4;
47689 - val = cpu_to_be32(*(u32 *) &ecc[5]);
47690 - elm_write_reg(info, offset, val);
47691 -
47692 - /* syndrome fragment 2 = ecc[1-4B] */
47693 - offset += 4;
47694 - val = cpu_to_be32(*(u32 *) &ecc[1]);
47695 - elm_write_reg(info, offset, val);
47696 -
47697 - /* syndrome fragment 3 = ecc[0B] */
47698 - offset += 4;
47699 - val = ecc[0];
47700 - elm_write_reg(info, offset, val);
47701 - } else {
47702 - /* syndrome fragment 0 = ecc[20-52b] bits */
47703 - val = (cpu_to_be32(*(u32 *) &ecc[3]) >> 4) |
47704 - ((ecc[2] & 0xf) << 28);
47705 - elm_write_reg(info, offset, val);
47706 -
47707 - /* syndrome fragment 1 = ecc[0-20b] bits */
47708 - offset += 4;
47709 - val = cpu_to_be32(*(u32 *) &ecc[0]) >> 12;
47710 - elm_write_reg(info, offset, val);
47711 + offset = SYNDROME_FRAGMENT_REG_SIZE * i;
47712 + ecc = ecc_calc + (i * eccbytes);
47713 + switch (info->bch_type) {
47714 + case BCH4_ECC:
47715 + val = ((*(ecc + 6) >> 4) & 0x0F) |
47716 + *(ecc + 5) << 4 | *(ecc + 4) << 12 |
47717 + *(ecc + 3) << 20 | *(ecc + 2) << 28;
47718 + elm_write_reg(info, (ELM_SYNDROME_FRAGMENT_0 +
47719 + offset), cpu_to_le32(val));
47720 + val = ((*(ecc + 2) >> 4) & 0x0F) |
47721 + *(ecc + 1) << 4 | *(ecc + 0) << 12;
47722 + elm_write_reg(info, (ELM_SYNDROME_FRAGMENT_1 +
47723 + offset), cpu_to_le32(val));
47724 + break;
47725 + case BCH8_ECC:
47726 + val = *(ecc + 12) << 0 | *(ecc + 11) << 8 |
47727 + *(ecc + 10) << 16 | *(ecc + 9) << 24;
47728 + elm_write_reg(info, (ELM_SYNDROME_FRAGMENT_0 +
47729 + offset), cpu_to_le32(val));
47730 + val = *(ecc + 8) << 0 | *(ecc + 7) << 8 |
47731 + *(ecc + 6) << 16 | *(ecc + 5) << 24;
47732 + elm_write_reg(info, (ELM_SYNDROME_FRAGMENT_1 +
47733 + offset), cpu_to_le32(val));
47734 + val = *(ecc + 4) << 0 | *(ecc + 3) << 8 |
47735 + *(ecc + 2) << 16 | *(ecc + 1) << 24;
47736 + elm_write_reg(info, (ELM_SYNDROME_FRAGMENT_2 +
47737 + offset), cpu_to_le32(val));
47738 + val = *(ecc + 0) << 0 & 0x000000FF;
47739 + elm_write_reg(info, (ELM_SYNDROME_FRAGMENT_3 +
47740 + offset), cpu_to_le32(val));
47741 + break;
47742 + case BCH16_ECC:
47743 + val = *(ecc + 25) << 0 | *(ecc + 24) << 8 |
47744 + *(ecc + 23) << 16 | *(ecc + 22) << 24;
47745 + elm_write_reg(info, (ELM_SYNDROME_FRAGMENT_0 +
47746 + offset), cpu_to_le32(val));
47747 + val = *(ecc + 21) << 0 | *(ecc + 20) << 8 |
47748 + *(ecc + 19) << 16 | *(ecc + 18) << 24;
47749 + elm_write_reg(info, (ELM_SYNDROME_FRAGMENT_1 +
47750 + offset), cpu_to_le32(val));
47751 + val = *(ecc + 17) << 0 | *(ecc + 16) << 8 |
47752 + *(ecc + 15) << 16 | *(ecc + 14) << 24;
47753 + elm_write_reg(info, (ELM_SYNDROME_FRAGMENT_2 +
47754 + offset), cpu_to_le32(val));
47755 + val = *(ecc + 13) << 0 | *(ecc + 12) << 8 |
47756 + *(ecc + 11) << 16 | *(ecc + 10) << 24;
47757 + elm_write_reg(info, (ELM_SYNDROME_FRAGMENT_3 +
47758 + offset), cpu_to_le32(val));
47759 + val = *(ecc + 9) << 0 | *(ecc + 8) << 8 |
47760 + *(ecc + 7) << 16 | *(ecc + 6) << 24;
47761 + elm_write_reg(info, (ELM_SYNDROME_FRAGMENT_4 +
47762 + offset), cpu_to_le32(val));
47763 + val = *(ecc + 5) << 0 | *(ecc + 4) << 8 |
47764 + *(ecc + 3) << 16 | *(ecc + 2) << 24;
47765 + elm_write_reg(info, (ELM_SYNDROME_FRAGMENT_5 +
47766 + offset), cpu_to_le32(val));
47767 + val = *(ecc + 1) << 0 | *(ecc + 0) << 8;
47768 + elm_write_reg(info, (ELM_SYNDROME_FRAGMENT_6 +
47769 + offset), cpu_to_le32(val));
47770 + break;
47771 }
47772 }
47773 -
47774 - /* Update ecc pointer with ecc byte size */
47775 - ecc += info->bch_type ? BCH8_SIZE : BCH4_SIZE;
47776 }
47777 }
47778
47779 @@ -223,7 +276,7 @@ static void elm_start_processing(struct
47780 * Set syndrome vector valid, so that ELM module
47781 * will process it for vectors error is reported
47782 */
47783 - for (i = 0; i < ERROR_VECTOR_MAX; i++) {
47784 + for (i = 0; i < info->eccsteps; i++) {
47785 if (err_vec[i].error_reported) {
47786 offset = ELM_SYNDROME_FRAGMENT_6 +
47787 SYNDROME_FRAGMENT_REG_SIZE * i;
47788 @@ -252,7 +305,7 @@ static void elm_error_correction(struct
47789 int offset;
47790 u32 reg_val;
47791
47792 - for (i = 0; i < ERROR_VECTOR_MAX; i++) {
47793 + for (i = 0; i < info->eccsteps; i++) {
47794
47795 /* Check error reported */
47796 if (err_vec[i].error_reported) {
47797 @@ -263,14 +316,12 @@ static void elm_error_correction(struct
47798 if (reg_val & ECC_CORRECTABLE_MASK) {
47799 offset = ELM_ERROR_LOCATION_0 +
47800 ERROR_LOCATION_SIZE * i;
47801 -
47802 /* Read count of correctable errors */
47803 err_vec[i].error_count = reg_val &
47804 ECC_NB_ERRORS_MASK;
47805
47806 /* Update the error locations in error vector */
47807 for (j = 0; j < err_vec[i].error_count; j++) {
47808 -
47809 reg_val = elm_read_reg(info, offset);
47810 err_vec[i].error_loc[j] = reg_val &
47811 ECC_ERROR_LOCATION_MASK;
47812 --- a/drivers/mtd/devices/Kconfig
47813 +++ b/drivers/mtd/devices/Kconfig
47814 @@ -95,13 +95,6 @@ config MTD_M25P80
47815 if you want to specify device partitioning or to use a device which
47816 doesn't support the JEDEC ID instruction.
47817
47818 -config M25PXX_USE_FAST_READ
47819 - bool "Use FAST_READ OPCode allowing SPI CLK >= 50MHz"
47820 - depends on MTD_M25P80
47821 - default y
47822 - help
47823 - This option enables FAST_READ access supported by ST M25Pxx.
47824 -
47825 config MTD_SPEAR_SMI
47826 tristate "SPEAR MTD NOR Support through SMI controller"
47827 depends on PLAT_SPEAR
47828 --- a/drivers/mtd/devices/m25p80.c
47829 +++ b/drivers/mtd/devices/m25p80.c
47830 @@ -41,6 +41,7 @@
47831 #define OPCODE_WRSR 0x01 /* Write status register 1 byte */
47832 #define OPCODE_NORM_READ 0x03 /* Read data bytes (low frequency) */
47833 #define OPCODE_FAST_READ 0x0b /* Read data bytes (high frequency) */
47834 +#define OPCODE_QUAD_READ 0x6b /* QUAD READ */
47835 #define OPCODE_PP 0x02 /* Page program (up to 256 bytes) */
47836 #define OPCODE_BE_4K 0x20 /* Erase 4KiB block */
47837 #define OPCODE_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */
47838 @@ -48,10 +49,12 @@
47839 #define OPCODE_CHIP_ERASE 0xc7 /* Erase whole flash chip */
47840 #define OPCODE_SE 0xd8 /* Sector erase (usually 64KiB) */
47841 #define OPCODE_RDID 0x9f /* Read JEDEC ID */
47842 +#define OPCODE_RDCR 0x35 /* Read configuration register */
47843
47844 /* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
47845 #define OPCODE_NORM_READ_4B 0x13 /* Read data bytes (low frequency) */
47846 #define OPCODE_FAST_READ_4B 0x0c /* Read data bytes (high frequency) */
47847 +#define OPCODE_QUAD_READ_4B 0x6c /* Read data bytes */
47848 #define OPCODE_PP_4B 0x12 /* Page program (up to 256 bytes) */
47849 #define OPCODE_SE_4B 0xdc /* Sector erase (usually 64KiB) */
47850
47851 @@ -76,9 +79,13 @@
47852 #define SR_BP2 0x10 /* Block protect 2 */
47853 #define SR_SRWD 0x80 /* SR write protect */
47854
47855 +/* Configuration Register bits. */
47856 +#define CR_QUAD_EN_SPAN 0x2 /* Spansion Quad I/O */
47857 +#define SR_QUAD_EN_MX 0x40 /* Macronix Quad I/O */
47858 +
47859 /* Define max times to check status register before we give up. */
47860 #define MAX_READY_WAIT_JIFFIES (40 * HZ) /* M25P16 specs 40s max chip erase */
47861 -#define MAX_CMD_SIZE 5
47862 +#define MAX_CMD_SIZE 6
47863
47864 #define JEDEC_MFR(_jedec_id) ((_jedec_id) >> 16)
47865
47866 @@ -101,6 +108,8 @@ struct m25p {
47867 u8 program_opcode;
47868 u8 *command;
47869 bool fast_read;
47870 + bool quad_read;
47871 + bool mmap;
47872 };
47873
47874 static inline struct m25p *mtd_to_m25p(struct mtd_info *mtd)
47875 @@ -137,6 +146,26 @@ static int read_sr(struct m25p *flash)
47876 }
47877
47878 /*
47879 + * Read the configuration register, returning its value in the location
47880 + * Return the configuration register value.
47881 + * Returns negative if error occurred.
47882 + */
47883 +static int read_cr(struct m25p *flash)
47884 +{
47885 + u8 code = OPCODE_RDCR;
47886 + int ret;
47887 + u8 val;
47888 +
47889 + ret = spi_write_then_read(flash->spi, &code, 1, &val, 1);
47890 + if (ret < 0) {
47891 + dev_err(&flash->spi->dev, "error %d reading CR\n", ret);
47892 + return ret;
47893 + }
47894 +
47895 + return val;
47896 +}
47897 +
47898 +/*
47899 * Write status register 1 byte
47900 * Returns negative if error occurred.
47901 */
47902 @@ -226,6 +255,93 @@ static int wait_till_ready(struct m25p *
47903 }
47904
47905 /*
47906 + * It should be something like this. Note the asterisk alignment. You
47907 + * also could wrap the right edge neatly to nearly 80 characters.
47908 + */
47909 +static int write_sr_cr(struct m25p *flash, u16 val)
47910 +{
47911 + flash->command[0] = OPCODE_WRSR;
47912 + flash->command[1] = val & 0xff;
47913 + flash->command[2] = (val >> 8);
47914 +
47915 + return spi_write(flash->spi, flash->command, 3);
47916 +}
47917 +
47918 +static int macronix_quad_enable(struct m25p *flash)
47919 +{
47920 + int ret, val;
47921 + u8 cmd[2];
47922 + cmd[0] = OPCODE_WRSR;
47923 +
47924 + val = read_sr(flash);
47925 + cmd[1] = val | SR_QUAD_EN_MX;
47926 + write_enable(flash);
47927 +
47928 + spi_write(flash->spi, &cmd, 2);
47929 +
47930 + if (wait_till_ready(flash))
47931 + return 1;
47932 +
47933 + ret = read_sr(flash);
47934 + if (!(ret > 0 && (ret & SR_QUAD_EN_MX))) {
47935 + dev_err(&flash->spi->dev,
47936 + "Macronix Quad bit not set");
47937 + return -EINVAL;
47938 + }
47939 +
47940 + return 0;
47941 +}
47942 +
47943 +static int spansion_quad_enable(struct m25p *flash)
47944 +{
47945 + int ret;
47946 + int quad_en = CR_QUAD_EN_SPAN << 8;
47947 +
47948 + write_enable(flash);
47949 +
47950 + ret = write_sr_cr(flash, quad_en);
47951 + if (ret < 0) {
47952 + dev_err(&flash->spi->dev,
47953 + "error while writing configuration register");
47954 + return -EINVAL;
47955 + }
47956 +
47957 + /* read back and check it */
47958 + ret = read_cr(flash);
47959 + if (!(ret > 0 && (ret & CR_QUAD_EN_SPAN))) {
47960 + dev_err(&flash->spi->dev,
47961 + "Spansion Quad bit not set");
47962 + return -EINVAL;
47963 + }
47964 +
47965 + return 0;
47966 +}
47967 +
47968 +static inline int set_quad_mode(struct m25p *flash, u32 jedec_id, int enable)
47969 +{
47970 + int status;
47971 +
47972 + switch (JEDEC_MFR(jedec_id)) {
47973 + case CFI_MFR_MACRONIX:
47974 + status = macronix_quad_enable(flash);
47975 + if (status) {
47976 + dev_err(&flash->spi->dev,
47977 + "Macronix quad not enable");
47978 + return -EINVAL;
47979 + }
47980 + return status;
47981 + default:
47982 + status = spansion_quad_enable(flash);
47983 + if (status) {
47984 + dev_err(&flash->spi->dev,
47985 + "Spansion quad not enable");
47986 + return -EINVAL;
47987 + }
47988 + return status;
47989 + }
47990 +}
47991 +
47992 +/*
47993 * Erase the whole flash memory
47994 *
47995 * Returns 0 if successful, non-zero otherwise.
47996 @@ -355,6 +471,13 @@ static int m25p80_erase(struct mtd_info
47997 return 0;
47998 }
47999
48000 +static inline int m25p80_dummy_cycles_read(struct m25p *flash)
48001 +{
48002 + if (flash->quad_read || flash->fast_read)
48003 + return 1;
48004 + return 0;
48005 +}
48006 +
48007 /*
48008 * Read an address range from the flash chip. The address range
48009 * may be any size provided it is within the physical boundaries.
48010 @@ -373,14 +496,14 @@ static int m25p80_read(struct mtd_info *
48011 spi_message_init(&m);
48012 memset(t, 0, (sizeof t));
48013
48014 - /* NOTE:
48015 - * OPCODE_FAST_READ (if available) is faster.
48016 - * Should add 1 byte DUMMY_BYTE.
48017 - */
48018 + t[0].memory_map = 1;
48019 t[0].tx_buf = flash->command;
48020 - t[0].len = m25p_cmdsz(flash) + (flash->fast_read ? 1 : 0);
48021 + t[0].len = flash->mmap ? from : m25p_cmdsz(flash) +
48022 + m25p80_dummy_cycles_read(flash);
48023 spi_message_add_tail(&t[0], &m);
48024
48025 + t[1].memory_map = 1;
48026 + t[1].rx_nbits = flash->quad_read ? SPI_NBITS_QUAD : 1;
48027 t[1].rx_buf = buf;
48028 t[1].len = len;
48029 spi_message_add_tail(&t[1], &m);
48030 @@ -394,11 +517,6 @@ static int m25p80_read(struct mtd_info *
48031 return 1;
48032 }
48033
48034 - /* FIXME switch to OPCODE_FAST_READ. It's required for higher
48035 - * clocks; and at this writing, every chip this driver handles
48036 - * supports that opcode.
48037 - */
48038 -
48039 /* Set up the write data buffer. */
48040 opcode = flash->read_opcode;
48041 flash->command[0] = opcode;
48042 @@ -406,8 +524,8 @@ static int m25p80_read(struct mtd_info *
48043
48044 spi_sync(flash->spi, &m);
48045
48046 - *retlen = m.actual_length - m25p_cmdsz(flash) -
48047 - (flash->fast_read ? 1 : 0);
48048 + *retlen = flash->mmap ? len : m.actual_length - m25p_cmdsz(flash) -
48049 + m25p80_dummy_cycles_read(flash);
48050
48051 mutex_unlock(&flash->lock);
48052
48053 @@ -713,6 +831,7 @@ struct flash_info {
48054 #define SST_WRITE 0x04 /* use SST byte programming */
48055 #define M25P_NO_FR 0x08 /* Can't do fastread */
48056 #define SECT_4K_PMC 0x10 /* OPCODE_BE_4K_PMC works uniformly */
48057 +#define M25P80_QUAD_READ 0x20 /* Flash supports Quad Read */
48058 };
48059
48060 #define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
48061 @@ -789,7 +908,7 @@ static const struct spi_device_id m25p_i
48062 { "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) },
48063 { "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512, 0) },
48064 { "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) },
48065 - { "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, 0) },
48066 + { "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, M25P80_QUAD_READ) },
48067
48068 /* Micron */
48069 { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, 0) },
48070 @@ -808,7 +927,7 @@ static const struct spi_device_id m25p_i
48071 { "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, 0) },
48072 { "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128, 0) },
48073 { "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, 0) },
48074 - { "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512, 0) },
48075 + { "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512, M25P80_QUAD_READ) },
48076 { "s25fl512s", INFO(0x010220, 0x4d00, 256 * 1024, 256, 0) },
48077 { "s70fl01gs", INFO(0x010221, 0x4d00, 256 * 1024, 256, 0) },
48078 { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) },
48079 @@ -821,7 +940,7 @@ static const struct spi_device_id m25p_i
48080 { "s25sl032a", INFO(0x010215, 0, 64 * 1024, 64, 0) },
48081 { "s25sl064a", INFO(0x010216, 0, 64 * 1024, 128, 0) },
48082 { "s25fl016k", INFO(0xef4015, 0, 64 * 1024, 32, SECT_4K) },
48083 - { "s25fl064k", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
48084 + { "s25fl064k", INFO(0xef4017, 0x4d01, 64 * 1024, 128, SECT_4K) },
48085
48086 /* SST -- large erase sizes are "overlays", "sectors" are 4K */
48087 { "sst25vf040b", INFO(0xbf258d, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
48088 @@ -949,12 +1068,8 @@ static int m25p_probe(struct spi_device
48089 struct flash_info *info;
48090 unsigned i;
48091 struct mtd_part_parser_data ppdata;
48092 - struct device_node __maybe_unused *np = spi->dev.of_node;
48093 -
48094 -#ifdef CONFIG_MTD_OF_PARTS
48095 - if (!of_device_is_available(np))
48096 - return -ENODEV;
48097 -#endif
48098 + struct device_node *np = spi->dev.of_node;
48099 + int ret;
48100
48101 /* Platform data helps sort out which chip type we have, as
48102 * well as how this board partitions it. If we don't have
48103 @@ -1001,15 +1116,14 @@ static int m25p_probe(struct spi_device
48104 }
48105 }
48106
48107 - flash = kzalloc(sizeof *flash, GFP_KERNEL);
48108 + flash = devm_kzalloc(&spi->dev, sizeof(*flash), GFP_KERNEL);
48109 if (!flash)
48110 return -ENOMEM;
48111 - flash->command = kmalloc(MAX_CMD_SIZE + (flash->fast_read ? 1 : 0),
48112 - GFP_KERNEL);
48113 - if (!flash->command) {
48114 - kfree(flash);
48115 +
48116 +
48117 + flash->command = devm_kzalloc(&spi->dev, MAX_CMD_SIZE, GFP_KERNEL);
48118 + if (!flash->command)
48119 return -ENOMEM;
48120 - }
48121
48122 flash->spi = spi;
48123 mutex_init(&flash->lock);
48124 @@ -1039,6 +1153,15 @@ static int m25p_probe(struct spi_device
48125 flash->mtd._erase = m25p80_erase;
48126 flash->mtd._read = m25p80_read;
48127
48128 + if (spi->mode & SPI_RX_QUAD && info->flags & M25P80_QUAD_READ) {
48129 + ret = set_quad_mode(flash, info->jedec_id, 1);
48130 + if (ret) {
48131 + dev_err(&flash->spi->dev, "quad mode not supported\n");
48132 + return ret;
48133 + }
48134 + flash->quad_read = true;
48135 + }
48136 +
48137 /* flash protection support for STmicro chips */
48138 if (JEDEC_MFR(info->jedec_id) == CFI_MFR_ST) {
48139 flash->mtd._lock = m25p80_lock;
48140 @@ -1071,18 +1194,21 @@ static int m25p_probe(struct spi_device
48141 flash->page_size = info->page_size;
48142 flash->mtd.writebufsize = flash->page_size;
48143
48144 - flash->fast_read = false;
48145 - if (np && of_property_read_bool(np, "m25p,fast-read"))
48146 + if (np)
48147 + /* If we were instantiated by DT, use it */
48148 + flash->fast_read = of_property_read_bool(np, "m25p,fast-read");
48149 + else
48150 + /* If we weren't instantiated by DT, default to fast-read */
48151 flash->fast_read = true;
48152
48153 -#ifdef CONFIG_M25PXX_USE_FAST_READ
48154 - flash->fast_read = true;
48155 -#endif
48156 + /* Some devices cannot do fast-read, no matter what DT tells us */
48157 if (info->flags & M25P_NO_FR)
48158 flash->fast_read = false;
48159
48160 /* Default commands */
48161 - if (flash->fast_read)
48162 + if (flash->quad_read)
48163 + flash->read_opcode = OPCODE_QUAD_READ;
48164 + else if (flash->fast_read)
48165 flash->read_opcode = OPCODE_FAST_READ;
48166 else
48167 flash->read_opcode = OPCODE_NORM_READ;
48168 @@ -1094,21 +1220,14 @@ static int m25p_probe(struct spi_device
48169 else if (flash->mtd.size > 0x1000000) {
48170 /* enable 4-byte addressing if the device exceeds 16MiB */
48171 flash->addr_width = 4;
48172 - if (JEDEC_MFR(info->jedec_id) == CFI_MFR_AMD) {
48173 - /* Dedicated 4-byte command set */
48174 - flash->read_opcode = flash->fast_read ?
48175 - OPCODE_FAST_READ_4B :
48176 - OPCODE_NORM_READ_4B;
48177 - flash->program_opcode = OPCODE_PP_4B;
48178 - /* No small sector erase for 4-byte command set */
48179 - flash->erase_opcode = OPCODE_SE_4B;
48180 - flash->mtd.erasesize = info->sector_size;
48181 - } else
48182 - set_4byte(flash, info->jedec_id, 1);
48183 + set_4byte(flash, info->jedec_id, 1);
48184 } else {
48185 flash->addr_width = 3;
48186 }
48187
48188 + if (spi->mode & SPI_RX_MMAP)
48189 + flash->mmap = true;
48190 +
48191 dev_info(&spi->dev, "%s (%lld Kbytes)\n", id->name,
48192 (long long)flash->mtd.size >> 10);
48193
48194 @@ -1142,14 +1261,10 @@ static int m25p_probe(struct spi_device
48195 static int m25p_remove(struct spi_device *spi)
48196 {
48197 struct m25p *flash = spi_get_drvdata(spi);
48198 - int status;
48199
48200 /* Clean up MTD stuff. */
48201 - status = mtd_device_unregister(&flash->mtd);
48202 - if (status == 0) {
48203 - kfree(flash->command);
48204 - kfree(flash);
48205 - }
48206 + mtd_device_unregister(&flash->mtd);
48207 +
48208 return 0;
48209 }
48210
48211 --- a/drivers/mtd/nand/Kconfig
48212 +++ b/drivers/mtd/nand/Kconfig
48213 @@ -96,35 +96,13 @@ config MTD_NAND_OMAP2
48214
48215 config MTD_NAND_OMAP_BCH
48216 depends on MTD_NAND && MTD_NAND_OMAP2 && ARCH_OMAP3
48217 - tristate "Enable support for hardware BCH error correction"
48218 + tristate "Support hardware based BCH error correction"
48219 default n
48220 select BCH
48221 - select BCH_CONST_PARAMS
48222 help
48223 - Support for hardware BCH error correction.
48224 -
48225 -choice
48226 - prompt "BCH error correction capability"
48227 - depends on MTD_NAND_OMAP_BCH
48228 -
48229 -config MTD_NAND_OMAP_BCH8
48230 - bool "8 bits / 512 bytes (recommended)"
48231 - help
48232 - Support correcting up to 8 bitflips per 512-byte block.
48233 - This will use 13 bytes of spare area per 512 bytes of page data.
48234 - This is the recommended mode, as 4-bit mode does not work
48235 - on some OMAP3 revisions, due to a hardware bug.
48236 -
48237 -config MTD_NAND_OMAP_BCH4
48238 - bool "4 bits / 512 bytes"
48239 - help
48240 - Support correcting up to 4 bitflips per 512-byte block.
48241 - This will use 7 bytes of spare area per 512 bytes of page data.
48242 - Note that this mode does not work on some OMAP3 revisions, due to a
48243 - hardware bug. Please check your OMAP datasheet before selecting this
48244 - mode.
48245 -
48246 -endchoice
48247 + Some devices have built-in ELM hardware engine, which can be used to
48248 + locate and correct errors when using BCH ECC scheme. This enables the
48249 + driver support for same.
48250
48251 if MTD_NAND_OMAP_BCH
48252 config BCH_CONST_M
48253 --- a/drivers/mtd/nand/omap2.c
48254 +++ b/drivers/mtd/nand/omap2.c
48255 @@ -25,8 +25,11 @@
48256 #include <linux/of.h>
48257 #include <linux/of_device.h>
48258
48259 -#ifdef CONFIG_MTD_NAND_OMAP_BCH
48260 +#ifdef CONFIG_MTD_NAND_ECC_BCH
48261 #include <linux/bch.h>
48262 +#include <linux/mtd/nand_bch.h>
48263 +#endif
48264 +#ifdef CONFIG_MTD_NAND_OMAP_BCH
48265 #include <linux/platform_data/elm.h>
48266 #endif
48267
48268 @@ -35,6 +38,10 @@
48269 #define DRIVER_NAME "omap2-nand"
48270 #define OMAP_NAND_TIMEOUT_MS 5000
48271
48272 +#define GPMC_ECC_READ 0 /* Reset Hardware ECC for read */
48273 +#define GPMC_ECC_WRITE 1 /* Reset Hardware ECC for write */
48274 +#define GPMC_ECC_READSYN 2 /* Reset before syndrom is read back */
48275 +
48276 #define NAND_Ecc_P1e (1 << 0)
48277 #define NAND_Ecc_P2e (1 << 1)
48278 #define NAND_Ecc_P4e (1 << 2)
48279 @@ -103,13 +110,9 @@
48280 #define P4o_s(a) (TF(a & NAND_Ecc_P4o) << 1)
48281
48282 #define PREFETCH_CONFIG1_CS_SHIFT 24
48283 -#define ECC_CONFIG_CS_SHIFT 1
48284 #define CS_MASK 0x7
48285 #define ENABLE_PREFETCH (0x1 << 7)
48286 #define DMA_MPU_MODE_SHIFT 2
48287 -#define ECCSIZE0_SHIFT 12
48288 -#define ECCSIZE1_SHIFT 22
48289 -#define ECC1RESULTSIZE 0x1
48290 #define ECCCLEAR 0x100
48291 #define ECC1 0x1
48292 #define PREFETCH_FIFOTHRESHOLD_MAX 0x40
48293 @@ -120,33 +123,24 @@
48294
48295 #define OMAP24XX_DMA_GPMC 4
48296
48297 -#define BCH8_MAX_ERROR 8 /* upto 8 bit correctable */
48298 -#define BCH4_MAX_ERROR 4 /* upto 4 bit correctable */
48299 -
48300 #define SECTOR_BYTES 512
48301 /* 4 bit padding to make byte aligned, 56 = 52 + 4 */
48302 #define BCH4_BIT_PAD 4
48303 -#define BCH8_ECC_MAX ((SECTOR_BYTES + BCH8_ECC_OOB_BYTES) * 8)
48304 -#define BCH4_ECC_MAX ((SECTOR_BYTES + BCH4_ECC_OOB_BYTES) * 8)
48305
48306 -/* GPMC ecc engine settings for read */
48307 -#define BCH_WRAPMODE_1 1 /* BCH wrap mode 1 */
48308 -#define BCH8R_ECC_SIZE0 0x1a /* ecc_size0 = 26 */
48309 -#define BCH8R_ECC_SIZE1 0x2 /* ecc_size1 = 2 */
48310 -#define BCH4R_ECC_SIZE0 0xd /* ecc_size0 = 13 */
48311 -#define BCH4R_ECC_SIZE1 0x3 /* ecc_size1 = 3 */
48312 -
48313 -/* GPMC ecc engine settings for write */
48314 -#define BCH_WRAPMODE_6 6 /* BCH wrap mode 6 */
48315 -#define BCH_ECC_SIZE0 0x0 /* ecc_size0 = 0, no oob protection */
48316 -#define BCH_ECC_SIZE1 0x20 /* ecc_size1 = 32 */
48317 +#define BADBLOCK_MARKER_LENGTH 0x2
48318
48319 #ifdef CONFIG_MTD_NAND_OMAP_BCH
48320 -static u_char bch8_vector[] = {0xf3, 0xdb, 0x14, 0x16, 0x8b, 0xd2, 0xbe, 0xcc,
48321 - 0xac, 0x6b, 0xff, 0x99, 0x7b};
48322 -static u_char bch4_vector[] = {0x00, 0x6b, 0x31, 0xdd, 0x41, 0xbc, 0x10};
48323 +static u_char bch4_vector[] = {0x00, 0x6b, 0x31, 0xdd, 0x41, 0xbc, 0x10};
48324 +static u_char bch8_vector[] = {0xf3, 0xdb, 0x14, 0x16, 0x8b, 0xd2, 0xbe, 0xcc,
48325 + 0xac, 0x6b, 0xff, 0x99, 0x7b};
48326 +static u_char bch16_vector[] = {0xf5, 0x24, 0x1c, 0xd0, 0x61, 0xb3, 0xf1, 0x55,
48327 + 0x2e, 0x2c, 0x86, 0xa3, 0xed, 0x36, 0x1b, 0x78,
48328 + 0x48, 0x76, 0xa9, 0x3b, 0x97, 0xd1, 0x7a, 0x93,
48329 + 0x07, 0x0e};
48330 #endif
48331 -
48332 +static u8 bch4_polynomial[] = {0x28, 0x13, 0xcc, 0x39, 0x96, 0xac, 0x7f};
48333 +static u8 bch8_polynomial[] = {0xef, 0x51, 0x2e, 0x09, 0xed, 0x93, 0x9a, 0xc2,
48334 + 0x97, 0x79, 0xe5, 0x24, 0xb5};
48335 /* oob info generated runtime depending on ecc algorithm and layout selected */
48336 static struct nand_ecclayout omap_oobinfo;
48337 /* Define some generic bad / good block scan pattern which are used
48338 @@ -171,6 +165,7 @@ struct omap_nand_info {
48339 int gpmc_cs;
48340 unsigned long phys_base;
48341 unsigned long mem_size;
48342 + enum omap_ecc ecc_opt;
48343 struct completion comp;
48344 struct dma_chan *dma;
48345 int gpmc_irq_fifo;
48346 @@ -180,16 +175,11 @@ struct omap_nand_info {
48347 OMAP_NAND_IO_WRITE, /* write */
48348 } iomode;
48349 u_char *buf;
48350 - int buf_len;
48351 + int buf_len;
48352 struct gpmc_nand_regs reg;
48353 -
48354 -#ifdef CONFIG_MTD_NAND_OMAP_BCH
48355 - struct bch_control *bch;
48356 - struct nand_ecclayout ecclayout;
48357 - bool is_elm_used;
48358 + /* fields specific for BCHx_HW ECC scheme */
48359 struct device *elm_dev;
48360 struct device_node *of_node;
48361 -#endif
48362 };
48363
48364 /**
48365 @@ -948,9 +938,11 @@ static int omap_calculate_ecc(struct mtd
48366 u32 val;
48367
48368 val = readl(info->reg.gpmc_ecc_config);
48369 - if (((val >> ECC_CONFIG_CS_SHIFT) & ~CS_MASK) != info->gpmc_cs)
48370 + if (((val >> 1) & 0x7) != info->gpmc_cs) {
48371 + pr_err("%s: invalid ECC configuration for chip-select=%d",
48372 + DRIVER_NAME, info->gpmc_cs);
48373 return -EINVAL;
48374 -
48375 + }
48376 /* read ecc result */
48377 val = readl(info->reg.gpmc_ecc1_result);
48378 *ecc_code++ = val; /* P128e, ..., P1e */
48379 @@ -962,47 +954,6 @@ static int omap_calculate_ecc(struct mtd
48380 }
48381
48382 /**
48383 - * omap_enable_hwecc - This function enables the hardware ecc functionality
48384 - * @mtd: MTD device structure
48385 - * @mode: Read/Write mode
48386 - */
48387 -static void omap_enable_hwecc(struct mtd_info *mtd, int mode)
48388 -{
48389 - struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
48390 - mtd);
48391 - struct nand_chip *chip = mtd->priv;
48392 - unsigned int dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0;
48393 - u32 val;
48394 -
48395 - /* clear ecc and enable bits */
48396 - val = ECCCLEAR | ECC1;
48397 - writel(val, info->reg.gpmc_ecc_control);
48398 -
48399 - /* program ecc and result sizes */
48400 - val = ((((info->nand.ecc.size >> 1) - 1) << ECCSIZE1_SHIFT) |
48401 - ECC1RESULTSIZE);
48402 - writel(val, info->reg.gpmc_ecc_size_config);
48403 -
48404 - switch (mode) {
48405 - case NAND_ECC_READ:
48406 - case NAND_ECC_WRITE:
48407 - writel(ECCCLEAR | ECC1, info->reg.gpmc_ecc_control);
48408 - break;
48409 - case NAND_ECC_READSYN:
48410 - writel(ECCCLEAR, info->reg.gpmc_ecc_control);
48411 - break;
48412 - default:
48413 - dev_info(&info->pdev->dev,
48414 - "error: unrecognized Mode[%d]!\n", mode);
48415 - break;
48416 - }
48417 -
48418 - /* (ECC 16 or 8 bit col) | ( CS ) | ECC Enable */
48419 - val = (dev_width << 7) | (info->gpmc_cs << 1) | (0x1);
48420 - writel(val, info->reg.gpmc_ecc_config);
48421 -}
48422 -
48423 -/**
48424 * omap_wait - wait until the command is done
48425 * @mtd: MTD device structure
48426 * @chip: NAND Chip structure
48427 @@ -1058,496 +1009,357 @@ static int omap_dev_ready(struct mtd_inf
48428 }
48429 }
48430
48431 -#ifdef CONFIG_MTD_NAND_OMAP_BCH
48432 -
48433 /**
48434 - * omap3_enable_hwecc_bch - Program OMAP3 GPMC to perform BCH ECC correction
48435 + * omap_enable_hwecc - Configure OMAP GPMC to perform ECC calculation
48436 * @mtd: MTD device structure
48437 * @mode: Read/Write mode
48438 - *
48439 - * When using BCH, sector size is hardcoded to 512 bytes.
48440 - * Using wrapping mode 6 both for reading and writing if ELM module not uses
48441 - * for error correction.
48442 - * On writing,
48443 - * eccsize0 = 0 (no additional protected byte in spare area)
48444 - * eccsize1 = 32 (skip 32 nibbles = 16 bytes per sector in spare area)
48445 + * Configurations for eccsize0, eccsize1, and bch_wrapmode are based on
48446 + * GPMC function spec:
48447 + * Section 4.6.3.2.3: Supported NAND page mappings and ECC schemes
48448 */
48449 -static void omap3_enable_hwecc_bch(struct mtd_info *mtd, int mode)
48450 +static void omap_enable_hwecc(struct mtd_info *mtd, int mode)
48451 {
48452 - int nerrors;
48453 - unsigned int dev_width, nsectors;
48454 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
48455 mtd);
48456 struct nand_chip *chip = mtd->priv;
48457 - u32 val, wr_mode;
48458 - unsigned int ecc_size1, ecc_size0;
48459 -
48460 - /* Using wrapping mode 6 for writing */
48461 - wr_mode = BCH_WRAPMODE_6;
48462 -
48463 - /*
48464 - * ECC engine enabled for valid ecc_size0 nibbles
48465 - * and disabled for ecc_size1 nibbles.
48466 - */
48467 - ecc_size0 = BCH_ECC_SIZE0;
48468 - ecc_size1 = BCH_ECC_SIZE1;
48469 -
48470 - /* Perform ecc calculation on 512-byte sector */
48471 - nsectors = 1;
48472 -
48473 - /* Update number of error correction */
48474 - nerrors = info->nand.ecc.strength;
48475 -
48476 - /* Multi sector reading/writing for NAND flash with page size < 4096 */
48477 - if (info->is_elm_used && (mtd->writesize <= 4096)) {
48478 - if (mode == NAND_ECC_READ) {
48479 - /* Using wrapping mode 1 for reading */
48480 - wr_mode = BCH_WRAPMODE_1;
48481 -
48482 - /*
48483 - * ECC engine enabled for ecc_size0 nibbles
48484 - * and disabled for ecc_size1 nibbles.
48485 - */
48486 - ecc_size0 = (nerrors == 8) ?
48487 - BCH8R_ECC_SIZE0 : BCH4R_ECC_SIZE0;
48488 - ecc_size1 = (nerrors == 8) ?
48489 - BCH8R_ECC_SIZE1 : BCH4R_ECC_SIZE1;
48490 + unsigned int dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0;
48491 + unsigned int nsectors = (mtd->writesize / SECTOR_BYTES);
48492 + unsigned int ecc_algo = 0;
48493 + unsigned int bch_type = 0;
48494 + unsigned int eccsize1 = 0x00, eccsize0 = 0x00, bch_wrapmode = 0x00;
48495 + u32 ecc_size_config_val = 0;
48496 + u32 ecc_config_val = 0;
48497 +
48498 + switch (info->ecc_opt) {
48499 + case OMAP_ECC_HAMMING_CODE_HW:
48500 + ecc_algo = 0x0;
48501 + bch_wrapmode = 0x00;
48502 + eccsize0 = (chip->ecc.size >> 1) - 1;
48503 + eccsize1 = 0;
48504 + nsectors = 0;
48505 + break;
48506 + case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW:
48507 + case OMAP_ECC_BCH4_CODE_HW:
48508 + ecc_algo = 0x1;
48509 + bch_type = 0x0;
48510 + if (mode == GPMC_ECC_READ) {
48511 + bch_wrapmode = 0x01;
48512 + eccsize0 = 13; /* ECC bits in nibbles per sector */
48513 + eccsize1 = 3; /* non-ECC bits in nibbles per sector */
48514 + } else if (mode == GPMC_ECC_WRITE) {
48515 + eccsize0 = 0; /* extra bits in nibbles per sector */
48516 + eccsize1 = 32; /* OOB bits in nibbles per sector */
48517 + bch_wrapmode = 0x06;
48518 }
48519 -
48520 - /* Perform ecc calculation for one page (< 4096) */
48521 - nsectors = info->nand.ecc.steps;
48522 + break;
48523 + case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
48524 + case OMAP_ECC_BCH8_CODE_HW:
48525 + ecc_algo = 0x1;
48526 + bch_type = 0x1;
48527 + if (mode == GPMC_ECC_READ) {
48528 + bch_wrapmode = 0x01;
48529 + eccsize0 = 26; /* ECC bits in nibbles per sector */
48530 + eccsize1 = 2; /* non-ECC bits in nibbles per sector */
48531 + } else if (mode == GPMC_ECC_WRITE) {
48532 + bch_wrapmode = 0x01;
48533 + eccsize0 = 0; /* extra bits in nibbles per sector */
48534 + eccsize1 = 28; /* OOB bits in nibbles per sector */
48535 + }
48536 + break;
48537 + case OMAP_ECC_BCH16_CODE_HW:
48538 + ecc_algo = 0x1;
48539 + bch_type = 0x2;
48540 + if (mode == GPMC_ECC_READ) {
48541 + bch_wrapmode = 0x01;
48542 + eccsize0 = 52; /* ECC bits in nibbles per sector */
48543 + eccsize1 = 0; /* non-ECC bits in nibbles per sector */
48544 + } else if (mode == GPMC_ECC_WRITE) {
48545 + bch_wrapmode = 0x01;
48546 + eccsize0 = 0; /* extra bits in nibbles per sector */
48547 + eccsize1 = 52; /* OOB bits in nibbles per sector */
48548 + }
48549 + break;
48550 + default:
48551 + pr_err("selected ECC scheme not supported or not enabled\n");
48552 }
48553 -
48554 - writel(ECC1, info->reg.gpmc_ecc_control);
48555 -
48556 - /* Configure ecc size for BCH */
48557 - val = (ecc_size1 << ECCSIZE1_SHIFT) | (ecc_size0 << ECCSIZE0_SHIFT);
48558 - writel(val, info->reg.gpmc_ecc_size_config);
48559 -
48560 - dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0;
48561 -
48562 - /* BCH configuration */
48563 - val = ((1 << 16) | /* enable BCH */
48564 - (((nerrors == 8) ? 1 : 0) << 12) | /* 8 or 4 bits */
48565 - (wr_mode << 8) | /* wrap mode */
48566 - (dev_width << 7) | /* bus width */
48567 - (((nsectors-1) & 0x7) << 4) | /* number of sectors */
48568 - (info->gpmc_cs << 1) | /* ECC CS */
48569 - (0x1)); /* enable ECC */
48570 -
48571 - writel(val, info->reg.gpmc_ecc_config);
48572 -
48573 /* Clear ecc and enable bits */
48574 writel(ECCCLEAR | ECC1, info->reg.gpmc_ecc_control);
48575 + /* Configure ecc size for BCH */
48576 + ecc_size_config_val = (eccsize1 << 22) | (eccsize0 << 12);
48577 + writel(ecc_size_config_val, info->reg.gpmc_ecc_size_config);
48578 + /* Configure device details for BCH engine */
48579 + ecc_config_val = ((ecc_algo << 16) | /* HAM1 | BCHx */
48580 + (bch_type << 12) | /* BCH4/BCH8/BCH16 */
48581 + (bch_wrapmode << 8) | /* wrap mode */
48582 + (dev_width << 7) | /* bus width */
48583 + (((nsectors-1) & 0x7) << 4) | /* number of sectors */
48584 + (info->gpmc_cs << 1) | /* ECC CS */
48585 + (0x0)); /* disable ECC */
48586 + writel(ecc_config_val, info->reg.gpmc_ecc_config);
48587 + /* enable ECC engine */
48588 + writel(ecc_config_val | 0x1, info->reg.gpmc_ecc_config);
48589 + /* Clear ECC and enable bits */
48590 + writel(ECCCLEAR | ECC1, info->reg.gpmc_ecc_control);
48591 }
48592
48593 +#if defined(CONFIG_MTD_NAND_ECC_BCH) || defined(CONFIG_MTD_NAND_OMAP_BCH)
48594 /**
48595 - * omap3_calculate_ecc_bch4 - Generate 7 bytes of ECC bytes
48596 - * @mtd: MTD device structure
48597 - * @dat: The pointer to data on which ecc is computed
48598 - * @ecc_code: The ecc_code buffer
48599 - */
48600 -static int omap3_calculate_ecc_bch4(struct mtd_info *mtd, const u_char *dat,
48601 - u_char *ecc_code)
48602 -{
48603 - struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
48604 - mtd);
48605 - unsigned long nsectors, val1, val2;
48606 - int i;
48607 -
48608 - nsectors = ((readl(info->reg.gpmc_ecc_config) >> 4) & 0x7) + 1;
48609 -
48610 - for (i = 0; i < nsectors; i++) {
48611 -
48612 - /* Read hw-computed remainder */
48613 - val1 = readl(info->reg.gpmc_bch_result0[i]);
48614 - val2 = readl(info->reg.gpmc_bch_result1[i]);
48615 -
48616 - /*
48617 - * Add constant polynomial to remainder, in order to get an ecc
48618 - * sequence of 0xFFs for a buffer filled with 0xFFs; and
48619 - * left-justify the resulting polynomial.
48620 - */
48621 - *ecc_code++ = 0x28 ^ ((val2 >> 12) & 0xFF);
48622 - *ecc_code++ = 0x13 ^ ((val2 >> 4) & 0xFF);
48623 - *ecc_code++ = 0xcc ^ (((val2 & 0xF) << 4)|((val1 >> 28) & 0xF));
48624 - *ecc_code++ = 0x39 ^ ((val1 >> 20) & 0xFF);
48625 - *ecc_code++ = 0x96 ^ ((val1 >> 12) & 0xFF);
48626 - *ecc_code++ = 0xac ^ ((val1 >> 4) & 0xFF);
48627 - *ecc_code++ = 0x7f ^ ((val1 & 0xF) << 4);
48628 - }
48629 -
48630 - return 0;
48631 -}
48632 -
48633 -/**
48634 - * omap3_calculate_ecc_bch8 - Generate 13 bytes of ECC bytes
48635 - * @mtd: MTD device structure
48636 - * @dat: The pointer to data on which ecc is computed
48637 - * @ecc_code: The ecc_code buffer
48638 - */
48639 -static int omap3_calculate_ecc_bch8(struct mtd_info *mtd, const u_char *dat,
48640 - u_char *ecc_code)
48641 -{
48642 - struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
48643 - mtd);
48644 - unsigned long nsectors, val1, val2, val3, val4;
48645 - int i;
48646 -
48647 - nsectors = ((readl(info->reg.gpmc_ecc_config) >> 4) & 0x7) + 1;
48648 -
48649 - for (i = 0; i < nsectors; i++) {
48650 -
48651 - /* Read hw-computed remainder */
48652 - val1 = readl(info->reg.gpmc_bch_result0[i]);
48653 - val2 = readl(info->reg.gpmc_bch_result1[i]);
48654 - val3 = readl(info->reg.gpmc_bch_result2[i]);
48655 - val4 = readl(info->reg.gpmc_bch_result3[i]);
48656 -
48657 - /*
48658 - * Add constant polynomial to remainder, in order to get an ecc
48659 - * sequence of 0xFFs for a buffer filled with 0xFFs.
48660 - */
48661 - *ecc_code++ = 0xef ^ (val4 & 0xFF);
48662 - *ecc_code++ = 0x51 ^ ((val3 >> 24) & 0xFF);
48663 - *ecc_code++ = 0x2e ^ ((val3 >> 16) & 0xFF);
48664 - *ecc_code++ = 0x09 ^ ((val3 >> 8) & 0xFF);
48665 - *ecc_code++ = 0xed ^ (val3 & 0xFF);
48666 - *ecc_code++ = 0x93 ^ ((val2 >> 24) & 0xFF);
48667 - *ecc_code++ = 0x9a ^ ((val2 >> 16) & 0xFF);
48668 - *ecc_code++ = 0xc2 ^ ((val2 >> 8) & 0xFF);
48669 - *ecc_code++ = 0x97 ^ (val2 & 0xFF);
48670 - *ecc_code++ = 0x79 ^ ((val1 >> 24) & 0xFF);
48671 - *ecc_code++ = 0xe5 ^ ((val1 >> 16) & 0xFF);
48672 - *ecc_code++ = 0x24 ^ ((val1 >> 8) & 0xFF);
48673 - *ecc_code++ = 0xb5 ^ (val1 & 0xFF);
48674 - }
48675 -
48676 - return 0;
48677 -}
48678 -
48679 -/**
48680 - * omap3_calculate_ecc_bch - Generate bytes of ECC bytes
48681 + * omap_calculate_ecc_bch - Generate bytes of ECC bytes
48682 * @mtd: MTD device structure
48683 * @dat: The pointer to data on which ecc is computed
48684 * @ecc_code: The ecc_code buffer
48685 *
48686 * Support calculating of BCH4/8 ecc vectors for the page
48687 */
48688 -static int omap3_calculate_ecc_bch(struct mtd_info *mtd, const u_char *dat,
48689 - u_char *ecc_code)
48690 +static int omap_calculate_ecc_bch(struct mtd_info *mtd, const u_char *dat,
48691 + u_char *ecc_calc)
48692 {
48693 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
48694 mtd);
48695 - unsigned long nsectors, bch_val1, bch_val2, bch_val3, bch_val4;
48696 - int i, eccbchtsel;
48697 + struct nand_chip *chip = mtd->priv;
48698 + enum omap_ecc ecc_opt = info->ecc_opt;
48699 + struct gpmc_nand_regs *gpmc_regs = &info->reg;
48700 + u32 eccbytes = chip->ecc.bytes;
48701 + u_char *ecc_ptr;
48702 + u32 nsectors;
48703 + int i, val;
48704
48705 - nsectors = ((readl(info->reg.gpmc_ecc_config) >> 4) & 0x7) + 1;
48706 - /*
48707 - * find BCH scheme used
48708 - * 0 -> BCH4
48709 - * 1 -> BCH8
48710 - */
48711 - eccbchtsel = ((readl(info->reg.gpmc_ecc_config) >> 12) & 0x3);
48712 + val = readl(info->reg.gpmc_ecc_config);
48713 + if (((val >> 1) & 0x07) != info->gpmc_cs) {
48714 + pr_err("%s: invalid ECC configuration for chip-select=%d",
48715 + DRIVER_NAME, info->gpmc_cs);
48716 + return -EINVAL;
48717 + }
48718 + nsectors = ((readl(gpmc_regs->gpmc_ecc_config) >> 4) & 0x7) + 1;
48719
48720 for (i = 0; i < nsectors; i++) {
48721 -
48722 - /* Read hw-computed remainder */
48723 - bch_val1 = readl(info->reg.gpmc_bch_result0[i]);
48724 - bch_val2 = readl(info->reg.gpmc_bch_result1[i]);
48725 - if (eccbchtsel) {
48726 - bch_val3 = readl(info->reg.gpmc_bch_result2[i]);
48727 - bch_val4 = readl(info->reg.gpmc_bch_result3[i]);
48728 - }
48729 -
48730 - if (eccbchtsel) {
48731 - /* BCH8 ecc scheme */
48732 - *ecc_code++ = (bch_val4 & 0xFF);
48733 - *ecc_code++ = ((bch_val3 >> 24) & 0xFF);
48734 - *ecc_code++ = ((bch_val3 >> 16) & 0xFF);
48735 - *ecc_code++ = ((bch_val3 >> 8) & 0xFF);
48736 - *ecc_code++ = (bch_val3 & 0xFF);
48737 - *ecc_code++ = ((bch_val2 >> 24) & 0xFF);
48738 - *ecc_code++ = ((bch_val2 >> 16) & 0xFF);
48739 - *ecc_code++ = ((bch_val2 >> 8) & 0xFF);
48740 - *ecc_code++ = (bch_val2 & 0xFF);
48741 - *ecc_code++ = ((bch_val1 >> 24) & 0xFF);
48742 - *ecc_code++ = ((bch_val1 >> 16) & 0xFF);
48743 - *ecc_code++ = ((bch_val1 >> 8) & 0xFF);
48744 - *ecc_code++ = (bch_val1 & 0xFF);
48745 - /*
48746 - * Setting 14th byte to zero to handle
48747 - * erased page & maintain compatibility
48748 - * with RBL
48749 - */
48750 - *ecc_code++ = 0x0;
48751 - } else {
48752 - /* BCH4 ecc scheme */
48753 - *ecc_code++ = ((bch_val2 >> 12) & 0xFF);
48754 - *ecc_code++ = ((bch_val2 >> 4) & 0xFF);
48755 - *ecc_code++ = ((bch_val2 & 0xF) << 4) |
48756 - ((bch_val1 >> 28) & 0xF);
48757 - *ecc_code++ = ((bch_val1 >> 20) & 0xFF);
48758 - *ecc_code++ = ((bch_val1 >> 12) & 0xFF);
48759 - *ecc_code++ = ((bch_val1 >> 4) & 0xFF);
48760 - *ecc_code++ = ((bch_val1 & 0xF) << 4);
48761 - /*
48762 - * Setting 8th byte to zero to handle
48763 - * erased page
48764 - */
48765 - *ecc_code++ = 0x0;
48766 + ecc_ptr = ecc_calc;
48767 + switch (ecc_opt) {
48768 + case OMAP_ECC_HAMMING_CODE_HW:
48769 + return -EINVAL;
48770 + case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW:
48771 + case OMAP_ECC_BCH4_CODE_HW:
48772 + val = readl(gpmc_regs->gpmc_bch_result1[i]);
48773 + *(ecc_ptr++) = ((val >> 12) & 0xFF);
48774 + *(ecc_ptr++) = ((val >> 4) & 0xFF);
48775 + *(ecc_ptr) = ((val >> 0) << 4) & 0xF0;
48776 + val = readl(gpmc_regs->gpmc_bch_result0[i]);
48777 + *(ecc_ptr) = ((val >> 28) & 0x0F) | *(ecc_ptr);
48778 + ecc_ptr++;
48779 + *(ecc_ptr++) = ((val >> 20) & 0xFF);
48780 + *(ecc_ptr++) = ((val >> 12) & 0xFF);
48781 + *(ecc_ptr++) = ((val >> 4) & 0xFF);
48782 + *(ecc_ptr++) = ((val >> 0) << 4) & 0xF0;
48783 + break;
48784 + case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
48785 + case OMAP_ECC_BCH8_CODE_HW:
48786 + val = readl(gpmc_regs->gpmc_bch_result3[i]);
48787 + *(ecc_ptr++) = ((val >> 0) & 0xFF);
48788 + val = readl(gpmc_regs->gpmc_bch_result2[i]);
48789 + *(ecc_ptr++) = ((val >> 24) & 0xFF);
48790 + *(ecc_ptr++) = ((val >> 16) & 0xFF);
48791 + *(ecc_ptr++) = ((val >> 8) & 0xFF);
48792 + *(ecc_ptr++) = ((val >> 0) & 0xFF);
48793 + val = readl(gpmc_regs->gpmc_bch_result1[i]);
48794 + *(ecc_ptr++) = ((val >> 24) & 0xFF);
48795 + *(ecc_ptr++) = ((val >> 16) & 0xFF);
48796 + *(ecc_ptr++) = ((val >> 8) & 0xFF);
48797 + *(ecc_ptr++) = ((val >> 0) & 0xFF);
48798 + val = readl(gpmc_regs->gpmc_bch_result0[i]);
48799 + *(ecc_ptr++) = ((val >> 24) & 0xFF);
48800 + *(ecc_ptr++) = ((val >> 16) & 0xFF);
48801 + *(ecc_ptr++) = ((val >> 8) & 0xFF);
48802 + *(ecc_ptr++) = ((val >> 0) & 0xFF);
48803 + break;
48804 + case OMAP_ECC_BCH16_CODE_HW:
48805 + val = readl(gpmc_regs->gpmc_bch_result6[i]);
48806 + *(ecc_ptr++) = ((val >> 8) & 0xFF);
48807 + *(ecc_ptr++) = ((val >> 0) & 0xFF);
48808 + val = readl(gpmc_regs->gpmc_bch_result5[i]);
48809 + *(ecc_ptr++) = ((val >> 24) & 0xFF);
48810 + *(ecc_ptr++) = ((val >> 16) & 0xFF);
48811 + *(ecc_ptr++) = ((val >> 8) & 0xFF);
48812 + *(ecc_ptr++) = ((val >> 0) & 0xFF);
48813 + val = readl(gpmc_regs->gpmc_bch_result4[i]);
48814 + *(ecc_ptr++) = ((val >> 24) & 0xFF);
48815 + *(ecc_ptr++) = ((val >> 16) & 0xFF);
48816 + *(ecc_ptr++) = ((val >> 8) & 0xFF);
48817 + *(ecc_ptr++) = ((val >> 0) & 0xFF);
48818 + val = readl(gpmc_regs->gpmc_bch_result3[i]);
48819 + *(ecc_ptr++) = ((val >> 24) & 0xFF);
48820 + *(ecc_ptr++) = ((val >> 16) & 0xFF);
48821 + *(ecc_ptr++) = ((val >> 8) & 0xFF);
48822 + *(ecc_ptr++) = ((val >> 0) & 0xFF);
48823 + val = readl(gpmc_regs->gpmc_bch_result2[i]);
48824 + *(ecc_ptr++) = ((val >> 24) & 0xFF);
48825 + *(ecc_ptr++) = ((val >> 16) & 0xFF);
48826 + *(ecc_ptr++) = ((val >> 8) & 0xFF);
48827 + *(ecc_ptr++) = ((val >> 0) & 0xFF);
48828 + val = readl(gpmc_regs->gpmc_bch_result1[i]);
48829 + *(ecc_ptr++) = ((val >> 24) & 0xFF);
48830 + *(ecc_ptr++) = ((val >> 16) & 0xFF);
48831 + *(ecc_ptr++) = ((val >> 8) & 0xFF);
48832 + *(ecc_ptr++) = ((val >> 0) & 0xFF);
48833 + val = readl(gpmc_regs->gpmc_bch_result0[i]);
48834 + *(ecc_ptr++) = ((val >> 24) & 0xFF);
48835 + *(ecc_ptr++) = ((val >> 16) & 0xFF);
48836 + *(ecc_ptr++) = ((val >> 8) & 0xFF);
48837 + *(ecc_ptr++) = ((val >> 0) & 0xFF);
48838 + break;
48839 + default:
48840 + return -EINVAL;
48841 }
48842 + /* ECC scheme specific syndrome customizations */
48843 + switch (ecc_opt) {
48844 + case OMAP_ECC_HAMMING_CODE_HW:
48845 + return -EINVAL;
48846 + case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW:
48847 + for (i = 0; i < eccbytes; i++)
48848 + *(ecc_calc + i) = *(ecc_calc + i) ^
48849 + bch4_polynomial[i];
48850 + break;
48851 + case OMAP_ECC_BCH4_CODE_HW:
48852 + *(ecc_ptr++) = 0x00;
48853 + break;
48854 + case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
48855 + for (i = 0; i < eccbytes; i++)
48856 + *(ecc_calc + i) = *(ecc_calc + i) ^
48857 + bch8_polynomial[i];
48858 + break;
48859 + case OMAP_ECC_BCH8_CODE_HW:
48860 + *(ecc_ptr++) = 0x00;
48861 + break;
48862 + case OMAP_ECC_BCH16_CODE_HW:
48863 + break;
48864 + }
48865 + /* update pointer to next sector */
48866 + ecc_calc += eccbytes;
48867 }
48868 -
48869 return 0;
48870 }
48871 +#endif /*defined(CONFIG_MTD_NAND_ECC_BCH) || defined(CONFIG_MTD_NAND_OMAP_BCH)*/
48872
48873 -/**
48874 - * erased_sector_bitflips - count bit flips
48875 - * @data: data sector buffer
48876 - * @oob: oob buffer
48877 - * @info: omap_nand_info
48878 - *
48879 - * Check the bit flips in erased page falls below correctable level.
48880 - * If falls below, report the page as erased with correctable bit
48881 - * flip, else report as uncorrectable page.
48882 - */
48883 -static int erased_sector_bitflips(u_char *data, u_char *oob,
48884 - struct omap_nand_info *info)
48885 -{
48886 - int flip_bits = 0, i;
48887 -
48888 - for (i = 0; i < info->nand.ecc.size; i++) {
48889 - flip_bits += hweight8(~data[i]);
48890 - if (flip_bits > info->nand.ecc.strength)
48891 - return 0;
48892 - }
48893 -
48894 - for (i = 0; i < info->nand.ecc.bytes - 1; i++) {
48895 - flip_bits += hweight8(~oob[i]);
48896 - if (flip_bits > info->nand.ecc.strength)
48897 - return 0;
48898 - }
48899 -
48900 - /*
48901 - * Bit flips falls in correctable level.
48902 - * Fill data area with 0xFF
48903 - */
48904 - if (flip_bits) {
48905 - memset(data, 0xFF, info->nand.ecc.size);
48906 - memset(oob, 0xFF, info->nand.ecc.bytes);
48907 - }
48908 -
48909 - return flip_bits;
48910 -}
48911 -
48912 +#ifdef CONFIG_MTD_NAND_OMAP_BCH
48913 /**
48914 * omap_elm_correct_data - corrects page data area in case error reported
48915 * @mtd: MTD device structure
48916 * @data: page data
48917 * @read_ecc: ecc read from nand flash
48918 - * @calc_ecc: ecc read from HW ECC registers
48919 - *
48920 - * Calculated ecc vector reported as zero in case of non-error pages.
48921 - * In case of error/erased pages non-zero error vector is reported.
48922 - * In case of non-zero ecc vector, check read_ecc at fixed offset
48923 - * (x = 13/7 in case of BCH8/4 == 0) to find page programmed or not.
48924 - * To handle bit flips in this data, count the number of 0's in
48925 - * read_ecc[x] and check if it greater than 4. If it is less, it is
48926 - * programmed page, else erased page.
48927 - *
48928 - * 1. If page is erased, check with standard ecc vector (ecc vector
48929 - * for erased page to find any bit flip). If check fails, bit flip
48930 - * is present in erased page. Count the bit flips in erased page and
48931 - * if it falls under correctable level, report page with 0xFF and
48932 - * update the correctable bit information.
48933 - * 2. If error is reported on programmed page, update elm error
48934 - * vector and correct the page with ELM error correction routine.
48935 - *
48936 + * @calc_ecc: ecc calculated after reading Data and OOB regions from flash
48937 + * As calc_ecc is calculated over both main & oob, so calc_ecc would be
48938 + * non-zero only in following cases:
48939 + * - bit-flips in data or oob region
48940 + * - erase page, where no ECC is written in OOB area
48941 + * However, erased_pages can be differentiated from corrupted pages
48942 + * by comparing the calculated ECC with pre-defined syndrome ECC_of_ALL(0xFF)
48943 + * Bit-flips in erased-pages would also be caught by comparing, calc_ecc
48944 + * with ECC_of_ALL(0xFF)
48945 */
48946 static int omap_elm_correct_data(struct mtd_info *mtd, u_char *data,
48947 u_char *read_ecc, u_char *calc_ecc)
48948 {
48949 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
48950 mtd);
48951 - int eccsteps = info->nand.ecc.steps;
48952 - int i , j, stat = 0;
48953 - int eccsize, eccflag, ecc_vector_size;
48954 + enum omap_ecc ecc_opt = info->ecc_opt;
48955 + struct nand_chip *chip = mtd->priv;
48956 + int eccsteps = chip->ecc.steps;
48957 + int eccsize = chip->ecc.size;
48958 + int eccbytes = chip->ecc.bytes;
48959 + int i , j, stat = 0, ret = 0, flag_read_ecc;
48960 struct elm_errorvec err_vec[ERROR_VECTOR_MAX];
48961 - u_char *ecc_vec = calc_ecc;
48962 - u_char *spare_ecc = read_ecc;
48963 - u_char *erased_ecc_vec;
48964 - enum bch_ecc type;
48965 + u_char *ecc;
48966 bool is_error_reported = false;
48967 + u32 bit_pos, byte_pos, error_max, pos;
48968
48969 /* Initialize elm error vector to zero */
48970 memset(err_vec, 0, sizeof(err_vec));
48971 -
48972 - if (info->nand.ecc.strength == BCH8_MAX_ERROR) {
48973 - type = BCH8_ECC;
48974 - erased_ecc_vec = bch8_vector;
48975 - } else {
48976 - type = BCH4_ECC;
48977 - erased_ecc_vec = bch4_vector;
48978 - }
48979 -
48980 - ecc_vector_size = info->nand.ecc.bytes;
48981 -
48982 - /*
48983 - * Remove extra byte padding for BCH8 RBL
48984 - * compatibility and erased page handling
48985 - */
48986 - eccsize = ecc_vector_size - 1;
48987 -
48988 for (i = 0; i < eccsteps ; i++) {
48989 - eccflag = 0; /* initialize eccflag */
48990 -
48991 - /*
48992 - * Check any error reported,
48993 - * In case of error, non zero ecc reported.
48994 - */
48995 -
48996 - for (j = 0; (j < eccsize); j++) {
48997 - if (calc_ecc[j] != 0) {
48998 - eccflag = 1; /* non zero ecc, error present */
48999 + flag_read_ecc = 0;
49000 + ecc = calc_ecc + (i * eccbytes);
49001 + /* check calc_ecc */
49002 + for (j = 0; j < eccbytes; j++) {
49003 + if (*(ecc + j) != 0x00) {
49004 + flag_read_ecc = 1;
49005 break;
49006 }
49007 }
49008 -
49009 - if (eccflag == 1) {
49010 - /*
49011 - * Set threshold to minimum of 4, half of ecc.strength/2
49012 - * to allow max bit flip in byte to 4
49013 - */
49014 - unsigned int threshold = min_t(unsigned int, 4,
49015 - info->nand.ecc.strength / 2);
49016 -
49017 - /*
49018 - * Check data area is programmed by counting
49019 - * number of 0's at fixed offset in spare area.
49020 - * Checking count of 0's against threshold.
49021 - * In case programmed page expects at least threshold
49022 - * zeros in byte.
49023 - * If zeros are less than threshold for programmed page/
49024 - * zeros are more than threshold erased page, either
49025 - * case page reported as uncorrectable.
49026 - */
49027 - if (hweight8(~read_ecc[eccsize]) >= threshold) {
49028 - /*
49029 - * Update elm error vector as
49030 - * data area is programmed
49031 - */
49032 - err_vec[i].error_reported = true;
49033 - is_error_reported = true;
49034 - } else {
49035 - /* Error reported in erased page */
49036 - int bitflip_count;
49037 - u_char *buf = &data[info->nand.ecc.size * i];
49038 -
49039 - if (memcmp(calc_ecc, erased_ecc_vec, eccsize)) {
49040 - bitflip_count = erased_sector_bitflips(
49041 - buf, read_ecc, info);
49042 -
49043 - if (bitflip_count)
49044 - stat += bitflip_count;
49045 - else
49046 - return -EINVAL;
49047 - }
49048 + /* check if its a erased-page */
49049 + if (flag_read_ecc) {
49050 + switch (ecc_opt) {
49051 + case OMAP_ECC_BCH4_CODE_HW:
49052 + if (memcmp(ecc, bch4_vector, eccbytes))
49053 + err_vec[i].error_reported = true;
49054 + break;
49055 + case OMAP_ECC_BCH8_CODE_HW:
49056 + if (memcmp(ecc, bch8_vector, eccbytes))
49057 + err_vec[i].error_reported = true;
49058 + break;
49059 + case OMAP_ECC_BCH16_CODE_HW:
49060 + if (memcmp(ecc, bch16_vector, eccbytes))
49061 + err_vec[i].error_reported = true;
49062 + break;
49063 + default:
49064 + pr_err("%s: invalid configuration",
49065 + DRIVER_NAME);
49066 + return -EINVAL;
49067 }
49068 }
49069 -
49070 - /* Update the ecc vector */
49071 - calc_ecc += ecc_vector_size;
49072 - read_ecc += ecc_vector_size;
49073 + /* page definitely has bit-flips */
49074 + if (err_vec[i].error_reported)
49075 + is_error_reported = true;
49076 }
49077
49078 - /* Check if any error reported */
49079 if (!is_error_reported)
49080 return 0;
49081 + /* detect bit-flips using ELM module */
49082 + elm_decode_bch_error_page(info->elm_dev, calc_ecc, err_vec);
49083
49084 - /* Decode BCH error using ELM module */
49085 - elm_decode_bch_error_page(info->elm_dev, ecc_vec, err_vec);
49086 -
49087 + /* correct bit-flip */
49088 for (i = 0; i < eccsteps; i++) {
49089 - if (err_vec[i].error_reported) {
49090 + if (err_vec[i].error_uncorrectable) {
49091 + ret = -EBADMSG;
49092 + } else if (err_vec[i].error_reported) {
49093 for (j = 0; j < err_vec[i].error_count; j++) {
49094 - u32 bit_pos, byte_pos, error_max, pos;
49095 -
49096 - if (type == BCH8_ECC)
49097 - error_max = BCH8_ECC_MAX;
49098 - else
49099 - error_max = BCH4_ECC_MAX;
49100 -
49101 - if (info->nand.ecc.strength == BCH8_MAX_ERROR)
49102 - pos = err_vec[i].error_loc[j];
49103 - else
49104 + switch (ecc_opt) {
49105 + case OMAP_ECC_BCH4_CODE_HW:
49106 + error_max = SECTOR_BYTES +
49107 + (eccbytes - 1);
49108 /* Add 4 to take care 4 bit padding */
49109 pos = err_vec[i].error_loc[j] +
49110 - BCH4_BIT_PAD;
49111 -
49112 - /* Calculate bit position of error */
49113 + BCH4_BIT_PAD;
49114 + break;
49115 + case OMAP_ECC_BCH8_CODE_HW:
49116 + error_max = SECTOR_BYTES +
49117 + (eccbytes - 1);
49118 + pos = err_vec[i].error_loc[j];
49119 + break;
49120 + case OMAP_ECC_BCH16_CODE_HW:
49121 + error_max = SECTOR_BYTES + eccbytes;
49122 + pos = err_vec[i].error_loc[j];
49123 + break;
49124 + default:
49125 + return -EINVAL;
49126 + }
49127 + /* Calculate bit & byte bit-flip position */
49128 bit_pos = pos % 8;
49129 -
49130 - /* Calculate byte position of error */
49131 - byte_pos = (error_max - pos - 1) / 8;
49132 -
49133 - if (pos < error_max) {
49134 - if (byte_pos < 512)
49135 - data[byte_pos] ^= 1 << bit_pos;
49136 - else
49137 - spare_ecc[byte_pos - 512] ^=
49138 + byte_pos = error_max - (pos / 8) - 1;
49139 + if (byte_pos < SECTOR_BYTES)
49140 + data[byte_pos] ^= 1 << bit_pos;
49141 + else if (byte_pos < error_max)
49142 + read_ecc[byte_pos - SECTOR_BYTES] ^=
49143 1 << bit_pos;
49144 - }
49145 - /* else, not interested to correct ecc */
49146 + else
49147 + ret = -EBADMSG;
49148 }
49149 }
49150 -
49151 /* Update number of correctable errors */
49152 stat += err_vec[i].error_count;
49153 -
49154 /* Update page data with sector size */
49155 - data += info->nand.ecc.size;
49156 - spare_ecc += ecc_vector_size;
49157 + data += eccsize;
49158 + read_ecc += eccbytes;
49159 }
49160
49161 - for (i = 0; i < eccsteps; i++)
49162 - /* Return error if uncorrectable error present */
49163 - if (err_vec[i].error_uncorrectable)
49164 - return -EINVAL;
49165 -
49166 - return stat;
49167 -}
49168 -
49169 -/**
49170 - * omap3_correct_data_bch - Decode received data and correct errors
49171 - * @mtd: MTD device structure
49172 - * @data: page data
49173 - * @read_ecc: ecc read from nand flash
49174 - * @calc_ecc: ecc read from HW ECC registers
49175 - */
49176 -static int omap3_correct_data_bch(struct mtd_info *mtd, u_char *data,
49177 - u_char *read_ecc, u_char *calc_ecc)
49178 -{
49179 - int i, count;
49180 - /* cannot correct more than 8 errors */
49181 - unsigned int errloc[8];
49182 - struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
49183 - mtd);
49184 -
49185 - count = decode_bch(info->bch, NULL, 512, read_ecc, calc_ecc, NULL,
49186 - errloc);
49187 - if (count > 0) {
49188 - /* correct errors */
49189 - for (i = 0; i < count; i++) {
49190 - /* correct data only, not ecc bytes */
49191 - if (errloc[i] < 8*512)
49192 - data[errloc[i]/8] ^= 1 << (errloc[i] & 7);
49193 - pr_debug("corrected bitflip %u\n", errloc[i]);
49194 - }
49195 - } else if (count < 0) {
49196 - pr_err("ecc unrecoverable error\n");
49197 - }
49198 - return count;
49199 + return (ret < 0) ? ret : stat;
49200 }
49201
49202 /**
49203 @@ -1637,186 +1449,30 @@ static int omap_read_page_bch(struct mtd
49204 }
49205
49206 /**
49207 - * omap3_free_bch - Release BCH ecc resources
49208 - * @mtd: MTD device structure
49209 - */
49210 -static void omap3_free_bch(struct mtd_info *mtd)
49211 -{
49212 - struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
49213 - mtd);
49214 - if (info->bch) {
49215 - free_bch(info->bch);
49216 - info->bch = NULL;
49217 - }
49218 -}
49219 -
49220 -/**
49221 - * omap3_init_bch - Initialize BCH ECC
49222 - * @mtd: MTD device structure
49223 - * @ecc_opt: OMAP ECC mode (OMAP_ECC_BCH4_CODE_HW or OMAP_ECC_BCH8_CODE_HW)
49224 - */
49225 -static int omap3_init_bch(struct mtd_info *mtd, int ecc_opt)
49226 -{
49227 - int max_errors;
49228 - struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
49229 - mtd);
49230 -#ifdef CONFIG_MTD_NAND_OMAP_BCH8
49231 - const int hw_errors = BCH8_MAX_ERROR;
49232 -#else
49233 - const int hw_errors = BCH4_MAX_ERROR;
49234 -#endif
49235 - enum bch_ecc bch_type;
49236 - const __be32 *parp;
49237 - int lenp;
49238 - struct device_node *elm_node;
49239 -
49240 - info->bch = NULL;
49241 -
49242 - max_errors = (ecc_opt == OMAP_ECC_BCH8_CODE_HW) ?
49243 - BCH8_MAX_ERROR : BCH4_MAX_ERROR;
49244 - if (max_errors != hw_errors) {
49245 - pr_err("cannot configure %d-bit BCH ecc, only %d-bit supported",
49246 - max_errors, hw_errors);
49247 - goto fail;
49248 - }
49249 -
49250 - info->nand.ecc.size = 512;
49251 - info->nand.ecc.hwctl = omap3_enable_hwecc_bch;
49252 - info->nand.ecc.mode = NAND_ECC_HW;
49253 - info->nand.ecc.strength = max_errors;
49254 -
49255 - if (hw_errors == BCH8_MAX_ERROR)
49256 - bch_type = BCH8_ECC;
49257 - else
49258 - bch_type = BCH4_ECC;
49259 -
49260 - /* Detect availability of ELM module */
49261 - parp = of_get_property(info->of_node, "elm_id", &lenp);
49262 - if ((parp == NULL) && (lenp != (sizeof(void *) * 2))) {
49263 - pr_err("Missing elm_id property, fall back to Software BCH\n");
49264 - info->is_elm_used = false;
49265 - } else {
49266 - struct platform_device *pdev;
49267 -
49268 - elm_node = of_find_node_by_phandle(be32_to_cpup(parp));
49269 - pdev = of_find_device_by_node(elm_node);
49270 - info->elm_dev = &pdev->dev;
49271 -
49272 - if (elm_config(info->elm_dev, bch_type) == 0)
49273 - info->is_elm_used = true;
49274 - }
49275 -
49276 - if (info->is_elm_used && (mtd->writesize <= 4096)) {
49277 -
49278 - if (hw_errors == BCH8_MAX_ERROR)
49279 - info->nand.ecc.bytes = BCH8_SIZE;
49280 - else
49281 - info->nand.ecc.bytes = BCH4_SIZE;
49282 -
49283 - info->nand.ecc.correct = omap_elm_correct_data;
49284 - info->nand.ecc.calculate = omap3_calculate_ecc_bch;
49285 - info->nand.ecc.read_page = omap_read_page_bch;
49286 - info->nand.ecc.write_page = omap_write_page_bch;
49287 - } else {
49288 - /*
49289 - * software bch library is only used to detect and
49290 - * locate errors
49291 - */
49292 - info->bch = init_bch(13, max_errors,
49293 - 0x201b /* hw polynomial */);
49294 - if (!info->bch)
49295 - goto fail;
49296 -
49297 - info->nand.ecc.correct = omap3_correct_data_bch;
49298 -
49299 - /*
49300 - * The number of corrected errors in an ecc block that will
49301 - * trigger block scrubbing defaults to the ecc strength (4 or 8)
49302 - * Set mtd->bitflip_threshold here to define a custom threshold.
49303 - */
49304 -
49305 - if (max_errors == 8) {
49306 - info->nand.ecc.bytes = 13;
49307 - info->nand.ecc.calculate = omap3_calculate_ecc_bch8;
49308 - } else {
49309 - info->nand.ecc.bytes = 7;
49310 - info->nand.ecc.calculate = omap3_calculate_ecc_bch4;
49311 - }
49312 - }
49313 -
49314 - pr_info("enabling NAND BCH ecc with %d-bit correction\n", max_errors);
49315 - return 0;
49316 -fail:
49317 - omap3_free_bch(mtd);
49318 - return -1;
49319 -}
49320 -
49321 -/**
49322 - * omap3_init_bch_tail - Build an oob layout for BCH ECC correction.
49323 - * @mtd: MTD device structure
49324 - */
49325 -static int omap3_init_bch_tail(struct mtd_info *mtd)
49326 -{
49327 - int i, steps, offset;
49328 - struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
49329 - mtd);
49330 - struct nand_ecclayout *layout = &info->ecclayout;
49331 -
49332 - /* build oob layout */
49333 - steps = mtd->writesize/info->nand.ecc.size;
49334 - layout->eccbytes = steps*info->nand.ecc.bytes;
49335 -
49336 - /* do not bother creating special oob layouts for small page devices */
49337 - if (mtd->oobsize < 64) {
49338 - pr_err("BCH ecc is not supported on small page devices\n");
49339 - goto fail;
49340 + * is_elm_present - checks for presence of ELM module by scanning DT nodes
49341 + * @omap_nand_info: NAND device structure containing platform data
49342 + * @bch_type: 0x0=BCH4, 0x1=BCH8, 0x2=BCH16
49343 + */
49344 +static int is_elm_present(struct omap_nand_info *info,
49345 + struct device_node *elm_node, enum bch_ecc bch_type)
49346 +{
49347 + struct platform_device *pdev;
49348 + /* check whether elm-id is passed via DT */
49349 + if (!elm_node) {
49350 + pr_err("nand: error: ELM DT node not found\n");
49351 + return -ENODEV;
49352 }
49353 -
49354 - /* reserve 2 bytes for bad block marker */
49355 - if (layout->eccbytes+2 > mtd->oobsize) {
49356 - pr_err("no oob layout available for oobsize %d eccbytes %u\n",
49357 - mtd->oobsize, layout->eccbytes);
49358 - goto fail;
49359 + pdev = of_find_device_by_node(elm_node);
49360 + /* check whether ELM device is registered */
49361 + if (!pdev) {
49362 + pr_err("nand: error: ELM device not found\n");
49363 + return -ENODEV;
49364 }
49365 -
49366 - /* ECC layout compatible with RBL for BCH8 */
49367 - if (info->is_elm_used && (info->nand.ecc.bytes == BCH8_SIZE))
49368 - offset = 2;
49369 - else
49370 - offset = mtd->oobsize - layout->eccbytes;
49371 -
49372 - /* put ecc bytes at oob tail */
49373 - for (i = 0; i < layout->eccbytes; i++)
49374 - layout->eccpos[i] = offset + i;
49375 -
49376 - if (info->is_elm_used && (info->nand.ecc.bytes == BCH8_SIZE))
49377 - layout->oobfree[0].offset = 2 + layout->eccbytes * steps;
49378 - else
49379 - layout->oobfree[0].offset = 2;
49380 -
49381 - layout->oobfree[0].length = mtd->oobsize-2-layout->eccbytes;
49382 - info->nand.ecc.layout = layout;
49383 -
49384 - if (!(info->nand.options & NAND_BUSWIDTH_16))
49385 - info->nand.badblock_pattern = &bb_descrip_flashbased;
49386 + /* ELM module available, now configure it */
49387 + info->elm_dev = &pdev->dev;
49388 + if (elm_config(info->elm_dev, &info->mtd, bch_type))
49389 + return -ENODEV;
49390 return 0;
49391 -fail:
49392 - omap3_free_bch(mtd);
49393 - return -1;
49394 -}
49395 -
49396 -#else
49397 -static int omap3_init_bch(struct mtd_info *mtd, int ecc_opt)
49398 -{
49399 - pr_err("CONFIG_MTD_NAND_OMAP_BCH is not enabled\n");
49400 - return -1;
49401 -}
49402 -static int omap3_init_bch_tail(struct mtd_info *mtd)
49403 -{
49404 - return -1;
49405 -}
49406 -static void omap3_free_bch(struct mtd_info *mtd)
49407 -{
49408 }
49409 #endif /* CONFIG_MTD_NAND_OMAP_BCH */
49410
49411 @@ -1824,10 +1480,13 @@ static int omap_nand_probe(struct platfo
49412 {
49413 struct omap_nand_info *info;
49414 struct omap_nand_platform_data *pdata;
49415 + struct mtd_info *mtd;
49416 + struct nand_chip *chip;
49417 + struct nand_ecclayout *ecclayout;
49418 int err;
49419 - int i, offset;
49420 - dma_cap_mask_t mask;
49421 - unsigned sig;
49422 + int i;
49423 + dma_cap_mask_t mask;
49424 + unsigned sig;
49425 struct resource *res;
49426 struct mtd_part_parser_data ppdata = {};
49427
49428 @@ -1846,20 +1505,22 @@ static int omap_nand_probe(struct platfo
49429 spin_lock_init(&info->controller.lock);
49430 init_waitqueue_head(&info->controller.wq);
49431
49432 - info->pdev = pdev;
49433 + mtd = &info->mtd;
49434 + mtd->name = dev_name(&pdev->dev);
49435 + mtd->owner = THIS_MODULE;
49436 + mtd->priv = &info->nand;
49437 + chip = mtd->priv;
49438 + chip->ecc.priv = NULL;
49439
49440 + info->pdev = pdev;
49441 info->gpmc_cs = pdata->cs;
49442 info->reg = pdata->reg;
49443 + info->ecc_opt = pdata->ecc_opt;
49444
49445 - info->mtd.priv = &info->nand;
49446 - info->mtd.name = dev_name(&pdev->dev);
49447 - info->mtd.owner = THIS_MODULE;
49448 -
49449 - info->nand.options = pdata->devsize;
49450 + info->nand.options = NAND_BUSWIDTH_AUTO;
49451 info->nand.options |= NAND_SKIP_BBTSCAN;
49452 -#ifdef CONFIG_MTD_NAND_OMAP_BCH
49453 info->of_node = pdata->of_node;
49454 -#endif
49455 +
49456
49457 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
49458 if (res == NULL) {
49459 @@ -1903,6 +1564,30 @@ static int omap_nand_probe(struct platfo
49460 info->nand.chip_delay = 50;
49461 }
49462
49463 + /* scan NAND device conncted to controller */
49464 + if (nand_scan_ident(mtd, 1, NULL)) {
49465 + err = -ENXIO;
49466 + goto out_release_mem_region;
49467 + }
49468 + pr_info("%s: detected %s NAND flash\n", DRIVER_NAME,
49469 + (info->nand.options & NAND_BUSWIDTH_16) ? "x16" : "x8");
49470 + if ((info->nand.options & NAND_BUSWIDTH_16) !=
49471 + (pdata->devsize & NAND_BUSWIDTH_16)) {
49472 + pr_err("%s: but incorrectly configured as %s", DRIVER_NAME,
49473 + (pdata->devsize & NAND_BUSWIDTH_16) ? "x16" : "x8");
49474 + err = -EINVAL;
49475 + goto out_release_mem_region;
49476 + }
49477 +
49478 + /* check for small page devices */
49479 + if ((mtd->oobsize < 64) &&
49480 + (pdata->ecc_opt != OMAP_ECC_HAMMING_CODE_HW)) {
49481 + pr_err("small page devices are not supported\n");
49482 + err = -EINVAL;
49483 + goto out_release_mem_region;
49484 + }
49485 +
49486 + /* populate read & write API based on xfer_type selected */
49487 switch (pdata->xfer_type) {
49488 case NAND_OMAP_PREFETCH_POLLED:
49489 info->nand.read_buf = omap_read_buf_pref;
49490 @@ -1992,64 +1677,218 @@ static int omap_nand_probe(struct platfo
49491 goto out_release_mem_region;
49492 }
49493
49494 - /* select the ecc type */
49495 - if (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_DEFAULT)
49496 - info->nand.ecc.mode = NAND_ECC_SOFT;
49497 - else if ((pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_HW) ||
49498 - (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_HW_ROMCODE)) {
49499 + /* populate MTD interface based on ECC scheme */
49500 + chip->ecclayout = &omap_oobinfo;
49501 + chip->ecc.layout = &omap_oobinfo;
49502 + ecclayout = &omap_oobinfo;
49503 + switch (pdata->ecc_opt) {
49504 + case OMAP_ECC_HAMMING_CODE_HW:
49505 + pr_info("nand: using OMAP_ECC_HAMMING_CODE_HW\n");
49506 + info->nand.ecc.mode = NAND_ECC_HW;
49507 info->nand.ecc.bytes = 3;
49508 info->nand.ecc.size = 512;
49509 info->nand.ecc.strength = 1;
49510 info->nand.ecc.calculate = omap_calculate_ecc;
49511 info->nand.ecc.hwctl = omap_enable_hwecc;
49512 info->nand.ecc.correct = omap_correct_data;
49513 - info->nand.ecc.mode = NAND_ECC_HW;
49514 - } else if ((pdata->ecc_opt == OMAP_ECC_BCH4_CODE_HW) ||
49515 - (pdata->ecc_opt == OMAP_ECC_BCH8_CODE_HW)) {
49516 - err = omap3_init_bch(&info->mtd, pdata->ecc_opt);
49517 - if (err) {
49518 + /* define custom ECC layout */
49519 + ecclayout->eccbytes = info->nand.ecc.bytes *
49520 + (mtd->writesize /
49521 + info->nand.ecc.size);
49522 + if (info->nand.options & NAND_BUSWIDTH_16)
49523 + ecclayout->eccpos[0] = BADBLOCK_MARKER_LENGTH;
49524 + else
49525 + ecclayout->eccpos[0] = 1;
49526 + ecclayout->oobfree->offset = ecclayout->eccpos[0] +
49527 + ecclayout->eccbytes;
49528 + goto custom_ecc_layout;
49529 + break;
49530 + case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW:
49531 +#ifdef CONFIG_MTD_NAND_ECC_BCH
49532 + pr_info("nand: using OMAP_ECC_BCH4_CODE_HW_DETECTION_SW\n");
49533 + info->nand.ecc.mode = NAND_ECC_HW;
49534 + info->nand.ecc.size = 512;
49535 + info->nand.ecc.bytes = 7;
49536 + info->nand.ecc.strength = 4;
49537 + info->nand.ecc.hwctl = omap_enable_hwecc;
49538 + info->nand.ecc.correct = nand_bch_correct_data;
49539 + info->nand.ecc.calculate = omap_calculate_ecc_bch;
49540 + /* define custom ECC layout */
49541 + ecclayout->eccbytes = info->nand.ecc.bytes *
49542 + (mtd->writesize /
49543 + info->nand.ecc.size);
49544 + ecclayout->eccpos[0] = info->mtd.oobsize -
49545 + ecclayout->eccbytes;
49546 + ecclayout->oobfree->offset = BADBLOCK_MARKER_LENGTH;
49547 + /* software bch library is used for locating errors */
49548 + info->nand.ecc.priv = nand_bch_init(mtd,
49549 + info->nand.ecc.size,
49550 + info->nand.ecc.bytes,
49551 + &info->nand.ecc.layout);
49552 + if (!info->nand.ecc.priv) {
49553 + pr_err("nand: error: unable to use s/w BCH library\n");
49554 err = -EINVAL;
49555 goto out_release_mem_region;
49556 }
49557 - }
49558 -
49559 - /* DIP switches on some boards change between 8 and 16 bit
49560 - * bus widths for flash. Try the other width if the first try fails.
49561 - */
49562 - if (nand_scan_ident(&info->mtd, 1, NULL)) {
49563 - info->nand.options ^= NAND_BUSWIDTH_16;
49564 - if (nand_scan_ident(&info->mtd, 1, NULL)) {
49565 - err = -ENXIO;
49566 + goto custom_ecc_layout;
49567 +#else
49568 + pr_err("nand: error: CONFIG_MTD_NAND_ECC_BCH not enabled\n");
49569 + err = -EINVAL;
49570 + goto out_release_mem_region;
49571 +#endif
49572 + break;
49573 + case OMAP_ECC_BCH4_CODE_HW:
49574 +#ifdef CONFIG_MTD_NAND_OMAP_BCH
49575 + pr_info("nand: using OMAP_ECC_BCH4_CODE_HW ECC scheme\n");
49576 + info->nand.ecc.mode = NAND_ECC_HW;
49577 + info->nand.ecc.size = 512;
49578 + /* 14th bit is kept reserved for ROM-code compatibility */
49579 + info->nand.ecc.bytes = 7 + 1;
49580 + info->nand.ecc.strength = 4;
49581 + info->nand.ecc.hwctl = omap_enable_hwecc;
49582 + info->nand.ecc.correct = omap_elm_correct_data;
49583 + info->nand.ecc.calculate = omap_calculate_ecc_bch;
49584 + info->nand.ecc.read_page = omap_read_page_bch;
49585 + info->nand.ecc.write_page = omap_write_page_bch;
49586 + /* This ECC scheme requires ELM H/W block */
49587 + if (is_elm_present(info, pdata->elm_of_node, BCH4_ECC) < 0) {
49588 + pr_err("nand: error: could not initialize ELM\n");
49589 + err = -ENODEV;
49590 goto out_release_mem_region;
49591 }
49592 - }
49593 -
49594 - /* rom code layout */
49595 - if (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_HW_ROMCODE) {
49596 -
49597 - if (info->nand.options & NAND_BUSWIDTH_16)
49598 - offset = 2;
49599 - else {
49600 - offset = 1;
49601 - info->nand.badblock_pattern = &bb_descrip_flashbased;
49602 - }
49603 - omap_oobinfo.eccbytes = 3 * (info->mtd.oobsize/16);
49604 - for (i = 0; i < omap_oobinfo.eccbytes; i++)
49605 - omap_oobinfo.eccpos[i] = i+offset;
49606 -
49607 - omap_oobinfo.oobfree->offset = offset + omap_oobinfo.eccbytes;
49608 - omap_oobinfo.oobfree->length = info->mtd.oobsize -
49609 - (offset + omap_oobinfo.eccbytes);
49610 -
49611 - info->nand.ecc.layout = &omap_oobinfo;
49612 - } else if ((pdata->ecc_opt == OMAP_ECC_BCH4_CODE_HW) ||
49613 - (pdata->ecc_opt == OMAP_ECC_BCH8_CODE_HW)) {
49614 - /* build OOB layout for BCH ECC correction */
49615 - err = omap3_init_bch_tail(&info->mtd);
49616 - if (err) {
49617 + /* define custom ECC layout */
49618 + ecclayout->eccbytes = info->nand.ecc.bytes *
49619 + (mtd->writesize /
49620 + info->nand.ecc.size);
49621 + ecclayout->eccpos[0] = BADBLOCK_MARKER_LENGTH;
49622 + ecclayout->oobfree->offset = ecclayout->eccpos[0] +
49623 + ecclayout->eccbytes;
49624 + goto custom_ecc_layout;
49625 +#else
49626 + pr_err("nand: error: CONFIG_MTD_NAND_OMAP_BCH not enabled\n");
49627 + err = -EINVAL;
49628 + goto out_release_mem_region;
49629 +#endif
49630 + break;
49631 + case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
49632 +#ifdef CONFIG_MTD_NAND_ECC_BCH
49633 + pr_info("nand: using OMAP_ECC_BCH8_CODE_HW_DETECTION_SW\n");
49634 + info->nand.ecc.mode = NAND_ECC_HW;
49635 + info->nand.ecc.size = 512;
49636 + info->nand.ecc.bytes = 13;
49637 + info->nand.ecc.strength = 8;
49638 + info->nand.ecc.hwctl = omap_enable_hwecc;
49639 + info->nand.ecc.correct = nand_bch_correct_data;
49640 + info->nand.ecc.calculate = omap_calculate_ecc_bch;
49641 + /* define custom ECC layout */
49642 + ecclayout->eccbytes = info->nand.ecc.bytes *
49643 + (mtd->writesize /
49644 + info->nand.ecc.size);
49645 + ecclayout->eccpos[0] = info->mtd.oobsize -
49646 + ecclayout->eccbytes;
49647 + ecclayout->oobfree->offset = BADBLOCK_MARKER_LENGTH;
49648 + /* software bch library is used for locating errors */
49649 + info->nand.ecc.priv = nand_bch_init(mtd,
49650 + info->nand.ecc.size,
49651 + info->nand.ecc.bytes,
49652 + &info->nand.ecc.layout);
49653 + if (!info->nand.ecc.priv) {
49654 + pr_err("nand: error: unable to use s/w BCH library\n");
49655 err = -EINVAL;
49656 goto out_release_mem_region;
49657 }
49658 + goto custom_ecc_layout;
49659 +#else
49660 + pr_err("nand: error: CONFIG_MTD_NAND_ECC_BCH not enabled\n");
49661 + err = -EINVAL;
49662 + goto out_release_mem_region;
49663 +#endif
49664 + break;
49665 + case OMAP_ECC_BCH8_CODE_HW:
49666 +#ifdef CONFIG_MTD_NAND_OMAP_BCH
49667 + pr_info("nand: using OMAP_ECC_BCH8_CODE_HW ECC scheme\n");
49668 + info->nand.ecc.mode = NAND_ECC_HW;
49669 + info->nand.ecc.size = 512;
49670 + /* 14th bit is kept reserved for ROM-code compatibility */
49671 + info->nand.ecc.bytes = 13 + 1;
49672 + info->nand.ecc.strength = 8;
49673 + info->nand.ecc.hwctl = omap_enable_hwecc;
49674 + info->nand.ecc.correct = omap_elm_correct_data;
49675 + info->nand.ecc.calculate = omap_calculate_ecc_bch;
49676 + info->nand.ecc.read_page = omap_read_page_bch;
49677 + info->nand.ecc.write_page = omap_write_page_bch;
49678 + /* This ECC scheme requires ELM H/W block */
49679 + if (is_elm_present(info, pdata->elm_of_node, BCH8_ECC) < 0) {
49680 + pr_err("nand: error: could not initialize ELM\n");
49681 + err = -ENODEV;
49682 + goto out_release_mem_region;
49683 + }
49684 + /* define custom ECC layout */
49685 + ecclayout->eccbytes = info->nand.ecc.bytes *
49686 + (mtd->writesize /
49687 + info->nand.ecc.size);
49688 + ecclayout->eccpos[0] = BADBLOCK_MARKER_LENGTH;
49689 + ecclayout->oobfree->offset = ecclayout->eccpos[0] +
49690 + ecclayout->eccbytes;
49691 + goto custom_ecc_layout;
49692 +#else
49693 + pr_err("nand: error: CONFIG_MTD_NAND_OMAP_BCH not enabled\n");
49694 + err = -EINVAL;
49695 + goto out_release_mem_region;
49696 +#endif
49697 + break;
49698 + case OMAP_ECC_BCH16_CODE_HW:
49699 +#ifdef CONFIG_MTD_NAND_OMAP_BCH
49700 + pr_info("using OMAP_ECC_BCH16_CODE_HW ECC scheme\n");
49701 + chip->ecc.mode = NAND_ECC_HW;
49702 + chip->ecc.size = 512;
49703 + /* 14th bit is kept reserved for ROM-code compatibility */
49704 + chip->ecc.bytes = 26;
49705 + chip->ecc.strength = 16;
49706 + chip->ecc.hwctl = omap_enable_hwecc;
49707 + chip->ecc.correct = omap_elm_correct_data;
49708 + chip->ecc.calculate = omap_calculate_ecc_bch;
49709 + chip->ecc.read_page = omap_read_page_bch;
49710 + chip->ecc.write_page = omap_write_page_bch;
49711 + /* ELM H/W engine is used for locating errors */
49712 + if (is_elm_present(info, pdata->elm_of_node, BCH16_ECC) < 0) {
49713 + pr_err("ELM module not detected, required for ECC\n");
49714 + err = -EINVAL;
49715 + goto out_release_mem_region;
49716 + }
49717 + /* define custom ECC layout */
49718 + omap_oobinfo.eccbytes = chip->ecc.bytes *
49719 + (mtd->writesize / chip->ecc.size);
49720 + omap_oobinfo.eccpos[0] = BADBLOCK_MARKER_LENGTH;
49721 + omap_oobinfo.oobfree->offset = omap_oobinfo.eccpos[0] +
49722 + omap_oobinfo.eccbytes;
49723 + goto custom_ecc_layout;
49724 +#else
49725 + pr_err("nand: error: CONFIG_MTD_NAND_OMAP_BCH not enabled\n");
49726 + err = -EINVAL;
49727 + goto out_release_mem_region;
49728 +#endif
49729 + default:
49730 + pr_err("nand: error: invalid or unsupported ECC scheme\n");
49731 + err = -EINVAL;
49732 + goto out_release_mem_region;
49733 + }
49734 +
49735 +custom_ecc_layout:
49736 + /* populate remaining info for custom ecc layout */
49737 + pr_info("%s: using custom ecc layout\n", DRIVER_NAME);
49738 + ecclayout->oobfree->length = mtd->oobsize - BADBLOCK_MARKER_LENGTH
49739 + - ecclayout->eccbytes;
49740 + if (!(info->nand.options & NAND_BUSWIDTH_16))
49741 + info->nand.badblock_pattern = &bb_descrip_flashbased;
49742 + for (i = 1; i < ecclayout->eccbytes; i++)
49743 + ecclayout->eccpos[i] = ecclayout->eccpos[0] + i;
49744 + /* check if NAND OOBSIZE meets ECC scheme requirement */
49745 + if (mtd->oobsize < (ecclayout->eccbytes + BADBLOCK_MARKER_LENGTH)) {
49746 + pr_err("not enough OOB bytes required = %d, available=%d\n",
49747 + ecclayout->eccbytes, mtd->oobsize);
49748 + err = -EINVAL;
49749 + goto out_release_mem_region;
49750 }
49751
49752 /* second phase scan */
49753 @@ -2074,7 +1913,14 @@ out_release_mem_region:
49754 if (info->gpmc_irq_fifo > 0)
49755 free_irq(info->gpmc_irq_fifo, info);
49756 release_mem_region(info->phys_base, info->mem_size);
49757 +
49758 out_free_info:
49759 +#ifdef CONFIG_MTD_NAND_ECC_BCH
49760 + if (info->nand.ecc.priv) {
49761 + nand_bch_free(info->nand.ecc.priv);
49762 + info->nand.ecc.priv = NULL;
49763 + }
49764 +#endif
49765 kfree(info);
49766
49767 return err;
49768 @@ -2085,8 +1931,12 @@ static int omap_nand_remove(struct platf
49769 struct mtd_info *mtd = platform_get_drvdata(pdev);
49770 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
49771 mtd);
49772 - omap3_free_bch(&info->mtd);
49773 -
49774 +#ifdef CONFIG_MTD_NAND_ECC_BCH
49775 + if (info->nand.ecc.priv) {
49776 + nand_bch_free(info->nand.ecc.priv);
49777 + info->nand.ecc.priv = NULL;
49778 + }
49779 +#endif
49780 if (info->dma)
49781 dma_release_channel(info->dma);
49782
49783 --- a/drivers/mtd/tests/oobtest.c
49784 +++ b/drivers/mtd/tests/oobtest.c
49785 @@ -210,11 +210,29 @@ static int verify_eraseblock(int ebnum)
49786 static int verify_eraseblock_in_one_go(int ebnum)
49787 {
49788 struct mtd_oob_ops ops;
49789 - int err = 0;
49790 + int i, err = 0;
49791 loff_t addr = ebnum * mtd->erasesize;
49792 size_t len = mtd->ecclayout->oobavail * pgcnt;
49793
49794 - prandom_bytes_state(&rnd_state, writebuf, len);
49795 + /*
49796 + * if mtd->ecclayout->oobavail is not a multiple of 4 then
49797 + * while generating psuedo random numbers to write to flash
49798 + * prandom_bytes_state () generates the extra random bytes
49799 + * which wont be done if we do for the whole length. So check
49800 + * for mtd->ecclayout->oobavail if its multiple of 4 then
49801 + * generate for full len (mtd->ecclayout->oobavail * pgcnt)
49802 + * else generate prandom of mtd->ecclayout->oobavail bytes
49803 + * pgcnt times.
49804 + */
49805 +
49806 + if (mtd->ecclayout->oobavail % sizeof(u32)) {
49807 + for (i = 0; i < len; i += mtd->ecclayout->oobavail)
49808 + prandom_bytes_state(&rnd_state, writebuf + i,
49809 + mtd->ecclayout->oobavail);
49810 + } else {
49811 + prandom_bytes_state(&rnd_state, writebuf, len);
49812 + }
49813 +
49814 ops.mode = MTD_OPS_AUTO_OOB;
49815 ops.len = 0;
49816 ops.retlen = 0;
49817 @@ -266,7 +284,7 @@ static int verify_all_eraseblocks(void)
49818 static int __init mtd_oobtest_init(void)
49819 {
49820 int err = 0;
49821 - unsigned int i;
49822 + unsigned int i, j;
49823 uint64_t tmp;
49824 struct mtd_oob_ops ops;
49825 loff_t addr = 0, addr0;
49826 @@ -341,7 +359,6 @@ static int __init mtd_oobtest_init(void)
49827 err = verify_all_eraseblocks();
49828 if (err)
49829 goto out;
49830 -
49831 /*
49832 * Second test: write all OOB, a block at a time, read it back and
49833 * verify.
49834 @@ -591,10 +608,26 @@ static int __init mtd_oobtest_init(void)
49835 prandom_seed_state(&rnd_state, 11);
49836 pr_info("verifying all eraseblocks\n");
49837 for (i = 0; i < ebcnt - 1; ++i) {
49838 + size_t sz = mtd->ecclayout->oobavail;
49839 if (bbt[i] || bbt[i + 1])
49840 continue;
49841 - prandom_bytes_state(&rnd_state, writebuf,
49842 - mtd->ecclayout->oobavail * 2);
49843 + /*
49844 + * if mtd->ecclayout->oobavail is not a multiple of 4 then
49845 + * while generating psuedo random numbers to write to flash
49846 + * prandom_bytes_state () generates the extra random bytes
49847 + * which wont be done if we do for the whole length. So check
49848 + * for mtd->ecclayout->oobavail if its multiple of 4 then
49849 + * generate for full len (mtd->ecclayout->oobavail * pgcnt)
49850 + * else generate prandom of mtd->ecclayout->oobavail bytes
49851 + * pgcnt times.
49852 + */
49853 + if (sz % sizeof(u32)) {
49854 + for (j = 0; j < sz * 2; j += sz)
49855 + prandom_bytes_state(&rnd_state,
49856 + writebuf + j , sz);
49857 + } else {
49858 + prandom_bytes_state(&rnd_state, writebuf, sz * 2);
49859 + }
49860 addr = (i + 1) * mtd->erasesize - mtd->writesize;
49861 ops.mode = MTD_OPS_AUTO_OOB;
49862 ops.len = 0;
49863 --- a/drivers/net/ethernet/ti/cpsw.c
49864 +++ b/drivers/net/ethernet/ti/cpsw.c
49865 @@ -367,8 +367,6 @@ struct cpsw_priv {
49866 spinlock_t lock;
49867 struct platform_device *pdev;
49868 struct net_device *ndev;
49869 - struct resource *cpsw_res;
49870 - struct resource *cpsw_wr_res;
49871 struct napi_struct napi;
49872 struct device *dev;
49873 struct cpsw_platform_data data;
49874 @@ -1016,6 +1014,10 @@ static void cpsw_slave_open(struct cpsw_
49875 dev_info(priv->dev, "phy found : id is : 0x%x\n",
49876 slave->phy->phy_id);
49877 phy_start(slave->phy);
49878 +
49879 + /* Configure GMII_SEL register */
49880 + cpsw_phy_sel(&priv->pdev->dev, slave->phy->interface,
49881 + slave->slave_num);
49882 }
49883 }
49884
49885 @@ -1705,62 +1707,55 @@ static int cpsw_probe_dt(struct cpsw_pla
49886
49887 if (of_property_read_u32(node, "active_slave", &prop)) {
49888 pr_err("Missing active_slave property in the DT.\n");
49889 - ret = -EINVAL;
49890 - goto error_ret;
49891 + return -EINVAL;
49892 }
49893 data->active_slave = prop;
49894
49895 if (of_property_read_u32(node, "cpts_clock_mult", &prop)) {
49896 pr_err("Missing cpts_clock_mult property in the DT.\n");
49897 - ret = -EINVAL;
49898 - goto error_ret;
49899 + return -EINVAL;
49900 }
49901 data->cpts_clock_mult = prop;
49902
49903 if (of_property_read_u32(node, "cpts_clock_shift", &prop)) {
49904 pr_err("Missing cpts_clock_shift property in the DT.\n");
49905 - ret = -EINVAL;
49906 - goto error_ret;
49907 + return -EINVAL;
49908 }
49909 data->cpts_clock_shift = prop;
49910
49911 - data->slave_data = kcalloc(data->slaves, sizeof(struct cpsw_slave_data),
49912 - GFP_KERNEL);
49913 + data->slave_data = devm_kzalloc(&pdev->dev, data->slaves
49914 + * sizeof(struct cpsw_slave_data),
49915 + GFP_KERNEL);
49916 if (!data->slave_data)
49917 - return -EINVAL;
49918 + return -ENOMEM;
49919
49920 if (of_property_read_u32(node, "cpdma_channels", &prop)) {
49921 pr_err("Missing cpdma_channels property in the DT.\n");
49922 - ret = -EINVAL;
49923 - goto error_ret;
49924 + return -EINVAL;
49925 }
49926 data->channels = prop;
49927
49928 if (of_property_read_u32(node, "ale_entries", &prop)) {
49929 pr_err("Missing ale_entries property in the DT.\n");
49930 - ret = -EINVAL;
49931 - goto error_ret;
49932 + return -EINVAL;
49933 }
49934 data->ale_entries = prop;
49935
49936 if (of_property_read_u32(node, "bd_ram_size", &prop)) {
49937 pr_err("Missing bd_ram_size property in the DT.\n");
49938 - ret = -EINVAL;
49939 - goto error_ret;
49940 + return -EINVAL;
49941 }
49942 data->bd_ram_size = prop;
49943
49944 if (of_property_read_u32(node, "rx_descs", &prop)) {
49945 pr_err("Missing rx_descs property in the DT.\n");
49946 - ret = -EINVAL;
49947 - goto error_ret;
49948 + return -EINVAL;
49949 }
49950 data->rx_descs = prop;
49951
49952 if (of_property_read_u32(node, "mac_control", &prop)) {
49953 pr_err("Missing mac_control property in the DT.\n");
49954 - ret = -EINVAL;
49955 - goto error_ret;
49956 + return -EINVAL;
49957 }
49958 data->mac_control = prop;
49959
49960 @@ -1791,8 +1786,7 @@ static int cpsw_probe_dt(struct cpsw_pla
49961 parp = of_get_property(slave_node, "phy_id", &lenp);
49962 if ((parp == NULL) || (lenp != (sizeof(void *) * 2))) {
49963 pr_err("Missing slave[%d] phy_id property\n", i);
49964 - ret = -EINVAL;
49965 - goto error_ret;
49966 + return -EINVAL;
49967 }
49968 mdio_node = of_find_node_by_phandle(be32_to_cpup(parp));
49969 phyid = be32_to_cpup(parp+1);
49970 @@ -1822,10 +1816,6 @@ static int cpsw_probe_dt(struct cpsw_pla
49971 }
49972
49973 return 0;
49974 -
49975 -error_ret:
49976 - kfree(data->slave_data);
49977 - return ret;
49978 }
49979
49980 static int cpsw_probe_dual_emac(struct platform_device *pdev,
49981 @@ -1867,7 +1857,6 @@ static int cpsw_probe_dual_emac(struct p
49982 priv_sl2->coal_intvl = 0;
49983 priv_sl2->bus_freq_mhz = priv->bus_freq_mhz;
49984
49985 - priv_sl2->cpsw_res = priv->cpsw_res;
49986 priv_sl2->regs = priv->regs;
49987 priv_sl2->host_port = priv->host_port;
49988 priv_sl2->host_port_regs = priv->host_port_regs;
49989 @@ -1911,8 +1900,8 @@ static int cpsw_probe(struct platform_de
49990 struct cpsw_priv *priv;
49991 struct cpdma_params dma_params;
49992 struct cpsw_ale_params ale_params;
49993 - void __iomem *ss_regs, *wr_regs;
49994 - struct resource *res;
49995 + void __iomem *ss_regs;
49996 + struct resource *res, *ss_res;
49997 u32 slave_offset, sliver_offset, slave_size;
49998 int ret = 0, i, k = 0;
49999
50000 @@ -1948,7 +1937,7 @@ static int cpsw_probe(struct platform_de
50001 if (cpsw_probe_dt(&priv->data, pdev)) {
50002 pr_err("cpsw: platform data missing\n");
50003 ret = -ENODEV;
50004 - goto clean_ndev_ret;
50005 + goto clean_runtime_disable_ret;
50006 }
50007 data = &priv->data;
50008
50009 @@ -1962,11 +1951,12 @@ static int cpsw_probe(struct platform_de
50010
50011 memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
50012
50013 - priv->slaves = kzalloc(sizeof(struct cpsw_slave) * data->slaves,
50014 - GFP_KERNEL);
50015 + priv->slaves = devm_kzalloc(&pdev->dev,
50016 + sizeof(struct cpsw_slave) * data->slaves,
50017 + GFP_KERNEL);
50018 if (!priv->slaves) {
50019 - ret = -EBUSY;
50020 - goto clean_ndev_ret;
50021 + ret = -ENOMEM;
50022 + goto clean_runtime_disable_ret;
50023 }
50024 for (i = 0; i < data->slaves; i++)
50025 priv->slaves[i].slave_num = i;
50026 @@ -1974,55 +1964,31 @@ static int cpsw_probe(struct platform_de
50027 priv->slaves[0].ndev = ndev;
50028 priv->emac_port = 0;
50029
50030 - priv->clk = clk_get(&pdev->dev, "fck");
50031 + priv->clk = devm_clk_get(&pdev->dev, "fck");
50032 if (IS_ERR(priv->clk)) {
50033 - dev_err(&pdev->dev, "fck is not found\n");
50034 + dev_err(priv->dev, "fck is not found\n");
50035 ret = -ENODEV;
50036 - goto clean_slave_ret;
50037 + goto clean_runtime_disable_ret;
50038 }
50039 priv->coal_intvl = 0;
50040 priv->bus_freq_mhz = clk_get_rate(priv->clk) / 1000000;
50041
50042 - priv->cpsw_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
50043 - if (!priv->cpsw_res) {
50044 - dev_err(priv->dev, "error getting i/o resource\n");
50045 - ret = -ENOENT;
50046 - goto clean_clk_ret;
50047 - }
50048 - if (!request_mem_region(priv->cpsw_res->start,
50049 - resource_size(priv->cpsw_res), ndev->name)) {
50050 - dev_err(priv->dev, "failed request i/o region\n");
50051 - ret = -ENXIO;
50052 - goto clean_clk_ret;
50053 - }
50054 - ss_regs = ioremap(priv->cpsw_res->start, resource_size(priv->cpsw_res));
50055 - if (!ss_regs) {
50056 - dev_err(priv->dev, "unable to map i/o region\n");
50057 - goto clean_cpsw_iores_ret;
50058 + ss_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
50059 + ss_regs = devm_ioremap_resource(&pdev->dev, ss_res);
50060 + if (IS_ERR(ss_regs)) {
50061 + ret = PTR_ERR(ss_regs);
50062 + goto clean_runtime_disable_ret;
50063 }
50064 priv->regs = ss_regs;
50065 priv->version = __raw_readl(&priv->regs->id_ver);
50066 priv->host_port = HOST_PORT_NUM;
50067
50068 - priv->cpsw_wr_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
50069 - if (!priv->cpsw_wr_res) {
50070 - dev_err(priv->dev, "error getting i/o resource\n");
50071 - ret = -ENOENT;
50072 - goto clean_iomap_ret;
50073 - }
50074 - if (!request_mem_region(priv->cpsw_wr_res->start,
50075 - resource_size(priv->cpsw_wr_res), ndev->name)) {
50076 - dev_err(priv->dev, "failed request i/o region\n");
50077 - ret = -ENXIO;
50078 - goto clean_iomap_ret;
50079 - }
50080 - wr_regs = ioremap(priv->cpsw_wr_res->start,
50081 - resource_size(priv->cpsw_wr_res));
50082 - if (!wr_regs) {
50083 - dev_err(priv->dev, "unable to map i/o region\n");
50084 - goto clean_cpsw_wr_iores_ret;
50085 + res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
50086 + priv->wr_regs = devm_ioremap_resource(&pdev->dev, res);
50087 + if (IS_ERR(priv->wr_regs)) {
50088 + ret = PTR_ERR(priv->wr_regs);
50089 + goto clean_runtime_disable_ret;
50090 }
50091 - priv->wr_regs = wr_regs;
50092
50093 memset(&dma_params, 0, sizeof(dma_params));
50094 memset(&ale_params, 0, sizeof(ale_params));
50095 @@ -2053,12 +2019,12 @@ static int cpsw_probe(struct platform_de
50096 slave_size = CPSW2_SLAVE_SIZE;
50097 sliver_offset = CPSW2_SLIVER_OFFSET;
50098 dma_params.desc_mem_phys =
50099 - (u32 __force) priv->cpsw_res->start + CPSW2_BD_OFFSET;
50100 + (u32 __force) ss_res->start + CPSW2_BD_OFFSET;
50101 break;
50102 default:
50103 dev_err(priv->dev, "unknown version 0x%08x\n", priv->version);
50104 ret = -ENODEV;
50105 - goto clean_cpsw_wr_iores_ret;
50106 + goto clean_runtime_disable_ret;
50107 }
50108 for (i = 0; i < priv->data.slaves; i++) {
50109 struct cpsw_slave *slave = &priv->slaves[i];
50110 @@ -2086,7 +2052,7 @@ static int cpsw_probe(struct platform_de
50111 if (!priv->dma) {
50112 dev_err(priv->dev, "error initializing dma\n");
50113 ret = -ENOMEM;
50114 - goto clean_wr_iomap_ret;
50115 + goto clean_runtime_disable_ret;
50116 }
50117
50118 priv->txch = cpdma_chan_create(priv->dma, tx_chan_num(0),
50119 @@ -2121,8 +2087,8 @@ static int cpsw_probe(struct platform_de
50120
50121 while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, k))) {
50122 for (i = res->start; i <= res->end; i++) {
50123 - if (request_irq(i, cpsw_interrupt, 0,
50124 - dev_name(&pdev->dev), priv)) {
50125 + if (devm_request_irq(&pdev->dev, i, cpsw_interrupt, 0,
50126 + dev_name(priv->dev), priv)) {
50127 dev_err(priv->dev, "error attaching irq\n");
50128 goto clean_ale_ret;
50129 }
50130 @@ -2144,7 +2110,7 @@ static int cpsw_probe(struct platform_de
50131 if (ret) {
50132 dev_err(priv->dev, "error registering net device\n");
50133 ret = -ENODEV;
50134 - goto clean_irq_ret;
50135 + goto clean_ale_ret;
50136 }
50137
50138 if (cpts_register(&pdev->dev, priv->cpts,
50139 @@ -2152,44 +2118,27 @@ static int cpsw_probe(struct platform_de
50140 dev_err(priv->dev, "error registering cpts device\n");
50141
50142 cpsw_notice(priv, probe, "initialized device (regs %x, irq %d)\n",
50143 - priv->cpsw_res->start, ndev->irq);
50144 + ss_res->start, ndev->irq);
50145
50146 if (priv->data.dual_emac) {
50147 ret = cpsw_probe_dual_emac(pdev, priv);
50148 if (ret) {
50149 cpsw_err(priv, probe, "error probe slave 2 emac interface\n");
50150 - goto clean_irq_ret;
50151 + goto clean_ale_ret;
50152 }
50153 }
50154
50155 return 0;
50156
50157 -clean_irq_ret:
50158 - for (i = 0; i < priv->num_irqs; i++)
50159 - free_irq(priv->irqs_table[i], priv);
50160 clean_ale_ret:
50161 cpsw_ale_destroy(priv->ale);
50162 clean_dma_ret:
50163 cpdma_chan_destroy(priv->txch);
50164 cpdma_chan_destroy(priv->rxch);
50165 cpdma_ctlr_destroy(priv->dma);
50166 -clean_wr_iomap_ret:
50167 - iounmap(priv->wr_regs);
50168 -clean_cpsw_wr_iores_ret:
50169 - release_mem_region(priv->cpsw_wr_res->start,
50170 - resource_size(priv->cpsw_wr_res));
50171 -clean_iomap_ret:
50172 - iounmap(priv->regs);
50173 -clean_cpsw_iores_ret:
50174 - release_mem_region(priv->cpsw_res->start,
50175 - resource_size(priv->cpsw_res));
50176 -clean_clk_ret:
50177 - clk_put(priv->clk);
50178 -clean_slave_ret:
50179 +clean_runtime_disable_ret:
50180 pm_runtime_disable(&pdev->dev);
50181 - kfree(priv->slaves);
50182 clean_ndev_ret:
50183 - kfree(priv->data.slave_data);
50184 free_netdev(priv->ndev);
50185 return ret;
50186 }
50187 @@ -2198,30 +2147,18 @@ static int cpsw_remove(struct platform_d
50188 {
50189 struct net_device *ndev = platform_get_drvdata(pdev);
50190 struct cpsw_priv *priv = netdev_priv(ndev);
50191 - int i;
50192
50193 if (priv->data.dual_emac)
50194 unregister_netdev(cpsw_get_slave_ndev(priv, 1));
50195 unregister_netdev(ndev);
50196
50197 cpts_unregister(priv->cpts);
50198 - for (i = 0; i < priv->num_irqs; i++)
50199 - free_irq(priv->irqs_table[i], priv);
50200
50201 cpsw_ale_destroy(priv->ale);
50202 cpdma_chan_destroy(priv->txch);
50203 cpdma_chan_destroy(priv->rxch);
50204 cpdma_ctlr_destroy(priv->dma);
50205 - iounmap(priv->regs);
50206 - release_mem_region(priv->cpsw_res->start,
50207 - resource_size(priv->cpsw_res));
50208 - iounmap(priv->wr_regs);
50209 - release_mem_region(priv->cpsw_wr_res->start,
50210 - resource_size(priv->cpsw_wr_res));
50211 pm_runtime_disable(&pdev->dev);
50212 - clk_put(priv->clk);
50213 - kfree(priv->slaves);
50214 - kfree(priv->data.slave_data);
50215 if (priv->data.dual_emac)
50216 free_netdev(cpsw_get_slave_ndev(priv, 1));
50217 free_netdev(ndev);
50218 --- a/drivers/net/ethernet/ti/cpsw.h
50219 +++ b/drivers/net/ethernet/ti/cpsw.h
50220 @@ -39,4 +39,6 @@ struct cpsw_platform_data {
50221 bool dual_emac; /* Enable Dual EMAC mode */
50222 };
50223
50224 +void cpsw_phy_sel(struct device *dev, phy_interface_t phy_mode, int slave);
50225 +
50226 #endif /* __CPSW_H__ */
50227 --- /dev/null
50228 +++ b/drivers/net/ethernet/ti/cpsw-phy-sel.c
50229 @@ -0,0 +1,161 @@
50230 +/* Texas Instruments Ethernet Switch Driver
50231 + *
50232 + * Copyright (C) 2013 Texas Instruments
50233 + *
50234 + * This program is free software; you can redistribute it and/or
50235 + * modify it under the terms of the GNU General Public License
50236 + * version 2 as published by the Free Software Foundation.
50237 + *
50238 + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
50239 + * kind, whether express or implied; without even the implied warranty
50240 + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
50241 + * GNU General Public License for more details.
50242 + */
50243 +
50244 +#include <linux/platform_device.h>
50245 +#include <linux/module.h>
50246 +#include <linux/netdevice.h>
50247 +#include <linux/phy.h>
50248 +#include <linux/of.h>
50249 +#include <linux/of_device.h>
50250 +
50251 +#include "cpsw.h"
50252 +
50253 +/* AM33xx SoC specific definitions for the CONTROL port */
50254 +#define AM33XX_GMII_SEL_MODE_MII 0
50255 +#define AM33XX_GMII_SEL_MODE_RMII 1
50256 +#define AM33XX_GMII_SEL_MODE_RGMII 2
50257 +
50258 +#define AM33XX_GMII_SEL_RMII2_IO_CLK_EN BIT(7)
50259 +#define AM33XX_GMII_SEL_RMII1_IO_CLK_EN BIT(6)
50260 +
50261 +struct cpsw_phy_sel_priv {
50262 + struct device *dev;
50263 + u32 __iomem *gmii_sel;
50264 + bool rmii_clock_external;
50265 + void (*cpsw_phy_sel)(struct cpsw_phy_sel_priv *priv,
50266 + phy_interface_t phy_mode, int slave);
50267 +};
50268 +
50269 +
50270 +static void cpsw_gmii_sel_am3352(struct cpsw_phy_sel_priv *priv,
50271 + phy_interface_t phy_mode, int slave)
50272 +{
50273 + u32 reg;
50274 + u32 mask;
50275 + u32 mode = 0;
50276 +
50277 + reg = readl(priv->gmii_sel);
50278 +
50279 + switch (phy_mode) {
50280 + case PHY_INTERFACE_MODE_RMII:
50281 + mode = AM33XX_GMII_SEL_MODE_RMII;
50282 + break;
50283 +
50284 + case PHY_INTERFACE_MODE_RGMII:
50285 + case PHY_INTERFACE_MODE_RGMII_ID:
50286 + case PHY_INTERFACE_MODE_RGMII_RXID:
50287 + case PHY_INTERFACE_MODE_RGMII_TXID:
50288 + mode = AM33XX_GMII_SEL_MODE_RGMII;
50289 + break;
50290 +
50291 + case PHY_INTERFACE_MODE_MII:
50292 + default:
50293 + mode = AM33XX_GMII_SEL_MODE_MII;
50294 + break;
50295 + };
50296 +
50297 + mask = 0x3 << (slave * 2) | BIT(slave + 6);
50298 + mode <<= slave * 2;
50299 +
50300 + if (priv->rmii_clock_external) {
50301 + if (slave == 0)
50302 + mode |= AM33XX_GMII_SEL_RMII1_IO_CLK_EN;
50303 + else
50304 + mode |= AM33XX_GMII_SEL_RMII2_IO_CLK_EN;
50305 + }
50306 +
50307 + reg &= ~mask;
50308 + reg |= mode;
50309 +
50310 + writel(reg, priv->gmii_sel);
50311 +}
50312 +
50313 +static struct platform_driver cpsw_phy_sel_driver;
50314 +static int match(struct device *dev, void *data)
50315 +{
50316 + struct device_node *node = (struct device_node *)data;
50317 + return dev->of_node == node &&
50318 + dev->driver == &cpsw_phy_sel_driver.driver;
50319 +}
50320 +
50321 +void cpsw_phy_sel(struct device *dev, phy_interface_t phy_mode, int slave)
50322 +{
50323 + struct device_node *node;
50324 + struct cpsw_phy_sel_priv *priv;
50325 +
50326 + node = of_get_child_by_name(dev->of_node, "cpsw-phy-sel");
50327 + if (!node) {
50328 + dev_err(dev, "Phy mode driver DT not found\n");
50329 + return;
50330 + }
50331 +
50332 + dev = bus_find_device(&platform_bus_type, NULL, node, match);
50333 + priv = dev_get_drvdata(dev);
50334 +
50335 + priv->cpsw_phy_sel(priv, phy_mode, slave);
50336 +}
50337 +EXPORT_SYMBOL_GPL(cpsw_phy_sel);
50338 +
50339 +static const struct of_device_id cpsw_phy_sel_id_table[] = {
50340 + {
50341 + .compatible = "ti,am3352-cpsw-phy-sel",
50342 + .data = &cpsw_gmii_sel_am3352,
50343 + },
50344 + {}
50345 +};
50346 +MODULE_DEVICE_TABLE(of, cpsw_phy_sel_id_table);
50347 +
50348 +static int cpsw_phy_sel_probe(struct platform_device *pdev)
50349 +{
50350 + struct resource *res;
50351 + const struct of_device_id *of_id;
50352 + struct cpsw_phy_sel_priv *priv;
50353 +
50354 + of_id = of_match_node(cpsw_phy_sel_id_table, pdev->dev.of_node);
50355 + if (!of_id)
50356 + return -EINVAL;
50357 +
50358 + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
50359 + if (!priv) {
50360 + dev_err(&pdev->dev, "unable to alloc memory for cpsw phy sel\n");
50361 + return -ENOMEM;
50362 + }
50363 +
50364 + priv->cpsw_phy_sel = of_id->data;
50365 +
50366 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "gmii-sel");
50367 + priv->gmii_sel = devm_ioremap_resource(&pdev->dev, res);
50368 + if (IS_ERR(priv->gmii_sel))
50369 + return PTR_ERR(priv->gmii_sel);
50370 +
50371 + if (of_find_property(pdev->dev.of_node, "rmii-clock-ext", NULL))
50372 + priv->rmii_clock_external = true;
50373 +
50374 + dev_set_drvdata(&pdev->dev, priv);
50375 +
50376 + return 0;
50377 +}
50378 +
50379 +static struct platform_driver cpsw_phy_sel_driver = {
50380 + .probe = cpsw_phy_sel_probe,
50381 + .driver = {
50382 + .name = "cpsw-phy-sel",
50383 + .owner = THIS_MODULE,
50384 + .of_match_table = of_match_ptr(cpsw_phy_sel_id_table),
50385 + },
50386 +};
50387 +
50388 +module_platform_driver(cpsw_phy_sel_driver);
50389 +MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>");
50390 +MODULE_LICENSE("GPL v2");
50391 --- a/drivers/net/ethernet/ti/Kconfig
50392 +++ b/drivers/net/ethernet/ti/Kconfig
50393 @@ -49,11 +49,19 @@ config TI_DAVINCI_CPDMA
50394 To compile this driver as a module, choose M here: the module
50395 will be called davinci_cpdma. This is recommended.
50396
50397 +config TI_CPSW_PHY_SEL
50398 + boolean "TI CPSW Switch Phy sel Support"
50399 + depends on TI_CPSW
50400 + ---help---
50401 + This driver supports configuring of the phy mode connected to
50402 + the CPSW.
50403 +
50404 config TI_CPSW
50405 tristate "TI CPSW Switch Support"
50406 depends on ARM && (ARCH_DAVINCI || SOC_AM33XX)
50407 select TI_DAVINCI_CPDMA
50408 select TI_DAVINCI_MDIO
50409 + select TI_CPSW_PHY_SEL
50410 ---help---
50411 This driver supports TI's CPSW Ethernet Switch.
50412
50413 --- a/drivers/net/ethernet/ti/Makefile
50414 +++ b/drivers/net/ethernet/ti/Makefile
50415 @@ -7,5 +7,6 @@ obj-$(CONFIG_CPMAC) += cpmac.o
50416 obj-$(CONFIG_TI_DAVINCI_EMAC) += davinci_emac.o
50417 obj-$(CONFIG_TI_DAVINCI_MDIO) += davinci_mdio.o
50418 obj-$(CONFIG_TI_DAVINCI_CPDMA) += davinci_cpdma.o
50419 +obj-$(CONFIG_TI_CPSW_PHY_SEL) += cpsw-phy-sel.o
50420 obj-$(CONFIG_TI_CPSW) += ti_cpsw.o
50421 ti_cpsw-y := cpsw_ale.o cpsw.o cpts.o
50422 --- a/drivers/net/usb/smsc95xx.c
50423 +++ b/drivers/net/usb/smsc95xx.c
50424 @@ -31,6 +31,9 @@
50425 #include <linux/crc32.h>
50426 #include <linux/usb/usbnet.h>
50427 #include <linux/slab.h>
50428 +#include <linux/of.h>
50429 +#include <linux/of_net.h>
50430 +
50431 #include "smsc95xx.h"
50432
50433 #define SMSC_CHIPNAME "smsc95xx"
50434 @@ -62,6 +65,8 @@
50435 #define SUSPEND_ALLMODES (SUSPEND_SUSPEND0 | SUSPEND_SUSPEND1 | \
50436 SUSPEND_SUSPEND2 | SUSPEND_SUSPEND3)
50437
50438 +#define SMSC95XX_OF_NAME "/smsc95xx@"
50439 +
50440 struct smsc95xx_priv {
50441 u32 mac_cr;
50442 u32 hash_hi;
50443 @@ -767,6 +772,10 @@ static int smsc95xx_ioctl(struct net_dev
50444
50445 static void smsc95xx_init_mac_address(struct usbnet *dev)
50446 {
50447 + struct device_node *ap = NULL;
50448 + const char *mac = NULL;
50449 + char *of_name = SMSC95XX_OF_NAME;
50450 +
50451 /* try reading mac address from EEPROM */
50452 if (smsc95xx_read_eeprom(dev, EEPROM_MAC_OFFSET, ETH_ALEN,
50453 dev->net->dev_addr) == 0) {
50454 @@ -777,6 +786,20 @@ static void smsc95xx_init_mac_address(st
50455 }
50456 }
50457
50458 +#ifdef CONFIG_OF
50459 + sprintf(of_name, "%s%i", SMSC95XX_OF_NAME, dev->udev->dev.id);
50460 + ap = of_find_node_by_path(of_name);
50461 + if (ap) {
50462 + mac = of_get_mac_address(ap);
50463 + if ((mac != NULL) && (is_valid_ether_addr(mac))) {
50464 + /* Device tree has a mac for this so use that */
50465 + memcpy(dev->net->dev_addr, mac, ETH_ALEN);
50466 + netif_dbg(dev, ifup, dev->net, "MAC address read from DTB\n");
50467 + return;
50468 + }
50469 + }
50470 +#endif
50471 +
50472 /* no eeprom, or eeprom values are invalid. generate random MAC */
50473 eth_hw_addr_random(dev->net);
50474 netif_dbg(dev, ifup, dev->net, "MAC address set to eth_random_addr\n");
50475 --- /dev/null
50476 +++ b/drivers/phy/Kconfig
50477 @@ -0,0 +1,63 @@
50478 +#
50479 +# PHY
50480 +#
50481 +
50482 +menu "PHY Subsystem"
50483 +
50484 +config GENERIC_PHY
50485 + tristate "PHY Core"
50486 + help
50487 + Generic PHY support.
50488 +
50489 + This framework is designed to provide a generic interface for PHY
50490 + devices present in the kernel. This layer will have the generic
50491 + API by which phy drivers can create PHY using the phy framework and
50492 + phy users can obtain reference to the PHY. All the users of this
50493 + framework should select this config.
50494 +
50495 +config OMAP_CONTROL_PHY
50496 + tristate "OMAP CONTROL PHY Driver"
50497 + help
50498 + Enable this to add support for the PHY part present in the control
50499 + module. This driver has API to power on the USB2 PHY and to write to
50500 + the mailbox. The mailbox is present only in omap4 and the register to
50501 + power on the USB2 PHY is present in OMAP4 and OMAP5. OMAP5 has an
50502 + additional register to power on USB3 PHY/SATA PHY/PCIE PHY
50503 + (PIPE3 PHY).
50504 +
50505 +config OMAP_USB2
50506 + tristate "OMAP USB2 PHY Driver"
50507 + depends on ARCH_OMAP2PLUS
50508 + depends on USB_SUPPORT
50509 + select GENERIC_PHY
50510 + select USB_PHY
50511 + select OMAP_CONTROL_PHY
50512 + help
50513 + Enable this to support the transceiver that is part of SOC. This
50514 + driver takes care of all the PHY functionality apart from comparator.
50515 + The USB OTG controller communicates with the comparator using this
50516 + driver.
50517 +
50518 +config OMAP_PIPE3
50519 + tristate "OMAP PIPE3 PHY Driver"
50520 + select GENERIC_PHY
50521 + select OMAP_CONTROL_PHY
50522 + help
50523 + Enable this to support the PIPE3 PHY that is part of SOC. This
50524 + driver takes care of all the PHY functionality apart from comparator.
50525 + This driver interacts with the "OMAP Control PHY Driver" to power
50526 + on/off the PHY.
50527 +
50528 +config TWL4030_USB
50529 + tristate "TWL4030 USB Transceiver Driver"
50530 + depends on TWL4030_CORE && REGULATOR_TWL4030 && USB_MUSB_OMAP2PLUS
50531 + depends on USB_SUPPORT
50532 + select GENERIC_PHY
50533 + select USB_PHY
50534 + help
50535 + Enable this to support the USB OTG transceiver on TWL4030
50536 + family chips (including the TWL5030 and TPS659x0 devices).
50537 + This transceiver supports high and full speed devices plus,
50538 + in host mode, low speed.
50539 +
50540 +endmenu
50541 --- /dev/null
50542 +++ b/drivers/phy/Makefile
50543 @@ -0,0 +1,9 @@
50544 +#
50545 +# Makefile for the phy drivers.
50546 +#
50547 +
50548 +obj-$(CONFIG_GENERIC_PHY) += phy-core.o
50549 +obj-$(CONFIG_OMAP_CONTROL_PHY) += phy-omap-control.o
50550 +obj-$(CONFIG_OMAP_USB2) += phy-omap-usb2.o
50551 +obj-$(CONFIG_OMAP_PIPE3) += phy-omap-pipe3.o
50552 +obj-$(CONFIG_TWL4030_USB) += phy-twl4030-usb.o
50553 --- /dev/null
50554 +++ b/drivers/phy/phy-core.c
50555 @@ -0,0 +1,698 @@
50556 +/*
50557 + * phy-core.c -- Generic Phy framework.
50558 + *
50559 + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
50560 + *
50561 + * Author: Kishon Vijay Abraham I <kishon@ti.com>
50562 + *
50563 + * This program is free software; you can redistribute it and/or modify it
50564 + * under the terms of the GNU General Public License as published by the
50565 + * Free Software Foundation; either version 2 of the License, or (at your
50566 + * option) any later version.
50567 + */
50568 +
50569 +#include <linux/kernel.h>
50570 +#include <linux/export.h>
50571 +#include <linux/module.h>
50572 +#include <linux/err.h>
50573 +#include <linux/device.h>
50574 +#include <linux/slab.h>
50575 +#include <linux/of.h>
50576 +#include <linux/phy/phy.h>
50577 +#include <linux/idr.h>
50578 +#include <linux/pm_runtime.h>
50579 +
50580 +static struct class *phy_class;
50581 +static DEFINE_MUTEX(phy_provider_mutex);
50582 +static LIST_HEAD(phy_provider_list);
50583 +static DEFINE_IDA(phy_ida);
50584 +
50585 +static void devm_phy_release(struct device *dev, void *res)
50586 +{
50587 + struct phy *phy = *(struct phy **)res;
50588 +
50589 + phy_put(phy);
50590 +}
50591 +
50592 +static void devm_phy_provider_release(struct device *dev, void *res)
50593 +{
50594 + struct phy_provider *phy_provider = *(struct phy_provider **)res;
50595 +
50596 + of_phy_provider_unregister(phy_provider);
50597 +}
50598 +
50599 +static void devm_phy_consume(struct device *dev, void *res)
50600 +{
50601 + struct phy *phy = *(struct phy **)res;
50602 +
50603 + phy_destroy(phy);
50604 +}
50605 +
50606 +static int devm_phy_match(struct device *dev, void *res, void *match_data)
50607 +{
50608 + return res == match_data;
50609 +}
50610 +
50611 +static struct phy *phy_lookup(struct device *device, const char *port)
50612 +{
50613 + unsigned int count;
50614 + struct phy *phy;
50615 + struct device *dev;
50616 + struct phy_consumer *consumers;
50617 + struct class_dev_iter iter;
50618 +
50619 + class_dev_iter_init(&iter, phy_class, NULL, NULL);
50620 + while ((dev = class_dev_iter_next(&iter))) {
50621 + phy = to_phy(dev);
50622 + count = phy->init_data->num_consumers;
50623 + consumers = phy->init_data->consumers;
50624 + while (count--) {
50625 + if (!strcmp(consumers->dev_name, dev_name(device)) &&
50626 + !strcmp(consumers->port, port)) {
50627 + class_dev_iter_exit(&iter);
50628 + return phy;
50629 + }
50630 + consumers++;
50631 + }
50632 + }
50633 +
50634 + class_dev_iter_exit(&iter);
50635 + return ERR_PTR(-ENODEV);
50636 +}
50637 +
50638 +static struct phy_provider *of_phy_provider_lookup(struct device_node *node)
50639 +{
50640 + struct phy_provider *phy_provider;
50641 +
50642 + list_for_each_entry(phy_provider, &phy_provider_list, list) {
50643 + if (phy_provider->dev->of_node == node)
50644 + return phy_provider;
50645 + }
50646 +
50647 + return ERR_PTR(-EPROBE_DEFER);
50648 +}
50649 +
50650 +int phy_pm_runtime_get(struct phy *phy)
50651 +{
50652 + if (!pm_runtime_enabled(&phy->dev))
50653 + return -ENOTSUPP;
50654 +
50655 + return pm_runtime_get(&phy->dev);
50656 +}
50657 +EXPORT_SYMBOL_GPL(phy_pm_runtime_get);
50658 +
50659 +int phy_pm_runtime_get_sync(struct phy *phy)
50660 +{
50661 + if (!pm_runtime_enabled(&phy->dev))
50662 + return -ENOTSUPP;
50663 +
50664 + return pm_runtime_get_sync(&phy->dev);
50665 +}
50666 +EXPORT_SYMBOL_GPL(phy_pm_runtime_get_sync);
50667 +
50668 +int phy_pm_runtime_put(struct phy *phy)
50669 +{
50670 + if (!pm_runtime_enabled(&phy->dev))
50671 + return -ENOTSUPP;
50672 +
50673 + return pm_runtime_put(&phy->dev);
50674 +}
50675 +EXPORT_SYMBOL_GPL(phy_pm_runtime_put);
50676 +
50677 +int phy_pm_runtime_put_sync(struct phy *phy)
50678 +{
50679 + if (!pm_runtime_enabled(&phy->dev))
50680 + return -ENOTSUPP;
50681 +
50682 + return pm_runtime_put_sync(&phy->dev);
50683 +}
50684 +EXPORT_SYMBOL_GPL(phy_pm_runtime_put_sync);
50685 +
50686 +void phy_pm_runtime_allow(struct phy *phy)
50687 +{
50688 + if (!pm_runtime_enabled(&phy->dev))
50689 + return;
50690 +
50691 + pm_runtime_allow(&phy->dev);
50692 +}
50693 +EXPORT_SYMBOL_GPL(phy_pm_runtime_allow);
50694 +
50695 +void phy_pm_runtime_forbid(struct phy *phy)
50696 +{
50697 + if (!pm_runtime_enabled(&phy->dev))
50698 + return;
50699 +
50700 + pm_runtime_forbid(&phy->dev);
50701 +}
50702 +EXPORT_SYMBOL_GPL(phy_pm_runtime_forbid);
50703 +
50704 +int phy_init(struct phy *phy)
50705 +{
50706 + int ret;
50707 +
50708 + ret = phy_pm_runtime_get_sync(phy);
50709 + if (ret < 0 && ret != -ENOTSUPP)
50710 + return ret;
50711 +
50712 + mutex_lock(&phy->mutex);
50713 + if (phy->init_count++ == 0 && phy->ops->init) {
50714 + ret = phy->ops->init(phy);
50715 + if (ret < 0) {
50716 + dev_err(&phy->dev, "phy init failed --> %d\n", ret);
50717 + goto out;
50718 + }
50719 + }
50720 +
50721 +out:
50722 + mutex_unlock(&phy->mutex);
50723 + phy_pm_runtime_put(phy);
50724 + return ret;
50725 +}
50726 +EXPORT_SYMBOL_GPL(phy_init);
50727 +
50728 +int phy_exit(struct phy *phy)
50729 +{
50730 + int ret;
50731 +
50732 + ret = phy_pm_runtime_get_sync(phy);
50733 + if (ret < 0 && ret != -ENOTSUPP)
50734 + return ret;
50735 +
50736 + mutex_lock(&phy->mutex);
50737 + if (--phy->init_count == 0 && phy->ops->exit) {
50738 + ret = phy->ops->exit(phy);
50739 + if (ret < 0) {
50740 + dev_err(&phy->dev, "phy exit failed --> %d\n", ret);
50741 + goto out;
50742 + }
50743 + }
50744 +
50745 +out:
50746 + mutex_unlock(&phy->mutex);
50747 + phy_pm_runtime_put(phy);
50748 + return ret;
50749 +}
50750 +EXPORT_SYMBOL_GPL(phy_exit);
50751 +
50752 +int phy_power_on(struct phy *phy)
50753 +{
50754 + int ret = -ENOTSUPP;
50755 +
50756 + ret = phy_pm_runtime_get_sync(phy);
50757 + if (ret < 0 && ret != -ENOTSUPP)
50758 + return ret;
50759 +
50760 + mutex_lock(&phy->mutex);
50761 + if (phy->power_count++ == 0 && phy->ops->power_on) {
50762 + ret = phy->ops->power_on(phy);
50763 + if (ret < 0) {
50764 + dev_err(&phy->dev, "phy poweron failed --> %d\n", ret);
50765 + goto out;
50766 + }
50767 + }
50768 +
50769 +out:
50770 + mutex_unlock(&phy->mutex);
50771 +
50772 + return ret;
50773 +}
50774 +EXPORT_SYMBOL_GPL(phy_power_on);
50775 +
50776 +int phy_power_off(struct phy *phy)
50777 +{
50778 + int ret = -ENOTSUPP;
50779 +
50780 + mutex_lock(&phy->mutex);
50781 + if (--phy->power_count == 0 && phy->ops->power_off) {
50782 + ret = phy->ops->power_off(phy);
50783 + if (ret < 0) {
50784 + dev_err(&phy->dev, "phy poweroff failed --> %d\n", ret);
50785 + goto out;
50786 + }
50787 + }
50788 +
50789 +out:
50790 + mutex_unlock(&phy->mutex);
50791 + phy_pm_runtime_put(phy);
50792 +
50793 + return ret;
50794 +}
50795 +EXPORT_SYMBOL_GPL(phy_power_off);
50796 +
50797 +/**
50798 + * of_phy_get() - lookup and obtain a reference to a phy by phandle
50799 + * @dev: device that requests this phy
50800 + * @index: the index of the phy
50801 + *
50802 + * Returns the phy associated with the given phandle value,
50803 + * after getting a refcount to it or -ENODEV if there is no such phy or
50804 + * -EPROBE_DEFER if there is a phandle to the phy, but the device is
50805 + * not yet loaded. This function uses of_xlate call back function provided
50806 + * while registering the phy_provider to find the phy instance.
50807 + */
50808 +static struct phy *of_phy_get(struct device *dev, int index)
50809 +{
50810 + int ret;
50811 + struct phy_provider *phy_provider;
50812 + struct phy *phy = NULL;
50813 + struct of_phandle_args args;
50814 +
50815 + ret = of_parse_phandle_with_args(dev->of_node, "phys", "#phy-cells",
50816 + index, &args);
50817 + if (ret) {
50818 + dev_dbg(dev, "failed to get phy in %s node\n",
50819 + dev->of_node->full_name);
50820 + return ERR_PTR(-ENODEV);
50821 + }
50822 +
50823 + mutex_lock(&phy_provider_mutex);
50824 + phy_provider = of_phy_provider_lookup(args.np);
50825 + if (IS_ERR(phy_provider) || !try_module_get(phy_provider->owner)) {
50826 + phy = ERR_PTR(-EPROBE_DEFER);
50827 + goto err0;
50828 + }
50829 +
50830 + phy = phy_provider->of_xlate(phy_provider->dev, &args);
50831 + module_put(phy_provider->owner);
50832 +
50833 +err0:
50834 + mutex_unlock(&phy_provider_mutex);
50835 + of_node_put(args.np);
50836 +
50837 + return phy;
50838 +}
50839 +
50840 +/**
50841 + * phy_put() - release the PHY
50842 + * @phy: the phy returned by phy_get()
50843 + *
50844 + * Releases a refcount the caller received from phy_get().
50845 + */
50846 +void phy_put(struct phy *phy)
50847 +{
50848 + if (IS_ERR(phy))
50849 + return;
50850 +
50851 + module_put(phy->ops->owner);
50852 + put_device(&phy->dev);
50853 +}
50854 +EXPORT_SYMBOL_GPL(phy_put);
50855 +
50856 +/**
50857 + * devm_phy_put() - release the PHY
50858 + * @dev: device that wants to release this phy
50859 + * @phy: the phy returned by devm_phy_get()
50860 + *
50861 + * destroys the devres associated with this phy and invokes phy_put
50862 + * to release the phy.
50863 + */
50864 +void devm_phy_put(struct device *dev, struct phy *phy)
50865 +{
50866 + int r;
50867 +
50868 + r = devres_destroy(dev, devm_phy_release, devm_phy_match, phy);
50869 + dev_WARN_ONCE(dev, r, "couldn't find PHY resource\n");
50870 +}
50871 +EXPORT_SYMBOL_GPL(devm_phy_put);
50872 +
50873 +/**
50874 + * of_phy_simple_xlate() - returns the phy instance from phy provider
50875 + * @dev: the PHY provider device
50876 + * @args: of_phandle_args (not used here)
50877 + *
50878 + * Intended to be used by phy provider for the common case where #phy-cells is
50879 + * 0. For other cases where #phy-cells is greater than '0', the phy provider
50880 + * should provide a custom of_xlate function that reads the *args* and returns
50881 + * the appropriate phy.
50882 + */
50883 +struct phy *of_phy_simple_xlate(struct device *dev, struct of_phandle_args
50884 + *args)
50885 +{
50886 + struct phy *phy;
50887 + struct class_dev_iter iter;
50888 + struct device_node *node = dev->of_node;
50889 +
50890 + class_dev_iter_init(&iter, phy_class, NULL, NULL);
50891 + while ((dev = class_dev_iter_next(&iter))) {
50892 + phy = to_phy(dev);
50893 + if (node != phy->dev.of_node)
50894 + continue;
50895 +
50896 + class_dev_iter_exit(&iter);
50897 + return phy;
50898 + }
50899 +
50900 + class_dev_iter_exit(&iter);
50901 + return ERR_PTR(-ENODEV);
50902 +}
50903 +EXPORT_SYMBOL_GPL(of_phy_simple_xlate);
50904 +
50905 +/**
50906 + * phy_get() - lookup and obtain a reference to a phy.
50907 + * @dev: device that requests this phy
50908 + * @string: the phy name as given in the dt data or the name of the controller
50909 + * port for non-dt case
50910 + *
50911 + * Returns the phy driver, after getting a refcount to it; or
50912 + * -ENODEV if there is no such phy. The caller is responsible for
50913 + * calling phy_put() to release that count.
50914 + */
50915 +struct phy *phy_get(struct device *dev, const char *string)
50916 +{
50917 + int index = 0;
50918 + struct phy *phy = NULL;
50919 +
50920 + if (string == NULL) {
50921 + dev_WARN(dev, "missing string\n");
50922 + return ERR_PTR(-EINVAL);
50923 + }
50924 +
50925 + if (dev->of_node) {
50926 + index = of_property_match_string(dev->of_node, "phy-names",
50927 + string);
50928 + phy = of_phy_get(dev, index);
50929 + if (IS_ERR(phy)) {
50930 + dev_err(dev, "unable to find phy\n");
50931 + return phy;
50932 + }
50933 + } else {
50934 + phy = phy_lookup(dev, string);
50935 + if (IS_ERR(phy)) {
50936 + dev_err(dev, "unable to find phy\n");
50937 + return phy;
50938 + }
50939 + }
50940 +
50941 + if (!try_module_get(phy->ops->owner))
50942 + return ERR_PTR(-EPROBE_DEFER);
50943 +
50944 + get_device(&phy->dev);
50945 +
50946 + return phy;
50947 +}
50948 +EXPORT_SYMBOL_GPL(phy_get);
50949 +
50950 +/**
50951 + * devm_phy_get() - lookup and obtain a reference to a phy.
50952 + * @dev: device that requests this phy
50953 + * @string: the phy name as given in the dt data or phy device name
50954 + * for non-dt case
50955 + *
50956 + * Gets the phy using phy_get(), and associates a device with it using
50957 + * devres. On driver detach, release function is invoked on the devres data,
50958 + * then, devres data is freed.
50959 + */
50960 +struct phy *devm_phy_get(struct device *dev, const char *string)
50961 +{
50962 + struct phy **ptr, *phy;
50963 +
50964 + ptr = devres_alloc(devm_phy_release, sizeof(*ptr), GFP_KERNEL);
50965 + if (!ptr)
50966 + return ERR_PTR(-ENOMEM);
50967 +
50968 + phy = phy_get(dev, string);
50969 + if (!IS_ERR(phy)) {
50970 + *ptr = phy;
50971 + devres_add(dev, ptr);
50972 + } else {
50973 + devres_free(ptr);
50974 + }
50975 +
50976 + return phy;
50977 +}
50978 +EXPORT_SYMBOL_GPL(devm_phy_get);
50979 +
50980 +/**
50981 + * phy_create() - create a new phy
50982 + * @dev: device that is creating the new phy
50983 + * @ops: function pointers for performing phy operations
50984 + * @init_data: contains the list of PHY consumers or NULL
50985 + *
50986 + * Called to create a phy using phy framework.
50987 + */
50988 +struct phy *phy_create(struct device *dev, const struct phy_ops *ops,
50989 + struct phy_init_data *init_data)
50990 +{
50991 + int ret;
50992 + int id;
50993 + struct phy *phy;
50994 +
50995 + if (!dev) {
50996 + dev_WARN(dev, "no device provided for PHY\n");
50997 + ret = -EINVAL;
50998 + goto err0;
50999 + }
51000 +
51001 + phy = kzalloc(sizeof(*phy), GFP_KERNEL);
51002 + if (!phy) {
51003 + ret = -ENOMEM;
51004 + goto err0;
51005 + }
51006 +
51007 + id = ida_simple_get(&phy_ida, 0, 0, GFP_KERNEL);
51008 + if (id < 0) {
51009 + dev_err(dev, "unable to get id\n");
51010 + ret = id;
51011 + goto err0;
51012 + }
51013 +
51014 + device_initialize(&phy->dev);
51015 + mutex_init(&phy->mutex);
51016 +
51017 + phy->dev.class = phy_class;
51018 + phy->dev.parent = dev;
51019 + phy->dev.of_node = dev->of_node;
51020 + phy->id = id;
51021 + phy->ops = ops;
51022 + phy->init_data = init_data;
51023 +
51024 + ret = dev_set_name(&phy->dev, "phy-%s.%d", dev_name(dev), id);
51025 + if (ret)
51026 + goto err1;
51027 +
51028 + ret = device_add(&phy->dev);
51029 + if (ret)
51030 + goto err1;
51031 +
51032 + if (pm_runtime_enabled(dev)) {
51033 + pm_runtime_enable(&phy->dev);
51034 + pm_runtime_no_callbacks(&phy->dev);
51035 + }
51036 +
51037 + return phy;
51038 +
51039 +err1:
51040 + ida_remove(&phy_ida, phy->id);
51041 + put_device(&phy->dev);
51042 + kfree(phy);
51043 +
51044 +err0:
51045 + return ERR_PTR(ret);
51046 +}
51047 +EXPORT_SYMBOL_GPL(phy_create);
51048 +
51049 +/**
51050 + * devm_phy_create() - create a new phy
51051 + * @dev: device that is creating the new phy
51052 + * @ops: function pointers for performing phy operations
51053 + * @init_data: contains the list of PHY consumers or NULL
51054 + *
51055 + * Creates a new PHY device adding it to the PHY class.
51056 + * While at that, it also associates the device with the phy using devres.
51057 + * On driver detach, release function is invoked on the devres data,
51058 + * then, devres data is freed.
51059 + */
51060 +struct phy *devm_phy_create(struct device *dev, const struct phy_ops *ops,
51061 + struct phy_init_data *init_data)
51062 +{
51063 + struct phy **ptr, *phy;
51064 +
51065 + ptr = devres_alloc(devm_phy_consume, sizeof(*ptr), GFP_KERNEL);
51066 + if (!ptr)
51067 + return ERR_PTR(-ENOMEM);
51068 +
51069 + phy = phy_create(dev, ops, init_data);
51070 + if (!IS_ERR(phy)) {
51071 + *ptr = phy;
51072 + devres_add(dev, ptr);
51073 + } else {
51074 + devres_free(ptr);
51075 + }
51076 +
51077 + return phy;
51078 +}
51079 +EXPORT_SYMBOL_GPL(devm_phy_create);
51080 +
51081 +/**
51082 + * phy_destroy() - destroy the phy
51083 + * @phy: the phy to be destroyed
51084 + *
51085 + * Called to destroy the phy.
51086 + */
51087 +void phy_destroy(struct phy *phy)
51088 +{
51089 + pm_runtime_disable(&phy->dev);
51090 + device_unregister(&phy->dev);
51091 +}
51092 +EXPORT_SYMBOL_GPL(phy_destroy);
51093 +
51094 +/**
51095 + * devm_phy_destroy() - destroy the PHY
51096 + * @dev: device that wants to release this phy
51097 + * @phy: the phy returned by devm_phy_get()
51098 + *
51099 + * destroys the devres associated with this phy and invokes phy_destroy
51100 + * to destroy the phy.
51101 + */
51102 +void devm_phy_destroy(struct device *dev, struct phy *phy)
51103 +{
51104 + int r;
51105 +
51106 + r = devres_destroy(dev, devm_phy_consume, devm_phy_match, phy);
51107 + dev_WARN_ONCE(dev, r, "couldn't find PHY resource\n");
51108 +}
51109 +EXPORT_SYMBOL_GPL(devm_phy_destroy);
51110 +
51111 +/**
51112 + * __of_phy_provider_register() - create/register phy provider with the framework
51113 + * @dev: struct device of the phy provider
51114 + * @owner: the module owner containing of_xlate
51115 + * @of_xlate: function pointer to obtain phy instance from phy provider
51116 + *
51117 + * Creates struct phy_provider from dev and of_xlate function pointer.
51118 + * This is used in the case of dt boot for finding the phy instance from
51119 + * phy provider.
51120 + */
51121 +struct phy_provider *__of_phy_provider_register(struct device *dev,
51122 + struct module *owner, struct phy * (*of_xlate)(struct device *dev,
51123 + struct of_phandle_args *args))
51124 +{
51125 + struct phy_provider *phy_provider;
51126 +
51127 + phy_provider = kzalloc(sizeof(*phy_provider), GFP_KERNEL);
51128 + if (!phy_provider)
51129 + return ERR_PTR(-ENOMEM);
51130 +
51131 + phy_provider->dev = dev;
51132 + phy_provider->owner = owner;
51133 + phy_provider->of_xlate = of_xlate;
51134 +
51135 + mutex_lock(&phy_provider_mutex);
51136 + list_add_tail(&phy_provider->list, &phy_provider_list);
51137 + mutex_unlock(&phy_provider_mutex);
51138 +
51139 + return phy_provider;
51140 +}
51141 +EXPORT_SYMBOL_GPL(__of_phy_provider_register);
51142 +
51143 +/**
51144 + * __devm_of_phy_provider_register() - create/register phy provider with the
51145 + * framework
51146 + * @dev: struct device of the phy provider
51147 + * @owner: the module owner containing of_xlate
51148 + * @of_xlate: function pointer to obtain phy instance from phy provider
51149 + *
51150 + * Creates struct phy_provider from dev and of_xlate function pointer.
51151 + * This is used in the case of dt boot for finding the phy instance from
51152 + * phy provider. While at that, it also associates the device with the
51153 + * phy provider using devres. On driver detach, release function is invoked
51154 + * on the devres data, then, devres data is freed.
51155 + */
51156 +struct phy_provider *__devm_of_phy_provider_register(struct device *dev,
51157 + struct module *owner, struct phy * (*of_xlate)(struct device *dev,
51158 + struct of_phandle_args *args))
51159 +{
51160 + struct phy_provider **ptr, *phy_provider;
51161 +
51162 + ptr = devres_alloc(devm_phy_provider_release, sizeof(*ptr), GFP_KERNEL);
51163 + if (!ptr)
51164 + return ERR_PTR(-ENOMEM);
51165 +
51166 + phy_provider = __of_phy_provider_register(dev, owner, of_xlate);
51167 + if (!IS_ERR(phy_provider)) {
51168 + *ptr = phy_provider;
51169 + devres_add(dev, ptr);
51170 + } else {
51171 + devres_free(ptr);
51172 + }
51173 +
51174 + return phy_provider;
51175 +}
51176 +EXPORT_SYMBOL_GPL(__devm_of_phy_provider_register);
51177 +
51178 +/**
51179 + * of_phy_provider_unregister() - unregister phy provider from the framework
51180 + * @phy_provider: phy provider returned by of_phy_provider_register()
51181 + *
51182 + * Removes the phy_provider created using of_phy_provider_register().
51183 + */
51184 +void of_phy_provider_unregister(struct phy_provider *phy_provider)
51185 +{
51186 + if (IS_ERR(phy_provider))
51187 + return;
51188 +
51189 + mutex_lock(&phy_provider_mutex);
51190 + list_del(&phy_provider->list);
51191 + kfree(phy_provider);
51192 + mutex_unlock(&phy_provider_mutex);
51193 +}
51194 +EXPORT_SYMBOL_GPL(of_phy_provider_unregister);
51195 +
51196 +/**
51197 + * devm_of_phy_provider_unregister() - remove phy provider from the framework
51198 + * @dev: struct device of the phy provider
51199 + *
51200 + * destroys the devres associated with this phy provider and invokes
51201 + * of_phy_provider_unregister to unregister the phy provider.
51202 + */
51203 +void devm_of_phy_provider_unregister(struct device *dev,
51204 + struct phy_provider *phy_provider) {
51205 + int r;
51206 +
51207 + r = devres_destroy(dev, devm_phy_provider_release, devm_phy_match,
51208 + phy_provider);
51209 + dev_WARN_ONCE(dev, r, "couldn't find PHY provider device resource\n");
51210 +}
51211 +EXPORT_SYMBOL_GPL(devm_of_phy_provider_unregister);
51212 +
51213 +/**
51214 + * phy_release() - release the phy
51215 + * @dev: the dev member within phy
51216 + *
51217 + * When the last reference to the device is removed, it is called
51218 + * from the embedded kobject as release method.
51219 + */
51220 +static void phy_release(struct device *dev)
51221 +{
51222 + struct phy *phy;
51223 +
51224 + phy = to_phy(dev);
51225 + dev_vdbg(dev, "releasing '%s'\n", dev_name(dev));
51226 + ida_remove(&phy_ida, phy->id);
51227 + kfree(phy);
51228 +}
51229 +
51230 +static int __init phy_core_init(void)
51231 +{
51232 + phy_class = class_create(THIS_MODULE, "phy");
51233 + if (IS_ERR(phy_class)) {
51234 + pr_err("failed to create phy class --> %ld\n",
51235 + PTR_ERR(phy_class));
51236 + return PTR_ERR(phy_class);
51237 + }
51238 +
51239 + phy_class->dev_release = phy_release;
51240 +
51241 + return 0;
51242 +}
51243 +module_init(phy_core_init);
51244 +
51245 +static void __exit phy_core_exit(void)
51246 +{
51247 + class_destroy(phy_class);
51248 +}
51249 +module_exit(phy_core_exit);
51250 +
51251 +MODULE_DESCRIPTION("Generic PHY Framework");
51252 +MODULE_AUTHOR("Kishon Vijay Abraham I <kishon@ti.com>");
51253 +MODULE_LICENSE("GPL v2");
51254 --- /dev/null
51255 +++ b/drivers/phy/phy-omap-control.c
51256 @@ -0,0 +1,319 @@
51257 +/*
51258 + * omap-control-phy.c - The PHY part of control module.
51259 + *
51260 + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
51261 + * This program is free software; you can redistribute it and/or modify
51262 + * it under the terms of the GNU General Public License as published by
51263 + * the Free Software Foundation; either version 2 of the License, or
51264 + * (at your option) any later version.
51265 + *
51266 + * Author: Kishon Vijay Abraham I <kishon@ti.com>
51267 + *
51268 + * This program is distributed in the hope that it will be useful,
51269 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
51270 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
51271 + * GNU General Public License for more details.
51272 + *
51273 + */
51274 +
51275 +#include <linux/module.h>
51276 +#include <linux/platform_device.h>
51277 +#include <linux/slab.h>
51278 +#include <linux/of.h>
51279 +#include <linux/of_device.h>
51280 +#include <linux/err.h>
51281 +#include <linux/io.h>
51282 +#include <linux/clk.h>
51283 +#include <linux/phy/omap_control_phy.h>
51284 +
51285 +/**
51286 + * omap_control_phy_power - power on/off the phy using control module reg
51287 + * @dev: the control module device
51288 + * @on: 0 or 1, based on powering on or off the PHY
51289 + */
51290 +void omap_control_phy_power(struct device *dev, int on)
51291 +{
51292 + u32 val;
51293 + unsigned long rate;
51294 + struct omap_control_phy *control_phy;
51295 +
51296 + if (IS_ERR(dev) || !dev) {
51297 + pr_err("%s: invalid device\n", __func__);
51298 + return;
51299 + }
51300 +
51301 + control_phy = dev_get_drvdata(dev);
51302 + if (!control_phy) {
51303 + dev_err(dev, "%s: invalid control phy device\n", __func__);
51304 + return;
51305 + }
51306 +
51307 + if (control_phy->type == OMAP_CTRL_TYPE_OTGHS)
51308 + return;
51309 +
51310 + val = readl(control_phy->power);
51311 +
51312 + switch (control_phy->type) {
51313 + case OMAP_CTRL_TYPE_USB2:
51314 + if (on)
51315 + val &= ~OMAP_CTRL_DEV_PHY_PD;
51316 + else
51317 + val |= OMAP_CTRL_DEV_PHY_PD;
51318 + break;
51319 +
51320 + case OMAP_CTRL_TYPE_PIPE3:
51321 + rate = clk_get_rate(control_phy->sys_clk);
51322 + rate = rate/1000000;
51323 +
51324 + if (on) {
51325 + val &= ~(OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK |
51326 + OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK);
51327 + val |= OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON <<
51328 + OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT;
51329 + val |= rate <<
51330 + OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT;
51331 + } else {
51332 + val &= ~OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK;
51333 + val |= OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF <<
51334 + OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT;
51335 + }
51336 + break;
51337 +
51338 + case OMAP_CTRL_TYPE_DRA7USB2:
51339 + if (on)
51340 + val &= ~OMAP_CTRL_USB2_PHY_PD;
51341 + else
51342 + val |= OMAP_CTRL_USB2_PHY_PD;
51343 + break;
51344 +
51345 + case OMAP_CTRL_TYPE_AM437USB2:
51346 + if (on) {
51347 + val &= ~(AM437X_CTRL_USB2_PHY_PD |
51348 + AM437X_CTRL_USB2_OTG_PD);
51349 + val |= (AM437X_CTRL_USB2_OTGVDET_EN |
51350 + AM437X_CTRL_USB2_OTGSESSEND_EN);
51351 + } else {
51352 + val &= ~(AM437X_CTRL_USB2_OTGVDET_EN |
51353 + AM437X_CTRL_USB2_OTGSESSEND_EN);
51354 + val |= (AM437X_CTRL_USB2_PHY_PD |
51355 + AM437X_CTRL_USB2_OTG_PD);
51356 + }
51357 + break;
51358 + default:
51359 + dev_err(dev, "%s: type %d not recognized\n",
51360 + __func__, control_phy->type);
51361 + break;
51362 + }
51363 +
51364 + writel(val, control_phy->power);
51365 +}
51366 +EXPORT_SYMBOL_GPL(omap_control_phy_power);
51367 +
51368 +/**
51369 + * omap_control_usb_host_mode - set AVALID, VBUSVALID and ID pin in grounded
51370 + * @ctrl_phy: struct omap_control_phy *
51371 + *
51372 + * Writes to the mailbox register to notify the usb core that a usb
51373 + * device has been connected.
51374 + */
51375 +static void omap_control_usb_host_mode(struct omap_control_phy *ctrl_phy)
51376 +{
51377 + u32 val;
51378 +
51379 + val = readl(ctrl_phy->otghs_control);
51380 + val &= ~(OMAP_CTRL_DEV_IDDIG | OMAP_CTRL_DEV_SESSEND);
51381 + val |= OMAP_CTRL_DEV_AVALID | OMAP_CTRL_DEV_VBUSVALID;
51382 + writel(val, ctrl_phy->otghs_control);
51383 +}
51384 +
51385 +/**
51386 + * omap_control_usb_device_mode - set AVALID, VBUSVALID and ID pin in high
51387 + * impedance
51388 + * @ctrl_phy: struct omap_control_phy *
51389 + *
51390 + * Writes to the mailbox register to notify the usb core that it has been
51391 + * connected to a usb host.
51392 + */
51393 +static void omap_control_usb_device_mode(struct omap_control_phy *ctrl_phy)
51394 +{
51395 + u32 val;
51396 +
51397 + val = readl(ctrl_phy->otghs_control);
51398 + val &= ~OMAP_CTRL_DEV_SESSEND;
51399 + val |= OMAP_CTRL_DEV_IDDIG | OMAP_CTRL_DEV_AVALID |
51400 + OMAP_CTRL_DEV_VBUSVALID;
51401 + writel(val, ctrl_phy->otghs_control);
51402 +}
51403 +
51404 +/**
51405 + * omap_control_usb_set_sessionend - Enable SESSIONEND and IDIG to high
51406 + * impedance
51407 + * @ctrl_phy: struct omap_control_phy *
51408 + *
51409 + * Writes to the mailbox register to notify the usb core it's now in
51410 + * disconnected state.
51411 + */
51412 +static void omap_control_usb_set_sessionend(struct omap_control_phy *ctrl_phy)
51413 +{
51414 + u32 val;
51415 +
51416 + val = readl(ctrl_phy->otghs_control);
51417 + val &= ~(OMAP_CTRL_DEV_AVALID | OMAP_CTRL_DEV_VBUSVALID);
51418 + val |= OMAP_CTRL_DEV_IDDIG | OMAP_CTRL_DEV_SESSEND;
51419 + writel(val, ctrl_phy->otghs_control);
51420 +}
51421 +
51422 +/**
51423 + * omap_control_usb_set_mode - Calls to functions to set USB in one of host mode
51424 + * or device mode or to denote disconnected state
51425 + * @dev: the control module device
51426 + * @mode: The mode to which usb should be configured
51427 + *
51428 + * This is an API to write to the mailbox register to notify the usb core that
51429 + * a usb device has been connected.
51430 + */
51431 +void omap_control_usb_set_mode(struct device *dev,
51432 + enum omap_control_usb_mode mode)
51433 +{
51434 + struct omap_control_phy *ctrl_phy;
51435 +
51436 + if (IS_ERR(dev) || !dev)
51437 + return;
51438 +
51439 + ctrl_phy = dev_get_drvdata(dev);
51440 +
51441 + if (!ctrl_phy) {
51442 + dev_err(dev, "Invalid control phy device\n");
51443 + return;
51444 + }
51445 +
51446 + if (ctrl_phy->type != OMAP_CTRL_TYPE_OTGHS)
51447 + return;
51448 +
51449 + switch (mode) {
51450 + case USB_MODE_HOST:
51451 + omap_control_usb_host_mode(ctrl_phy);
51452 + break;
51453 + case USB_MODE_DEVICE:
51454 + omap_control_usb_device_mode(ctrl_phy);
51455 + break;
51456 + case USB_MODE_DISCONNECT:
51457 + omap_control_usb_set_sessionend(ctrl_phy);
51458 + break;
51459 + default:
51460 + dev_vdbg(dev, "invalid omap control usb mode\n");
51461 + }
51462 +}
51463 +EXPORT_SYMBOL_GPL(omap_control_usb_set_mode);
51464 +
51465 +#ifdef CONFIG_OF
51466 +
51467 +static const enum omap_control_phy_type otghs_data = OMAP_CTRL_TYPE_OTGHS;
51468 +static const enum omap_control_phy_type usb2_data = OMAP_CTRL_TYPE_USB2;
51469 +static const enum omap_control_phy_type pipe3_data = OMAP_CTRL_TYPE_PIPE3;
51470 +static const enum omap_control_phy_type dra7usb2_data = OMAP_CTRL_TYPE_DRA7USB2;
51471 +static const enum omap_control_phy_type am437usb2_data = OMAP_CTRL_TYPE_AM437USB2;
51472 +
51473 +static const struct of_device_id omap_control_phy_id_table[] = {
51474 + {
51475 + .compatible = "ti,control-phy-otghs",
51476 + .data = &otghs_data,
51477 + },
51478 + {
51479 + .compatible = "ti,control-phy-usb2",
51480 + .data = &usb2_data,
51481 + },
51482 + {
51483 + .compatible = "ti,control-phy-pipe3",
51484 + .data = &pipe3_data,
51485 + },
51486 + {
51487 + .compatible = "ti,control-phy-dra7usb2",
51488 + .data = &dra7usb2_data,
51489 + },
51490 + {
51491 + .compatible = "ti,control-phy-am437usb2",
51492 + .data = &am437usb2_data,
51493 + },
51494 + {},
51495 +};
51496 +MODULE_DEVICE_TABLE(of, omap_control_phy_id_table);
51497 +#endif
51498 +
51499 +static int omap_control_phy_probe(struct platform_device *pdev)
51500 +{
51501 + struct resource *res;
51502 + const struct of_device_id *of_id;
51503 + struct omap_control_phy *control_phy;
51504 +
51505 + of_id = of_match_device(of_match_ptr(omap_control_phy_id_table),
51506 + &pdev->dev);
51507 + if (!of_id)
51508 + return -EINVAL;
51509 +
51510 + control_phy = devm_kzalloc(&pdev->dev, sizeof(*control_phy),
51511 + GFP_KERNEL);
51512 + if (!control_phy) {
51513 + dev_err(&pdev->dev, "unable to alloc memory for control phy\n");
51514 + return -ENOMEM;
51515 + }
51516 +
51517 + control_phy->dev = &pdev->dev;
51518 + control_phy->type = *(enum omap_control_phy_type *)of_id->data;
51519 +
51520 + if (control_phy->type == OMAP_CTRL_TYPE_OTGHS) {
51521 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
51522 + "otghs_control");
51523 + control_phy->otghs_control = devm_ioremap_resource(
51524 + &pdev->dev, res);
51525 + if (IS_ERR(control_phy->otghs_control))
51526 + return PTR_ERR(control_phy->otghs_control);
51527 + } else {
51528 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
51529 + "power");
51530 + control_phy->power = devm_ioremap_resource(&pdev->dev, res);
51531 + if (IS_ERR(control_phy->power)) {
51532 + dev_err(&pdev->dev, "Couldn't get power register\n");
51533 + return PTR_ERR(control_phy->power);
51534 + }
51535 + }
51536 +
51537 + if (control_phy->type == OMAP_CTRL_TYPE_PIPE3) {
51538 + control_phy->sys_clk = devm_clk_get(control_phy->dev,
51539 + "sys_clkin");
51540 + if (IS_ERR(control_phy->sys_clk)) {
51541 + pr_err("%s: unable to get sys_clkin\n", __func__);
51542 + return -EINVAL;
51543 + }
51544 + }
51545 +
51546 + dev_set_drvdata(control_phy->dev, control_phy);
51547 +
51548 + return 0;
51549 +}
51550 +
51551 +static struct platform_driver omap_control_phy_driver = {
51552 + .probe = omap_control_phy_probe,
51553 + .driver = {
51554 + .name = "omap-control-phy",
51555 + .owner = THIS_MODULE,
51556 + .of_match_table = of_match_ptr(omap_control_phy_id_table),
51557 + },
51558 +};
51559 +
51560 +static int __init omap_control_phy_init(void)
51561 +{
51562 + return platform_driver_register(&omap_control_phy_driver);
51563 +}
51564 +subsys_initcall(omap_control_phy_init);
51565 +
51566 +static void __exit omap_control_phy_exit(void)
51567 +{
51568 + platform_driver_unregister(&omap_control_phy_driver);
51569 +}
51570 +module_exit(omap_control_phy_exit);
51571 +
51572 +MODULE_ALIAS("platform: omap_control_phy");
51573 +MODULE_AUTHOR("Texas Instruments Inc.");
51574 +MODULE_DESCRIPTION("OMAP Control Module PHY Driver");
51575 +MODULE_LICENSE("GPL v2");
51576 --- /dev/null
51577 +++ b/drivers/phy/phy-omap-pipe3.c
51578 @@ -0,0 +1,430 @@
51579 +/*
51580 + * omap-pipe3 - PHY driver for SATA, USB and PCIE in OMAP platforms
51581 + *
51582 + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
51583 + * This program is free software; you can redistribute it and/or modify
51584 + * it under the terms of the GNU General Public License as published by
51585 + * the Free Software Foundation; either version 2 of the License, or
51586 + * (at your option) any later version.
51587 + *
51588 + * Author: Kishon Vijay Abraham I <kishon@ti.com>
51589 + *
51590 + * This program is distributed in the hope that it will be useful,
51591 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
51592 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
51593 + * GNU General Public License for more details.
51594 + *
51595 + */
51596 +
51597 +#include <linux/module.h>
51598 +#include <linux/platform_device.h>
51599 +#include <linux/slab.h>
51600 +#include <linux/phy/omap_pipe3.h>
51601 +#include <linux/phy/phy.h>
51602 +#include <linux/of.h>
51603 +#include <linux/clk.h>
51604 +#include <linux/err.h>
51605 +#include <linux/pm_runtime.h>
51606 +#include <linux/delay.h>
51607 +#include <linux/phy/omap_control_phy.h>
51608 +#include <linux/of_platform.h>
51609 +
51610 +#define PLL_STATUS 0x00000004
51611 +#define PLL_GO 0x00000008
51612 +#define PLL_CONFIGURATION1 0x0000000C
51613 +#define PLL_CONFIGURATION2 0x00000010
51614 +#define PLL_CONFIGURATION3 0x00000014
51615 +#define PLL_CONFIGURATION4 0x00000020
51616 +
51617 +#define PLL_REGM_MASK 0x001FFE00
51618 +#define PLL_REGM_SHIFT 9
51619 +#define PLL_REGM_F_MASK 0x0003FFFF
51620 +#define PLL_REGM_F_SHIFT 0
51621 +#define PLL_REGN_MASK 0x000001FE
51622 +#define PLL_REGN_SHIFT 1
51623 +#define PLL_SELFREQDCO_MASK 0x0000000E
51624 +#define PLL_SELFREQDCO_SHIFT 1
51625 +#define PLL_SD_MASK 0x0003FC00
51626 +#define PLL_SD_SHIFT 10
51627 +#define SET_PLL_GO 0x1
51628 +#define PLL_TICOPWDN 0x10000
51629 +#define PLL_LOCK 0x2
51630 +#define PLL_IDLE 0x1
51631 +
51632 +/*
51633 + * This is an Empirical value that works, need to confirm the actual
51634 + * value required for the PIPE3PHY_PLL_CONFIGURATION2.PLL_IDLE status
51635 + * to be correctly reflected in the PIPE3PHY_PLL_STATUS register.
51636 + */
51637 +# define PLL_IDLE_TIME 100;
51638 +
51639 +static struct pipe3_dpll_map dpll_map_usb[] = {
51640 + {12000000, {1250, 5, 4, 20, 0} }, /* 12 MHz */
51641 + {16800000, {3125, 20, 4, 20, 0} }, /* 16.8 MHz */
51642 + {19200000, {1172, 8, 4, 20, 65537} }, /* 19.2 MHz */
51643 + {20000000, {1000, 7, 4, 10, 0} }, /* 20 MHz */
51644 + {26000000, {1250, 12, 4, 20, 0} }, /* 26 MHz */
51645 + {38400000, {3125, 47, 4, 20, 92843} }, /* 38.4 MHz */
51646 + { }, /* Terminator */
51647 +};
51648 +
51649 +static struct pipe3_dpll_map dpll_map_sata[] = {
51650 + {12000000, {1000, 7, 4, 6, 0} }, /* 12 MHz */
51651 + {16800000, {714, 7, 4, 6, 0} }, /* 16.8 MHz */
51652 + {19200000, {625, 7, 4, 6, 0} }, /* 19.2 MHz */
51653 + {20000000, {600, 7, 4, 6, 0} }, /* 20 MHz */
51654 + {26000000, {461, 7, 4, 6, 0} }, /* 26 MHz */
51655 + {38400000, {312, 7, 4, 6, 0} }, /* 38.4 MHz */
51656 + { }, /* Terminator */
51657 +};
51658 +
51659 +static struct pipe3_dpll_params *omap_pipe3_get_dpll_params(struct omap_pipe3
51660 + *pipe3)
51661 +{
51662 + unsigned long rate;
51663 + struct pipe3_dpll_map *dpll_map = pipe3->dpll_map;
51664 +
51665 + rate = clk_get_rate(pipe3->sys_clk);
51666 +
51667 + for (; dpll_map->rate; dpll_map++) {
51668 + if (rate == dpll_map->rate)
51669 + return &dpll_map->params;
51670 + }
51671 +
51672 + dev_err(pipe3->dev,
51673 + "No DPLL configuration for %lu Hz SYS CLK\n", rate);
51674 + return 0;
51675 +}
51676 +
51677 +static int omap_pipe3_power_off(struct phy *x)
51678 +{
51679 + struct omap_pipe3 *phy = phy_get_drvdata(x);
51680 + int val;
51681 + int timeout = PLL_IDLE_TIME;
51682 +
51683 + val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
51684 + val |= PLL_IDLE;
51685 + omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
51686 +
51687 + do {
51688 + val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
51689 + if (val & PLL_TICOPWDN)
51690 + break;
51691 + udelay(1);
51692 + } while (--timeout);
51693 +
51694 + omap_control_phy_power(phy->control_dev, 0);
51695 +
51696 + return 0;
51697 +}
51698 +
51699 +static int omap_pipe3_power_on(struct phy *x)
51700 +{
51701 + struct omap_pipe3 *phy = phy_get_drvdata(x);
51702 + int val;
51703 + int timeout = PLL_IDLE_TIME;
51704 +
51705 + val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
51706 + val &= ~PLL_IDLE;
51707 + omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
51708 +
51709 + do {
51710 + val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
51711 + if (!(val & PLL_TICOPWDN))
51712 + break;
51713 + udelay(1);
51714 + } while (--timeout);
51715 +
51716 + msleep(100);
51717 +
51718 + return 0;
51719 +}
51720 +
51721 +static void omap_pipe3_dpll_relock(struct omap_pipe3 *phy)
51722 +{
51723 + u32 val;
51724 + unsigned long timeout;
51725 +
51726 + omap_pipe3_writel(phy->pll_ctrl_base, PLL_GO, SET_PLL_GO);
51727 +
51728 + timeout = jiffies + msecs_to_jiffies(20);
51729 + do {
51730 + val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
51731 + if (val & PLL_LOCK)
51732 + break;
51733 + } while (!WARN_ON(time_after(jiffies, timeout)));
51734 +}
51735 +
51736 +static int omap_pipe3_dpll_lock(struct omap_pipe3 *phy)
51737 +{
51738 + u32 val;
51739 + unsigned long rate;
51740 + struct pipe3_dpll_params *dpll_params;
51741 +
51742 + rate = clk_get_rate(phy->sys_clk);
51743 + dpll_params = omap_pipe3_get_dpll_params(phy);
51744 + if (!dpll_params) {
51745 + return -EINVAL;
51746 + }
51747 +
51748 + val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
51749 + val &= ~PLL_REGN_MASK;
51750 + val |= dpll_params->n << PLL_REGN_SHIFT;
51751 + omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);
51752 +
51753 + val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
51754 + val &= ~PLL_SELFREQDCO_MASK;
51755 + val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT;
51756 + omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
51757 +
51758 + val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
51759 + val &= ~PLL_REGM_MASK;
51760 + val |= dpll_params->m << PLL_REGM_SHIFT;
51761 + omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);
51762 +
51763 + val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION4);
51764 + val &= ~PLL_REGM_F_MASK;
51765 + val |= dpll_params->mf << PLL_REGM_F_SHIFT;
51766 + omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION4, val);
51767 +
51768 + val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION3);
51769 + val &= ~PLL_SD_MASK;
51770 + val |= dpll_params->sd << PLL_SD_SHIFT;
51771 + omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION3, val);
51772 +
51773 + omap_pipe3_dpll_relock(phy);
51774 +
51775 + return 0;
51776 +}
51777 +
51778 +static int omap_pipe3_init(struct phy *x)
51779 +{
51780 + struct omap_pipe3 *phy = phy_get_drvdata(x);
51781 + int ret;
51782 +
51783 + ret = omap_pipe3_dpll_lock(phy);
51784 + if (ret)
51785 + return ret;
51786 +
51787 + omap_control_phy_power(phy->control_dev, 1);
51788 +
51789 + return 0;
51790 +}
51791 +
51792 +static struct phy_ops ops = {
51793 + .init = omap_pipe3_init,
51794 + .power_on = omap_pipe3_power_on,
51795 + .power_off = omap_pipe3_power_off,
51796 + .owner = THIS_MODULE,
51797 +};
51798 +
51799 +#ifdef CONFIG_OF
51800 +static const struct of_device_id omap_pipe3_id_table[] = {
51801 + {
51802 + .compatible = "ti,phy-pipe3-usb3",
51803 + .data = dpll_map_usb,
51804 + },
51805 + {
51806 + .compatible = "ti,phy-pipe3-sata",
51807 + .data = dpll_map_sata,
51808 + },
51809 + {},
51810 +};
51811 +MODULE_DEVICE_TABLE(of, omap_pipe3_id_table);
51812 +#endif
51813 +
51814 +static int omap_pipe3_probe(struct platform_device *pdev)
51815 +{
51816 + struct omap_pipe3 *phy;
51817 + struct phy *generic_phy;
51818 + struct phy_provider *phy_provider;
51819 + struct resource *res;
51820 + struct device_node *node = pdev->dev.of_node;
51821 + struct device_node *control_node;
51822 + struct platform_device *control_pdev;
51823 + const struct of_device_id *match;
51824 +
51825 + match = of_match_device(of_match_ptr(omap_pipe3_id_table), &pdev->dev);
51826 + if (!match)
51827 + return -EINVAL;
51828 +
51829 + phy = devm_kzalloc(&pdev->dev, sizeof(*phy), GFP_KERNEL);
51830 + if (!phy) {
51831 + dev_err(&pdev->dev, "unable to alloc mem for OMAP PIPE3 PHY\n");
51832 + return -ENOMEM;
51833 + }
51834 +
51835 + phy->dpll_map = (struct pipe3_dpll_map *)match->data;
51836 + if (!phy->dpll_map) {
51837 + dev_err(&pdev->dev, "no dpll data\n");
51838 + return -EINVAL;
51839 + }
51840 +
51841 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pll_ctrl");
51842 + phy->pll_ctrl_base = devm_ioremap_resource(&pdev->dev, res);
51843 + if (IS_ERR(phy->pll_ctrl_base))
51844 + return PTR_ERR(phy->pll_ctrl_base);
51845 +
51846 + phy->dev = &pdev->dev;
51847 +
51848 + phy->wkupclk = devm_clk_get(phy->dev, "wkupclk");
51849 + if (IS_ERR(phy->wkupclk))
51850 + dev_dbg(&pdev->dev, "unable to get wkupclk\n");
51851 + else
51852 + clk_prepare(phy->wkupclk);
51853 +
51854 + phy->optclk = devm_clk_get(phy->dev, "refclk");
51855 + if (IS_ERR(phy->optclk))
51856 + dev_dbg(&pdev->dev, "unable to get refclk\n");
51857 + else
51858 + clk_prepare(phy->optclk);
51859 +
51860 + phy->optclk2 = devm_clk_get(phy->dev, "refclk2");
51861 + if (IS_ERR(phy->optclk2))
51862 + dev_dbg(&pdev->dev, "unable to get refclk2\n");
51863 + else
51864 + clk_prepare(phy->optclk2);
51865 +
51866 + phy->sys_clk = devm_clk_get(phy->dev, "sys_clkin");
51867 + if (IS_ERR(phy->sys_clk)) {
51868 + pr_err("%s: unable to get sys_clkin\n", __func__);
51869 + return -EINVAL;
51870 + }
51871 +
51872 + control_node = of_parse_phandle(node, "ctrl-module", 0);
51873 + if (!control_node) {
51874 + dev_err(&pdev->dev, "Failed to get control device phandle\n");
51875 + return -EINVAL;
51876 + }
51877 +
51878 + phy_provider = devm_of_phy_provider_register(phy->dev,
51879 + of_phy_simple_xlate);
51880 + if (IS_ERR(phy_provider))
51881 + return PTR_ERR(phy_provider);
51882 +
51883 + control_pdev = of_find_device_by_node(control_node);
51884 + if (!control_pdev) {
51885 + dev_err(&pdev->dev, "Failed to get control device\n");
51886 + return -EINVAL;
51887 + }
51888 +
51889 + phy->control_dev = &control_pdev->dev;
51890 +
51891 + omap_control_phy_power(phy->control_dev, 0);
51892 +
51893 + platform_set_drvdata(pdev, phy);
51894 + pm_runtime_enable(phy->dev);
51895 +
51896 + generic_phy = devm_phy_create(phy->dev, &ops, NULL);
51897 + if (IS_ERR(generic_phy))
51898 + return PTR_ERR(generic_phy);
51899 +
51900 + phy_set_drvdata(generic_phy, phy);
51901 +
51902 + pm_runtime_get(&pdev->dev);
51903 +
51904 + return 0;
51905 +}
51906 +
51907 +static int omap_pipe3_remove(struct platform_device *pdev)
51908 +{
51909 + struct omap_pipe3 *phy = platform_get_drvdata(pdev);
51910 +
51911 + if (!IS_ERR(phy->wkupclk))
51912 + clk_unprepare(phy->wkupclk);
51913 + if (!IS_ERR(phy->optclk))
51914 + clk_unprepare(phy->optclk);
51915 + if (!IS_ERR(phy->optclk2))
51916 + clk_unprepare(phy->optclk2);
51917 + if (!pm_runtime_suspended(&pdev->dev))
51918 + pm_runtime_put(&pdev->dev);
51919 + pm_runtime_disable(&pdev->dev);
51920 +
51921 + return 0;
51922 +}
51923 +
51924 +#ifdef CONFIG_PM_RUNTIME
51925 +
51926 +static int omap_pipe3_runtime_suspend(struct device *dev)
51927 +{
51928 + struct omap_pipe3 *phy = dev_get_drvdata(dev);
51929 +
51930 + if (!IS_ERR(phy->wkupclk))
51931 + clk_disable(phy->wkupclk);
51932 + if (!IS_ERR(phy->optclk))
51933 + clk_disable(phy->optclk);
51934 + if (!IS_ERR(phy->optclk2))
51935 + clk_disable(phy->optclk2);
51936 +
51937 + return 0;
51938 +}
51939 +
51940 +static int omap_pipe3_runtime_resume(struct device *dev)
51941 +{
51942 + u32 ret = 0;
51943 + struct omap_pipe3 *phy = dev_get_drvdata(dev);
51944 +
51945 + if (!IS_ERR(phy->optclk)) {
51946 + ret = clk_enable(phy->optclk);
51947 + if (ret) {
51948 + dev_err(phy->dev, "Failed to enable optclk %d\n", ret);
51949 + goto err1;
51950 + }
51951 + }
51952 +
51953 + if (!IS_ERR(phy->wkupclk)) {
51954 + ret = clk_enable(phy->wkupclk);
51955 + if (ret) {
51956 + dev_err(phy->dev, "Failed to enable wkupclk %d\n", ret);
51957 + goto err2;
51958 + }
51959 + }
51960 +
51961 + if (!IS_ERR(phy->optclk2)) {
51962 + ret = clk_enable(phy->optclk2);
51963 + if (ret) {
51964 + dev_err(phy->dev, "Failed to enable optclk2 %d\n", ret);
51965 + goto err3;
51966 + }
51967 + }
51968 +
51969 + return 0;
51970 +
51971 +err3:
51972 + if (!IS_ERR(phy->wkupclk))
51973 + clk_disable(phy->wkupclk);
51974 +err2:
51975 + if (!IS_ERR(phy->optclk))
51976 + clk_disable(phy->optclk);
51977 +
51978 +err1:
51979 + return ret;
51980 +}
51981 +
51982 +static const struct dev_pm_ops omap_pipe3_pm_ops = {
51983 + SET_RUNTIME_PM_OPS(omap_pipe3_runtime_suspend,
51984 + omap_pipe3_runtime_resume, NULL)
51985 +};
51986 +
51987 +#define DEV_PM_OPS (&omap_pipe3_pm_ops)
51988 +#else
51989 +#define DEV_PM_OPS NULL
51990 +#endif
51991 +
51992 +static struct platform_driver omap_pipe3_driver = {
51993 + .probe = omap_pipe3_probe,
51994 + .remove = omap_pipe3_remove,
51995 + .driver = {
51996 + .name = "omap-pipe3",
51997 + .owner = THIS_MODULE,
51998 + .pm = DEV_PM_OPS,
51999 + .of_match_table = of_match_ptr(omap_pipe3_id_table),
52000 + },
52001 +};
52002 +
52003 +module_platform_driver(omap_pipe3_driver);
52004 +
52005 +MODULE_ALIAS("platform: omap_pipe3");
52006 +MODULE_AUTHOR("Texas Instruments Inc.");
52007 +MODULE_DESCRIPTION("OMAP PIPE3 phy driver");
52008 +MODULE_LICENSE("GPL v2");
52009 --- /dev/null
52010 +++ b/drivers/phy/phy-omap-usb2.c
52011 @@ -0,0 +1,326 @@
52012 +/*
52013 + * omap-usb2.c - USB PHY, talking to musb controller in OMAP.
52014 + *
52015 + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com
52016 + * This program is free software; you can redistribute it and/or modify
52017 + * it under the terms of the GNU General Public License as published by
52018 + * the Free Software Foundation; either version 2 of the License, or
52019 + * (at your option) any later version.
52020 + *
52021 + * Author: Kishon Vijay Abraham I <kishon@ti.com>
52022 + *
52023 + * This program is distributed in the hope that it will be useful,
52024 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
52025 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
52026 + * GNU General Public License for more details.
52027 + *
52028 + */
52029 +
52030 +#include <linux/module.h>
52031 +#include <linux/platform_device.h>
52032 +#include <linux/slab.h>
52033 +#include <linux/of.h>
52034 +#include <linux/io.h>
52035 +#include <linux/phy/omap_usb.h>
52036 +#include <linux/usb/phy_companion.h>
52037 +#include <linux/clk.h>
52038 +#include <linux/err.h>
52039 +#include <linux/pm_runtime.h>
52040 +#include <linux/delay.h>
52041 +#include <linux/phy/omap_control_phy.h>
52042 +#include <linux/phy/phy.h>
52043 +#include <linux/of_platform.h>
52044 +#include <linux/phy/phy.h>
52045 +#include <linux/of_platform.h>
52046 +
52047 +/**
52048 + * omap_usb2_set_comparator - links the comparator present in the sytem with
52049 + * this phy
52050 + * @comparator - the companion phy(comparator) for this phy
52051 + *
52052 + * The phy companion driver should call this API passing the phy_companion
52053 + * filled with set_vbus and start_srp to be used by usb phy.
52054 + *
52055 + * For use by phy companion driver
52056 + */
52057 +int omap_usb2_set_comparator(struct phy_companion *comparator)
52058 +{
52059 + struct omap_usb *phy;
52060 + struct usb_phy *x = usb_get_phy(USB_PHY_TYPE_USB2);
52061 +
52062 + if (IS_ERR(x))
52063 + return -ENODEV;
52064 +
52065 + phy = phy_to_omapusb(x);
52066 + phy->comparator = comparator;
52067 + return 0;
52068 +}
52069 +EXPORT_SYMBOL_GPL(omap_usb2_set_comparator);
52070 +
52071 +static int omap_usb_set_vbus(struct usb_otg *otg, bool enabled)
52072 +{
52073 + struct omap_usb *phy = phy_to_omapusb(otg->phy);
52074 +
52075 + if (!phy->comparator)
52076 + return -ENODEV;
52077 +
52078 + return phy->comparator->set_vbus(phy->comparator, enabled);
52079 +}
52080 +
52081 +static int omap_usb_start_srp(struct usb_otg *otg)
52082 +{
52083 + struct omap_usb *phy = phy_to_omapusb(otg->phy);
52084 +
52085 + if (!phy->comparator)
52086 + return -ENODEV;
52087 +
52088 + return phy->comparator->start_srp(phy->comparator);
52089 +}
52090 +
52091 +static int omap_usb_set_host(struct usb_otg *otg, struct usb_bus *host)
52092 +{
52093 + struct usb_phy *phy = otg->phy;
52094 +
52095 + otg->host = host;
52096 + if (!host)
52097 + phy->state = OTG_STATE_UNDEFINED;
52098 +
52099 + return 0;
52100 +}
52101 +
52102 +static int omap_usb_set_peripheral(struct usb_otg *otg,
52103 + struct usb_gadget *gadget)
52104 +{
52105 + struct usb_phy *phy = otg->phy;
52106 +
52107 + otg->gadget = gadget;
52108 + if (!gadget)
52109 + phy->state = OTG_STATE_UNDEFINED;
52110 +
52111 + return 0;
52112 +}
52113 +
52114 +static int omap_usb_power_off(struct phy *x)
52115 +{
52116 + struct omap_usb *phy = phy_get_drvdata(x);
52117 +
52118 + omap_control_phy_power(phy->control_dev, 0);
52119 +
52120 + return 0;
52121 +}
52122 +
52123 +static int omap_usb_power_on(struct phy *x)
52124 +{
52125 + struct omap_usb *phy = phy_get_drvdata(x);
52126 +
52127 + omap_control_phy_power(phy->control_dev, 1);
52128 +
52129 + return 0;
52130 +}
52131 +
52132 +static struct phy_ops ops = {
52133 + .power_on = omap_usb_power_on,
52134 + .power_off = omap_usb_power_off,
52135 + .owner = THIS_MODULE,
52136 +};
52137 +
52138 +#ifdef CONFIG_OF
52139 +static const struct usb_phy_data omap_usb2_data = {
52140 + .label = "omap_usb2",
52141 + .flags = OMAP_USB2_HAS_START_SRP | OMAP_USB2_HAS_SET_VBUS,
52142 +};
52143 +
52144 +static const struct usb_phy_data am437x_usb2_data = {
52145 + .label = "am437x_usb2",
52146 + .flags = 0,
52147 +};
52148 +
52149 +static const struct of_device_id omap_usb2_id_table[] = {
52150 + {
52151 + .compatible = "ti,omap-usb2",
52152 + .data = &omap_usb2_data,
52153 + },
52154 + {
52155 + .compatible = "ti,am437x-usb2",
52156 + .data = &am437x_usb2_data,
52157 + },
52158 + {},
52159 +};
52160 +MODULE_DEVICE_TABLE(of, omap_usb2_id_table);
52161 +#endif
52162 +
52163 +static int omap_usb2_probe(struct platform_device *pdev)
52164 +{
52165 + struct omap_usb *phy;
52166 + struct usb_otg *otg;
52167 + struct device_node *node = pdev->dev.of_node;
52168 + struct device_node *control_node;
52169 + struct platform_device *control_pdev;
52170 + struct phy *generic_phy;
52171 + struct phy_provider *phy_provider;
52172 + const struct of_device_id *of_id;
52173 + struct usb_phy_data *phy_data;
52174 +
52175 + of_id = of_match_device(of_match_ptr(omap_usb2_id_table), &pdev->dev);
52176 +
52177 + if (!of_id)
52178 + return -EINVAL;
52179 + phy_data = (struct usb_phy_data *)of_id->data;
52180 +
52181 + phy = devm_kzalloc(&pdev->dev, sizeof(*phy), GFP_KERNEL);
52182 + if (!phy) {
52183 + dev_err(&pdev->dev, "unable to allocate memory for USB2 PHY\n");
52184 + return -ENOMEM;
52185 + }
52186 +
52187 + otg = devm_kzalloc(&pdev->dev, sizeof(*otg), GFP_KERNEL);
52188 + if (!otg) {
52189 + dev_err(&pdev->dev, "unable to allocate memory for USB OTG\n");
52190 + return -ENOMEM;
52191 + }
52192 +
52193 + phy->dev = &pdev->dev;
52194 +
52195 + phy->phy.dev = phy->dev;
52196 + phy->phy.label = phy_data->label;
52197 + phy->phy.otg = otg;
52198 + phy->phy.type = USB_PHY_TYPE_USB2;
52199 +
52200 + phy_provider = devm_of_phy_provider_register(phy->dev,
52201 + of_phy_simple_xlate);
52202 + if (IS_ERR(phy_provider))
52203 + return PTR_ERR(phy_provider);
52204 +
52205 + control_node = of_parse_phandle(node, "ctrl-module", 0);
52206 + if (!control_node) {
52207 + dev_err(&pdev->dev, "Failed to get control device phandle\n");
52208 + return -EINVAL;
52209 + }
52210 +
52211 + control_pdev = of_find_device_by_node(control_node);
52212 + if (!control_pdev) {
52213 + dev_err(&pdev->dev, "Failed to get control device\n");
52214 + return -EINVAL;
52215 + }
52216 +
52217 + phy->control_dev = &control_pdev->dev;
52218 +
52219 + omap_control_phy_power(phy->control_dev, 0);
52220 +
52221 + otg->set_host = omap_usb_set_host;
52222 + otg->set_peripheral = omap_usb_set_peripheral;
52223 + if (phy_data->flags & OMAP_USB2_HAS_SET_VBUS)
52224 + otg->set_vbus = omap_usb_set_vbus;
52225 + if (phy_data->flags & OMAP_USB2_HAS_START_SRP)
52226 + otg->start_srp = omap_usb_start_srp;
52227 + otg->phy = &phy->phy;
52228 +
52229 + platform_set_drvdata(pdev, phy);
52230 + pm_runtime_enable(phy->dev);
52231 +
52232 + generic_phy = devm_phy_create(phy->dev, &ops, NULL);
52233 + if (IS_ERR(generic_phy))
52234 + return PTR_ERR(generic_phy);
52235 +
52236 + phy_set_drvdata(generic_phy, phy);
52237 +
52238 + phy->wkupclk = devm_clk_get(phy->dev, "wkupclk");
52239 + if (IS_ERR(phy->wkupclk)) {
52240 + dev_err(&pdev->dev, "unable to get wkupclk\n");
52241 + return PTR_ERR(phy->wkupclk);
52242 + }
52243 + clk_prepare(phy->wkupclk);
52244 +
52245 + phy->optclk = devm_clk_get(phy->dev, "refclk");
52246 + if (IS_ERR(phy->optclk))
52247 + dev_dbg(&pdev->dev, "unable to get refclk\n");
52248 + else
52249 + clk_prepare(phy->optclk);
52250 +
52251 + usb_add_phy_dev(&phy->phy);
52252 +
52253 + return 0;
52254 +}
52255 +
52256 +static int omap_usb2_remove(struct platform_device *pdev)
52257 +{
52258 + struct omap_usb *phy = platform_get_drvdata(pdev);
52259 +
52260 + clk_unprepare(phy->wkupclk);
52261 + if (!IS_ERR(phy->optclk))
52262 + clk_unprepare(phy->optclk);
52263 + usb_remove_phy(&phy->phy);
52264 +
52265 + return 0;
52266 +}
52267 +
52268 +#ifdef CONFIG_PM_RUNTIME
52269 +
52270 +static int omap_usb2_runtime_suspend(struct device *dev)
52271 +{
52272 + struct platform_device *pdev = to_platform_device(dev);
52273 + struct omap_usb *phy = platform_get_drvdata(pdev);
52274 +
52275 + clk_disable(phy->wkupclk);
52276 + if (!IS_ERR(phy->optclk))
52277 + clk_disable(phy->optclk);
52278 +
52279 + return 0;
52280 +}
52281 +
52282 +static int omap_usb2_runtime_resume(struct device *dev)
52283 +{
52284 + struct platform_device *pdev = to_platform_device(dev);
52285 + struct omap_usb *phy = platform_get_drvdata(pdev);
52286 + int ret;
52287 +
52288 + ret = clk_enable(phy->wkupclk);
52289 + if (ret < 0) {
52290 + dev_err(phy->dev, "Failed to enable wkupclk %d\n", ret);
52291 + goto err0;
52292 + }
52293 +
52294 + if (!IS_ERR(phy->optclk)) {
52295 + ret = clk_enable(phy->optclk);
52296 + if (ret < 0) {
52297 + dev_err(phy->dev, "Failed to enable optclk %d\n", ret);
52298 + goto err1;
52299 + }
52300 + }
52301 +
52302 + return 0;
52303 +
52304 +err1:
52305 + clk_disable(phy->wkupclk);
52306 +
52307 +err0:
52308 + return ret;
52309 +}
52310 +
52311 +static const struct dev_pm_ops omap_usb2_pm_ops = {
52312 + SET_RUNTIME_PM_OPS(omap_usb2_runtime_suspend, omap_usb2_runtime_resume,
52313 + NULL)
52314 +};
52315 +
52316 +#define DEV_PM_OPS (&omap_usb2_pm_ops)
52317 +#else
52318 +#define DEV_PM_OPS NULL
52319 +#endif
52320 +
52321 +static struct platform_driver omap_usb2_driver = {
52322 + .probe = omap_usb2_probe,
52323 + .remove = omap_usb2_remove,
52324 + .driver = {
52325 + .name = "omap-usb2",
52326 + .owner = THIS_MODULE,
52327 + .pm = DEV_PM_OPS,
52328 + .of_match_table = of_match_ptr(omap_usb2_id_table),
52329 + },
52330 +};
52331 +
52332 +module_platform_driver(omap_usb2_driver);
52333 +
52334 +MODULE_ALIAS("platform: omap_usb2");
52335 +MODULE_AUTHOR("Texas Instruments Inc.");
52336 +MODULE_DESCRIPTION("OMAP USB2 phy driver");
52337 +MODULE_LICENSE("GPL v2");
52338 --- /dev/null
52339 +++ b/drivers/phy/phy-twl4030-usb.c
52340 @@ -0,0 +1,815 @@
52341 +/*
52342 + * twl4030_usb - TWL4030 USB transceiver, talking to OMAP OTG controller
52343 + *
52344 + * Copyright (C) 2004-2007 Texas Instruments
52345 + * Copyright (C) 2008 Nokia Corporation
52346 + * Contact: Felipe Balbi <felipe.balbi@nokia.com>
52347 + *
52348 + * This program is free software; you can redistribute it and/or modify
52349 + * it under the terms of the GNU General Public License as published by
52350 + * the Free Software Foundation; either version 2 of the License, or
52351 + * (at your option) any later version.
52352 + *
52353 + * This program is distributed in the hope that it will be useful,
52354 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
52355 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
52356 + * GNU General Public License for more details.
52357 + *
52358 + * You should have received a copy of the GNU General Public License
52359 + * along with this program; if not, write to the Free Software
52360 + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
52361 + *
52362 + * Current status:
52363 + * - HS USB ULPI mode works.
52364 + * - 3-pin mode support may be added in future.
52365 + */
52366 +
52367 +#include <linux/module.h>
52368 +#include <linux/init.h>
52369 +#include <linux/interrupt.h>
52370 +#include <linux/platform_device.h>
52371 +#include <linux/spinlock.h>
52372 +#include <linux/workqueue.h>
52373 +#include <linux/io.h>
52374 +#include <linux/delay.h>
52375 +#include <linux/usb/otg.h>
52376 +#include <linux/phy/phy.h>
52377 +#include <linux/usb/musb-omap.h>
52378 +#include <linux/usb/ulpi.h>
52379 +#include <linux/i2c/twl.h>
52380 +#include <linux/regulator/consumer.h>
52381 +#include <linux/err.h>
52382 +#include <linux/slab.h>
52383 +
52384 +/* Register defines */
52385 +
52386 +#define MCPC_CTRL 0x30
52387 +#define MCPC_CTRL_RTSOL (1 << 7)
52388 +#define MCPC_CTRL_EXTSWR (1 << 6)
52389 +#define MCPC_CTRL_EXTSWC (1 << 5)
52390 +#define MCPC_CTRL_VOICESW (1 << 4)
52391 +#define MCPC_CTRL_OUT64K (1 << 3)
52392 +#define MCPC_CTRL_RTSCTSSW (1 << 2)
52393 +#define MCPC_CTRL_HS_UART (1 << 0)
52394 +
52395 +#define MCPC_IO_CTRL 0x33
52396 +#define MCPC_IO_CTRL_MICBIASEN (1 << 5)
52397 +#define MCPC_IO_CTRL_CTS_NPU (1 << 4)
52398 +#define MCPC_IO_CTRL_RXD_PU (1 << 3)
52399 +#define MCPC_IO_CTRL_TXDTYP (1 << 2)
52400 +#define MCPC_IO_CTRL_CTSTYP (1 << 1)
52401 +#define MCPC_IO_CTRL_RTSTYP (1 << 0)
52402 +
52403 +#define MCPC_CTRL2 0x36
52404 +#define MCPC_CTRL2_MCPC_CK_EN (1 << 0)
52405 +
52406 +#define OTHER_FUNC_CTRL 0x80
52407 +#define OTHER_FUNC_CTRL_BDIS_ACON_EN (1 << 4)
52408 +#define OTHER_FUNC_CTRL_FIVEWIRE_MODE (1 << 2)
52409 +
52410 +#define OTHER_IFC_CTRL 0x83
52411 +#define OTHER_IFC_CTRL_OE_INT_EN (1 << 6)
52412 +#define OTHER_IFC_CTRL_CEA2011_MODE (1 << 5)
52413 +#define OTHER_IFC_CTRL_FSLSSERIALMODE_4PIN (1 << 4)
52414 +#define OTHER_IFC_CTRL_HIZ_ULPI_60MHZ_OUT (1 << 3)
52415 +#define OTHER_IFC_CTRL_HIZ_ULPI (1 << 2)
52416 +#define OTHER_IFC_CTRL_ALT_INT_REROUTE (1 << 0)
52417 +
52418 +#define OTHER_INT_EN_RISE 0x86
52419 +#define OTHER_INT_EN_FALL 0x89
52420 +#define OTHER_INT_STS 0x8C
52421 +#define OTHER_INT_LATCH 0x8D
52422 +#define OTHER_INT_VB_SESS_VLD (1 << 7)
52423 +#define OTHER_INT_DM_HI (1 << 6) /* not valid for "latch" reg */
52424 +#define OTHER_INT_DP_HI (1 << 5) /* not valid for "latch" reg */
52425 +#define OTHER_INT_BDIS_ACON (1 << 3) /* not valid for "fall" regs */
52426 +#define OTHER_INT_MANU (1 << 1)
52427 +#define OTHER_INT_ABNORMAL_STRESS (1 << 0)
52428 +
52429 +#define ID_STATUS 0x96
52430 +#define ID_RES_FLOAT (1 << 4)
52431 +#define ID_RES_440K (1 << 3)
52432 +#define ID_RES_200K (1 << 2)
52433 +#define ID_RES_102K (1 << 1)
52434 +#define ID_RES_GND (1 << 0)
52435 +
52436 +#define POWER_CTRL 0xAC
52437 +#define POWER_CTRL_OTG_ENAB (1 << 5)
52438 +
52439 +#define OTHER_IFC_CTRL2 0xAF
52440 +#define OTHER_IFC_CTRL2_ULPI_STP_LOW (1 << 4)
52441 +#define OTHER_IFC_CTRL2_ULPI_TXEN_POL (1 << 3)
52442 +#define OTHER_IFC_CTRL2_ULPI_4PIN_2430 (1 << 2)
52443 +#define OTHER_IFC_CTRL2_USB_INT_OUTSEL_MASK (3 << 0) /* bits 0 and 1 */
52444 +#define OTHER_IFC_CTRL2_USB_INT_OUTSEL_INT1N (0 << 0)
52445 +#define OTHER_IFC_CTRL2_USB_INT_OUTSEL_INT2N (1 << 0)
52446 +
52447 +#define REG_CTRL_EN 0xB2
52448 +#define REG_CTRL_ERROR 0xB5
52449 +#define ULPI_I2C_CONFLICT_INTEN (1 << 0)
52450 +
52451 +#define OTHER_FUNC_CTRL2 0xB8
52452 +#define OTHER_FUNC_CTRL2_VBAT_TIMER_EN (1 << 0)
52453 +
52454 +/* following registers do not have separate _clr and _set registers */
52455 +#define VBUS_DEBOUNCE 0xC0
52456 +#define ID_DEBOUNCE 0xC1
52457 +#define VBAT_TIMER 0xD3
52458 +#define PHY_PWR_CTRL 0xFD
52459 +#define PHY_PWR_PHYPWD (1 << 0)
52460 +#define PHY_CLK_CTRL 0xFE
52461 +#define PHY_CLK_CTRL_CLOCKGATING_EN (1 << 2)
52462 +#define PHY_CLK_CTRL_CLK32K_EN (1 << 1)
52463 +#define REQ_PHY_DPLL_CLK (1 << 0)
52464 +#define PHY_CLK_CTRL_STS 0xFF
52465 +#define PHY_DPLL_CLK (1 << 0)
52466 +
52467 +/* In module TWL_MODULE_PM_MASTER */
52468 +#define STS_HW_CONDITIONS 0x0F
52469 +
52470 +/* In module TWL_MODULE_PM_RECEIVER */
52471 +#define VUSB_DEDICATED1 0x7D
52472 +#define VUSB_DEDICATED2 0x7E
52473 +#define VUSB1V5_DEV_GRP 0x71
52474 +#define VUSB1V5_TYPE 0x72
52475 +#define VUSB1V5_REMAP 0x73
52476 +#define VUSB1V8_DEV_GRP 0x74
52477 +#define VUSB1V8_TYPE 0x75
52478 +#define VUSB1V8_REMAP 0x76
52479 +#define VUSB3V1_DEV_GRP 0x77
52480 +#define VUSB3V1_TYPE 0x78
52481 +#define VUSB3V1_REMAP 0x79
52482 +
52483 +/* In module TWL4030_MODULE_INTBR */
52484 +#define PMBR1 0x0D
52485 +#define GPIO_USB_4PIN_ULPI_2430C (3 << 0)
52486 +
52487 +struct twl4030_usb {
52488 + struct usb_phy phy;
52489 + struct device *dev;
52490 +
52491 + /* TWL4030 internal USB regulator supplies */
52492 + struct regulator *usb1v5;
52493 + struct regulator *usb1v8;
52494 + struct regulator *usb3v1;
52495 +
52496 + /* for vbus reporting with irqs disabled */
52497 + spinlock_t lock;
52498 +
52499 + /* pin configuration */
52500 + enum twl4030_usb_mode usb_mode;
52501 +
52502 + int irq;
52503 + enum omap_musb_vbus_id_status linkstat;
52504 + bool vbus_supplied;
52505 + u8 asleep;
52506 + bool irq_enabled;
52507 +
52508 + struct delayed_work id_workaround_work;
52509 +};
52510 +
52511 +/* internal define on top of container_of */
52512 +#define phy_to_twl(x) container_of((x), struct twl4030_usb, phy)
52513 +
52514 +/*-------------------------------------------------------------------------*/
52515 +
52516 +static int twl4030_i2c_write_u8_verify(struct twl4030_usb *twl,
52517 + u8 module, u8 data, u8 address)
52518 +{
52519 + u8 check;
52520 +
52521 + if ((twl_i2c_write_u8(module, data, address) >= 0) &&
52522 + (twl_i2c_read_u8(module, &check, address) >= 0) &&
52523 + (check == data))
52524 + return 0;
52525 + dev_dbg(twl->dev, "Write%d[%d,0x%x] wrote %02x but read %02x\n",
52526 + 1, module, address, check, data);
52527 +
52528 + /* Failed once: Try again */
52529 + if ((twl_i2c_write_u8(module, data, address) >= 0) &&
52530 + (twl_i2c_read_u8(module, &check, address) >= 0) &&
52531 + (check == data))
52532 + return 0;
52533 + dev_dbg(twl->dev, "Write%d[%d,0x%x] wrote %02x but read %02x\n",
52534 + 2, module, address, check, data);
52535 +
52536 + /* Failed again: Return error */
52537 + return -EBUSY;
52538 +}
52539 +
52540 +#define twl4030_usb_write_verify(twl, address, data) \
52541 + twl4030_i2c_write_u8_verify(twl, TWL_MODULE_USB, (data), (address))
52542 +
52543 +static inline int twl4030_usb_write(struct twl4030_usb *twl,
52544 + u8 address, u8 data)
52545 +{
52546 + int ret = 0;
52547 +
52548 + ret = twl_i2c_write_u8(TWL_MODULE_USB, data, address);
52549 + if (ret < 0)
52550 + dev_dbg(twl->dev,
52551 + "TWL4030:USB:Write[0x%x] Error %d\n", address, ret);
52552 + return ret;
52553 +}
52554 +
52555 +static inline int twl4030_readb(struct twl4030_usb *twl, u8 module, u8 address)
52556 +{
52557 + u8 data;
52558 + int ret = 0;
52559 +
52560 + ret = twl_i2c_read_u8(module, &data, address);
52561 + if (ret >= 0)
52562 + ret = data;
52563 + else
52564 + dev_dbg(twl->dev,
52565 + "TWL4030:readb[0x%x,0x%x] Error %d\n",
52566 + module, address, ret);
52567 +
52568 + return ret;
52569 +}
52570 +
52571 +static inline int twl4030_usb_read(struct twl4030_usb *twl, u8 address)
52572 +{
52573 + return twl4030_readb(twl, TWL_MODULE_USB, address);
52574 +}
52575 +
52576 +/*-------------------------------------------------------------------------*/
52577 +
52578 +static inline int
52579 +twl4030_usb_set_bits(struct twl4030_usb *twl, u8 reg, u8 bits)
52580 +{
52581 + return twl4030_usb_write(twl, ULPI_SET(reg), bits);
52582 +}
52583 +
52584 +static inline int
52585 +twl4030_usb_clear_bits(struct twl4030_usb *twl, u8 reg, u8 bits)
52586 +{
52587 + return twl4030_usb_write(twl, ULPI_CLR(reg), bits);
52588 +}
52589 +
52590 +/*-------------------------------------------------------------------------*/
52591 +
52592 +static bool twl4030_is_driving_vbus(struct twl4030_usb *twl)
52593 +{
52594 + int ret;
52595 +
52596 + ret = twl4030_usb_read(twl, PHY_CLK_CTRL_STS);
52597 + if (ret < 0 || !(ret & PHY_DPLL_CLK))
52598 + /*
52599 + * if clocks are off, registers are not updated,
52600 + * but we can assume we don't drive VBUS in this case
52601 + */
52602 + return false;
52603 +
52604 + ret = twl4030_usb_read(twl, ULPI_OTG_CTRL);
52605 + if (ret < 0)
52606 + return false;
52607 +
52608 + return (ret & (ULPI_OTG_DRVVBUS | ULPI_OTG_CHRGVBUS)) ? true : false;
52609 +}
52610 +
52611 +static enum omap_musb_vbus_id_status
52612 + twl4030_usb_linkstat(struct twl4030_usb *twl)
52613 +{
52614 + int status;
52615 + enum omap_musb_vbus_id_status linkstat = OMAP_MUSB_UNKNOWN;
52616 +
52617 + twl->vbus_supplied = false;
52618 +
52619 + /*
52620 + * For ID/VBUS sensing, see manual section 15.4.8 ...
52621 + * except when using only battery backup power, two
52622 + * comparators produce VBUS_PRES and ID_PRES signals,
52623 + * which don't match docs elsewhere. But ... BIT(7)
52624 + * and BIT(2) of STS_HW_CONDITIONS, respectively, do
52625 + * seem to match up. If either is true the USB_PRES
52626 + * signal is active, the OTG module is activated, and
52627 + * its interrupt may be raised (may wake the system).
52628 + */
52629 + status = twl4030_readb(twl, TWL_MODULE_PM_MASTER, STS_HW_CONDITIONS);
52630 + if (status < 0)
52631 + dev_err(twl->dev, "USB link status err %d\n", status);
52632 + else if (status & (BIT(7) | BIT(2))) {
52633 + if (status & BIT(7)) {
52634 + if (twl4030_is_driving_vbus(twl))
52635 + status &= ~BIT(7);
52636 + else
52637 + twl->vbus_supplied = true;
52638 + }
52639 +
52640 + if (status & BIT(2))
52641 + linkstat = OMAP_MUSB_ID_GROUND;
52642 + else if (status & BIT(7))
52643 + linkstat = OMAP_MUSB_VBUS_VALID;
52644 + else
52645 + linkstat = OMAP_MUSB_VBUS_OFF;
52646 + } else {
52647 + if (twl->linkstat != OMAP_MUSB_UNKNOWN)
52648 + linkstat = OMAP_MUSB_VBUS_OFF;
52649 + }
52650 +
52651 + dev_dbg(twl->dev, "HW_CONDITIONS 0x%02x/%d; link %d\n",
52652 + status, status, linkstat);
52653 +
52654 + /* REVISIT this assumes host and peripheral controllers
52655 + * are registered, and that both are active...
52656 + */
52657 +
52658 + return linkstat;
52659 +}
52660 +
52661 +static void twl4030_usb_set_mode(struct twl4030_usb *twl, int mode)
52662 +{
52663 + twl->usb_mode = mode;
52664 +
52665 + switch (mode) {
52666 + case T2_USB_MODE_ULPI:
52667 + twl4030_usb_clear_bits(twl, ULPI_IFC_CTRL,
52668 + ULPI_IFC_CTRL_CARKITMODE);
52669 + twl4030_usb_set_bits(twl, POWER_CTRL, POWER_CTRL_OTG_ENAB);
52670 + twl4030_usb_clear_bits(twl, ULPI_FUNC_CTRL,
52671 + ULPI_FUNC_CTRL_XCVRSEL_MASK |
52672 + ULPI_FUNC_CTRL_OPMODE_MASK);
52673 + break;
52674 + case -1:
52675 + /* FIXME: power on defaults */
52676 + break;
52677 + default:
52678 + dev_err(twl->dev, "unsupported T2 transceiver mode %d\n",
52679 + mode);
52680 + break;
52681 + };
52682 +}
52683 +
52684 +static void twl4030_i2c_access(struct twl4030_usb *twl, int on)
52685 +{
52686 + unsigned long timeout;
52687 + int val = twl4030_usb_read(twl, PHY_CLK_CTRL);
52688 +
52689 + if (val >= 0) {
52690 + if (on) {
52691 + /* enable DPLL to access PHY registers over I2C */
52692 + val |= REQ_PHY_DPLL_CLK;
52693 + WARN_ON(twl4030_usb_write_verify(twl, PHY_CLK_CTRL,
52694 + (u8)val) < 0);
52695 +
52696 + timeout = jiffies + HZ;
52697 + while (!(twl4030_usb_read(twl, PHY_CLK_CTRL_STS) &
52698 + PHY_DPLL_CLK)
52699 + && time_before(jiffies, timeout))
52700 + udelay(10);
52701 + if (!(twl4030_usb_read(twl, PHY_CLK_CTRL_STS) &
52702 + PHY_DPLL_CLK))
52703 + dev_err(twl->dev, "Timeout setting T2 HSUSB "
52704 + "PHY DPLL clock\n");
52705 + } else {
52706 + /* let ULPI control the DPLL clock */
52707 + val &= ~REQ_PHY_DPLL_CLK;
52708 + WARN_ON(twl4030_usb_write_verify(twl, PHY_CLK_CTRL,
52709 + (u8)val) < 0);
52710 + }
52711 + }
52712 +}
52713 +
52714 +static void __twl4030_phy_power(struct twl4030_usb *twl, int on)
52715 +{
52716 + u8 pwr = twl4030_usb_read(twl, PHY_PWR_CTRL);
52717 +
52718 + if (on)
52719 + pwr &= ~PHY_PWR_PHYPWD;
52720 + else
52721 + pwr |= PHY_PWR_PHYPWD;
52722 +
52723 + WARN_ON(twl4030_usb_write_verify(twl, PHY_PWR_CTRL, pwr) < 0);
52724 +}
52725 +
52726 +static void twl4030_phy_power(struct twl4030_usb *twl, int on)
52727 +{
52728 + int ret;
52729 +
52730 + if (on) {
52731 + ret = regulator_enable(twl->usb3v1);
52732 + if (ret)
52733 + dev_err(twl->dev, "Failed to enable usb3v1\n");
52734 +
52735 + ret = regulator_enable(twl->usb1v8);
52736 + if (ret)
52737 + dev_err(twl->dev, "Failed to enable usb1v8\n");
52738 +
52739 + /*
52740 + * Disabling usb3v1 regulator (= writing 0 to VUSB3V1_DEV_GRP
52741 + * in twl4030) resets the VUSB_DEDICATED2 register. This reset
52742 + * enables VUSB3V1_SLEEP bit that remaps usb3v1 ACTIVE state to
52743 + * SLEEP. We work around this by clearing the bit after usv3v1
52744 + * is re-activated. This ensures that VUSB3V1 is really active.
52745 + */
52746 + twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB_DEDICATED2);
52747 +
52748 + ret = regulator_enable(twl->usb1v5);
52749 + if (ret)
52750 + dev_err(twl->dev, "Failed to enable usb1v5\n");
52751 +
52752 + __twl4030_phy_power(twl, 1);
52753 + twl4030_usb_write(twl, PHY_CLK_CTRL,
52754 + twl4030_usb_read(twl, PHY_CLK_CTRL) |
52755 + (PHY_CLK_CTRL_CLOCKGATING_EN |
52756 + PHY_CLK_CTRL_CLK32K_EN));
52757 + } else {
52758 + __twl4030_phy_power(twl, 0);
52759 + regulator_disable(twl->usb1v5);
52760 + regulator_disable(twl->usb1v8);
52761 + regulator_disable(twl->usb3v1);
52762 + }
52763 +}
52764 +
52765 +static int twl4030_phy_power_off(struct phy *phy)
52766 +{
52767 + struct twl4030_usb *twl = phy_get_drvdata(phy);
52768 +
52769 + if (twl->asleep)
52770 + return 0;
52771 +
52772 + twl4030_phy_power(twl, 0);
52773 + twl->asleep = 1;
52774 + dev_dbg(twl->dev, "%s\n", __func__);
52775 + return 0;
52776 +}
52777 +
52778 +static void __twl4030_phy_power_on(struct twl4030_usb *twl)
52779 +{
52780 + twl4030_phy_power(twl, 1);
52781 + twl4030_i2c_access(twl, 1);
52782 + twl4030_usb_set_mode(twl, twl->usb_mode);
52783 + if (twl->usb_mode == T2_USB_MODE_ULPI)
52784 + twl4030_i2c_access(twl, 0);
52785 +}
52786 +
52787 +static int twl4030_phy_power_on(struct phy *phy)
52788 +{
52789 + struct twl4030_usb *twl = phy_get_drvdata(phy);
52790 +
52791 + if (!twl->asleep)
52792 + return 0;
52793 + __twl4030_phy_power_on(twl);
52794 + twl->asleep = 0;
52795 + dev_dbg(twl->dev, "%s\n", __func__);
52796 +
52797 + /*
52798 + * XXX When VBUS gets driven after musb goes to A mode,
52799 + * ID_PRES related interrupts no longer arrive, why?
52800 + * Register itself is updated fine though, so we must poll.
52801 + */
52802 + if (twl->linkstat == OMAP_MUSB_ID_GROUND) {
52803 + cancel_delayed_work(&twl->id_workaround_work);
52804 + schedule_delayed_work(&twl->id_workaround_work, HZ);
52805 + }
52806 + return 0;
52807 +}
52808 +
52809 +static int twl4030_usb_ldo_init(struct twl4030_usb *twl)
52810 +{
52811 + /* Enable writing to power configuration registers */
52812 + twl_i2c_write_u8(TWL_MODULE_PM_MASTER, TWL4030_PM_MASTER_KEY_CFG1,
52813 + TWL4030_PM_MASTER_PROTECT_KEY);
52814 +
52815 + twl_i2c_write_u8(TWL_MODULE_PM_MASTER, TWL4030_PM_MASTER_KEY_CFG2,
52816 + TWL4030_PM_MASTER_PROTECT_KEY);
52817 +
52818 + /* Keep VUSB3V1 LDO in sleep state until VBUS/ID change detected*/
52819 + /*twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB_DEDICATED2);*/
52820 +
52821 + /* input to VUSB3V1 LDO is from VBAT, not VBUS */
52822 + twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0x14, VUSB_DEDICATED1);
52823 +
52824 + /* Initialize 3.1V regulator */
52825 + twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB3V1_DEV_GRP);
52826 +
52827 + twl->usb3v1 = devm_regulator_get(twl->dev, "usb3v1");
52828 + if (IS_ERR(twl->usb3v1))
52829 + return -ENODEV;
52830 +
52831 + twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB3V1_TYPE);
52832 +
52833 + /* Initialize 1.5V regulator */
52834 + twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB1V5_DEV_GRP);
52835 +
52836 + twl->usb1v5 = devm_regulator_get(twl->dev, "usb1v5");
52837 + if (IS_ERR(twl->usb1v5))
52838 + return -ENODEV;
52839 +
52840 + twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB1V5_TYPE);
52841 +
52842 + /* Initialize 1.8V regulator */
52843 + twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB1V8_DEV_GRP);
52844 +
52845 + twl->usb1v8 = devm_regulator_get(twl->dev, "usb1v8");
52846 + if (IS_ERR(twl->usb1v8))
52847 + return -ENODEV;
52848 +
52849 + twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB1V8_TYPE);
52850 +
52851 + /* disable access to power configuration registers */
52852 + twl_i2c_write_u8(TWL_MODULE_PM_MASTER, 0,
52853 + TWL4030_PM_MASTER_PROTECT_KEY);
52854 +
52855 + return 0;
52856 +}
52857 +
52858 +static ssize_t twl4030_usb_vbus_show(struct device *dev,
52859 + struct device_attribute *attr, char *buf)
52860 +{
52861 + struct twl4030_usb *twl = dev_get_drvdata(dev);
52862 + unsigned long flags;
52863 + int ret = -EINVAL;
52864 +
52865 + spin_lock_irqsave(&twl->lock, flags);
52866 + ret = sprintf(buf, "%s\n",
52867 + twl->vbus_supplied ? "on" : "off");
52868 + spin_unlock_irqrestore(&twl->lock, flags);
52869 +
52870 + return ret;
52871 +}
52872 +static DEVICE_ATTR(vbus, 0444, twl4030_usb_vbus_show, NULL);
52873 +
52874 +static irqreturn_t twl4030_usb_irq(int irq, void *_twl)
52875 +{
52876 + struct twl4030_usb *twl = _twl;
52877 + enum omap_musb_vbus_id_status status;
52878 + bool status_changed = false;
52879 +
52880 + status = twl4030_usb_linkstat(twl);
52881 +
52882 + spin_lock_irq(&twl->lock);
52883 + if (status >= 0 && status != twl->linkstat) {
52884 + twl->linkstat = status;
52885 + status_changed = true;
52886 + }
52887 + spin_unlock_irq(&twl->lock);
52888 +
52889 + if (status_changed) {
52890 + /* FIXME add a set_power() method so that B-devices can
52891 + * configure the charger appropriately. It's not always
52892 + * correct to consume VBUS power, and how much current to
52893 + * consume is a function of the USB configuration chosen
52894 + * by the host.
52895 + *
52896 + * REVISIT usb_gadget_vbus_connect(...) as needed, ditto
52897 + * its disconnect() sibling, when changing to/from the
52898 + * USB_LINK_VBUS state. musb_hdrc won't care until it
52899 + * starts to handle softconnect right.
52900 + */
52901 + omap_musb_mailbox(status);
52902 + }
52903 + sysfs_notify(&twl->dev->kobj, NULL, "vbus");
52904 +
52905 + return IRQ_HANDLED;
52906 +}
52907 +
52908 +static void twl4030_id_workaround_work(struct work_struct *work)
52909 +{
52910 + struct twl4030_usb *twl = container_of(work, struct twl4030_usb,
52911 + id_workaround_work.work);
52912 + enum omap_musb_vbus_id_status status;
52913 + bool status_changed = false;
52914 +
52915 + status = twl4030_usb_linkstat(twl);
52916 +
52917 + spin_lock_irq(&twl->lock);
52918 + if (status >= 0 && status != twl->linkstat) {
52919 + twl->linkstat = status;
52920 + status_changed = true;
52921 + }
52922 + spin_unlock_irq(&twl->lock);
52923 +
52924 + if (status_changed) {
52925 + dev_dbg(twl->dev, "handle missing status change to %d\n",
52926 + status);
52927 + omap_musb_mailbox(status);
52928 + }
52929 +
52930 + /* don't schedule during sleep - irq works right then */
52931 + if (status == OMAP_MUSB_ID_GROUND && !twl->asleep) {
52932 + cancel_delayed_work(&twl->id_workaround_work);
52933 + schedule_delayed_work(&twl->id_workaround_work, HZ);
52934 + }
52935 +}
52936 +
52937 +static int twl4030_phy_init(struct phy *phy)
52938 +{
52939 + struct twl4030_usb *twl = phy_get_drvdata(phy);
52940 + enum omap_musb_vbus_id_status status;
52941 +
52942 + /*
52943 + * Start in sleep state, we'll get called through set_suspend()
52944 + * callback when musb is runtime resumed and it's time to start.
52945 + */
52946 + __twl4030_phy_power(twl, 0);
52947 + twl->asleep = 1;
52948 +
52949 + status = twl4030_usb_linkstat(twl);
52950 + twl->linkstat = status;
52951 +
52952 + if (status == OMAP_MUSB_ID_GROUND || status == OMAP_MUSB_VBUS_VALID) {
52953 + omap_musb_mailbox(twl->linkstat);
52954 + twl4030_phy_power_on(phy);
52955 + }
52956 +
52957 + sysfs_notify(&twl->dev->kobj, NULL, "vbus");
52958 + return 0;
52959 +}
52960 +
52961 +static int twl4030_set_peripheral(struct usb_otg *otg,
52962 + struct usb_gadget *gadget)
52963 +{
52964 + if (!otg)
52965 + return -ENODEV;
52966 +
52967 + otg->gadget = gadget;
52968 + if (!gadget)
52969 + otg->phy->state = OTG_STATE_UNDEFINED;
52970 +
52971 + return 0;
52972 +}
52973 +
52974 +static int twl4030_set_host(struct usb_otg *otg, struct usb_bus *host)
52975 +{
52976 + if (!otg)
52977 + return -ENODEV;
52978 +
52979 + otg->host = host;
52980 + if (!host)
52981 + otg->phy->state = OTG_STATE_UNDEFINED;
52982 +
52983 + return 0;
52984 +}
52985 +
52986 +static const struct phy_ops ops = {
52987 + .init = twl4030_phy_init,
52988 + .power_on = twl4030_phy_power_on,
52989 + .power_off = twl4030_phy_power_off,
52990 + .owner = THIS_MODULE,
52991 +};
52992 +
52993 +static int twl4030_usb_probe(struct platform_device *pdev)
52994 +{
52995 + struct twl4030_usb_data *pdata = dev_get_platdata(&pdev->dev);
52996 + struct twl4030_usb *twl;
52997 + struct phy *phy;
52998 + int status, err;
52999 + struct usb_otg *otg;
53000 + struct device_node *np = pdev->dev.of_node;
53001 + struct phy_provider *phy_provider;
53002 + struct phy_init_data *init_data = NULL;
53003 +
53004 + twl = devm_kzalloc(&pdev->dev, sizeof *twl, GFP_KERNEL);
53005 + if (!twl)
53006 + return -ENOMEM;
53007 +
53008 + if (np)
53009 + of_property_read_u32(np, "usb_mode",
53010 + (enum twl4030_usb_mode *)&twl->usb_mode);
53011 + else if (pdata) {
53012 + twl->usb_mode = pdata->usb_mode;
53013 + init_data = pdata->init_data;
53014 + } else {
53015 + dev_err(&pdev->dev, "twl4030 initialized without pdata\n");
53016 + return -EINVAL;
53017 + }
53018 +
53019 + otg = devm_kzalloc(&pdev->dev, sizeof *otg, GFP_KERNEL);
53020 + if (!otg)
53021 + return -ENOMEM;
53022 +
53023 + twl->dev = &pdev->dev;
53024 + twl->irq = platform_get_irq(pdev, 0);
53025 + twl->vbus_supplied = false;
53026 + twl->asleep = 1;
53027 + twl->linkstat = OMAP_MUSB_UNKNOWN;
53028 +
53029 + twl->phy.dev = twl->dev;
53030 + twl->phy.label = "twl4030";
53031 + twl->phy.otg = otg;
53032 + twl->phy.type = USB_PHY_TYPE_USB2;
53033 +
53034 + otg->phy = &twl->phy;
53035 + otg->set_host = twl4030_set_host;
53036 + otg->set_peripheral = twl4030_set_peripheral;
53037 +
53038 + phy_provider = devm_of_phy_provider_register(twl->dev,
53039 + of_phy_simple_xlate);
53040 + if (IS_ERR(phy_provider))
53041 + return PTR_ERR(phy_provider);
53042 +
53043 + phy = devm_phy_create(twl->dev, &ops, init_data);
53044 + if (IS_ERR(phy)) {
53045 + dev_dbg(&pdev->dev, "Failed to create PHY\n");
53046 + return PTR_ERR(phy);
53047 + }
53048 +
53049 + phy_set_drvdata(phy, twl);
53050 +
53051 + /* init spinlock for workqueue */
53052 + spin_lock_init(&twl->lock);
53053 +
53054 + INIT_DELAYED_WORK(&twl->id_workaround_work, twl4030_id_workaround_work);
53055 +
53056 + err = twl4030_usb_ldo_init(twl);
53057 + if (err) {
53058 + dev_err(&pdev->dev, "ldo init failed\n");
53059 + return err;
53060 + }
53061 + usb_add_phy_dev(&twl->phy);
53062 +
53063 + platform_set_drvdata(pdev, twl);
53064 + if (device_create_file(&pdev->dev, &dev_attr_vbus))
53065 + dev_warn(&pdev->dev, "could not create sysfs file\n");
53066 +
53067 + ATOMIC_INIT_NOTIFIER_HEAD(&twl->phy.notifier);
53068 +
53069 + /* Our job is to use irqs and status from the power module
53070 + * to keep the transceiver disabled when nothing's connected.
53071 + *
53072 + * FIXME we actually shouldn't start enabling it until the
53073 + * USB controller drivers have said they're ready, by calling
53074 + * set_host() and/or set_peripheral() ... OTG_capable boards
53075 + * need both handles, otherwise just one suffices.
53076 + */
53077 + twl->irq_enabled = true;
53078 + status = devm_request_threaded_irq(twl->dev, twl->irq, NULL,
53079 + twl4030_usb_irq, IRQF_TRIGGER_FALLING |
53080 + IRQF_TRIGGER_RISING | IRQF_ONESHOT, "twl4030_usb", twl);
53081 + if (status < 0) {
53082 + dev_dbg(&pdev->dev, "can't get IRQ %d, err %d\n",
53083 + twl->irq, status);
53084 + return status;
53085 + }
53086 +
53087 + dev_info(&pdev->dev, "Initialized TWL4030 USB module\n");
53088 + return 0;
53089 +}
53090 +
53091 +static int twl4030_usb_remove(struct platform_device *pdev)
53092 +{
53093 + struct twl4030_usb *twl = platform_get_drvdata(pdev);
53094 + int val;
53095 +
53096 + cancel_delayed_work(&twl->id_workaround_work);
53097 + device_remove_file(twl->dev, &dev_attr_vbus);
53098 +
53099 + /* set transceiver mode to power on defaults */
53100 + twl4030_usb_set_mode(twl, -1);
53101 +
53102 + /* autogate 60MHz ULPI clock,
53103 + * clear dpll clock request for i2c access,
53104 + * disable 32KHz
53105 + */
53106 + val = twl4030_usb_read(twl, PHY_CLK_CTRL);
53107 + if (val >= 0) {
53108 + val |= PHY_CLK_CTRL_CLOCKGATING_EN;
53109 + val &= ~(PHY_CLK_CTRL_CLK32K_EN | REQ_PHY_DPLL_CLK);
53110 + twl4030_usb_write(twl, PHY_CLK_CTRL, (u8)val);
53111 + }
53112 +
53113 + /* disable complete OTG block */
53114 + twl4030_usb_clear_bits(twl, POWER_CTRL, POWER_CTRL_OTG_ENAB);
53115 +
53116 + if (!twl->asleep)
53117 + twl4030_phy_power(twl, 0);
53118 +
53119 + return 0;
53120 +}
53121 +
53122 +#ifdef CONFIG_OF
53123 +static const struct of_device_id twl4030_usb_id_table[] = {
53124 + { .compatible = "ti,twl4030-usb" },
53125 + {}
53126 +};
53127 +MODULE_DEVICE_TABLE(of, twl4030_usb_id_table);
53128 +#endif
53129 +
53130 +static struct platform_driver twl4030_usb_driver = {
53131 + .probe = twl4030_usb_probe,
53132 + .remove = twl4030_usb_remove,
53133 + .driver = {
53134 + .name = "twl4030_usb",
53135 + .owner = THIS_MODULE,
53136 + .of_match_table = of_match_ptr(twl4030_usb_id_table),
53137 + },
53138 +};
53139 +
53140 +static int __init twl4030_usb_init(void)
53141 +{
53142 + return platform_driver_register(&twl4030_usb_driver);
53143 +}
53144 +subsys_initcall(twl4030_usb_init);
53145 +
53146 +static void __exit twl4030_usb_exit(void)
53147 +{
53148 + platform_driver_unregister(&twl4030_usb_driver);
53149 +}
53150 +module_exit(twl4030_usb_exit);
53151 +
53152 +MODULE_ALIAS("platform:twl4030_usb");
53153 +MODULE_AUTHOR("Texas Instruments, Inc, Nokia Corporation");
53154 +MODULE_DESCRIPTION("TWL4030 USB transceiver driver");
53155 +MODULE_LICENSE("GPL");
53156 --- a/drivers/regulator/core.c
53157 +++ b/drivers/regulator/core.c
53158 @@ -124,6 +124,51 @@ static const char *rdev_get_name(struct
53159 return "";
53160 }
53161
53162 +static void regulator_lock(struct regulator_dev *rdev)
53163 +{
53164 + struct regulator_dev *locking_rdev = rdev;
53165 +
53166 + while (locking_rdev->supply)
53167 + locking_rdev = locking_rdev->supply->rdev;
53168 +
53169 + if (!mutex_trylock(&locking_rdev->mutex)) {
53170 + if (locking_rdev->lock_owner == current) {
53171 + locking_rdev->lock_count++;
53172 + dev_dbg(&locking_rdev->dev,
53173 + "Is locked. locking %s (ref=%u)\n",
53174 + rdev_get_name(rdev),
53175 + locking_rdev->lock_count);
53176 + return;
53177 + }
53178 + mutex_lock(&locking_rdev->mutex);
53179 + }
53180 +
53181 + WARN_ON_ONCE(locking_rdev->lock_owner != NULL);
53182 + WARN_ON_ONCE(locking_rdev->lock_count != 0);
53183 +
53184 + locking_rdev->lock_count = 1;
53185 + locking_rdev->lock_owner = current;
53186 + dev_dbg(&locking_rdev->dev, "Is locked. locking %s\n",
53187 + rdev_get_name(rdev));
53188 +}
53189 +
53190 +static void regulator_unlock(struct regulator_dev *rdev)
53191 +{
53192 + struct regulator_dev *locking_rdev = rdev;
53193 +
53194 + while (locking_rdev->supply)
53195 + locking_rdev = locking_rdev->supply->rdev;
53196 +
53197 + dev_dbg(&locking_rdev->dev, "Is unlocked. unlocking %s (ref=%u)\n",
53198 + rdev_get_name(rdev), locking_rdev->lock_count);
53199 +
53200 + if (--locking_rdev->lock_count)
53201 + return;
53202 +
53203 + locking_rdev->lock_owner = NULL;
53204 + mutex_unlock(&locking_rdev->mutex);
53205 +}
53206 +
53207 /**
53208 * of_get_regulator - get a regulator device node based on supply name
53209 * @dev: Device pointer for the consumer (of regulator) device
53210 @@ -306,9 +351,9 @@ static ssize_t regulator_uV_show(struct
53211 struct regulator_dev *rdev = dev_get_drvdata(dev);
53212 ssize_t ret;
53213
53214 - mutex_lock(&rdev->mutex);
53215 + regulator_lock(rdev);
53216 ret = sprintf(buf, "%d\n", _regulator_get_voltage(rdev));
53217 - mutex_unlock(&rdev->mutex);
53218 + regulator_unlock(rdev);
53219
53220 return ret;
53221 }
53222 @@ -372,9 +417,9 @@ static ssize_t regulator_state_show(stru
53223 struct regulator_dev *rdev = dev_get_drvdata(dev);
53224 ssize_t ret;
53225
53226 - mutex_lock(&rdev->mutex);
53227 + regulator_lock(rdev);
53228 ret = regulator_print_state(buf, _regulator_is_enabled(rdev));
53229 - mutex_unlock(&rdev->mutex);
53230 + regulator_unlock(rdev);
53231
53232 return ret;
53233 }
53234 @@ -482,10 +527,10 @@ static ssize_t regulator_total_uA_show(s
53235 struct regulator *regulator;
53236 int uA = 0;
53237
53238 - mutex_lock(&rdev->mutex);
53239 + regulator_lock(rdev);
53240 list_for_each_entry(regulator, &rdev->consumer_list, list)
53241 uA += regulator->uA_load;
53242 - mutex_unlock(&rdev->mutex);
53243 + regulator_unlock(rdev);
53244 return sprintf(buf, "%d\n", uA);
53245 }
53246 static DEVICE_ATTR(requested_microamps, 0444, regulator_total_uA_show, NULL);
53247 @@ -1123,7 +1168,7 @@ static struct regulator *create_regulato
53248 if (regulator == NULL)
53249 return NULL;
53250
53251 - mutex_lock(&rdev->mutex);
53252 + regulator_lock(rdev);
53253 regulator->rdev = rdev;
53254 list_add(&regulator->list, &rdev->consumer_list);
53255
53256 @@ -1175,12 +1220,12 @@ static struct regulator *create_regulato
53257 _regulator_is_enabled(rdev))
53258 regulator->always_on = true;
53259
53260 - mutex_unlock(&rdev->mutex);
53261 + regulator_unlock(rdev);
53262 return regulator;
53263 overflow_err:
53264 list_del(&regulator->list);
53265 kfree(regulator);
53266 - mutex_unlock(&rdev->mutex);
53267 + regulator_unlock(rdev);
53268 return NULL;
53269 }
53270
53271 @@ -1774,9 +1819,9 @@ int regulator_enable(struct regulator *r
53272 return ret;
53273 }
53274
53275 - mutex_lock(&rdev->mutex);
53276 + regulator_lock(rdev);
53277 ret = _regulator_enable(rdev);
53278 - mutex_unlock(&rdev->mutex);
53279 + regulator_unlock(rdev);
53280
53281 if (ret != 0 && rdev->supply)
53282 regulator_disable(rdev->supply);
53283 @@ -1866,9 +1911,9 @@ int regulator_disable(struct regulator *
53284 if (regulator->always_on)
53285 return 0;
53286
53287 - mutex_lock(&rdev->mutex);
53288 + regulator_lock(rdev);
53289 ret = _regulator_disable(rdev);
53290 - mutex_unlock(&rdev->mutex);
53291 + regulator_unlock(rdev);
53292
53293 if (ret == 0 && rdev->supply)
53294 regulator_disable(rdev->supply);
53295 @@ -1912,10 +1957,10 @@ int regulator_force_disable(struct regul
53296 struct regulator_dev *rdev = regulator->rdev;
53297 int ret;
53298
53299 - mutex_lock(&rdev->mutex);
53300 + regulator_lock(rdev);
53301 regulator->uA_load = 0;
53302 ret = _regulator_force_disable(regulator->rdev);
53303 - mutex_unlock(&rdev->mutex);
53304 + regulator_unlock(rdev);
53305
53306 if (rdev->supply)
53307 while (rdev->open_count--)
53308 @@ -1931,7 +1976,7 @@ static void regulator_disable_work(struc
53309 disable_work.work);
53310 int count, i, ret;
53311
53312 - mutex_lock(&rdev->mutex);
53313 + regulator_lock(rdev);
53314
53315 BUG_ON(!rdev->deferred_disables);
53316
53317 @@ -1944,7 +1989,7 @@ static void regulator_disable_work(struc
53318 rdev_err(rdev, "Deferred disable failed: %d\n", ret);
53319 }
53320
53321 - mutex_unlock(&rdev->mutex);
53322 + regulator_unlock(rdev);
53323
53324 if (rdev->supply) {
53325 for (i = 0; i < count; i++) {
53326 @@ -1980,9 +2025,9 @@ int regulator_disable_deferred(struct re
53327 if (!ms)
53328 return regulator_disable(regulator);
53329
53330 - mutex_lock(&rdev->mutex);
53331 + regulator_lock(rdev);
53332 rdev->deferred_disables++;
53333 - mutex_unlock(&rdev->mutex);
53334 + regulator_unlock(rdev);
53335
53336 ret = queue_delayed_work(system_power_efficient_wq,
53337 &rdev->disable_work,
53338 @@ -2026,9 +2071,9 @@ int regulator_is_enabled(struct regulato
53339 if (regulator->always_on)
53340 return 1;
53341
53342 - mutex_lock(&regulator->rdev->mutex);
53343 + regulator_lock(regulator->rdev);
53344 ret = _regulator_is_enabled(regulator->rdev);
53345 - mutex_unlock(&regulator->rdev->mutex);
53346 + regulator_unlock(regulator->rdev);
53347
53348 return ret;
53349 }
53350 @@ -2097,9 +2142,9 @@ int regulator_list_voltage(struct regula
53351 if (!ops->list_voltage || selector >= rdev->desc->n_voltages)
53352 return -EINVAL;
53353
53354 - mutex_lock(&rdev->mutex);
53355 + regulator_lock(rdev);
53356 ret = ops->list_voltage(rdev, selector);
53357 - mutex_unlock(&rdev->mutex);
53358 + regulator_unlock(rdev);
53359
53360 if (ret > 0) {
53361 if (ret < rdev->constraints->min_uV)
53362 @@ -2298,7 +2343,7 @@ int regulator_set_voltage(struct regulat
53363 int ret = 0;
53364 int old_min_uV, old_max_uV;
53365
53366 - mutex_lock(&rdev->mutex);
53367 + regulator_lock(rdev);
53368
53369 /* If we're setting the same range as last time the change
53370 * should be a noop (some cpufreq implementations use the same
53371 @@ -2334,12 +2379,12 @@ int regulator_set_voltage(struct regulat
53372 goto out2;
53373
53374 out:
53375 - mutex_unlock(&rdev->mutex);
53376 + regulator_unlock(rdev);
53377 return ret;
53378 out2:
53379 regulator->min_uV = old_min_uV;
53380 regulator->max_uV = old_max_uV;
53381 - mutex_unlock(&rdev->mutex);
53382 + regulator_unlock(rdev);
53383 return ret;
53384 }
53385 EXPORT_SYMBOL_GPL(regulator_set_voltage);
53386 @@ -2442,7 +2487,7 @@ int regulator_sync_voltage(struct regula
53387 struct regulator_dev *rdev = regulator->rdev;
53388 int ret, min_uV, max_uV;
53389
53390 - mutex_lock(&rdev->mutex);
53391 + regulator_lock(rdev);
53392
53393 if (!rdev->desc->ops->set_voltage &&
53394 !rdev->desc->ops->set_voltage_sel) {
53395 @@ -2471,7 +2516,7 @@ int regulator_sync_voltage(struct regula
53396 ret = _regulator_do_set_voltage(rdev, min_uV, max_uV);
53397
53398 out:
53399 - mutex_unlock(&rdev->mutex);
53400 + regulator_unlock(rdev);
53401 return ret;
53402 }
53403 EXPORT_SYMBOL_GPL(regulator_sync_voltage);
53404 @@ -2511,11 +2556,11 @@ int regulator_get_voltage(struct regulat
53405 {
53406 int ret;
53407
53408 - mutex_lock(&regulator->rdev->mutex);
53409 + regulator_lock(regulator->rdev);
53410
53411 ret = _regulator_get_voltage(regulator->rdev);
53412
53413 - mutex_unlock(&regulator->rdev->mutex);
53414 + regulator_unlock(regulator->rdev);
53415
53416 return ret;
53417 }
53418 @@ -2543,7 +2588,7 @@ int regulator_set_current_limit(struct r
53419 struct regulator_dev *rdev = regulator->rdev;
53420 int ret;
53421
53422 - mutex_lock(&rdev->mutex);
53423 + regulator_lock(rdev);
53424
53425 /* sanity check */
53426 if (!rdev->desc->ops->set_current_limit) {
53427 @@ -2558,7 +2603,7 @@ int regulator_set_current_limit(struct r
53428
53429 ret = rdev->desc->ops->set_current_limit(rdev, min_uA, max_uA);
53430 out:
53431 - mutex_unlock(&rdev->mutex);
53432 + regulator_unlock(rdev);
53433 return ret;
53434 }
53435 EXPORT_SYMBOL_GPL(regulator_set_current_limit);
53436 @@ -2567,7 +2612,7 @@ static int _regulator_get_current_limit(
53437 {
53438 int ret;
53439
53440 - mutex_lock(&rdev->mutex);
53441 + regulator_lock(rdev);
53442
53443 /* sanity check */
53444 if (!rdev->desc->ops->get_current_limit) {
53445 @@ -2577,7 +2622,7 @@ static int _regulator_get_current_limit(
53446
53447 ret = rdev->desc->ops->get_current_limit(rdev);
53448 out:
53449 - mutex_unlock(&rdev->mutex);
53450 + regulator_unlock(rdev);
53451 return ret;
53452 }
53453
53454 @@ -2613,7 +2658,7 @@ int regulator_set_mode(struct regulator
53455 int ret;
53456 int regulator_curr_mode;
53457
53458 - mutex_lock(&rdev->mutex);
53459 + regulator_lock(rdev);
53460
53461 /* sanity check */
53462 if (!rdev->desc->ops->set_mode) {
53463 @@ -2637,7 +2682,7 @@ int regulator_set_mode(struct regulator
53464
53465 ret = rdev->desc->ops->set_mode(rdev, mode);
53466 out:
53467 - mutex_unlock(&rdev->mutex);
53468 + regulator_unlock(rdev);
53469 return ret;
53470 }
53471 EXPORT_SYMBOL_GPL(regulator_set_mode);
53472 @@ -2646,7 +2691,7 @@ static unsigned int _regulator_get_mode(
53473 {
53474 int ret;
53475
53476 - mutex_lock(&rdev->mutex);
53477 + regulator_lock(rdev);
53478
53479 /* sanity check */
53480 if (!rdev->desc->ops->get_mode) {
53481 @@ -2656,7 +2701,7 @@ static unsigned int _regulator_get_mode(
53482
53483 ret = rdev->desc->ops->get_mode(rdev);
53484 out:
53485 - mutex_unlock(&rdev->mutex);
53486 + regulator_unlock(rdev);
53487 return ret;
53488 }
53489
53490 @@ -2708,7 +2753,7 @@ int regulator_set_optimum_mode(struct re
53491 if (rdev->supply)
53492 input_uV = regulator_get_voltage(rdev->supply);
53493
53494 - mutex_lock(&rdev->mutex);
53495 + regulator_lock(rdev);
53496
53497 /*
53498 * first check to see if we can set modes at all, otherwise just
53499 @@ -2769,7 +2814,7 @@ int regulator_set_optimum_mode(struct re
53500 }
53501 ret = mode;
53502 out:
53503 - mutex_unlock(&rdev->mutex);
53504 + regulator_unlock(rdev);
53505 return ret;
53506 }
53507 EXPORT_SYMBOL_GPL(regulator_set_optimum_mode);
53508 @@ -2797,7 +2842,7 @@ int regulator_allow_bypass(struct regula
53509 !(rdev->constraints->valid_ops_mask & REGULATOR_CHANGE_BYPASS))
53510 return 0;
53511
53512 - mutex_lock(&rdev->mutex);
53513 + regulator_lock(rdev);
53514
53515 if (enable && !regulator->bypass) {
53516 rdev->bypass_count++;
53517 @@ -2821,7 +2866,7 @@ int regulator_allow_bypass(struct regula
53518 if (ret == 0)
53519 regulator->bypass = enable;
53520
53521 - mutex_unlock(&rdev->mutex);
53522 + regulator_unlock(rdev);
53523
53524 return ret;
53525 }
53526 @@ -3540,9 +3585,9 @@ int regulator_suspend_prepare(suspend_st
53527 mutex_lock(&regulator_list_mutex);
53528 list_for_each_entry(rdev, &regulator_list, list) {
53529
53530 - mutex_lock(&rdev->mutex);
53531 + regulator_lock(rdev);
53532 ret = suspend_prepare(rdev, state);
53533 - mutex_unlock(&rdev->mutex);
53534 + regulator_unlock(rdev);
53535
53536 if (ret < 0) {
53537 rdev_err(rdev, "failed to prepare\n");
53538 @@ -3570,7 +3615,7 @@ int regulator_suspend_finish(void)
53539 list_for_each_entry(rdev, &regulator_list, list) {
53540 struct regulator_ops *ops = rdev->desc->ops;
53541
53542 - mutex_lock(&rdev->mutex);
53543 + regulator_lock(rdev);
53544 if ((rdev->use_count > 0 || rdev->constraints->always_on) &&
53545 ops->enable) {
53546 error = ops->enable(rdev);
53547 @@ -3589,7 +3634,7 @@ int regulator_suspend_finish(void)
53548 ret = error;
53549 }
53550 unlock:
53551 - mutex_unlock(&rdev->mutex);
53552 + regulator_unlock(rdev);
53553 }
53554 mutex_unlock(&regulator_list_mutex);
53555 return ret;
53556 @@ -3777,7 +3822,7 @@ static int __init regulator_init_complet
53557 if (!ops->disable || (c && c->always_on))
53558 continue;
53559
53560 - mutex_lock(&rdev->mutex);
53561 + regulator_lock(rdev);
53562
53563 if (rdev->use_count)
53564 goto unlock;
53565 @@ -3809,7 +3854,7 @@ static int __init regulator_init_complet
53566 }
53567
53568 unlock:
53569 - mutex_unlock(&rdev->mutex);
53570 + regulator_unlock(rdev);
53571 }
53572
53573 mutex_unlock(&regulator_list_mutex);
53574 --- a/drivers/regulator/Kconfig
53575 +++ b/drivers/regulator/Kconfig
53576 @@ -492,6 +492,15 @@ config REGULATOR_TPS65217
53577 voltage regulators. It supports software based voltage control
53578 for different voltage domains
53579
53580 +config REGULATOR_TPS65218
53581 + tristate "TI TPS65218 Power regulators"
53582 + depends on MFD_TPS65218
53583 + help
53584 + This driver supports TPS65218 voltage regulator chips. TPS65218
53585 + provides six step-down converters and one general-purpose LDO
53586 + voltage regulators. It supports software based voltage control
53587 + for different voltage domains
53588 +
53589 config REGULATOR_TPS6524X
53590 tristate "TI TPS6524X Power regulators"
53591 depends on SPI
53592 @@ -571,5 +580,19 @@ config REGULATOR_WM8994
53593 This driver provides support for the voltage regulators on the
53594 WM8994 CODEC.
53595
53596 +config REGULATOR_TIAVSCLASS0
53597 + tristate "Adaptive Voltage Scaling class 0 support for TI SoCs"
53598 + depends on ARCH_OMAP2PLUS
53599 + help
53600 + AVS is a power management technique which finely controls the
53601 + operating voltage of a device in order to optimize (i.e. reduce)
53602 + its power consumption.
53603 + At a given operating point, the voltage is adapted depending on
53604 + static factors (chip manufacturing process) and this adapted
53605 + voltage is made available in an efuse offset.
53606 + AVS is also called SmartReflex on OMAP devices.
53607 +
53608 + Say Y here to enable Adaptive Voltage Scaling class 0 support.
53609 +
53610 endif
53611
53612 --- a/drivers/regulator/Makefile
53613 +++ b/drivers/regulator/Makefile
53614 @@ -63,6 +63,7 @@ obj-$(CONFIG_REGULATOR_TPS65023) += tps6
53615 obj-$(CONFIG_REGULATOR_TPS6507X) += tps6507x-regulator.o
53616 obj-$(CONFIG_REGULATOR_TPS65090) += tps65090-regulator.o
53617 obj-$(CONFIG_REGULATOR_TPS65217) += tps65217-regulator.o
53618 +obj-$(CONFIG_REGULATOR_TPS65218) += tps65218-regulator.o
53619 obj-$(CONFIG_REGULATOR_TPS6524X) += tps6524x-regulator.o
53620 obj-$(CONFIG_REGULATOR_TPS6586X) += tps6586x-regulator.o
53621 obj-$(CONFIG_REGULATOR_TPS65910) += tps65910-regulator.o
53622 @@ -76,6 +77,7 @@ obj-$(CONFIG_REGULATOR_WM831X) += wm831x
53623 obj-$(CONFIG_REGULATOR_WM8350) += wm8350-regulator.o
53624 obj-$(CONFIG_REGULATOR_WM8400) += wm8400-regulator.o
53625 obj-$(CONFIG_REGULATOR_WM8994) += wm8994-regulator.o
53626 +obj-$(CONFIG_REGULATOR_TIAVSCLASS0) += ti-avs-class0-regulator.o
53627
53628
53629 ccflags-$(CONFIG_REGULATOR_DEBUG) += -DDEBUG
53630 --- /dev/null
53631 +++ b/drivers/regulator/ti-avs-class0-regulator.c
53632 @@ -0,0 +1,349 @@
53633 +/*
53634 + * Texas Instrument SmartReflex AVS Class 0 driver
53635 + *
53636 + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
53637 + * Nishanth Menon
53638 + *
53639 + * This program is free software; you can redistribute it and/or modify
53640 + * it under the terms of the GNU General Public License version 2 as
53641 + * published by the Free Software Foundation.
53642 + *
53643 + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
53644 + * kind, whether express or implied; without even the implied warranty
53645 + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
53646 + * GNU General Public License for more details.
53647 + */
53648 +#define pr_fmt(fmt) KBUILD_MODNAME ": %s(): " fmt, __func__
53649 +
53650 +#include <linux/err.h>
53651 +#include <linux/init.h>
53652 +#include <linux/io.h>
53653 +#include <linux/module.h>
53654 +#include <linux/of_device.h>
53655 +#include <linux/of.h>
53656 +#include <linux/platform_device.h>
53657 +#include <linux/regulator/consumer.h>
53658 +#include <linux/regulator/driver.h>
53659 +#include <linux/regulator/machine.h>
53660 +#include <linux/regulator/of_regulator.h>
53661 +#include <linux/slab.h>
53662 +#include <linux/string.h>
53663 +
53664 +/**
53665 + * struct tiavs_class0_data - class data for the regulator instance
53666 + * @desc: regulator descriptor
53667 + * @reg: regulator that will actually set the voltage
53668 + * @volt_set_table: voltage to set data table
53669 + * @current_idx: current index
53670 + * @voltage_tolerance: % tolerance for voltage(optional)
53671 + */
53672 +struct tiavs_class0_data {
53673 + struct regulator_desc desc;
53674 + struct regulator *reg;
53675 + unsigned int *volt_set_table;
53676 + int current_idx;
53677 + u32 voltage_tolerance;
53678 +};
53679 +
53680 +/**
53681 + * tiavs_class0_set_voltage_sel() - set voltage
53682 + * @rdev: regulator device
53683 + * @sel: set voltage corresponding to selector
53684 + *
53685 + * This searches for a best case match and uses the child regulator to set
53686 + * appropriate voltage
53687 + *
53688 + * Return: -ENODEV if no proper regulator data/-EINVAL if no match,bad efuse
53689 + * else returns regulator set result
53690 + */
53691 +static int tiavs_class0_set_voltage_sel(struct regulator_dev *rdev,
53692 + unsigned sel)
53693 +{
53694 + struct tiavs_class0_data *data = rdev_get_drvdata(rdev);
53695 + const struct regulator_desc *desc = rdev->desc;
53696 + struct regulator *reg;
53697 + int vset, ret, tol;
53698 +
53699 + if (!data) {
53700 + pr_err("No regulator drvdata\n");
53701 + return -ENODEV;
53702 + }
53703 +
53704 + reg = data->reg;
53705 + if (!reg) {
53706 + pr_err("No regulator\n");
53707 + return -ENODEV;
53708 + }
53709 +
53710 + if (!desc->n_voltages || !data->volt_set_table) {
53711 + pr_err("No valid voltage table entries?\n");
53712 + return -EINVAL;
53713 + }
53714 +
53715 + if (sel >= desc->n_voltages) {
53716 + pr_err("sel(%d) > max voltage table entries(%d)\n", sel,
53717 + desc->n_voltages);
53718 + return -EINVAL;
53719 + }
53720 +
53721 + vset = data->volt_set_table[sel];
53722 +
53723 + /* Adjust for % tolerance needed */
53724 + tol = DIV_ROUND_UP(vset * data->voltage_tolerance, 100);
53725 + ret = regulator_set_voltage_tol(reg, vset, tol);
53726 + if (!ret)
53727 + data->current_idx = sel;
53728 +
53729 + return ret;
53730 +}
53731 +
53732 +/**
53733 + * tiavs_class0_get_voltage_sel() - Get voltage selector
53734 + * @rdev: regulator device
53735 + *
53736 + * Return: -ENODEV if no proper regulator data/-EINVAL if no data,
53737 + * else returns current index.
53738 + */
53739 +static int tiavs_class0_get_voltage_sel(struct regulator_dev *rdev)
53740 +{
53741 + const struct regulator_desc *desc = rdev->desc;
53742 + struct tiavs_class0_data *data = rdev_get_drvdata(rdev);
53743 +
53744 + if (!data) {
53745 + pr_err("No regulator drvdata\n");
53746 + return -ENODEV;
53747 + }
53748 +
53749 + if (!desc->n_voltages || !data->volt_set_table) {
53750 + pr_err("No valid voltage table entries?\n");
53751 + return -EINVAL;
53752 + }
53753 +
53754 + if (data->current_idx > desc->n_voltages) {
53755 + pr_err("Corrupted data structure?? idx(%d) > n_voltages(%d)\n",
53756 + data->current_idx, desc->n_voltages);
53757 + return -EINVAL;
53758 + }
53759 +
53760 + return data->current_idx;
53761 +}
53762 +
53763 +static struct regulator_ops tiavs_class0_ops = {
53764 + .list_voltage = regulator_list_voltage_table,
53765 +
53766 + .set_voltage_sel = tiavs_class0_set_voltage_sel,
53767 + .get_voltage_sel = tiavs_class0_get_voltage_sel,
53768 +
53769 +};
53770 +
53771 +static const struct of_device_id tiavs_class0_of_match[] = {
53772 + {.compatible = "ti,avsclass0",},
53773 + {},
53774 +};
53775 +
53776 +MODULE_DEVICE_TABLE(of, tiavs_class0_of_match);
53777 +
53778 +/**
53779 + * tiavs_class0_probe() - AVS class 0 probe
53780 + * @pdev: matching platform device
53781 + *
53782 + * We support only device tree provided data here. Once we find a regulator,
53783 + * efuse offsets, we pick up the efuse register voltages store them per
53784 + * instance.
53785 + *
53786 + * Return: if everything goes through, we return 0, else corresponding error
53787 + * value is returned.
53788 + */
53789 +static int tiavs_class0_probe(struct platform_device *pdev)
53790 +{
53791 + const struct of_device_id *match;
53792 + struct device_node *np = pdev->dev.of_node;
53793 + struct property *prop;
53794 + struct resource *res;
53795 + struct regulator *reg;
53796 + struct regulator_init_data *initdata = NULL;
53797 + struct regulator_config config = { };
53798 + struct regulation_constraints *c;
53799 + struct regulator_dev *rdev;
53800 + struct regulator_desc *desc;
53801 + struct tiavs_class0_data *data;
53802 + void __iomem *base;
53803 + const __be32 *val;
53804 + unsigned int *volt_table;
53805 + bool efuse_is_uV = false;
53806 + int proplen, i, ret;
53807 + int reg_v, min_uV = INT_MAX, max_uV = 0;
53808 + int best_val = INT_MAX, choice = -EINVAL;
53809 +
53810 + match = of_match_device(tiavs_class0_of_match, &pdev->dev);
53811 + if (match)
53812 + initdata = of_get_regulator_init_data(&pdev->dev, np);
53813 + if (!initdata) {
53814 + dev_err(&pdev->dev, "No proper OF?\n");
53815 + return -ENODEV;
53816 + }
53817 +
53818 + /* look for avs-supply */
53819 + reg = devm_regulator_get(&pdev->dev, "avs");
53820 + if (IS_ERR(reg)) {
53821 + ret = PTR_ERR(reg);
53822 + reg = NULL;
53823 + dev_err(&pdev->dev, "avs_class0 regulator not available(%d)\n",
53824 + ret);
53825 + return ret;
53826 + }
53827 +
53828 + data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
53829 + if (!data) {
53830 + dev_err(&pdev->dev, "No memory to alloc data!\n");
53831 + return -ENOMEM;
53832 + }
53833 + data->reg = reg;
53834 +
53835 + desc = &data->desc;
53836 + desc->name = dev_name(&pdev->dev);
53837 + desc->owner = THIS_MODULE;
53838 + desc->type = REGULATOR_VOLTAGE;
53839 + desc->ops = &tiavs_class0_ops;
53840 +
53841 + /* pick up optional properties */
53842 + of_property_read_u32(np, "voltage-tolerance", &data->voltage_tolerance);
53843 + efuse_is_uV = of_property_read_bool(np,
53844 + "ti,avsclass0-microvolt-values");
53845 +
53846 + /* pick up Efuse based voltages */
53847 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
53848 + if (!res) {
53849 + dev_err(&pdev->dev, "Unable to get IO resource\n");
53850 + return -ENODEV;
53851 + }
53852 +
53853 + base = devm_ioremap_nocache(&pdev->dev, res->start, resource_size(res));
53854 + if (!base) {
53855 + dev_err(&pdev->dev, "Unable to map Efuse registers\n");
53856 + return -ENOMEM;
53857 + }
53858 +
53859 + /* Fetch efuse-settings. */
53860 + prop = of_find_property(np, "efuse-settings", NULL);
53861 + if (!prop) {
53862 + dev_err(&pdev->dev, "No 'efuse-settings' property found\n");
53863 + return -EINVAL;
53864 + }
53865 +
53866 + proplen = prop->length / sizeof(int);
53867 +
53868 + data->volt_set_table =
53869 + devm_kzalloc(&pdev->dev, sizeof(unsigned int) * (proplen / 2),
53870 + GFP_KERNEL);
53871 + if (!data->volt_set_table) {
53872 + dev_err(&pdev->dev, "Unable to Allocate voltage set table\n");
53873 + return -ENOMEM;
53874 + }
53875 +
53876 + volt_table =
53877 + devm_kzalloc(&pdev->dev, sizeof(unsigned int) * (proplen / 2),
53878 + GFP_KERNEL);
53879 + if (!volt_table) {
53880 + dev_err(&pdev->dev,
53881 + "Unable to Allocate voltage lookup table\n");
53882 + return -ENOMEM;
53883 + }
53884 +
53885 + val = prop->value;
53886 + for (i = 0; i < proplen / 2; i++) {
53887 + u32 efuse_offset;
53888 +
53889 + volt_table[i] = be32_to_cpup(val++);
53890 + efuse_offset = be32_to_cpup(val++);
53891 +
53892 + data->volt_set_table[i] = efuse_is_uV ?
53893 + readl(base + efuse_offset) :
53894 + readw(base + efuse_offset) * 1000;
53895 +
53896 + /* Find min/max for the voltage sets */
53897 + if (min_uV > volt_table[i])
53898 + min_uV = volt_table[i];
53899 + if (max_uV < volt_table[i])
53900 + max_uV = volt_table[i];
53901 +
53902 + dev_dbg(&pdev->dev, "[%d] efuse=0x%08x volt_table=%d vset=%d\n",
53903 + i, efuse_offset, volt_table[i],
53904 + data->volt_set_table[i]);
53905 + }
53906 + desc->n_voltages = i;
53907 + desc->volt_table = volt_table;
53908 +
53909 + /* Search for a best match voltage */
53910 + reg_v = regulator_get_voltage(reg);
53911 + if (reg_v < 0) {
53912 + dev_err(&pdev->dev, "Regulator error %d for get_voltage!\n",
53913 + reg_v);
53914 + return reg_v;
53915 + }
53916 +
53917 + for (i = 0; i < desc->n_voltages; i++)
53918 + if (data->volt_set_table[i] < best_val &&
53919 + data->volt_set_table[i] >= reg_v) {
53920 + best_val = data->volt_set_table[i];
53921 + choice = i;
53922 + }
53923 +
53924 + if (choice == -EINVAL) {
53925 + dev_err(&pdev->dev, "No match regulator V=%d\n", reg_v);
53926 + return -EINVAL;
53927 + }
53928 + data->current_idx = choice;
53929 +
53930 + /*
53931 + * Constrain board-specific capabilities according to what
53932 + * this driver can actually do.
53933 + */
53934 + c = &initdata->constraints;
53935 + if (desc->n_voltages > 1)
53936 + c->valid_ops_mask |= REGULATOR_CHANGE_VOLTAGE;
53937 + c->always_on = true;
53938 +
53939 + c->min_uV = min_uV;
53940 + c->max_uV = max_uV;
53941 +
53942 + config.dev = &pdev->dev;
53943 + config.init_data = initdata;
53944 + config.driver_data = data;
53945 + config.of_node = pdev->dev.of_node;
53946 +
53947 + rdev = regulator_register(desc, &config);
53948 + if (IS_ERR(rdev)) {
53949 + dev_err(&pdev->dev, "can't register %s, %ld\n",
53950 + desc->name, PTR_ERR(rdev));
53951 + return PTR_ERR(rdev);
53952 + }
53953 + platform_set_drvdata(pdev, rdev);
53954 +
53955 + return 0;
53956 +}
53957 +
53958 +static int tiavs_class0_remove(struct platform_device *pdev)
53959 +{
53960 + struct regulator_dev *rdev = platform_get_drvdata(pdev);
53961 +
53962 + regulator_unregister(rdev);
53963 + return 0;
53964 +}
53965 +
53966 +MODULE_ALIAS("platform:tiavs_class0");
53967 +
53968 +static struct platform_driver tiavs_class0_driver = {
53969 + .probe = tiavs_class0_probe,
53970 + .remove = tiavs_class0_remove,
53971 + .driver = {
53972 + .name = "tiavs_class0",
53973 + .owner = THIS_MODULE,
53974 + .of_match_table = of_match_ptr(tiavs_class0_of_match),
53975 + },
53976 +};
53977 +module_platform_driver(tiavs_class0_driver);
53978 +
53979 +MODULE_DESCRIPTION("TI SmartReflex AVS class 0 regulator driver");
53980 +MODULE_AUTHOR("Texas Instruments Inc.");
53981 +MODULE_LICENSE("GPL v2");
53982 --- /dev/null
53983 +++ b/drivers/regulator/tps65218-regulator.c
53984 @@ -0,0 +1,392 @@
53985 +/*
53986 + * tps65218-regulator.c
53987 + *
53988 + * Regulator driver for TPS65218 PMIC
53989 + *
53990 + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
53991 + *
53992 + * This program is free software; you can redistribute it and/or
53993 + * modify it under the terms of the GNU General Public License version 2 as
53994 + * published by the Free Software Foundation.
53995 + *
53996 + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
53997 + * kind, whether expressed or implied; without even the implied warranty
53998 + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
53999 + * GNU General Public License version 2 for more details.
54000 + */
54001 +
54002 +#include <linux/kernel.h>
54003 +#include <linux/module.h>
54004 +#include <linux/device.h>
54005 +#include <linux/init.h>
54006 +#include <linux/err.h>
54007 +#include <linux/platform_device.h>
54008 +#include <linux/of_device.h>
54009 +#include <linux/regulator/of_regulator.h>
54010 +#include <linux/regulator/driver.h>
54011 +#include <linux/regulator/machine.h>
54012 +#include <linux/mfd/tps65218.h>
54013 +
54014 +static unsigned int tps65218_ramp_delay = 4000;
54015 +
54016 +#define TPS65218_REGULATOR(_name, _id, _ops, _n, _vr, _vm, _er, _em, _t) \
54017 + { \
54018 + .name = _name, \
54019 + .id = _id, \
54020 + .ops = &_ops, \
54021 + .n_voltages = _n, \
54022 + .type = REGULATOR_VOLTAGE, \
54023 + .owner = THIS_MODULE, \
54024 + .vsel_reg = _vr, \
54025 + .vsel_mask = _vm, \
54026 + .enable_reg = _er, \
54027 + .enable_mask = _em, \
54028 + .volt_table = _t, \
54029 + } \
54030 +
54031 +#define TPS65218_INFO(_id, _nm, _min, _max, _f1, _f2) \
54032 + { \
54033 + .id = _id, \
54034 + .name = _nm, \
54035 + .min_uV = _min, \
54036 + .max_uV = _max, \
54037 + .vsel_to_uv = _f1, \
54038 + .uv_to_vsel = _f2, \
54039 + }
54040 +
54041 +static int tps65218_ldo1_dcdc3_vsel_to_uv(unsigned int vsel)
54042 +{
54043 + int uV = 0;
54044 +
54045 + if (vsel <= 26)
54046 + uV = vsel * 25000 + 900000;
54047 + else
54048 + uV = (vsel - 26) * 50000 + 1550000;
54049 +
54050 + return uV;
54051 +}
54052 +
54053 +static int tps65218_ldo1_dcdc3_uv_to_vsel(int uV, unsigned int *vsel)
54054 +{
54055 + if (uV <= 15500000)
54056 + *vsel = DIV_ROUND_UP(uV - 900000, 25000);
54057 + else
54058 + *vsel = 26 + DIV_ROUND_UP(uV - 1550000, 50000);
54059 +
54060 + return 0;
54061 +}
54062 +
54063 +static int tps65218_dcdc1_2_vsel_to_uv(unsigned int vsel)
54064 +{
54065 + int uV = 0;
54066 +
54067 + if (vsel <= 50)
54068 + uV = vsel * 10000 + 850000;
54069 + else
54070 + uV = (vsel - 50) * 25000 + 1350000;
54071 +
54072 + return uV;
54073 +}
54074 +
54075 +static int tps65218_dcdc1_2_uv_to_vsel(int uV, unsigned int *vsel)
54076 +{
54077 + if (uV <= 13500000)
54078 + *vsel = DIV_ROUND_UP(uV - 850000, 10000);
54079 + else
54080 + *vsel = 50 + DIV_ROUND_UP(uV - 1350000, 25000);
54081 +
54082 + return 0;
54083 +}
54084 +
54085 +static int tps65218_dcd4_vsel_to_uv(unsigned int vsel)
54086 +{
54087 + int uV = 0;
54088 +
54089 + if (vsel <= 15)
54090 + uV = vsel * 25000 + 1175000;
54091 + else
54092 + uV = (vsel - 15) * 50000 + 1550000;
54093 +
54094 + return uV;
54095 +}
54096 +
54097 +static int tps65218_dcdc4_uv_to_vsel(int uV, unsigned int *vsel)
54098 +{
54099 + if (uV <= 15500000)
54100 + *vsel = DIV_ROUND_UP(uV - 1175000, 25000);
54101 + else
54102 + *vsel = 15 + DIV_ROUND_UP(uV - 1550000, 50000);
54103 +
54104 + return 0;
54105 +}
54106 +
54107 +static struct tps_info tps65218_pmic_regs[] = {
54108 + TPS65218_INFO(0, "DCDC1", 850000, 1675000, tps65218_dcdc1_2_vsel_to_uv,
54109 + tps65218_dcdc1_2_uv_to_vsel),
54110 + TPS65218_INFO(1, "DCDC2", 850000, 1675000, tps65218_dcdc1_2_vsel_to_uv,
54111 + tps65218_dcdc1_2_uv_to_vsel),
54112 + TPS65218_INFO(2, "DCDC3", 900000, 3400000,
54113 + tps65218_ldo1_dcdc3_vsel_to_uv,
54114 + tps65218_ldo1_dcdc3_uv_to_vsel),
54115 + TPS65218_INFO(3, "DCDC4", 1175000, 3400000, tps65218_dcd4_vsel_to_uv,
54116 + tps65218_dcdc4_uv_to_vsel),
54117 + TPS65218_INFO(4, "DCDC5", 1000000, 1000000, NULL, NULL),
54118 + TPS65218_INFO(5, "DCDC6", 1800000, 1800000, NULL, NULL),
54119 + TPS65218_INFO(6, "LDO1", 900000, 3400000,
54120 + tps65218_ldo1_dcdc3_vsel_to_uv,
54121 + tps65218_ldo1_dcdc3_uv_to_vsel),
54122 +};
54123 +
54124 +#define TPS65218_OF_MATCH(comp, label) \
54125 + { \
54126 + .compatible = comp, \
54127 + .data = &label, \
54128 + }
54129 +
54130 +static const struct of_device_id tps65218_of_match[] = {
54131 + TPS65218_OF_MATCH("ti,tps65218-dcdc1", tps65218_pmic_regs[0]),
54132 + TPS65218_OF_MATCH("ti,tps65218-dcdc2", tps65218_pmic_regs[1]),
54133 + TPS65218_OF_MATCH("ti,tps65218-dcdc3", tps65218_pmic_regs[2]),
54134 + TPS65218_OF_MATCH("ti,tps65218-dcdc4", tps65218_pmic_regs[3]),
54135 + TPS65218_OF_MATCH("ti,tps65218-dcdc5", tps65218_pmic_regs[4]),
54136 + TPS65218_OF_MATCH("ti,tps65218-dcdc6", tps65218_pmic_regs[5]),
54137 + TPS65218_OF_MATCH("ti,tps65218-ldo1", tps65218_pmic_regs[6]),
54138 +};
54139 +MODULE_DEVICE_TABLE(of, tps65218_of_match);
54140 +
54141 +static int tps65218_pmic_set_voltage_sel(struct regulator_dev *dev,
54142 + unsigned selector)
54143 +{
54144 + int ret;
54145 + struct tps65218 *tps = rdev_get_drvdata(dev);
54146 + unsigned int rid = rdev_get_id(dev);
54147 +
54148 + /* Set the voltage based on vsel value and write protect level is 2 */
54149 + ret = tps65218_set_bits(tps, dev->desc->vsel_reg, dev->desc->vsel_mask,
54150 + selector, TPS65218_PROTECT_L1);
54151 +
54152 + /* Set GO bit for DCDC1/2 to initiate voltage transistion */
54153 + switch (rid) {
54154 + case TPS65218_DCDC_1:
54155 + case TPS65218_DCDC_2:
54156 + ret = tps65218_set_bits(tps, TPS65218_REG_CONTRL_SLEW_RATE,
54157 + TPS65218_SLEW_RATE_GO,
54158 + TPS65218_SLEW_RATE_GO,
54159 + TPS65218_PROTECT_L1);
54160 + break;
54161 + }
54162 +
54163 + return ret;
54164 +}
54165 +
54166 +static int tps65218_pmic_map_voltage(struct regulator_dev *dev,
54167 + int min_uV, int max_uV)
54168 +{
54169 + struct tps65218 *tps = rdev_get_drvdata(dev);
54170 + unsigned int sel, rid = rdev_get_id(dev);
54171 + int ret;
54172 +
54173 + if (rid < TPS65218_DCDC_1 || rid > TPS65218_LDO_1)
54174 + return -EINVAL;
54175 +
54176 + if (min_uV < tps->info[rid]->min_uV)
54177 + min_uV = tps->info[rid]->min_uV;
54178 +
54179 + if (max_uV < tps->info[rid]->min_uV || min_uV > tps->info[rid]->max_uV)
54180 + return -EINVAL;
54181 +
54182 + ret = tps->info[rid]->uv_to_vsel(min_uV, &sel);
54183 + if (ret)
54184 + return ret;
54185 +
54186 + return sel;
54187 +}
54188 +
54189 +static int tps65218_pmic_list_voltage(struct regulator_dev *dev,
54190 + unsigned selector)
54191 +{
54192 + struct tps65218 *tps = rdev_get_drvdata(dev);
54193 + unsigned int rid = rdev_get_id(dev);
54194 +
54195 + if (rid < TPS65218_DCDC_1 || rid > TPS65218_LDO_1)
54196 + return -EINVAL;
54197 +
54198 + if (selector >= dev->desc->n_voltages)
54199 + return -EINVAL;
54200 +
54201 + return tps->info[rid]->vsel_to_uv(selector);
54202 +}
54203 +
54204 +static int tps65218_pmic_enable(struct regulator_dev *dev)
54205 +{
54206 + struct tps65218 *tps = rdev_get_drvdata(dev);
54207 + unsigned int rid = rdev_get_id(dev);
54208 +
54209 + if (rid < TPS65218_DCDC_1 || rid > TPS65218_LDO_1)
54210 + return -EINVAL;
54211 +
54212 + /* Enable the regulator and password protection is level 1 */
54213 + return tps65218_set_bits(tps, dev->desc->enable_reg,
54214 + dev->desc->enable_mask, dev->desc->enable_mask,
54215 + TPS65218_PROTECT_L1);
54216 +}
54217 +
54218 +static int tps65218_pmic_disable(struct regulator_dev *dev)
54219 +{
54220 + struct tps65218 *tps = rdev_get_drvdata(dev);
54221 + unsigned int rid = rdev_get_id(dev);
54222 +
54223 + if (rid < TPS65218_DCDC_1 || rid > TPS65218_LDO_1)
54224 + return -EINVAL;
54225 +
54226 + /* Disable the regulator and password protection is level 1 */
54227 + return tps65218_clear_bits(tps, dev->desc->enable_reg,
54228 + dev->desc->enable_mask, TPS65218_PROTECT_L1);
54229 +}
54230 +
54231 +static int tps65218_set_voltage_time_sel(struct regulator_dev *rdev,
54232 + unsigned int old_selector, unsigned int new_selector)
54233 +{
54234 + int old_uv, new_uv;
54235 +
54236 + old_uv = tps65218_pmic_list_voltage(rdev, old_selector);
54237 + if (old_uv < 0)
54238 + return old_uv;
54239 +
54240 + new_uv = tps65218_pmic_list_voltage(rdev, new_selector);
54241 + if (new_uv < 0)
54242 + return new_uv;
54243 +
54244 + return DIV_ROUND_UP(abs(old_uv - new_uv), tps65218_ramp_delay);
54245 +}
54246 +
54247 +/* Operations permitted on DCDC1, DCDC2 */
54248 +static struct regulator_ops tps65218_dcdc12_ops = {
54249 + .is_enabled = regulator_is_enabled_regmap,
54250 + .enable = tps65218_pmic_enable,
54251 + .disable = tps65218_pmic_disable,
54252 + .get_voltage_sel = regulator_get_voltage_sel_regmap,
54253 + .set_voltage_sel = tps65218_pmic_set_voltage_sel,
54254 + .list_voltage = tps65218_pmic_list_voltage,
54255 + .map_voltage = tps65218_pmic_map_voltage,
54256 + .set_voltage_time_sel = tps65218_set_voltage_time_sel,
54257 +};
54258 +
54259 +/* Operations permitted on DCDC3, DCDC4 and LDO1 */
54260 +static struct regulator_ops tps65218_ldo1_dcdc34_ops = {
54261 + .is_enabled = regulator_is_enabled_regmap,
54262 + .enable = tps65218_pmic_enable,
54263 + .disable = tps65218_pmic_disable,
54264 + .get_voltage_sel = regulator_get_voltage_sel_regmap,
54265 + .set_voltage_sel = tps65218_pmic_set_voltage_sel,
54266 + .list_voltage = tps65218_pmic_list_voltage,
54267 + .map_voltage = tps65218_pmic_map_voltage,
54268 +};
54269 +
54270 +/* Operations permitted on DCDC5, DCDC6 */
54271 +static struct regulator_ops tps65218_dcdc56_pmic_ops = {
54272 + .is_enabled = regulator_is_enabled_regmap,
54273 + .enable = tps65218_pmic_enable,
54274 + .disable = tps65218_pmic_disable,
54275 +};
54276 +
54277 +static const struct regulator_desc regulators[] = {
54278 + TPS65218_REGULATOR("DCDC1", TPS65218_DCDC_1, tps65218_dcdc12_ops, 64,
54279 + TPS65218_REG_CONTROL_DCDC1,
54280 + TPS65218_CONTROL_DCDC1_MASK,
54281 + TPS65218_REG_ENABLE1, TPS65218_ENABLE1_DC1_EN, NULL),
54282 + TPS65218_REGULATOR("DCDC2", TPS65218_DCDC_2, tps65218_dcdc12_ops, 64,
54283 + TPS65218_REG_CONTROL_DCDC2,
54284 + TPS65218_CONTROL_DCDC2_MASK,
54285 + TPS65218_REG_ENABLE1, TPS65218_ENABLE1_DC2_EN, NULL),
54286 + TPS65218_REGULATOR("DCDC3", TPS65218_DCDC_3, tps65218_ldo1_dcdc34_ops,
54287 + 64, TPS65218_REG_CONTROL_DCDC3,
54288 + TPS65218_CONTROL_DCDC3_MASK, TPS65218_REG_ENABLE1,
54289 + TPS65218_ENABLE1_DC3_EN, NULL),
54290 + TPS65218_REGULATOR("DCDC4", TPS65218_DCDC_4, tps65218_ldo1_dcdc34_ops,
54291 + 53, TPS65218_REG_CONTROL_DCDC4,
54292 + TPS65218_CONTROL_DCDC4_MASK,
54293 + TPS65218_REG_ENABLE1, TPS65218_ENABLE1_DC4_EN, NULL),
54294 + TPS65218_REGULATOR("DCDC5", TPS65218_DCDC_5, tps65218_dcdc56_pmic_ops,
54295 + 1, -1, -1, TPS65218_REG_ENABLE1,
54296 + TPS65218_ENABLE1_DC5_EN, NULL),
54297 + TPS65218_REGULATOR("DCDC6", TPS65218_DCDC_6, tps65218_dcdc56_pmic_ops,
54298 + 1, -1, -1, TPS65218_REG_ENABLE1,
54299 + TPS65218_ENABLE1_DC6_EN, NULL),
54300 + TPS65218_REGULATOR("LDO1", TPS65218_LDO_1, tps65218_ldo1_dcdc34_ops, 64,
54301 + TPS65218_REG_CONTROL_DCDC4,
54302 + TPS65218_CONTROL_LDO1_MASK, TPS65218_REG_ENABLE2,
54303 + TPS65218_ENABLE2_LDO1_EN, NULL),
54304 +};
54305 +
54306 +static int tps65218_regulator_probe(struct platform_device *pdev)
54307 +{
54308 + struct tps65218 *tps = dev_get_drvdata(pdev->dev.parent);
54309 + struct regulator_init_data *init_data;
54310 + const struct tps_info *template;
54311 + struct regulator_dev *rdev;
54312 + const struct of_device_id *match;
54313 + struct regulator_config config = { };
54314 + int id;
54315 +
54316 + match = of_match_device(tps65218_of_match, &pdev->dev);
54317 + if (match) {
54318 + template = match->data;
54319 + id = template->id;
54320 + init_data = of_get_regulator_init_data(&pdev->dev,
54321 + pdev->dev.of_node);
54322 + } else {
54323 + return -ENODEV;
54324 + }
54325 +
54326 + platform_set_drvdata(pdev, tps);
54327 +
54328 + tps->info[id] = &tps65218_pmic_regs[id];
54329 + config.dev = &pdev->dev;
54330 + config.init_data = init_data;
54331 + config.driver_data = tps;
54332 + config.regmap = tps->regmap;
54333 +
54334 + rdev = regulator_register(&regulators[id], &config);
54335 + if (IS_ERR(rdev)) {
54336 + dev_err(tps->dev, "failed to register %s regulator\n",
54337 + pdev->name);
54338 + return PTR_ERR(rdev);
54339 + }
54340 +
54341 + /* Save regulator */
54342 + tps->rdev[id] = rdev;
54343 +
54344 + return 0;
54345 +}
54346 +
54347 +static int tps65218_regulator_remove(struct platform_device *pdev)
54348 +{
54349 + struct tps65218 *tps = platform_get_drvdata(pdev);
54350 + const struct of_device_id *match;
54351 + const struct tps_info *template;
54352 +
54353 + match = of_match_device(tps65218_of_match, &pdev->dev);
54354 + template = match->data;
54355 + regulator_unregister(tps->rdev[template->id]);
54356 + platform_set_drvdata(pdev, NULL);
54357 +
54358 + return 0;
54359 +}
54360 +
54361 +static struct platform_driver tps65218_regulator_driver = {
54362 + .driver = {
54363 + .name = "tps65218-pmic",
54364 + .owner = THIS_MODULE,
54365 + .of_match_table = of_match_ptr(tps65218_of_match),
54366 + },
54367 + .probe = tps65218_regulator_probe,
54368 + .remove = tps65218_regulator_remove,
54369 +};
54370 +
54371 +module_platform_driver(tps65218_regulator_driver);
54372 +
54373 +MODULE_AUTHOR("J Keerthy <j-keerthy@ti.com>");
54374 +MODULE_DESCRIPTION("TPS65218 voltage regulator driver");
54375 +MODULE_ALIAS("platform:tps65218-pmic");
54376 +MODULE_LICENSE("GPL v2");
54377 --- a/drivers/reset/core.c
54378 +++ b/drivers/reset/core.c
54379 @@ -127,6 +127,38 @@ int reset_control_deassert(struct reset_
54380 EXPORT_SYMBOL_GPL(reset_control_deassert);
54381
54382 /**
54383 + * reset_control_is_reset - check reset status
54384 + * @rstc: reset controller
54385 + *
54386 + * Returns a boolean or negative error code
54387 + *
54388 + */
54389 +int reset_control_is_reset(struct reset_control *rstc)
54390 +{
54391 + if (rstc->rcdev->ops->is_reset)
54392 + return rstc->rcdev->ops->is_reset(rstc->rcdev, rstc->id);
54393 +
54394 + return -ENOSYS;
54395 +}
54396 +EXPORT_SYMBOL_GPL(reset_control_is_reset);
54397 +
54398 +/**
54399 + * reset_control_clear_reset - clear the reset
54400 + * @rstc: reset controller
54401 + *
54402 + * Returns zero on success or negative error code
54403 + *
54404 + */
54405 +int reset_control_clear_reset(struct reset_control *rstc)
54406 +{
54407 + if (rstc->rcdev->ops->clear_reset)
54408 + return rstc->rcdev->ops->clear_reset(rstc->rcdev, rstc->id);
54409 +
54410 + return -ENOSYS;
54411 +}
54412 +EXPORT_SYMBOL_GPL(reset_control_clear_reset);
54413 +
54414 +/**
54415 * reset_control_get - Lookup and obtain a reference to a reset controller.
54416 * @dev: device to be reset by the controller
54417 * @id: reset line name
54418 --- a/drivers/reset/Kconfig
54419 +++ b/drivers/reset/Kconfig
54420 @@ -11,3 +11,17 @@ menuconfig RESET_CONTROLLER
54421 via GPIOs or SoC-internal reset controller modules.
54422
54423 If unsure, say no.
54424 +
54425 +if RESET_CONTROLLER
54426 +
54427 +config RESET_TI
54428 + bool "TI reset controller"
54429 + help
54430 + Reset controller support for TI SoC's
54431 +
54432 + Reset controller found in TI's AM series of SoC's like
54433 + AM335x and AM43x and OMAP SoC's like OMAP5 and DRA7
54434 +
54435 + If unsure, say no.
54436 +
54437 +endif
54438 --- a/drivers/reset/Makefile
54439 +++ b/drivers/reset/Makefile
54440 @@ -1 +1,2 @@
54441 obj-$(CONFIG_RESET_CONTROLLER) += core.o
54442 +obj-$(CONFIG_RESET_TI) += ti_reset.o
54443 --- /dev/null
54444 +++ b/drivers/reset/ti_reset.c
54445 @@ -0,0 +1,172 @@
54446 +/*
54447 + * PRCM reset driver for TI SoC's
54448 + *
54449 + * This program is free software; you can redistribute it and/or modify
54450 + * it under the terms of the GNU General Public License as published by
54451 + * the Free Software Foundation; either version 2 of the License, or
54452 + * (at your option) any later version.
54453 + */
54454 +#include <linux/device.h>
54455 +#include <linux/err.h>
54456 +#include <linux/kernel.h>
54457 +#include <linux/module.h>
54458 +#include <linux/of_device.h>
54459 +#include <linux/reset.h>
54460 +#include <linux/reset-controller.h>
54461 +#include <linux/platform_device.h>
54462 +#include <linux/io.h>
54463 +
54464 +#define DRIVER_NAME "ti_reset"
54465 +
54466 +struct ti_reset_reg_data {
54467 + u32 rstctrl_offs;
54468 + u32 rstst_offs;
54469 + u8 rstctrl_bit;
54470 + u8 rstst_bit;
54471 +};
54472 +
54473 +struct ti_reset_data {
54474 + struct ti_reset_reg_data *reg_data;
54475 + u8 nr_resets;
54476 +};
54477 +
54478 +static void __iomem *reg_base;
54479 +static const struct ti_reset_data *reset_data;
54480 +
54481 +static struct ti_reset_reg_data am335x_reset_reg_data[] = {
54482 + {
54483 + .rstctrl_offs = 0x1104,
54484 + .rstst_offs = 0x1114,
54485 + .rstctrl_bit = 0,
54486 + .rstst_bit = 0,
54487 + },
54488 +};
54489 +
54490 +static struct ti_reset_data am335x_reset_data = {
54491 + .reg_data = am335x_reset_reg_data,
54492 + .nr_resets = ARRAY_SIZE(am335x_reset_reg_data),
54493 +};
54494 +
54495 +static struct ti_reset_reg_data am43x_reset_reg_data[] = {
54496 + {
54497 + .rstctrl_offs = 0x410,
54498 + .rstst_offs = 0x414,
54499 + .rstctrl_bit = 0,
54500 + .rstst_bit = 0,
54501 + },
54502 +};
54503 +
54504 +static struct ti_reset_data am43x_reset_data = {
54505 + .reg_data = am43x_reset_reg_data,
54506 + .nr_resets = ARRAY_SIZE(am43x_reset_reg_data),
54507 +};
54508 +
54509 +static struct ti_reset_reg_data dra7_reset_reg_data[] = {
54510 + {
54511 + .rstctrl_offs = 0x1310,
54512 + .rstst_offs = 0x1314,
54513 + .rstctrl_bit = 0,
54514 + .rstst_bit = 0,
54515 + },
54516 +};
54517 +
54518 +static struct ti_reset_data dra7_reset_data = {
54519 + .reg_data = dra7_reset_reg_data,
54520 + .nr_resets = ARRAY_SIZE(dra7_reset_reg_data),
54521 +};
54522 +
54523 +static int ti_reset_clear_reset(struct reset_controller_dev *rcdev,
54524 + unsigned long id)
54525 +{
54526 + void __iomem *reg = reset_data->reg_data[id].rstst_offs + reg_base;
54527 + u8 bit = reset_data->reg_data[id].rstst_bit;
54528 + u32 val = readl(reg);
54529 +
54530 + val &= ~(1 << bit);
54531 + val |= 1 << bit;
54532 + writel(val, reg);
54533 + return 0;
54534 +}
54535 +
54536 +static int ti_reset_is_reset(struct reset_controller_dev *rcdev,
54537 + unsigned long id)
54538 +{
54539 + void __iomem *reg = reset_data->reg_data[id].rstst_offs + reg_base;
54540 + u8 bit = reset_data->reg_data[id].rstst_bit;
54541 + u32 val = readl(reg);
54542 +
54543 + val &= (1 << bit);
54544 + return !!val;
54545 +}
54546 +
54547 +static int ti_reset_deassert(struct reset_controller_dev *rcdev,
54548 + unsigned long id)
54549 +{
54550 + void __iomem *reg = reset_data->reg_data[id].rstctrl_offs +
54551 + reg_base;
54552 + u8 bit = reset_data->reg_data[id].rstctrl_bit;
54553 + u32 val = readl(reg);
54554 +
54555 + val &= ~(1 << bit);
54556 + writel(val, reg);
54557 + return 0;
54558 +}
54559 +
54560 +static struct reset_control_ops ti_reset_ops = {
54561 + .deassert = ti_reset_deassert,
54562 + .is_reset = ti_reset_is_reset,
54563 + .clear_reset = ti_reset_clear_reset,
54564 +};
54565 +
54566 +static struct reset_controller_dev ti_reset_controller = {
54567 + .ops = &ti_reset_ops,
54568 +};
54569 +
54570 +static const struct of_device_id ti_reset_of_match[] = {
54571 + { .compatible = "ti,am3352-prcm", .data = &am335x_reset_data,},
54572 + { .compatible = "ti,am4372-prcm", .data = &am43x_reset_data,},
54573 + { .compatible = "ti,dra7-prcm", .data = &dra7_reset_data,},
54574 + {},
54575 +};
54576 +
54577 +static int ti_reset_probe(struct platform_device *pdev)
54578 +{
54579 + struct resource *res;
54580 + const struct of_device_id *id;
54581 +
54582 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
54583 + reg_base = devm_ioremap_resource(&pdev->dev, res);
54584 + if (IS_ERR(reg_base))
54585 + return PTR_ERR(reg_base);
54586 +
54587 + ti_reset_controller.of_node = pdev->dev.of_node;
54588 + id = of_match_device(ti_reset_of_match, &pdev->dev);
54589 + reset_data = id->data;
54590 + ti_reset_controller.nr_resets = reset_data->nr_resets;
54591 +
54592 + reset_controller_register(&ti_reset_controller);
54593 +
54594 + return 0;
54595 +}
54596 +
54597 +static int ti_reset_remove(struct platform_device *pdev)
54598 +{
54599 + reset_controller_unregister(&ti_reset_controller);
54600 +
54601 + return 0;
54602 +}
54603 +
54604 +static struct platform_driver ti_reset_driver = {
54605 + .probe = ti_reset_probe,
54606 + .remove = ti_reset_remove,
54607 + .driver = {
54608 + .name = DRIVER_NAME,
54609 + .owner = THIS_MODULE,
54610 + .of_match_table = of_match_ptr(ti_reset_of_match),
54611 + },
54612 +};
54613 +module_platform_driver(ti_reset_driver);
54614 +
54615 +MODULE_DESCRIPTION("PRCM reset driver for TI SoC's");
54616 +MODULE_LICENSE("GPL v2");
54617 +MODULE_ALIAS("platform:" DRIVER_NAME);
54618 --- a/drivers/rtc/rtc-omap.c
54619 +++ b/drivers/rtc/rtc-omap.c
54620 @@ -393,6 +393,10 @@ static int __init omap_rtc_probe(struct
54621 */
54622 rtc_write(0, OMAP_RTC_INTERRUPTS_REG);
54623
54624 + /* Selecting CLK cource for RTC */
54625 + rtc_writel((1 << 3) | (1 << 6), OMAP_RTC_OSC_REG);
54626 + rtc_writel(0x3, OMAP_RTC_IRQWAKEEN);
54627 +
54628 /* clear old status */
54629 reg = rtc_read(OMAP_RTC_STATUS_REG);
54630 if (reg & (u8) OMAP_RTC_STATUS_POWER_UP) {
54631 --- a/drivers/spi/spi-ti-qspi.c
54632 +++ b/drivers/spi/spi-ti-qspi.c
54633 @@ -41,14 +41,13 @@ struct ti_qspi_regs {
54634 struct ti_qspi {
54635 struct completion transfer_complete;
54636
54637 - /* IRQ synchronization */
54638 - spinlock_t lock;
54639 -
54640 /* list synchronization */
54641 struct mutex list_lock;
54642
54643 struct spi_master *master;
54644 void __iomem *base;
54645 + void __iomem *ctrl_base;
54646 + void __iomem *mmap_base;
54647 struct clk *fclk;
54648 struct device *dev;
54649
54650 @@ -57,7 +56,9 @@ struct ti_qspi {
54651 u32 spi_max_frequency;
54652 u32 cmd;
54653 u32 dc;
54654 - u32 stat;
54655 +
54656 + bool memory_mapped;
54657 + bool ctrl_mod;
54658 };
54659
54660 #define QSPI_PID (0x0)
54661 @@ -113,6 +114,23 @@ struct ti_qspi {
54662 #define QSPI_CSPOL(n) (1 << (1 + n * 8))
54663 #define QSPI_CKPOL(n) (1 << (n * 8))
54664
54665 +#define MM_SWITCH 0x01
54666 +#define MEM_CS 0x100
54667 +#define MEM_CS_DIS 0xfffff0ff
54668 +
54669 +#define QSPI_CMD_RD (0x3 << 0)
54670 +#define QSPI_CMD_DUAL_RD (0x3b << 0)
54671 +#define QSPI_CMD_QUAD_RD (0x6b << 0)
54672 +#define QSPI_CMD_READ_FAST (0x0b << 0)
54673 +#define QSPI_SETUP0_A_BYTES (0x3 << 8)
54674 +#define QSPI_SETUP0_NO_BITS (0x0 << 10)
54675 +#define QSPI_SETUP0_8_BITS (0x1 << 10)
54676 +#define QSPI_SETUP0_RD_NORMAL (0x0 << 12)
54677 +#define QSPI_SETUP0_RD_DUAL (0x1 << 12)
54678 +#define QSPI_SETUP0_RD_QUAD (0x3 << 12)
54679 +#define QSPI_CMD_WRITE (0x2 << 16)
54680 +#define QSPI_NUM_DUMMY_BITS (0x0 << 24)
54681 +
54682 #define QSPI_FRAME 4096
54683
54684 #define QSPI_AUTOSUSPEND_TIMEOUT 2000
54685 @@ -129,12 +147,37 @@ static inline void ti_qspi_write(struct
54686 writel(val, qspi->base + reg);
54687 }
54688
54689 +void enable_qspi_memory_mapped(struct ti_qspi *qspi)
54690 +{
54691 + u32 val;
54692 +
54693 + ti_qspi_write(qspi, MM_SWITCH, QSPI_SPI_SWITCH_REG);
54694 + if (qspi->ctrl_mod) {
54695 + val = readl(qspi->ctrl_base);
54696 + val |= MEM_CS;
54697 + writel(val, qspi->ctrl_base);
54698 + }
54699 +}
54700 +
54701 +void disable_qspi_memory_mapped(struct ti_qspi *qspi)
54702 +{
54703 + u32 val;
54704 +
54705 + ti_qspi_write(qspi, ~MM_SWITCH, QSPI_SPI_SWITCH_REG);
54706 + if (qspi->ctrl_mod) {
54707 + val = readl(qspi->ctrl_base);
54708 + val |= MEM_CS_DIS;
54709 + writel(val, qspi->ctrl_base);
54710 + }
54711 +}
54712 +
54713 static int ti_qspi_setup(struct spi_device *spi)
54714 {
54715 struct ti_qspi *qspi = spi_master_get_devdata(spi->master);
54716 struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg;
54717 int clk_div = 0, ret;
54718 - u32 clk_ctrl_reg, clk_rate, clk_mask;
54719 + u32 clk_ctrl_reg, clk_rate, clk_mask, memval = 0;
54720 + qspi->dc = 0;
54721
54722 if (spi->master->busy) {
54723 dev_dbg(qspi->dev, "master busy doing other trasnfers\n");
54724 @@ -182,6 +225,37 @@ static int ti_qspi_setup(struct spi_devi
54725 ti_qspi_write(qspi, clk_mask, QSPI_SPI_CLOCK_CNTRL_REG);
54726 ctx_reg->clkctrl = clk_mask;
54727
54728 + if (spi->mode & SPI_CPHA)
54729 + qspi->dc |= QSPI_CKPHA(spi->chip_select);
54730 + if (spi->mode & SPI_CPOL)
54731 + qspi->dc |= QSPI_CKPOL(spi->chip_select);
54732 + if (spi->mode & SPI_CS_HIGH)
54733 + qspi->dc |= QSPI_CSPOL(spi->chip_select);
54734 +
54735 + ti_qspi_write(qspi, qspi->dc, QSPI_SPI_DC_REG);
54736 +
54737 + if (qspi->memory_mapped) {
54738 + switch (spi->mode) {
54739 + case SPI_TX_DUAL:
54740 + memval |= (QSPI_CMD_DUAL_RD | QSPI_SETUP0_A_BYTES |
54741 + QSPI_SETUP0_8_BITS | QSPI_SETUP0_RD_DUAL |
54742 + QSPI_CMD_WRITE | QSPI_NUM_DUMMY_BITS);
54743 + break;
54744 + case SPI_TX_QUAD:
54745 + memval |= (QSPI_CMD_QUAD_RD | QSPI_SETUP0_A_BYTES |
54746 + QSPI_SETUP0_8_BITS | QSPI_SETUP0_RD_QUAD |
54747 + QSPI_CMD_WRITE | QSPI_NUM_DUMMY_BITS);
54748 + break;
54749 + default:
54750 + memval |= (QSPI_CMD_RD | QSPI_SETUP0_A_BYTES |
54751 + QSPI_SETUP0_NO_BITS | QSPI_SETUP0_RD_NORMAL |
54752 + QSPI_CMD_WRITE | QSPI_NUM_DUMMY_BITS);
54753 + break;
54754 + }
54755 + ti_qspi_write(qspi, memval, QSPI_SPI_SETUP0_REG);
54756 + spi->mode |= SPI_RX_MMAP;
54757 + }
54758 +
54759 pm_runtime_mark_last_busy(qspi->dev);
54760 ret = pm_runtime_put_autosuspend(qspi->dev);
54761 if (ret < 0) {
54762 @@ -344,16 +418,7 @@ static int ti_qspi_start_transfer_one(st
54763 struct spi_transfer *t;
54764 int status = 0, ret;
54765 int frame_length;
54766 -
54767 - /* setup device control reg */
54768 - qspi->dc = 0;
54769 -
54770 - if (spi->mode & SPI_CPHA)
54771 - qspi->dc |= QSPI_CKPHA(spi->chip_select);
54772 - if (spi->mode & SPI_CPOL)
54773 - qspi->dc |= QSPI_CKPOL(spi->chip_select);
54774 - if (spi->mode & SPI_CS_HIGH)
54775 - qspi->dc |= QSPI_CSPOL(spi->chip_select);
54776 + size_t from = 0;
54777
54778 frame_length = (m->frame_length << 3) / spi->bits_per_word;
54779
54780 @@ -366,11 +431,20 @@ static int ti_qspi_start_transfer_one(st
54781 qspi->cmd |= QSPI_WC_CMD_INT_EN;
54782
54783 ti_qspi_write(qspi, QSPI_WC_INT_EN, QSPI_INTR_ENABLE_SET_REG);
54784 - ti_qspi_write(qspi, qspi->dc, QSPI_SPI_DC_REG);
54785
54786 mutex_lock(&qspi->list_lock);
54787
54788 list_for_each_entry(t, &m->transfers, transfer_list) {
54789 + if (t->memory_map) {
54790 + if (t->tx_buf) {
54791 + from = t->len;
54792 + continue;
54793 + }
54794 + enable_qspi_memory_mapped(qspi);
54795 + memcpy(t->rx_buf, qspi->mmap_base + from, t->len);
54796 + disable_qspi_memory_mapped(qspi);
54797 + goto out;
54798 + }
54799 qspi->cmd |= QSPI_WLEN(t->bits_per_word);
54800
54801 ret = qspi_transfer_msg(qspi, t);
54802 @@ -383,6 +457,7 @@ static int ti_qspi_start_transfer_one(st
54803 m->actual_length += t->len;
54804 }
54805
54806 +out:
54807 mutex_unlock(&qspi->list_lock);
54808
54809 m->status = status;
54810 @@ -397,13 +472,12 @@ static irqreturn_t ti_qspi_isr(int irq,
54811 {
54812 struct ti_qspi *qspi = dev_id;
54813 u16 int_stat;
54814 + u32 stat;
54815
54816 irqreturn_t ret = IRQ_HANDLED;
54817
54818 - spin_lock(&qspi->lock);
54819 -
54820 int_stat = ti_qspi_read(qspi, QSPI_INTR_STATUS_ENABLED_CLEAR);
54821 - qspi->stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
54822 + stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
54823
54824 if (!int_stat) {
54825 dev_dbg(qspi->dev, "No IRQ triggered\n");
54826 @@ -411,35 +485,14 @@ static irqreturn_t ti_qspi_isr(int irq,
54827 goto out;
54828 }
54829
54830 - ret = IRQ_WAKE_THREAD;
54831 -
54832 - ti_qspi_write(qspi, QSPI_WC_INT_DISABLE, QSPI_INTR_ENABLE_CLEAR_REG);
54833 ti_qspi_write(qspi, QSPI_WC_INT_DISABLE,
54834 QSPI_INTR_STATUS_ENABLED_CLEAR);
54835 -
54836 + if (stat & WC)
54837 + complete(&qspi->transfer_complete);
54838 out:
54839 - spin_unlock(&qspi->lock);
54840 -
54841 return ret;
54842 }
54843
54844 -static irqreturn_t ti_qspi_threaded_isr(int this_irq, void *dev_id)
54845 -{
54846 - struct ti_qspi *qspi = dev_id;
54847 - unsigned long flags;
54848 -
54849 - spin_lock_irqsave(&qspi->lock, flags);
54850 -
54851 - if (qspi->stat & WC)
54852 - complete(&qspi->transfer_complete);
54853 -
54854 - spin_unlock_irqrestore(&qspi->lock, flags);
54855 -
54856 - ti_qspi_write(qspi, QSPI_WC_INT_EN, QSPI_INTR_ENABLE_SET_REG);
54857 -
54858 - return IRQ_HANDLED;
54859 -}
54860 -
54861 static int ti_qspi_runtime_resume(struct device *dev)
54862 {
54863 struct ti_qspi *qspi;
54864 @@ -463,7 +516,7 @@ static int ti_qspi_probe(struct platform
54865 {
54866 struct ti_qspi *qspi;
54867 struct spi_master *master;
54868 - struct resource *r;
54869 + struct resource *r, *res_ctrl, *res_mmap;
54870 struct device_node *np = pdev->dev.of_node;
54871 u32 max_freq;
54872 int ret = 0, num_cs, irq;
54873 @@ -472,7 +525,7 @@ static int ti_qspi_probe(struct platform
54874 if (!master)
54875 return -ENOMEM;
54876
54877 - master->mode_bits = SPI_CPOL | SPI_CPHA;
54878 + master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_QUAD | SPI_RX_MMAP;
54879
54880 master->bus_num = -1;
54881 master->flags = SPI_MASTER_HALF_DUPLEX;
54882 @@ -491,7 +544,16 @@ static int ti_qspi_probe(struct platform
54883 qspi->master = master;
54884 qspi->dev = &pdev->dev;
54885
54886 - r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
54887 + r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_base");
54888 + if (r == NULL) {
54889 + dev_err(&pdev->dev, "missing platform resources data\n");
54890 + return -ENODEV;
54891 + }
54892 +
54893 + res_mmap = platform_get_resource_byname(pdev,
54894 + IORESOURCE_MEM, "qspi_mmap");
54895 + res_ctrl = platform_get_resource_byname(pdev,
54896 + IORESOURCE_MEM, "qspi_ctrlmod");
54897
54898 irq = platform_get_irq(pdev, 0);
54899 if (irq < 0) {
54900 @@ -499,7 +561,6 @@ static int ti_qspi_probe(struct platform
54901 return irq;
54902 }
54903
54904 - spin_lock_init(&qspi->lock);
54905 mutex_init(&qspi->list_lock);
54906
54907 qspi->base = devm_ioremap_resource(&pdev->dev, r);
54908 @@ -508,8 +569,24 @@ static int ti_qspi_probe(struct platform
54909 goto free_master;
54910 }
54911
54912 - ret = devm_request_threaded_irq(&pdev->dev, irq, ti_qspi_isr,
54913 - ti_qspi_threaded_isr, 0,
54914 + if (res_ctrl) {
54915 + qspi->ctrl_mod = true;
54916 + qspi->ctrl_base = devm_ioremap_resource(&pdev->dev, res_ctrl);
54917 + if (IS_ERR(qspi->ctrl_base)) {
54918 + ret = PTR_ERR(qspi->ctrl_base);
54919 + goto free_master;
54920 + }
54921 + }
54922 +
54923 + if (res_mmap) {
54924 + qspi->mmap_base = devm_ioremap_resource(&pdev->dev, res_mmap);
54925 + if (IS_ERR(qspi->mmap_base)) {
54926 + ret = PTR_ERR(qspi->mmap_base);
54927 + goto free_master;
54928 + }
54929 + }
54930 +
54931 + ret = devm_request_irq(&pdev->dev, irq, ti_qspi_isr, 0,
54932 dev_name(&pdev->dev), qspi);
54933 if (ret < 0) {
54934 dev_err(&pdev->dev, "Failed to register ISR for IRQ %d\n",
54935 @@ -532,6 +609,9 @@ static int ti_qspi_probe(struct platform
54936 if (!of_property_read_u32(np, "spi-max-frequency", &max_freq))
54937 qspi->spi_max_frequency = max_freq;
54938
54939 + if (of_property_read_bool(np, "mmap_read"))
54940 + qspi->memory_mapped = true;
54941 +
54942 ret = spi_register_master(master);
54943 if (ret)
54944 goto free_master;
54945 @@ -547,6 +627,7 @@ static int ti_qspi_remove(struct platfor
54946 {
54947 struct ti_qspi *qspi = platform_get_drvdata(pdev);
54948
54949 + ti_qspi_write(qspi, QSPI_WC_INT_DISABLE, QSPI_INTR_ENABLE_CLEAR_REG);
54950 spi_unregister_master(qspi->master);
54951
54952 return 0;
54953 --- a/drivers/tty/serial/omap-serial.c
54954 +++ b/drivers/tty/serial/omap-serial.c
54955 @@ -240,8 +240,8 @@ serial_omap_baud_is_mode16(struct uart_p
54956 {
54957 unsigned int n13 = port->uartclk / (13 * baud);
54958 unsigned int n16 = port->uartclk / (16 * baud);
54959 - int baudAbsDiff13 = baud - (port->uartclk / (13 * n13));
54960 - int baudAbsDiff16 = baud - (port->uartclk / (16 * n16));
54961 + int baudAbsDiff13 = n13 ? (baud - (port->uartclk / (13 * n13))) : INT_MAX;
54962 + int baudAbsDiff16 = n16 ? (baud - (port->uartclk / (16 * n16))) : INT_MAX;
54963 if(baudAbsDiff13 < 0)
54964 baudAbsDiff13 = -baudAbsDiff13;
54965 if(baudAbsDiff16 < 0)
54966 --- a/drivers/usb/dwc3/core.c
54967 +++ b/drivers/usb/dwc3/core.c
54968 @@ -80,8 +80,6 @@ static void dwc3_core_soft_reset(struct
54969 reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST;
54970 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
54971
54972 - usb_phy_init(dwc->usb2_phy);
54973 - usb_phy_init(dwc->usb3_phy);
54974 mdelay(100);
54975
54976 /* Clear USB3 PHY reset */
54977 @@ -343,6 +341,11 @@ static void dwc3_core_exit(struct dwc3 *
54978 {
54979 usb_phy_shutdown(dwc->usb2_phy);
54980 usb_phy_shutdown(dwc->usb3_phy);
54981 +
54982 + if (dwc->usb2_generic_phy)
54983 + phy_power_off(dwc->usb2_generic_phy);
54984 + if (dwc->usb3_generic_phy)
54985 + phy_power_off(dwc->usb3_generic_phy);
54986 }
54987
54988 #define DWC3_ALIGN_MASK (16 - 1)
54989 @@ -387,16 +390,102 @@ static int dwc3_probe(struct platform_de
54990 if (node) {
54991 dwc->maximum_speed = of_usb_get_maximum_speed(node);
54992
54993 - dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
54994 - dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
54995 + switch (dwc->maximum_speed) {
54996 + case USB_SPEED_SUPER:
54997 + if (of_property_read_bool(node, "usb-phy")) {
54998 + dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev,
54999 + "usb-phy", 0);
55000 + if (IS_ERR(dwc->usb2_phy))
55001 + return PTR_ERR(dwc->usb2_phy);
55002 + dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev,
55003 + "usb-phy", 1);
55004 + if (IS_ERR(dwc->usb3_phy))
55005 + return PTR_ERR(dwc->usb3_phy);
55006 + } else {
55007 + dwc->usb2_phy = NULL;
55008 + dwc->usb3_phy = NULL;
55009 + }
55010 +
55011 + if (of_property_read_bool(node, "phys")) {
55012 + dwc->usb2_generic_phy = devm_phy_get(dev,
55013 + "usb2-phy");
55014 + if (IS_ERR(dwc->usb2_generic_phy)) {
55015 + dev_err(dev, "no usb2 phy configured");
55016 + return PTR_ERR(dwc->usb2_generic_phy);
55017 + }
55018 +
55019 + dwc->usb3_generic_phy = devm_phy_get(dev,
55020 + "usb3-phy");
55021 + if (IS_ERR(dwc->usb3_generic_phy)) {
55022 + dev_err(dev, "no usb3 phy configured");
55023 + return PTR_ERR(dwc->usb3_generic_phy);
55024 + }
55025 + } else {
55026 + dwc->usb2_generic_phy = NULL;
55027 + dwc->usb3_generic_phy = NULL;
55028 + }
55029 + break;
55030 + case USB_SPEED_HIGH:
55031 + case USB_SPEED_FULL:
55032 + case USB_SPEED_LOW:
55033 + dwc->usb3_phy = NULL;
55034 + dwc->usb3_generic_phy = NULL;
55035 + if (of_property_read_bool(node, "usb-phy")) {
55036 + dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev,
55037 + "usb-phy", 0);
55038 + if (IS_ERR(dwc->usb2_phy))
55039 + return PTR_ERR(dwc->usb2_phy);
55040 + } else {
55041 + dwc->usb2_phy = NULL;
55042 + }
55043 + if (of_property_read_bool(node, "phys")) {
55044 + dwc->usb2_generic_phy = devm_phy_get(dev,
55045 + "usb2-phy");
55046 + if (IS_ERR(dwc->usb2_generic_phy)) {
55047 + dev_err(dev, "no usb2 phy configured");
55048 + return PTR_ERR(dwc->usb2_generic_phy);
55049 + }
55050 + } else {
55051 + dwc->usb2_generic_phy = NULL;
55052 + }
55053 + break;
55054 + }
55055
55056 dwc->needs_fifo_resize = of_property_read_bool(node, "tx-fifo-resize");
55057 dwc->dr_mode = of_usb_get_dr_mode(node);
55058 } else if (pdata) {
55059 dwc->maximum_speed = pdata->maximum_speed;
55060
55061 - dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
55062 - dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
55063 + switch (dwc->maximum_speed) {
55064 + case USB_SPEED_SUPER:
55065 + if (pdata->has_phy) {
55066 + dwc->usb2_phy = devm_usb_get_phy(dev,
55067 + USB_PHY_TYPE_USB2);
55068 + if (IS_ERR(dwc->usb2_phy))
55069 + return PTR_ERR(dwc->usb2_phy);
55070 + dwc->usb3_phy = devm_usb_get_phy(dev,
55071 + USB_PHY_TYPE_USB3);
55072 + if (IS_ERR(dwc->usb3_phy))
55073 + return PTR_ERR(dwc->usb3_phy);
55074 + } else {
55075 + dwc->usb2_phy = NULL;
55076 + dwc->usb3_phy = NULL;
55077 + }
55078 + break;
55079 + case USB_SPEED_HIGH:
55080 + case USB_SPEED_FULL:
55081 + case USB_SPEED_LOW:
55082 + dwc->usb3_phy = NULL;
55083 + if (pdata->has_phy) {
55084 + dwc->usb2_phy = devm_usb_get_phy(dev,
55085 + USB_PHY_TYPE_USB2);
55086 + if (IS_ERR(dwc->usb2_phy))
55087 + return PTR_ERR(dwc->usb2_phy);
55088 + } else {
55089 + dwc->usb2_phy = NULL;
55090 + }
55091 + break;
55092 + }
55093
55094 dwc->needs_fifo_resize = pdata->tx_fifo_resize;
55095 dwc->dr_mode = pdata->dr_mode;
55096 @@ -409,36 +498,6 @@ static int dwc3_probe(struct platform_de
55097 if (dwc->maximum_speed == USB_SPEED_UNKNOWN)
55098 dwc->maximum_speed = USB_SPEED_SUPER;
55099
55100 - if (IS_ERR(dwc->usb2_phy)) {
55101 - ret = PTR_ERR(dwc->usb2_phy);
55102 -
55103 - /*
55104 - * if -ENXIO is returned, it means PHY layer wasn't
55105 - * enabled, so it makes no sense to return -EPROBE_DEFER
55106 - * in that case, since no PHY driver will ever probe.
55107 - */
55108 - if (ret == -ENXIO)
55109 - return ret;
55110 -
55111 - dev_err(dev, "no usb2 phy configured\n");
55112 - return -EPROBE_DEFER;
55113 - }
55114 -
55115 - if (IS_ERR(dwc->usb3_phy)) {
55116 - ret = PTR_ERR(dwc->usb3_phy);
55117 -
55118 - /*
55119 - * if -ENXIO is returned, it means PHY layer wasn't
55120 - * enabled, so it makes no sense to return -EPROBE_DEFER
55121 - * in that case, since no PHY driver will ever probe.
55122 - */
55123 - if (ret == -ENXIO)
55124 - return ret;
55125 -
55126 - dev_err(dev, "no usb3 phy configured\n");
55127 - return -EPROBE_DEFER;
55128 - }
55129 -
55130 dwc->xhci_resources[0].start = res->start;
55131 dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
55132 DWC3_XHCI_REGS_END;
55133 @@ -455,9 +514,20 @@ static int dwc3_probe(struct platform_de
55134 if (IS_ERR(regs))
55135 return PTR_ERR(regs);
55136
55137 + usb_phy_init(dwc->usb2_phy);
55138 + usb_phy_init(dwc->usb3_phy);
55139 usb_phy_set_suspend(dwc->usb2_phy, 0);
55140 usb_phy_set_suspend(dwc->usb3_phy, 0);
55141
55142 + if (dwc->usb2_generic_phy) {
55143 + phy_init(dwc->usb2_generic_phy);
55144 + phy_power_on(dwc->usb2_generic_phy);
55145 + }
55146 + if (dwc->usb3_generic_phy) {
55147 + phy_init(dwc->usb3_generic_phy);
55148 + phy_power_on(dwc->usb3_generic_phy);
55149 + }
55150 +
55151 spin_lock_init(&dwc->lock);
55152 platform_set_drvdata(pdev, dwc);
55153
55154 @@ -584,7 +654,12 @@ static int dwc3_remove(struct platform_d
55155 usb_phy_set_suspend(dwc->usb2_phy, 1);
55156 usb_phy_set_suspend(dwc->usb3_phy, 1);
55157
55158 - pm_runtime_put(&pdev->dev);
55159 + if (dwc->usb2_generic_phy)
55160 + phy_power_off(dwc->usb2_generic_phy);
55161 + if (dwc->usb3_generic_phy)
55162 + phy_power_off(dwc->usb3_generic_phy);
55163 +
55164 + pm_runtime_put_sync(&pdev->dev);
55165 pm_runtime_disable(&pdev->dev);
55166
55167 dwc3_debugfs_exit(dwc);
55168 @@ -681,6 +756,11 @@ static int dwc3_suspend(struct device *d
55169 usb_phy_shutdown(dwc->usb3_phy);
55170 usb_phy_shutdown(dwc->usb2_phy);
55171
55172 + if (dwc->usb2_generic_phy)
55173 + phy_exit(dwc->usb2_generic_phy);
55174 + if (dwc->usb3_generic_phy)
55175 + phy_exit(dwc->usb3_generic_phy);
55176 +
55177 return 0;
55178 }
55179
55180 @@ -691,6 +771,12 @@ static int dwc3_resume(struct device *de
55181
55182 usb_phy_init(dwc->usb3_phy);
55183 usb_phy_init(dwc->usb2_phy);
55184 +
55185 + if (dwc->usb2_generic_phy)
55186 + phy_init(dwc->usb2_generic_phy);
55187 + if (dwc->usb3_generic_phy)
55188 + phy_init(dwc->usb3_generic_phy);
55189 +
55190 msleep(100);
55191
55192 spin_lock_irqsave(&dwc->lock, flags);
55193 --- a/drivers/usb/dwc3/core.h
55194 +++ b/drivers/usb/dwc3/core.h
55195 @@ -31,6 +31,8 @@
55196 #include <linux/usb/gadget.h>
55197 #include <linux/usb/otg.h>
55198
55199 +#include <linux/phy/phy.h>
55200 +
55201 /* Global constants */
55202 #define DWC3_EP0_BOUNCE_SIZE 512
55203 #define DWC3_ENDPOINTS_NUM 32
55204 @@ -613,6 +615,8 @@ struct dwc3_scratchpad_array {
55205 * @dr_mode: requested mode of operation
55206 * @usb2_phy: pointer to USB2 PHY
55207 * @usb3_phy: pointer to USB3 PHY
55208 + * @usb2_generic_phy: pointer to USB2 PHY
55209 + * @usb3_generic_phy: pointer to USB3 PHY
55210 * @dcfg: saved contents of DCFG register
55211 * @gctl: saved contents of GCTL register
55212 * @is_selfpowered: true when we are selfpowered
55213 @@ -665,6 +669,9 @@ struct dwc3 {
55214 struct usb_phy *usb2_phy;
55215 struct usb_phy *usb3_phy;
55216
55217 + struct phy *usb2_generic_phy;
55218 + struct phy *usb3_generic_phy;
55219 +
55220 void __iomem *regs;
55221 size_t regs_size;
55222
55223 --- a/drivers/usb/dwc3/dwc3-omap.c
55224 +++ b/drivers/usb/dwc3/dwc3-omap.c
55225 @@ -535,7 +535,7 @@ static int dwc3_omap_probe(struct platfo
55226 edev = of_extcon_get_extcon_dev(dev, 0);
55227 if (IS_ERR(edev)) {
55228 dev_vdbg(dev, "couldn't get extcon device\n");
55229 - ret = PTR_ERR(edev);
55230 + ret = -EPROBE_DEFER;
55231 goto err2;
55232 }
55233
55234 --- a/drivers/usb/dwc3/dwc3-pci.c
55235 +++ b/drivers/usb/dwc3/dwc3-pci.c
55236 @@ -165,7 +165,6 @@ static int dwc3_pci_probe(struct pci_dev
55237 return 0;
55238
55239 err3:
55240 - pci_set_drvdata(pci, NULL);
55241 platform_device_put(dwc3);
55242 err1:
55243 pci_disable_device(pci);
55244 @@ -180,7 +179,6 @@ static void dwc3_pci_remove(struct pci_d
55245 platform_device_unregister(glue->dwc3);
55246 platform_device_unregister(glue->usb2_phy);
55247 platform_device_unregister(glue->usb3_phy);
55248 - pci_set_drvdata(pci, NULL);
55249 pci_disable_device(pci);
55250 }
55251
55252 --- a/drivers/usb/dwc3/Kconfig
55253 +++ b/drivers/usb/dwc3/Kconfig
55254 @@ -1,6 +1,9 @@
55255 config USB_DWC3
55256 tristate "DesignWare USB3 DRD Core Support"
55257 depends on (USB || USB_GADGET) && HAS_DMA
55258 + depends on EXTCON
55259 + select USB_PHY
55260 + select GENERIC_PHY
55261 select USB_XHCI_PLATFORM if USB_SUPPORT && USB_XHCI_HCD
55262 help
55263 Say Y or M here if your system has a Dual Role SuperSpeed
55264 --- a/drivers/usb/dwc3/platform_data.h
55265 +++ b/drivers/usb/dwc3/platform_data.h
55266 @@ -24,4 +24,5 @@ struct dwc3_platform_data {
55267 enum usb_device_speed maximum_speed;
55268 enum usb_dr_mode dr_mode;
55269 bool tx_fifo_resize;
55270 + bool has_phy;
55271 };
55272 --- a/drivers/usb/gadget/acm_ms.c
55273 +++ b/drivers/usb/gadget/acm_ms.c
55274 @@ -31,16 +31,7 @@
55275 #define ACM_MS_VENDOR_NUM 0x1d6b /* Linux Foundation */
55276 #define ACM_MS_PRODUCT_NUM 0x0106 /* Composite Gadget: ACM + MS*/
55277
55278 -/*-------------------------------------------------------------------------*/
55279 -
55280 -/*
55281 - * Kbuild is not very cooperative with respect to linking separately
55282 - * compiled library objects into one module. So for now we won't use
55283 - * separate compilation ... ensuring init/exit sections work to shrink
55284 - * the runtime footprint, and giving us at least some parts of what
55285 - * a "gcc --combine ... part1.c part2.c part3.c ... " build would.
55286 - */
55287 -#include "f_mass_storage.c"
55288 +#include "f_mass_storage.h"
55289
55290 /*-------------------------------------------------------------------------*/
55291 USB_GADGET_COMPOSITE_OPTIONS();
55292 @@ -104,18 +95,35 @@ static struct usb_gadget_strings *dev_st
55293 /****************************** Configurations ******************************/
55294
55295 static struct fsg_module_parameters fsg_mod_data = { .stall = 1 };
55296 -FSG_MODULE_PARAMETERS(/* no prefix */, fsg_mod_data);
55297 +#ifdef CONFIG_USB_GADGET_DEBUG_FILES
55298 +
55299 +static unsigned int fsg_num_buffers = CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS;
55300
55301 -static struct fsg_common fsg_common;
55302 +#else
55303 +
55304 +/*
55305 + * Number of buffers we will use.
55306 + * 2 is usually enough for good buffering pipeline
55307 + */
55308 +#define fsg_num_buffers CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS
55309 +
55310 +#endif /* CONFIG_USB_DEBUG */
55311 +
55312 +FSG_MODULE_PARAMETERS(/* no prefix */, fsg_mod_data);
55313
55314 /*-------------------------------------------------------------------------*/
55315 static struct usb_function *f_acm;
55316 static struct usb_function_instance *f_acm_inst;
55317 +
55318 +static struct usb_function_instance *fi_msg;
55319 +static struct usb_function *f_msg;
55320 +
55321 /*
55322 * We _always_ have both ACM and mass storage functions.
55323 */
55324 static int __init acm_ms_do_config(struct usb_configuration *c)
55325 {
55326 + struct fsg_opts *opts;
55327 int status;
55328
55329 if (gadget_is_otg(c->cdev->gadget)) {
55330 @@ -123,31 +131,37 @@ static int __init acm_ms_do_config(struc
55331 c->bmAttributes |= USB_CONFIG_ATT_WAKEUP;
55332 }
55333
55334 - f_acm_inst = usb_get_function_instance("acm");
55335 - if (IS_ERR(f_acm_inst))
55336 - return PTR_ERR(f_acm_inst);
55337 + opts = fsg_opts_from_func_inst(fi_msg);
55338
55339 f_acm = usb_get_function(f_acm_inst);
55340 - if (IS_ERR(f_acm)) {
55341 - status = PTR_ERR(f_acm);
55342 - goto err_func;
55343 + if (IS_ERR(f_acm))
55344 + return PTR_ERR(f_acm);
55345 +
55346 + f_msg = usb_get_function(fi_msg);
55347 + if (IS_ERR(f_msg)) {
55348 + status = PTR_ERR(f_msg);
55349 + goto put_acm;
55350 }
55351
55352 status = usb_add_function(c, f_acm);
55353 if (status < 0)
55354 - goto err_conf;
55355 + goto put_msg;
55356
55357 - status = fsg_bind_config(c->cdev, c, &fsg_common);
55358 - if (status < 0)
55359 - goto err_fsg;
55360 + status = fsg_common_run_thread(opts->common);
55361 + if (status)
55362 + goto remove_acm;
55363 +
55364 + status = usb_add_function(c, f_msg);
55365 + if (status)
55366 + goto remove_acm;
55367
55368 return 0;
55369 -err_fsg:
55370 +remove_acm:
55371 usb_remove_function(c, f_acm);
55372 -err_conf:
55373 +put_msg:
55374 + usb_put_function(f_msg);
55375 +put_acm:
55376 usb_put_function(f_acm);
55377 -err_func:
55378 - usb_put_function_instance(f_acm_inst);
55379 return status;
55380 }
55381
55382 @@ -163,45 +177,82 @@ static struct usb_configuration acm_ms_c
55383 static int __init acm_ms_bind(struct usb_composite_dev *cdev)
55384 {
55385 struct usb_gadget *gadget = cdev->gadget;
55386 + struct fsg_opts *opts;
55387 + struct fsg_config config;
55388 int status;
55389 - void *retp;
55390
55391 - /* set up mass storage function */
55392 - retp = fsg_common_from_params(&fsg_common, cdev, &fsg_mod_data);
55393 - if (IS_ERR(retp)) {
55394 - status = PTR_ERR(retp);
55395 - return PTR_ERR(retp);
55396 + f_acm_inst = usb_get_function_instance("acm");
55397 + if (IS_ERR(f_acm_inst))
55398 + return PTR_ERR(f_acm_inst);
55399 +
55400 + fi_msg = usb_get_function_instance("mass_storage");
55401 + if (IS_ERR(fi_msg)) {
55402 + status = PTR_ERR(fi_msg);
55403 + goto fail_get_msg;
55404 }
55405
55406 + /* set up mass storage function */
55407 + fsg_config_from_params(&config, &fsg_mod_data, fsg_num_buffers);
55408 + opts = fsg_opts_from_func_inst(fi_msg);
55409 +
55410 + opts->no_configfs = true;
55411 + status = fsg_common_set_num_buffers(opts->common, fsg_num_buffers);
55412 + if (status)
55413 + goto fail;
55414 +
55415 + status = fsg_common_set_nluns(opts->common, config.nluns);
55416 + if (status)
55417 + goto fail_set_nluns;
55418 +
55419 + status = fsg_common_set_cdev(opts->common, cdev, config.can_stall);
55420 + if (status)
55421 + goto fail_set_cdev;
55422 +
55423 + fsg_common_set_sysfs(opts->common, true);
55424 + status = fsg_common_create_luns(opts->common, &config);
55425 + if (status)
55426 + goto fail_set_cdev;
55427 +
55428 + fsg_common_set_inquiry_string(opts->common, config.vendor_name,
55429 + config.product_name);
55430 /*
55431 * Allocate string descriptor numbers ... note that string
55432 * contents can be overridden by the composite_dev glue.
55433 */
55434 status = usb_string_ids_tab(cdev, strings_dev);
55435 if (status < 0)
55436 - goto fail1;
55437 + goto fail_string_ids;
55438 device_desc.iManufacturer = strings_dev[USB_GADGET_MANUFACTURER_IDX].id;
55439 device_desc.iProduct = strings_dev[USB_GADGET_PRODUCT_IDX].id;
55440
55441 /* register our configuration */
55442 status = usb_add_config(cdev, &acm_ms_config_driver, acm_ms_do_config);
55443 if (status < 0)
55444 - goto fail1;
55445 + goto fail_string_ids;
55446
55447 usb_composite_overwrite_options(cdev, &coverwrite);
55448 dev_info(&gadget->dev, "%s, version: " DRIVER_VERSION "\n",
55449 DRIVER_DESC);
55450 - fsg_common_put(&fsg_common);
55451 return 0;
55452
55453 /* error recovery */
55454 -fail1:
55455 - fsg_common_put(&fsg_common);
55456 +fail_string_ids:
55457 + fsg_common_remove_luns(opts->common);
55458 +fail_set_cdev:
55459 + fsg_common_free_luns(opts->common);
55460 +fail_set_nluns:
55461 + fsg_common_free_buffers(opts->common);
55462 +fail:
55463 + usb_put_function_instance(fi_msg);
55464 +fail_get_msg:
55465 + usb_put_function_instance(f_acm_inst);
55466 return status;
55467 }
55468
55469 static int __exit acm_ms_unbind(struct usb_composite_dev *cdev)
55470 {
55471 + usb_put_function(f_msg);
55472 + usb_put_function_instance(fi_msg);
55473 usb_put_function(f_acm);
55474 usb_put_function_instance(f_acm_inst);
55475 return 0;
55476 --- a/drivers/usb/gadget/amd5536udc.c
55477 +++ b/drivers/usb/gadget/amd5536udc.c
55478 @@ -3078,8 +3078,6 @@ static void udc_pci_remove(struct pci_de
55479 if (dev->active)
55480 pci_disable_device(pdev);
55481
55482 - pci_set_drvdata(pdev, NULL);
55483 -
55484 udc_remove(dev);
55485 }
55486
55487 --- a/drivers/usb/gadget/configfs.c
55488 +++ b/drivers/usb/gadget/configfs.c
55489 @@ -557,7 +557,7 @@ static struct config_group *function_mak
55490
55491 fi = usb_get_function_instance(func_name);
55492 if (IS_ERR(fi))
55493 - return ERR_PTR(PTR_ERR(fi));
55494 + return ERR_CAST(fi);
55495
55496 ret = config_item_set_name(&fi->group.cg_item, name);
55497 if (ret) {
55498 @@ -991,6 +991,14 @@ static struct configfs_subsystem gadget_
55499 .su_mutex = __MUTEX_INITIALIZER(gadget_subsys.su_mutex),
55500 };
55501
55502 +void unregister_gadget_item(struct config_item *item)
55503 +{
55504 + struct gadget_info *gi = to_gadget_info(item);
55505 +
55506 + unregister_gadget(gi);
55507 +}
55508 +EXPORT_SYMBOL(unregister_gadget_item);
55509 +
55510 static int __init gadget_cfs_init(void)
55511 {
55512 int ret;
55513 --- /dev/null
55514 +++ b/drivers/usb/gadget/configfs.h
55515 @@ -0,0 +1,6 @@
55516 +#ifndef USB__GADGET__CONFIGFS__H
55517 +#define USB__GADGET__CONFIGFS__H
55518 +
55519 +void unregister_gadget_item(struct config_item *item);
55520 +
55521 +#endif /* USB__GADGET__CONFIGFS__H */
55522 --- a/drivers/usb/gadget/f_mass_storage.c
55523 +++ b/drivers/usb/gadget/f_mass_storage.c
55524 @@ -213,12 +213,14 @@
55525 #include <linux/spinlock.h>
55526 #include <linux/string.h>
55527 #include <linux/freezer.h>
55528 +#include <linux/module.h>
55529
55530 #include <linux/usb/ch9.h>
55531 #include <linux/usb/gadget.h>
55532 #include <linux/usb/composite.h>
55533
55534 #include "gadget_chips.h"
55535 +#include "configfs.h"
55536
55537
55538 /*------------------------------------------------------------------------*/
55539 @@ -228,26 +230,30 @@
55540
55541 static const char fsg_string_interface[] = "Mass Storage";
55542
55543 -#include "storage_common.c"
55544 +#include "storage_common.h"
55545 +#include "f_mass_storage.h"
55546
55547 +/* Static strings, in UTF-8 (for simplicity we use only ASCII characters) */
55548 +static struct usb_string fsg_strings[] = {
55549 + {FSG_STRING_INTERFACE, fsg_string_interface},
55550 + {}
55551 +};
55552 +
55553 +static struct usb_gadget_strings fsg_stringtab = {
55554 + .language = 0x0409, /* en-us */
55555 + .strings = fsg_strings,
55556 +};
55557 +
55558 +static struct usb_gadget_strings *fsg_strings_array[] = {
55559 + &fsg_stringtab,
55560 + NULL,
55561 +};
55562
55563 /*-------------------------------------------------------------------------*/
55564
55565 struct fsg_dev;
55566 struct fsg_common;
55567
55568 -/* FSF callback functions */
55569 -struct fsg_operations {
55570 - /*
55571 - * Callback function to call when thread exits. If no
55572 - * callback is set or it returns value lower then zero MSF
55573 - * will force eject all LUNs it operates on (including those
55574 - * marked as non-removable or with prevent_medium_removal flag
55575 - * set).
55576 - */
55577 - int (*thread_exits)(struct fsg_common *common);
55578 -};
55579 -
55580 /* Data shared by all the FSG instances. */
55581 struct fsg_common {
55582 struct usb_gadget *gadget;
55583 @@ -268,13 +274,14 @@ struct fsg_common {
55584 struct fsg_buffhd *next_buffhd_to_fill;
55585 struct fsg_buffhd *next_buffhd_to_drain;
55586 struct fsg_buffhd *buffhds;
55587 + unsigned int fsg_num_buffers;
55588
55589 int cmnd_size;
55590 u8 cmnd[MAX_COMMAND_SIZE];
55591
55592 unsigned int nluns;
55593 unsigned int lun;
55594 - struct fsg_lun *luns;
55595 + struct fsg_lun **luns;
55596 struct fsg_lun *curlun;
55597
55598 unsigned int bulk_out_maxpacket;
55599 @@ -294,6 +301,7 @@ struct fsg_common {
55600 unsigned int short_packet_received:1;
55601 unsigned int bad_lun_okay:1;
55602 unsigned int running:1;
55603 + unsigned int sysfs:1;
55604
55605 int thread_wakeup_needed;
55606 struct completion thread_notifier;
55607 @@ -313,27 +321,6 @@ struct fsg_common {
55608 struct kref ref;
55609 };
55610
55611 -struct fsg_config {
55612 - unsigned nluns;
55613 - struct fsg_lun_config {
55614 - const char *filename;
55615 - char ro;
55616 - char removable;
55617 - char cdrom;
55618 - char nofua;
55619 - } luns[FSG_MAX_LUNS];
55620 -
55621 - /* Callback functions. */
55622 - const struct fsg_operations *ops;
55623 - /* Gadget's private data. */
55624 - void *private_data;
55625 -
55626 - const char *vendor_name; /* 8 characters or less */
55627 - const char *product_name; /* 16 characters or less */
55628 -
55629 - char can_stall;
55630 -};
55631 -
55632 struct fsg_dev {
55633 struct usb_function function;
55634 struct usb_gadget *gadget; /* Copy of cdev->gadget */
55635 @@ -615,13 +602,14 @@ static bool start_out_transfer(struct fs
55636 return true;
55637 }
55638
55639 -static int sleep_thread(struct fsg_common *common)
55640 +static int sleep_thread(struct fsg_common *common, bool can_freeze)
55641 {
55642 int rc = 0;
55643
55644 /* Wait until a signal arrives or we are woken up */
55645 for (;;) {
55646 - try_to_freeze();
55647 + if (can_freeze)
55648 + try_to_freeze();
55649 set_current_state(TASK_INTERRUPTIBLE);
55650 if (signal_pending(current)) {
55651 rc = -EINTR;
55652 @@ -695,7 +683,7 @@ static int do_read(struct fsg_common *co
55653 /* Wait for the next buffer to become available */
55654 bh = common->next_buffhd_to_fill;
55655 while (bh->state != BUF_STATE_EMPTY) {
55656 - rc = sleep_thread(common);
55657 + rc = sleep_thread(common, false);
55658 if (rc)
55659 return rc;
55660 }
55661 @@ -950,7 +938,7 @@ static int do_write(struct fsg_common *c
55662 }
55663
55664 /* Wait for something to happen */
55665 - rc = sleep_thread(common);
55666 + rc = sleep_thread(common, false);
55667 if (rc)
55668 return rc;
55669 }
55670 @@ -1517,7 +1505,7 @@ static int throw_away_data(struct fsg_co
55671 }
55672
55673 /* Otherwise wait for something to happen */
55674 - rc = sleep_thread(common);
55675 + rc = sleep_thread(common, true);
55676 if (rc)
55677 return rc;
55678 }
55679 @@ -1638,7 +1626,7 @@ static int send_status(struct fsg_common
55680 /* Wait for the next buffer to become available */
55681 bh = common->next_buffhd_to_fill;
55682 while (bh->state != BUF_STATE_EMPTY) {
55683 - rc = sleep_thread(common);
55684 + rc = sleep_thread(common, true);
55685 if (rc)
55686 return rc;
55687 }
55688 @@ -1841,7 +1829,7 @@ static int do_scsi_command(struct fsg_co
55689 bh = common->next_buffhd_to_fill;
55690 common->next_buffhd_to_drain = bh;
55691 while (bh->state != BUF_STATE_EMPTY) {
55692 - rc = sleep_thread(common);
55693 + rc = sleep_thread(common, true);
55694 if (rc)
55695 return rc;
55696 }
55697 @@ -2172,7 +2160,7 @@ static int received_cbw(struct fsg_dev *
55698 common->data_dir = DATA_DIR_NONE;
55699 common->lun = cbw->Lun;
55700 if (common->lun < common->nluns)
55701 - common->curlun = &common->luns[common->lun];
55702 + common->curlun = common->luns[common->lun];
55703 else
55704 common->curlun = NULL;
55705 common->tag = cbw->Tag;
55706 @@ -2187,7 +2175,7 @@ static int get_next_command(struct fsg_c
55707 /* Wait for the next buffer to become available */
55708 bh = common->next_buffhd_to_fill;
55709 while (bh->state != BUF_STATE_EMPTY) {
55710 - rc = sleep_thread(common);
55711 + rc = sleep_thread(common, true);
55712 if (rc)
55713 return rc;
55714 }
55715 @@ -2206,7 +2194,7 @@ static int get_next_command(struct fsg_c
55716
55717 /* Wait for the CBW to arrive */
55718 while (bh->state != BUF_STATE_FULL) {
55719 - rc = sleep_thread(common);
55720 + rc = sleep_thread(common, true);
55721 if (rc)
55722 return rc;
55723 }
55724 @@ -2244,7 +2232,7 @@ reset:
55725 if (common->fsg) {
55726 fsg = common->fsg;
55727
55728 - for (i = 0; i < fsg_num_buffers; ++i) {
55729 + for (i = 0; i < common->fsg_num_buffers; ++i) {
55730 struct fsg_buffhd *bh = &common->buffhds[i];
55731
55732 if (bh->inreq) {
55733 @@ -2303,7 +2291,7 @@ reset:
55734 clear_bit(IGNORE_BULK_OUT, &fsg->atomic_bitflags);
55735
55736 /* Allocate the requests */
55737 - for (i = 0; i < fsg_num_buffers; ++i) {
55738 + for (i = 0; i < common->fsg_num_buffers; ++i) {
55739 struct fsg_buffhd *bh = &common->buffhds[i];
55740
55741 rc = alloc_request(common, fsg->bulk_in, &bh->inreq);
55742 @@ -2320,7 +2308,9 @@ reset:
55743
55744 common->running = 1;
55745 for (i = 0; i < common->nluns; ++i)
55746 - common->luns[i].unit_attention_data = SS_RESET_OCCURRED;
55747 + if (common->luns[i])
55748 + common->luns[i]->unit_attention_data =
55749 + SS_RESET_OCCURRED;
55750 return rc;
55751 }
55752
55753 @@ -2372,7 +2362,7 @@ static void handle_exception(struct fsg_
55754
55755 /* Cancel all the pending transfers */
55756 if (likely(common->fsg)) {
55757 - for (i = 0; i < fsg_num_buffers; ++i) {
55758 + for (i = 0; i < common->fsg_num_buffers; ++i) {
55759 bh = &common->buffhds[i];
55760 if (bh->inreq_busy)
55761 usb_ep_dequeue(common->fsg->bulk_in, bh->inreq);
55762 @@ -2384,13 +2374,13 @@ static void handle_exception(struct fsg_
55763 /* Wait until everything is idle */
55764 for (;;) {
55765 int num_active = 0;
55766 - for (i = 0; i < fsg_num_buffers; ++i) {
55767 + for (i = 0; i < common->fsg_num_buffers; ++i) {
55768 bh = &common->buffhds[i];
55769 num_active += bh->inreq_busy + bh->outreq_busy;
55770 }
55771 if (num_active == 0)
55772 break;
55773 - if (sleep_thread(common))
55774 + if (sleep_thread(common, true))
55775 return;
55776 }
55777
55778 @@ -2407,7 +2397,7 @@ static void handle_exception(struct fsg_
55779 */
55780 spin_lock_irq(&common->lock);
55781
55782 - for (i = 0; i < fsg_num_buffers; ++i) {
55783 + for (i = 0; i < common->fsg_num_buffers; ++i) {
55784 bh = &common->buffhds[i];
55785 bh->state = BUF_STATE_EMPTY;
55786 }
55787 @@ -2420,7 +2410,9 @@ static void handle_exception(struct fsg_
55788 common->state = FSG_STATE_STATUS_PHASE;
55789 else {
55790 for (i = 0; i < common->nluns; ++i) {
55791 - curlun = &common->luns[i];
55792 + curlun = common->luns[i];
55793 + if (!curlun)
55794 + continue;
55795 curlun->prevent_medium_removal = 0;
55796 curlun->sense_data = SS_NO_SENSE;
55797 curlun->unit_attention_data = SS_NO_SENSE;
55798 @@ -2462,8 +2454,9 @@ static void handle_exception(struct fsg_
55799 * CONFIG_CHANGE cases.
55800 */
55801 /* for (i = 0; i < common->nluns; ++i) */
55802 - /* common->luns[i].unit_attention_data = */
55803 - /* SS_RESET_OCCURRED; */
55804 + /* if (common->luns[i]) */
55805 + /* common->luns[i]->unit_attention_data = */
55806 + /* SS_RESET_OCCURRED; */
55807 break;
55808
55809 case FSG_STATE_CONFIG_CHANGE:
55810 @@ -2524,7 +2517,7 @@ static int fsg_main_thread(void *common_
55811 }
55812
55813 if (!common->running) {
55814 - sleep_thread(common);
55815 + sleep_thread(common, true);
55816 continue;
55817 }
55818
55819 @@ -2559,12 +2552,13 @@ static int fsg_main_thread(void *common_
55820
55821 if (!common->ops || !common->ops->thread_exits
55822 || common->ops->thread_exits(common) < 0) {
55823 - struct fsg_lun *curlun = common->luns;
55824 + struct fsg_lun **curlun_it = common->luns;
55825 unsigned i = common->nluns;
55826
55827 down_write(&common->filesem);
55828 - for (; i--; ++curlun) {
55829 - if (!fsg_lun_is_open(curlun))
55830 + for (; i--; ++curlun_it) {
55831 + struct fsg_lun *curlun = *curlun_it;
55832 + if (!curlun || !fsg_lun_is_open(curlun))
55833 continue;
55834
55835 fsg_lun_close(curlun);
55836 @@ -2580,6 +2574,56 @@ static int fsg_main_thread(void *common_
55837
55838 /*************************** DEVICE ATTRIBUTES ***************************/
55839
55840 +static ssize_t ro_show(struct device *dev, struct device_attribute *attr, char *buf)
55841 +{
55842 + struct fsg_lun *curlun = fsg_lun_from_dev(dev);
55843 +
55844 + return fsg_show_ro(curlun, buf);
55845 +}
55846 +
55847 +static ssize_t nofua_show(struct device *dev, struct device_attribute *attr,
55848 + char *buf)
55849 +{
55850 + struct fsg_lun *curlun = fsg_lun_from_dev(dev);
55851 +
55852 + return fsg_show_nofua(curlun, buf);
55853 +}
55854 +
55855 +static ssize_t file_show(struct device *dev, struct device_attribute *attr,
55856 + char *buf)
55857 +{
55858 + struct fsg_lun *curlun = fsg_lun_from_dev(dev);
55859 + struct rw_semaphore *filesem = dev_get_drvdata(dev);
55860 +
55861 + return fsg_show_file(curlun, filesem, buf);
55862 +}
55863 +
55864 +static ssize_t ro_store(struct device *dev, struct device_attribute *attr,
55865 + const char *buf, size_t count)
55866 +{
55867 + struct fsg_lun *curlun = fsg_lun_from_dev(dev);
55868 + struct rw_semaphore *filesem = dev_get_drvdata(dev);
55869 +
55870 + return fsg_store_ro(curlun, filesem, buf, count);
55871 +}
55872 +
55873 +static ssize_t nofua_store(struct device *dev, struct device_attribute *attr,
55874 + const char *buf, size_t count)
55875 +{
55876 + struct fsg_lun *curlun = fsg_lun_from_dev(dev);
55877 +
55878 + return fsg_store_nofua(curlun, buf, count);
55879 +}
55880 +
55881 +static ssize_t file_store(struct device *dev, struct device_attribute *attr,
55882 + const char *buf, size_t count)
55883 +{
55884 + struct fsg_lun *curlun = fsg_lun_from_dev(dev);
55885 + struct rw_semaphore *filesem = dev_get_drvdata(dev);
55886 +
55887 + return fsg_store_file(curlun, filesem, buf, count);
55888 +}
55889 +
55890 static DEVICE_ATTR_RW(ro);
55891 static DEVICE_ATTR_RW(nofua);
55892 static DEVICE_ATTR_RW(file);
55893 @@ -2597,221 +2641,422 @@ static void fsg_lun_release(struct devic
55894 /* Nothing needs to be done */
55895 }
55896
55897 -static inline void fsg_common_get(struct fsg_common *common)
55898 +void fsg_common_get(struct fsg_common *common)
55899 {
55900 kref_get(&common->ref);
55901 }
55902 +EXPORT_SYMBOL_GPL(fsg_common_get);
55903
55904 -static inline void fsg_common_put(struct fsg_common *common)
55905 +void fsg_common_put(struct fsg_common *common)
55906 {
55907 kref_put(&common->ref, fsg_common_release);
55908 }
55909 +EXPORT_SYMBOL_GPL(fsg_common_put);
55910
55911 -static struct fsg_common *fsg_common_init(struct fsg_common *common,
55912 - struct usb_composite_dev *cdev,
55913 - struct fsg_config *cfg)
55914 -{
55915 - struct usb_gadget *gadget = cdev->gadget;
55916 - struct fsg_buffhd *bh;
55917 - struct fsg_lun *curlun;
55918 - struct fsg_lun_config *lcfg;
55919 - int nluns, i, rc;
55920 - char *pathbuf;
55921 -
55922 - rc = fsg_num_buffers_validate();
55923 - if (rc != 0)
55924 - return ERR_PTR(rc);
55925 -
55926 - /* Find out how many LUNs there should be */
55927 - nluns = cfg->nluns;
55928 - if (nluns < 1 || nluns > FSG_MAX_LUNS) {
55929 - dev_err(&gadget->dev, "invalid number of LUNs: %u\n", nluns);
55930 - return ERR_PTR(-EINVAL);
55931 - }
55932 +/* check if fsg_num_buffers is within a valid range */
55933 +static inline int fsg_num_buffers_validate(unsigned int fsg_num_buffers)
55934 +{
55935 + if (fsg_num_buffers >= 2 && fsg_num_buffers <= 4)
55936 + return 0;
55937 + pr_err("fsg_num_buffers %u is out of range (%d to %d)\n",
55938 + fsg_num_buffers, 2, 4);
55939 + return -EINVAL;
55940 +}
55941
55942 - /* Allocate? */
55943 +static struct fsg_common *fsg_common_setup(struct fsg_common *common)
55944 +{
55945 if (!common) {
55946 - common = kzalloc(sizeof *common, GFP_KERNEL);
55947 + common = kzalloc(sizeof(*common), GFP_KERNEL);
55948 if (!common)
55949 return ERR_PTR(-ENOMEM);
55950 common->free_storage_on_release = 1;
55951 } else {
55952 - memset(common, 0, sizeof *common);
55953 common->free_storage_on_release = 0;
55954 }
55955 + init_rwsem(&common->filesem);
55956 + spin_lock_init(&common->lock);
55957 + kref_init(&common->ref);
55958 + init_completion(&common->thread_notifier);
55959 + init_waitqueue_head(&common->fsg_wait);
55960 + common->state = FSG_STATE_TERMINATED;
55961
55962 - common->buffhds = kcalloc(fsg_num_buffers,
55963 - sizeof *(common->buffhds), GFP_KERNEL);
55964 - if (!common->buffhds) {
55965 - if (common->free_storage_on_release)
55966 - kfree(common);
55967 - return ERR_PTR(-ENOMEM);
55968 + return common;
55969 +}
55970 +
55971 +void fsg_common_set_sysfs(struct fsg_common *common, bool sysfs)
55972 +{
55973 + common->sysfs = sysfs;
55974 +}
55975 +EXPORT_SYMBOL_GPL(fsg_common_set_sysfs);
55976 +
55977 +static void _fsg_common_free_buffers(struct fsg_buffhd *buffhds, unsigned n)
55978 +{
55979 + if (buffhds) {
55980 + struct fsg_buffhd *bh = buffhds;
55981 + while (n--) {
55982 + kfree(bh->buf);
55983 + ++bh;
55984 + }
55985 + kfree(buffhds);
55986 }
55987 +}
55988
55989 - common->ops = cfg->ops;
55990 - common->private_data = cfg->private_data;
55991 +int fsg_common_set_num_buffers(struct fsg_common *common, unsigned int n)
55992 +{
55993 + struct fsg_buffhd *bh, *buffhds;
55994 + int i, rc;
55995
55996 - common->gadget = gadget;
55997 - common->ep0 = gadget->ep0;
55998 - common->ep0req = cdev->req;
55999 - common->cdev = cdev;
56000 + rc = fsg_num_buffers_validate(n);
56001 + if (rc != 0)
56002 + return rc;
56003
56004 - /* Maybe allocate device-global string IDs, and patch descriptors */
56005 - if (fsg_strings[FSG_STRING_INTERFACE].id == 0) {
56006 - rc = usb_string_id(cdev);
56007 - if (unlikely(rc < 0))
56008 + buffhds = kcalloc(n, sizeof(*buffhds), GFP_KERNEL);
56009 + if (!buffhds)
56010 + return -ENOMEM;
56011 +
56012 + /* Data buffers cyclic list */
56013 + bh = buffhds;
56014 + i = n;
56015 + goto buffhds_first_it;
56016 + do {
56017 + bh->next = bh + 1;
56018 + ++bh;
56019 +buffhds_first_it:
56020 + bh->buf = kmalloc(FSG_BUFLEN, GFP_KERNEL);
56021 + if (unlikely(!bh->buf))
56022 goto error_release;
56023 - fsg_strings[FSG_STRING_INTERFACE].id = rc;
56024 - fsg_intf_desc.iInterface = rc;
56025 - }
56026 + } while (--i);
56027 + bh->next = buffhds;
56028 +
56029 + _fsg_common_free_buffers(common->buffhds, common->fsg_num_buffers);
56030 + common->fsg_num_buffers = n;
56031 + common->buffhds = buffhds;
56032 +
56033 + return 0;
56034
56035 +error_release:
56036 /*
56037 - * Create the LUNs, open their backing files, and register the
56038 - * LUN devices in sysfs.
56039 + * "buf"s pointed to by heads after n - i are NULL
56040 + * so releasing them won't hurt
56041 */
56042 - curlun = kcalloc(nluns, sizeof(*curlun), GFP_KERNEL);
56043 - if (unlikely(!curlun)) {
56044 - rc = -ENOMEM;
56045 - goto error_release;
56046 - }
56047 - common->luns = curlun;
56048 + _fsg_common_free_buffers(buffhds, n);
56049
56050 - init_rwsem(&common->filesem);
56051 + return -ENOMEM;
56052 +}
56053 +EXPORT_SYMBOL_GPL(fsg_common_set_num_buffers);
56054
56055 - for (i = 0, lcfg = cfg->luns; i < nluns; ++i, ++curlun, ++lcfg) {
56056 - curlun->cdrom = !!lcfg->cdrom;
56057 - curlun->ro = lcfg->cdrom || lcfg->ro;
56058 - curlun->initially_ro = curlun->ro;
56059 - curlun->removable = lcfg->removable;
56060 - curlun->dev.release = fsg_lun_release;
56061 - curlun->dev.parent = &gadget->dev;
56062 - /* curlun->dev.driver = &fsg_driver.driver; XXX */
56063 - dev_set_drvdata(&curlun->dev, &common->filesem);
56064 - dev_set_name(&curlun->dev, "lun%d", i);
56065 +static inline void fsg_common_remove_sysfs(struct fsg_lun *lun)
56066 +{
56067 + device_remove_file(&lun->dev, &dev_attr_nofua);
56068 + /*
56069 + * device_remove_file() =>
56070 + *
56071 + * here the attr (e.g. dev_attr_ro) is only used to be passed to:
56072 + *
56073 + * sysfs_remove_file() =>
56074 + *
56075 + * here e.g. both dev_attr_ro_cdrom and dev_attr_ro are in
56076 + * the same namespace and
56077 + * from here only attr->name is passed to:
56078 + *
56079 + * sysfs_hash_and_remove()
56080 + *
56081 + * attr->name is the same for dev_attr_ro_cdrom and
56082 + * dev_attr_ro
56083 + * attr->name is the same for dev_attr_file and
56084 + * dev_attr_file_nonremovable
56085 + *
56086 + * so we don't differentiate between removing e.g. dev_attr_ro_cdrom
56087 + * and dev_attr_ro
56088 + */
56089 + device_remove_file(&lun->dev, &dev_attr_ro);
56090 + device_remove_file(&lun->dev, &dev_attr_file);
56091 +}
56092
56093 - rc = device_register(&curlun->dev);
56094 - if (rc) {
56095 - INFO(common, "failed to register LUN%d: %d\n", i, rc);
56096 - common->nluns = i;
56097 - put_device(&curlun->dev);
56098 - goto error_release;
56099 - }
56100 +void fsg_common_remove_lun(struct fsg_lun *lun, bool sysfs)
56101 +{
56102 + if (sysfs) {
56103 + fsg_common_remove_sysfs(lun);
56104 + device_unregister(&lun->dev);
56105 + }
56106 + fsg_lun_close(lun);
56107 + kfree(lun);
56108 +}
56109 +EXPORT_SYMBOL_GPL(fsg_common_remove_lun);
56110
56111 - rc = device_create_file(&curlun->dev,
56112 - curlun->cdrom
56113 - ? &dev_attr_ro_cdrom
56114 - : &dev_attr_ro);
56115 - if (rc)
56116 - goto error_luns;
56117 - rc = device_create_file(&curlun->dev,
56118 - curlun->removable
56119 - ? &dev_attr_file
56120 - : &dev_attr_file_nonremovable);
56121 - if (rc)
56122 - goto error_luns;
56123 - rc = device_create_file(&curlun->dev, &dev_attr_nofua);
56124 - if (rc)
56125 - goto error_luns;
56126 +static void _fsg_common_remove_luns(struct fsg_common *common, int n)
56127 +{
56128 + int i;
56129
56130 - if (lcfg->filename) {
56131 - rc = fsg_lun_open(curlun, lcfg->filename);
56132 - if (rc)
56133 - goto error_luns;
56134 - } else if (!curlun->removable) {
56135 - ERROR(common, "no file given for LUN%d\n", i);
56136 - rc = -EINVAL;
56137 - goto error_luns;
56138 + for (i = 0; i < n; ++i)
56139 + if (common->luns[i]) {
56140 + fsg_common_remove_lun(common->luns[i], common->sysfs);
56141 + common->luns[i] = NULL;
56142 }
56143 +}
56144 +EXPORT_SYMBOL_GPL(fsg_common_remove_luns);
56145 +
56146 +void fsg_common_remove_luns(struct fsg_common *common)
56147 +{
56148 + _fsg_common_remove_luns(common, common->nluns);
56149 +}
56150 +
56151 +void fsg_common_free_luns(struct fsg_common *common)
56152 +{
56153 + fsg_common_remove_luns(common);
56154 + kfree(common->luns);
56155 + common->luns = NULL;
56156 +}
56157 +EXPORT_SYMBOL_GPL(fsg_common_free_luns);
56158 +
56159 +int fsg_common_set_nluns(struct fsg_common *common, int nluns)
56160 +{
56161 + struct fsg_lun **curlun;
56162 +
56163 + /* Find out how many LUNs there should be */
56164 + if (nluns < 1 || nluns > FSG_MAX_LUNS) {
56165 + pr_err("invalid number of LUNs: %u\n", nluns);
56166 + return -EINVAL;
56167 }
56168 +
56169 + curlun = kcalloc(nluns, sizeof(*curlun), GFP_KERNEL);
56170 + if (unlikely(!curlun))
56171 + return -ENOMEM;
56172 +
56173 + if (common->luns)
56174 + fsg_common_free_luns(common);
56175 +
56176 + common->luns = curlun;
56177 common->nluns = nluns;
56178
56179 - /* Data buffers cyclic list */
56180 - bh = common->buffhds;
56181 - i = fsg_num_buffers;
56182 - goto buffhds_first_it;
56183 - do {
56184 - bh->next = bh + 1;
56185 - ++bh;
56186 -buffhds_first_it:
56187 - bh->buf = kmalloc(FSG_BUFLEN, GFP_KERNEL);
56188 - if (unlikely(!bh->buf)) {
56189 - rc = -ENOMEM;
56190 - goto error_release;
56191 - }
56192 - } while (--i);
56193 - bh->next = common->buffhds;
56194 + pr_info("Number of LUNs=%d\n", common->nluns);
56195
56196 - /* Prepare inquiryString */
56197 - i = get_default_bcdDevice();
56198 - snprintf(common->inquiry_string, sizeof common->inquiry_string,
56199 - "%-8s%-16s%04x", cfg->vendor_name ?: "Linux",
56200 - /* Assume product name dependent on the first LUN */
56201 - cfg->product_name ?: (common->luns->cdrom
56202 - ? "File-CD Gadget"
56203 - : "File-Stor Gadget"),
56204 - i);
56205 + return 0;
56206 +}
56207 +EXPORT_SYMBOL_GPL(fsg_common_set_nluns);
56208 +
56209 +void fsg_common_set_ops(struct fsg_common *common,
56210 + const struct fsg_operations *ops)
56211 +{
56212 + common->ops = ops;
56213 +}
56214 +EXPORT_SYMBOL_GPL(fsg_common_set_ops);
56215 +
56216 +void fsg_common_free_buffers(struct fsg_common *common)
56217 +{
56218 + _fsg_common_free_buffers(common->buffhds, common->fsg_num_buffers);
56219 + common->buffhds = NULL;
56220 +}
56221 +EXPORT_SYMBOL_GPL(fsg_common_free_buffers);
56222 +
56223 +int fsg_common_set_cdev(struct fsg_common *common,
56224 + struct usb_composite_dev *cdev, bool can_stall)
56225 +{
56226 + struct usb_string *us;
56227 +
56228 + common->gadget = cdev->gadget;
56229 + common->ep0 = cdev->gadget->ep0;
56230 + common->ep0req = cdev->req;
56231 + common->cdev = cdev;
56232 +
56233 + us = usb_gstrings_attach(cdev, fsg_strings_array,
56234 + ARRAY_SIZE(fsg_strings));
56235 + if (IS_ERR(us))
56236 + return PTR_ERR(us);
56237 +
56238 + fsg_intf_desc.iInterface = us[FSG_STRING_INTERFACE].id;
56239
56240 /*
56241 * Some peripheral controllers are known not to be able to
56242 * halt bulk endpoints correctly. If one of them is present,
56243 * disable stalls.
56244 */
56245 - common->can_stall = cfg->can_stall &&
56246 - !(gadget_is_at91(common->gadget));
56247 + common->can_stall = can_stall && !(gadget_is_at91(common->gadget));
56248
56249 - spin_lock_init(&common->lock);
56250 - kref_init(&common->ref);
56251 + return 0;
56252 +}
56253 +EXPORT_SYMBOL_GPL(fsg_common_set_cdev);
56254
56255 - /* Tell the thread to start working */
56256 - common->thread_task =
56257 - kthread_create(fsg_main_thread, common, "file-storage");
56258 - if (IS_ERR(common->thread_task)) {
56259 - rc = PTR_ERR(common->thread_task);
56260 - goto error_release;
56261 +static inline int fsg_common_add_sysfs(struct fsg_common *common,
56262 + struct fsg_lun *lun)
56263 +{
56264 + int rc;
56265 +
56266 + rc = device_register(&lun->dev);
56267 + if (rc) {
56268 + put_device(&lun->dev);
56269 + return rc;
56270 }
56271 - init_completion(&common->thread_notifier);
56272 - init_waitqueue_head(&common->fsg_wait);
56273
56274 - /* Information */
56275 - INFO(common, FSG_DRIVER_DESC ", version: " FSG_DRIVER_VERSION "\n");
56276 - INFO(common, "Number of LUNs=%d\n", common->nluns);
56277 + rc = device_create_file(&lun->dev,
56278 + lun->cdrom
56279 + ? &dev_attr_ro_cdrom
56280 + : &dev_attr_ro);
56281 + if (rc)
56282 + goto error;
56283 + rc = device_create_file(&lun->dev,
56284 + lun->removable
56285 + ? &dev_attr_file
56286 + : &dev_attr_file_nonremovable);
56287 + if (rc)
56288 + goto error;
56289 + rc = device_create_file(&lun->dev, &dev_attr_nofua);
56290 + if (rc)
56291 + goto error;
56292 +
56293 + return 0;
56294 +
56295 +error:
56296 + /* removing nonexistent files is a no-op */
56297 + fsg_common_remove_sysfs(lun);
56298 + device_unregister(&lun->dev);
56299 + return rc;
56300 +}
56301 +
56302 +int fsg_common_create_lun(struct fsg_common *common, struct fsg_lun_config *cfg,
56303 + unsigned int id, const char *name,
56304 + const char **name_pfx)
56305 +{
56306 + struct fsg_lun *lun;
56307 + char *pathbuf, *p;
56308 + int rc = -ENOMEM;
56309 +
56310 + if (!common->nluns || !common->luns)
56311 + return -ENODEV;
56312 +
56313 + if (common->luns[id])
56314 + return -EBUSY;
56315 +
56316 + if (!cfg->filename && !cfg->removable) {
56317 + pr_err("no file given for LUN%d\n", id);
56318 + return -EINVAL;
56319 + }
56320 +
56321 + lun = kzalloc(sizeof(*lun), GFP_KERNEL);
56322 + if (!lun)
56323 + return -ENOMEM;
56324 +
56325 + lun->name_pfx = name_pfx;
56326 +
56327 + lun->cdrom = !!cfg->cdrom;
56328 + lun->ro = cfg->cdrom || cfg->ro;
56329 + lun->initially_ro = lun->ro;
56330 + lun->removable = !!cfg->removable;
56331 +
56332 + if (!common->sysfs) {
56333 + /* we DON'T own the name!*/
56334 + lun->name = name;
56335 + } else {
56336 + lun->dev.release = fsg_lun_release;
56337 + lun->dev.parent = &common->gadget->dev;
56338 + dev_set_drvdata(&lun->dev, &common->filesem);
56339 + dev_set_name(&lun->dev, name);
56340 + lun->name = dev_name(&lun->dev);
56341 +
56342 + rc = fsg_common_add_sysfs(common, lun);
56343 + if (rc) {
56344 + pr_info("failed to register LUN%d: %d\n", id, rc);
56345 + goto error_sysfs;
56346 + }
56347 + }
56348 +
56349 + common->luns[id] = lun;
56350 +
56351 + if (cfg->filename) {
56352 + rc = fsg_lun_open(lun, cfg->filename);
56353 + if (rc)
56354 + goto error_lun;
56355 + }
56356
56357 pathbuf = kmalloc(PATH_MAX, GFP_KERNEL);
56358 - for (i = 0, nluns = common->nluns, curlun = common->luns;
56359 - i < nluns;
56360 - ++curlun, ++i) {
56361 - char *p = "(no medium)";
56362 - if (fsg_lun_is_open(curlun)) {
56363 - p = "(error)";
56364 - if (pathbuf) {
56365 - p = d_path(&curlun->filp->f_path,
56366 - pathbuf, PATH_MAX);
56367 - if (IS_ERR(p))
56368 - p = "(error)";
56369 - }
56370 + p = "(no medium)";
56371 + if (fsg_lun_is_open(lun)) {
56372 + p = "(error)";
56373 + if (pathbuf) {
56374 + p = d_path(&lun->filp->f_path, pathbuf, PATH_MAX);
56375 + if (IS_ERR(p))
56376 + p = "(error)";
56377 }
56378 - LINFO(curlun, "LUN: %s%s%sfile: %s\n",
56379 - curlun->removable ? "removable " : "",
56380 - curlun->ro ? "read only " : "",
56381 - curlun->cdrom ? "CD-ROM " : "",
56382 - p);
56383 }
56384 + pr_info("LUN: %s%s%sfile: %s\n",
56385 + lun->removable ? "removable " : "",
56386 + lun->ro ? "read only " : "",
56387 + lun->cdrom ? "CD-ROM " : "",
56388 + p);
56389 kfree(pathbuf);
56390
56391 + return 0;
56392 +
56393 +error_lun:
56394 + if (common->sysfs) {
56395 + fsg_common_remove_sysfs(lun);
56396 + device_unregister(&lun->dev);
56397 + }
56398 + fsg_lun_close(lun);
56399 + common->luns[id] = NULL;
56400 +error_sysfs:
56401 + kfree(lun);
56402 + return rc;
56403 +}
56404 +EXPORT_SYMBOL_GPL(fsg_common_create_lun);
56405 +
56406 +int fsg_common_create_luns(struct fsg_common *common, struct fsg_config *cfg)
56407 +{
56408 + char buf[8]; /* enough for 100000000 different numbers, decimal */
56409 + int i, rc;
56410 +
56411 + for (i = 0; i < common->nluns; ++i) {
56412 + snprintf(buf, sizeof(buf), "lun%d", i);
56413 + rc = fsg_common_create_lun(common, &cfg->luns[i], i, buf, NULL);
56414 + if (rc)
56415 + goto fail;
56416 + }
56417 +
56418 + pr_info("Number of LUNs=%d\n", common->nluns);
56419 +
56420 + return 0;
56421 +
56422 +fail:
56423 + _fsg_common_remove_luns(common, i);
56424 + return rc;
56425 +}
56426 +EXPORT_SYMBOL_GPL(fsg_common_create_luns);
56427 +
56428 +void fsg_common_set_inquiry_string(struct fsg_common *common, const char *vn,
56429 + const char *pn)
56430 +{
56431 + int i;
56432 +
56433 + /* Prepare inquiryString */
56434 + i = get_default_bcdDevice();
56435 + snprintf(common->inquiry_string, sizeof(common->inquiry_string),
56436 + "%-8s%-16s%04x", vn ?: "Linux",
56437 + /* Assume product name dependent on the first LUN */
56438 + pn ?: ((*common->luns)->cdrom
56439 + ? "File-CD Gadget"
56440 + : "File-Stor Gadget"),
56441 + i);
56442 +}
56443 +EXPORT_SYMBOL_GPL(fsg_common_set_inquiry_string);
56444 +
56445 +int fsg_common_run_thread(struct fsg_common *common)
56446 +{
56447 + common->state = FSG_STATE_IDLE;
56448 + /* Tell the thread to start working */
56449 + common->thread_task =
56450 + kthread_create(fsg_main_thread, common, "file-storage");
56451 + if (IS_ERR(common->thread_task)) {
56452 + common->state = FSG_STATE_TERMINATED;
56453 + return PTR_ERR(common->thread_task);
56454 + }
56455 +
56456 DBG(common, "I/O thread pid: %d\n", task_pid_nr(common->thread_task));
56457
56458 wake_up_process(common->thread_task);
56459
56460 - return common;
56461 -
56462 -error_luns:
56463 - common->nluns = i + 1;
56464 -error_release:
56465 - common->state = FSG_STATE_TERMINATED; /* The thread is dead */
56466 - /* Call fsg_common_release() directly, ref might be not initialised. */
56467 - fsg_common_release(&common->ref);
56468 - return ERR_PTR(rc);
56469 + return 0;
56470 }
56471 +EXPORT_SYMBOL_GPL(fsg_common_run_thread);
56472
56473 static void fsg_common_release(struct kref *ref)
56474 {
56475 @@ -2824,36 +3069,26 @@ static void fsg_common_release(struct kr
56476 }
56477
56478 if (likely(common->luns)) {
56479 - struct fsg_lun *lun = common->luns;
56480 + struct fsg_lun **lun_it = common->luns;
56481 unsigned i = common->nluns;
56482
56483 /* In error recovery common->nluns may be zero. */
56484 - for (; i; --i, ++lun) {
56485 - device_remove_file(&lun->dev, &dev_attr_nofua);
56486 - device_remove_file(&lun->dev,
56487 - lun->cdrom
56488 - ? &dev_attr_ro_cdrom
56489 - : &dev_attr_ro);
56490 - device_remove_file(&lun->dev,
56491 - lun->removable
56492 - ? &dev_attr_file
56493 - : &dev_attr_file_nonremovable);
56494 + for (; i; --i, ++lun_it) {
56495 + struct fsg_lun *lun = *lun_it;
56496 + if (!lun)
56497 + continue;
56498 + if (common->sysfs)
56499 + fsg_common_remove_sysfs(lun);
56500 fsg_lun_close(lun);
56501 - device_unregister(&lun->dev);
56502 + if (common->sysfs)
56503 + device_unregister(&lun->dev);
56504 + kfree(lun);
56505 }
56506
56507 kfree(common->luns);
56508 }
56509
56510 - {
56511 - struct fsg_buffhd *bh = common->buffhds;
56512 - unsigned i = fsg_num_buffers;
56513 - do {
56514 - kfree(bh->buf);
56515 - } while (++bh, --i);
56516 - }
56517 -
56518 - kfree(common->buffhds);
56519 + _fsg_common_free_buffers(common->buffhds, common->fsg_num_buffers);
56520 if (common->free_storage_on_release)
56521 kfree(common);
56522 }
56523 @@ -2861,24 +3096,6 @@ static void fsg_common_release(struct kr
56524
56525 /*-------------------------------------------------------------------------*/
56526
56527 -static void fsg_unbind(struct usb_configuration *c, struct usb_function *f)
56528 -{
56529 - struct fsg_dev *fsg = fsg_from_func(f);
56530 - struct fsg_common *common = fsg->common;
56531 -
56532 - DBG(fsg, "unbind\n");
56533 - if (fsg->common->fsg == fsg) {
56534 - fsg->common->new_fsg = NULL;
56535 - raise_exception(fsg->common, FSG_STATE_CONFIG_CHANGE);
56536 - /* FIXME: make interruptible or killable somehow? */
56537 - wait_event(common->fsg_wait, common->fsg != fsg);
56538 - }
56539 -
56540 - fsg_common_put(common);
56541 - usb_free_all_descriptors(&fsg->function);
56542 - kfree(fsg);
56543 -}
56544 -
56545 static int fsg_bind(struct usb_configuration *c, struct usb_function *f)
56546 {
56547 struct fsg_dev *fsg = fsg_from_func(f);
56548 @@ -2887,6 +3104,19 @@ static int fsg_bind(struct usb_configura
56549 struct usb_ep *ep;
56550 unsigned max_burst;
56551 int ret;
56552 + struct fsg_opts *opts;
56553 +
56554 + opts = fsg_opts_from_func_inst(f->fi);
56555 + if (!opts->no_configfs) {
56556 + ret = fsg_common_set_cdev(fsg->common, c->cdev,
56557 + fsg->common->can_stall);
56558 + if (ret)
56559 + return ret;
56560 + fsg_common_set_inquiry_string(fsg->common, 0, 0);
56561 + ret = fsg_common_run_thread(fsg->common);
56562 + if (ret)
56563 + return ret;
56564 + }
56565
56566 fsg->gadget = gadget;
56567
56568 @@ -2939,95 +3169,472 @@ autoconf_fail:
56569 return -ENOTSUPP;
56570 }
56571
56572 -/****************************** ADD FUNCTION ******************************/
56573 +/****************************** ALLOCATE FUNCTION *************************/
56574
56575 -static struct usb_gadget_strings *fsg_strings_array[] = {
56576 - &fsg_stringtab,
56577 +static void fsg_unbind(struct usb_configuration *c, struct usb_function *f)
56578 +{
56579 + struct fsg_dev *fsg = fsg_from_func(f);
56580 + struct fsg_common *common = fsg->common;
56581 +
56582 + DBG(fsg, "unbind\n");
56583 + if (fsg->common->fsg == fsg) {
56584 + fsg->common->new_fsg = NULL;
56585 + raise_exception(fsg->common, FSG_STATE_CONFIG_CHANGE);
56586 + /* FIXME: make interruptible or killable somehow? */
56587 + wait_event(common->fsg_wait, common->fsg != fsg);
56588 + }
56589 +
56590 + usb_free_all_descriptors(&fsg->function);
56591 +}
56592 +
56593 +static inline struct fsg_lun_opts *to_fsg_lun_opts(struct config_item *item)
56594 +{
56595 + return container_of(to_config_group(item), struct fsg_lun_opts, group);
56596 +}
56597 +
56598 +static inline struct fsg_opts *to_fsg_opts(struct config_item *item)
56599 +{
56600 + return container_of(to_config_group(item), struct fsg_opts,
56601 + func_inst.group);
56602 +}
56603 +
56604 +CONFIGFS_ATTR_STRUCT(fsg_lun_opts);
56605 +CONFIGFS_ATTR_OPS(fsg_lun_opts);
56606 +
56607 +static void fsg_lun_attr_release(struct config_item *item)
56608 +{
56609 + struct fsg_lun_opts *lun_opts;
56610 +
56611 + lun_opts = to_fsg_lun_opts(item);
56612 + kfree(lun_opts);
56613 +}
56614 +
56615 +static struct configfs_item_operations fsg_lun_item_ops = {
56616 + .release = fsg_lun_attr_release,
56617 + .show_attribute = fsg_lun_opts_attr_show,
56618 + .store_attribute = fsg_lun_opts_attr_store,
56619 +};
56620 +
56621 +static ssize_t fsg_lun_opts_file_show(struct fsg_lun_opts *opts, char *page)
56622 +{
56623 + struct fsg_opts *fsg_opts;
56624 +
56625 + fsg_opts = to_fsg_opts(opts->group.cg_item.ci_parent);
56626 +
56627 + return fsg_show_file(opts->lun, &fsg_opts->common->filesem, page);
56628 +}
56629 +
56630 +static ssize_t fsg_lun_opts_file_store(struct fsg_lun_opts *opts,
56631 + const char *page, size_t len)
56632 +{
56633 + struct fsg_opts *fsg_opts;
56634 +
56635 + fsg_opts = to_fsg_opts(opts->group.cg_item.ci_parent);
56636 +
56637 + return fsg_store_file(opts->lun, &fsg_opts->common->filesem, page, len);
56638 +}
56639 +
56640 +static struct fsg_lun_opts_attribute fsg_lun_opts_file =
56641 + __CONFIGFS_ATTR(file, S_IRUGO | S_IWUSR, fsg_lun_opts_file_show,
56642 + fsg_lun_opts_file_store);
56643 +
56644 +static ssize_t fsg_lun_opts_ro_show(struct fsg_lun_opts *opts, char *page)
56645 +{
56646 + return fsg_show_ro(opts->lun, page);
56647 +}
56648 +
56649 +static ssize_t fsg_lun_opts_ro_store(struct fsg_lun_opts *opts,
56650 + const char *page, size_t len)
56651 +{
56652 + struct fsg_opts *fsg_opts;
56653 +
56654 + fsg_opts = to_fsg_opts(opts->group.cg_item.ci_parent);
56655 +
56656 + return fsg_store_ro(opts->lun, &fsg_opts->common->filesem, page, len);
56657 +}
56658 +
56659 +static struct fsg_lun_opts_attribute fsg_lun_opts_ro =
56660 + __CONFIGFS_ATTR(ro, S_IRUGO | S_IWUSR, fsg_lun_opts_ro_show,
56661 + fsg_lun_opts_ro_store);
56662 +
56663 +static ssize_t fsg_lun_opts_removable_show(struct fsg_lun_opts *opts,
56664 + char *page)
56665 +{
56666 + return fsg_show_removable(opts->lun, page);
56667 +}
56668 +
56669 +static ssize_t fsg_lun_opts_removable_store(struct fsg_lun_opts *opts,
56670 + const char *page, size_t len)
56671 +{
56672 + return fsg_store_removable(opts->lun, page, len);
56673 +}
56674 +
56675 +static struct fsg_lun_opts_attribute fsg_lun_opts_removable =
56676 + __CONFIGFS_ATTR(removable, S_IRUGO | S_IWUSR,
56677 + fsg_lun_opts_removable_show,
56678 + fsg_lun_opts_removable_store);
56679 +
56680 +static ssize_t fsg_lun_opts_cdrom_show(struct fsg_lun_opts *opts, char *page)
56681 +{
56682 + return fsg_show_cdrom(opts->lun, page);
56683 +}
56684 +
56685 +static ssize_t fsg_lun_opts_cdrom_store(struct fsg_lun_opts *opts,
56686 + const char *page, size_t len)
56687 +{
56688 + struct fsg_opts *fsg_opts;
56689 +
56690 + fsg_opts = to_fsg_opts(opts->group.cg_item.ci_parent);
56691 +
56692 + return fsg_store_cdrom(opts->lun, &fsg_opts->common->filesem, page,
56693 + len);
56694 +}
56695 +
56696 +static struct fsg_lun_opts_attribute fsg_lun_opts_cdrom =
56697 + __CONFIGFS_ATTR(cdrom, S_IRUGO | S_IWUSR, fsg_lun_opts_cdrom_show,
56698 + fsg_lun_opts_cdrom_store);
56699 +
56700 +static ssize_t fsg_lun_opts_nofua_show(struct fsg_lun_opts *opts, char *page)
56701 +{
56702 + return fsg_show_nofua(opts->lun, page);
56703 +}
56704 +
56705 +static ssize_t fsg_lun_opts_nofua_store(struct fsg_lun_opts *opts,
56706 + const char *page, size_t len)
56707 +{
56708 + return fsg_store_nofua(opts->lun, page, len);
56709 +}
56710 +
56711 +static struct fsg_lun_opts_attribute fsg_lun_opts_nofua =
56712 + __CONFIGFS_ATTR(nofua, S_IRUGO | S_IWUSR, fsg_lun_opts_nofua_show,
56713 + fsg_lun_opts_nofua_store);
56714 +
56715 +static struct configfs_attribute *fsg_lun_attrs[] = {
56716 + &fsg_lun_opts_file.attr,
56717 + &fsg_lun_opts_ro.attr,
56718 + &fsg_lun_opts_removable.attr,
56719 + &fsg_lun_opts_cdrom.attr,
56720 + &fsg_lun_opts_nofua.attr,
56721 NULL,
56722 };
56723
56724 -static int fsg_bind_config(struct usb_composite_dev *cdev,
56725 - struct usb_configuration *c,
56726 - struct fsg_common *common)
56727 +static struct config_item_type fsg_lun_type = {
56728 + .ct_item_ops = &fsg_lun_item_ops,
56729 + .ct_attrs = fsg_lun_attrs,
56730 + .ct_owner = THIS_MODULE,
56731 +};
56732 +
56733 +static struct config_group *fsg_lun_make(struct config_group *group,
56734 + const char *name)
56735 {
56736 - struct fsg_dev *fsg;
56737 + struct fsg_lun_opts *opts;
56738 + struct fsg_opts *fsg_opts;
56739 + struct fsg_lun_config config;
56740 + char *num_str;
56741 + u8 num;
56742 + int ret;
56743 +
56744 + num_str = strchr(name, '.');
56745 + if (!num_str) {
56746 + pr_err("Unable to locate . in LUN.NUMBER\n");
56747 + return ERR_PTR(-EINVAL);
56748 + }
56749 + num_str++;
56750 +
56751 + ret = kstrtou8(num_str, 0, &num);
56752 + if (ret)
56753 + return ERR_PTR(ret);
56754 +
56755 + fsg_opts = to_fsg_opts(&group->cg_item);
56756 + if (num >= FSG_MAX_LUNS)
56757 + return ERR_PTR(-ERANGE);
56758 +
56759 + mutex_lock(&fsg_opts->lock);
56760 + if (fsg_opts->refcnt || fsg_opts->common->luns[num]) {
56761 + ret = -EBUSY;
56762 + goto out;
56763 + }
56764 +
56765 + opts = kzalloc(sizeof(*opts), GFP_KERNEL);
56766 + if (!opts) {
56767 + ret = -ENOMEM;
56768 + goto out;
56769 + }
56770 +
56771 + memset(&config, 0, sizeof(config));
56772 + config.removable = true;
56773 +
56774 + ret = fsg_common_create_lun(fsg_opts->common, &config, num, name,
56775 + (const char **)&group->cg_item.ci_name);
56776 + if (ret) {
56777 + kfree(opts);
56778 + goto out;
56779 + }
56780 + opts->lun = fsg_opts->common->luns[num];
56781 + opts->lun_id = num;
56782 + mutex_unlock(&fsg_opts->lock);
56783 +
56784 + config_group_init_type_name(&opts->group, name, &fsg_lun_type);
56785 +
56786 + return &opts->group;
56787 +out:
56788 + mutex_unlock(&fsg_opts->lock);
56789 + return ERR_PTR(ret);
56790 +}
56791 +
56792 +static void fsg_lun_drop(struct config_group *group, struct config_item *item)
56793 +{
56794 + struct fsg_lun_opts *lun_opts;
56795 + struct fsg_opts *fsg_opts;
56796 +
56797 + lun_opts = to_fsg_lun_opts(item);
56798 + fsg_opts = to_fsg_opts(&group->cg_item);
56799 +
56800 + mutex_lock(&fsg_opts->lock);
56801 + if (fsg_opts->refcnt) {
56802 + struct config_item *gadget;
56803 +
56804 + gadget = group->cg_item.ci_parent->ci_parent;
56805 + unregister_gadget_item(gadget);
56806 + }
56807 +
56808 + fsg_common_remove_lun(lun_opts->lun, fsg_opts->common->sysfs);
56809 + fsg_opts->common->luns[lun_opts->lun_id] = NULL;
56810 + lun_opts->lun_id = 0;
56811 + mutex_unlock(&fsg_opts->lock);
56812 +
56813 + config_item_put(item);
56814 +}
56815 +
56816 +CONFIGFS_ATTR_STRUCT(fsg_opts);
56817 +CONFIGFS_ATTR_OPS(fsg_opts);
56818 +
56819 +static void fsg_attr_release(struct config_item *item)
56820 +{
56821 + struct fsg_opts *opts = to_fsg_opts(item);
56822 +
56823 + usb_put_function_instance(&opts->func_inst);
56824 +}
56825 +
56826 +static struct configfs_item_operations fsg_item_ops = {
56827 + .release = fsg_attr_release,
56828 + .show_attribute = fsg_opts_attr_show,
56829 + .store_attribute = fsg_opts_attr_store,
56830 +};
56831 +
56832 +static ssize_t fsg_opts_stall_show(struct fsg_opts *opts, char *page)
56833 +{
56834 + int result;
56835 +
56836 + mutex_lock(&opts->lock);
56837 + result = sprintf(page, "%d", opts->common->can_stall);
56838 + mutex_unlock(&opts->lock);
56839 +
56840 + return result;
56841 +}
56842 +
56843 +static ssize_t fsg_opts_stall_store(struct fsg_opts *opts, const char *page,
56844 + size_t len)
56845 +{
56846 + int ret;
56847 + bool stall;
56848 +
56849 + mutex_lock(&opts->lock);
56850 +
56851 + if (opts->refcnt) {
56852 + mutex_unlock(&opts->lock);
56853 + return -EBUSY;
56854 + }
56855 +
56856 + ret = strtobool(page, &stall);
56857 + if (!ret) {
56858 + opts->common->can_stall = stall;
56859 + ret = len;
56860 + }
56861 +
56862 + mutex_unlock(&opts->lock);
56863 +
56864 + return ret;
56865 +}
56866 +
56867 +static struct fsg_opts_attribute fsg_opts_stall =
56868 + __CONFIGFS_ATTR(stall, S_IRUGO | S_IWUSR, fsg_opts_stall_show,
56869 + fsg_opts_stall_store);
56870 +
56871 +#ifdef CONFIG_USB_GADGET_DEBUG_FILES
56872 +static ssize_t fsg_opts_num_buffers_show(struct fsg_opts *opts, char *page)
56873 +{
56874 + int result;
56875 +
56876 + mutex_lock(&opts->lock);
56877 + result = sprintf(page, "%d", opts->common->fsg_num_buffers);
56878 + mutex_unlock(&opts->lock);
56879 +
56880 + return result;
56881 +}
56882 +
56883 +static ssize_t fsg_opts_num_buffers_store(struct fsg_opts *opts,
56884 + const char *page, size_t len)
56885 +{
56886 + int ret;
56887 + u8 num;
56888 +
56889 + mutex_lock(&opts->lock);
56890 + if (opts->refcnt) {
56891 + ret = -EBUSY;
56892 + goto end;
56893 + }
56894 + ret = kstrtou8(page, 0, &num);
56895 + if (ret)
56896 + goto end;
56897 +
56898 + ret = fsg_num_buffers_validate(num);
56899 + if (ret)
56900 + goto end;
56901 +
56902 + fsg_common_set_num_buffers(opts->common, num);
56903 + ret = len;
56904 +
56905 +end:
56906 + mutex_unlock(&opts->lock);
56907 + return ret;
56908 +}
56909 +
56910 +static struct fsg_opts_attribute fsg_opts_num_buffers =
56911 + __CONFIGFS_ATTR(num_buffers, S_IRUGO | S_IWUSR,
56912 + fsg_opts_num_buffers_show,
56913 + fsg_opts_num_buffers_store);
56914 +
56915 +#endif
56916 +
56917 +static struct configfs_attribute *fsg_attrs[] = {
56918 + &fsg_opts_stall.attr,
56919 +#ifdef CONFIG_USB_GADGET_DEBUG_FILES
56920 + &fsg_opts_num_buffers.attr,
56921 +#endif
56922 + NULL,
56923 +};
56924 +
56925 +static struct configfs_group_operations fsg_group_ops = {
56926 + .make_group = fsg_lun_make,
56927 + .drop_item = fsg_lun_drop,
56928 +};
56929 +
56930 +static struct config_item_type fsg_func_type = {
56931 + .ct_item_ops = &fsg_item_ops,
56932 + .ct_group_ops = &fsg_group_ops,
56933 + .ct_attrs = fsg_attrs,
56934 + .ct_owner = THIS_MODULE,
56935 +};
56936 +
56937 +static void fsg_free_inst(struct usb_function_instance *fi)
56938 +{
56939 + struct fsg_opts *opts;
56940 +
56941 + opts = fsg_opts_from_func_inst(fi);
56942 + fsg_common_put(opts->common);
56943 + kfree(opts);
56944 +}
56945 +
56946 +static struct usb_function_instance *fsg_alloc_inst(void)
56947 +{
56948 + struct fsg_opts *opts;
56949 + struct fsg_lun_config config;
56950 int rc;
56951
56952 - fsg = kzalloc(sizeof *fsg, GFP_KERNEL);
56953 + opts = kzalloc(sizeof(*opts), GFP_KERNEL);
56954 + if (!opts)
56955 + return ERR_PTR(-ENOMEM);
56956 + mutex_init(&opts->lock);
56957 + opts->func_inst.free_func_inst = fsg_free_inst;
56958 + opts->common = fsg_common_setup(opts->common);
56959 + if (IS_ERR(opts->common)) {
56960 + rc = PTR_ERR(opts->common);
56961 + goto release_opts;
56962 + }
56963 + rc = fsg_common_set_nluns(opts->common, FSG_MAX_LUNS);
56964 + if (rc)
56965 + goto release_opts;
56966 +
56967 + rc = fsg_common_set_num_buffers(opts->common,
56968 + CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS);
56969 + if (rc)
56970 + goto release_luns;
56971 +
56972 + pr_info(FSG_DRIVER_DESC ", version: " FSG_DRIVER_VERSION "\n");
56973 +
56974 + memset(&config, 0, sizeof(config));
56975 + config.removable = true;
56976 + rc = fsg_common_create_lun(opts->common, &config, 0, "lun.0",
56977 + (const char **)&opts->func_inst.group.cg_item.ci_name);
56978 + opts->lun0.lun = opts->common->luns[0];
56979 + opts->lun0.lun_id = 0;
56980 + config_group_init_type_name(&opts->lun0.group, "lun.0", &fsg_lun_type);
56981 + opts->default_groups[0] = &opts->lun0.group;
56982 + opts->func_inst.group.default_groups = opts->default_groups;
56983 +
56984 + config_group_init_type_name(&opts->func_inst.group, "", &fsg_func_type);
56985 +
56986 + return &opts->func_inst;
56987 +
56988 +release_luns:
56989 + kfree(opts->common->luns);
56990 +release_opts:
56991 + kfree(opts);
56992 + return ERR_PTR(rc);
56993 +}
56994 +
56995 +static void fsg_free(struct usb_function *f)
56996 +{
56997 + struct fsg_dev *fsg;
56998 + struct fsg_opts *opts;
56999 +
57000 + fsg = container_of(f, struct fsg_dev, function);
57001 + opts = container_of(f->fi, struct fsg_opts, func_inst);
57002 +
57003 + mutex_lock(&opts->lock);
57004 + opts->refcnt--;
57005 + mutex_unlock(&opts->lock);
57006 +
57007 + kfree(fsg);
57008 +}
57009 +
57010 +static struct usb_function *fsg_alloc(struct usb_function_instance *fi)
57011 +{
57012 + struct fsg_opts *opts = fsg_opts_from_func_inst(fi);
57013 + struct fsg_common *common = opts->common;
57014 + struct fsg_dev *fsg;
57015 +
57016 + fsg = kzalloc(sizeof(*fsg), GFP_KERNEL);
57017 if (unlikely(!fsg))
57018 - return -ENOMEM;
57019 + return ERR_PTR(-ENOMEM);
57020
57021 - fsg->function.name = FSG_DRIVER_DESC;
57022 - fsg->function.strings = fsg_strings_array;
57023 - fsg->function.bind = fsg_bind;
57024 - fsg->function.unbind = fsg_unbind;
57025 - fsg->function.setup = fsg_setup;
57026 - fsg->function.set_alt = fsg_set_alt;
57027 - fsg->function.disable = fsg_disable;
57028 + mutex_lock(&opts->lock);
57029 + opts->refcnt++;
57030 + mutex_unlock(&opts->lock);
57031 + fsg->function.name = FSG_DRIVER_DESC;
57032 + fsg->function.bind = fsg_bind;
57033 + fsg->function.unbind = fsg_unbind;
57034 + fsg->function.setup = fsg_setup;
57035 + fsg->function.set_alt = fsg_set_alt;
57036 + fsg->function.disable = fsg_disable;
57037 + fsg->function.free_func = fsg_free;
57038
57039 fsg->common = common;
57040 - /*
57041 - * Our caller holds a reference to common structure so we
57042 - * don't have to be worry about it being freed until we return
57043 - * from this function. So instead of incrementing counter now
57044 - * and decrement in error recovery we increment it only when
57045 - * call to usb_add_function() was successful.
57046 - */
57047
57048 - rc = usb_add_function(c, &fsg->function);
57049 - if (unlikely(rc))
57050 - kfree(fsg);
57051 - else
57052 - fsg_common_get(fsg->common);
57053 - return rc;
57054 + return &fsg->function;
57055 }
57056
57057 +DECLARE_USB_FUNCTION_INIT(mass_storage, fsg_alloc_inst, fsg_alloc);
57058 +MODULE_LICENSE("GPL");
57059 +MODULE_AUTHOR("Michal Nazarewicz");
57060
57061 /************************* Module parameters *************************/
57062
57063 -struct fsg_module_parameters {
57064 - char *file[FSG_MAX_LUNS];
57065 - bool ro[FSG_MAX_LUNS];
57066 - bool removable[FSG_MAX_LUNS];
57067 - bool cdrom[FSG_MAX_LUNS];
57068 - bool nofua[FSG_MAX_LUNS];
57069 -
57070 - unsigned int file_count, ro_count, removable_count, cdrom_count;
57071 - unsigned int nofua_count;
57072 - unsigned int luns; /* nluns */
57073 - bool stall; /* can_stall */
57074 -};
57075
57076 -#define _FSG_MODULE_PARAM_ARRAY(prefix, params, name, type, desc) \
57077 - module_param_array_named(prefix ## name, params.name, type, \
57078 - &prefix ## params.name ## _count, \
57079 - S_IRUGO); \
57080 - MODULE_PARM_DESC(prefix ## name, desc)
57081 -
57082 -#define _FSG_MODULE_PARAM(prefix, params, name, type, desc) \
57083 - module_param_named(prefix ## name, params.name, type, \
57084 - S_IRUGO); \
57085 - MODULE_PARM_DESC(prefix ## name, desc)
57086 -
57087 -#define FSG_MODULE_PARAMETERS(prefix, params) \
57088 - _FSG_MODULE_PARAM_ARRAY(prefix, params, file, charp, \
57089 - "names of backing files or devices"); \
57090 - _FSG_MODULE_PARAM_ARRAY(prefix, params, ro, bool, \
57091 - "true to force read-only"); \
57092 - _FSG_MODULE_PARAM_ARRAY(prefix, params, removable, bool, \
57093 - "true to simulate removable media"); \
57094 - _FSG_MODULE_PARAM_ARRAY(prefix, params, cdrom, bool, \
57095 - "true to simulate CD-ROM instead of disk"); \
57096 - _FSG_MODULE_PARAM_ARRAY(prefix, params, nofua, bool, \
57097 - "true to ignore SCSI WRITE(10,12) FUA bit"); \
57098 - _FSG_MODULE_PARAM(prefix, params, luns, uint, \
57099 - "number of LUNs"); \
57100 - _FSG_MODULE_PARAM(prefix, params, stall, bool, \
57101 - "false to prevent bulk stalls")
57102 -
57103 -static void
57104 -fsg_config_from_params(struct fsg_config *cfg,
57105 - const struct fsg_module_parameters *params)
57106 +void fsg_config_from_params(struct fsg_config *cfg,
57107 + const struct fsg_module_parameters *params,
57108 + unsigned int fsg_num_buffers)
57109 {
57110 struct fsg_lun_config *lun;
57111 unsigned i;
57112 @@ -3055,19 +3662,7 @@ fsg_config_from_params(struct fsg_config
57113
57114 /* Finalise */
57115 cfg->can_stall = params->stall;
57116 + cfg->fsg_num_buffers = fsg_num_buffers;
57117 }
57118 +EXPORT_SYMBOL_GPL(fsg_config_from_params);
57119
57120 -static inline struct fsg_common *
57121 -fsg_common_from_params(struct fsg_common *common,
57122 - struct usb_composite_dev *cdev,
57123 - const struct fsg_module_parameters *params)
57124 - __attribute__((unused));
57125 -static inline struct fsg_common *
57126 -fsg_common_from_params(struct fsg_common *common,
57127 - struct usb_composite_dev *cdev,
57128 - const struct fsg_module_parameters *params)
57129 -{
57130 - struct fsg_config cfg;
57131 - fsg_config_from_params(&cfg, params);
57132 - return fsg_common_init(common, cdev, &cfg);
57133 -}
57134 --- /dev/null
57135 +++ b/drivers/usb/gadget/f_mass_storage.h
57136 @@ -0,0 +1,166 @@
57137 +#ifndef USB_F_MASS_STORAGE_H
57138 +#define USB_F_MASS_STORAGE_H
57139 +
57140 +#include <linux/usb/composite.h>
57141 +#include "storage_common.h"
57142 +
57143 +struct fsg_module_parameters {
57144 + char *file[FSG_MAX_LUNS];
57145 + bool ro[FSG_MAX_LUNS];
57146 + bool removable[FSG_MAX_LUNS];
57147 + bool cdrom[FSG_MAX_LUNS];
57148 + bool nofua[FSG_MAX_LUNS];
57149 +
57150 + unsigned int file_count, ro_count, removable_count, cdrom_count;
57151 + unsigned int nofua_count;
57152 + unsigned int luns; /* nluns */
57153 + bool stall; /* can_stall */
57154 +};
57155 +
57156 +#define _FSG_MODULE_PARAM_ARRAY(prefix, params, name, type, desc) \
57157 + module_param_array_named(prefix ## name, params.name, type, \
57158 + &prefix ## params.name ## _count, \
57159 + S_IRUGO); \
57160 + MODULE_PARM_DESC(prefix ## name, desc)
57161 +
57162 +#define _FSG_MODULE_PARAM(prefix, params, name, type, desc) \
57163 + module_param_named(prefix ## name, params.name, type, \
57164 + S_IRUGO); \
57165 + MODULE_PARM_DESC(prefix ## name, desc)
57166 +
57167 +#define __FSG_MODULE_PARAMETERS(prefix, params) \
57168 + _FSG_MODULE_PARAM_ARRAY(prefix, params, file, charp, \
57169 + "names of backing files or devices"); \
57170 + _FSG_MODULE_PARAM_ARRAY(prefix, params, ro, bool, \
57171 + "true to force read-only"); \
57172 + _FSG_MODULE_PARAM_ARRAY(prefix, params, removable, bool, \
57173 + "true to simulate removable media"); \
57174 + _FSG_MODULE_PARAM_ARRAY(prefix, params, cdrom, bool, \
57175 + "true to simulate CD-ROM instead of disk"); \
57176 + _FSG_MODULE_PARAM_ARRAY(prefix, params, nofua, bool, \
57177 + "true to ignore SCSI WRITE(10,12) FUA bit"); \
57178 + _FSG_MODULE_PARAM(prefix, params, luns, uint, \
57179 + "number of LUNs"); \
57180 + _FSG_MODULE_PARAM(prefix, params, stall, bool, \
57181 + "false to prevent bulk stalls")
57182 +
57183 +#ifdef CONFIG_USB_GADGET_DEBUG_FILES
57184 +
57185 +#define FSG_MODULE_PARAMETERS(prefix, params) \
57186 + __FSG_MODULE_PARAMETERS(prefix, params); \
57187 + module_param_named(num_buffers, fsg_num_buffers, uint, S_IRUGO);\
57188 + MODULE_PARM_DESC(num_buffers, "Number of pipeline buffers")
57189 +#else
57190 +
57191 +#define FSG_MODULE_PARAMETERS(prefix, params) \
57192 + __FSG_MODULE_PARAMETERS(prefix, params)
57193 +
57194 +#endif
57195 +
57196 +struct fsg_common;
57197 +
57198 +/* FSF callback functions */
57199 +struct fsg_operations {
57200 + /*
57201 + * Callback function to call when thread exits. If no
57202 + * callback is set or it returns value lower then zero MSF
57203 + * will force eject all LUNs it operates on (including those
57204 + * marked as non-removable or with prevent_medium_removal flag
57205 + * set).
57206 + */
57207 + int (*thread_exits)(struct fsg_common *common);
57208 +};
57209 +
57210 +struct fsg_lun_opts {
57211 + struct config_group group;
57212 + struct fsg_lun *lun;
57213 + int lun_id;
57214 +};
57215 +
57216 +struct fsg_opts {
57217 + struct fsg_common *common;
57218 + struct usb_function_instance func_inst;
57219 + struct fsg_lun_opts lun0;
57220 + struct config_group *default_groups[2];
57221 + bool no_configfs; /* for legacy gadgets */
57222 +
57223 + /*
57224 + * Read/write access to configfs attributes is handled by configfs.
57225 + *
57226 + * This is to protect the data from concurrent access by read/write
57227 + * and create symlink/remove symlink.
57228 + */
57229 + struct mutex lock;
57230 + int refcnt;
57231 +};
57232 +
57233 +struct fsg_lun_config {
57234 + const char *filename;
57235 + char ro;
57236 + char removable;
57237 + char cdrom;
57238 + char nofua;
57239 +};
57240 +
57241 +struct fsg_config {
57242 + unsigned nluns;
57243 + struct fsg_lun_config luns[FSG_MAX_LUNS];
57244 +
57245 + /* Callback functions. */
57246 + const struct fsg_operations *ops;
57247 + /* Gadget's private data. */
57248 + void *private_data;
57249 +
57250 + const char *vendor_name; /* 8 characters or less */
57251 + const char *product_name; /* 16 characters or less */
57252 +
57253 + char can_stall;
57254 + unsigned int fsg_num_buffers;
57255 +};
57256 +
57257 +static inline struct fsg_opts *
57258 +fsg_opts_from_func_inst(const struct usb_function_instance *fi)
57259 +{
57260 + return container_of(fi, struct fsg_opts, func_inst);
57261 +}
57262 +
57263 +void fsg_common_get(struct fsg_common *common);
57264 +
57265 +void fsg_common_put(struct fsg_common *common);
57266 +
57267 +void fsg_common_set_sysfs(struct fsg_common *common, bool sysfs);
57268 +
57269 +int fsg_common_set_num_buffers(struct fsg_common *common, unsigned int n);
57270 +
57271 +void fsg_common_free_buffers(struct fsg_common *common);
57272 +
57273 +int fsg_common_set_cdev(struct fsg_common *common,
57274 + struct usb_composite_dev *cdev, bool can_stall);
57275 +
57276 +void fsg_common_remove_lun(struct fsg_lun *lun, bool sysfs);
57277 +
57278 +void fsg_common_remove_luns(struct fsg_common *common);
57279 +
57280 +void fsg_common_free_luns(struct fsg_common *common);
57281 +
57282 +int fsg_common_set_nluns(struct fsg_common *common, int nluns);
57283 +
57284 +void fsg_common_set_ops(struct fsg_common *common,
57285 + const struct fsg_operations *ops);
57286 +
57287 +int fsg_common_create_lun(struct fsg_common *common, struct fsg_lun_config *cfg,
57288 + unsigned int id, const char *name,
57289 + const char **name_pfx);
57290 +
57291 +int fsg_common_create_luns(struct fsg_common *common, struct fsg_config *cfg);
57292 +
57293 +void fsg_common_set_inquiry_string(struct fsg_common *common, const char *vn,
57294 + const char *pn);
57295 +
57296 +int fsg_common_run_thread(struct fsg_common *common);
57297 +
57298 +void fsg_config_from_params(struct fsg_config *cfg,
57299 + const struct fsg_module_parameters *params,
57300 + unsigned int fsg_num_buffers);
57301 +
57302 +#endif /* USB_F_MASS_STORAGE_H */
57303 --- a/drivers/usb/gadget/g_ffs.c
57304 +++ b/drivers/usb/gadget/g_ffs.c
57305 @@ -76,7 +76,9 @@ struct gfs_ffs_obj {
57306
57307 USB_GADGET_COMPOSITE_OPTIONS();
57308
57309 +#if defined CONFIG_USB_FUNCTIONFS_ETH || defined CONFIG_USB_FUNCTIONFS_RNDIS
57310 USB_ETHERNET_MODULE_PARAMETERS();
57311 +#endif
57312
57313 static struct usb_device_descriptor gfs_dev_desc = {
57314 .bLength = sizeof gfs_dev_desc,
57315 --- a/drivers/usb/gadget/goku_udc.c
57316 +++ b/drivers/usb/gadget/goku_udc.c
57317 @@ -1701,7 +1701,6 @@ static void goku_remove(struct pci_dev *
57318 if (dev->enabled)
57319 pci_disable_device(pdev);
57320
57321 - pci_set_drvdata(pdev, NULL);
57322 dev->regs = NULL;
57323
57324 INFO(dev, "unbind\n");
57325 --- a/drivers/usb/gadget/Kconfig
57326 +++ b/drivers/usb/gadget/Kconfig
57327 @@ -58,6 +58,20 @@ config USB_GADGET_DEBUG
57328 trying to track down. Never enable these messages for a
57329 production build.
57330
57331 +config USB_GADGET_VERBOSE
57332 + bool "Verbose debugging Messages (DEVELOPMENT)"
57333 + depends on USB_GADGET_DEBUG
57334 + help
57335 + Many controller and gadget drivers will print verbose debugging
57336 + messages if you use this option to ask for those messages.
57337 +
57338 + Avoid enabling these messages, even if you're actively
57339 + debugging such a driver. Many drivers will emit so many
57340 + messages that the driver timings are affected, which will
57341 + either create new failure modes or remove the one you're
57342 + trying to track down. Never enable these messages for a
57343 + production build.
57344 +
57345 config USB_GADGET_DEBUG_FILES
57346 boolean "Debugging information files (DEVELOPMENT)"
57347 depends on PROC_FS
57348 @@ -525,6 +539,9 @@ config USB_F_SUBSET
57349 config USB_F_RNDIS
57350 tristate
57351
57352 +config USB_F_MASS_STORAGE
57353 + tristate
57354 +
57355 choice
57356 tristate "USB Gadget Drivers"
57357 default USB_ETH
57358 @@ -662,6 +679,16 @@ config USB_CONFIGFS_PHONET
57359 help
57360 The Phonet protocol implementation for USB device.
57361
57362 +config USB_CONFIGFS_MASS_STORAGE
57363 + boolean "Mass storage"
57364 + depends on USB_CONFIGFS
57365 + select USB_F_MASS_STORAGE
57366 + help
57367 + The Mass Storage Gadget acts as a USB Mass Storage disk drive.
57368 + As its storage repository it can use a regular file or a block
57369 + device (in much the same way as the "loop" device driver),
57370 + specified as a module parameter or sysfs option.
57371 +
57372 config USB_ZERO
57373 tristate "Gadget Zero (DEVELOPMENT)"
57374 select USB_LIBCOMPOSITE
57375 @@ -878,6 +905,7 @@ config USB_MASS_STORAGE
57376 tristate "Mass Storage Gadget"
57377 depends on BLOCK
57378 select USB_LIBCOMPOSITE
57379 + select USB_F_MASS_STORAGE
57380 help
57381 The Mass Storage Gadget acts as a USB Mass Storage disk drive.
57382 As its storage repository it can use a regular file or a block
57383 @@ -1001,6 +1029,7 @@ config USB_G_ACM_MS
57384 select USB_LIBCOMPOSITE
57385 select USB_U_SERIAL
57386 select USB_F_ACM
57387 + select USB_F_MASS_STORAGE
57388 help
57389 This driver provides two functions in one configuration:
57390 a mass storage, and a CDC ACM (serial port) link.
57391 @@ -1015,8 +1044,8 @@ config USB_G_MULTI
57392 select USB_LIBCOMPOSITE
57393 select USB_U_SERIAL
57394 select USB_U_ETHER
57395 - select USB_U_RNDIS
57396 select USB_F_ACM
57397 + select USB_F_MASS_STORAGE
57398 help
57399 The Multifunction Composite Gadget provides Ethernet (RNDIS
57400 and/or CDC Ethernet), mass storage and ACM serial link
57401 @@ -1035,6 +1064,8 @@ config USB_G_MULTI
57402 config USB_G_MULTI_RNDIS
57403 bool "RNDIS + CDC Serial + Storage configuration"
57404 depends on USB_G_MULTI
57405 + select USB_U_RNDIS
57406 + select USB_F_RNDIS
57407 default y
57408 help
57409 This option enables a configuration with RNDIS, CDC Serial and
57410 @@ -1048,6 +1079,7 @@ config USB_G_MULTI_CDC
57411 bool "CDC Ethernet + CDC Serial + Storage configuration"
57412 depends on USB_G_MULTI
57413 default n
57414 + select USB_F_ECM
57415 help
57416 This option enables a configuration with CDC Ethernet (ECM), CDC
57417 Serial and Mass Storage functions available in the Multifunction
57418 --- a/drivers/usb/gadget/Makefile
57419 +++ b/drivers/usb/gadget/Makefile
57420 @@ -1,7 +1,8 @@
57421 #
57422 # USB peripheral controller drivers
57423 #
57424 -ccflags-$(CONFIG_USB_GADGET_DEBUG) := -DDEBUG
57425 +ccflags-$(CONFIG_USB_GADGET_DEBUG) := -DDEBUG
57426 +ccflags-$(CONFIG_USB_GADGET_VERBOSE) += -DVERBOSE_DEBUG
57427
57428 obj-$(CONFIG_USB_GADGET) += udc-core.o
57429 obj-$(CONFIG_USB_LIBCOMPOSITE) += libcomposite.o
57430 @@ -60,6 +61,8 @@ usb_f_ecm_subset-y := f_subset.o
57431 obj-$(CONFIG_USB_F_SUBSET) += usb_f_ecm_subset.o
57432 usb_f_rndis-y := f_rndis.o
57433 obj-$(CONFIG_USB_F_RNDIS) += usb_f_rndis.o
57434 +usb_f_mass_storage-y := f_mass_storage.o storage_common.o
57435 +obj-$(CONFIG_USB_F_MASS_STORAGE)+= usb_f_mass_storage.o
57436
57437 #
57438 # USB gadget drivers
57439 --- a/drivers/usb/gadget/mass_storage.c
57440 +++ b/drivers/usb/gadget/mass_storage.c
57441 @@ -37,16 +37,16 @@
57442 #define DRIVER_DESC "Mass Storage Gadget"
57443 #define DRIVER_VERSION "2009/09/11"
57444
57445 -/*-------------------------------------------------------------------------*/
57446 -
57447 /*
57448 - * kbuild is not very cooperative with respect to linking separately
57449 - * compiled library objects into one module. So for now we won't use
57450 - * separate compilation ... ensuring init/exit sections work to shrink
57451 - * the runtime footprint, and giving us at least some parts of what
57452 - * a "gcc --combine ... part1.c part2.c part3.c ... " build would.
57453 + * Thanks to NetChip Technologies for donating this product ID.
57454 + *
57455 + * DO NOT REUSE THESE IDs with any other driver!! Ever!!
57456 + * Instead: allocate your own, using normal USB-IF procedures.
57457 */
57458 -#include "f_mass_storage.c"
57459 +#define FSG_VENDOR_ID 0x0525 /* NetChip */
57460 +#define FSG_PRODUCT_ID 0xa4a5 /* Linux-USB File-backed Storage Gadget */
57461 +
57462 +#include "f_mass_storage.h"
57463
57464 /*-------------------------------------------------------------------------*/
57465 USB_GADGET_COMPOSITE_OPTIONS();
57466 @@ -97,11 +97,28 @@ static struct usb_gadget_strings *dev_st
57467 NULL,
57468 };
57469
57470 +static struct usb_function_instance *fi_msg;
57471 +static struct usb_function *f_msg;
57472 +
57473 /****************************** Configurations ******************************/
57474
57475 static struct fsg_module_parameters mod_data = {
57476 .stall = 1
57477 };
57478 +#ifdef CONFIG_USB_GADGET_DEBUG_FILES
57479 +
57480 +static unsigned int fsg_num_buffers = CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS;
57481 +
57482 +#else
57483 +
57484 +/*
57485 + * Number of buffers we will use.
57486 + * 2 is usually enough for good buffering pipeline
57487 + */
57488 +#define fsg_num_buffers CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS
57489 +
57490 +#endif /* CONFIG_USB_GADGET_DEBUG_FILES */
57491 +
57492 FSG_MODULE_PARAMETERS(/* no prefix */, mod_data);
57493
57494 static unsigned long msg_registered;
57495 @@ -115,13 +132,7 @@ static int msg_thread_exits(struct fsg_c
57496
57497 static int __init msg_do_config(struct usb_configuration *c)
57498 {
57499 - static const struct fsg_operations ops = {
57500 - .thread_exits = msg_thread_exits,
57501 - };
57502 - static struct fsg_common common;
57503 -
57504 - struct fsg_common *retp;
57505 - struct fsg_config config;
57506 + struct fsg_opts *opts;
57507 int ret;
57508
57509 if (gadget_is_otg(c->cdev->gadget)) {
57510 @@ -129,15 +140,24 @@ static int __init msg_do_config(struct u
57511 c->bmAttributes |= USB_CONFIG_ATT_WAKEUP;
57512 }
57513
57514 - fsg_config_from_params(&config, &mod_data);
57515 - config.ops = &ops;
57516 + opts = fsg_opts_from_func_inst(fi_msg);
57517
57518 - retp = fsg_common_init(&common, c->cdev, &config);
57519 - if (IS_ERR(retp))
57520 - return PTR_ERR(retp);
57521 + f_msg = usb_get_function(fi_msg);
57522 + if (IS_ERR(f_msg))
57523 + return PTR_ERR(f_msg);
57524 +
57525 + ret = fsg_common_run_thread(opts->common);
57526 + if (ret)
57527 + goto put_func;
57528 +
57529 + ret = usb_add_function(c, f_msg);
57530 + if (ret)
57531 + goto put_func;
57532
57533 - ret = fsg_bind_config(c->cdev, c, &common);
57534 - fsg_common_put(&common);
57535 + return 0;
57536 +
57537 +put_func:
57538 + usb_put_function(f_msg);
57539 return ret;
57540 }
57541
57542 @@ -152,23 +172,79 @@ static struct usb_configuration msg_conf
57543
57544 static int __init msg_bind(struct usb_composite_dev *cdev)
57545 {
57546 + static const struct fsg_operations ops = {
57547 + .thread_exits = msg_thread_exits,
57548 + };
57549 + struct fsg_opts *opts;
57550 + struct fsg_config config;
57551 int status;
57552
57553 + fi_msg = usb_get_function_instance("mass_storage");
57554 + if (IS_ERR(fi_msg))
57555 + return PTR_ERR(fi_msg);
57556 +
57557 + fsg_config_from_params(&config, &mod_data, fsg_num_buffers);
57558 + opts = fsg_opts_from_func_inst(fi_msg);
57559 +
57560 + opts->no_configfs = true;
57561 + status = fsg_common_set_num_buffers(opts->common, fsg_num_buffers);
57562 + if (status)
57563 + goto fail;
57564 +
57565 + status = fsg_common_set_nluns(opts->common, config.nluns);
57566 + if (status)
57567 + goto fail_set_nluns;
57568 +
57569 + fsg_common_set_ops(opts->common, &ops);
57570 +
57571 + status = fsg_common_set_cdev(opts->common, cdev, config.can_stall);
57572 + if (status)
57573 + goto fail_set_cdev;
57574 +
57575 + fsg_common_set_sysfs(opts->common, true);
57576 + status = fsg_common_create_luns(opts->common, &config);
57577 + if (status)
57578 + goto fail_set_cdev;
57579 +
57580 + fsg_common_set_inquiry_string(opts->common, config.vendor_name,
57581 + config.product_name);
57582 +
57583 status = usb_string_ids_tab(cdev, strings_dev);
57584 if (status < 0)
57585 - return status;
57586 + goto fail_string_ids;
57587 msg_device_desc.iProduct = strings_dev[USB_GADGET_PRODUCT_IDX].id;
57588
57589 status = usb_add_config(cdev, &msg_config_driver, msg_do_config);
57590 if (status < 0)
57591 - return status;
57592 + goto fail_string_ids;
57593 +
57594 usb_composite_overwrite_options(cdev, &coverwrite);
57595 dev_info(&cdev->gadget->dev,
57596 DRIVER_DESC ", version: " DRIVER_VERSION "\n");
57597 set_bit(0, &msg_registered);
57598 return 0;
57599 +
57600 +fail_string_ids:
57601 + fsg_common_remove_luns(opts->common);
57602 +fail_set_cdev:
57603 + fsg_common_free_luns(opts->common);
57604 +fail_set_nluns:
57605 + fsg_common_free_buffers(opts->common);
57606 +fail:
57607 + usb_put_function_instance(fi_msg);
57608 + return status;
57609 }
57610
57611 +static int msg_unbind(struct usb_composite_dev *cdev)
57612 +{
57613 + if (!IS_ERR(f_msg))
57614 + usb_put_function(f_msg);
57615 +
57616 + if (!IS_ERR(fi_msg))
57617 + usb_put_function_instance(fi_msg);
57618 +
57619 + return 0;
57620 +}
57621
57622 /****************************** Some noise ******************************/
57623
57624 @@ -179,6 +255,7 @@ static __refdata struct usb_composite_dr
57625 .needs_serial = 1,
57626 .strings = dev_strings,
57627 .bind = msg_bind,
57628 + .unbind = msg_unbind,
57629 };
57630
57631 MODULE_DESCRIPTION(DRIVER_DESC);
57632 --- a/drivers/usb/gadget/multi.c
57633 +++ b/drivers/usb/gadget/multi.c
57634 @@ -15,6 +15,7 @@
57635
57636 #include <linux/kernel.h>
57637 #include <linux/module.h>
57638 +#include <linux/netdevice.h>
57639
57640 #include "u_serial.h"
57641 #if defined USB_ETH_RNDIS
57642 @@ -32,22 +33,11 @@ MODULE_AUTHOR("Michal Nazarewicz");
57643 MODULE_LICENSE("GPL");
57644
57645
57646 -/***************************** All the files... *****************************/
57647 +#include "f_mass_storage.h"
57648
57649 -/*
57650 - * kbuild is not very cooperative with respect to linking separately
57651 - * compiled library objects into one module. So for now we won't use
57652 - * separate compilation ... ensuring init/exit sections work to shrink
57653 - * the runtime footprint, and giving us at least some parts of what
57654 - * a "gcc --combine ... part1.c part2.c part3.c ... " build would.
57655 - */
57656 -#include "f_mass_storage.c"
57657 -
57658 -#define USBF_ECM_INCLUDED
57659 -#include "f_ecm.c"
57660 +#include "u_ecm.h"
57661 #ifdef USB_ETH_RNDIS
57662 -# define USB_FRNDIS_INCLUDED
57663 -# include "f_rndis.c"
57664 +# include "u_rndis.h"
57665 # include "rndis.h"
57666 #endif
57667 #include "u_ether.h"
57668 @@ -132,22 +122,36 @@ static struct usb_gadget_strings *dev_st
57669 /****************************** Configurations ******************************/
57670
57671 static struct fsg_module_parameters fsg_mod_data = { .stall = 1 };
57672 -FSG_MODULE_PARAMETERS(/* no prefix */, fsg_mod_data);
57673 +#ifdef CONFIG_USB_GADGET_DEBUG_FILES
57674 +
57675 +static unsigned int fsg_num_buffers = CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS;
57676 +
57677 +#else
57678 +
57679 +/*
57680 + * Number of buffers we will use.
57681 + * 2 is usually enough for good buffering pipeline
57682 + */
57683 +#define fsg_num_buffers CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS
57684
57685 -static struct fsg_common fsg_common;
57686 +#endif /* CONFIG_USB_DEBUG */
57687
57688 -static u8 host_mac[ETH_ALEN];
57689 +FSG_MODULE_PARAMETERS(/* no prefix */, fsg_mod_data);
57690
57691 static struct usb_function_instance *fi_acm;
57692 -static struct eth_dev *the_dev;
57693 +static struct usb_function_instance *fi_msg;
57694
57695 /********** RNDIS **********/
57696
57697 #ifdef USB_ETH_RNDIS
57698 +static struct usb_function_instance *fi_rndis;
57699 static struct usb_function *f_acm_rndis;
57700 +static struct usb_function *f_rndis;
57701 +static struct usb_function *f_msg_rndis;
57702
57703 static __init int rndis_do_config(struct usb_configuration *c)
57704 {
57705 + struct fsg_opts *fsg_opts;
57706 int ret;
57707
57708 if (gadget_is_otg(c->cdev->gadget)) {
57709 @@ -155,27 +159,50 @@ static __init int rndis_do_config(struct
57710 c->bmAttributes |= USB_CONFIG_ATT_WAKEUP;
57711 }
57712
57713 - ret = rndis_bind_config(c, host_mac, the_dev);
57714 + f_rndis = usb_get_function(fi_rndis);
57715 + if (IS_ERR(f_rndis))
57716 + return PTR_ERR(f_rndis);
57717 +
57718 + ret = usb_add_function(c, f_rndis);
57719 if (ret < 0)
57720 - return ret;
57721 + goto err_func_rndis;
57722
57723 f_acm_rndis = usb_get_function(fi_acm);
57724 - if (IS_ERR(f_acm_rndis))
57725 - return PTR_ERR(f_acm_rndis);
57726 + if (IS_ERR(f_acm_rndis)) {
57727 + ret = PTR_ERR(f_acm_rndis);
57728 + goto err_func_acm;
57729 + }
57730
57731 ret = usb_add_function(c, f_acm_rndis);
57732 if (ret)
57733 goto err_conf;
57734
57735 - ret = fsg_bind_config(c->cdev, c, &fsg_common);
57736 - if (ret < 0)
57737 + f_msg_rndis = usb_get_function(fi_msg);
57738 + if (IS_ERR(f_msg_rndis)) {
57739 + ret = PTR_ERR(f_msg_rndis);
57740 goto err_fsg;
57741 + }
57742 +
57743 + fsg_opts = fsg_opts_from_func_inst(fi_msg);
57744 + ret = fsg_common_run_thread(fsg_opts->common);
57745 + if (ret)
57746 + goto err_run;
57747 +
57748 + ret = usb_add_function(c, f_msg_rndis);
57749 + if (ret)
57750 + goto err_run;
57751
57752 return 0;
57753 +err_run:
57754 + usb_put_function(f_msg_rndis);
57755 err_fsg:
57756 usb_remove_function(c, f_acm_rndis);
57757 err_conf:
57758 usb_put_function(f_acm_rndis);
57759 +err_func_acm:
57760 + usb_remove_function(c, f_rndis);
57761 +err_func_rndis:
57762 + usb_put_function(f_rndis);
57763 return ret;
57764 }
57765
57766 @@ -205,10 +232,14 @@ static __ref int rndis_config_register(s
57767 /********** CDC ECM **********/
57768
57769 #ifdef CONFIG_USB_G_MULTI_CDC
57770 +static struct usb_function_instance *fi_ecm;
57771 static struct usb_function *f_acm_multi;
57772 +static struct usb_function *f_ecm;
57773 +static struct usb_function *f_msg_multi;
57774
57775 static __init int cdc_do_config(struct usb_configuration *c)
57776 {
57777 + struct fsg_opts *fsg_opts;
57778 int ret;
57779
57780 if (gadget_is_otg(c->cdev->gadget)) {
57781 @@ -216,28 +247,51 @@ static __init int cdc_do_config(struct u
57782 c->bmAttributes |= USB_CONFIG_ATT_WAKEUP;
57783 }
57784
57785 - ret = ecm_bind_config(c, host_mac, the_dev);
57786 + f_ecm = usb_get_function(fi_ecm);
57787 + if (IS_ERR(f_ecm))
57788 + return PTR_ERR(f_ecm);
57789 +
57790 + ret = usb_add_function(c, f_ecm);
57791 if (ret < 0)
57792 - return ret;
57793 + goto err_func_ecm;
57794
57795 /* implicit port_num is zero */
57796 f_acm_multi = usb_get_function(fi_acm);
57797 - if (IS_ERR(f_acm_multi))
57798 - return PTR_ERR(f_acm_multi);
57799 + if (IS_ERR(f_acm_multi)) {
57800 + ret = PTR_ERR(f_acm_multi);
57801 + goto err_func_acm;
57802 + }
57803
57804 ret = usb_add_function(c, f_acm_multi);
57805 if (ret)
57806 goto err_conf;
57807
57808 - ret = fsg_bind_config(c->cdev, c, &fsg_common);
57809 - if (ret < 0)
57810 + f_msg_multi = usb_get_function(fi_msg);
57811 + if (IS_ERR(f_msg_multi)) {
57812 + ret = PTR_ERR(f_msg_multi);
57813 goto err_fsg;
57814 + }
57815 +
57816 + fsg_opts = fsg_opts_from_func_inst(fi_msg);
57817 + ret = fsg_common_run_thread(fsg_opts->common);
57818 + if (ret)
57819 + goto err_run;
57820 +
57821 + ret = usb_add_function(c, f_msg_multi);
57822 + if (ret)
57823 + goto err_run;
57824
57825 return 0;
57826 +err_run:
57827 + usb_put_function(f_msg_multi);
57828 err_fsg:
57829 usb_remove_function(c, f_acm_multi);
57830 err_conf:
57831 usb_put_function(f_acm_multi);
57832 +err_func_acm:
57833 + usb_remove_function(c, f_ecm);
57834 +err_func_ecm:
57835 + usb_put_function(f_ecm);
57836 return ret;
57837 }
57838
57839 @@ -270,19 +324,67 @@ static __ref int cdc_config_register(str
57840 static int __ref multi_bind(struct usb_composite_dev *cdev)
57841 {
57842 struct usb_gadget *gadget = cdev->gadget;
57843 +#ifdef CONFIG_USB_G_MULTI_CDC
57844 + struct f_ecm_opts *ecm_opts;
57845 +#endif
57846 +#ifdef USB_ETH_RNDIS
57847 + struct f_rndis_opts *rndis_opts;
57848 +#endif
57849 + struct fsg_opts *fsg_opts;
57850 + struct fsg_config config;
57851 int status;
57852
57853 if (!can_support_ecm(cdev->gadget)) {
57854 dev_err(&gadget->dev, "controller '%s' not usable\n",
57855 - gadget->name);
57856 + gadget->name);
57857 return -EINVAL;
57858 }
57859
57860 - /* set up network link layer */
57861 - the_dev = gether_setup(cdev->gadget, dev_addr, host_addr, host_mac,
57862 - qmult);
57863 - if (IS_ERR(the_dev))
57864 - return PTR_ERR(the_dev);
57865 +#ifdef CONFIG_USB_G_MULTI_CDC
57866 + fi_ecm = usb_get_function_instance("ecm");
57867 + if (IS_ERR(fi_ecm))
57868 + return PTR_ERR(fi_ecm);
57869 +
57870 + ecm_opts = container_of(fi_ecm, struct f_ecm_opts, func_inst);
57871 +
57872 + gether_set_qmult(ecm_opts->net, qmult);
57873 + if (!gether_set_host_addr(ecm_opts->net, host_addr))
57874 + pr_info("using host ethernet address: %s", host_addr);
57875 + if (!gether_set_dev_addr(ecm_opts->net, dev_addr))
57876 + pr_info("using self ethernet address: %s", dev_addr);
57877 +#endif
57878 +
57879 +#ifdef USB_ETH_RNDIS
57880 + fi_rndis = usb_get_function_instance("rndis");
57881 + if (IS_ERR(fi_rndis)) {
57882 + status = PTR_ERR(fi_rndis);
57883 + goto fail;
57884 + }
57885 +
57886 + rndis_opts = container_of(fi_rndis, struct f_rndis_opts, func_inst);
57887 +
57888 + gether_set_qmult(rndis_opts->net, qmult);
57889 + if (!gether_set_host_addr(rndis_opts->net, host_addr))
57890 + pr_info("using host ethernet address: %s", host_addr);
57891 + if (!gether_set_dev_addr(rndis_opts->net, dev_addr))
57892 + pr_info("using self ethernet address: %s", dev_addr);
57893 +#endif
57894 +
57895 +#if (defined CONFIG_USB_G_MULTI_CDC && defined USB_ETH_RNDIS)
57896 + /*
57897 + * If both ecm and rndis are selected then:
57898 + * 1) rndis borrows the net interface from ecm
57899 + * 2) since the interface is shared it must not be bound
57900 + * twice - in ecm's _and_ rndis' binds, so do it here.
57901 + */
57902 + gether_set_gadget(ecm_opts->net, cdev->gadget);
57903 + status = gether_register_netdev(ecm_opts->net);
57904 + if (status)
57905 + goto fail0;
57906 +
57907 + rndis_borrow_net(fi_rndis, ecm_opts->net);
57908 + ecm_opts->bound = true;
57909 +#endif
57910
57911 /* set up serial link layer */
57912 fi_acm = usb_get_function_instance("acm");
57913 @@ -292,57 +394,102 @@ static int __ref multi_bind(struct usb_c
57914 }
57915
57916 /* set up mass storage function */
57917 - {
57918 - void *retp;
57919 - retp = fsg_common_from_params(&fsg_common, cdev, &fsg_mod_data);
57920 - if (IS_ERR(retp)) {
57921 - status = PTR_ERR(retp);
57922 - goto fail1;
57923 - }
57924 + fi_msg = usb_get_function_instance("mass_storage");
57925 + if (IS_ERR(fi_msg)) {
57926 + status = PTR_ERR(fi_msg);
57927 + goto fail1;
57928 }
57929 + fsg_config_from_params(&config, &fsg_mod_data, fsg_num_buffers);
57930 + fsg_opts = fsg_opts_from_func_inst(fi_msg);
57931 +
57932 + fsg_opts->no_configfs = true;
57933 + status = fsg_common_set_num_buffers(fsg_opts->common, fsg_num_buffers);
57934 + if (status)
57935 + goto fail2;
57936 +
57937 + status = fsg_common_set_nluns(fsg_opts->common, config.nluns);
57938 + if (status)
57939 + goto fail_set_nluns;
57940 +
57941 + status = fsg_common_set_cdev(fsg_opts->common, cdev, config.can_stall);
57942 + if (status)
57943 + goto fail_set_cdev;
57944 +
57945 + fsg_common_set_sysfs(fsg_opts->common, true);
57946 + status = fsg_common_create_luns(fsg_opts->common, &config);
57947 + if (status)
57948 + goto fail_set_cdev;
57949 +
57950 + fsg_common_set_inquiry_string(fsg_opts->common, config.vendor_name,
57951 + config.product_name);
57952
57953 /* allocate string IDs */
57954 status = usb_string_ids_tab(cdev, strings_dev);
57955 if (unlikely(status < 0))
57956 - goto fail2;
57957 + goto fail_string_ids;
57958 device_desc.iProduct = strings_dev[USB_GADGET_PRODUCT_IDX].id;
57959
57960 /* register configurations */
57961 status = rndis_config_register(cdev);
57962 if (unlikely(status < 0))
57963 - goto fail2;
57964 + goto fail_string_ids;
57965
57966 status = cdc_config_register(cdev);
57967 if (unlikely(status < 0))
57968 - goto fail2;
57969 + goto fail_string_ids;
57970 usb_composite_overwrite_options(cdev, &coverwrite);
57971
57972 /* we're done */
57973 dev_info(&gadget->dev, DRIVER_DESC "\n");
57974 - fsg_common_put(&fsg_common);
57975 return 0;
57976
57977
57978 /* error recovery */
57979 +fail_string_ids:
57980 + fsg_common_remove_luns(fsg_opts->common);
57981 +fail_set_cdev:
57982 + fsg_common_free_luns(fsg_opts->common);
57983 +fail_set_nluns:
57984 + fsg_common_free_buffers(fsg_opts->common);
57985 fail2:
57986 - fsg_common_put(&fsg_common);
57987 + usb_put_function_instance(fi_msg);
57988 fail1:
57989 usb_put_function_instance(fi_acm);
57990 fail0:
57991 - gether_cleanup(the_dev);
57992 +#ifdef USB_ETH_RNDIS
57993 + usb_put_function_instance(fi_rndis);
57994 +fail:
57995 +#endif
57996 +#ifdef CONFIG_USB_G_MULTI_CDC
57997 + usb_put_function_instance(fi_ecm);
57998 +#endif
57999 return status;
58000 }
58001
58002 static int __exit multi_unbind(struct usb_composite_dev *cdev)
58003 {
58004 #ifdef CONFIG_USB_G_MULTI_CDC
58005 + usb_put_function(f_msg_multi);
58006 +#endif
58007 +#ifdef USB_ETH_RNDIS
58008 + usb_put_function(f_msg_rndis);
58009 +#endif
58010 + usb_put_function_instance(fi_msg);
58011 +#ifdef CONFIG_USB_G_MULTI_CDC
58012 usb_put_function(f_acm_multi);
58013 #endif
58014 #ifdef USB_ETH_RNDIS
58015 usb_put_function(f_acm_rndis);
58016 #endif
58017 usb_put_function_instance(fi_acm);
58018 - gether_cleanup(the_dev);
58019 +#ifdef USB_ETH_RNDIS
58020 + usb_put_function(f_rndis);
58021 + usb_put_function_instance(fi_rndis);
58022 +#endif
58023 +#ifdef CONFIG_USB_G_MULTI_CDC
58024 + usb_put_function(f_ecm);
58025 + usb_put_function_instance(fi_ecm);
58026 +#endif
58027 return 0;
58028 }
58029
58030 --- a/drivers/usb/gadget/mv_u3d_core.c
58031 +++ b/drivers/usb/gadget/mv_u3d_core.c
58032 @@ -310,6 +310,7 @@ static struct mv_u3d_trb *mv_u3d_build_t
58033 */
58034 trb_hw = dma_pool_alloc(u3d->trb_pool, GFP_ATOMIC, dma);
58035 if (!trb_hw) {
58036 + kfree(trb);
58037 dev_err(u3d->dev,
58038 "%s, dma_pool_alloc fail\n", __func__);
58039 return NULL;
58040 @@ -454,6 +455,7 @@ static int mv_u3d_req_to_trb(struct mv_u
58041
58042 trb_hw = kcalloc(trb_num, sizeof(*trb_hw), GFP_ATOMIC);
58043 if (!trb_hw) {
58044 + kfree(trb);
58045 dev_err(u3d->dev,
58046 "%s, trb_hw alloc fail\n", __func__);
58047 return -ENOMEM;
58048 @@ -1936,7 +1938,7 @@ static int mv_u3d_probe(struct platform_
58049 }
58050 u3d->irq = r->start;
58051 if (request_irq(u3d->irq, mv_u3d_irq,
58052 - IRQF_DISABLED | IRQF_SHARED, driver_name, u3d)) {
58053 + IRQF_SHARED, driver_name, u3d)) {
58054 u3d->irq = 0;
58055 dev_err(&dev->dev, "Request irq %d for u3d failed\n",
58056 u3d->irq);
58057 --- a/drivers/usb/gadget/net2280.c
58058 +++ b/drivers/usb/gadget/net2280.c
58059 @@ -2680,7 +2680,6 @@ static void net2280_remove (struct pci_d
58060 if (dev->enabled)
58061 pci_disable_device (pdev);
58062 device_remove_file (&pdev->dev, &dev_attr_registers);
58063 - pci_set_drvdata (pdev, NULL);
58064
58065 INFO (dev, "unbind\n");
58066 }
58067 --- a/drivers/usb/gadget/pch_udc.c
58068 +++ b/drivers/usb/gadget/pch_udc.c
58069 @@ -3080,7 +3080,6 @@ static void pch_udc_remove(struct pci_de
58070 if (dev->active)
58071 pci_disable_device(pdev);
58072 kfree(dev);
58073 - pci_set_drvdata(pdev, NULL);
58074 }
58075
58076 #ifdef CONFIG_PM
58077 --- a/drivers/usb/gadget/s3c-hsotg.c
58078 +++ b/drivers/usb/gadget/s3c-hsotg.c
58079 @@ -83,9 +83,12 @@ struct s3c_hsotg_req;
58080 * @dir_in: Set to true if this endpoint is of the IN direction, which
58081 * means that it is sending data to the Host.
58082 * @index: The index for the endpoint registers.
58083 + * @mc: Multi Count - number of transactions per microframe
58084 + * @interval - Interval for periodic endpoints
58085 * @name: The name array passed to the USB core.
58086 * @halted: Set if the endpoint has been halted.
58087 * @periodic: Set if this is a periodic ep, such as Interrupt
58088 + * @isochronous: Set if this is a isochronous ep
58089 * @sent_zlp: Set if we've sent a zero-length packet.
58090 * @total_data: The total number of data bytes done.
58091 * @fifo_size: The size of the FIFO (for periodic IN endpoints)
58092 @@ -121,9 +124,12 @@ struct s3c_hsotg_ep {
58093
58094 unsigned char dir_in;
58095 unsigned char index;
58096 + unsigned char mc;
58097 + unsigned char interval;
58098
58099 unsigned int halted:1;
58100 unsigned int periodic:1;
58101 + unsigned int isochronous:1;
58102 unsigned int sent_zlp:1;
58103
58104 char name[10];
58105 @@ -468,6 +474,7 @@ static int s3c_hsotg_write_fifo(struct s
58106 void *data;
58107 int can_write;
58108 int pkt_round;
58109 + int max_transfer;
58110
58111 to_write -= (buf_pos - hs_ep->last_load);
58112
58113 @@ -535,8 +542,10 @@ static int s3c_hsotg_write_fifo(struct s
58114 can_write *= 4; /* fifo size is in 32bit quantities. */
58115 }
58116
58117 - dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, mps %d\n",
58118 - __func__, gnptxsts, can_write, to_write, hs_ep->ep.maxpacket);
58119 + max_transfer = hs_ep->ep.maxpacket * hs_ep->mc;
58120 +
58121 + dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, max_transfer %d\n",
58122 + __func__, gnptxsts, can_write, to_write, max_transfer);
58123
58124 /*
58125 * limit to 512 bytes of data, it seems at least on the non-periodic
58126 @@ -551,19 +560,21 @@ static int s3c_hsotg_write_fifo(struct s
58127 * the transfer to return that it did not run out of fifo space
58128 * doing it.
58129 */
58130 - if (to_write > hs_ep->ep.maxpacket) {
58131 - to_write = hs_ep->ep.maxpacket;
58132 + if (to_write > max_transfer) {
58133 + to_write = max_transfer;
58134
58135 - s3c_hsotg_en_gsint(hsotg,
58136 - periodic ? GINTSTS_PTxFEmp :
58137 - GINTSTS_NPTxFEmp);
58138 + /* it's needed only when we do not use dedicated fifos */
58139 + if (!hsotg->dedicated_fifos)
58140 + s3c_hsotg_en_gsint(hsotg,
58141 + periodic ? GINTSTS_PTxFEmp :
58142 + GINTSTS_NPTxFEmp);
58143 }
58144
58145 /* see if we can write data */
58146
58147 if (to_write > can_write) {
58148 to_write = can_write;
58149 - pkt_round = to_write % hs_ep->ep.maxpacket;
58150 + pkt_round = to_write % max_transfer;
58151
58152 /*
58153 * Round the write down to an
58154 @@ -581,9 +592,11 @@ static int s3c_hsotg_write_fifo(struct s
58155 * is more room left.
58156 */
58157
58158 - s3c_hsotg_en_gsint(hsotg,
58159 - periodic ? GINTSTS_PTxFEmp :
58160 - GINTSTS_NPTxFEmp);
58161 + /* it's needed only when we do not use dedicated fifos */
58162 + if (!hsotg->dedicated_fifos)
58163 + s3c_hsotg_en_gsint(hsotg,
58164 + periodic ? GINTSTS_PTxFEmp :
58165 + GINTSTS_NPTxFEmp);
58166 }
58167
58168 dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n",
58169 @@ -727,8 +740,16 @@ static void s3c_hsotg_start_req(struct s
58170 else
58171 packets = 1; /* send one packet if length is zero. */
58172
58173 + if (hs_ep->isochronous && length > (hs_ep->mc * hs_ep->ep.maxpacket)) {
58174 + dev_err(hsotg->dev, "req length > maxpacket*mc\n");
58175 + return;
58176 + }
58177 +
58178 if (dir_in && index != 0)
58179 - epsize = DxEPTSIZ_MC(1);
58180 + if (hs_ep->isochronous)
58181 + epsize = DxEPTSIZ_MC(packets);
58182 + else
58183 + epsize = DxEPTSIZ_MC(1);
58184 else
58185 epsize = 0;
58186
58187 @@ -820,6 +841,9 @@ static void s3c_hsotg_start_req(struct s
58188
58189 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n",
58190 __func__, readl(hsotg->regs + epctrl_reg));
58191 +
58192 + /* enable ep interrupts */
58193 + s3c_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 1);
58194 }
58195
58196 /**
58197 @@ -1091,6 +1115,7 @@ static int s3c_hsotg_process_req_feature
58198 bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE);
58199 struct s3c_hsotg_ep *ep;
58200 int ret;
58201 + bool halted;
58202
58203 dev_dbg(hsotg->dev, "%s: %s_FEATURE\n",
58204 __func__, set ? "SET" : "CLEAR");
58205 @@ -1105,6 +1130,8 @@ static int s3c_hsotg_process_req_feature
58206
58207 switch (le16_to_cpu(ctrl->wValue)) {
58208 case USB_ENDPOINT_HALT:
58209 + halted = ep->halted;
58210 +
58211 s3c_hsotg_ep_sethalt(&ep->ep, set);
58212
58213 ret = s3c_hsotg_send_reply(hsotg, ep0, NULL, 0);
58214 @@ -1114,7 +1141,12 @@ static int s3c_hsotg_process_req_feature
58215 return ret;
58216 }
58217
58218 - if (!set) {
58219 + /*
58220 + * we have to complete all requests for ep if it was
58221 + * halted, and the halt was cleared by CLEAR_FEATURE
58222 + */
58223 +
58224 + if (!set && halted) {
58225 /*
58226 * If we have request in progress,
58227 * then complete it
58228 @@ -1147,6 +1179,8 @@ static int s3c_hsotg_process_req_feature
58229 return 1;
58230 }
58231
58232 +static void s3c_hsotg_enqueue_setup(struct s3c_hsotg *hsotg);
58233 +
58234 /**
58235 * s3c_hsotg_process_control - process a control request
58236 * @hsotg: The device state
58237 @@ -1246,11 +1280,15 @@ static void s3c_hsotg_process_control(st
58238 * don't believe we need to anything more to get the EP
58239 * to reply with a STALL packet
58240 */
58241 +
58242 + /*
58243 + * complete won't be called, so we enqueue
58244 + * setup request here
58245 + */
58246 + s3c_hsotg_enqueue_setup(hsotg);
58247 }
58248 }
58249
58250 -static void s3c_hsotg_enqueue_setup(struct s3c_hsotg *hsotg);
58251 -
58252 /**
58253 * s3c_hsotg_complete_setup - completion of a setup transfer
58254 * @ep: The endpoint the request was on.
58255 @@ -1698,6 +1736,7 @@ static void s3c_hsotg_set_ep_maxpacket(s
58256 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[ep];
58257 void __iomem *regs = hsotg->regs;
58258 u32 mpsval;
58259 + u32 mcval;
58260 u32 reg;
58261
58262 if (ep == 0) {
58263 @@ -1705,15 +1744,19 @@ static void s3c_hsotg_set_ep_maxpacket(s
58264 mpsval = s3c_hsotg_ep0_mps(mps);
58265 if (mpsval > 3)
58266 goto bad_mps;
58267 + hs_ep->ep.maxpacket = mps;
58268 + hs_ep->mc = 1;
58269 } else {
58270 - if (mps >= DxEPCTL_MPS_LIMIT+1)
58271 + mpsval = mps & DxEPCTL_MPS_MASK;
58272 + if (mpsval > 1024)
58273 goto bad_mps;
58274 -
58275 - mpsval = mps;
58276 + mcval = ((mps >> 11) & 0x3) + 1;
58277 + hs_ep->mc = mcval;
58278 + if (mcval > 3)
58279 + goto bad_mps;
58280 + hs_ep->ep.maxpacket = mpsval;
58281 }
58282
58283 - hs_ep->ep.maxpacket = mps;
58284 -
58285 /*
58286 * update both the in and out endpoint controldir_ registers, even
58287 * if one of the directions may not be in use.
58288 @@ -1782,8 +1825,16 @@ static int s3c_hsotg_trytx(struct s3c_hs
58289 {
58290 struct s3c_hsotg_req *hs_req = hs_ep->req;
58291
58292 - if (!hs_ep->dir_in || !hs_req)
58293 + if (!hs_ep->dir_in || !hs_req) {
58294 + /**
58295 + * if request is not enqueued, we disable interrupts
58296 + * for endpoints, excepting ep0
58297 + */
58298 + if (hs_ep->index != 0)
58299 + s3c_hsotg_ctrl_epint(hsotg, hs_ep->index,
58300 + hs_ep->dir_in, 0);
58301 return 0;
58302 + }
58303
58304 if (hs_req->req.actual < hs_req->req.length) {
58305 dev_dbg(hsotg->dev, "trying to write more for ep%d\n",
58306 @@ -1887,8 +1938,10 @@ static void s3c_hsotg_epint(struct s3c_h
58307 u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx);
58308 u32 epsiz_reg = dir_in ? DIEPTSIZ(idx) : DOEPTSIZ(idx);
58309 u32 ints;
58310 + u32 ctrl;
58311
58312 ints = readl(hsotg->regs + epint_reg);
58313 + ctrl = readl(hsotg->regs + epctl_reg);
58314
58315 /* Clear endpoint interrupts */
58316 writel(ints, hsotg->regs + epint_reg);
58317 @@ -1897,6 +1950,14 @@ static void s3c_hsotg_epint(struct s3c_h
58318 __func__, idx, dir_in ? "in" : "out", ints);
58319
58320 if (ints & DxEPINT_XferCompl) {
58321 + if (hs_ep->isochronous && hs_ep->interval == 1) {
58322 + if (ctrl & DxEPCTL_EOFrNum)
58323 + ctrl |= DxEPCTL_SetEvenFr;
58324 + else
58325 + ctrl |= DxEPCTL_SetOddFr;
58326 + writel(ctrl, hsotg->regs + epctl_reg);
58327 + }
58328 +
58329 dev_dbg(hsotg->dev,
58330 "%s: XferCompl: DxEPCTL=0x%08x, DxEPTSIZ=%08x\n",
58331 __func__, readl(hsotg->regs + epctl_reg),
58332 @@ -1963,7 +2024,7 @@ static void s3c_hsotg_epint(struct s3c_h
58333 if (ints & DxEPINT_Back2BackSetup)
58334 dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__);
58335
58336 - if (dir_in) {
58337 + if (dir_in && !hs_ep->isochronous) {
58338 /* not sure if this is important, but we'll clear it anyway */
58339 if (ints & DIEPMSK_INTknTXFEmpMsk) {
58340 dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n",
58341 @@ -2092,12 +2153,14 @@ static void kill_all_requests(struct s3c
58342 }
58343
58344 #define call_gadget(_hs, _entry) \
58345 +do { \
58346 if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \
58347 (_hs)->driver && (_hs)->driver->_entry) { \
58348 spin_unlock(&_hs->lock); \
58349 (_hs)->driver->_entry(&(_hs)->gadget); \
58350 spin_lock(&_hs->lock); \
58351 - }
58352 + } \
58353 +} while (0)
58354
58355 /**
58356 * s3c_hsotg_disconnect - disconnect service
58357 @@ -2241,15 +2304,19 @@ static void s3c_hsotg_core_init(struct s
58358 GAHBCFG_HBstLen_Incr4,
58359 hsotg->regs + GAHBCFG);
58360 else
58361 - writel(GAHBCFG_GlblIntrEn, hsotg->regs + GAHBCFG);
58362 + writel(((hsotg->dedicated_fifos) ? (GAHBCFG_NPTxFEmpLvl |
58363 + GAHBCFG_PTxFEmpLvl) : 0) |
58364 + GAHBCFG_GlblIntrEn,
58365 + hsotg->regs + GAHBCFG);
58366
58367 /*
58368 - * Enabling INTknTXFEmpMsk here seems to be a big mistake, we end
58369 - * up being flooded with interrupts if the host is polling the
58370 - * endpoint to try and read data.
58371 + * If INTknTXFEmpMsk is enabled, it's important to disable ep interrupts
58372 + * when we have no data to transfer. Otherwise we get being flooded by
58373 + * interrupts.
58374 */
58375
58376 - writel(((hsotg->dedicated_fifos) ? DIEPMSK_TxFIFOEmpty : 0) |
58377 + writel(((hsotg->dedicated_fifos) ? DIEPMSK_TxFIFOEmpty |
58378 + DIEPMSK_INTknTXFEmpMsk : 0) |
58379 DIEPMSK_EPDisbldMsk | DIEPMSK_XferComplMsk |
58380 DIEPMSK_TimeOUTMsk | DIEPMSK_AHBErrMsk |
58381 DIEPMSK_INTknEPMisMsk,
58382 @@ -2378,10 +2445,14 @@ irq_retry:
58383
58384 if (gintsts & (GINTSTS_OEPInt | GINTSTS_IEPInt)) {
58385 u32 daint = readl(hsotg->regs + DAINT);
58386 - u32 daint_out = daint >> DAINT_OutEP_SHIFT;
58387 - u32 daint_in = daint & ~(daint_out << DAINT_OutEP_SHIFT);
58388 + u32 daintmsk = readl(hsotg->regs + DAINTMSK);
58389 + u32 daint_out, daint_in;
58390 int ep;
58391
58392 + daint &= daintmsk;
58393 + daint_out = daint >> DAINT_OutEP_SHIFT;
58394 + daint_in = daint & ~(daint_out << DAINT_OutEP_SHIFT);
58395 +
58396 dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint);
58397
58398 for (ep = 0; ep < 15 && daint_out; ep++, daint_out >>= 1) {
58399 @@ -2577,16 +2648,25 @@ static int s3c_hsotg_ep_enable(struct us
58400 epctrl |= DxEPCTL_SNAK;
58401
58402 /* update the endpoint state */
58403 - hs_ep->ep.maxpacket = mps;
58404 + s3c_hsotg_set_ep_maxpacket(hsotg, hs_ep->index, mps);
58405
58406 /* default, set to non-periodic */
58407 + hs_ep->isochronous = 0;
58408 hs_ep->periodic = 0;
58409 + hs_ep->halted = 0;
58410 + hs_ep->interval = desc->bInterval;
58411 +
58412 + if (hs_ep->interval > 1 && hs_ep->mc > 1)
58413 + dev_err(hsotg->dev, "MC > 1 when interval is not 1\n");
58414
58415 switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
58416 case USB_ENDPOINT_XFER_ISOC:
58417 - dev_err(hsotg->dev, "no current ISOC support\n");
58418 - ret = -EINVAL;
58419 - goto out;
58420 + epctrl |= DxEPCTL_EPType_Iso;
58421 + epctrl |= DxEPCTL_SetEvenFr;
58422 + hs_ep->isochronous = 1;
58423 + if (dir_in)
58424 + hs_ep->periodic = 1;
58425 + break;
58426
58427 case USB_ENDPOINT_XFER_BULK:
58428 epctrl |= DxEPCTL_EPType_Bulk;
58429 @@ -2634,7 +2714,6 @@ static int s3c_hsotg_ep_enable(struct us
58430 /* enable the endpoint interrupt */
58431 s3c_hsotg_ctrl_epint(hsotg, index, dir_in, 1);
58432
58433 -out:
58434 spin_unlock_irqrestore(&hsotg->lock, flags);
58435 return ret;
58436 }
58437 @@ -2776,6 +2855,8 @@ static int s3c_hsotg_ep_sethalt(struct u
58438
58439 writel(epctl, hs->regs + epreg);
58440
58441 + hs_ep->halted = value;
58442 +
58443 return 0;
58444 }
58445
58446 @@ -2903,7 +2984,7 @@ static int s3c_hsotg_udc_start(struct us
58447 int ret;
58448
58449 if (!hsotg) {
58450 - printk(KERN_ERR "%s: called with no device\n", __func__);
58451 + pr_err("%s: called with no device\n", __func__);
58452 return -ENODEV;
58453 }
58454
58455 @@ -3066,7 +3147,7 @@ static void s3c_hsotg_initep(struct s3c_
58456
58457 hs_ep->parent = hsotg;
58458 hs_ep->ep.name = hs_ep->name;
58459 - hs_ep->ep.maxpacket = epnum ? 512 : EP0_MPS_LIMIT;
58460 + hs_ep->ep.maxpacket = epnum ? 1024 : EP0_MPS_LIMIT;
58461 hs_ep->ep.ops = &s3c_hsotg_ep_ops;
58462
58463 /*
58464 @@ -3200,7 +3281,7 @@ static int state_show(struct seq_file *s
58465 readl(regs + GNPTXSTS),
58466 readl(regs + GRXSTSR));
58467
58468 - seq_printf(seq, "\nEndpoint status:\n");
58469 + seq_puts(seq, "\nEndpoint status:\n");
58470
58471 for (idx = 0; idx < 15; idx++) {
58472 u32 in, out;
58473 @@ -3217,7 +3298,7 @@ static int state_show(struct seq_file *s
58474 seq_printf(seq, ", DIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x",
58475 in, out);
58476
58477 - seq_printf(seq, "\n");
58478 + seq_puts(seq, "\n");
58479 }
58480
58481 return 0;
58482 @@ -3251,7 +3332,7 @@ static int fifo_show(struct seq_file *se
58483 u32 val;
58484 int idx;
58485
58486 - seq_printf(seq, "Non-periodic FIFOs:\n");
58487 + seq_puts(seq, "Non-periodic FIFOs:\n");
58488 seq_printf(seq, "RXFIFO: Size %d\n", readl(regs + GRXFSIZ));
58489
58490 val = readl(regs + GNPTXFSIZ);
58491 @@ -3259,7 +3340,7 @@ static int fifo_show(struct seq_file *se
58492 val >> GNPTXFSIZ_NPTxFDep_SHIFT,
58493 val & GNPTXFSIZ_NPTxFStAddr_MASK);
58494
58495 - seq_printf(seq, "\nPeriodic TXFIFOs:\n");
58496 + seq_puts(seq, "\nPeriodic TXFIFOs:\n");
58497
58498 for (idx = 1; idx <= 15; idx++) {
58499 val = readl(regs + DPTXFSIZn(idx));
58500 @@ -3330,7 +3411,7 @@ static int ep_show(struct seq_file *seq,
58501 readl(regs + DIEPTSIZ(index)),
58502 readl(regs + DOEPTSIZ(index)));
58503
58504 - seq_printf(seq, "\n");
58505 + seq_puts(seq, "\n");
58506 seq_printf(seq, "mps %d\n", ep->ep.maxpacket);
58507 seq_printf(seq, "total_data=%ld\n", ep->total_data);
58508
58509 @@ -3341,7 +3422,7 @@ static int ep_show(struct seq_file *seq,
58510
58511 list_for_each_entry(req, &ep->queue, queue) {
58512 if (--show_limit < 0) {
58513 - seq_printf(seq, "not showing more requests...\n");
58514 + seq_puts(seq, "not showing more requests...\n");
58515 break;
58516 }
58517
58518 --- a/drivers/usb/gadget/storage_common.c
58519 +++ b/drivers/usb/gadget/storage_common.c
58520 @@ -23,242 +23,17 @@
58521 * The valid range of num_buffers is: num >= 2 && num <= 4.
58522 */
58523
58524 +#include <linux/module.h>
58525 +#include <linux/blkdev.h>
58526 +#include <linux/file.h>
58527 +#include <linux/fs.h>
58528 +#include <linux/usb/composite.h>
58529
58530 -#include <linux/usb/storage.h>
58531 -#include <scsi/scsi.h>
58532 -#include <asm/unaligned.h>
58533 -
58534 -
58535 -/*
58536 - * Thanks to NetChip Technologies for donating this product ID.
58537 - *
58538 - * DO NOT REUSE THESE IDs with any other driver!! Ever!!
58539 - * Instead: allocate your own, using normal USB-IF procedures.
58540 - */
58541 -#define FSG_VENDOR_ID 0x0525 /* NetChip */
58542 -#define FSG_PRODUCT_ID 0xa4a5 /* Linux-USB File-backed Storage Gadget */
58543 -
58544 -
58545 -/*-------------------------------------------------------------------------*/
58546 -
58547 -
58548 -#ifndef DEBUG
58549 -#undef VERBOSE_DEBUG
58550 -#undef DUMP_MSGS
58551 -#endif /* !DEBUG */
58552 -
58553 -#ifdef VERBOSE_DEBUG
58554 -#define VLDBG LDBG
58555 -#else
58556 -#define VLDBG(lun, fmt, args...) do { } while (0)
58557 -#endif /* VERBOSE_DEBUG */
58558 -
58559 -#define LDBG(lun, fmt, args...) dev_dbg (&(lun)->dev, fmt, ## args)
58560 -#define LERROR(lun, fmt, args...) dev_err (&(lun)->dev, fmt, ## args)
58561 -#define LWARN(lun, fmt, args...) dev_warn(&(lun)->dev, fmt, ## args)
58562 -#define LINFO(lun, fmt, args...) dev_info(&(lun)->dev, fmt, ## args)
58563 -
58564 -
58565 -#ifdef DUMP_MSGS
58566 -
58567 -# define dump_msg(fsg, /* const char * */ label, \
58568 - /* const u8 * */ buf, /* unsigned */ length) do { \
58569 - if (length < 512) { \
58570 - DBG(fsg, "%s, length %u:\n", label, length); \
58571 - print_hex_dump(KERN_DEBUG, "", DUMP_PREFIX_OFFSET, \
58572 - 16, 1, buf, length, 0); \
58573 - } \
58574 -} while (0)
58575 -
58576 -# define dump_cdb(fsg) do { } while (0)
58577 -
58578 -#else
58579 -
58580 -# define dump_msg(fsg, /* const char * */ label, \
58581 - /* const u8 * */ buf, /* unsigned */ length) do { } while (0)
58582 -
58583 -# ifdef VERBOSE_DEBUG
58584 -
58585 -# define dump_cdb(fsg) \
58586 - print_hex_dump(KERN_DEBUG, "SCSI CDB: ", DUMP_PREFIX_NONE, \
58587 - 16, 1, (fsg)->cmnd, (fsg)->cmnd_size, 0) \
58588 -
58589 -# else
58590 -
58591 -# define dump_cdb(fsg) do { } while (0)
58592 -
58593 -# endif /* VERBOSE_DEBUG */
58594 -
58595 -#endif /* DUMP_MSGS */
58596 -
58597 -/*-------------------------------------------------------------------------*/
58598 -
58599 -/* Length of a SCSI Command Data Block */
58600 -#define MAX_COMMAND_SIZE 16
58601 -
58602 -/* SCSI Sense Key/Additional Sense Code/ASC Qualifier values */
58603 -#define SS_NO_SENSE 0
58604 -#define SS_COMMUNICATION_FAILURE 0x040800
58605 -#define SS_INVALID_COMMAND 0x052000
58606 -#define SS_INVALID_FIELD_IN_CDB 0x052400
58607 -#define SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE 0x052100
58608 -#define SS_LOGICAL_UNIT_NOT_SUPPORTED 0x052500
58609 -#define SS_MEDIUM_NOT_PRESENT 0x023a00
58610 -#define SS_MEDIUM_REMOVAL_PREVENTED 0x055302
58611 -#define SS_NOT_READY_TO_READY_TRANSITION 0x062800
58612 -#define SS_RESET_OCCURRED 0x062900
58613 -#define SS_SAVING_PARAMETERS_NOT_SUPPORTED 0x053900
58614 -#define SS_UNRECOVERED_READ_ERROR 0x031100
58615 -#define SS_WRITE_ERROR 0x030c02
58616 -#define SS_WRITE_PROTECTED 0x072700
58617 -
58618 -#define SK(x) ((u8) ((x) >> 16)) /* Sense Key byte, etc. */
58619 -#define ASC(x) ((u8) ((x) >> 8))
58620 -#define ASCQ(x) ((u8) (x))
58621 -
58622 -
58623 -/*-------------------------------------------------------------------------*/
58624 -
58625 -
58626 -struct fsg_lun {
58627 - struct file *filp;
58628 - loff_t file_length;
58629 - loff_t num_sectors;
58630 -
58631 - unsigned int initially_ro:1;
58632 - unsigned int ro:1;
58633 - unsigned int removable:1;
58634 - unsigned int cdrom:1;
58635 - unsigned int prevent_medium_removal:1;
58636 - unsigned int registered:1;
58637 - unsigned int info_valid:1;
58638 - unsigned int nofua:1;
58639 -
58640 - u32 sense_data;
58641 - u32 sense_data_info;
58642 - u32 unit_attention_data;
58643 -
58644 - unsigned int blkbits; /* Bits of logical block size of bound block device */
58645 - unsigned int blksize; /* logical block size of bound block device */
58646 - struct device dev;
58647 -};
58648 -
58649 -static inline bool fsg_lun_is_open(struct fsg_lun *curlun)
58650 -{
58651 - return curlun->filp != NULL;
58652 -}
58653 -
58654 -static inline struct fsg_lun *fsg_lun_from_dev(struct device *dev)
58655 -{
58656 - return container_of(dev, struct fsg_lun, dev);
58657 -}
58658 -
58659 -
58660 -/* Big enough to hold our biggest descriptor */
58661 -#define EP0_BUFSIZE 256
58662 -#define DELAYED_STATUS (EP0_BUFSIZE + 999) /* An impossibly large value */
58663 -
58664 -#ifdef CONFIG_USB_GADGET_DEBUG_FILES
58665 -
58666 -static unsigned int fsg_num_buffers = CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS;
58667 -module_param_named(num_buffers, fsg_num_buffers, uint, S_IRUGO);
58668 -MODULE_PARM_DESC(num_buffers, "Number of pipeline buffers");
58669 -
58670 -#else
58671 -
58672 -/*
58673 - * Number of buffers we will use.
58674 - * 2 is usually enough for good buffering pipeline
58675 - */
58676 -#define fsg_num_buffers CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS
58677 -
58678 -#endif /* CONFIG_USB_GADGET_DEBUG_FILES */
58679 -
58680 -/* check if fsg_num_buffers is within a valid range */
58681 -static inline int fsg_num_buffers_validate(void)
58682 -{
58683 - if (fsg_num_buffers >= 2 && fsg_num_buffers <= 4)
58684 - return 0;
58685 - pr_err("fsg_num_buffers %u is out of range (%d to %d)\n",
58686 - fsg_num_buffers, 2 ,4);
58687 - return -EINVAL;
58688 -}
58689 -
58690 -/* Default size of buffer length. */
58691 -#define FSG_BUFLEN ((u32)16384)
58692 -
58693 -/* Maximal number of LUNs supported in mass storage function */
58694 -#define FSG_MAX_LUNS 8
58695 -
58696 -enum fsg_buffer_state {
58697 - BUF_STATE_EMPTY = 0,
58698 - BUF_STATE_FULL,
58699 - BUF_STATE_BUSY
58700 -};
58701 -
58702 -struct fsg_buffhd {
58703 - void *buf;
58704 - enum fsg_buffer_state state;
58705 - struct fsg_buffhd *next;
58706 -
58707 - /*
58708 - * The NetChip 2280 is faster, and handles some protocol faults
58709 - * better, if we don't submit any short bulk-out read requests.
58710 - * So we will record the intended request length here.
58711 - */
58712 - unsigned int bulk_out_intended_length;
58713 -
58714 - struct usb_request *inreq;
58715 - int inreq_busy;
58716 - struct usb_request *outreq;
58717 - int outreq_busy;
58718 -};
58719 -
58720 -enum fsg_state {
58721 - /* This one isn't used anywhere */
58722 - FSG_STATE_COMMAND_PHASE = -10,
58723 - FSG_STATE_DATA_PHASE,
58724 - FSG_STATE_STATUS_PHASE,
58725 -
58726 - FSG_STATE_IDLE = 0,
58727 - FSG_STATE_ABORT_BULK_OUT,
58728 - FSG_STATE_RESET,
58729 - FSG_STATE_INTERFACE_CHANGE,
58730 - FSG_STATE_CONFIG_CHANGE,
58731 - FSG_STATE_DISCONNECT,
58732 - FSG_STATE_EXIT,
58733 - FSG_STATE_TERMINATED
58734 -};
58735 -
58736 -enum data_direction {
58737 - DATA_DIR_UNKNOWN = 0,
58738 - DATA_DIR_FROM_HOST,
58739 - DATA_DIR_TO_HOST,
58740 - DATA_DIR_NONE
58741 -};
58742 -
58743 -
58744 -/*-------------------------------------------------------------------------*/
58745 -
58746 -
58747 -static inline u32 get_unaligned_be24(u8 *buf)
58748 -{
58749 - return 0xffffff & (u32) get_unaligned_be32(buf - 1);
58750 -}
58751 -
58752 -
58753 -/*-------------------------------------------------------------------------*/
58754 -
58755 -
58756 -enum {
58757 - FSG_STRING_INTERFACE
58758 -};
58759 -
58760 +#include "storage_common.h"
58761
58762 /* There is only one interface. */
58763
58764 -static struct usb_interface_descriptor
58765 -fsg_intf_desc = {
58766 +struct usb_interface_descriptor fsg_intf_desc = {
58767 .bLength = sizeof fsg_intf_desc,
58768 .bDescriptorType = USB_DT_INTERFACE,
58769
58770 @@ -268,14 +43,14 @@ fsg_intf_desc = {
58771 .bInterfaceProtocol = USB_PR_BULK, /* Adjusted during fsg_bind() */
58772 .iInterface = FSG_STRING_INTERFACE,
58773 };
58774 +EXPORT_SYMBOL(fsg_intf_desc);
58775
58776 /*
58777 * Three full-speed endpoint descriptors: bulk-in, bulk-out, and
58778 * interrupt-in.
58779 */
58780
58781 -static struct usb_endpoint_descriptor
58782 -fsg_fs_bulk_in_desc = {
58783 +struct usb_endpoint_descriptor fsg_fs_bulk_in_desc = {
58784 .bLength = USB_DT_ENDPOINT_SIZE,
58785 .bDescriptorType = USB_DT_ENDPOINT,
58786
58787 @@ -283,9 +58,9 @@ fsg_fs_bulk_in_desc = {
58788 .bmAttributes = USB_ENDPOINT_XFER_BULK,
58789 /* wMaxPacketSize set by autoconfiguration */
58790 };
58791 +EXPORT_SYMBOL(fsg_fs_bulk_in_desc);
58792
58793 -static struct usb_endpoint_descriptor
58794 -fsg_fs_bulk_out_desc = {
58795 +struct usb_endpoint_descriptor fsg_fs_bulk_out_desc = {
58796 .bLength = USB_DT_ENDPOINT_SIZE,
58797 .bDescriptorType = USB_DT_ENDPOINT,
58798
58799 @@ -293,13 +68,15 @@ fsg_fs_bulk_out_desc = {
58800 .bmAttributes = USB_ENDPOINT_XFER_BULK,
58801 /* wMaxPacketSize set by autoconfiguration */
58802 };
58803 +EXPORT_SYMBOL(fsg_fs_bulk_out_desc);
58804
58805 -static struct usb_descriptor_header *fsg_fs_function[] = {
58806 +struct usb_descriptor_header *fsg_fs_function[] = {
58807 (struct usb_descriptor_header *) &fsg_intf_desc,
58808 (struct usb_descriptor_header *) &fsg_fs_bulk_in_desc,
58809 (struct usb_descriptor_header *) &fsg_fs_bulk_out_desc,
58810 NULL,
58811 };
58812 +EXPORT_SYMBOL(fsg_fs_function);
58813
58814
58815 /*
58816 @@ -310,8 +87,7 @@ static struct usb_descriptor_header *fsg
58817 * and a "device qualifier" ... plus more construction options
58818 * for the configuration descriptor.
58819 */
58820 -static struct usb_endpoint_descriptor
58821 -fsg_hs_bulk_in_desc = {
58822 +struct usb_endpoint_descriptor fsg_hs_bulk_in_desc = {
58823 .bLength = USB_DT_ENDPOINT_SIZE,
58824 .bDescriptorType = USB_DT_ENDPOINT,
58825
58826 @@ -319,9 +95,9 @@ fsg_hs_bulk_in_desc = {
58827 .bmAttributes = USB_ENDPOINT_XFER_BULK,
58828 .wMaxPacketSize = cpu_to_le16(512),
58829 };
58830 +EXPORT_SYMBOL(fsg_hs_bulk_in_desc);
58831
58832 -static struct usb_endpoint_descriptor
58833 -fsg_hs_bulk_out_desc = {
58834 +struct usb_endpoint_descriptor fsg_hs_bulk_out_desc = {
58835 .bLength = USB_DT_ENDPOINT_SIZE,
58836 .bDescriptorType = USB_DT_ENDPOINT,
58837
58838 @@ -330,17 +106,18 @@ fsg_hs_bulk_out_desc = {
58839 .wMaxPacketSize = cpu_to_le16(512),
58840 .bInterval = 1, /* NAK every 1 uframe */
58841 };
58842 +EXPORT_SYMBOL(fsg_hs_bulk_out_desc);
58843
58844
58845 -static struct usb_descriptor_header *fsg_hs_function[] = {
58846 +struct usb_descriptor_header *fsg_hs_function[] = {
58847 (struct usb_descriptor_header *) &fsg_intf_desc,
58848 (struct usb_descriptor_header *) &fsg_hs_bulk_in_desc,
58849 (struct usb_descriptor_header *) &fsg_hs_bulk_out_desc,
58850 NULL,
58851 };
58852 +EXPORT_SYMBOL(fsg_hs_function);
58853
58854 -static struct usb_endpoint_descriptor
58855 -fsg_ss_bulk_in_desc = {
58856 +struct usb_endpoint_descriptor fsg_ss_bulk_in_desc = {
58857 .bLength = USB_DT_ENDPOINT_SIZE,
58858 .bDescriptorType = USB_DT_ENDPOINT,
58859
58860 @@ -348,16 +125,17 @@ fsg_ss_bulk_in_desc = {
58861 .bmAttributes = USB_ENDPOINT_XFER_BULK,
58862 .wMaxPacketSize = cpu_to_le16(1024),
58863 };
58864 +EXPORT_SYMBOL(fsg_ss_bulk_in_desc);
58865
58866 -static struct usb_ss_ep_comp_descriptor fsg_ss_bulk_in_comp_desc = {
58867 +struct usb_ss_ep_comp_descriptor fsg_ss_bulk_in_comp_desc = {
58868 .bLength = sizeof(fsg_ss_bulk_in_comp_desc),
58869 .bDescriptorType = USB_DT_SS_ENDPOINT_COMP,
58870
58871 /*.bMaxBurst = DYNAMIC, */
58872 };
58873 +EXPORT_SYMBOL(fsg_ss_bulk_in_comp_desc);
58874
58875 -static struct usb_endpoint_descriptor
58876 -fsg_ss_bulk_out_desc = {
58877 +struct usb_endpoint_descriptor fsg_ss_bulk_out_desc = {
58878 .bLength = USB_DT_ENDPOINT_SIZE,
58879 .bDescriptorType = USB_DT_ENDPOINT,
58880
58881 @@ -365,15 +143,17 @@ fsg_ss_bulk_out_desc = {
58882 .bmAttributes = USB_ENDPOINT_XFER_BULK,
58883 .wMaxPacketSize = cpu_to_le16(1024),
58884 };
58885 +EXPORT_SYMBOL(fsg_ss_bulk_out_desc);
58886
58887 -static struct usb_ss_ep_comp_descriptor fsg_ss_bulk_out_comp_desc = {
58888 +struct usb_ss_ep_comp_descriptor fsg_ss_bulk_out_comp_desc = {
58889 .bLength = sizeof(fsg_ss_bulk_in_comp_desc),
58890 .bDescriptorType = USB_DT_SS_ENDPOINT_COMP,
58891
58892 /*.bMaxBurst = DYNAMIC, */
58893 };
58894 +EXPORT_SYMBOL(fsg_ss_bulk_out_comp_desc);
58895
58896 -static struct usb_descriptor_header *fsg_ss_function[] = {
58897 +struct usb_descriptor_header *fsg_ss_function[] = {
58898 (struct usb_descriptor_header *) &fsg_intf_desc,
58899 (struct usb_descriptor_header *) &fsg_ss_bulk_in_desc,
58900 (struct usb_descriptor_header *) &fsg_ss_bulk_in_comp_desc,
58901 @@ -381,17 +161,7 @@ static struct usb_descriptor_header *fsg
58902 (struct usb_descriptor_header *) &fsg_ss_bulk_out_comp_desc,
58903 NULL,
58904 };
58905 -
58906 -/* Static strings, in UTF-8 (for simplicity we use only ASCII characters) */
58907 -static struct usb_string fsg_strings[] = {
58908 - {FSG_STRING_INTERFACE, fsg_string_interface},
58909 - {}
58910 -};
58911 -
58912 -static struct usb_gadget_strings fsg_stringtab = {
58913 - .language = 0x0409, /* en-us */
58914 - .strings = fsg_strings,
58915 -};
58916 +EXPORT_SYMBOL(fsg_ss_function);
58917
58918
58919 /*-------------------------------------------------------------------------*/
58920 @@ -401,7 +171,7 @@ static struct usb_gadget_strings fsg_str
58921 * the caller must own fsg->filesem for writing.
58922 */
58923
58924 -static void fsg_lun_close(struct fsg_lun *curlun)
58925 +void fsg_lun_close(struct fsg_lun *curlun)
58926 {
58927 if (curlun->filp) {
58928 LDBG(curlun, "close backing file\n");
58929 @@ -409,9 +179,9 @@ static void fsg_lun_close(struct fsg_lun
58930 curlun->filp = NULL;
58931 }
58932 }
58933 +EXPORT_SYMBOL(fsg_lun_close);
58934
58935 -
58936 -static int fsg_lun_open(struct fsg_lun *curlun, const char *filename)
58937 +int fsg_lun_open(struct fsg_lun *curlun, const char *filename)
58938 {
58939 int ro;
58940 struct file *filp = NULL;
58941 @@ -508,6 +278,7 @@ out:
58942 fput(filp);
58943 return rc;
58944 }
58945 +EXPORT_SYMBOL(fsg_lun_open);
58946
58947
58948 /*-------------------------------------------------------------------------*/
58949 @@ -516,7 +287,7 @@ out:
58950 * Sync the file data, don't bother with the metadata.
58951 * This code was copied from fs/buffer.c:sys_fdatasync().
58952 */
58953 -static int fsg_lun_fsync_sub(struct fsg_lun *curlun)
58954 +int fsg_lun_fsync_sub(struct fsg_lun *curlun)
58955 {
58956 struct file *filp = curlun->filp;
58957
58958 @@ -524,8 +295,9 @@ static int fsg_lun_fsync_sub(struct fsg_
58959 return 0;
58960 return vfs_fsync(filp, 1);
58961 }
58962 +EXPORT_SYMBOL(fsg_lun_fsync_sub);
58963
58964 -static void store_cdrom_address(u8 *dest, int msf, u32 addr)
58965 +void store_cdrom_address(u8 *dest, int msf, u32 addr)
58966 {
58967 if (msf) {
58968 /* Convert to Minutes-Seconds-Frames */
58969 @@ -542,34 +314,28 @@ static void store_cdrom_address(u8 *dest
58970 put_unaligned_be32(addr, dest);
58971 }
58972 }
58973 -
58974 +EXPORT_SYMBOL(store_cdrom_address);
58975
58976 /*-------------------------------------------------------------------------*/
58977
58978
58979 -static ssize_t ro_show(struct device *dev, struct device_attribute *attr,
58980 - char *buf)
58981 +ssize_t fsg_show_ro(struct fsg_lun *curlun, char *buf)
58982 {
58983 - struct fsg_lun *curlun = fsg_lun_from_dev(dev);
58984 -
58985 return sprintf(buf, "%d\n", fsg_lun_is_open(curlun)
58986 ? curlun->ro
58987 : curlun->initially_ro);
58988 }
58989 +EXPORT_SYMBOL(fsg_show_ro);
58990
58991 -static ssize_t nofua_show(struct device *dev, struct device_attribute *attr,
58992 - char *buf)
58993 +ssize_t fsg_show_nofua(struct fsg_lun *curlun, char *buf)
58994 {
58995 - struct fsg_lun *curlun = fsg_lun_from_dev(dev);
58996 -
58997 return sprintf(buf, "%u\n", curlun->nofua);
58998 }
58999 +EXPORT_SYMBOL(fsg_show_nofua);
59000
59001 -static ssize_t file_show(struct device *dev, struct device_attribute *attr,
59002 - char *buf)
59003 +ssize_t fsg_show_file(struct fsg_lun *curlun, struct rw_semaphore *filesem,
59004 + char *buf)
59005 {
59006 - struct fsg_lun *curlun = fsg_lun_from_dev(dev);
59007 - struct rw_semaphore *filesem = dev_get_drvdata(dev);
59008 char *p;
59009 ssize_t rc;
59010
59011 @@ -591,17 +357,44 @@ static ssize_t file_show(struct device *
59012 up_read(filesem);
59013 return rc;
59014 }
59015 +EXPORT_SYMBOL(fsg_show_file);
59016
59017 +ssize_t fsg_show_cdrom(struct fsg_lun *curlun, char *buf)
59018 +{
59019 + return sprintf(buf, "%u\n", curlun->cdrom);
59020 +}
59021 +EXPORT_SYMBOL(fsg_show_cdrom);
59022
59023 -static ssize_t ro_store(struct device *dev, struct device_attribute *attr,
59024 - const char *buf, size_t count)
59025 +ssize_t fsg_show_removable(struct fsg_lun *curlun, char *buf)
59026 +{
59027 + return sprintf(buf, "%u\n", curlun->removable);
59028 +}
59029 +EXPORT_SYMBOL(fsg_show_removable);
59030 +
59031 +/*
59032 + * The caller must hold fsg->filesem for reading when calling this function.
59033 + */
59034 +static ssize_t _fsg_store_ro(struct fsg_lun *curlun, bool ro)
59035 +{
59036 + if (fsg_lun_is_open(curlun)) {
59037 + LDBG(curlun, "read-only status change prevented\n");
59038 + return -EBUSY;
59039 + }
59040 +
59041 + curlun->ro = ro;
59042 + curlun->initially_ro = ro;
59043 + LDBG(curlun, "read-only status set to %d\n", curlun->ro);
59044 +
59045 + return 0;
59046 +}
59047 +
59048 +ssize_t fsg_store_ro(struct fsg_lun *curlun, struct rw_semaphore *filesem,
59049 + const char *buf, size_t count)
59050 {
59051 ssize_t rc;
59052 - struct fsg_lun *curlun = fsg_lun_from_dev(dev);
59053 - struct rw_semaphore *filesem = dev_get_drvdata(dev);
59054 - unsigned ro;
59055 + bool ro;
59056
59057 - rc = kstrtouint(buf, 2, &ro);
59058 + rc = strtobool(buf, &ro);
59059 if (rc)
59060 return rc;
59061
59062 @@ -610,27 +403,21 @@ static ssize_t ro_store(struct device *d
59063 * backing file is closed.
59064 */
59065 down_read(filesem);
59066 - if (fsg_lun_is_open(curlun)) {
59067 - LDBG(curlun, "read-only status change prevented\n");
59068 - rc = -EBUSY;
59069 - } else {
59070 - curlun->ro = ro;
59071 - curlun->initially_ro = ro;
59072 - LDBG(curlun, "read-only status set to %d\n", curlun->ro);
59073 + rc = _fsg_store_ro(curlun, ro);
59074 + if (!rc)
59075 rc = count;
59076 - }
59077 up_read(filesem);
59078 +
59079 return rc;
59080 }
59081 +EXPORT_SYMBOL(fsg_store_ro);
59082
59083 -static ssize_t nofua_store(struct device *dev, struct device_attribute *attr,
59084 - const char *buf, size_t count)
59085 +ssize_t fsg_store_nofua(struct fsg_lun *curlun, const char *buf, size_t count)
59086 {
59087 - struct fsg_lun *curlun = fsg_lun_from_dev(dev);
59088 - unsigned nofua;
59089 + bool nofua;
59090 int ret;
59091
59092 - ret = kstrtouint(buf, 2, &nofua);
59093 + ret = strtobool(buf, &nofua);
59094 if (ret)
59095 return ret;
59096
59097 @@ -642,12 +429,11 @@ static ssize_t nofua_store(struct device
59098
59099 return count;
59100 }
59101 +EXPORT_SYMBOL(fsg_store_nofua);
59102
59103 -static ssize_t file_store(struct device *dev, struct device_attribute *attr,
59104 - const char *buf, size_t count)
59105 +ssize_t fsg_store_file(struct fsg_lun *curlun, struct rw_semaphore *filesem,
59106 + const char *buf, size_t count)
59107 {
59108 - struct fsg_lun *curlun = fsg_lun_from_dev(dev);
59109 - struct rw_semaphore *filesem = dev_get_drvdata(dev);
59110 int rc = 0;
59111
59112 if (curlun->prevent_medium_removal && fsg_lun_is_open(curlun)) {
59113 @@ -674,3 +460,45 @@ static ssize_t file_store(struct device
59114 up_write(filesem);
59115 return (rc < 0 ? rc : count);
59116 }
59117 +EXPORT_SYMBOL(fsg_store_file);
59118 +
59119 +ssize_t fsg_store_cdrom(struct fsg_lun *curlun, struct rw_semaphore *filesem,
59120 + const char *buf, size_t count)
59121 +{
59122 + bool cdrom;
59123 + int ret;
59124 +
59125 + ret = strtobool(buf, &cdrom);
59126 + if (ret)
59127 + return ret;
59128 +
59129 + down_read(filesem);
59130 + ret = cdrom ? _fsg_store_ro(curlun, true) : 0;
59131 +
59132 + if (!ret) {
59133 + curlun->cdrom = cdrom;
59134 + ret = count;
59135 + }
59136 + up_read(filesem);
59137 +
59138 + return ret;
59139 +}
59140 +EXPORT_SYMBOL(fsg_store_cdrom);
59141 +
59142 +ssize_t fsg_store_removable(struct fsg_lun *curlun, const char *buf,
59143 + size_t count)
59144 +{
59145 + bool removable;
59146 + int ret;
59147 +
59148 + ret = strtobool(buf, &removable);
59149 + if (ret)
59150 + return ret;
59151 +
59152 + curlun->removable = removable;
59153 +
59154 + return count;
59155 +}
59156 +EXPORT_SYMBOL(fsg_store_removable);
59157 +
59158 +MODULE_LICENSE("GPL");
59159 --- /dev/null
59160 +++ b/drivers/usb/gadget/storage_common.h
59161 @@ -0,0 +1,229 @@
59162 +#ifndef USB_STORAGE_COMMON_H
59163 +#define USB_STORAGE_COMMON_H
59164 +
59165 +#include <linux/device.h>
59166 +#include <linux/usb/storage.h>
59167 +#include <scsi/scsi.h>
59168 +#include <asm/unaligned.h>
59169 +
59170 +#ifndef DEBUG
59171 +#undef VERBOSE_DEBUG
59172 +#undef DUMP_MSGS
59173 +#endif /* !DEBUG */
59174 +
59175 +#ifdef VERBOSE_DEBUG
59176 +#define VLDBG LDBG
59177 +#else
59178 +#define VLDBG(lun, fmt, args...) do { } while (0)
59179 +#endif /* VERBOSE_DEBUG */
59180 +
59181 +#define _LMSG(func, lun, fmt, args...) \
59182 + do { \
59183 + if ((lun)->name_pfx && *(lun)->name_pfx) \
59184 + func("%s/%s: " fmt, *(lun)->name_pfx, \
59185 + (lun)->name, ## args); \
59186 + else \
59187 + func("%s: " fmt, (lun)->name, ## args); \
59188 + } while (0)
59189 +
59190 +#define LDBG(lun, fmt, args...) _LMSG(pr_debug, lun, fmt, ## args)
59191 +#define LERROR(lun, fmt, args...) _LMSG(pr_err, lun, fmt, ## args)
59192 +#define LWARN(lun, fmt, args...) _LMSG(pr_warn, lun, fmt, ## args)
59193 +#define LINFO(lun, fmt, args...) _LMSG(pr_info, lun, fmt, ## args)
59194 +
59195 +
59196 +#ifdef DUMP_MSGS
59197 +
59198 +# define dump_msg(fsg, /* const char * */ label, \
59199 + /* const u8 * */ buf, /* unsigned */ length) \
59200 +do { \
59201 + if (length < 512) { \
59202 + DBG(fsg, "%s, length %u:\n", label, length); \
59203 + print_hex_dump(KERN_DEBUG, "", DUMP_PREFIX_OFFSET, \
59204 + 16, 1, buf, length, 0); \
59205 + } \
59206 +} while (0)
59207 +
59208 +# define dump_cdb(fsg) do { } while (0)
59209 +
59210 +#else
59211 +
59212 +# define dump_msg(fsg, /* const char * */ label, \
59213 + /* const u8 * */ buf, /* unsigned */ length) do { } while (0)
59214 +
59215 +# ifdef VERBOSE_DEBUG
59216 +
59217 +# define dump_cdb(fsg) \
59218 + print_hex_dump(KERN_DEBUG, "SCSI CDB: ", DUMP_PREFIX_NONE, \
59219 + 16, 1, (fsg)->cmnd, (fsg)->cmnd_size, 0) \
59220 +
59221 +# else
59222 +
59223 +# define dump_cdb(fsg) do { } while (0)
59224 +
59225 +# endif /* VERBOSE_DEBUG */
59226 +
59227 +#endif /* DUMP_MSGS */
59228 +
59229 +/* Length of a SCSI Command Data Block */
59230 +#define MAX_COMMAND_SIZE 16
59231 +
59232 +/* SCSI Sense Key/Additional Sense Code/ASC Qualifier values */
59233 +#define SS_NO_SENSE 0
59234 +#define SS_COMMUNICATION_FAILURE 0x040800
59235 +#define SS_INVALID_COMMAND 0x052000
59236 +#define SS_INVALID_FIELD_IN_CDB 0x052400
59237 +#define SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE 0x052100
59238 +#define SS_LOGICAL_UNIT_NOT_SUPPORTED 0x052500
59239 +#define SS_MEDIUM_NOT_PRESENT 0x023a00
59240 +#define SS_MEDIUM_REMOVAL_PREVENTED 0x055302
59241 +#define SS_NOT_READY_TO_READY_TRANSITION 0x062800
59242 +#define SS_RESET_OCCURRED 0x062900
59243 +#define SS_SAVING_PARAMETERS_NOT_SUPPORTED 0x053900
59244 +#define SS_UNRECOVERED_READ_ERROR 0x031100
59245 +#define SS_WRITE_ERROR 0x030c02
59246 +#define SS_WRITE_PROTECTED 0x072700
59247 +
59248 +#define SK(x) ((u8) ((x) >> 16)) /* Sense Key byte, etc. */
59249 +#define ASC(x) ((u8) ((x) >> 8))
59250 +#define ASCQ(x) ((u8) (x))
59251 +
59252 +struct fsg_lun {
59253 + struct file *filp;
59254 + loff_t file_length;
59255 + loff_t num_sectors;
59256 +
59257 + unsigned int initially_ro:1;
59258 + unsigned int ro:1;
59259 + unsigned int removable:1;
59260 + unsigned int cdrom:1;
59261 + unsigned int prevent_medium_removal:1;
59262 + unsigned int registered:1;
59263 + unsigned int info_valid:1;
59264 + unsigned int nofua:1;
59265 +
59266 + u32 sense_data;
59267 + u32 sense_data_info;
59268 + u32 unit_attention_data;
59269 +
59270 + unsigned int blkbits; /* Bits of logical block size
59271 + of bound block device */
59272 + unsigned int blksize; /* logical block size of bound block device */
59273 + struct device dev;
59274 + const char *name; /* "lun.name" */
59275 + const char **name_pfx; /* "function.name" */
59276 +};
59277 +
59278 +static inline bool fsg_lun_is_open(struct fsg_lun *curlun)
59279 +{
59280 + return curlun->filp != NULL;
59281 +}
59282 +
59283 +/* Big enough to hold our biggest descriptor */
59284 +#define EP0_BUFSIZE 256
59285 +#define DELAYED_STATUS (EP0_BUFSIZE + 999) /* An impossibly large value */
59286 +
59287 +/* Default size of buffer length. */
59288 +#define FSG_BUFLEN ((u32)16384)
59289 +
59290 +/* Maximal number of LUNs supported in mass storage function */
59291 +#define FSG_MAX_LUNS 8
59292 +
59293 +enum fsg_buffer_state {
59294 + BUF_STATE_EMPTY = 0,
59295 + BUF_STATE_FULL,
59296 + BUF_STATE_BUSY
59297 +};
59298 +
59299 +struct fsg_buffhd {
59300 + void *buf;
59301 + enum fsg_buffer_state state;
59302 + struct fsg_buffhd *next;
59303 +
59304 + /*
59305 + * The NetChip 2280 is faster, and handles some protocol faults
59306 + * better, if we don't submit any short bulk-out read requests.
59307 + * So we will record the intended request length here.
59308 + */
59309 + unsigned int bulk_out_intended_length;
59310 +
59311 + struct usb_request *inreq;
59312 + int inreq_busy;
59313 + struct usb_request *outreq;
59314 + int outreq_busy;
59315 +};
59316 +
59317 +enum fsg_state {
59318 + /* This one isn't used anywhere */
59319 + FSG_STATE_COMMAND_PHASE = -10,
59320 + FSG_STATE_DATA_PHASE,
59321 + FSG_STATE_STATUS_PHASE,
59322 +
59323 + FSG_STATE_IDLE = 0,
59324 + FSG_STATE_ABORT_BULK_OUT,
59325 + FSG_STATE_RESET,
59326 + FSG_STATE_INTERFACE_CHANGE,
59327 + FSG_STATE_CONFIG_CHANGE,
59328 + FSG_STATE_DISCONNECT,
59329 + FSG_STATE_EXIT,
59330 + FSG_STATE_TERMINATED
59331 +};
59332 +
59333 +enum data_direction {
59334 + DATA_DIR_UNKNOWN = 0,
59335 + DATA_DIR_FROM_HOST,
59336 + DATA_DIR_TO_HOST,
59337 + DATA_DIR_NONE
59338 +};
59339 +
59340 +static inline u32 get_unaligned_be24(u8 *buf)
59341 +{
59342 + return 0xffffff & (u32) get_unaligned_be32(buf - 1);
59343 +}
59344 +
59345 +static inline struct fsg_lun *fsg_lun_from_dev(struct device *dev)
59346 +{
59347 + return container_of(dev, struct fsg_lun, dev);
59348 +}
59349 +
59350 +enum {
59351 + FSG_STRING_INTERFACE
59352 +};
59353 +
59354 +extern struct usb_interface_descriptor fsg_intf_desc;
59355 +
59356 +extern struct usb_endpoint_descriptor fsg_fs_bulk_in_desc;
59357 +extern struct usb_endpoint_descriptor fsg_fs_bulk_out_desc;
59358 +extern struct usb_descriptor_header *fsg_fs_function[];
59359 +
59360 +extern struct usb_endpoint_descriptor fsg_hs_bulk_in_desc;
59361 +extern struct usb_endpoint_descriptor fsg_hs_bulk_out_desc;
59362 +extern struct usb_descriptor_header *fsg_hs_function[];
59363 +
59364 +extern struct usb_endpoint_descriptor fsg_ss_bulk_in_desc;
59365 +extern struct usb_ss_ep_comp_descriptor fsg_ss_bulk_in_comp_desc;
59366 +extern struct usb_endpoint_descriptor fsg_ss_bulk_out_desc;
59367 +extern struct usb_ss_ep_comp_descriptor fsg_ss_bulk_out_comp_desc;
59368 +extern struct usb_descriptor_header *fsg_ss_function[];
59369 +
59370 +void fsg_lun_close(struct fsg_lun *curlun);
59371 +int fsg_lun_open(struct fsg_lun *curlun, const char *filename);
59372 +int fsg_lun_fsync_sub(struct fsg_lun *curlun);
59373 +void store_cdrom_address(u8 *dest, int msf, u32 addr);
59374 +ssize_t fsg_show_ro(struct fsg_lun *curlun, char *buf);
59375 +ssize_t fsg_show_nofua(struct fsg_lun *curlun, char *buf);
59376 +ssize_t fsg_show_file(struct fsg_lun *curlun, struct rw_semaphore *filesem,
59377 + char *buf);
59378 +ssize_t fsg_show_cdrom(struct fsg_lun *curlun, char *buf);
59379 +ssize_t fsg_show_removable(struct fsg_lun *curlun, char *buf);
59380 +ssize_t fsg_store_ro(struct fsg_lun *curlun, struct rw_semaphore *filesem,
59381 + const char *buf, size_t count);
59382 +ssize_t fsg_store_nofua(struct fsg_lun *curlun, const char *buf, size_t count);
59383 +ssize_t fsg_store_file(struct fsg_lun *curlun, struct rw_semaphore *filesem,
59384 + const char *buf, size_t count);
59385 +ssize_t fsg_store_cdrom(struct fsg_lun *curlun, struct rw_semaphore *filesem,
59386 + const char *buf, size_t count);
59387 +ssize_t fsg_store_removable(struct fsg_lun *curlun, const char *buf,
59388 + size_t count);
59389 +
59390 +#endif /* USB_STORAGE_COMMON_H */
59391 --- a/drivers/usb/gadget/udc-core.c
59392 +++ b/drivers/usb/gadget/udc-core.c
59393 @@ -356,7 +356,8 @@ static int udc_bind_to_driver(struct usb
59394 kobject_uevent(&udc->dev.kobj, KOBJ_CHANGE);
59395 return 0;
59396 err1:
59397 - dev_err(&udc->dev, "failed to start %s: %d\n",
59398 + if (ret != -EISNAM)
59399 + dev_err(&udc->dev, "failed to start %s: %d\n",
59400 udc->driver->function, ret);
59401 udc->driver = NULL;
59402 udc->dev.driver = NULL;
59403 --- a/drivers/usb/gadget/zero.c
59404 +++ b/drivers/usb/gadget/zero.c
59405 @@ -95,6 +95,18 @@ unsigned autoresume = DEFAULT_AUTORESUME
59406 module_param(autoresume, uint, S_IRUGO);
59407 MODULE_PARM_DESC(autoresume, "zero, or seconds before remote wakeup");
59408
59409 +/* Maximum Autoresume time */
59410 +unsigned max_autoresume;
59411 +module_param(max_autoresume, uint, S_IRUGO);
59412 +MODULE_PARM_DESC(max_autoresume, "maximum seconds before remote wakeup");
59413 +
59414 +/* Interval between two remote wakeups */
59415 +unsigned autoresume_interval_ms;
59416 +module_param(autoresume_interval_ms, uint, S_IRUGO);
59417 +MODULE_PARM_DESC(autoresume_interval_ms,
59418 + "milliseconds to increase successive wakeup delays");
59419 +
59420 +static unsigned autoresume_step_ms;
59421 /*-------------------------------------------------------------------------*/
59422
59423 static struct usb_device_descriptor device_desc = {
59424 @@ -183,8 +195,16 @@ static void zero_suspend(struct usb_comp
59425 return;
59426
59427 if (autoresume) {
59428 - mod_timer(&autoresume_timer, jiffies + (HZ * autoresume));
59429 - DBG(cdev, "suspend, wakeup in %d seconds\n", autoresume);
59430 + if (max_autoresume &&
59431 + (autoresume_step_ms > max_autoresume * 1000))
59432 + autoresume_step_ms = autoresume * 1000;
59433 +
59434 + mod_timer(&autoresume_timer, jiffies +
59435 + msecs_to_jiffies(autoresume_step_ms));
59436 + DBG(cdev, "suspend, wakeup in %d milliseconds\n",
59437 + autoresume_step_ms);
59438 +
59439 + autoresume_step_ms += autoresume_interval_ms;
59440 } else
59441 DBG(cdev, "%s\n", __func__);
59442 }
59443 @@ -316,6 +336,7 @@ static int __init zero_bind(struct usb_c
59444 if (autoresume) {
59445 sourcesink_driver.bmAttributes |= USB_CONFIG_ATT_WAKEUP;
59446 loopback_driver.bmAttributes |= USB_CONFIG_ATT_WAKEUP;
59447 + autoresume_step_ms = autoresume * 1000;
59448 }
59449
59450 /* support OTG systems */
59451 --- a/drivers/usb/misc/usbtest.c
59452 +++ b/drivers/usb/misc/usbtest.c
59453 @@ -120,7 +120,7 @@ get_endpoints(struct usbtest_dev *dev, s
59454 struct usb_host_endpoint *e;
59455
59456 e = alt->endpoint + ep;
59457 - switch (e->desc.bmAttributes) {
59458 + switch (usb_endpoint_type(&e->desc)) {
59459 case USB_ENDPOINT_XFER_BULK:
59460 break;
59461 case USB_ENDPOINT_XFER_ISOC:
59462 --- a/drivers/usb/musb/am35x.c
59463 +++ b/drivers/usb/musb/am35x.c
59464 @@ -89,7 +89,6 @@ struct am35x_glue {
59465 struct clk *phy_clk;
59466 struct clk *clk;
59467 };
59468 -#define glue_to_musb(g) platform_get_drvdata(g->musb)
59469
59470 /*
59471 * am35x_musb_enable - enable interrupts
59472 @@ -452,14 +451,18 @@ static const struct musb_platform_ops am
59473 .set_vbus = am35x_musb_set_vbus,
59474 };
59475
59476 -static u64 am35x_dmamask = DMA_BIT_MASK(32);
59477 +static const struct platform_device_info am35x_dev_info = {
59478 + .name = "musb-hdrc",
59479 + .id = PLATFORM_DEVID_AUTO,
59480 + .dma_mask = DMA_BIT_MASK(32),
59481 +};
59482
59483 static int am35x_probe(struct platform_device *pdev)
59484 {
59485 struct musb_hdrc_platform_data *pdata = dev_get_platdata(&pdev->dev);
59486 struct platform_device *musb;
59487 struct am35x_glue *glue;
59488 -
59489 + struct platform_device_info pinfo;
59490 struct clk *phy_clk;
59491 struct clk *clk;
59492
59493 @@ -471,12 +474,6 @@ static int am35x_probe(struct platform_d
59494 goto err0;
59495 }
59496
59497 - musb = platform_device_alloc("musb-hdrc", PLATFORM_DEVID_AUTO);
59498 - if (!musb) {
59499 - dev_err(&pdev->dev, "failed to allocate musb device\n");
59500 - goto err1;
59501 - }
59502 -
59503 phy_clk = clk_get(&pdev->dev, "fck");
59504 if (IS_ERR(phy_clk)) {
59505 dev_err(&pdev->dev, "failed to get PHY clock\n");
59506 @@ -503,12 +500,7 @@ static int am35x_probe(struct platform_d
59507 goto err6;
59508 }
59509
59510 - musb->dev.parent = &pdev->dev;
59511 - musb->dev.dma_mask = &am35x_dmamask;
59512 - musb->dev.coherent_dma_mask = am35x_dmamask;
59513 -
59514 glue->dev = &pdev->dev;
59515 - glue->musb = musb;
59516 glue->phy_clk = phy_clk;
59517 glue->clk = clk;
59518
59519 @@ -516,22 +508,17 @@ static int am35x_probe(struct platform_d
59520
59521 platform_set_drvdata(pdev, glue);
59522
59523 - ret = platform_device_add_resources(musb, pdev->resource,
59524 - pdev->num_resources);
59525 - if (ret) {
59526 - dev_err(&pdev->dev, "failed to add resources\n");
59527 - goto err7;
59528 - }
59529 -
59530 - ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
59531 - if (ret) {
59532 - dev_err(&pdev->dev, "failed to add platform_data\n");
59533 - goto err7;
59534 - }
59535 -
59536 - ret = platform_device_add(musb);
59537 - if (ret) {
59538 - dev_err(&pdev->dev, "failed to register musb device\n");
59539 + pinfo = am35x_dev_info;
59540 + pinfo.parent = &pdev->dev;
59541 + pinfo.res = pdev->resource;
59542 + pinfo.num_res = pdev->num_resources;
59543 + pinfo.data = pdata;
59544 + pinfo.size_data = sizeof(*pdata);
59545 +
59546 + glue->musb = musb = platform_device_register_full(&pinfo);
59547 + if (IS_ERR(musb)) {
59548 + ret = PTR_ERR(musb);
59549 + dev_err(&pdev->dev, "failed to register musb device: %d\n", ret);
59550 goto err7;
59551 }
59552
59553 @@ -550,9 +537,6 @@ err4:
59554 clk_put(phy_clk);
59555
59556 err3:
59557 - platform_device_put(musb);
59558 -
59559 -err1:
59560 kfree(glue);
59561
59562 err0:
59563 @@ -615,23 +599,16 @@ static int am35x_resume(struct device *d
59564
59565 return 0;
59566 }
59567 -
59568 -static struct dev_pm_ops am35x_pm_ops = {
59569 - .suspend = am35x_suspend,
59570 - .resume = am35x_resume,
59571 -};
59572 -
59573 -#define DEV_PM_OPS &am35x_pm_ops
59574 -#else
59575 -#define DEV_PM_OPS NULL
59576 #endif
59577
59578 +static SIMPLE_DEV_PM_OPS(am35x_pm_ops, am35x_suspend, am35x_resume);
59579 +
59580 static struct platform_driver am35x_driver = {
59581 .probe = am35x_probe,
59582 .remove = am35x_remove,
59583 .driver = {
59584 .name = "musb-am35x",
59585 - .pm = DEV_PM_OPS,
59586 + .pm = &am35x_pm_ops,
59587 },
59588 };
59589
59590 --- a/drivers/usb/musb/blackfin.c
59591 +++ b/drivers/usb/musb/blackfin.c
59592 @@ -561,23 +561,16 @@ static int bfin_resume(struct device *de
59593
59594 return 0;
59595 }
59596 -
59597 -static struct dev_pm_ops bfin_pm_ops = {
59598 - .suspend = bfin_suspend,
59599 - .resume = bfin_resume,
59600 -};
59601 -
59602 -#define DEV_PM_OPS &bfin_pm_ops
59603 -#else
59604 -#define DEV_PM_OPS NULL
59605 #endif
59606
59607 +static SIMPLE_DEV_PM_OPS(bfin_pm_ops, bfin_suspend, bfin_resume);
59608 +
59609 static struct platform_driver bfin_driver = {
59610 .probe = bfin_probe,
59611 .remove = __exit_p(bfin_remove),
59612 .driver = {
59613 .name = "musb-blackfin",
59614 - .pm = DEV_PM_OPS,
59615 + .pm = &bfin_pm_ops,
59616 },
59617 };
59618
59619 --- a/drivers/usb/musb/da8xx.c
59620 +++ b/drivers/usb/musb/da8xx.c
59621 @@ -472,7 +472,11 @@ static const struct musb_platform_ops da
59622 .set_vbus = da8xx_musb_set_vbus,
59623 };
59624
59625 -static u64 da8xx_dmamask = DMA_BIT_MASK(32);
59626 +static const struct platform_device_info da8xx_dev_info = {
59627 + .name = "musb-hdrc",
59628 + .id = PLATFORM_DEVID_AUTO,
59629 + .dma_mask = DMA_BIT_MASK(32),
59630 +};
59631
59632 static int da8xx_probe(struct platform_device *pdev)
59633 {
59634 @@ -480,7 +484,7 @@ static int da8xx_probe(struct platform_d
59635 struct musb_hdrc_platform_data *pdata = dev_get_platdata(&pdev->dev);
59636 struct platform_device *musb;
59637 struct da8xx_glue *glue;
59638 -
59639 + struct platform_device_info pinfo;
59640 struct clk *clk;
59641
59642 int ret = -ENOMEM;
59643 @@ -491,12 +495,6 @@ static int da8xx_probe(struct platform_d
59644 goto err0;
59645 }
59646
59647 - musb = platform_device_alloc("musb-hdrc", PLATFORM_DEVID_AUTO);
59648 - if (!musb) {
59649 - dev_err(&pdev->dev, "failed to allocate musb device\n");
59650 - goto err1;
59651 - }
59652 -
59653 clk = clk_get(&pdev->dev, "usb20");
59654 if (IS_ERR(clk)) {
59655 dev_err(&pdev->dev, "failed to get clock\n");
59656 @@ -510,12 +508,7 @@ static int da8xx_probe(struct platform_d
59657 goto err4;
59658 }
59659
59660 - musb->dev.parent = &pdev->dev;
59661 - musb->dev.dma_mask = &da8xx_dmamask;
59662 - musb->dev.coherent_dma_mask = da8xx_dmamask;
59663 -
59664 glue->dev = &pdev->dev;
59665 - glue->musb = musb;
59666 glue->clk = clk;
59667
59668 pdata->platform_ops = &da8xx_ops;
59669 @@ -535,22 +528,17 @@ static int da8xx_probe(struct platform_d
59670 musb_resources[1].end = pdev->resource[1].end;
59671 musb_resources[1].flags = pdev->resource[1].flags;
59672
59673 - ret = platform_device_add_resources(musb, musb_resources,
59674 - ARRAY_SIZE(musb_resources));
59675 - if (ret) {
59676 - dev_err(&pdev->dev, "failed to add resources\n");
59677 - goto err5;
59678 - }
59679 -
59680 - ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
59681 - if (ret) {
59682 - dev_err(&pdev->dev, "failed to add platform_data\n");
59683 - goto err5;
59684 - }
59685 -
59686 - ret = platform_device_add(musb);
59687 - if (ret) {
59688 - dev_err(&pdev->dev, "failed to register musb device\n");
59689 + pinfo = da8xx_dev_info;
59690 + pinfo.parent = &pdev->dev;
59691 + pinfo.res = musb_resources;
59692 + pinfo.num_res = ARRAY_SIZE(musb_resources);
59693 + pinfo.data = pdata;
59694 + pinfo.size_data = sizeof(*pdata);
59695 +
59696 + glue->musb = musb = platform_device_register_full(&pinfo);
59697 + if (IS_ERR(musb)) {
59698 + ret = PTR_ERR(musb);
59699 + dev_err(&pdev->dev, "failed to register musb device: %d\n", ret);
59700 goto err5;
59701 }
59702
59703 @@ -563,9 +551,6 @@ err4:
59704 clk_put(clk);
59705
59706 err3:
59707 - platform_device_put(musb);
59708 -
59709 -err1:
59710 kfree(glue);
59711
59712 err0:
59713 --- a/drivers/usb/musb/davinci.c
59714 +++ b/drivers/usb/musb/davinci.c
59715 @@ -505,14 +505,19 @@ static const struct musb_platform_ops da
59716 .set_vbus = davinci_musb_set_vbus,
59717 };
59718
59719 -static u64 davinci_dmamask = DMA_BIT_MASK(32);
59720 +static const struct platform_device_info davinci_dev_info = {
59721 + .name = "musb-hdrc",
59722 + .id = PLATFORM_DEVID_AUTO,
59723 + .dma_mask = DMA_BIT_MASK(32),
59724 +};
59725
59726 static int davinci_probe(struct platform_device *pdev)
59727 {
59728 - struct resource musb_resources[2];
59729 + struct resource musb_resources[3];
59730 struct musb_hdrc_platform_data *pdata = dev_get_platdata(&pdev->dev);
59731 struct platform_device *musb;
59732 struct davinci_glue *glue;
59733 + struct platform_device_info pinfo;
59734 struct clk *clk;
59735
59736 int ret = -ENOMEM;
59737 @@ -523,12 +528,6 @@ static int davinci_probe(struct platform
59738 goto err0;
59739 }
59740
59741 - musb = platform_device_alloc("musb-hdrc", PLATFORM_DEVID_AUTO);
59742 - if (!musb) {
59743 - dev_err(&pdev->dev, "failed to allocate musb device\n");
59744 - goto err1;
59745 - }
59746 -
59747 clk = clk_get(&pdev->dev, "usb");
59748 if (IS_ERR(clk)) {
59749 dev_err(&pdev->dev, "failed to get clock\n");
59750 @@ -542,12 +541,7 @@ static int davinci_probe(struct platform
59751 goto err4;
59752 }
59753
59754 - musb->dev.parent = &pdev->dev;
59755 - musb->dev.dma_mask = &davinci_dmamask;
59756 - musb->dev.coherent_dma_mask = davinci_dmamask;
59757 -
59758 glue->dev = &pdev->dev;
59759 - glue->musb = musb;
59760 glue->clk = clk;
59761
59762 pdata->platform_ops = &davinci_ops;
59763 @@ -567,22 +561,26 @@ static int davinci_probe(struct platform
59764 musb_resources[1].end = pdev->resource[1].end;
59765 musb_resources[1].flags = pdev->resource[1].flags;
59766
59767 - ret = platform_device_add_resources(musb, musb_resources,
59768 - ARRAY_SIZE(musb_resources));
59769 - if (ret) {
59770 - dev_err(&pdev->dev, "failed to add resources\n");
59771 - goto err5;
59772 - }
59773 -
59774 - ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
59775 - if (ret) {
59776 - dev_err(&pdev->dev, "failed to add platform_data\n");
59777 - goto err5;
59778 - }
59779 -
59780 - ret = platform_device_add(musb);
59781 - if (ret) {
59782 - dev_err(&pdev->dev, "failed to register musb device\n");
59783 + /*
59784 + * For DM6467 3 resources are passed. A placeholder for the 3rd
59785 + * resource is always there, so it's safe to always copy it...
59786 + */
59787 + musb_resources[2].name = pdev->resource[2].name;
59788 + musb_resources[2].start = pdev->resource[2].start;
59789 + musb_resources[2].end = pdev->resource[2].end;
59790 + musb_resources[2].flags = pdev->resource[2].flags;
59791 +
59792 + pinfo = davinci_dev_info;
59793 + pinfo.parent = &pdev->dev;
59794 + pinfo.res = musb_resources;
59795 + pinfo.num_res = ARRAY_SIZE(musb_resources);
59796 + pinfo.data = pdata;
59797 + pinfo.size_data = sizeof(*pdata);
59798 +
59799 + glue->musb = musb = platform_device_register_full(&pinfo);
59800 + if (IS_ERR(musb)) {
59801 + ret = PTR_ERR(musb);
59802 + dev_err(&pdev->dev, "failed to register musb device: %d\n", ret);
59803 goto err5;
59804 }
59805
59806 @@ -595,9 +593,6 @@ err4:
59807 clk_put(clk);
59808
59809 err3:
59810 - platform_device_put(musb);
59811 -
59812 -err1:
59813 kfree(glue);
59814
59815 err0:
59816 --- a/drivers/usb/musb/Kconfig
59817 +++ b/drivers/usb/musb/Kconfig
59818 @@ -75,6 +75,7 @@ config USB_MUSB_TUSB6010
59819 config USB_MUSB_OMAP2PLUS
59820 tristate "OMAP2430 and onwards"
59821 depends on ARCH_OMAP2PLUS
59822 + select GENERIC_PHY
59823
59824 config USB_MUSB_AM35X
59825 tristate "AM35x"
59826 @@ -90,7 +91,7 @@ config USB_MUSB_BLACKFIN
59827 depends on (BF54x && !BF544) || (BF52x && ! BF522 && !BF523)
59828
59829 config USB_MUSB_UX500
59830 - tristate "U8500 and U5500"
59831 + tristate "Ux500 platforms"
59832
59833 endchoice
59834
59835 @@ -112,7 +113,7 @@ choice
59836 allow using DMA on multiplatform kernels.
59837
59838 config USB_UX500_DMA
59839 - bool 'ST Ericsson U8500 and U5500'
59840 + bool 'ST Ericsson Ux500'
59841 depends on USB_MUSB_UX500
59842 help
59843 Enable DMA transfers on UX500 platforms.
59844 --- a/drivers/usb/musb/musb_am335x.c
59845 +++ b/drivers/usb/musb/musb_am335x.c
59846 @@ -46,7 +46,7 @@ static struct platform_driver am335x_chi
59847 .remove = am335x_child_remove,
59848 .driver = {
59849 .name = "am335x-usb-childs",
59850 - .of_match_table = of_match_ptr(am335x_child_of_match),
59851 + .of_match_table = am335x_child_of_match,
59852 },
59853 };
59854
59855 --- a/drivers/usb/musb/musb_core.c
59856 +++ b/drivers/usb/musb/musb_core.c
59857 @@ -94,6 +94,7 @@
59858 #include <linux/sched.h>
59859 #include <linux/slab.h>
59860 #include <linux/init.h>
59861 +#include <linux/idr.h>
59862 #include <linux/list.h>
59863 #include <linux/kobject.h>
59864 #include <linux/prefetch.h>
59865 @@ -120,7 +121,7 @@ MODULE_DESCRIPTION(DRIVER_INFO);
59866 MODULE_AUTHOR(DRIVER_AUTHOR);
59867 MODULE_LICENSE("GPL");
59868 MODULE_ALIAS("platform:" MUSB_DRIVER_NAME);
59869 -
59870 +static DEFINE_IDA(musb_ida);
59871
59872 /*-------------------------------------------------------------------------*/
59873
59874 @@ -131,6 +132,35 @@ static inline struct musb *dev_to_musb(s
59875
59876 /*-------------------------------------------------------------------------*/
59877
59878 +int musb_get_id(struct device *dev, gfp_t gfp_mask)
59879 +{
59880 + int ret;
59881 + int id;
59882 +
59883 + ret = ida_pre_get(&musb_ida, gfp_mask);
59884 + if (!ret) {
59885 + dev_err(dev, "failed to reserve resource for id\n");
59886 + return -ENOMEM;
59887 + }
59888 +
59889 + ret = ida_get_new(&musb_ida, &id);
59890 + if (ret < 0) {
59891 + dev_err(dev, "failed to allocate a new id\n");
59892 + return ret;
59893 + }
59894 +
59895 + return id;
59896 +}
59897 +EXPORT_SYMBOL_GPL(musb_get_id);
59898 +
59899 +void musb_put_id(struct device *dev, int id)
59900 +{
59901 +
59902 + dev_dbg(dev, "removing id %d\n", id);
59903 + ida_remove(&musb_ida, id);
59904 +}
59905 +EXPORT_SYMBOL_GPL(musb_put_id);
59906 +
59907 #ifndef CONFIG_BLACKFIN
59908 static int musb_ulpi_read(struct usb_phy *phy, u32 offset)
59909 {
59910 @@ -1809,8 +1839,7 @@ static void musb_free(struct musb *musb)
59911 disable_irq_wake(musb->nIrq);
59912 free_irq(musb->nIrq, musb);
59913 }
59914 - if (musb->dma_controller)
59915 - dma_controller_destroy(musb->dma_controller);
59916 + cancel_work_sync(&musb->irq_work);
59917
59918 musb_host_free(musb);
59919 }
59920 @@ -1885,8 +1914,13 @@ musb_init_controller(struct device *dev,
59921
59922 pm_runtime_get_sync(musb->controller);
59923
59924 - if (use_dma && dev->dma_mask)
59925 + if (use_dma && dev->dma_mask) {
59926 musb->dma_controller = dma_controller_create(musb, musb->mregs);
59927 + if (IS_ERR(musb->dma_controller)) {
59928 + status = PTR_ERR(musb->dma_controller);
59929 + goto fail2_5;
59930 + }
59931 + }
59932
59933 /* be sure interrupts are disabled before connecting ISR */
59934 musb_platform_disable(musb);
59935 @@ -1937,15 +1971,26 @@ musb_init_controller(struct device *dev,
59936 switch (musb->port_mode) {
59937 case MUSB_PORT_MODE_HOST:
59938 status = musb_host_setup(musb, plat->power);
59939 + if (status < 0)
59940 + goto fail3;
59941 + status = musb_platform_set_mode(musb, MUSB_HOST);
59942 break;
59943 case MUSB_PORT_MODE_GADGET:
59944 status = musb_gadget_setup(musb);
59945 + if (status < 0)
59946 + goto fail3;
59947 + status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
59948 break;
59949 case MUSB_PORT_MODE_DUAL_ROLE:
59950 status = musb_host_setup(musb, plat->power);
59951 if (status < 0)
59952 goto fail3;
59953 status = musb_gadget_setup(musb);
59954 + if (status) {
59955 + musb_host_cleanup(musb);
59956 + goto fail3;
59957 + }
59958 + status = musb_platform_set_mode(musb, MUSB_OTG);
59959 break;
59960 default:
59961 dev_err(dev, "unsupported port mode %d\n", musb->port_mode);
59962 @@ -1972,10 +2017,12 @@ fail5:
59963
59964 fail4:
59965 musb_gadget_cleanup(musb);
59966 + musb_host_cleanup(musb);
59967
59968 fail3:
59969 if (musb->dma_controller)
59970 dma_controller_destroy(musb->dma_controller);
59971 +fail2_5:
59972 pm_runtime_put_sync(musb->controller);
59973
59974 fail2:
59975 @@ -2032,6 +2079,9 @@ static int musb_remove(struct platform_d
59976 musb_exit_debugfs(musb);
59977 musb_shutdown(pdev);
59978
59979 + if (musb->dma_controller)
59980 + dma_controller_destroy(musb->dma_controller);
59981 +
59982 musb_free(musb);
59983 device_init_wakeup(dev, 0);
59984 return 0;
59985 --- a/drivers/usb/musb/musb_core.h
59986 +++ b/drivers/usb/musb/musb_core.h
59987 @@ -46,6 +46,7 @@
59988 #include <linux/usb.h>
59989 #include <linux/usb/otg.h>
59990 #include <linux/usb/musb.h>
59991 +#include <linux/phy/phy.h>
59992
59993 struct musb;
59994 struct musb_hw_ep;
59995 @@ -341,6 +342,7 @@ struct musb {
59996 u16 int_tx;
59997
59998 struct usb_phy *xceiv;
59999 + struct phy *phy;
60000
60001 int nIrq;
60002 unsigned irq_wake:1;
60003 @@ -505,6 +507,9 @@ extern const char musb_driver_name[];
60004 extern void musb_stop(struct musb *musb);
60005 extern void musb_start(struct musb *musb);
60006
60007 +extern int musb_get_id(struct device *dev, gfp_t gfp_mask);
60008 +extern void musb_put_id(struct device *dev, int id);
60009 +
60010 extern void musb_write_fifo(struct musb_hw_ep *ep, u16 len, const u8 *src);
60011 extern void musb_read_fifo(struct musb_hw_ep *ep, u16 len, u8 *dst);
60012
60013 --- a/drivers/usb/musb/musb_cppi41.c
60014 +++ b/drivers/usb/musb/musb_cppi41.c
60015 @@ -484,6 +484,7 @@ static int cppi41_dma_controller_start(s
60016 if (ret)
60017 goto err;
60018
60019 + ret = -EINVAL;
60020 if (port > MUSB_DMA_NUM_CHANNELS || !port)
60021 goto err;
60022 if (is_tx)
60023 @@ -503,6 +504,7 @@ static int cppi41_dma_controller_start(s
60024 dc = dma_request_slave_channel(dev, str);
60025 if (!dc) {
60026 dev_err(dev, "Falied to request %s.\n", str);
60027 + ret = -EPROBE_DEFER;
60028 goto err;
60029 }
60030 cppi41_channel->dc = dc;
60031 @@ -510,7 +512,7 @@ static int cppi41_dma_controller_start(s
60032 return 0;
60033 err:
60034 cppi41_release_all_dma_chans(controller);
60035 - return -EINVAL;
60036 + return ret;
60037 }
60038
60039 void dma_controller_destroy(struct dma_controller *c)
60040 @@ -526,7 +528,7 @@ struct dma_controller *dma_controller_cr
60041 void __iomem *base)
60042 {
60043 struct cppi41_dma_controller *controller;
60044 - int ret;
60045 + int ret = 0;
60046
60047 if (!musb->controller->of_node) {
60048 dev_err(musb->controller, "Need DT for the DMA engine.\n");
60049 @@ -553,5 +555,7 @@ struct dma_controller *dma_controller_cr
60050 plat_get_fail:
60051 kfree(controller);
60052 kzalloc_fail:
60053 + if (ret == -EPROBE_DEFER)
60054 + return ERR_PTR(ret);
60055 return NULL;
60056 }
60057 --- a/drivers/usb/musb/musb_dsps.c
60058 +++ b/drivers/usb/musb/musb_dsps.c
60059 @@ -106,6 +106,7 @@ struct dsps_musb_wrapper {
60060
60061 /* bit positions for mode */
60062 unsigned iddig:5;
60063 + unsigned iddig_mux:5;
60064 /* miscellaneous stuff */
60065 u8 poll_seconds;
60066 };
60067 @@ -121,6 +122,43 @@ struct dsps_glue {
60068 unsigned long last_timer; /* last timer data for each instance */
60069 };
60070
60071 +static void dsps_musb_try_idle(struct musb *musb, unsigned long timeout)
60072 +{
60073 + struct device *dev = musb->controller;
60074 + struct dsps_glue *glue = dev_get_drvdata(dev->parent);
60075 +
60076 + if (timeout == 0)
60077 + timeout = jiffies + msecs_to_jiffies(3);
60078 +
60079 + /* Never idle if active, or when VBUS timeout is not set as host */
60080 + if (musb->is_active || (musb->a_wait_bcon == 0 &&
60081 + musb->xceiv->state == OTG_STATE_A_WAIT_BCON)) {
60082 + dev_dbg(musb->controller, "%s active, deleting timer\n",
60083 + usb_otg_state_string(musb->xceiv->state));
60084 + del_timer(&glue->timer);
60085 + glue->last_timer = jiffies;
60086 + return;
60087 + }
60088 + if (musb->port_mode != MUSB_PORT_MODE_DUAL_ROLE)
60089 + return;
60090 +
60091 + if (!musb->g.dev.driver)
60092 + return;
60093 +
60094 + if (time_after(glue->last_timer, timeout) &&
60095 + timer_pending(&glue->timer)) {
60096 + dev_dbg(musb->controller,
60097 + "Longer idle timer already pending, ignoring...\n");
60098 + return;
60099 + }
60100 + glue->last_timer = timeout;
60101 +
60102 + dev_dbg(musb->controller, "%s inactive, starting idle timer for %u ms\n",
60103 + usb_otg_state_string(musb->xceiv->state),
60104 + jiffies_to_msecs(timeout - jiffies));
60105 + mod_timer(&glue->timer, timeout);
60106 +}
60107 +
60108 /**
60109 * dsps_musb_enable - enable interrupts
60110 */
60111 @@ -143,6 +181,7 @@ static void dsps_musb_enable(struct musb
60112 /* Force the DRVVBUS IRQ so we can start polling for ID change. */
60113 dsps_writel(reg_base, wrp->coreintr_set,
60114 (1 << wrp->drvvbus) << wrp->usb_shift);
60115 + dsps_musb_try_idle(musb, 0);
60116 }
60117
60118 /**
60119 @@ -171,6 +210,7 @@ static void otg_timer(unsigned long _mus
60120 const struct dsps_musb_wrapper *wrp = glue->wrp;
60121 u8 devctl;
60122 unsigned long flags;
60123 + int skip_session = 0;
60124
60125 /*
60126 * We poll because DSPS IP's won't expose several OTG-critical
60127 @@ -183,10 +223,12 @@ static void otg_timer(unsigned long _mus
60128 spin_lock_irqsave(&musb->lock, flags);
60129 switch (musb->xceiv->state) {
60130 case OTG_STATE_A_WAIT_BCON:
60131 - devctl &= ~MUSB_DEVCTL_SESSION;
60132 - dsps_writeb(musb->mregs, MUSB_DEVCTL, devctl);
60133 + dsps_writeb(musb->mregs, MUSB_DEVCTL, 0);
60134 + skip_session = 1;
60135 + /* fall */
60136
60137 - devctl = dsps_readb(musb->mregs, MUSB_DEVCTL);
60138 + case OTG_STATE_A_IDLE:
60139 + case OTG_STATE_B_IDLE:
60140 if (devctl & MUSB_DEVCTL_BDEVICE) {
60141 musb->xceiv->state = OTG_STATE_B_IDLE;
60142 MUSB_DEV_MODE(musb);
60143 @@ -194,60 +236,21 @@ static void otg_timer(unsigned long _mus
60144 musb->xceiv->state = OTG_STATE_A_IDLE;
60145 MUSB_HST_MODE(musb);
60146 }
60147 + if (!(devctl & MUSB_DEVCTL_SESSION) && !skip_session)
60148 + dsps_writeb(mregs, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
60149 + mod_timer(&glue->timer, jiffies + wrp->poll_seconds * HZ);
60150 break;
60151 case OTG_STATE_A_WAIT_VFALL:
60152 musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
60153 dsps_writel(musb->ctrl_base, wrp->coreintr_set,
60154 MUSB_INTR_VBUSERROR << wrp->usb_shift);
60155 break;
60156 - case OTG_STATE_B_IDLE:
60157 - devctl = dsps_readb(mregs, MUSB_DEVCTL);
60158 - if (devctl & MUSB_DEVCTL_BDEVICE)
60159 - mod_timer(&glue->timer,
60160 - jiffies + wrp->poll_seconds * HZ);
60161 - else
60162 - musb->xceiv->state = OTG_STATE_A_IDLE;
60163 - break;
60164 default:
60165 break;
60166 }
60167 spin_unlock_irqrestore(&musb->lock, flags);
60168 }
60169
60170 -static void dsps_musb_try_idle(struct musb *musb, unsigned long timeout)
60171 -{
60172 - struct device *dev = musb->controller;
60173 - struct dsps_glue *glue = dev_get_drvdata(dev->parent);
60174 -
60175 - if (timeout == 0)
60176 - timeout = jiffies + msecs_to_jiffies(3);
60177 -
60178 - /* Never idle if active, or when VBUS timeout is not set as host */
60179 - if (musb->is_active || (musb->a_wait_bcon == 0 &&
60180 - musb->xceiv->state == OTG_STATE_A_WAIT_BCON)) {
60181 - dev_dbg(musb->controller, "%s active, deleting timer\n",
60182 - usb_otg_state_string(musb->xceiv->state));
60183 - del_timer(&glue->timer);
60184 - glue->last_timer = jiffies;
60185 - return;
60186 - }
60187 - if (musb->port_mode == MUSB_PORT_MODE_HOST)
60188 - return;
60189 -
60190 - if (time_after(glue->last_timer, timeout) &&
60191 - timer_pending(&glue->timer)) {
60192 - dev_dbg(musb->controller,
60193 - "Longer idle timer already pending, ignoring...\n");
60194 - return;
60195 - }
60196 - glue->last_timer = timeout;
60197 -
60198 - dev_dbg(musb->controller, "%s inactive, starting idle timer for %u ms\n",
60199 - usb_otg_state_string(musb->xceiv->state),
60200 - jiffies_to_msecs(timeout - jiffies));
60201 - mod_timer(&glue->timer, timeout);
60202 -}
60203 -
60204 static irqreturn_t dsps_interrupt(int irq, void *hci)
60205 {
60206 struct musb *musb = hci;
60207 @@ -404,6 +407,54 @@ static int dsps_musb_exit(struct musb *m
60208 return 0;
60209 }
60210
60211 +static int dsps_musb_set_mode(struct musb *musb, u8 mode)
60212 +{
60213 + struct device *dev = musb->controller;
60214 + struct dsps_glue *glue = dev_get_drvdata(dev->parent);
60215 + const struct dsps_musb_wrapper *wrp = glue->wrp;
60216 + void __iomem *ctrl_base = musb->ctrl_base;
60217 + void __iomem *base = musb->mregs;
60218 + u32 reg;
60219 +
60220 + reg = dsps_readl(base, wrp->mode);
60221 +
60222 + switch (mode) {
60223 + case MUSB_HOST:
60224 + reg &= ~(1 << wrp->iddig);
60225 +
60226 + /*
60227 + * if we're setting mode to host-only or device-only, we're
60228 + * going to ignore whatever the PHY sends us and just force
60229 + * ID pin status by SW
60230 + */
60231 + reg |= (1 << wrp->iddig_mux);
60232 +
60233 + dsps_writel(base, wrp->mode, reg);
60234 + dsps_writel(ctrl_base, wrp->phy_utmi, 0x02);
60235 + break;
60236 + case MUSB_PERIPHERAL:
60237 + reg |= (1 << wrp->iddig);
60238 +
60239 + /*
60240 + * if we're setting mode to host-only or device-only, we're
60241 + * going to ignore whatever the PHY sends us and just force
60242 + * ID pin status by SW
60243 + */
60244 + reg |= (1 << wrp->iddig_mux);
60245 +
60246 + dsps_writel(base, wrp->mode, reg);
60247 + break;
60248 + case MUSB_OTG:
60249 + dsps_writel(base, wrp->phy_utmi, 0x02);
60250 + break;
60251 + default:
60252 + dev_err(glue->dev, "unsupported mode %d\n", mode);
60253 + return -EINVAL;
60254 + }
60255 +
60256 + return 0;
60257 +}
60258 +
60259 static struct musb_platform_ops dsps_ops = {
60260 .init = dsps_musb_init,
60261 .exit = dsps_musb_exit,
60262 @@ -412,6 +463,7 @@ static struct musb_platform_ops dsps_ops
60263 .disable = dsps_musb_disable,
60264
60265 .try_idle = dsps_musb_try_idle,
60266 + .set_mode = dsps_musb_set_mode,
60267 };
60268
60269 static u64 musb_dmamask = DMA_BIT_MASK(32);
60270 @@ -606,6 +658,7 @@ static const struct dsps_musb_wrapper am
60271 .reset = 0,
60272 .otg_disable = 21,
60273 .iddig = 8,
60274 + .iddig_mux = 7,
60275 .usb_shift = 0,
60276 .usb_mask = 0x1ff,
60277 .usb_bitmap = (0x1ff << 0),
60278 @@ -631,7 +684,7 @@ static struct platform_driver dsps_usbss
60279 .remove = dsps_remove,
60280 .driver = {
60281 .name = "musb-dsps",
60282 - .of_match_table = of_match_ptr(musb_dsps_of_match),
60283 + .of_match_table = musb_dsps_of_match,
60284 },
60285 };
60286
60287 --- a/drivers/usb/musb/musb_virthub.c
60288 +++ b/drivers/usb/musb/musb_virthub.c
60289 @@ -220,6 +220,23 @@ int musb_hub_status_data(struct usb_hcd
60290 return retval;
60291 }
60292
60293 +static int musb_has_gadget(struct musb *musb)
60294 +{
60295 + /*
60296 + * In host-only mode we start a connection right away. In OTG mode
60297 + * we have to wait until we loaded a gadget. We don't really need a
60298 + * gadget if we operate as a host but we should not start a session
60299 + * as a device without a gadget or else we explode.
60300 + */
60301 +#ifdef CONFIG_USB_MUSB_HOST
60302 + return 1;
60303 +#else
60304 + if (musb->port_mode == MUSB_PORT_MODE_HOST)
60305 + return 1;
60306 + return musb->g.dev.driver != NULL;
60307 +#endif
60308 +}
60309 +
60310 int musb_hub_control(
60311 struct usb_hcd *hcd,
60312 u16 typeReq,
60313 @@ -362,7 +379,7 @@ int musb_hub_control(
60314 * initialization logic, e.g. for OTG, or change any
60315 * logic relating to VBUS power-up.
60316 */
60317 - if (!hcd->self.is_b_host)
60318 + if (!hcd->self.is_b_host && musb_has_gadget(musb))
60319 musb_start(musb);
60320 break;
60321 case USB_PORT_FEAT_RESET:
60322 --- a/drivers/usb/musb/omap2430.c
60323 +++ b/drivers/usb/musb/omap2430.c
60324 @@ -37,7 +37,8 @@
60325 #include <linux/err.h>
60326 #include <linux/delay.h>
60327 #include <linux/usb/musb-omap.h>
60328 -#include <linux/usb/omap_control_usb.h>
60329 +#include <linux/phy/omap_control_phy.h>
60330 +#include <linux/of_platform.h>
60331
60332 #include "musb_core.h"
60333 #include "omap2430.h"
60334 @@ -305,6 +306,9 @@ static void omap_musb_set_mailbox(struct
60335 default:
60336 dev_dbg(dev, "ID float\n");
60337 }
60338 +
60339 + atomic_notifier_call_chain(&musb->xceiv->notifier,
60340 + musb->xceiv->last_event, NULL);
60341 }
60342
60343
60344 @@ -348,11 +352,21 @@ static int omap2430_musb_init(struct mus
60345 * up through ULPI. TWL4030-family PMICs include one,
60346 * which needs a driver, drivers aren't always needed.
60347 */
60348 - if (dev->parent->of_node)
60349 + if (dev->parent->of_node) {
60350 + musb->phy = devm_phy_get(dev->parent, "usb2-phy");
60351 +
60352 + /* We can't totally remove musb->xceiv as of now because
60353 + * musb core uses xceiv.state and xceiv.otg. Once we have
60354 + * a separate state machine to handle otg, these can be moved
60355 + * out of xceiv and then we can start using the generic PHY
60356 + * framework
60357 + */
60358 musb->xceiv = devm_usb_get_phy_by_phandle(dev->parent,
60359 "usb-phy", 0);
60360 - else
60361 + } else {
60362 musb->xceiv = devm_usb_get_phy_dev(dev, 0);
60363 + musb->phy = devm_phy_get(dev, "usb");
60364 + }
60365
60366 if (IS_ERR(musb->xceiv)) {
60367 status = PTR_ERR(musb->xceiv);
60368 @@ -364,6 +378,10 @@ static int omap2430_musb_init(struct mus
60369 return -EPROBE_DEFER;
60370 }
60371
60372 + if (IS_ERR(musb->phy)) {
60373 + pr_err("HS USB OTG: no PHY configured\n");
60374 + return PTR_ERR(musb->phy);
60375 + }
60376 musb->isr = omap2430_musb_interrupt;
60377
60378 status = pm_runtime_get_sync(dev);
60379 @@ -397,7 +415,7 @@ static int omap2430_musb_init(struct mus
60380 if (glue->status != OMAP_MUSB_UNKNOWN)
60381 omap_musb_set_mailbox(glue);
60382
60383 - usb_phy_init(musb->xceiv);
60384 + phy_init(musb->phy);
60385
60386 pm_runtime_put_noidle(musb->controller);
60387 return 0;
60388 @@ -460,6 +478,7 @@ static int omap2430_musb_exit(struct mus
60389 del_timer_sync(&musb_idle_timer);
60390
60391 omap2430_low_level_exit(musb);
60392 + phy_exit(musb->phy);
60393
60394 return 0;
60395 }
60396 @@ -489,6 +508,7 @@ static int omap2430_probe(struct platfor
60397 struct device_node *np = pdev->dev.of_node;
60398 struct musb_hdrc_config *config;
60399 int ret = -ENOMEM;
60400 + int musbid;
60401
60402 glue = devm_kzalloc(&pdev->dev, sizeof(*glue), GFP_KERNEL);
60403 if (!glue) {
60404 @@ -496,10 +516,18 @@ static int omap2430_probe(struct platfor
60405 goto err0;
60406 }
60407
60408 - musb = platform_device_alloc("musb-hdrc", PLATFORM_DEVID_AUTO);
60409 + /* get the musb id */
60410 + musbid = musb_get_id(&pdev->dev, GFP_KERNEL);
60411 + if (musbid < 0) {
60412 + dev_err(&pdev->dev, "failed to allocate musb id\n");
60413 + ret = -ENOMEM;
60414 + goto err0;
60415 + }
60416 +
60417 + musb = platform_device_alloc("musb-hdrc", musbid);
60418 if (!musb) {
60419 dev_err(&pdev->dev, "failed to allocate musb device\n");
60420 - goto err0;
60421 + goto err1;
60422 }
60423
60424 musb->dev.parent = &pdev->dev;
60425 @@ -509,8 +537,12 @@ static int omap2430_probe(struct platfor
60426 glue->dev = &pdev->dev;
60427 glue->musb = musb;
60428 glue->status = OMAP_MUSB_UNKNOWN;
60429 + glue->control_otghs = ERR_PTR(-ENODEV);
60430
60431 if (np) {
60432 + struct device_node *control_node;
60433 + struct platform_device *control_pdev;
60434 +
60435 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
60436 if (!pdata) {
60437 dev_err(&pdev->dev,
60438 @@ -539,22 +571,20 @@ static int omap2430_probe(struct platfor
60439 of_property_read_u32(np, "ram-bits", (u32 *)&config->ram_bits);
60440 of_property_read_u32(np, "power", (u32 *)&pdata->power);
60441 config->multipoint = of_property_read_bool(np, "multipoint");
60442 - pdata->has_mailbox = of_property_read_bool(np,
60443 - "ti,has-mailbox");
60444
60445 pdata->board_data = data;
60446 pdata->config = config;
60447 - }
60448
60449 - if (pdata->has_mailbox) {
60450 - glue->control_otghs = omap_get_control_dev();
60451 - if (IS_ERR(glue->control_otghs)) {
60452 - dev_vdbg(&pdev->dev, "Failed to get control device\n");
60453 - ret = PTR_ERR(glue->control_otghs);
60454 - goto err2;
60455 + control_node = of_parse_phandle(np, "ctrl-module", 0);
60456 + if (control_node) {
60457 + control_pdev = of_find_device_by_node(control_node);
60458 + if (!control_pdev) {
60459 + dev_err(&pdev->dev, "Failed to get control device\n");
60460 + ret = -EINVAL;
60461 + goto err2;
60462 + }
60463 + glue->control_otghs = &control_pdev->dev;
60464 }
60465 - } else {
60466 - glue->control_otghs = ERR_PTR(-ENODEV);
60467 }
60468 pdata->platform_ops = &omap2430_ops;
60469
60470 @@ -612,6 +642,9 @@ static int omap2430_probe(struct platfor
60471 err2:
60472 platform_device_put(musb);
60473
60474 +err1:
60475 + musb_put_id(&pdev->dev, musbid);
60476 +
60477 err0:
60478 return ret;
60479 }
60480 @@ -638,7 +671,7 @@ static int omap2430_runtime_suspend(stru
60481 OTG_INTERFSEL);
60482
60483 omap2430_low_level_exit(musb);
60484 - usb_phy_set_suspend(musb->xceiv, 1);
60485 + phy_power_off(musb->phy);
60486 }
60487
60488 return 0;
60489 @@ -653,8 +686,7 @@ static int omap2430_runtime_resume(struc
60490 omap2430_low_level_init(musb);
60491 musb_writel(musb->mregs, OTG_INTERFSEL,
60492 musb->context.otg_interfsel);
60493 -
60494 - usb_phy_set_suspend(musb->xceiv, 0);
60495 + phy_power_on(musb->phy);
60496 }
60497
60498 return 0;
60499 --- a/drivers/usb/musb/tusb6010.c
60500 +++ b/drivers/usb/musb/tusb6010.c
60501 @@ -1152,7 +1152,11 @@ static const struct musb_platform_ops tu
60502 .set_vbus = tusb_musb_set_vbus,
60503 };
60504
60505 -static u64 tusb_dmamask = DMA_BIT_MASK(32);
60506 +static const struct platform_device_info tusb_dev_info = {
60507 + .name = "musb-hdrc",
60508 + .id = PLATFORM_DEVID_AUTO,
60509 + .dma_mask = DMA_BIT_MASK(32),
60510 +};
60511
60512 static int tusb_probe(struct platform_device *pdev)
60513 {
60514 @@ -1160,7 +1164,7 @@ static int tusb_probe(struct platform_de
60515 struct musb_hdrc_platform_data *pdata = dev_get_platdata(&pdev->dev);
60516 struct platform_device *musb;
60517 struct tusb6010_glue *glue;
60518 -
60519 + struct platform_device_info pinfo;
60520 int ret = -ENOMEM;
60521
60522 glue = kzalloc(sizeof(*glue), GFP_KERNEL);
60523 @@ -1169,18 +1173,7 @@ static int tusb_probe(struct platform_de
60524 goto err0;
60525 }
60526
60527 - musb = platform_device_alloc("musb-hdrc", PLATFORM_DEVID_AUTO);
60528 - if (!musb) {
60529 - dev_err(&pdev->dev, "failed to allocate musb device\n");
60530 - goto err1;
60531 - }
60532 -
60533 - musb->dev.parent = &pdev->dev;
60534 - musb->dev.dma_mask = &tusb_dmamask;
60535 - musb->dev.coherent_dma_mask = tusb_dmamask;
60536 -
60537 glue->dev = &pdev->dev;
60538 - glue->musb = musb;
60539
60540 pdata->platform_ops = &tusb_ops;
60541
60542 @@ -1204,31 +1197,23 @@ static int tusb_probe(struct platform_de
60543 musb_resources[2].end = pdev->resource[2].end;
60544 musb_resources[2].flags = pdev->resource[2].flags;
60545
60546 - ret = platform_device_add_resources(musb, musb_resources,
60547 - ARRAY_SIZE(musb_resources));
60548 - if (ret) {
60549 - dev_err(&pdev->dev, "failed to add resources\n");
60550 - goto err3;
60551 - }
60552 -
60553 - ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
60554 - if (ret) {
60555 - dev_err(&pdev->dev, "failed to add platform_data\n");
60556 - goto err3;
60557 - }
60558 -
60559 - ret = platform_device_add(musb);
60560 - if (ret) {
60561 - dev_err(&pdev->dev, "failed to register musb device\n");
60562 + pinfo = tusb_dev_info;
60563 + pinfo.parent = &pdev->dev;
60564 + pinfo.res = musb_resources;
60565 + pinfo.num_res = ARRAY_SIZE(musb_resources);
60566 + pinfo.data = pdata;
60567 + pinfo.size_data = sizeof(*pdata);
60568 +
60569 + glue->musb = musb = platform_device_register_full(&pinfo);
60570 + if (IS_ERR(musb)) {
60571 + ret = PTR_ERR(musb);
60572 + dev_err(&pdev->dev, "failed to register musb device: %d\n", ret);
60573 goto err3;
60574 }
60575
60576 return 0;
60577
60578 err3:
60579 - platform_device_put(musb);
60580 -
60581 -err1:
60582 kfree(glue);
60583
60584 err0:
60585 --- a/drivers/usb/musb/ux500.c
60586 +++ b/drivers/usb/musb/ux500.c
60587 @@ -376,17 +376,10 @@ static int ux500_resume(struct device *d
60588
60589 return 0;
60590 }
60591 -
60592 -static const struct dev_pm_ops ux500_pm_ops = {
60593 - .suspend = ux500_suspend,
60594 - .resume = ux500_resume,
60595 -};
60596 -
60597 -#define DEV_PM_OPS (&ux500_pm_ops)
60598 -#else
60599 -#define DEV_PM_OPS NULL
60600 #endif
60601
60602 +static SIMPLE_DEV_PM_OPS(ux500_pm_ops, ux500_suspend, ux500_resume);
60603 +
60604 static const struct of_device_id ux500_match[] = {
60605 { .compatible = "stericsson,db8500-musb", },
60606 {}
60607 @@ -397,7 +390,7 @@ static struct platform_driver ux500_driv
60608 .remove = ux500_remove,
60609 .driver = {
60610 .name = "musb-ux500",
60611 - .pm = DEV_PM_OPS,
60612 + .pm = &ux500_pm_ops,
60613 .of_match_table = ux500_match,
60614 },
60615 };
60616 --- a/drivers/usb/phy/Kconfig
60617 +++ b/drivers/usb/phy/Kconfig
60618 @@ -56,38 +56,6 @@ config NOP_USB_XCEIV
60619 built-in with usb ip or which are autonomous and doesn't require any
60620 phy programming such as ISP1x04 etc.
60621
60622 -config OMAP_CONTROL_USB
60623 - tristate "OMAP CONTROL USB Driver"
60624 - depends on ARCH_OMAP2PLUS || COMPILE_TEST
60625 - help
60626 - Enable this to add support for the USB part present in the control
60627 - module. This driver has API to power on the USB2 PHY and to write to
60628 - the mailbox. The mailbox is present only in omap4 and the register to
60629 - power on the USB2 PHY is present in OMAP4 and OMAP5. OMAP5 has an
60630 - additional register to power on USB3 PHY.
60631 -
60632 -config OMAP_USB2
60633 - tristate "OMAP USB2 PHY Driver"
60634 - depends on ARCH_OMAP2PLUS
60635 - select OMAP_CONTROL_USB
60636 - select USB_PHY
60637 - help
60638 - Enable this to support the transceiver that is part of SOC. This
60639 - driver takes care of all the PHY functionality apart from comparator.
60640 - The USB OTG controller communicates with the comparator using this
60641 - driver.
60642 -
60643 -config OMAP_USB3
60644 - tristate "OMAP USB3 PHY Driver"
60645 - depends on ARCH_OMAP2PLUS || COMPILE_TEST
60646 - select OMAP_CONTROL_USB
60647 - select USB_PHY
60648 - help
60649 - Enable this to support the USB3 PHY that is part of SOC. This
60650 - driver takes care of all the PHY functionality apart from comparator.
60651 - This driver interacts with the "OMAP Control USB Driver" to power
60652 - on/off the PHY.
60653 -
60654 config AM335X_CONTROL_USB
60655 tristate
60656
60657 @@ -123,16 +91,6 @@ config SAMSUNG_USB3PHY
60658 Enable this to support Samsung USB 3.0 (Super Speed) phy controller
60659 for samsung SoCs.
60660
60661 -config TWL4030_USB
60662 - tristate "TWL4030 USB Transceiver Driver"
60663 - depends on TWL4030_CORE && REGULATOR_TWL4030 && USB_MUSB_OMAP2PLUS
60664 - select USB_PHY
60665 - help
60666 - Enable this to support the USB OTG transceiver on TWL4030
60667 - family chips (including the TWL5030 and TPS659x0 devices).
60668 - This transceiver supports high and full speed devices plus,
60669 - in host mode, low speed.
60670 -
60671 config TWL6030_USB
60672 tristate "TWL6030 USB Transceiver Driver"
60673 depends on TWL4030_CORE && OMAP_USB2 && USB_MUSB_OMAP2PLUS
60674 @@ -214,6 +172,19 @@ config USB_RCAR_PHY
60675 To compile this driver as a module, choose M here: the
60676 module will be called phy-rcar-usb.
60677
60678 +config USB_RCAR_GEN2_PHY
60679 + tristate "Renesas R-Car Gen2 USB PHY support"
60680 + depends on ARCH_R8A7790 || ARCH_R8A7791 || COMPILE_TEST
60681 + select USB_PHY
60682 + help
60683 + Say Y here to add support for the Renesas R-Car Gen2 USB PHY driver.
60684 + It is typically used to control internal USB PHY for USBHS,
60685 + and to configure shared USB channels 0 and 2.
60686 + This driver supports R8A7790 and R8A7791.
60687 +
60688 + To compile this driver as a module, choose M here: the
60689 + module will be called phy-rcar-gen2-usb.
60690 +
60691 config USB_ULPI
60692 bool "Generic ULPI Transceiver Driver"
60693 depends on ARM
60694 --- a/drivers/usb/phy/Makefile
60695 +++ b/drivers/usb/phy/Makefile
60696 @@ -12,15 +12,11 @@ obj-$(CONFIG_FSL_USB2_OTG) += phy-fsl-u
60697 obj-$(CONFIG_ISP1301_OMAP) += phy-isp1301-omap.o
60698 obj-$(CONFIG_MV_U3D_PHY) += phy-mv-u3d-usb.o
60699 obj-$(CONFIG_NOP_USB_XCEIV) += phy-generic.o
60700 -obj-$(CONFIG_OMAP_CONTROL_USB) += phy-omap-control.o
60701 obj-$(CONFIG_AM335X_CONTROL_USB) += phy-am335x-control.o
60702 obj-$(CONFIG_AM335X_PHY_USB) += phy-am335x.o
60703 -obj-$(CONFIG_OMAP_USB2) += phy-omap-usb2.o
60704 -obj-$(CONFIG_OMAP_USB3) += phy-omap-usb3.o
60705 obj-$(CONFIG_SAMSUNG_USBPHY) += phy-samsung-usb.o
60706 obj-$(CONFIG_SAMSUNG_USB2PHY) += phy-samsung-usb2.o
60707 obj-$(CONFIG_SAMSUNG_USB3PHY) += phy-samsung-usb3.o
60708 -obj-$(CONFIG_TWL4030_USB) += phy-twl4030-usb.o
60709 obj-$(CONFIG_TWL6030_USB) += phy-twl6030-usb.o
60710 obj-$(CONFIG_USB_EHCI_TEGRA) += phy-tegra-usb.o
60711 obj-$(CONFIG_USB_GPIO_VBUS) += phy-gpio-vbus-usb.o
60712 @@ -29,5 +25,6 @@ obj-$(CONFIG_USB_MSM_OTG) += phy-msm-us
60713 obj-$(CONFIG_USB_MV_OTG) += phy-mv-usb.o
60714 obj-$(CONFIG_USB_MXS_PHY) += phy-mxs-usb.o
60715 obj-$(CONFIG_USB_RCAR_PHY) += phy-rcar-usb.o
60716 +obj-$(CONFIG_USB_RCAR_GEN2_PHY) += phy-rcar-gen2-usb.o
60717 obj-$(CONFIG_USB_ULPI) += phy-ulpi.o
60718 obj-$(CONFIG_USB_ULPI_VIEWPORT) += phy-ulpi-viewport.o
60719 --- a/drivers/usb/phy/phy-am335x.c
60720 +++ b/drivers/usb/phy/phy-am335x.c
60721 @@ -52,23 +52,19 @@ static int am335x_phy_probe(struct platf
60722 return am_phy->id;
60723 }
60724
60725 - ret = usb_phy_gen_create_phy(dev, &am_phy->usb_phy_gen,
60726 - USB_PHY_TYPE_USB2, 0, false, false);
60727 + ret = usb_phy_gen_create_phy(dev, &am_phy->usb_phy_gen, NULL);
60728 if (ret)
60729 return ret;
60730
60731 ret = usb_add_phy_dev(&am_phy->usb_phy_gen.phy);
60732 if (ret)
60733 - goto err_add;
60734 + return ret;
60735 am_phy->usb_phy_gen.phy.init = am335x_init;
60736 am_phy->usb_phy_gen.phy.shutdown = am335x_shutdown;
60737
60738 platform_set_drvdata(pdev, am_phy);
60739 - return 0;
60740
60741 -err_add:
60742 - usb_phy_gen_cleanup_phy(&am_phy->usb_phy_gen);
60743 - return ret;
60744 + return 0;
60745 }
60746
60747 static int am335x_phy_remove(struct platform_device *pdev)
60748 @@ -79,6 +75,40 @@ static int am335x_phy_remove(struct plat
60749 return 0;
60750 }
60751
60752 +#ifdef CONFIG_PM_RUNTIME
60753 +
60754 +static int am335x_phy_runtime_suspend(struct device *dev)
60755 +{
60756 + struct platform_device *pdev = to_platform_device(dev);
60757 + struct am335x_phy *am_phy = platform_get_drvdata(pdev);
60758 +
60759 + if (device_may_wakeup(dev))
60760 + phy_ctrl_wkup(am_phy->phy_ctrl, am_phy->id, true);
60761 + phy_ctrl_power(am_phy->phy_ctrl, am_phy->id, false);
60762 + return 0;
60763 +}
60764 +
60765 +static int am335x_phy_runtime_resume(struct device *dev)
60766 +{
60767 + struct platform_device *pdev = to_platform_device(dev);
60768 + struct am335x_phy *am_phy = platform_get_drvdata(pdev);
60769 +
60770 + phy_ctrl_power(am_phy->phy_ctrl, am_phy->id, true);
60771 + if (device_may_wakeup(dev))
60772 + phy_ctrl_wkup(am_phy->phy_ctrl, am_phy->id, false);
60773 + return 0;
60774 +}
60775 +
60776 +static const struct dev_pm_ops am335x_pm_ops = {
60777 + SET_RUNTIME_PM_OPS(am335x_phy_runtime_suspend,
60778 + am335x_phy_runtime_resume, NULL)
60779 +};
60780 +
60781 +#define DEV_PM_OPS (&am335x_pm_ops)
60782 +#else
60783 +#define DEV_PM_OPS NULL
60784 +#endif
60785 +
60786 static const struct of_device_id am335x_phy_ids[] = {
60787 { .compatible = "ti,am335x-usb-phy" },
60788 { }
60789 @@ -91,7 +121,8 @@ static struct platform_driver am335x_phy
60790 .driver = {
60791 .name = "am335x-phy-driver",
60792 .owner = THIS_MODULE,
60793 - .of_match_table = of_match_ptr(am335x_phy_ids),
60794 + .pm = DEV_PM_OPS,
60795 + .of_match_table = am335x_phy_ids,
60796 },
60797 };
60798
60799 --- a/drivers/usb/phy/phy-am335x-control.c
60800 +++ b/drivers/usb/phy/phy-am335x-control.c
60801 @@ -26,6 +26,41 @@ struct am335x_control_usb {
60802 #define USBPHY_OTGVDET_EN (1 << 19)
60803 #define USBPHY_OTGSESSEND_EN (1 << 20)
60804
60805 +#define AM335X_PHY0_WK_EN (1 << 0)
60806 +#define AM335X_PHY1_WK_EN (1 << 8)
60807 +
60808 +static void am335x_phy_wkup(struct phy_control *phy_ctrl, u32 id, bool on)
60809 +{
60810 + struct am335x_control_usb *usb_ctrl;
60811 + u32 val;
60812 + u32 reg;
60813 +
60814 + usb_ctrl = container_of(phy_ctrl, struct am335x_control_usb, phy_ctrl);
60815 +
60816 + switch (id) {
60817 + case 0:
60818 + reg = AM335X_PHY0_WK_EN;
60819 + break;
60820 + case 1:
60821 + reg = AM335X_PHY1_WK_EN;
60822 + break;
60823 + default:
60824 + WARN_ON(1);
60825 + return;
60826 + }
60827 +
60828 + spin_lock(&usb_ctrl->lock);
60829 + val = readl(usb_ctrl->wkup);
60830 +
60831 + if (on)
60832 + val |= reg;
60833 + else
60834 + val &= ~reg;
60835 +
60836 + writel(val, usb_ctrl->wkup);
60837 + spin_unlock(&usb_ctrl->lock);
60838 +}
60839 +
60840 static void am335x_phy_power(struct phy_control *phy_ctrl, u32 id, bool on)
60841 {
60842 struct am335x_control_usb *usb_ctrl;
60843 @@ -59,6 +94,7 @@ static void am335x_phy_power(struct phy_
60844
60845 static const struct phy_control ctrl_am335x = {
60846 .phy_power = am335x_phy_power,
60847 + .phy_wkup = am335x_phy_wkup,
60848 };
60849
60850 static const struct of_device_id omap_control_usb_id_table[] = {
60851 @@ -117,6 +153,12 @@ static int am335x_control_usb_probe(stru
60852 ctrl_usb->phy_reg = devm_ioremap_resource(&pdev->dev, res);
60853 if (IS_ERR(ctrl_usb->phy_reg))
60854 return PTR_ERR(ctrl_usb->phy_reg);
60855 +
60856 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "wakeup");
60857 + ctrl_usb->wkup = devm_ioremap_resource(&pdev->dev, res);
60858 + if (IS_ERR(ctrl_usb->wkup))
60859 + return PTR_ERR(ctrl_usb->wkup);
60860 +
60861 spin_lock_init(&ctrl_usb->lock);
60862 ctrl_usb->phy_ctrl = *phy_ctrl;
60863
60864 @@ -129,7 +171,7 @@ static struct platform_driver am335x_con
60865 .driver = {
60866 .name = "am335x-control-usb",
60867 .owner = THIS_MODULE,
60868 - .of_match_table = of_match_ptr(omap_control_usb_id_table),
60869 + .of_match_table = omap_control_usb_id_table,
60870 },
60871 };
60872
60873 --- a/drivers/usb/phy/phy.c
60874 +++ b/drivers/usb/phy/phy.c
60875 @@ -98,7 +98,7 @@ struct usb_phy *devm_usb_get_phy(struct
60876
60877 ptr = devres_alloc(devm_usb_phy_release, sizeof(*ptr), GFP_KERNEL);
60878 if (!ptr)
60879 - return NULL;
60880 + return ERR_PTR(-ENOMEM);
60881
60882 phy = usb_get_phy(type);
60883 if (!IS_ERR(phy)) {
60884 --- a/drivers/usb/phy/phy-fsl-usb.c
60885 +++ b/drivers/usb/phy/phy-fsl-usb.c
60886 @@ -134,7 +134,7 @@ int write_ulpi(u8 addr, u8 data)
60887 /* Operations that will be called from OTG Finite State Machine */
60888
60889 /* Charge vbus for vbus pulsing in SRP */
60890 -void fsl_otg_chrg_vbus(int on)
60891 +void fsl_otg_chrg_vbus(struct otg_fsm *fsm, int on)
60892 {
60893 u32 tmp;
60894
60895 @@ -170,7 +170,7 @@ void fsl_otg_dischrg_vbus(int on)
60896 }
60897
60898 /* A-device driver vbus, controlled through PP bit in PORTSC */
60899 -void fsl_otg_drv_vbus(int on)
60900 +void fsl_otg_drv_vbus(struct otg_fsm *fsm, int on)
60901 {
60902 u32 tmp;
60903
60904 @@ -188,7 +188,7 @@ void fsl_otg_drv_vbus(int on)
60905 * Pull-up D+, signalling connect by periperal. Also used in
60906 * data-line pulsing in SRP
60907 */
60908 -void fsl_otg_loc_conn(int on)
60909 +void fsl_otg_loc_conn(struct otg_fsm *fsm, int on)
60910 {
60911 u32 tmp;
60912
60913 @@ -207,7 +207,7 @@ void fsl_otg_loc_conn(int on)
60914 * port. In host mode, controller will automatically send SOF.
60915 * Suspend will block the data on the port.
60916 */
60917 -void fsl_otg_loc_sof(int on)
60918 +void fsl_otg_loc_sof(struct otg_fsm *fsm, int on)
60919 {
60920 u32 tmp;
60921
60922 @@ -222,7 +222,7 @@ void fsl_otg_loc_sof(int on)
60923 }
60924
60925 /* Start SRP pulsing by data-line pulsing, followed with v-bus pulsing. */
60926 -void fsl_otg_start_pulse(void)
60927 +void fsl_otg_start_pulse(struct otg_fsm *fsm)
60928 {
60929 u32 tmp;
60930
60931 @@ -235,7 +235,7 @@ void fsl_otg_start_pulse(void)
60932 fsl_otg_loc_conn(1);
60933 #endif
60934
60935 - fsl_otg_add_timer(b_data_pulse_tmr);
60936 + fsl_otg_add_timer(fsm, b_data_pulse_tmr);
60937 }
60938
60939 void b_data_pulse_end(unsigned long foo)
60940 @@ -252,14 +252,14 @@ void b_data_pulse_end(unsigned long foo)
60941 void fsl_otg_pulse_vbus(void)
60942 {
60943 srp_wait_done = 0;
60944 - fsl_otg_chrg_vbus(1);
60945 + fsl_otg_chrg_vbus(&fsl_otg_dev->fsm, 1);
60946 /* start the timer to end vbus charge */
60947 - fsl_otg_add_timer(b_vbus_pulse_tmr);
60948 + fsl_otg_add_timer(&fsl_otg_dev->fsm, b_vbus_pulse_tmr);
60949 }
60950
60951 void b_vbus_pulse_end(unsigned long foo)
60952 {
60953 - fsl_otg_chrg_vbus(0);
60954 + fsl_otg_chrg_vbus(&fsl_otg_dev->fsm, 0);
60955
60956 /*
60957 * As USB3300 using the same a_sess_vld and b_sess_vld voltage
60958 @@ -267,7 +267,7 @@ void b_vbus_pulse_end(unsigned long foo)
60959 * residual voltage of vbus pulsing and A device pull up
60960 */
60961 fsl_otg_dischrg_vbus(1);
60962 - fsl_otg_add_timer(b_srp_wait_tmr);
60963 + fsl_otg_add_timer(&fsl_otg_dev->fsm, b_srp_wait_tmr);
60964 }
60965
60966 void b_srp_end(unsigned long foo)
60967 @@ -289,7 +289,7 @@ void a_wait_enum(unsigned long foo)
60968 {
60969 VDBG("a_wait_enum timeout\n");
60970 if (!fsl_otg_dev->phy.otg->host->b_hnp_enable)
60971 - fsl_otg_add_timer(a_wait_enum_tmr);
60972 + fsl_otg_add_timer(&fsl_otg_dev->fsm, a_wait_enum_tmr);
60973 else
60974 otg_statemachine(&fsl_otg_dev->fsm);
60975 }
60976 @@ -375,8 +375,42 @@ void fsl_otg_uninit_timers(void)
60977 kfree(b_vbus_pulse_tmr);
60978 }
60979
60980 +static struct fsl_otg_timer *fsl_otg_get_timer(enum otg_fsm_timer t)
60981 +{
60982 + struct fsl_otg_timer *timer;
60983 +
60984 + /* REVISIT: use array of pointers to timers instead */
60985 + switch (t) {
60986 + case A_WAIT_VRISE:
60987 + timer = a_wait_vrise_tmr;
60988 + break;
60989 + case A_WAIT_BCON:
60990 + timer = a_wait_vrise_tmr;
60991 + break;
60992 + case A_AIDL_BDIS:
60993 + timer = a_wait_vrise_tmr;
60994 + break;
60995 + case B_ASE0_BRST:
60996 + timer = a_wait_vrise_tmr;
60997 + break;
60998 + case B_SE0_SRP:
60999 + timer = a_wait_vrise_tmr;
61000 + break;
61001 + case B_SRP_FAIL:
61002 + timer = a_wait_vrise_tmr;
61003 + break;
61004 + case A_WAIT_ENUM:
61005 + timer = a_wait_vrise_tmr;
61006 + break;
61007 + default:
61008 + timer = NULL;
61009 + }
61010 +
61011 + return timer;
61012 +}
61013 +
61014 /* Add timer to timer list */
61015 -void fsl_otg_add_timer(void *gtimer)
61016 +void fsl_otg_add_timer(struct otg_fsm *fsm, void *gtimer)
61017 {
61018 struct fsl_otg_timer *timer = gtimer;
61019 struct fsl_otg_timer *tmp_timer;
61020 @@ -394,8 +428,19 @@ void fsl_otg_add_timer(void *gtimer)
61021 list_add_tail(&timer->list, &active_timers);
61022 }
61023
61024 +static void fsl_otg_fsm_add_timer(struct otg_fsm *fsm, enum otg_fsm_timer t)
61025 +{
61026 + struct fsl_otg_timer *timer;
61027 +
61028 + timer = fsl_otg_get_timer(t);
61029 + if (!timer)
61030 + return;
61031 +
61032 + fsl_otg_add_timer(fsm, timer);
61033 +}
61034 +
61035 /* Remove timer from the timer list; clear timeout status */
61036 -void fsl_otg_del_timer(void *gtimer)
61037 +void fsl_otg_del_timer(struct otg_fsm *fsm, void *gtimer)
61038 {
61039 struct fsl_otg_timer *timer = gtimer;
61040 struct fsl_otg_timer *tmp_timer, *del_tmp;
61041 @@ -405,6 +450,17 @@ void fsl_otg_del_timer(void *gtimer)
61042 list_del(&timer->list);
61043 }
61044
61045 +static void fsl_otg_fsm_del_timer(struct otg_fsm *fsm, enum otg_fsm_timer t)
61046 +{
61047 + struct fsl_otg_timer *timer;
61048 +
61049 + timer = fsl_otg_get_timer(t);
61050 + if (!timer)
61051 + return;
61052 +
61053 + fsl_otg_del_timer(fsm, timer);
61054 +}
61055 +
61056 /*
61057 * Reduce timer count by 1, and find timeout conditions.
61058 * Called by fsl_otg 1ms timer interrupt
61059 @@ -468,7 +524,7 @@ int fsl_otg_start_host(struct otg_fsm *f
61060 retval = dev->driver->pm->resume(dev);
61061 if (fsm->id) {
61062 /* default-b */
61063 - fsl_otg_drv_vbus(1);
61064 + fsl_otg_drv_vbus(fsm, 1);
61065 /*
61066 * Workaround: b_host can't driver
61067 * vbus, but PP in PORTSC needs to
61068 @@ -493,7 +549,7 @@ int fsl_otg_start_host(struct otg_fsm *f
61069 retval = dev->driver->pm->suspend(dev);
61070 if (fsm->id)
61071 /* default-b */
61072 - fsl_otg_drv_vbus(0);
61073 + fsl_otg_drv_vbus(fsm, 0);
61074 }
61075 otg_dev->host_working = 0;
61076 }
61077 @@ -757,8 +813,8 @@ static struct otg_fsm_ops fsl_otg_ops =
61078 .loc_sof = fsl_otg_loc_sof,
61079 .start_pulse = fsl_otg_start_pulse,
61080
61081 - .add_timer = fsl_otg_add_timer,
61082 - .del_timer = fsl_otg_del_timer,
61083 + .add_timer = fsl_otg_fsm_add_timer,
61084 + .del_timer = fsl_otg_fsm_del_timer,
61085
61086 .start_host = fsl_otg_start_host,
61087 .start_gadget = fsl_otg_start_gadget,
61088 @@ -1011,7 +1067,7 @@ static int show_fsl_usb2_otg_state(struc
61089 "b_bus_suspend: %d\n"
61090 "b_conn: %d\n"
61091 "b_se0_srp: %d\n"
61092 - "b_sess_end: %d\n"
61093 + "b_ssend_srp: %d\n"
61094 "b_sess_vld: %d\n"
61095 "id: %d\n",
61096 fsm->a_bus_req,
61097 @@ -1026,7 +1082,7 @@ static int show_fsl_usb2_otg_state(struc
61098 fsm->b_bus_suspend,
61099 fsm->b_conn,
61100 fsm->b_se0_srp,
61101 - fsm->b_sess_end,
61102 + fsm->b_ssend_srp,
61103 fsm->b_sess_vld,
61104 fsm->id);
61105 size -= t;
61106 @@ -1057,7 +1113,7 @@ static long fsl_otg_ioctl(struct file *f
61107 break;
61108
61109 case SET_A_SUSPEND_REQ:
61110 - fsl_otg_dev->fsm.a_suspend_req = arg;
61111 + fsl_otg_dev->fsm.a_suspend_req_inf = arg;
61112 break;
61113
61114 case SET_A_BUS_DROP:
61115 --- a/drivers/usb/phy/phy-fsl-usb.h
61116 +++ b/drivers/usb/phy/phy-fsl-usb.h
61117 @@ -401,6 +401,6 @@ struct fsl_otg_config {
61118 #define GET_A_BUS_REQ _IOR(OTG_IOCTL_MAGIC, 8, int)
61119 #define GET_B_BUS_REQ _IOR(OTG_IOCTL_MAGIC, 9, int)
61120
61121 -void fsl_otg_add_timer(void *timer);
61122 -void fsl_otg_del_timer(void *timer);
61123 +void fsl_otg_add_timer(struct otg_fsm *fsm, void *timer);
61124 +void fsl_otg_del_timer(struct otg_fsm *fsm, void *timer);
61125 void fsl_otg_pulse_vbus(void);
61126 --- a/drivers/usb/phy/phy-fsm-usb.c
61127 +++ b/drivers/usb/phy/phy-fsm-usb.c
61128 @@ -41,17 +41,17 @@ static int otg_set_protocol(struct otg_f
61129 fsm->protocol, protocol);
61130 /* stop old protocol */
61131 if (fsm->protocol == PROTO_HOST)
61132 - ret = fsm->ops->start_host(fsm, 0);
61133 + ret = otg_start_host(fsm, 0);
61134 else if (fsm->protocol == PROTO_GADGET)
61135 - ret = fsm->ops->start_gadget(fsm, 0);
61136 + ret = otg_start_gadget(fsm, 0);
61137 if (ret)
61138 return ret;
61139
61140 /* start new protocol */
61141 if (protocol == PROTO_HOST)
61142 - ret = fsm->ops->start_host(fsm, 1);
61143 + ret = otg_start_host(fsm, 1);
61144 else if (protocol == PROTO_GADGET)
61145 - ret = fsm->ops->start_gadget(fsm, 1);
61146 + ret = otg_start_gadget(fsm, 1);
61147 if (ret)
61148 return ret;
61149
61150 @@ -69,42 +69,50 @@ void otg_leave_state(struct otg_fsm *fsm
61151 {
61152 switch (old_state) {
61153 case OTG_STATE_B_IDLE:
61154 - otg_del_timer(fsm, b_se0_srp_tmr);
61155 + otg_del_timer(fsm, B_SE0_SRP);
61156 fsm->b_se0_srp = 0;
61157 + fsm->adp_sns = 0;
61158 + fsm->adp_prb = 0;
61159 break;
61160 case OTG_STATE_B_SRP_INIT:
61161 + fsm->data_pulse = 0;
61162 fsm->b_srp_done = 0;
61163 break;
61164 case OTG_STATE_B_PERIPHERAL:
61165 break;
61166 case OTG_STATE_B_WAIT_ACON:
61167 - otg_del_timer(fsm, b_ase0_brst_tmr);
61168 + otg_del_timer(fsm, B_ASE0_BRST);
61169 fsm->b_ase0_brst_tmout = 0;
61170 break;
61171 case OTG_STATE_B_HOST:
61172 break;
61173 case OTG_STATE_A_IDLE:
61174 + fsm->adp_prb = 0;
61175 break;
61176 case OTG_STATE_A_WAIT_VRISE:
61177 - otg_del_timer(fsm, a_wait_vrise_tmr);
61178 + otg_del_timer(fsm, A_WAIT_VRISE);
61179 fsm->a_wait_vrise_tmout = 0;
61180 break;
61181 case OTG_STATE_A_WAIT_BCON:
61182 - otg_del_timer(fsm, a_wait_bcon_tmr);
61183 + otg_del_timer(fsm, A_WAIT_BCON);
61184 fsm->a_wait_bcon_tmout = 0;
61185 break;
61186 case OTG_STATE_A_HOST:
61187 - otg_del_timer(fsm, a_wait_enum_tmr);
61188 + otg_del_timer(fsm, A_WAIT_ENUM);
61189 break;
61190 case OTG_STATE_A_SUSPEND:
61191 - otg_del_timer(fsm, a_aidl_bdis_tmr);
61192 + otg_del_timer(fsm, A_AIDL_BDIS);
61193 fsm->a_aidl_bdis_tmout = 0;
61194 - fsm->a_suspend_req = 0;
61195 + fsm->a_suspend_req_inf = 0;
61196 break;
61197 case OTG_STATE_A_PERIPHERAL:
61198 + otg_del_timer(fsm, A_BIDL_ADIS);
61199 + fsm->a_bidl_adis_tmout = 0;
61200 break;
61201 case OTG_STATE_A_WAIT_VFALL:
61202 - otg_del_timer(fsm, a_wait_vrise_tmr);
61203 + otg_del_timer(fsm, A_WAIT_VFALL);
61204 + fsm->a_wait_vfall_tmout = 0;
61205 + otg_del_timer(fsm, A_WAIT_VRISE);
61206 break;
61207 case OTG_STATE_A_VBUS_ERR:
61208 break;
61209 @@ -127,14 +135,19 @@ int otg_set_state(struct otg_fsm *fsm, e
61210 otg_chrg_vbus(fsm, 0);
61211 otg_loc_conn(fsm, 0);
61212 otg_loc_sof(fsm, 0);
61213 + /*
61214 + * Driver is responsible for starting ADP probing
61215 + * if ADP sensing times out.
61216 + */
61217 + otg_start_adp_sns(fsm);
61218 otg_set_protocol(fsm, PROTO_UNDEF);
61219 - otg_add_timer(fsm, b_se0_srp_tmr);
61220 + otg_add_timer(fsm, B_SE0_SRP);
61221 break;
61222 case OTG_STATE_B_SRP_INIT:
61223 otg_start_pulse(fsm);
61224 otg_loc_sof(fsm, 0);
61225 otg_set_protocol(fsm, PROTO_UNDEF);
61226 - otg_add_timer(fsm, b_srp_fail_tmr);
61227 + otg_add_timer(fsm, B_SRP_FAIL);
61228 break;
61229 case OTG_STATE_B_PERIPHERAL:
61230 otg_chrg_vbus(fsm, 0);
61231 @@ -147,7 +160,7 @@ int otg_set_state(struct otg_fsm *fsm, e
61232 otg_loc_conn(fsm, 0);
61233 otg_loc_sof(fsm, 0);
61234 otg_set_protocol(fsm, PROTO_HOST);
61235 - otg_add_timer(fsm, b_ase0_brst_tmr);
61236 + otg_add_timer(fsm, B_ASE0_BRST);
61237 fsm->a_bus_suspend = 0;
61238 break;
61239 case OTG_STATE_B_HOST:
61240 @@ -163,6 +176,7 @@ int otg_set_state(struct otg_fsm *fsm, e
61241 otg_chrg_vbus(fsm, 0);
61242 otg_loc_conn(fsm, 0);
61243 otg_loc_sof(fsm, 0);
61244 + otg_start_adp_prb(fsm);
61245 otg_set_protocol(fsm, PROTO_HOST);
61246 break;
61247 case OTG_STATE_A_WAIT_VRISE:
61248 @@ -170,14 +184,14 @@ int otg_set_state(struct otg_fsm *fsm, e
61249 otg_loc_conn(fsm, 0);
61250 otg_loc_sof(fsm, 0);
61251 otg_set_protocol(fsm, PROTO_HOST);
61252 - otg_add_timer(fsm, a_wait_vrise_tmr);
61253 + otg_add_timer(fsm, A_WAIT_VRISE);
61254 break;
61255 case OTG_STATE_A_WAIT_BCON:
61256 otg_drv_vbus(fsm, 1);
61257 otg_loc_conn(fsm, 0);
61258 otg_loc_sof(fsm, 0);
61259 otg_set_protocol(fsm, PROTO_HOST);
61260 - otg_add_timer(fsm, a_wait_bcon_tmr);
61261 + otg_add_timer(fsm, A_WAIT_BCON);
61262 break;
61263 case OTG_STATE_A_HOST:
61264 otg_drv_vbus(fsm, 1);
61265 @@ -188,15 +202,15 @@ int otg_set_state(struct otg_fsm *fsm, e
61266 * When HNP is triggered while a_bus_req = 0, a_host will
61267 * suspend too fast to complete a_set_b_hnp_en
61268 */
61269 - if (!fsm->a_bus_req || fsm->a_suspend_req)
61270 - otg_add_timer(fsm, a_wait_enum_tmr);
61271 + if (!fsm->a_bus_req || fsm->a_suspend_req_inf)
61272 + otg_add_timer(fsm, A_WAIT_ENUM);
61273 break;
61274 case OTG_STATE_A_SUSPEND:
61275 otg_drv_vbus(fsm, 1);
61276 otg_loc_conn(fsm, 0);
61277 otg_loc_sof(fsm, 0);
61278 otg_set_protocol(fsm, PROTO_HOST);
61279 - otg_add_timer(fsm, a_aidl_bdis_tmr);
61280 + otg_add_timer(fsm, A_AIDL_BDIS);
61281
61282 break;
61283 case OTG_STATE_A_PERIPHERAL:
61284 @@ -204,12 +218,14 @@ int otg_set_state(struct otg_fsm *fsm, e
61285 otg_loc_sof(fsm, 0);
61286 otg_set_protocol(fsm, PROTO_GADGET);
61287 otg_drv_vbus(fsm, 1);
61288 + otg_add_timer(fsm, A_BIDL_ADIS);
61289 break;
61290 case OTG_STATE_A_WAIT_VFALL:
61291 otg_drv_vbus(fsm, 0);
61292 otg_loc_conn(fsm, 0);
61293 otg_loc_sof(fsm, 0);
61294 otg_set_protocol(fsm, PROTO_HOST);
61295 + otg_add_timer(fsm, A_WAIT_VFALL);
61296 break;
61297 case OTG_STATE_A_VBUS_ERR:
61298 otg_drv_vbus(fsm, 0);
61299 @@ -250,7 +266,8 @@ int otg_statemachine(struct otg_fsm *fsm
61300 otg_set_state(fsm, OTG_STATE_A_IDLE);
61301 else if (fsm->b_sess_vld && fsm->otg->gadget)
61302 otg_set_state(fsm, OTG_STATE_B_PERIPHERAL);
61303 - else if (fsm->b_bus_req && fsm->b_sess_end && fsm->b_se0_srp)
61304 + else if ((fsm->b_bus_req || fsm->adp_change || fsm->power_up) &&
61305 + fsm->b_ssend_srp && fsm->b_se0_srp)
61306 otg_set_state(fsm, OTG_STATE_B_SRP_INIT);
61307 break;
61308 case OTG_STATE_B_SRP_INIT:
61309 @@ -277,13 +294,14 @@ int otg_statemachine(struct otg_fsm *fsm
61310 case OTG_STATE_B_HOST:
61311 if (!fsm->id || !fsm->b_sess_vld)
61312 otg_set_state(fsm, OTG_STATE_B_IDLE);
61313 - else if (!fsm->b_bus_req || !fsm->a_conn)
61314 + else if (!fsm->b_bus_req || !fsm->a_conn || fsm->test_device)
61315 otg_set_state(fsm, OTG_STATE_B_PERIPHERAL);
61316 break;
61317 case OTG_STATE_A_IDLE:
61318 if (fsm->id)
61319 otg_set_state(fsm, OTG_STATE_B_IDLE);
61320 - else if (!fsm->a_bus_drop && (fsm->a_bus_req || fsm->a_srp_det))
61321 + else if (!fsm->a_bus_drop && (fsm->a_bus_req ||
61322 + fsm->a_srp_det || fsm->adp_change || fsm->power_up))
61323 otg_set_state(fsm, OTG_STATE_A_WAIT_VRISE);
61324 break;
61325 case OTG_STATE_A_WAIT_VRISE:
61326 @@ -301,7 +319,7 @@ int otg_statemachine(struct otg_fsm *fsm
61327 otg_set_state(fsm, OTG_STATE_A_WAIT_VFALL);
61328 break;
61329 case OTG_STATE_A_HOST:
61330 - if ((!fsm->a_bus_req || fsm->a_suspend_req) &&
61331 + if ((!fsm->a_bus_req || fsm->a_suspend_req_inf) &&
61332 fsm->otg->host->b_hnp_enable)
61333 otg_set_state(fsm, OTG_STATE_A_SUSPEND);
61334 else if (fsm->id || !fsm->b_conn || fsm->a_bus_drop)
61335 @@ -324,14 +342,14 @@ int otg_statemachine(struct otg_fsm *fsm
61336 case OTG_STATE_A_PERIPHERAL:
61337 if (fsm->id || fsm->a_bus_drop)
61338 otg_set_state(fsm, OTG_STATE_A_WAIT_VFALL);
61339 - else if (fsm->b_bus_suspend)
61340 + else if (fsm->a_bidl_adis_tmout || fsm->b_bus_suspend)
61341 otg_set_state(fsm, OTG_STATE_A_WAIT_BCON);
61342 else if (!fsm->a_vbus_vld)
61343 otg_set_state(fsm, OTG_STATE_A_VBUS_ERR);
61344 break;
61345 case OTG_STATE_A_WAIT_VFALL:
61346 - if (fsm->id || fsm->a_bus_req || (!fsm->a_sess_vld &&
61347 - !fsm->b_conn))
61348 + if (fsm->a_wait_vfall_tmout || fsm->id || fsm->a_bus_req ||
61349 + (!fsm->a_sess_vld && !fsm->b_conn))
61350 otg_set_state(fsm, OTG_STATE_A_IDLE);
61351 break;
61352 case OTG_STATE_A_VBUS_ERR:
61353 --- a/drivers/usb/phy/phy-fsm-usb.h
61354 +++ b/drivers/usb/phy/phy-fsm-usb.h
61355 @@ -34,45 +34,76 @@
61356 #define PROTO_HOST (1)
61357 #define PROTO_GADGET (2)
61358
61359 +enum otg_fsm_timer {
61360 + /* Standard OTG timers */
61361 + A_WAIT_VRISE,
61362 + A_WAIT_VFALL,
61363 + A_WAIT_BCON,
61364 + A_AIDL_BDIS,
61365 + B_ASE0_BRST,
61366 + A_BIDL_ADIS,
61367 +
61368 + /* Auxiliary timers */
61369 + B_SE0_SRP,
61370 + B_SRP_FAIL,
61371 + A_WAIT_ENUM,
61372 +
61373 + NUM_OTG_FSM_TIMERS,
61374 +};
61375 +
61376 /* OTG state machine according to the OTG spec */
61377 struct otg_fsm {
61378 /* Input */
61379 + int id;
61380 + int adp_change;
61381 + int power_up;
61382 + int test_device;
61383 + int a_bus_drop;
61384 + int a_bus_req;
61385 + int a_srp_det;
61386 + int a_vbus_vld;
61387 + int b_conn;
61388 int a_bus_resume;
61389 int a_bus_suspend;
61390 int a_conn;
61391 + int b_bus_req;
61392 + int b_se0_srp;
61393 + int b_ssend_srp;
61394 + int b_sess_vld;
61395 + /* Auxilary inputs */
61396 int a_sess_vld;
61397 - int a_srp_det;
61398 - int a_vbus_vld;
61399 int b_bus_resume;
61400 int b_bus_suspend;
61401 - int b_conn;
61402 - int b_se0_srp;
61403 - int b_sess_end;
61404 - int b_sess_vld;
61405 - int id;
61406 +
61407 + /* Output */
61408 + int data_pulse;
61409 + int drv_vbus;
61410 + int loc_conn;
61411 + int loc_sof;
61412 + int adp_prb;
61413 + int adp_sns;
61414
61415 /* Internal variables */
61416 int a_set_b_hnp_en;
61417 int b_srp_done;
61418 int b_hnp_enable;
61419 + int a_clr_err;
61420 +
61421 + /* Informative variables */
61422 + int a_bus_drop_inf;
61423 + int a_bus_req_inf;
61424 + int a_clr_err_inf;
61425 + int b_bus_req_inf;
61426 + /* Auxilary informative variables */
61427 + int a_suspend_req_inf;
61428
61429 /* Timeout indicator for timers */
61430 int a_wait_vrise_tmout;
61431 + int a_wait_vfall_tmout;
61432 int a_wait_bcon_tmout;
61433 int a_aidl_bdis_tmout;
61434 int b_ase0_brst_tmout;
61435 -
61436 - /* Informative variables */
61437 - int a_bus_drop;
61438 - int a_bus_req;
61439 - int a_clr_err;
61440 - int a_suspend_req;
61441 - int b_bus_req;
61442 -
61443 - /* Output */
61444 - int drv_vbus;
61445 - int loc_conn;
61446 - int loc_sof;
61447 + int a_bidl_adis_tmout;
61448
61449 struct otg_fsm_ops *ops;
61450 struct usb_otg *otg;
61451 @@ -83,65 +114,123 @@ struct otg_fsm {
61452 };
61453
61454 struct otg_fsm_ops {
61455 - void (*chrg_vbus)(int on);
61456 - void (*drv_vbus)(int on);
61457 - void (*loc_conn)(int on);
61458 - void (*loc_sof)(int on);
61459 - void (*start_pulse)(void);
61460 - void (*add_timer)(void *timer);
61461 - void (*del_timer)(void *timer);
61462 + void (*chrg_vbus)(struct otg_fsm *fsm, int on);
61463 + void (*drv_vbus)(struct otg_fsm *fsm, int on);
61464 + void (*loc_conn)(struct otg_fsm *fsm, int on);
61465 + void (*loc_sof)(struct otg_fsm *fsm, int on);
61466 + void (*start_pulse)(struct otg_fsm *fsm);
61467 + void (*start_adp_prb)(struct otg_fsm *fsm);
61468 + void (*start_adp_sns)(struct otg_fsm *fsm);
61469 + void (*add_timer)(struct otg_fsm *fsm, enum otg_fsm_timer timer);
61470 + void (*del_timer)(struct otg_fsm *fsm, enum otg_fsm_timer timer);
61471 int (*start_host)(struct otg_fsm *fsm, int on);
61472 int (*start_gadget)(struct otg_fsm *fsm, int on);
61473 };
61474
61475
61476 -static inline void otg_chrg_vbus(struct otg_fsm *fsm, int on)
61477 +static inline int otg_chrg_vbus(struct otg_fsm *fsm, int on)
61478 {
61479 - fsm->ops->chrg_vbus(on);
61480 + if (!fsm->ops->chrg_vbus)
61481 + return -EOPNOTSUPP;
61482 + fsm->ops->chrg_vbus(fsm, on);
61483 + return 0;
61484 }
61485
61486 -static inline void otg_drv_vbus(struct otg_fsm *fsm, int on)
61487 +static inline int otg_drv_vbus(struct otg_fsm *fsm, int on)
61488 {
61489 + if (!fsm->ops->drv_vbus)
61490 + return -EOPNOTSUPP;
61491 if (fsm->drv_vbus != on) {
61492 fsm->drv_vbus = on;
61493 - fsm->ops->drv_vbus(on);
61494 + fsm->ops->drv_vbus(fsm, on);
61495 }
61496 + return 0;
61497 }
61498
61499 -static inline void otg_loc_conn(struct otg_fsm *fsm, int on)
61500 +static inline int otg_loc_conn(struct otg_fsm *fsm, int on)
61501 {
61502 + if (!fsm->ops->loc_conn)
61503 + return -EOPNOTSUPP;
61504 if (fsm->loc_conn != on) {
61505 fsm->loc_conn = on;
61506 - fsm->ops->loc_conn(on);
61507 + fsm->ops->loc_conn(fsm, on);
61508 }
61509 + return 0;
61510 }
61511
61512 -static inline void otg_loc_sof(struct otg_fsm *fsm, int on)
61513 +static inline int otg_loc_sof(struct otg_fsm *fsm, int on)
61514 {
61515 + if (!fsm->ops->loc_sof)
61516 + return -EOPNOTSUPP;
61517 if (fsm->loc_sof != on) {
61518 fsm->loc_sof = on;
61519 - fsm->ops->loc_sof(on);
61520 + fsm->ops->loc_sof(fsm, on);
61521 + }
61522 + return 0;
61523 +}
61524 +
61525 +static inline int otg_start_pulse(struct otg_fsm *fsm)
61526 +{
61527 + if (!fsm->ops->start_pulse)
61528 + return -EOPNOTSUPP;
61529 + if (!fsm->data_pulse) {
61530 + fsm->data_pulse = 1;
61531 + fsm->ops->start_pulse(fsm);
61532 }
61533 + return 0;
61534 }
61535
61536 -static inline void otg_start_pulse(struct otg_fsm *fsm)
61537 +static inline int otg_start_adp_prb(struct otg_fsm *fsm)
61538 {
61539 - fsm->ops->start_pulse();
61540 + if (!fsm->ops->start_adp_prb)
61541 + return -EOPNOTSUPP;
61542 + if (!fsm->adp_prb) {
61543 + fsm->adp_sns = 0;
61544 + fsm->adp_prb = 1;
61545 + fsm->ops->start_adp_prb(fsm);
61546 + }
61547 + return 0;
61548 }
61549
61550 -static inline void otg_add_timer(struct otg_fsm *fsm, void *timer)
61551 +static inline int otg_start_adp_sns(struct otg_fsm *fsm)
61552 {
61553 - fsm->ops->add_timer(timer);
61554 + if (!fsm->ops->start_adp_sns)
61555 + return -EOPNOTSUPP;
61556 + if (!fsm->adp_sns) {
61557 + fsm->adp_sns = 1;
61558 + fsm->ops->start_adp_sns(fsm);
61559 + }
61560 + return 0;
61561 }
61562
61563 -static inline void otg_del_timer(struct otg_fsm *fsm, void *timer)
61564 +static inline int otg_add_timer(struct otg_fsm *fsm, enum otg_fsm_timer timer)
61565 {
61566 - fsm->ops->del_timer(timer);
61567 + if (!fsm->ops->add_timer)
61568 + return -EOPNOTSUPP;
61569 + fsm->ops->add_timer(fsm, timer);
61570 + return 0;
61571 }
61572
61573 -int otg_statemachine(struct otg_fsm *fsm);
61574 +static inline int otg_del_timer(struct otg_fsm *fsm, enum otg_fsm_timer timer)
61575 +{
61576 + if (!fsm->ops->del_timer)
61577 + return -EOPNOTSUPP;
61578 + fsm->ops->del_timer(fsm, timer);
61579 + return 0;
61580 +}
61581
61582 -/* Defined by device specific driver, for different timer implementation */
61583 -extern struct fsl_otg_timer *a_wait_vrise_tmr, *a_wait_bcon_tmr,
61584 - *a_aidl_bdis_tmr, *b_ase0_brst_tmr, *b_se0_srp_tmr, *b_srp_fail_tmr,
61585 - *a_wait_enum_tmr;
61586 +static inline int otg_start_host(struct otg_fsm *fsm, int on)
61587 +{
61588 + if (!fsm->ops->start_host)
61589 + return -EOPNOTSUPP;
61590 + return fsm->ops->start_host(fsm, on);
61591 +}
61592 +
61593 +static inline int otg_start_gadget(struct otg_fsm *fsm, int on)
61594 +{
61595 + if (!fsm->ops->start_gadget)
61596 + return -EOPNOTSUPP;
61597 + return fsm->ops->start_gadget(fsm, on);
61598 +}
61599 +
61600 +int otg_statemachine(struct otg_fsm *fsm);
61601 --- a/drivers/usb/phy/phy-generic.c
61602 +++ b/drivers/usb/phy/phy-generic.c
61603 @@ -35,6 +35,9 @@
61604 #include <linux/clk.h>
61605 #include <linux/regulator/consumer.h>
61606 #include <linux/of.h>
61607 +#include <linux/of_gpio.h>
61608 +#include <linux/gpio.h>
61609 +#include <linux/delay.h>
61610
61611 #include "phy-generic.h"
61612
61613 @@ -64,6 +67,23 @@ static int nop_set_suspend(struct usb_ph
61614 return 0;
61615 }
61616
61617 +static void nop_reset_set(struct usb_phy_gen_xceiv *nop, int asserted)
61618 +{
61619 + int value;
61620 +
61621 + if (!gpio_is_valid(nop->gpio_reset))
61622 + return;
61623 +
61624 + value = asserted;
61625 + if (nop->reset_active_low)
61626 + value = !value;
61627 +
61628 + gpio_set_value_cansleep(nop->gpio_reset, value);
61629 +
61630 + if (!asserted)
61631 + usleep_range(10000, 20000);
61632 +}
61633 +
61634 int usb_gen_phy_init(struct usb_phy *phy)
61635 {
61636 struct usb_phy_gen_xceiv *nop = dev_get_drvdata(phy->dev);
61637 @@ -74,13 +94,10 @@ int usb_gen_phy_init(struct usb_phy *phy
61638 }
61639
61640 if (!IS_ERR(nop->clk))
61641 - clk_enable(nop->clk);
61642 + clk_prepare_enable(nop->clk);
61643
61644 - if (!IS_ERR(nop->reset)) {
61645 - /* De-assert RESET */
61646 - if (regulator_enable(nop->reset))
61647 - dev_err(phy->dev, "Failed to de-assert reset\n");
61648 - }
61649 + /* De-assert RESET */
61650 + nop_reset_set(nop, 0);
61651
61652 return 0;
61653 }
61654 @@ -90,14 +107,11 @@ void usb_gen_phy_shutdown(struct usb_phy
61655 {
61656 struct usb_phy_gen_xceiv *nop = dev_get_drvdata(phy->dev);
61657
61658 - if (!IS_ERR(nop->reset)) {
61659 - /* Assert RESET */
61660 - if (regulator_disable(nop->reset))
61661 - dev_err(phy->dev, "Failed to assert reset\n");
61662 - }
61663 + /* Assert RESET */
61664 + nop_reset_set(nop, 1);
61665
61666 if (!IS_ERR(nop->clk))
61667 - clk_disable(nop->clk);
61668 + clk_disable_unprepare(nop->clk);
61669
61670 if (!IS_ERR(nop->vcc)) {
61671 if (regulator_disable(nop->vcc))
61672 @@ -136,11 +150,38 @@ static int nop_set_host(struct usb_otg *
61673 }
61674
61675 int usb_phy_gen_create_phy(struct device *dev, struct usb_phy_gen_xceiv *nop,
61676 - enum usb_phy_type type, u32 clk_rate, bool needs_vcc,
61677 - bool needs_reset)
61678 + struct usb_phy_gen_xceiv_platform_data *pdata)
61679 {
61680 + enum usb_phy_type type = USB_PHY_TYPE_USB2;
61681 int err;
61682
61683 + u32 clk_rate = 0;
61684 + bool needs_vcc = false;
61685 +
61686 + nop->reset_active_low = true; /* default behaviour */
61687 +
61688 + if (dev->of_node) {
61689 + struct device_node *node = dev->of_node;
61690 + enum of_gpio_flags flags;
61691 +
61692 + if (of_property_read_u32(node, "clock-frequency", &clk_rate))
61693 + clk_rate = 0;
61694 +
61695 + needs_vcc = of_property_read_bool(node, "vcc-supply");
61696 + nop->gpio_reset = of_get_named_gpio_flags(node, "reset-gpios",
61697 + 0, &flags);
61698 + if (nop->gpio_reset == -EPROBE_DEFER)
61699 + return -EPROBE_DEFER;
61700 +
61701 + nop->reset_active_low = flags & OF_GPIO_ACTIVE_LOW;
61702 +
61703 + } else if (pdata) {
61704 + type = pdata->type;
61705 + clk_rate = pdata->clk_rate;
61706 + needs_vcc = pdata->needs_vcc;
61707 + nop->gpio_reset = pdata->gpio_reset;
61708 + }
61709 +
61710 nop->phy.otg = devm_kzalloc(dev, sizeof(*nop->phy.otg),
61711 GFP_KERNEL);
61712 if (!nop->phy.otg)
61713 @@ -160,14 +201,6 @@ int usb_phy_gen_create_phy(struct device
61714 }
61715 }
61716
61717 - if (!IS_ERR(nop->clk)) {
61718 - err = clk_prepare(nop->clk);
61719 - if (err) {
61720 - dev_err(dev, "Error preparing clock\n");
61721 - return err;
61722 - }
61723 - }
61724 -
61725 nop->vcc = devm_regulator_get(dev, "vcc");
61726 if (IS_ERR(nop->vcc)) {
61727 dev_dbg(dev, "Error getting vcc regulator: %ld\n",
61728 @@ -176,12 +209,22 @@ int usb_phy_gen_create_phy(struct device
61729 return -EPROBE_DEFER;
61730 }
61731
61732 - nop->reset = devm_regulator_get(dev, "reset");
61733 - if (IS_ERR(nop->reset)) {
61734 - dev_dbg(dev, "Error getting reset regulator: %ld\n",
61735 - PTR_ERR(nop->reset));
61736 - if (needs_reset)
61737 - return -EPROBE_DEFER;
61738 + if (gpio_is_valid(nop->gpio_reset)) {
61739 + unsigned long gpio_flags;
61740 +
61741 + /* Assert RESET */
61742 + if (nop->reset_active_low)
61743 + gpio_flags = GPIOF_OUT_INIT_LOW;
61744 + else
61745 + gpio_flags = GPIOF_OUT_INIT_HIGH;
61746 +
61747 + err = devm_gpio_request_one(dev, nop->gpio_reset,
61748 + gpio_flags, dev_name(dev));
61749 + if (err) {
61750 + dev_err(dev, "Error requesting RESET GPIO %d\n",
61751 + nop->gpio_reset);
61752 + return err;
61753 + }
61754 }
61755
61756 nop->dev = dev;
61757 @@ -200,48 +243,17 @@ int usb_phy_gen_create_phy(struct device
61758 }
61759 EXPORT_SYMBOL_GPL(usb_phy_gen_create_phy);
61760
61761 -void usb_phy_gen_cleanup_phy(struct usb_phy_gen_xceiv *nop)
61762 -{
61763 - if (!IS_ERR(nop->clk))
61764 - clk_unprepare(nop->clk);
61765 -}
61766 -EXPORT_SYMBOL_GPL(usb_phy_gen_cleanup_phy);
61767 -
61768 static int usb_phy_gen_xceiv_probe(struct platform_device *pdev)
61769 {
61770 struct device *dev = &pdev->dev;
61771 - struct usb_phy_gen_xceiv_platform_data *pdata =
61772 - dev_get_platdata(&pdev->dev);
61773 struct usb_phy_gen_xceiv *nop;
61774 - enum usb_phy_type type = USB_PHY_TYPE_USB2;
61775 int err;
61776 - u32 clk_rate = 0;
61777 - bool needs_vcc = false;
61778 - bool needs_reset = false;
61779 -
61780 - if (dev->of_node) {
61781 - struct device_node *node = dev->of_node;
61782 -
61783 - if (of_property_read_u32(node, "clock-frequency", &clk_rate))
61784 - clk_rate = 0;
61785 -
61786 - needs_vcc = of_property_read_bool(node, "vcc-supply");
61787 - needs_reset = of_property_read_bool(node, "reset-supply");
61788 -
61789 - } else if (pdata) {
61790 - type = pdata->type;
61791 - clk_rate = pdata->clk_rate;
61792 - needs_vcc = pdata->needs_vcc;
61793 - needs_reset = pdata->needs_reset;
61794 - }
61795
61796 nop = devm_kzalloc(dev, sizeof(*nop), GFP_KERNEL);
61797 if (!nop)
61798 return -ENOMEM;
61799
61800 -
61801 - err = usb_phy_gen_create_phy(dev, nop, type, clk_rate, needs_vcc,
61802 - needs_reset);
61803 + err = usb_phy_gen_create_phy(dev, nop, dev_get_platdata(&pdev->dev));
61804 if (err)
61805 return err;
61806
61807 @@ -252,23 +264,18 @@ static int usb_phy_gen_xceiv_probe(struc
61808 if (err) {
61809 dev_err(&pdev->dev, "can't register transceiver, err: %d\n",
61810 err);
61811 - goto err_add;
61812 + return err;
61813 }
61814
61815 platform_set_drvdata(pdev, nop);
61816
61817 return 0;
61818 -
61819 -err_add:
61820 - usb_phy_gen_cleanup_phy(nop);
61821 - return err;
61822 }
61823
61824 static int usb_phy_gen_xceiv_remove(struct platform_device *pdev)
61825 {
61826 struct usb_phy_gen_xceiv *nop = platform_get_drvdata(pdev);
61827
61828 - usb_phy_gen_cleanup_phy(nop);
61829 usb_remove_phy(&nop->phy);
61830
61831 return 0;
61832 --- a/drivers/usb/phy/phy-generic.h
61833 +++ b/drivers/usb/phy/phy-generic.h
61834 @@ -1,20 +1,21 @@
61835 #ifndef _PHY_GENERIC_H_
61836 #define _PHY_GENERIC_H_
61837
61838 +#include <linux/usb/usb_phy_gen_xceiv.h>
61839 +
61840 struct usb_phy_gen_xceiv {
61841 struct usb_phy phy;
61842 struct device *dev;
61843 struct clk *clk;
61844 struct regulator *vcc;
61845 - struct regulator *reset;
61846 + int gpio_reset;
61847 + bool reset_active_low;
61848 };
61849
61850 int usb_gen_phy_init(struct usb_phy *phy);
61851 void usb_gen_phy_shutdown(struct usb_phy *phy);
61852
61853 int usb_phy_gen_create_phy(struct device *dev, struct usb_phy_gen_xceiv *nop,
61854 - enum usb_phy_type type, u32 clk_rate, bool needs_vcc,
61855 - bool needs_reset);
61856 -void usb_phy_gen_cleanup_phy(struct usb_phy_gen_xceiv *nop);
61857 + struct usb_phy_gen_xceiv_platform_data *pdata);
61858
61859 #endif
61860 --- a/drivers/usb/phy/phy-omap-control.c
61861 +++ /dev/null
61862 @@ -1,290 +0,0 @@
61863 -/*
61864 - * omap-control-usb.c - The USB part of control module.
61865 - *
61866 - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
61867 - * This program is free software; you can redistribute it and/or modify
61868 - * it under the terms of the GNU General Public License as published by
61869 - * the Free Software Foundation; either version 2 of the License, or
61870 - * (at your option) any later version.
61871 - *
61872 - * Author: Kishon Vijay Abraham I <kishon@ti.com>
61873 - *
61874 - * This program is distributed in the hope that it will be useful,
61875 - * but WITHOUT ANY WARRANTY; without even the implied warranty of
61876 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
61877 - * GNU General Public License for more details.
61878 - *
61879 - */
61880 -
61881 -#include <linux/module.h>
61882 -#include <linux/platform_device.h>
61883 -#include <linux/slab.h>
61884 -#include <linux/of.h>
61885 -#include <linux/err.h>
61886 -#include <linux/io.h>
61887 -#include <linux/clk.h>
61888 -#include <linux/usb/omap_control_usb.h>
61889 -
61890 -static struct omap_control_usb *control_usb;
61891 -
61892 -/**
61893 - * omap_get_control_dev - returns the device pointer for this control device
61894 - *
61895 - * This API should be called to get the device pointer for this control
61896 - * module device. This device pointer should be used for called other
61897 - * exported API's in this driver.
61898 - *
61899 - * To be used by PHY driver and glue driver.
61900 - */
61901 -struct device *omap_get_control_dev(void)
61902 -{
61903 - if (!control_usb)
61904 - return ERR_PTR(-ENODEV);
61905 -
61906 - return control_usb->dev;
61907 -}
61908 -EXPORT_SYMBOL_GPL(omap_get_control_dev);
61909 -
61910 -/**
61911 - * omap_control_usb3_phy_power - power on/off the serializer using control
61912 - * module
61913 - * @dev: the control module device
61914 - * @on: 0 to off and 1 to on based on powering on or off the PHY
61915 - *
61916 - * usb3 PHY driver should call this API to power on or off the PHY.
61917 - */
61918 -void omap_control_usb3_phy_power(struct device *dev, bool on)
61919 -{
61920 - u32 val;
61921 - unsigned long rate;
61922 - struct omap_control_usb *control_usb = dev_get_drvdata(dev);
61923 -
61924 - if (control_usb->type != OMAP_CTRL_DEV_TYPE2)
61925 - return;
61926 -
61927 - rate = clk_get_rate(control_usb->sys_clk);
61928 - rate = rate/1000000;
61929 -
61930 - val = readl(control_usb->phy_power);
61931 -
61932 - if (on) {
61933 - val &= ~(OMAP_CTRL_USB_PWRCTL_CLK_CMD_MASK |
61934 - OMAP_CTRL_USB_PWRCTL_CLK_FREQ_MASK);
61935 - val |= OMAP_CTRL_USB3_PHY_TX_RX_POWERON <<
61936 - OMAP_CTRL_USB_PWRCTL_CLK_CMD_SHIFT;
61937 - val |= rate << OMAP_CTRL_USB_PWRCTL_CLK_FREQ_SHIFT;
61938 - } else {
61939 - val &= ~OMAP_CTRL_USB_PWRCTL_CLK_CMD_MASK;
61940 - val |= OMAP_CTRL_USB3_PHY_TX_RX_POWEROFF <<
61941 - OMAP_CTRL_USB_PWRCTL_CLK_CMD_SHIFT;
61942 - }
61943 -
61944 - writel(val, control_usb->phy_power);
61945 -}
61946 -EXPORT_SYMBOL_GPL(omap_control_usb3_phy_power);
61947 -
61948 -/**
61949 - * omap_control_usb_phy_power - power on/off the phy using control module reg
61950 - * @dev: the control module device
61951 - * @on: 0 or 1, based on powering on or off the PHY
61952 - */
61953 -void omap_control_usb_phy_power(struct device *dev, int on)
61954 -{
61955 - u32 val;
61956 - struct omap_control_usb *control_usb = dev_get_drvdata(dev);
61957 -
61958 - val = readl(control_usb->dev_conf);
61959 -
61960 - if (on)
61961 - val &= ~OMAP_CTRL_DEV_PHY_PD;
61962 - else
61963 - val |= OMAP_CTRL_DEV_PHY_PD;
61964 -
61965 - writel(val, control_usb->dev_conf);
61966 -}
61967 -EXPORT_SYMBOL_GPL(omap_control_usb_phy_power);
61968 -
61969 -/**
61970 - * omap_control_usb_host_mode - set AVALID, VBUSVALID and ID pin in grounded
61971 - * @ctrl_usb: struct omap_control_usb *
61972 - *
61973 - * Writes to the mailbox register to notify the usb core that a usb
61974 - * device has been connected.
61975 - */
61976 -static void omap_control_usb_host_mode(struct omap_control_usb *ctrl_usb)
61977 -{
61978 - u32 val;
61979 -
61980 - val = readl(ctrl_usb->otghs_control);
61981 - val &= ~(OMAP_CTRL_DEV_IDDIG | OMAP_CTRL_DEV_SESSEND);
61982 - val |= OMAP_CTRL_DEV_AVALID | OMAP_CTRL_DEV_VBUSVALID;
61983 - writel(val, ctrl_usb->otghs_control);
61984 -}
61985 -
61986 -/**
61987 - * omap_control_usb_device_mode - set AVALID, VBUSVALID and ID pin in high
61988 - * impedance
61989 - * @ctrl_usb: struct omap_control_usb *
61990 - *
61991 - * Writes to the mailbox register to notify the usb core that it has been
61992 - * connected to a usb host.
61993 - */
61994 -static void omap_control_usb_device_mode(struct omap_control_usb *ctrl_usb)
61995 -{
61996 - u32 val;
61997 -
61998 - val = readl(ctrl_usb->otghs_control);
61999 - val &= ~OMAP_CTRL_DEV_SESSEND;
62000 - val |= OMAP_CTRL_DEV_IDDIG | OMAP_CTRL_DEV_AVALID |
62001 - OMAP_CTRL_DEV_VBUSVALID;
62002 - writel(val, ctrl_usb->otghs_control);
62003 -}
62004 -
62005 -/**
62006 - * omap_control_usb_set_sessionend - Enable SESSIONEND and IDIG to high
62007 - * impedance
62008 - * @ctrl_usb: struct omap_control_usb *
62009 - *
62010 - * Writes to the mailbox register to notify the usb core it's now in
62011 - * disconnected state.
62012 - */
62013 -static void omap_control_usb_set_sessionend(struct omap_control_usb *ctrl_usb)
62014 -{
62015 - u32 val;
62016 -
62017 - val = readl(ctrl_usb->otghs_control);
62018 - val &= ~(OMAP_CTRL_DEV_AVALID | OMAP_CTRL_DEV_VBUSVALID);
62019 - val |= OMAP_CTRL_DEV_IDDIG | OMAP_CTRL_DEV_SESSEND;
62020 - writel(val, ctrl_usb->otghs_control);
62021 -}
62022 -
62023 -/**
62024 - * omap_control_usb_set_mode - Calls to functions to set USB in one of host mode
62025 - * or device mode or to denote disconnected state
62026 - * @dev: the control module device
62027 - * @mode: The mode to which usb should be configured
62028 - *
62029 - * This is an API to write to the mailbox register to notify the usb core that
62030 - * a usb device has been connected.
62031 - */
62032 -void omap_control_usb_set_mode(struct device *dev,
62033 - enum omap_control_usb_mode mode)
62034 -{
62035 - struct omap_control_usb *ctrl_usb;
62036 -
62037 - if (IS_ERR(dev) || control_usb->type != OMAP_CTRL_DEV_TYPE1)
62038 - return;
62039 -
62040 - ctrl_usb = dev_get_drvdata(dev);
62041 -
62042 - switch (mode) {
62043 - case USB_MODE_HOST:
62044 - omap_control_usb_host_mode(ctrl_usb);
62045 - break;
62046 - case USB_MODE_DEVICE:
62047 - omap_control_usb_device_mode(ctrl_usb);
62048 - break;
62049 - case USB_MODE_DISCONNECT:
62050 - omap_control_usb_set_sessionend(ctrl_usb);
62051 - break;
62052 - default:
62053 - dev_vdbg(dev, "invalid omap control usb mode\n");
62054 - }
62055 -}
62056 -EXPORT_SYMBOL_GPL(omap_control_usb_set_mode);
62057 -
62058 -static int omap_control_usb_probe(struct platform_device *pdev)
62059 -{
62060 - struct resource *res;
62061 - struct device_node *np = pdev->dev.of_node;
62062 - struct omap_control_usb_platform_data *pdata =
62063 - dev_get_platdata(&pdev->dev);
62064 -
62065 - control_usb = devm_kzalloc(&pdev->dev, sizeof(*control_usb),
62066 - GFP_KERNEL);
62067 - if (!control_usb) {
62068 - dev_err(&pdev->dev, "unable to alloc memory for control usb\n");
62069 - return -ENOMEM;
62070 - }
62071 -
62072 - if (np) {
62073 - of_property_read_u32(np, "ti,type", &control_usb->type);
62074 - } else if (pdata) {
62075 - control_usb->type = pdata->type;
62076 - } else {
62077 - dev_err(&pdev->dev, "no pdata present\n");
62078 - return -EINVAL;
62079 - }
62080 -
62081 - control_usb->dev = &pdev->dev;
62082 -
62083 - res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
62084 - "control_dev_conf");
62085 - control_usb->dev_conf = devm_ioremap_resource(&pdev->dev, res);
62086 - if (IS_ERR(control_usb->dev_conf))
62087 - return PTR_ERR(control_usb->dev_conf);
62088 -
62089 - if (control_usb->type == OMAP_CTRL_DEV_TYPE1) {
62090 - res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
62091 - "otghs_control");
62092 - control_usb->otghs_control = devm_ioremap_resource(
62093 - &pdev->dev, res);
62094 - if (IS_ERR(control_usb->otghs_control))
62095 - return PTR_ERR(control_usb->otghs_control);
62096 - }
62097 -
62098 - if (control_usb->type == OMAP_CTRL_DEV_TYPE2) {
62099 - res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
62100 - "phy_power_usb");
62101 - control_usb->phy_power = devm_ioremap_resource(
62102 - &pdev->dev, res);
62103 - if (IS_ERR(control_usb->phy_power))
62104 - return PTR_ERR(control_usb->phy_power);
62105 -
62106 - control_usb->sys_clk = devm_clk_get(control_usb->dev,
62107 - "sys_clkin");
62108 - if (IS_ERR(control_usb->sys_clk)) {
62109 - pr_err("%s: unable to get sys_clkin\n", __func__);
62110 - return -EINVAL;
62111 - }
62112 - }
62113 -
62114 -
62115 - dev_set_drvdata(control_usb->dev, control_usb);
62116 -
62117 - return 0;
62118 -}
62119 -
62120 -#ifdef CONFIG_OF
62121 -static const struct of_device_id omap_control_usb_id_table[] = {
62122 - { .compatible = "ti,omap-control-usb" },
62123 - {}
62124 -};
62125 -MODULE_DEVICE_TABLE(of, omap_control_usb_id_table);
62126 -#endif
62127 -
62128 -static struct platform_driver omap_control_usb_driver = {
62129 - .probe = omap_control_usb_probe,
62130 - .driver = {
62131 - .name = "omap-control-usb",
62132 - .owner = THIS_MODULE,
62133 - .of_match_table = of_match_ptr(omap_control_usb_id_table),
62134 - },
62135 -};
62136 -
62137 -static int __init omap_control_usb_init(void)
62138 -{
62139 - return platform_driver_register(&omap_control_usb_driver);
62140 -}
62141 -subsys_initcall(omap_control_usb_init);
62142 -
62143 -static void __exit omap_control_usb_exit(void)
62144 -{
62145 - platform_driver_unregister(&omap_control_usb_driver);
62146 -}
62147 -module_exit(omap_control_usb_exit);
62148 -
62149 -MODULE_ALIAS("platform: omap_control_usb");
62150 -MODULE_AUTHOR("Texas Instruments Inc.");
62151 -MODULE_DESCRIPTION("OMAP Control Module USB Driver");
62152 -MODULE_LICENSE("GPL v2");
62153 --- a/drivers/usb/phy/phy-omap-usb2.c
62154 +++ /dev/null
62155 @@ -1,272 +0,0 @@
62156 -/*
62157 - * omap-usb2.c - USB PHY, talking to musb controller in OMAP.
62158 - *
62159 - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com
62160 - * This program is free software; you can redistribute it and/or modify
62161 - * it under the terms of the GNU General Public License as published by
62162 - * the Free Software Foundation; either version 2 of the License, or
62163 - * (at your option) any later version.
62164 - *
62165 - * Author: Kishon Vijay Abraham I <kishon@ti.com>
62166 - *
62167 - * This program is distributed in the hope that it will be useful,
62168 - * but WITHOUT ANY WARRANTY; without even the implied warranty of
62169 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
62170 - * GNU General Public License for more details.
62171 - *
62172 - */
62173 -
62174 -#include <linux/module.h>
62175 -#include <linux/platform_device.h>
62176 -#include <linux/slab.h>
62177 -#include <linux/of.h>
62178 -#include <linux/io.h>
62179 -#include <linux/usb/omap_usb.h>
62180 -#include <linux/usb/phy_companion.h>
62181 -#include <linux/clk.h>
62182 -#include <linux/err.h>
62183 -#include <linux/pm_runtime.h>
62184 -#include <linux/delay.h>
62185 -#include <linux/usb/omap_control_usb.h>
62186 -
62187 -/**
62188 - * omap_usb2_set_comparator - links the comparator present in the sytem with
62189 - * this phy
62190 - * @comparator - the companion phy(comparator) for this phy
62191 - *
62192 - * The phy companion driver should call this API passing the phy_companion
62193 - * filled with set_vbus and start_srp to be used by usb phy.
62194 - *
62195 - * For use by phy companion driver
62196 - */
62197 -int omap_usb2_set_comparator(struct phy_companion *comparator)
62198 -{
62199 - struct omap_usb *phy;
62200 - struct usb_phy *x = usb_get_phy(USB_PHY_TYPE_USB2);
62201 -
62202 - if (IS_ERR(x))
62203 - return -ENODEV;
62204 -
62205 - phy = phy_to_omapusb(x);
62206 - phy->comparator = comparator;
62207 - return 0;
62208 -}
62209 -EXPORT_SYMBOL_GPL(omap_usb2_set_comparator);
62210 -
62211 -static int omap_usb_set_vbus(struct usb_otg *otg, bool enabled)
62212 -{
62213 - struct omap_usb *phy = phy_to_omapusb(otg->phy);
62214 -
62215 - if (!phy->comparator)
62216 - return -ENODEV;
62217 -
62218 - return phy->comparator->set_vbus(phy->comparator, enabled);
62219 -}
62220 -
62221 -static int omap_usb_start_srp(struct usb_otg *otg)
62222 -{
62223 - struct omap_usb *phy = phy_to_omapusb(otg->phy);
62224 -
62225 - if (!phy->comparator)
62226 - return -ENODEV;
62227 -
62228 - return phy->comparator->start_srp(phy->comparator);
62229 -}
62230 -
62231 -static int omap_usb_set_host(struct usb_otg *otg, struct usb_bus *host)
62232 -{
62233 - struct usb_phy *phy = otg->phy;
62234 -
62235 - otg->host = host;
62236 - if (!host)
62237 - phy->state = OTG_STATE_UNDEFINED;
62238 -
62239 - return 0;
62240 -}
62241 -
62242 -static int omap_usb_set_peripheral(struct usb_otg *otg,
62243 - struct usb_gadget *gadget)
62244 -{
62245 - struct usb_phy *phy = otg->phy;
62246 -
62247 - otg->gadget = gadget;
62248 - if (!gadget)
62249 - phy->state = OTG_STATE_UNDEFINED;
62250 -
62251 - return 0;
62252 -}
62253 -
62254 -static int omap_usb2_suspend(struct usb_phy *x, int suspend)
62255 -{
62256 - struct omap_usb *phy = phy_to_omapusb(x);
62257 - int ret;
62258 -
62259 - if (suspend && !phy->is_suspended) {
62260 - omap_control_usb_phy_power(phy->control_dev, 0);
62261 - pm_runtime_put_sync(phy->dev);
62262 - phy->is_suspended = 1;
62263 - } else if (!suspend && phy->is_suspended) {
62264 - ret = pm_runtime_get_sync(phy->dev);
62265 - if (ret < 0) {
62266 - dev_err(phy->dev, "get_sync failed with err %d\n", ret);
62267 - return ret;
62268 - }
62269 - omap_control_usb_phy_power(phy->control_dev, 1);
62270 - phy->is_suspended = 0;
62271 - }
62272 -
62273 - return 0;
62274 -}
62275 -
62276 -static int omap_usb2_probe(struct platform_device *pdev)
62277 -{
62278 - struct omap_usb *phy;
62279 - struct usb_otg *otg;
62280 -
62281 - phy = devm_kzalloc(&pdev->dev, sizeof(*phy), GFP_KERNEL);
62282 - if (!phy) {
62283 - dev_err(&pdev->dev, "unable to allocate memory for USB2 PHY\n");
62284 - return -ENOMEM;
62285 - }
62286 -
62287 - otg = devm_kzalloc(&pdev->dev, sizeof(*otg), GFP_KERNEL);
62288 - if (!otg) {
62289 - dev_err(&pdev->dev, "unable to allocate memory for USB OTG\n");
62290 - return -ENOMEM;
62291 - }
62292 -
62293 - phy->dev = &pdev->dev;
62294 -
62295 - phy->phy.dev = phy->dev;
62296 - phy->phy.label = "omap-usb2";
62297 - phy->phy.set_suspend = omap_usb2_suspend;
62298 - phy->phy.otg = otg;
62299 - phy->phy.type = USB_PHY_TYPE_USB2;
62300 -
62301 - phy->control_dev = omap_get_control_dev();
62302 - if (IS_ERR(phy->control_dev)) {
62303 - dev_dbg(&pdev->dev, "Failed to get control device\n");
62304 - return -ENODEV;
62305 - }
62306 -
62307 - phy->is_suspended = 1;
62308 - omap_control_usb_phy_power(phy->control_dev, 0);
62309 -
62310 - otg->set_host = omap_usb_set_host;
62311 - otg->set_peripheral = omap_usb_set_peripheral;
62312 - otg->set_vbus = omap_usb_set_vbus;
62313 - otg->start_srp = omap_usb_start_srp;
62314 - otg->phy = &phy->phy;
62315 -
62316 - phy->wkupclk = devm_clk_get(phy->dev, "usb_phy_cm_clk32k");
62317 - if (IS_ERR(phy->wkupclk)) {
62318 - dev_err(&pdev->dev, "unable to get usb_phy_cm_clk32k\n");
62319 - return PTR_ERR(phy->wkupclk);
62320 - }
62321 - clk_prepare(phy->wkupclk);
62322 -
62323 - phy->optclk = devm_clk_get(phy->dev, "usb_otg_ss_refclk960m");
62324 - if (IS_ERR(phy->optclk))
62325 - dev_vdbg(&pdev->dev, "unable to get refclk960m\n");
62326 - else
62327 - clk_prepare(phy->optclk);
62328 -
62329 - usb_add_phy_dev(&phy->phy);
62330 -
62331 - platform_set_drvdata(pdev, phy);
62332 -
62333 - pm_runtime_enable(phy->dev);
62334 -
62335 - return 0;
62336 -}
62337 -
62338 -static int omap_usb2_remove(struct platform_device *pdev)
62339 -{
62340 - struct omap_usb *phy = platform_get_drvdata(pdev);
62341 -
62342 - clk_unprepare(phy->wkupclk);
62343 - if (!IS_ERR(phy->optclk))
62344 - clk_unprepare(phy->optclk);
62345 - usb_remove_phy(&phy->phy);
62346 -
62347 - return 0;
62348 -}
62349 -
62350 -#ifdef CONFIG_PM_RUNTIME
62351 -
62352 -static int omap_usb2_runtime_suspend(struct device *dev)
62353 -{
62354 - struct platform_device *pdev = to_platform_device(dev);
62355 - struct omap_usb *phy = platform_get_drvdata(pdev);
62356 -
62357 - clk_disable(phy->wkupclk);
62358 - if (!IS_ERR(phy->optclk))
62359 - clk_disable(phy->optclk);
62360 -
62361 - return 0;
62362 -}
62363 -
62364 -static int omap_usb2_runtime_resume(struct device *dev)
62365 -{
62366 - struct platform_device *pdev = to_platform_device(dev);
62367 - struct omap_usb *phy = platform_get_drvdata(pdev);
62368 - int ret;
62369 -
62370 - ret = clk_enable(phy->wkupclk);
62371 - if (ret < 0) {
62372 - dev_err(phy->dev, "Failed to enable wkupclk %d\n", ret);
62373 - goto err0;
62374 - }
62375 -
62376 - if (!IS_ERR(phy->optclk)) {
62377 - ret = clk_enable(phy->optclk);
62378 - if (ret < 0) {
62379 - dev_err(phy->dev, "Failed to enable optclk %d\n", ret);
62380 - goto err1;
62381 - }
62382 - }
62383 -
62384 - return 0;
62385 -
62386 -err1:
62387 - clk_disable(phy->wkupclk);
62388 -
62389 -err0:
62390 - return ret;
62391 -}
62392 -
62393 -static const struct dev_pm_ops omap_usb2_pm_ops = {
62394 - SET_RUNTIME_PM_OPS(omap_usb2_runtime_suspend, omap_usb2_runtime_resume,
62395 - NULL)
62396 -};
62397 -
62398 -#define DEV_PM_OPS (&omap_usb2_pm_ops)
62399 -#else
62400 -#define DEV_PM_OPS NULL
62401 -#endif
62402 -
62403 -#ifdef CONFIG_OF
62404 -static const struct of_device_id omap_usb2_id_table[] = {
62405 - { .compatible = "ti,omap-usb2" },
62406 - {}
62407 -};
62408 -MODULE_DEVICE_TABLE(of, omap_usb2_id_table);
62409 -#endif
62410 -
62411 -static struct platform_driver omap_usb2_driver = {
62412 - .probe = omap_usb2_probe,
62413 - .remove = omap_usb2_remove,
62414 - .driver = {
62415 - .name = "omap-usb2",
62416 - .owner = THIS_MODULE,
62417 - .pm = DEV_PM_OPS,
62418 - .of_match_table = of_match_ptr(omap_usb2_id_table),
62419 - },
62420 -};
62421 -
62422 -module_platform_driver(omap_usb2_driver);
62423 -
62424 -MODULE_ALIAS("platform: omap_usb2");
62425 -MODULE_AUTHOR("Texas Instruments Inc.");
62426 -MODULE_DESCRIPTION("OMAP USB2 phy driver");
62427 -MODULE_LICENSE("GPL v2");
62428 --- a/drivers/usb/phy/phy-omap-usb3.c
62429 +++ /dev/null
62430 @@ -1,347 +0,0 @@
62431 -/*
62432 - * omap-usb3 - USB PHY, talking to dwc3 controller in OMAP.
62433 - *
62434 - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
62435 - * This program is free software; you can redistribute it and/or modify
62436 - * it under the terms of the GNU General Public License as published by
62437 - * the Free Software Foundation; either version 2 of the License, or
62438 - * (at your option) any later version.
62439 - *
62440 - * Author: Kishon Vijay Abraham I <kishon@ti.com>
62441 - *
62442 - * This program is distributed in the hope that it will be useful,
62443 - * but WITHOUT ANY WARRANTY; without even the implied warranty of
62444 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
62445 - * GNU General Public License for more details.
62446 - *
62447 - */
62448 -
62449 -#include <linux/module.h>
62450 -#include <linux/platform_device.h>
62451 -#include <linux/slab.h>
62452 -#include <linux/usb/omap_usb.h>
62453 -#include <linux/of.h>
62454 -#include <linux/clk.h>
62455 -#include <linux/err.h>
62456 -#include <linux/pm_runtime.h>
62457 -#include <linux/delay.h>
62458 -#include <linux/usb/omap_control_usb.h>
62459 -
62460 -#define PLL_STATUS 0x00000004
62461 -#define PLL_GO 0x00000008
62462 -#define PLL_CONFIGURATION1 0x0000000C
62463 -#define PLL_CONFIGURATION2 0x00000010
62464 -#define PLL_CONFIGURATION3 0x00000014
62465 -#define PLL_CONFIGURATION4 0x00000020
62466 -
62467 -#define PLL_REGM_MASK 0x001FFE00
62468 -#define PLL_REGM_SHIFT 0x9
62469 -#define PLL_REGM_F_MASK 0x0003FFFF
62470 -#define PLL_REGM_F_SHIFT 0x0
62471 -#define PLL_REGN_MASK 0x000001FE
62472 -#define PLL_REGN_SHIFT 0x1
62473 -#define PLL_SELFREQDCO_MASK 0x0000000E
62474 -#define PLL_SELFREQDCO_SHIFT 0x1
62475 -#define PLL_SD_MASK 0x0003FC00
62476 -#define PLL_SD_SHIFT 0x9
62477 -#define SET_PLL_GO 0x1
62478 -#define PLL_TICOPWDN 0x10000
62479 -#define PLL_LOCK 0x2
62480 -#define PLL_IDLE 0x1
62481 -
62482 -/*
62483 - * This is an Empirical value that works, need to confirm the actual
62484 - * value required for the USB3PHY_PLL_CONFIGURATION2.PLL_IDLE status
62485 - * to be correctly reflected in the USB3PHY_PLL_STATUS register.
62486 - */
62487 -# define PLL_IDLE_TIME 100;
62488 -
62489 -struct usb_dpll_map {
62490 - unsigned long rate;
62491 - struct usb_dpll_params params;
62492 -};
62493 -
62494 -static struct usb_dpll_map dpll_map[] = {
62495 - {12000000, {1250, 5, 4, 20, 0} }, /* 12 MHz */
62496 - {16800000, {3125, 20, 4, 20, 0} }, /* 16.8 MHz */
62497 - {19200000, {1172, 8, 4, 20, 65537} }, /* 19.2 MHz */
62498 - {20000000, {1000, 7, 4, 10, 0} }, /* 20 MHz */
62499 - {26000000, {1250, 12, 4, 20, 0} }, /* 26 MHz */
62500 - {38400000, {3125, 47, 4, 20, 92843} }, /* 38.4 MHz */
62501 -};
62502 -
62503 -static struct usb_dpll_params *omap_usb3_get_dpll_params(unsigned long rate)
62504 -{
62505 - int i;
62506 -
62507 - for (i = 0; i < ARRAY_SIZE(dpll_map); i++) {
62508 - if (rate == dpll_map[i].rate)
62509 - return &dpll_map[i].params;
62510 - }
62511 -
62512 - return NULL;
62513 -}
62514 -
62515 -static int omap_usb3_suspend(struct usb_phy *x, int suspend)
62516 -{
62517 - struct omap_usb *phy = phy_to_omapusb(x);
62518 - int val;
62519 - int timeout = PLL_IDLE_TIME;
62520 -
62521 - if (suspend && !phy->is_suspended) {
62522 - val = omap_usb_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
62523 - val |= PLL_IDLE;
62524 - omap_usb_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
62525 -
62526 - do {
62527 - val = omap_usb_readl(phy->pll_ctrl_base, PLL_STATUS);
62528 - if (val & PLL_TICOPWDN)
62529 - break;
62530 - udelay(1);
62531 - } while (--timeout);
62532 -
62533 - omap_control_usb3_phy_power(phy->control_dev, 0);
62534 -
62535 - phy->is_suspended = 1;
62536 - } else if (!suspend && phy->is_suspended) {
62537 - phy->is_suspended = 0;
62538 -
62539 - val = omap_usb_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
62540 - val &= ~PLL_IDLE;
62541 - omap_usb_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
62542 -
62543 - do {
62544 - val = omap_usb_readl(phy->pll_ctrl_base, PLL_STATUS);
62545 - if (!(val & PLL_TICOPWDN))
62546 - break;
62547 - udelay(1);
62548 - } while (--timeout);
62549 - }
62550 -
62551 - return 0;
62552 -}
62553 -
62554 -static void omap_usb_dpll_relock(struct omap_usb *phy)
62555 -{
62556 - u32 val;
62557 - unsigned long timeout;
62558 -
62559 - omap_usb_writel(phy->pll_ctrl_base, PLL_GO, SET_PLL_GO);
62560 -
62561 - timeout = jiffies + msecs_to_jiffies(20);
62562 - do {
62563 - val = omap_usb_readl(phy->pll_ctrl_base, PLL_STATUS);
62564 - if (val & PLL_LOCK)
62565 - break;
62566 - } while (!WARN_ON(time_after(jiffies, timeout)));
62567 -}
62568 -
62569 -static int omap_usb_dpll_lock(struct omap_usb *phy)
62570 -{
62571 - u32 val;
62572 - unsigned long rate;
62573 - struct usb_dpll_params *dpll_params;
62574 -
62575 - rate = clk_get_rate(phy->sys_clk);
62576 - dpll_params = omap_usb3_get_dpll_params(rate);
62577 - if (!dpll_params) {
62578 - dev_err(phy->dev,
62579 - "No DPLL configuration for %lu Hz SYS CLK\n", rate);
62580 - return -EINVAL;
62581 - }
62582 -
62583 - val = omap_usb_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
62584 - val &= ~PLL_REGN_MASK;
62585 - val |= dpll_params->n << PLL_REGN_SHIFT;
62586 - omap_usb_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);
62587 -
62588 - val = omap_usb_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
62589 - val &= ~PLL_SELFREQDCO_MASK;
62590 - val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT;
62591 - omap_usb_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
62592 -
62593 - val = omap_usb_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
62594 - val &= ~PLL_REGM_MASK;
62595 - val |= dpll_params->m << PLL_REGM_SHIFT;
62596 - omap_usb_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);
62597 -
62598 - val = omap_usb_readl(phy->pll_ctrl_base, PLL_CONFIGURATION4);
62599 - val &= ~PLL_REGM_F_MASK;
62600 - val |= dpll_params->mf << PLL_REGM_F_SHIFT;
62601 - omap_usb_writel(phy->pll_ctrl_base, PLL_CONFIGURATION4, val);
62602 -
62603 - val = omap_usb_readl(phy->pll_ctrl_base, PLL_CONFIGURATION3);
62604 - val &= ~PLL_SD_MASK;
62605 - val |= dpll_params->sd << PLL_SD_SHIFT;
62606 - omap_usb_writel(phy->pll_ctrl_base, PLL_CONFIGURATION3, val);
62607 -
62608 - omap_usb_dpll_relock(phy);
62609 -
62610 - return 0;
62611 -}
62612 -
62613 -static int omap_usb3_init(struct usb_phy *x)
62614 -{
62615 - struct omap_usb *phy = phy_to_omapusb(x);
62616 - int ret;
62617 -
62618 - ret = omap_usb_dpll_lock(phy);
62619 - if (ret)
62620 - return ret;
62621 -
62622 - omap_control_usb3_phy_power(phy->control_dev, 1);
62623 -
62624 - return 0;
62625 -}
62626 -
62627 -static int omap_usb3_probe(struct platform_device *pdev)
62628 -{
62629 - struct omap_usb *phy;
62630 - struct resource *res;
62631 -
62632 - phy = devm_kzalloc(&pdev->dev, sizeof(*phy), GFP_KERNEL);
62633 - if (!phy) {
62634 - dev_err(&pdev->dev, "unable to alloc mem for OMAP USB3 PHY\n");
62635 - return -ENOMEM;
62636 - }
62637 -
62638 - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pll_ctrl");
62639 - phy->pll_ctrl_base = devm_ioremap_resource(&pdev->dev, res);
62640 - if (IS_ERR(phy->pll_ctrl_base))
62641 - return PTR_ERR(phy->pll_ctrl_base);
62642 -
62643 - phy->dev = &pdev->dev;
62644 -
62645 - phy->phy.dev = phy->dev;
62646 - phy->phy.label = "omap-usb3";
62647 - phy->phy.init = omap_usb3_init;
62648 - phy->phy.set_suspend = omap_usb3_suspend;
62649 - phy->phy.type = USB_PHY_TYPE_USB3;
62650 -
62651 - phy->is_suspended = 1;
62652 - phy->wkupclk = devm_clk_get(phy->dev, "usb_phy_cm_clk32k");
62653 - if (IS_ERR(phy->wkupclk)) {
62654 - dev_err(&pdev->dev, "unable to get usb_phy_cm_clk32k\n");
62655 - return PTR_ERR(phy->wkupclk);
62656 - }
62657 - clk_prepare(phy->wkupclk);
62658 -
62659 - phy->optclk = devm_clk_get(phy->dev, "usb_otg_ss_refclk960m");
62660 - if (IS_ERR(phy->optclk)) {
62661 - dev_err(&pdev->dev, "unable to get usb_otg_ss_refclk960m\n");
62662 - return PTR_ERR(phy->optclk);
62663 - }
62664 - clk_prepare(phy->optclk);
62665 -
62666 - phy->sys_clk = devm_clk_get(phy->dev, "sys_clkin");
62667 - if (IS_ERR(phy->sys_clk)) {
62668 - pr_err("%s: unable to get sys_clkin\n", __func__);
62669 - return -EINVAL;
62670 - }
62671 -
62672 - phy->control_dev = omap_get_control_dev();
62673 - if (IS_ERR(phy->control_dev)) {
62674 - dev_dbg(&pdev->dev, "Failed to get control device\n");
62675 - return -ENODEV;
62676 - }
62677 -
62678 - omap_control_usb3_phy_power(phy->control_dev, 0);
62679 - usb_add_phy_dev(&phy->phy);
62680 -
62681 - platform_set_drvdata(pdev, phy);
62682 -
62683 - pm_runtime_enable(phy->dev);
62684 - pm_runtime_get(&pdev->dev);
62685 -
62686 - return 0;
62687 -}
62688 -
62689 -static int omap_usb3_remove(struct platform_device *pdev)
62690 -{
62691 - struct omap_usb *phy = platform_get_drvdata(pdev);
62692 -
62693 - clk_unprepare(phy->wkupclk);
62694 - clk_unprepare(phy->optclk);
62695 - usb_remove_phy(&phy->phy);
62696 - if (!pm_runtime_suspended(&pdev->dev))
62697 - pm_runtime_put(&pdev->dev);
62698 - pm_runtime_disable(&pdev->dev);
62699 -
62700 - return 0;
62701 -}
62702 -
62703 -#ifdef CONFIG_PM_RUNTIME
62704 -
62705 -static int omap_usb3_runtime_suspend(struct device *dev)
62706 -{
62707 - struct platform_device *pdev = to_platform_device(dev);
62708 - struct omap_usb *phy = platform_get_drvdata(pdev);
62709 -
62710 - clk_disable(phy->wkupclk);
62711 - clk_disable(phy->optclk);
62712 -
62713 - return 0;
62714 -}
62715 -
62716 -static int omap_usb3_runtime_resume(struct device *dev)
62717 -{
62718 - u32 ret = 0;
62719 - struct platform_device *pdev = to_platform_device(dev);
62720 - struct omap_usb *phy = platform_get_drvdata(pdev);
62721 -
62722 - ret = clk_enable(phy->optclk);
62723 - if (ret) {
62724 - dev_err(phy->dev, "Failed to enable optclk %d\n", ret);
62725 - goto err1;
62726 - }
62727 -
62728 - ret = clk_enable(phy->wkupclk);
62729 - if (ret) {
62730 - dev_err(phy->dev, "Failed to enable wkupclk %d\n", ret);
62731 - goto err2;
62732 - }
62733 -
62734 - return 0;
62735 -
62736 -err2:
62737 - clk_disable(phy->optclk);
62738 -
62739 -err1:
62740 - return ret;
62741 -}
62742 -
62743 -static const struct dev_pm_ops omap_usb3_pm_ops = {
62744 - SET_RUNTIME_PM_OPS(omap_usb3_runtime_suspend, omap_usb3_runtime_resume,
62745 - NULL)
62746 -};
62747 -
62748 -#define DEV_PM_OPS (&omap_usb3_pm_ops)
62749 -#else
62750 -#define DEV_PM_OPS NULL
62751 -#endif
62752 -
62753 -#ifdef CONFIG_OF
62754 -static const struct of_device_id omap_usb3_id_table[] = {
62755 - { .compatible = "ti,omap-usb3" },
62756 - {}
62757 -};
62758 -MODULE_DEVICE_TABLE(of, omap_usb3_id_table);
62759 -#endif
62760 -
62761 -static struct platform_driver omap_usb3_driver = {
62762 - .probe = omap_usb3_probe,
62763 - .remove = omap_usb3_remove,
62764 - .driver = {
62765 - .name = "omap-usb3",
62766 - .owner = THIS_MODULE,
62767 - .pm = DEV_PM_OPS,
62768 - .of_match_table = of_match_ptr(omap_usb3_id_table),
62769 - },
62770 -};
62771 -
62772 -module_platform_driver(omap_usb3_driver);
62773 -
62774 -MODULE_ALIAS("platform: omap_usb3");
62775 -MODULE_AUTHOR("Texas Instruments Inc.");
62776 -MODULE_DESCRIPTION("OMAP USB3 phy driver");
62777 -MODULE_LICENSE("GPL v2");
62778 --- /dev/null
62779 +++ b/drivers/usb/phy/phy-rcar-gen2-usb.c
62780 @@ -0,0 +1,248 @@
62781 +/*
62782 + * Renesas R-Car Gen2 USB phy driver
62783 + *
62784 + * Copyright (C) 2013 Renesas Solutions Corp.
62785 + * Copyright (C) 2013 Cogent Embedded, Inc.
62786 + *
62787 + * This program is free software; you can redistribute it and/or modify
62788 + * it under the terms of the GNU General Public License version 2 as
62789 + * published by the Free Software Foundation.
62790 + */
62791 +
62792 +#include <linux/clk.h>
62793 +#include <linux/delay.h>
62794 +#include <linux/io.h>
62795 +#include <linux/module.h>
62796 +#include <linux/platform_data/usb-rcar-gen2-phy.h>
62797 +#include <linux/platform_device.h>
62798 +#include <linux/spinlock.h>
62799 +#include <linux/usb/otg.h>
62800 +
62801 +struct rcar_gen2_usb_phy_priv {
62802 + struct usb_phy phy;
62803 + void __iomem *base;
62804 + struct clk *clk;
62805 + spinlock_t lock;
62806 + int usecount;
62807 + u32 ugctrl2;
62808 +};
62809 +
62810 +#define usb_phy_to_priv(p) container_of(p, struct rcar_gen2_usb_phy_priv, phy)
62811 +
62812 +/* Low Power Status register */
62813 +#define USBHS_LPSTS_REG 0x02
62814 +#define USBHS_LPSTS_SUSPM (1 << 14)
62815 +
62816 +/* USB General control register */
62817 +#define USBHS_UGCTRL_REG 0x80
62818 +#define USBHS_UGCTRL_CONNECT (1 << 2)
62819 +#define USBHS_UGCTRL_PLLRESET (1 << 0)
62820 +
62821 +/* USB General control register 2 */
62822 +#define USBHS_UGCTRL2_REG 0x84
62823 +#define USBHS_UGCTRL2_USB0_PCI (1 << 4)
62824 +#define USBHS_UGCTRL2_USB0_HS (3 << 4)
62825 +#define USBHS_UGCTRL2_USB2_PCI (0 << 31)
62826 +#define USBHS_UGCTRL2_USB2_SS (1 << 31)
62827 +
62828 +/* USB General status register */
62829 +#define USBHS_UGSTS_REG 0x88
62830 +#define USBHS_UGSTS_LOCK (3 << 8)
62831 +
62832 +/* Enable USBHS internal phy */
62833 +static int __rcar_gen2_usbhs_phy_enable(void __iomem *base)
62834 +{
62835 + u32 val;
62836 + int i;
62837 +
62838 + /* USBHS PHY power on */
62839 + val = ioread32(base + USBHS_UGCTRL_REG);
62840 + val &= ~USBHS_UGCTRL_PLLRESET;
62841 + iowrite32(val, base + USBHS_UGCTRL_REG);
62842 +
62843 + val = ioread16(base + USBHS_LPSTS_REG);
62844 + val |= USBHS_LPSTS_SUSPM;
62845 + iowrite16(val, base + USBHS_LPSTS_REG);
62846 +
62847 + for (i = 0; i < 20; i++) {
62848 + val = ioread32(base + USBHS_UGSTS_REG);
62849 + if ((val & USBHS_UGSTS_LOCK) == USBHS_UGSTS_LOCK) {
62850 + val = ioread32(base + USBHS_UGCTRL_REG);
62851 + val |= USBHS_UGCTRL_CONNECT;
62852 + iowrite32(val, base + USBHS_UGCTRL_REG);
62853 + return 0;
62854 + }
62855 + udelay(1);
62856 + }
62857 +
62858 + /* Timed out waiting for the PLL lock */
62859 + return -ETIMEDOUT;
62860 +}
62861 +
62862 +/* Disable USBHS internal phy */
62863 +static int __rcar_gen2_usbhs_phy_disable(void __iomem *base)
62864 +{
62865 + u32 val;
62866 +
62867 + /* USBHS PHY power off */
62868 + val = ioread32(base + USBHS_UGCTRL_REG);
62869 + val &= ~USBHS_UGCTRL_CONNECT;
62870 + iowrite32(val, base + USBHS_UGCTRL_REG);
62871 +
62872 + val = ioread16(base + USBHS_LPSTS_REG);
62873 + val &= ~USBHS_LPSTS_SUSPM;
62874 + iowrite16(val, base + USBHS_LPSTS_REG);
62875 +
62876 + val = ioread32(base + USBHS_UGCTRL_REG);
62877 + val |= USBHS_UGCTRL_PLLRESET;
62878 + iowrite32(val, base + USBHS_UGCTRL_REG);
62879 + return 0;
62880 +}
62881 +
62882 +/* Setup USB channels */
62883 +static void __rcar_gen2_usb_phy_init(struct rcar_gen2_usb_phy_priv *priv)
62884 +{
62885 + u32 val;
62886 +
62887 + clk_prepare_enable(priv->clk);
62888 +
62889 + /* Set USB channels in the USBHS UGCTRL2 register */
62890 + val = ioread32(priv->base);
62891 + val &= ~(USBHS_UGCTRL2_USB0_HS | USBHS_UGCTRL2_USB2_SS);
62892 + val |= priv->ugctrl2;
62893 + iowrite32(val, priv->base);
62894 +}
62895 +
62896 +/* Shutdown USB channels */
62897 +static void __rcar_gen2_usb_phy_shutdown(struct rcar_gen2_usb_phy_priv *priv)
62898 +{
62899 + __rcar_gen2_usbhs_phy_disable(priv->base);
62900 + clk_disable_unprepare(priv->clk);
62901 +}
62902 +
62903 +static int rcar_gen2_usb_phy_set_suspend(struct usb_phy *phy, int suspend)
62904 +{
62905 + struct rcar_gen2_usb_phy_priv *priv = usb_phy_to_priv(phy);
62906 + unsigned long flags;
62907 + int retval;
62908 +
62909 + spin_lock_irqsave(&priv->lock, flags);
62910 + retval = suspend ? __rcar_gen2_usbhs_phy_disable(priv->base) :
62911 + __rcar_gen2_usbhs_phy_enable(priv->base);
62912 + spin_unlock_irqrestore(&priv->lock, flags);
62913 + return retval;
62914 +}
62915 +
62916 +static int rcar_gen2_usb_phy_init(struct usb_phy *phy)
62917 +{
62918 + struct rcar_gen2_usb_phy_priv *priv = usb_phy_to_priv(phy);
62919 + unsigned long flags;
62920 +
62921 + spin_lock_irqsave(&priv->lock, flags);
62922 + /*
62923 + * Enable the clock and setup USB channels
62924 + * if it's the first user
62925 + */
62926 + if (!priv->usecount++)
62927 + __rcar_gen2_usb_phy_init(priv);
62928 + spin_unlock_irqrestore(&priv->lock, flags);
62929 + return 0;
62930 +}
62931 +
62932 +static void rcar_gen2_usb_phy_shutdown(struct usb_phy *phy)
62933 +{
62934 + struct rcar_gen2_usb_phy_priv *priv = usb_phy_to_priv(phy);
62935 + unsigned long flags;
62936 +
62937 + spin_lock_irqsave(&priv->lock, flags);
62938 + if (!priv->usecount) {
62939 + dev_warn(phy->dev, "Trying to disable phy with 0 usecount\n");
62940 + goto out;
62941 + }
62942 +
62943 + /* Disable everything if it's the last user */
62944 + if (!--priv->usecount)
62945 + __rcar_gen2_usb_phy_shutdown(priv);
62946 +out:
62947 + spin_unlock_irqrestore(&priv->lock, flags);
62948 +}
62949 +
62950 +static int rcar_gen2_usb_phy_probe(struct platform_device *pdev)
62951 +{
62952 + struct device *dev = &pdev->dev;
62953 + struct rcar_gen2_phy_platform_data *pdata;
62954 + struct rcar_gen2_usb_phy_priv *priv;
62955 + struct resource *res;
62956 + void __iomem *base;
62957 + struct clk *clk;
62958 + int retval;
62959 +
62960 + pdata = dev_get_platdata(&pdev->dev);
62961 + if (!pdata) {
62962 + dev_err(dev, "No platform data\n");
62963 + return -EINVAL;
62964 + }
62965 +
62966 + clk = devm_clk_get(&pdev->dev, "usbhs");
62967 + if (IS_ERR(clk)) {
62968 + dev_err(&pdev->dev, "Can't get the clock\n");
62969 + return PTR_ERR(clk);
62970 + }
62971 +
62972 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
62973 + base = devm_ioremap_resource(dev, res);
62974 + if (IS_ERR(base))
62975 + return PTR_ERR(base);
62976 +
62977 + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
62978 + if (!priv) {
62979 + dev_err(dev, "Memory allocation failed\n");
62980 + return -ENOMEM;
62981 + }
62982 +
62983 + spin_lock_init(&priv->lock);
62984 + priv->clk = clk;
62985 + priv->base = base;
62986 + priv->ugctrl2 = pdata->chan0_pci ?
62987 + USBHS_UGCTRL2_USB0_PCI : USBHS_UGCTRL2_USB0_HS;
62988 + priv->ugctrl2 |= pdata->chan2_pci ?
62989 + USBHS_UGCTRL2_USB2_PCI : USBHS_UGCTRL2_USB2_SS;
62990 + priv->phy.dev = dev;
62991 + priv->phy.label = dev_name(dev);
62992 + priv->phy.init = rcar_gen2_usb_phy_init;
62993 + priv->phy.shutdown = rcar_gen2_usb_phy_shutdown;
62994 + priv->phy.set_suspend = rcar_gen2_usb_phy_set_suspend;
62995 +
62996 + retval = usb_add_phy(&priv->phy, USB_PHY_TYPE_USB2);
62997 + if (retval < 0) {
62998 + dev_err(dev, "Failed to add USB phy\n");
62999 + return retval;
63000 + }
63001 +
63002 + platform_set_drvdata(pdev, priv);
63003 +
63004 + return retval;
63005 +}
63006 +
63007 +static int rcar_gen2_usb_phy_remove(struct platform_device *pdev)
63008 +{
63009 + struct rcar_gen2_usb_phy_priv *priv = platform_get_drvdata(pdev);
63010 +
63011 + usb_remove_phy(&priv->phy);
63012 +
63013 + return 0;
63014 +}
63015 +
63016 +static struct platform_driver rcar_gen2_usb_phy_driver = {
63017 + .driver = {
63018 + .name = "usb_phy_rcar_gen2",
63019 + },
63020 + .probe = rcar_gen2_usb_phy_probe,
63021 + .remove = rcar_gen2_usb_phy_remove,
63022 +};
63023 +
63024 +module_platform_driver(rcar_gen2_usb_phy_driver);
63025 +
63026 +MODULE_LICENSE("GPL v2");
63027 +MODULE_DESCRIPTION("Renesas R-Car Gen2 USB phy");
63028 +MODULE_AUTHOR("Valentine Barshak <valentine.barshak@cogentembedded.com>");
63029 --- a/drivers/usb/phy/phy-tegra-usb.c
63030 +++ b/drivers/usb/phy/phy-tegra-usb.c
63031 @@ -1090,7 +1090,7 @@ static struct platform_driver tegra_usb_
63032 .driver = {
63033 .name = "tegra-phy",
63034 .owner = THIS_MODULE,
63035 - .of_match_table = of_match_ptr(tegra_usb_phy_id_table),
63036 + .of_match_table = tegra_usb_phy_id_table,
63037 },
63038 };
63039 module_platform_driver(tegra_usb_phy_driver);
63040 --- a/drivers/usb/phy/phy-twl4030-usb.c
63041 +++ /dev/null
63042 @@ -1,794 +0,0 @@
63043 -/*
63044 - * twl4030_usb - TWL4030 USB transceiver, talking to OMAP OTG controller
63045 - *
63046 - * Copyright (C) 2004-2007 Texas Instruments
63047 - * Copyright (C) 2008 Nokia Corporation
63048 - * Contact: Felipe Balbi <felipe.balbi@nokia.com>
63049 - *
63050 - * This program is free software; you can redistribute it and/or modify
63051 - * it under the terms of the GNU General Public License as published by
63052 - * the Free Software Foundation; either version 2 of the License, or
63053 - * (at your option) any later version.
63054 - *
63055 - * This program is distributed in the hope that it will be useful,
63056 - * but WITHOUT ANY WARRANTY; without even the implied warranty of
63057 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
63058 - * GNU General Public License for more details.
63059 - *
63060 - * You should have received a copy of the GNU General Public License
63061 - * along with this program; if not, write to the Free Software
63062 - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
63063 - *
63064 - * Current status:
63065 - * - HS USB ULPI mode works.
63066 - * - 3-pin mode support may be added in future.
63067 - */
63068 -
63069 -#include <linux/module.h>
63070 -#include <linux/init.h>
63071 -#include <linux/interrupt.h>
63072 -#include <linux/platform_device.h>
63073 -#include <linux/spinlock.h>
63074 -#include <linux/workqueue.h>
63075 -#include <linux/io.h>
63076 -#include <linux/delay.h>
63077 -#include <linux/usb/otg.h>
63078 -#include <linux/usb/musb-omap.h>
63079 -#include <linux/usb/ulpi.h>
63080 -#include <linux/i2c/twl.h>
63081 -#include <linux/regulator/consumer.h>
63082 -#include <linux/err.h>
63083 -#include <linux/slab.h>
63084 -
63085 -/* Register defines */
63086 -
63087 -#define MCPC_CTRL 0x30
63088 -#define MCPC_CTRL_RTSOL (1 << 7)
63089 -#define MCPC_CTRL_EXTSWR (1 << 6)
63090 -#define MCPC_CTRL_EXTSWC (1 << 5)
63091 -#define MCPC_CTRL_VOICESW (1 << 4)
63092 -#define MCPC_CTRL_OUT64K (1 << 3)
63093 -#define MCPC_CTRL_RTSCTSSW (1 << 2)
63094 -#define MCPC_CTRL_HS_UART (1 << 0)
63095 -
63096 -#define MCPC_IO_CTRL 0x33
63097 -#define MCPC_IO_CTRL_MICBIASEN (1 << 5)
63098 -#define MCPC_IO_CTRL_CTS_NPU (1 << 4)
63099 -#define MCPC_IO_CTRL_RXD_PU (1 << 3)
63100 -#define MCPC_IO_CTRL_TXDTYP (1 << 2)
63101 -#define MCPC_IO_CTRL_CTSTYP (1 << 1)
63102 -#define MCPC_IO_CTRL_RTSTYP (1 << 0)
63103 -
63104 -#define MCPC_CTRL2 0x36
63105 -#define MCPC_CTRL2_MCPC_CK_EN (1 << 0)
63106 -
63107 -#define OTHER_FUNC_CTRL 0x80
63108 -#define OTHER_FUNC_CTRL_BDIS_ACON_EN (1 << 4)
63109 -#define OTHER_FUNC_CTRL_FIVEWIRE_MODE (1 << 2)
63110 -
63111 -#define OTHER_IFC_CTRL 0x83
63112 -#define OTHER_IFC_CTRL_OE_INT_EN (1 << 6)
63113 -#define OTHER_IFC_CTRL_CEA2011_MODE (1 << 5)
63114 -#define OTHER_IFC_CTRL_FSLSSERIALMODE_4PIN (1 << 4)
63115 -#define OTHER_IFC_CTRL_HIZ_ULPI_60MHZ_OUT (1 << 3)
63116 -#define OTHER_IFC_CTRL_HIZ_ULPI (1 << 2)
63117 -#define OTHER_IFC_CTRL_ALT_INT_REROUTE (1 << 0)
63118 -
63119 -#define OTHER_INT_EN_RISE 0x86
63120 -#define OTHER_INT_EN_FALL 0x89
63121 -#define OTHER_INT_STS 0x8C
63122 -#define OTHER_INT_LATCH 0x8D
63123 -#define OTHER_INT_VB_SESS_VLD (1 << 7)
63124 -#define OTHER_INT_DM_HI (1 << 6) /* not valid for "latch" reg */
63125 -#define OTHER_INT_DP_HI (1 << 5) /* not valid for "latch" reg */
63126 -#define OTHER_INT_BDIS_ACON (1 << 3) /* not valid for "fall" regs */
63127 -#define OTHER_INT_MANU (1 << 1)
63128 -#define OTHER_INT_ABNORMAL_STRESS (1 << 0)
63129 -
63130 -#define ID_STATUS 0x96
63131 -#define ID_RES_FLOAT (1 << 4)
63132 -#define ID_RES_440K (1 << 3)
63133 -#define ID_RES_200K (1 << 2)
63134 -#define ID_RES_102K (1 << 1)
63135 -#define ID_RES_GND (1 << 0)
63136 -
63137 -#define POWER_CTRL 0xAC
63138 -#define POWER_CTRL_OTG_ENAB (1 << 5)
63139 -
63140 -#define OTHER_IFC_CTRL2 0xAF
63141 -#define OTHER_IFC_CTRL2_ULPI_STP_LOW (1 << 4)
63142 -#define OTHER_IFC_CTRL2_ULPI_TXEN_POL (1 << 3)
63143 -#define OTHER_IFC_CTRL2_ULPI_4PIN_2430 (1 << 2)
63144 -#define OTHER_IFC_CTRL2_USB_INT_OUTSEL_MASK (3 << 0) /* bits 0 and 1 */
63145 -#define OTHER_IFC_CTRL2_USB_INT_OUTSEL_INT1N (0 << 0)
63146 -#define OTHER_IFC_CTRL2_USB_INT_OUTSEL_INT2N (1 << 0)
63147 -
63148 -#define REG_CTRL_EN 0xB2
63149 -#define REG_CTRL_ERROR 0xB5
63150 -#define ULPI_I2C_CONFLICT_INTEN (1 << 0)
63151 -
63152 -#define OTHER_FUNC_CTRL2 0xB8
63153 -#define OTHER_FUNC_CTRL2_VBAT_TIMER_EN (1 << 0)
63154 -
63155 -/* following registers do not have separate _clr and _set registers */
63156 -#define VBUS_DEBOUNCE 0xC0
63157 -#define ID_DEBOUNCE 0xC1
63158 -#define VBAT_TIMER 0xD3
63159 -#define PHY_PWR_CTRL 0xFD
63160 -#define PHY_PWR_PHYPWD (1 << 0)
63161 -#define PHY_CLK_CTRL 0xFE
63162 -#define PHY_CLK_CTRL_CLOCKGATING_EN (1 << 2)
63163 -#define PHY_CLK_CTRL_CLK32K_EN (1 << 1)
63164 -#define REQ_PHY_DPLL_CLK (1 << 0)
63165 -#define PHY_CLK_CTRL_STS 0xFF
63166 -#define PHY_DPLL_CLK (1 << 0)
63167 -
63168 -/* In module TWL_MODULE_PM_MASTER */
63169 -#define STS_HW_CONDITIONS 0x0F
63170 -
63171 -/* In module TWL_MODULE_PM_RECEIVER */
63172 -#define VUSB_DEDICATED1 0x7D
63173 -#define VUSB_DEDICATED2 0x7E
63174 -#define VUSB1V5_DEV_GRP 0x71
63175 -#define VUSB1V5_TYPE 0x72
63176 -#define VUSB1V5_REMAP 0x73
63177 -#define VUSB1V8_DEV_GRP 0x74
63178 -#define VUSB1V8_TYPE 0x75
63179 -#define VUSB1V8_REMAP 0x76
63180 -#define VUSB3V1_DEV_GRP 0x77
63181 -#define VUSB3V1_TYPE 0x78
63182 -#define VUSB3V1_REMAP 0x79
63183 -
63184 -/* In module TWL4030_MODULE_INTBR */
63185 -#define PMBR1 0x0D
63186 -#define GPIO_USB_4PIN_ULPI_2430C (3 << 0)
63187 -
63188 -struct twl4030_usb {
63189 - struct usb_phy phy;
63190 - struct device *dev;
63191 -
63192 - /* TWL4030 internal USB regulator supplies */
63193 - struct regulator *usb1v5;
63194 - struct regulator *usb1v8;
63195 - struct regulator *usb3v1;
63196 -
63197 - /* for vbus reporting with irqs disabled */
63198 - spinlock_t lock;
63199 -
63200 - /* pin configuration */
63201 - enum twl4030_usb_mode usb_mode;
63202 -
63203 - int irq;
63204 - enum omap_musb_vbus_id_status linkstat;
63205 - bool vbus_supplied;
63206 - u8 asleep;
63207 - bool irq_enabled;
63208 -
63209 - struct delayed_work id_workaround_work;
63210 -};
63211 -
63212 -/* internal define on top of container_of */
63213 -#define phy_to_twl(x) container_of((x), struct twl4030_usb, phy)
63214 -
63215 -/*-------------------------------------------------------------------------*/
63216 -
63217 -static int twl4030_i2c_write_u8_verify(struct twl4030_usb *twl,
63218 - u8 module, u8 data, u8 address)
63219 -{
63220 - u8 check;
63221 -
63222 - if ((twl_i2c_write_u8(module, data, address) >= 0) &&
63223 - (twl_i2c_read_u8(module, &check, address) >= 0) &&
63224 - (check == data))
63225 - return 0;
63226 - dev_dbg(twl->dev, "Write%d[%d,0x%x] wrote %02x but read %02x\n",
63227 - 1, module, address, check, data);
63228 -
63229 - /* Failed once: Try again */
63230 - if ((twl_i2c_write_u8(module, data, address) >= 0) &&
63231 - (twl_i2c_read_u8(module, &check, address) >= 0) &&
63232 - (check == data))
63233 - return 0;
63234 - dev_dbg(twl->dev, "Write%d[%d,0x%x] wrote %02x but read %02x\n",
63235 - 2, module, address, check, data);
63236 -
63237 - /* Failed again: Return error */
63238 - return -EBUSY;
63239 -}
63240 -
63241 -#define twl4030_usb_write_verify(twl, address, data) \
63242 - twl4030_i2c_write_u8_verify(twl, TWL_MODULE_USB, (data), (address))
63243 -
63244 -static inline int twl4030_usb_write(struct twl4030_usb *twl,
63245 - u8 address, u8 data)
63246 -{
63247 - int ret = 0;
63248 -
63249 - ret = twl_i2c_write_u8(TWL_MODULE_USB, data, address);
63250 - if (ret < 0)
63251 - dev_dbg(twl->dev,
63252 - "TWL4030:USB:Write[0x%x] Error %d\n", address, ret);
63253 - return ret;
63254 -}
63255 -
63256 -static inline int twl4030_readb(struct twl4030_usb *twl, u8 module, u8 address)
63257 -{
63258 - u8 data;
63259 - int ret = 0;
63260 -
63261 - ret = twl_i2c_read_u8(module, &data, address);
63262 - if (ret >= 0)
63263 - ret = data;
63264 - else
63265 - dev_dbg(twl->dev,
63266 - "TWL4030:readb[0x%x,0x%x] Error %d\n",
63267 - module, address, ret);
63268 -
63269 - return ret;
63270 -}
63271 -
63272 -static inline int twl4030_usb_read(struct twl4030_usb *twl, u8 address)
63273 -{
63274 - return twl4030_readb(twl, TWL_MODULE_USB, address);
63275 -}
63276 -
63277 -/*-------------------------------------------------------------------------*/
63278 -
63279 -static inline int
63280 -twl4030_usb_set_bits(struct twl4030_usb *twl, u8 reg, u8 bits)
63281 -{
63282 - return twl4030_usb_write(twl, ULPI_SET(reg), bits);
63283 -}
63284 -
63285 -static inline int
63286 -twl4030_usb_clear_bits(struct twl4030_usb *twl, u8 reg, u8 bits)
63287 -{
63288 - return twl4030_usb_write(twl, ULPI_CLR(reg), bits);
63289 -}
63290 -
63291 -/*-------------------------------------------------------------------------*/
63292 -
63293 -static bool twl4030_is_driving_vbus(struct twl4030_usb *twl)
63294 -{
63295 - int ret;
63296 -
63297 - ret = twl4030_usb_read(twl, PHY_CLK_CTRL_STS);
63298 - if (ret < 0 || !(ret & PHY_DPLL_CLK))
63299 - /*
63300 - * if clocks are off, registers are not updated,
63301 - * but we can assume we don't drive VBUS in this case
63302 - */
63303 - return false;
63304 -
63305 - ret = twl4030_usb_read(twl, ULPI_OTG_CTRL);
63306 - if (ret < 0)
63307 - return false;
63308 -
63309 - return (ret & (ULPI_OTG_DRVVBUS | ULPI_OTG_CHRGVBUS)) ? true : false;
63310 -}
63311 -
63312 -static enum omap_musb_vbus_id_status
63313 - twl4030_usb_linkstat(struct twl4030_usb *twl)
63314 -{
63315 - int status;
63316 - enum omap_musb_vbus_id_status linkstat = OMAP_MUSB_UNKNOWN;
63317 -
63318 - twl->vbus_supplied = false;
63319 -
63320 - /*
63321 - * For ID/VBUS sensing, see manual section 15.4.8 ...
63322 - * except when using only battery backup power, two
63323 - * comparators produce VBUS_PRES and ID_PRES signals,
63324 - * which don't match docs elsewhere. But ... BIT(7)
63325 - * and BIT(2) of STS_HW_CONDITIONS, respectively, do
63326 - * seem to match up. If either is true the USB_PRES
63327 - * signal is active, the OTG module is activated, and
63328 - * its interrupt may be raised (may wake the system).
63329 - */
63330 - status = twl4030_readb(twl, TWL_MODULE_PM_MASTER, STS_HW_CONDITIONS);
63331 - if (status < 0)
63332 - dev_err(twl->dev, "USB link status err %d\n", status);
63333 - else if (status & (BIT(7) | BIT(2))) {
63334 - if (status & BIT(7)) {
63335 - if (twl4030_is_driving_vbus(twl))
63336 - status &= ~BIT(7);
63337 - else
63338 - twl->vbus_supplied = true;
63339 - }
63340 -
63341 - if (status & BIT(2))
63342 - linkstat = OMAP_MUSB_ID_GROUND;
63343 - else if (status & BIT(7))
63344 - linkstat = OMAP_MUSB_VBUS_VALID;
63345 - else
63346 - linkstat = OMAP_MUSB_VBUS_OFF;
63347 - } else {
63348 - if (twl->linkstat != OMAP_MUSB_UNKNOWN)
63349 - linkstat = OMAP_MUSB_VBUS_OFF;
63350 - }
63351 -
63352 - dev_dbg(twl->dev, "HW_CONDITIONS 0x%02x/%d; link %d\n",
63353 - status, status, linkstat);
63354 -
63355 - /* REVISIT this assumes host and peripheral controllers
63356 - * are registered, and that both are active...
63357 - */
63358 -
63359 - return linkstat;
63360 -}
63361 -
63362 -static void twl4030_usb_set_mode(struct twl4030_usb *twl, int mode)
63363 -{
63364 - twl->usb_mode = mode;
63365 -
63366 - switch (mode) {
63367 - case T2_USB_MODE_ULPI:
63368 - twl4030_usb_clear_bits(twl, ULPI_IFC_CTRL,
63369 - ULPI_IFC_CTRL_CARKITMODE);
63370 - twl4030_usb_set_bits(twl, POWER_CTRL, POWER_CTRL_OTG_ENAB);
63371 - twl4030_usb_clear_bits(twl, ULPI_FUNC_CTRL,
63372 - ULPI_FUNC_CTRL_XCVRSEL_MASK |
63373 - ULPI_FUNC_CTRL_OPMODE_MASK);
63374 - break;
63375 - case -1:
63376 - /* FIXME: power on defaults */
63377 - break;
63378 - default:
63379 - dev_err(twl->dev, "unsupported T2 transceiver mode %d\n",
63380 - mode);
63381 - break;
63382 - };
63383 -}
63384 -
63385 -static void twl4030_i2c_access(struct twl4030_usb *twl, int on)
63386 -{
63387 - unsigned long timeout;
63388 - int val = twl4030_usb_read(twl, PHY_CLK_CTRL);
63389 -
63390 - if (val >= 0) {
63391 - if (on) {
63392 - /* enable DPLL to access PHY registers over I2C */
63393 - val |= REQ_PHY_DPLL_CLK;
63394 - WARN_ON(twl4030_usb_write_verify(twl, PHY_CLK_CTRL,
63395 - (u8)val) < 0);
63396 -
63397 - timeout = jiffies + HZ;
63398 - while (!(twl4030_usb_read(twl, PHY_CLK_CTRL_STS) &
63399 - PHY_DPLL_CLK)
63400 - && time_before(jiffies, timeout))
63401 - udelay(10);
63402 - if (!(twl4030_usb_read(twl, PHY_CLK_CTRL_STS) &
63403 - PHY_DPLL_CLK))
63404 - dev_err(twl->dev, "Timeout setting T2 HSUSB "
63405 - "PHY DPLL clock\n");
63406 - } else {
63407 - /* let ULPI control the DPLL clock */
63408 - val &= ~REQ_PHY_DPLL_CLK;
63409 - WARN_ON(twl4030_usb_write_verify(twl, PHY_CLK_CTRL,
63410 - (u8)val) < 0);
63411 - }
63412 - }
63413 -}
63414 -
63415 -static void __twl4030_phy_power(struct twl4030_usb *twl, int on)
63416 -{
63417 - u8 pwr = twl4030_usb_read(twl, PHY_PWR_CTRL);
63418 -
63419 - if (on)
63420 - pwr &= ~PHY_PWR_PHYPWD;
63421 - else
63422 - pwr |= PHY_PWR_PHYPWD;
63423 -
63424 - WARN_ON(twl4030_usb_write_verify(twl, PHY_PWR_CTRL, pwr) < 0);
63425 -}
63426 -
63427 -static void twl4030_phy_power(struct twl4030_usb *twl, int on)
63428 -{
63429 - int ret;
63430 -
63431 - if (on) {
63432 - ret = regulator_enable(twl->usb3v1);
63433 - if (ret)
63434 - dev_err(twl->dev, "Failed to enable usb3v1\n");
63435 -
63436 - ret = regulator_enable(twl->usb1v8);
63437 - if (ret)
63438 - dev_err(twl->dev, "Failed to enable usb1v8\n");
63439 -
63440 - /*
63441 - * Disabling usb3v1 regulator (= writing 0 to VUSB3V1_DEV_GRP
63442 - * in twl4030) resets the VUSB_DEDICATED2 register. This reset
63443 - * enables VUSB3V1_SLEEP bit that remaps usb3v1 ACTIVE state to
63444 - * SLEEP. We work around this by clearing the bit after usv3v1
63445 - * is re-activated. This ensures that VUSB3V1 is really active.
63446 - */
63447 - twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB_DEDICATED2);
63448 -
63449 - ret = regulator_enable(twl->usb1v5);
63450 - if (ret)
63451 - dev_err(twl->dev, "Failed to enable usb1v5\n");
63452 -
63453 - __twl4030_phy_power(twl, 1);
63454 - twl4030_usb_write(twl, PHY_CLK_CTRL,
63455 - twl4030_usb_read(twl, PHY_CLK_CTRL) |
63456 - (PHY_CLK_CTRL_CLOCKGATING_EN |
63457 - PHY_CLK_CTRL_CLK32K_EN));
63458 - } else {
63459 - __twl4030_phy_power(twl, 0);
63460 - regulator_disable(twl->usb1v5);
63461 - regulator_disable(twl->usb1v8);
63462 - regulator_disable(twl->usb3v1);
63463 - }
63464 -}
63465 -
63466 -static void twl4030_phy_suspend(struct twl4030_usb *twl, int controller_off)
63467 -{
63468 - if (twl->asleep)
63469 - return;
63470 -
63471 - twl4030_phy_power(twl, 0);
63472 - twl->asleep = 1;
63473 - dev_dbg(twl->dev, "%s\n", __func__);
63474 -}
63475 -
63476 -static void __twl4030_phy_resume(struct twl4030_usb *twl)
63477 -{
63478 - twl4030_phy_power(twl, 1);
63479 - twl4030_i2c_access(twl, 1);
63480 - twl4030_usb_set_mode(twl, twl->usb_mode);
63481 - if (twl->usb_mode == T2_USB_MODE_ULPI)
63482 - twl4030_i2c_access(twl, 0);
63483 -}
63484 -
63485 -static void twl4030_phy_resume(struct twl4030_usb *twl)
63486 -{
63487 - if (!twl->asleep)
63488 - return;
63489 - __twl4030_phy_resume(twl);
63490 - twl->asleep = 0;
63491 - dev_dbg(twl->dev, "%s\n", __func__);
63492 -
63493 - /*
63494 - * XXX When VBUS gets driven after musb goes to A mode,
63495 - * ID_PRES related interrupts no longer arrive, why?
63496 - * Register itself is updated fine though, so we must poll.
63497 - */
63498 - if (twl->linkstat == OMAP_MUSB_ID_GROUND) {
63499 - cancel_delayed_work(&twl->id_workaround_work);
63500 - schedule_delayed_work(&twl->id_workaround_work, HZ);
63501 - }
63502 -}
63503 -
63504 -static int twl4030_usb_ldo_init(struct twl4030_usb *twl)
63505 -{
63506 - /* Enable writing to power configuration registers */
63507 - twl_i2c_write_u8(TWL_MODULE_PM_MASTER, TWL4030_PM_MASTER_KEY_CFG1,
63508 - TWL4030_PM_MASTER_PROTECT_KEY);
63509 -
63510 - twl_i2c_write_u8(TWL_MODULE_PM_MASTER, TWL4030_PM_MASTER_KEY_CFG2,
63511 - TWL4030_PM_MASTER_PROTECT_KEY);
63512 -
63513 - /* Keep VUSB3V1 LDO in sleep state until VBUS/ID change detected*/
63514 - /*twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB_DEDICATED2);*/
63515 -
63516 - /* input to VUSB3V1 LDO is from VBAT, not VBUS */
63517 - twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0x14, VUSB_DEDICATED1);
63518 -
63519 - /* Initialize 3.1V regulator */
63520 - twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB3V1_DEV_GRP);
63521 -
63522 - twl->usb3v1 = devm_regulator_get(twl->dev, "usb3v1");
63523 - if (IS_ERR(twl->usb3v1))
63524 - return -ENODEV;
63525 -
63526 - twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB3V1_TYPE);
63527 -
63528 - /* Initialize 1.5V regulator */
63529 - twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB1V5_DEV_GRP);
63530 -
63531 - twl->usb1v5 = devm_regulator_get(twl->dev, "usb1v5");
63532 - if (IS_ERR(twl->usb1v5))
63533 - return -ENODEV;
63534 -
63535 - twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB1V5_TYPE);
63536 -
63537 - /* Initialize 1.8V regulator */
63538 - twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB1V8_DEV_GRP);
63539 -
63540 - twl->usb1v8 = devm_regulator_get(twl->dev, "usb1v8");
63541 - if (IS_ERR(twl->usb1v8))
63542 - return -ENODEV;
63543 -
63544 - twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB1V8_TYPE);
63545 -
63546 - /* disable access to power configuration registers */
63547 - twl_i2c_write_u8(TWL_MODULE_PM_MASTER, 0,
63548 - TWL4030_PM_MASTER_PROTECT_KEY);
63549 -
63550 - return 0;
63551 -}
63552 -
63553 -static ssize_t twl4030_usb_vbus_show(struct device *dev,
63554 - struct device_attribute *attr, char *buf)
63555 -{
63556 - struct twl4030_usb *twl = dev_get_drvdata(dev);
63557 - unsigned long flags;
63558 - int ret = -EINVAL;
63559 -
63560 - spin_lock_irqsave(&twl->lock, flags);
63561 - ret = sprintf(buf, "%s\n",
63562 - twl->vbus_supplied ? "on" : "off");
63563 - spin_unlock_irqrestore(&twl->lock, flags);
63564 -
63565 - return ret;
63566 -}
63567 -static DEVICE_ATTR(vbus, 0444, twl4030_usb_vbus_show, NULL);
63568 -
63569 -static irqreturn_t twl4030_usb_irq(int irq, void *_twl)
63570 -{
63571 - struct twl4030_usb *twl = _twl;
63572 - enum omap_musb_vbus_id_status status;
63573 - bool status_changed = false;
63574 -
63575 - status = twl4030_usb_linkstat(twl);
63576 -
63577 - spin_lock_irq(&twl->lock);
63578 - if (status >= 0 && status != twl->linkstat) {
63579 - twl->linkstat = status;
63580 - status_changed = true;
63581 - }
63582 - spin_unlock_irq(&twl->lock);
63583 -
63584 - if (status_changed) {
63585 - /* FIXME add a set_power() method so that B-devices can
63586 - * configure the charger appropriately. It's not always
63587 - * correct to consume VBUS power, and how much current to
63588 - * consume is a function of the USB configuration chosen
63589 - * by the host.
63590 - *
63591 - * REVISIT usb_gadget_vbus_connect(...) as needed, ditto
63592 - * its disconnect() sibling, when changing to/from the
63593 - * USB_LINK_VBUS state. musb_hdrc won't care until it
63594 - * starts to handle softconnect right.
63595 - */
63596 - omap_musb_mailbox(status);
63597 - }
63598 - sysfs_notify(&twl->dev->kobj, NULL, "vbus");
63599 -
63600 - return IRQ_HANDLED;
63601 -}
63602 -
63603 -static void twl4030_id_workaround_work(struct work_struct *work)
63604 -{
63605 - struct twl4030_usb *twl = container_of(work, struct twl4030_usb,
63606 - id_workaround_work.work);
63607 - enum omap_musb_vbus_id_status status;
63608 - bool status_changed = false;
63609 -
63610 - status = twl4030_usb_linkstat(twl);
63611 -
63612 - spin_lock_irq(&twl->lock);
63613 - if (status >= 0 && status != twl->linkstat) {
63614 - twl->linkstat = status;
63615 - status_changed = true;
63616 - }
63617 - spin_unlock_irq(&twl->lock);
63618 -
63619 - if (status_changed) {
63620 - dev_dbg(twl->dev, "handle missing status change to %d\n",
63621 - status);
63622 - omap_musb_mailbox(status);
63623 - }
63624 -
63625 - /* don't schedule during sleep - irq works right then */
63626 - if (status == OMAP_MUSB_ID_GROUND && !twl->asleep) {
63627 - cancel_delayed_work(&twl->id_workaround_work);
63628 - schedule_delayed_work(&twl->id_workaround_work, HZ);
63629 - }
63630 -}
63631 -
63632 -static int twl4030_usb_phy_init(struct usb_phy *phy)
63633 -{
63634 - struct twl4030_usb *twl = phy_to_twl(phy);
63635 - enum omap_musb_vbus_id_status status;
63636 -
63637 - /*
63638 - * Start in sleep state, we'll get called through set_suspend()
63639 - * callback when musb is runtime resumed and it's time to start.
63640 - */
63641 - __twl4030_phy_power(twl, 0);
63642 - twl->asleep = 1;
63643 -
63644 - status = twl4030_usb_linkstat(twl);
63645 - twl->linkstat = status;
63646 -
63647 - if (status == OMAP_MUSB_ID_GROUND || status == OMAP_MUSB_VBUS_VALID)
63648 - omap_musb_mailbox(twl->linkstat);
63649 -
63650 - sysfs_notify(&twl->dev->kobj, NULL, "vbus");
63651 - return 0;
63652 -}
63653 -
63654 -static int twl4030_set_suspend(struct usb_phy *x, int suspend)
63655 -{
63656 - struct twl4030_usb *twl = phy_to_twl(x);
63657 -
63658 - if (suspend)
63659 - twl4030_phy_suspend(twl, 1);
63660 - else
63661 - twl4030_phy_resume(twl);
63662 -
63663 - return 0;
63664 -}
63665 -
63666 -static int twl4030_set_peripheral(struct usb_otg *otg,
63667 - struct usb_gadget *gadget)
63668 -{
63669 - if (!otg)
63670 - return -ENODEV;
63671 -
63672 - otg->gadget = gadget;
63673 - if (!gadget)
63674 - otg->phy->state = OTG_STATE_UNDEFINED;
63675 -
63676 - return 0;
63677 -}
63678 -
63679 -static int twl4030_set_host(struct usb_otg *otg, struct usb_bus *host)
63680 -{
63681 - if (!otg)
63682 - return -ENODEV;
63683 -
63684 - otg->host = host;
63685 - if (!host)
63686 - otg->phy->state = OTG_STATE_UNDEFINED;
63687 -
63688 - return 0;
63689 -}
63690 -
63691 -static int twl4030_usb_probe(struct platform_device *pdev)
63692 -{
63693 - struct twl4030_usb_data *pdata = dev_get_platdata(&pdev->dev);
63694 - struct twl4030_usb *twl;
63695 - int status, err;
63696 - struct usb_otg *otg;
63697 - struct device_node *np = pdev->dev.of_node;
63698 -
63699 - twl = devm_kzalloc(&pdev->dev, sizeof *twl, GFP_KERNEL);
63700 - if (!twl)
63701 - return -ENOMEM;
63702 -
63703 - if (np)
63704 - of_property_read_u32(np, "usb_mode",
63705 - (enum twl4030_usb_mode *)&twl->usb_mode);
63706 - else if (pdata)
63707 - twl->usb_mode = pdata->usb_mode;
63708 - else {
63709 - dev_err(&pdev->dev, "twl4030 initialized without pdata\n");
63710 - return -EINVAL;
63711 - }
63712 -
63713 - otg = devm_kzalloc(&pdev->dev, sizeof *otg, GFP_KERNEL);
63714 - if (!otg)
63715 - return -ENOMEM;
63716 -
63717 - twl->dev = &pdev->dev;
63718 - twl->irq = platform_get_irq(pdev, 0);
63719 - twl->vbus_supplied = false;
63720 - twl->asleep = 1;
63721 - twl->linkstat = OMAP_MUSB_UNKNOWN;
63722 -
63723 - twl->phy.dev = twl->dev;
63724 - twl->phy.label = "twl4030";
63725 - twl->phy.otg = otg;
63726 - twl->phy.type = USB_PHY_TYPE_USB2;
63727 - twl->phy.set_suspend = twl4030_set_suspend;
63728 - twl->phy.init = twl4030_usb_phy_init;
63729 -
63730 - otg->phy = &twl->phy;
63731 - otg->set_host = twl4030_set_host;
63732 - otg->set_peripheral = twl4030_set_peripheral;
63733 -
63734 - /* init spinlock for workqueue */
63735 - spin_lock_init(&twl->lock);
63736 -
63737 - INIT_DELAYED_WORK(&twl->id_workaround_work, twl4030_id_workaround_work);
63738 -
63739 - err = twl4030_usb_ldo_init(twl);
63740 - if (err) {
63741 - dev_err(&pdev->dev, "ldo init failed\n");
63742 - return err;
63743 - }
63744 - usb_add_phy_dev(&twl->phy);
63745 -
63746 - platform_set_drvdata(pdev, twl);
63747 - if (device_create_file(&pdev->dev, &dev_attr_vbus))
63748 - dev_warn(&pdev->dev, "could not create sysfs file\n");
63749 -
63750 - /* Our job is to use irqs and status from the power module
63751 - * to keep the transceiver disabled when nothing's connected.
63752 - *
63753 - * FIXME we actually shouldn't start enabling it until the
63754 - * USB controller drivers have said they're ready, by calling
63755 - * set_host() and/or set_peripheral() ... OTG_capable boards
63756 - * need both handles, otherwise just one suffices.
63757 - */
63758 - twl->irq_enabled = true;
63759 - status = devm_request_threaded_irq(twl->dev, twl->irq, NULL,
63760 - twl4030_usb_irq, IRQF_TRIGGER_FALLING |
63761 - IRQF_TRIGGER_RISING | IRQF_ONESHOT, "twl4030_usb", twl);
63762 - if (status < 0) {
63763 - dev_dbg(&pdev->dev, "can't get IRQ %d, err %d\n",
63764 - twl->irq, status);
63765 - return status;
63766 - }
63767 -
63768 - dev_info(&pdev->dev, "Initialized TWL4030 USB module\n");
63769 - return 0;
63770 -}
63771 -
63772 -static int twl4030_usb_remove(struct platform_device *pdev)
63773 -{
63774 - struct twl4030_usb *twl = platform_get_drvdata(pdev);
63775 - int val;
63776 -
63777 - cancel_delayed_work(&twl->id_workaround_work);
63778 - device_remove_file(twl->dev, &dev_attr_vbus);
63779 -
63780 - /* set transceiver mode to power on defaults */
63781 - twl4030_usb_set_mode(twl, -1);
63782 -
63783 - /* autogate 60MHz ULPI clock,
63784 - * clear dpll clock request for i2c access,
63785 - * disable 32KHz
63786 - */
63787 - val = twl4030_usb_read(twl, PHY_CLK_CTRL);
63788 - if (val >= 0) {
63789 - val |= PHY_CLK_CTRL_CLOCKGATING_EN;
63790 - val &= ~(PHY_CLK_CTRL_CLK32K_EN | REQ_PHY_DPLL_CLK);
63791 - twl4030_usb_write(twl, PHY_CLK_CTRL, (u8)val);
63792 - }
63793 -
63794 - /* disable complete OTG block */
63795 - twl4030_usb_clear_bits(twl, POWER_CTRL, POWER_CTRL_OTG_ENAB);
63796 -
63797 - if (!twl->asleep)
63798 - twl4030_phy_power(twl, 0);
63799 -
63800 - return 0;
63801 -}
63802 -
63803 -#ifdef CONFIG_OF
63804 -static const struct of_device_id twl4030_usb_id_table[] = {
63805 - { .compatible = "ti,twl4030-usb" },
63806 - {}
63807 -};
63808 -MODULE_DEVICE_TABLE(of, twl4030_usb_id_table);
63809 -#endif
63810 -
63811 -static struct platform_driver twl4030_usb_driver = {
63812 - .probe = twl4030_usb_probe,
63813 - .remove = twl4030_usb_remove,
63814 - .driver = {
63815 - .name = "twl4030_usb",
63816 - .owner = THIS_MODULE,
63817 - .of_match_table = of_match_ptr(twl4030_usb_id_table),
63818 - },
63819 -};
63820 -
63821 -static int __init twl4030_usb_init(void)
63822 -{
63823 - return platform_driver_register(&twl4030_usb_driver);
63824 -}
63825 -subsys_initcall(twl4030_usb_init);
63826 -
63827 -static void __exit twl4030_usb_exit(void)
63828 -{
63829 - platform_driver_unregister(&twl4030_usb_driver);
63830 -}
63831 -module_exit(twl4030_usb_exit);
63832 -
63833 -MODULE_ALIAS("platform:twl4030_usb");
63834 -MODULE_AUTHOR("Texas Instruments, Inc, Nokia Corporation");
63835 -MODULE_DESCRIPTION("TWL4030 USB transceiver driver");
63836 -MODULE_LICENSE("GPL");
63837 --- a/drivers/usb/phy/phy-twl6030-usb.c
63838 +++ b/drivers/usb/phy/phy-twl6030-usb.c
63839 @@ -26,13 +26,14 @@
63840 #include <linux/platform_device.h>
63841 #include <linux/io.h>
63842 #include <linux/usb/musb-omap.h>
63843 +#include <linux/phy/omap_usb.h>
63844 #include <linux/usb/phy_companion.h>
63845 -#include <linux/usb/omap_usb.h>
63846 #include <linux/i2c/twl.h>
63847 #include <linux/regulator/consumer.h>
63848 #include <linux/err.h>
63849 #include <linux/slab.h>
63850 #include <linux/delay.h>
63851 +#include <linux/of.h>
63852
63853 /* usb register definitions */
63854 #define USB_VENDOR_ID_LSB 0x00
63855 --- a/drivers/video/da8xx-fb.c
63856 +++ b/drivers/video/da8xx-fb.c
63857 @@ -19,6 +19,9 @@
63858 * along with this program; if not, write to the Free Software
63859 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
63860 */
63861 +
63862 +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
63863 +
63864 #include <linux/module.h>
63865 #include <linux/kernel.h>
63866 #include <linux/fb.h>
63867 @@ -36,9 +39,16 @@
63868 #include <linux/slab.h>
63869 #include <linux/delay.h>
63870 #include <linux/lcm.h>
63871 +#include <video/of_display_timing.h>
63872 #include <video/da8xx-fb.h>
63873 +
63874 +#ifdef CONFIG_FB_DA8XX_TDA998X
63875 +#include <video/da8xx-tda998x-hdmi.h>
63876 +#endif
63877 +
63878 #include <asm/div64.h>
63879
63880 +
63881 #define DRIVER_NAME "da8xx_lcdc"
63882
63883 #define LCD_VERSION_1 1
63884 @@ -141,6 +151,32 @@ static irq_handler_t lcdc_irq_handler;
63885 static wait_queue_head_t frame_done_wq;
63886 static int frame_done_flag;
63887
63888 +static LIST_HEAD(encoder_modules);
63889 +
63890 +void da8xx_register_encoder(struct da8xx_encoder *encoder)
63891 +{
63892 + INIT_LIST_HEAD(&encoder->list);
63893 + list_add(&encoder->list, &encoder_modules);
63894 +}
63895 +EXPORT_SYMBOL(da8xx_register_encoder);
63896 +
63897 +void da8xx_unregister_encoder(struct da8xx_encoder *encoder)
63898 +{
63899 + list_del(&encoder->list);
63900 +}
63901 +EXPORT_SYMBOL(da8xx_unregister_encoder);
63902 +
63903 +
63904 +struct da8xx_encoder *da8xx_get_encoder_from_phandle(struct device_node *node)
63905 +{
63906 + struct da8xx_encoder *entry;
63907 + list_for_each_entry(entry, &encoder_modules, list)
63908 + if (entry->node == node)
63909 + return entry;
63910 +
63911 + return 0;
63912 +}
63913 +
63914 static unsigned int lcdc_read(unsigned int addr)
63915 {
63916 return (unsigned int)__raw_readl(da8xx_fb_reg_base + (addr));
63917 @@ -161,6 +197,7 @@ struct da8xx_fb_par {
63918 unsigned int dma_start;
63919 unsigned int dma_end;
63920 struct clk *lcdc_clk;
63921 + struct clk *disp_clk;
63922 int irq;
63923 unsigned int palette_sz;
63924 int blank;
63925 @@ -182,6 +219,7 @@ struct da8xx_fb_par {
63926 u32 pseudo_palette[16];
63927 struct fb_videomode mode;
63928 struct lcd_ctrl_config cfg;
63929 + struct device_node *hdmi_node;
63930 };
63931
63932 static struct fb_var_screeninfo da8xx_fb_var;
63933 @@ -197,6 +235,9 @@ static struct fb_fix_screeninfo da8xx_fb
63934 .accel = FB_ACCEL_NONE
63935 };
63936
63937 +static vsync_callback_t vsync_cb_handler;
63938 +static void *vsync_cb_arg;
63939 +
63940 static struct fb_videomode known_lcd_panels[] = {
63941 /* Sharp LCD035Q3DG01 */
63942 [0] = {
63943 @@ -730,8 +771,8 @@ static int da8xx_fb_config_clk_divider(s
63944 }
63945
63946 static unsigned int da8xx_fb_calc_clk_divider(struct da8xx_fb_par *par,
63947 - unsigned pixclock,
63948 - unsigned *lcdc_clk_rate)
63949 + unsigned pixclock,
63950 + unsigned *lcdc_clk_rate)
63951 {
63952 unsigned lcdc_clk_div;
63953
63954 @@ -765,7 +806,7 @@ static int da8xx_fb_calc_config_clk_divi
63955 }
63956
63957 static unsigned da8xx_fb_round_clk(struct da8xx_fb_par *par,
63958 - unsigned pixclock)
63959 + unsigned pixclock)
63960 {
63961 unsigned lcdc_clk_div, lcdc_clk_rate;
63962
63963 @@ -778,11 +819,53 @@ static int lcd_init(struct da8xx_fb_par
63964 {
63965 u32 bpp;
63966 int ret = 0;
63967 + struct da8xx_encoder *enc = 0;
63968
63969 - ret = da8xx_fb_calc_config_clk_divider(par, panel);
63970 - if (IS_ERR_VALUE(ret)) {
63971 - dev_err(par->dev, "unable to configure clock\n");
63972 - return ret;
63973 + if (IS_ENABLED(CONFIG_FB_DA8XX_TDA998X) && par->hdmi_node) {
63974 + unsigned int div = 0;
63975 + unsigned long pixclock = 0;
63976 +
63977 + pr_debug("pixclock from panel %d\n", panel->pixclock);
63978 + pixclock = PICOS2KHZ(panel->pixclock) * 1000;
63979 + pr_debug("pixclock converted to hz %ld\n", pixclock);
63980 + /* remove any rounding errors as this seems to mess up clk */
63981 + pixclock = (pixclock/10000)*10000;
63982 + pr_debug("rounded clock rate %ld\n",
63983 + clk_round_rate(par->lcdc_clk, pixclock*2));
63984 + /* in raster mode, minimum divisor is 2: */
63985 + ret = clk_set_rate(par->disp_clk, pixclock * 2);
63986 + if (IS_ERR_VALUE(ret)) {
63987 + dev_err(par->dev, "failed to set display clock rate to: %ld\n",
63988 + pixclock);
63989 + return ret;
63990 + }
63991 +
63992 + par->lcdc_clk_rate = clk_get_rate(par->lcdc_clk);
63993 + div = par->lcdc_clk_rate / pixclock;
63994 +
63995 + pr_debug("lcd_clk=%u, mode clock=%ld, div=%u\n",
63996 + par->lcdc_clk_rate, pixclock, div);
63997 + pr_debug("fck=%lu, dpll_disp_ck=%lu\n",
63998 + clk_get_rate(par->lcdc_clk),
63999 + clk_get_rate(par->disp_clk));
64000 +
64001 + /* Configure the LCD clock divisor. */
64002 + lcdc_write(LCD_CLK_DIVISOR(div) |
64003 + (LCD_RASTER_MODE & 0x1), LCD_CTRL_REG);
64004 +
64005 + if (lcd_revision == LCD_VERSION_2)
64006 + lcdc_write(LCD_V2_DMA_CLK_EN | LCD_V2_LIDD_CLK_EN |
64007 + LCD_V2_CORE_CLK_EN, LCD_CLK_ENABLE_REG);
64008 + } else {
64009 + /*
64010 + * Not using external encoder, using old and more inaccurate
64011 + * method of setting the clocks.
64012 + */
64013 + ret = da8xx_fb_calc_config_clk_divider(par, panel);
64014 + if (IS_ERR_VALUE(ret)) {
64015 + dev_err(par->dev, "unable to configure clock\n");
64016 + return ret;
64017 + }
64018 }
64019
64020 if (panel->sync & FB_SYNC_CLK_INVERT)
64021 @@ -822,9 +905,45 @@ static int lcd_init(struct da8xx_fb_par
64022 lcdc_write((lcdc_read(LCD_RASTER_CTRL_REG) & 0xfff00fff) |
64023 (cfg->fdd << 12), LCD_RASTER_CTRL_REG);
64024
64025 + if (IS_ENABLED(CONFIG_FB_DA8XX_TDA998X) && par->hdmi_node) {
64026 + /*
64027 + * keep doing this lookup, because there is a posibility that
64028 + * somebody went and unloaded the encoder driver from out
64029 + * beneath us
64030 + */
64031 + enc = da8xx_get_encoder_from_phandle(par->hdmi_node);
64032 + if (enc)
64033 + enc->set_mode(enc, panel);
64034 + }
64035 return 0;
64036 }
64037
64038 +int register_vsync_cb(vsync_callback_t handler, void *arg, int idx)
64039 +{
64040 + if ((vsync_cb_handler == NULL) && (vsync_cb_arg == NULL)) {
64041 + vsync_cb_arg = arg;
64042 + vsync_cb_handler = handler;
64043 + } else {
64044 + return -EEXIST;
64045 + }
64046 +
64047 + return 0;
64048 +}
64049 +EXPORT_SYMBOL(register_vsync_cb);
64050 +
64051 +int unregister_vsync_cb(vsync_callback_t handler, void *arg, int idx)
64052 +{
64053 + if ((vsync_cb_handler == handler) && (vsync_cb_arg == arg)) {
64054 + vsync_cb_handler = NULL;
64055 + vsync_cb_arg = NULL;
64056 + } else {
64057 + return -ENXIO;
64058 + }
64059 +
64060 + return 0;
64061 +}
64062 +EXPORT_SYMBOL(unregister_vsync_cb);
64063 +
64064 /* IRQ handler for version 2 of LCDC */
64065 static irqreturn_t lcdc_irq_handler_rev02(int irq, void *arg)
64066 {
64067 @@ -862,6 +981,8 @@ static irqreturn_t lcdc_irq_handler_rev0
64068 LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
64069 par->vsync_flag = 1;
64070 wake_up_interruptible(&par->vsync_wait);
64071 + if (vsync_cb_handler)
64072 + vsync_cb_handler(vsync_cb_arg);
64073 }
64074
64075 if (stat & LCD_END_OF_FRAME1) {
64076 @@ -872,6 +993,8 @@ static irqreturn_t lcdc_irq_handler_rev0
64077 LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
64078 par->vsync_flag = 1;
64079 wake_up_interruptible(&par->vsync_wait);
64080 + if (vsync_cb_handler)
64081 + vsync_cb_handler(vsync_cb_arg);
64082 }
64083
64084 /* Set only when controller is disabled and at the end of
64085 @@ -1032,7 +1155,13 @@ static int fb_check_var(struct fb_var_sc
64086 if (var->yres + var->yoffset > var->yres_virtual)
64087 var->yoffset = var->yres_virtual - var->yres;
64088
64089 - var->pixclock = da8xx_fb_round_clk(par, var->pixclock);
64090 + /*
64091 + * if we don't have an encoder attached, use the legacy
64092 + * clock setting code that works on da8xx but is a bit
64093 + * inaccurate for the encoders on AM335x
64094 + */
64095 + if (!IS_ENABLED(CONFIG_FB_DA8XX_TDA998X) || (par->hdmi_node == 0))
64096 + var->pixclock = da8xx_fb_round_clk(par, var->pixclock);
64097
64098 return err;
64099 }
64100 @@ -1312,12 +1441,54 @@ static struct fb_ops da8xx_fb_ops = {
64101 .fb_blank = cfb_blank,
64102 };
64103
64104 +static struct lcd_ctrl_config *da8xx_fb_create_cfg(struct platform_device *dev)
64105 +{
64106 + struct lcd_ctrl_config *cfg;
64107 +
64108 + cfg = devm_kzalloc(&dev->dev, sizeof(struct fb_videomode), GFP_KERNEL);
64109 + if (!cfg)
64110 + return NULL;
64111 +
64112 + /* default values */
64113 +
64114 + if (lcd_revision == LCD_VERSION_1)
64115 + cfg->bpp = 16;
64116 + else
64117 + cfg->bpp = 32;
64118 +
64119 + /*
64120 + * For panels so far used with this LCDC, below statement is sufficient.
64121 + * For new panels, if required, struct lcd_ctrl_cfg fields to be updated
64122 + * with additional/modified values. Those values would have to be then
64123 + * obtained from dt(requiring new dt bindings).
64124 + */
64125 +
64126 + cfg->panel_shade = COLOR_ACTIVE;
64127 +
64128 + return cfg;
64129 +}
64130 +
64131 static struct fb_videomode *da8xx_fb_get_videomode(struct platform_device *dev)
64132 {
64133 struct da8xx_lcdc_platform_data *fb_pdata = dev->dev.platform_data;
64134 struct fb_videomode *lcdc_info;
64135 + struct device_node *np = dev->dev.of_node;
64136 int i;
64137
64138 + if (np) {
64139 + lcdc_info = devm_kzalloc(&dev->dev,
64140 + sizeof(struct fb_videomode),
64141 + GFP_KERNEL);
64142 + if (!lcdc_info)
64143 + return NULL;
64144 +
64145 + if (of_get_fb_videomode(np, lcdc_info, OF_USE_NATIVE_MODE)) {
64146 + dev_err(&dev->dev, "timings not available in DT\n");
64147 + return NULL;
64148 + }
64149 + return lcdc_info;
64150 + }
64151 +
64152 for (i = 0, lcdc_info = known_lcd_panels;
64153 i < ARRAY_SIZE(known_lcd_panels); i++, lcdc_info++) {
64154 if (strcmp(fb_pdata->type, lcdc_info->name) == 0)
64155 @@ -1342,15 +1513,28 @@ static int fb_probe(struct platform_devi
64156 struct fb_videomode *lcdc_info;
64157 struct fb_info *da8xx_fb_info;
64158 struct da8xx_fb_par *par;
64159 - struct clk *tmp_lcdc_clk;
64160 + struct clk *tmp_lcdc_clk, *tmp_disp_clk;
64161 int ret;
64162 unsigned long ulcm;
64163 + struct device_node *hdmi_node = NULL;
64164 +
64165
64166 - if (fb_pdata == NULL) {
64167 + if (fb_pdata == NULL && !device->dev.of_node) {
64168 dev_err(&device->dev, "Can not get platform data\n");
64169 return -ENOENT;
64170 }
64171
64172 + if (device->dev.of_node) {
64173 + hdmi_node = of_parse_phandle(device->dev.of_node,
64174 + "hdmi", 0);
64175 + if (hdmi_node &&
64176 + (da8xx_get_encoder_from_phandle(hdmi_node) == 0)) {
64177 + /* i2c encoder has not initialized yet, defer */
64178 + of_node_put(hdmi_node);
64179 + return -EPROBE_DEFER;
64180 + }
64181 + }
64182 +
64183 lcdc_info = da8xx_fb_get_videomode(device);
64184 if (lcdc_info == NULL)
64185 return -ENODEV;
64186 @@ -1366,6 +1550,12 @@ static int fb_probe(struct platform_devi
64187 return PTR_ERR(tmp_lcdc_clk);
64188 }
64189
64190 + tmp_disp_clk = devm_clk_get(&device->dev, "dpll_disp_ck");
64191 + if (IS_ERR(tmp_disp_clk)) {
64192 + /* we can live if dpll_disp_ck is not available */
64193 + tmp_disp_clk = 0;
64194 + }
64195 +
64196 pm_runtime_enable(&device->dev);
64197 pm_runtime_get_sync(&device->dev);
64198
64199 @@ -1386,7 +1576,10 @@ static int fb_probe(struct platform_devi
64200 break;
64201 }
64202
64203 - lcd_cfg = (struct lcd_ctrl_config *)fb_pdata->controller_data;
64204 + if (device->dev.of_node)
64205 + lcd_cfg = da8xx_fb_create_cfg(device);
64206 + else
64207 + lcd_cfg = fb_pdata->controller_data;
64208
64209 if (!lcd_cfg) {
64210 ret = -EINVAL;
64211 @@ -1405,11 +1598,16 @@ static int fb_probe(struct platform_devi
64212 par->dev = &device->dev;
64213 par->lcdc_clk = tmp_lcdc_clk;
64214 par->lcdc_clk_rate = clk_get_rate(par->lcdc_clk);
64215 - if (fb_pdata->panel_power_ctrl) {
64216 + par->disp_clk = tmp_disp_clk;
64217 +
64218 + if (fb_pdata && fb_pdata->panel_power_ctrl) {
64219 par->panel_power_ctrl = fb_pdata->panel_power_ctrl;
64220 par->panel_power_ctrl(1);
64221 }
64222
64223 + if (device->dev.of_node)
64224 + par->hdmi_node = hdmi_node;
64225 +
64226 fb_videomode_to_var(&da8xx_fb_var, lcdc_info);
64227 par->cfg = *lcd_cfg;
64228
64229 @@ -1653,6 +1851,19 @@ static int fb_resume(struct platform_dev
64230 #define fb_resume NULL
64231 #endif
64232
64233 +#if IS_ENABLED(CONFIG_OF)
64234 +static const struct of_device_id da8xx_fb_of_match[] = {
64235 + /*
64236 + * this driver supports version 1 and version 2 of the
64237 + * Texas Instruments lcd controller (lcdc) hardware block
64238 + */
64239 + {.compatible = "ti,da8xx-tilcdc", },
64240 + {.compatible = "ti,am33xx-tilcdc", },
64241 + {},
64242 +};
64243 +MODULE_DEVICE_TABLE(of, da8xx_fb_of_match);
64244 +#endif
64245 +
64246 static struct platform_driver da8xx_fb_driver = {
64247 .probe = fb_probe,
64248 .remove = fb_remove,
64249 @@ -1661,6 +1872,7 @@ static struct platform_driver da8xx_fb_d
64250 .driver = {
64251 .name = DRIVER_NAME,
64252 .owner = THIS_MODULE,
64253 + .of_match_table = of_match_ptr(da8xx_fb_of_match),
64254 },
64255 };
64256
64257 --- /dev/null
64258 +++ b/drivers/video/da8xx-tda998x-hdmi.c
64259 @@ -0,0 +1,840 @@
64260 +/*
64261 + * Copyright (C) 2012 Texas Instruments
64262 + * Author: Rob Clark <robdclark@gmail.com>
64263 + * Author: Darren Etheridge <detheridge@ti.com>
64264 + *
64265 + * This program is free software; you can redistribute it and/or modify it
64266 + * under the terms of the GNU General Public License version 2 as published by
64267 + * the Free Software Foundation.
64268 + *
64269 + * This program is distributed in the hope that it will be useful, but WITHOUT
64270 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
64271 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
64272 + * more details.
64273 + *
64274 + * You should have received a copy of the GNU General Public License along with
64275 + * this program. If not, see <http://www.gnu.org/licenses/>.
64276 + */
64277 +
64278 +
64279 +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
64280 +
64281 +
64282 +#include <linux/module.h>
64283 +#include <linux/i2c.h>
64284 +#include <linux/slab.h>
64285 +#include <linux/delay.h>
64286 +#include <video/da8xx-fb.h>
64287 +#include <video/da8xx-tda998x-hdmi.h>
64288 +
64289 +#define TDA998X_DEBUG
64290 +
64291 +#ifdef TDA998X_DEBUG
64292 +#define DBG(fmt, ...) printk(KERN_DEBUG "%s: " fmt, __func__, ##__VA_ARGS__)
64293 +#else
64294 +#define DBG(fmt, ...)
64295 +#endif
64296 +
64297 +
64298 +#define tda998x_encoder da8xx_encoder
64299 +
64300 +struct tda998x_priv {
64301 + struct i2c_client *cec;
64302 + uint16_t rev;
64303 + uint8_t current_page;
64304 + int dpms;
64305 + bool is_hdmi_sink;
64306 + u8 vip_cntrl_0;
64307 + u8 vip_cntrl_1;
64308 + u8 vip_cntrl_2;
64309 + struct tda998x_encoder_params params;
64310 +};
64311 +
64312 +#define to_tda998x_priv(x) ((struct tda998x_priv *)x->priv)
64313 +#define tda998x_i2c_encoder_get_client(x) ((struct i2c_client *)x->client)
64314 +
64315 +/* The TDA9988 series of devices use a paged register scheme.. to simplify
64316 + * things we encode the page # in upper bits of the register #. To read/
64317 + * write a given register, we need to make sure CURPAGE register is set
64318 + * appropriately. Which implies reads/writes are not atomic. Fun!
64319 + */
64320 +
64321 +#define REG(page, addr) (((page) << 8) | (addr))
64322 +#define REG2ADDR(reg) ((reg) & 0xff)
64323 +#define REG2PAGE(reg) (((reg) >> 8) & 0xff)
64324 +
64325 +#define REG_CURPAGE 0xff /* write */
64326 +
64327 +
64328 +/* Page 00h: General Control */
64329 +#define REG_VERSION_LSB REG(0x00, 0x00) /* read */
64330 +#define REG_MAIN_CNTRL0 REG(0x00, 0x01) /* read/write */
64331 +# define MAIN_CNTRL0_SR (1 << 0)
64332 +# define MAIN_CNTRL0_DECS (1 << 1)
64333 +# define MAIN_CNTRL0_DEHS (1 << 2)
64334 +# define MAIN_CNTRL0_CECS (1 << 3)
64335 +# define MAIN_CNTRL0_CEHS (1 << 4)
64336 +# define MAIN_CNTRL0_SCALER (1 << 7)
64337 +#define REG_VERSION_MSB REG(0x00, 0x02) /* read */
64338 +#define REG_SOFTRESET REG(0x00, 0x0a) /* write */
64339 +# define SOFTRESET_AUDIO (1 << 0)
64340 +# define SOFTRESET_I2C_MASTER (1 << 1)
64341 +#define REG_DDC_DISABLE REG(0x00, 0x0b) /* read/write */
64342 +#define REG_CCLK_ON REG(0x00, 0x0c) /* read/write */
64343 +#define REG_I2C_MASTER REG(0x00, 0x0d) /* read/write */
64344 +# define I2C_MASTER_DIS_MM (1 << 0)
64345 +# define I2C_MASTER_DIS_FILT (1 << 1)
64346 +# define I2C_MASTER_APP_STRT_LAT (1 << 2)
64347 +#define REG_FEAT_POWERDOWN REG(0x00, 0x0e) /* read/write */
64348 +# define FEAT_POWERDOWN_SPDIF (1 << 3)
64349 +#define REG_INT_FLAGS_0 REG(0x00, 0x0f) /* read/write */
64350 +#define REG_INT_FLAGS_1 REG(0x00, 0x10) /* read/write */
64351 +#define REG_INT_FLAGS_2 REG(0x00, 0x11) /* read/write */
64352 +# define INT_FLAGS_2_EDID_BLK_RD (1 << 1)
64353 +#define REG_ENA_ACLK REG(0x00, 0x16) /* read/write */
64354 +#define REG_ENA_VP_0 REG(0x00, 0x18) /* read/write */
64355 +#define REG_ENA_VP_1 REG(0x00, 0x19) /* read/write */
64356 +#define REG_ENA_VP_2 REG(0x00, 0x1a) /* read/write */
64357 +#define REG_ENA_AP REG(0x00, 0x1e) /* read/write */
64358 +#define REG_VIP_CNTRL_0 REG(0x00, 0x20) /* write */
64359 +# define VIP_CNTRL_0_MIRR_A (1 << 7)
64360 +# define VIP_CNTRL_0_SWAP_A(x) (((x) & 7) << 4)
64361 +# define VIP_CNTRL_0_MIRR_B (1 << 3)
64362 +# define VIP_CNTRL_0_SWAP_B(x) (((x) & 7) << 0)
64363 +#define REG_VIP_CNTRL_1 REG(0x00, 0x21) /* write */
64364 +# define VIP_CNTRL_1_MIRR_C (1 << 7)
64365 +# define VIP_CNTRL_1_SWAP_C(x) (((x) & 7) << 4)
64366 +# define VIP_CNTRL_1_MIRR_D (1 << 3)
64367 +# define VIP_CNTRL_1_SWAP_D(x) (((x) & 7) << 0)
64368 +#define REG_VIP_CNTRL_2 REG(0x00, 0x22) /* write */
64369 +# define VIP_CNTRL_2_MIRR_E (1 << 7)
64370 +# define VIP_CNTRL_2_SWAP_E(x) (((x) & 7) << 4)
64371 +# define VIP_CNTRL_2_MIRR_F (1 << 3)
64372 +# define VIP_CNTRL_2_SWAP_F(x) (((x) & 7) << 0)
64373 +#define REG_VIP_CNTRL_3 REG(0x00, 0x23) /* write */
64374 +# define VIP_CNTRL_3_X_TGL (1 << 0)
64375 +# define VIP_CNTRL_3_H_TGL (1 << 1)
64376 +# define VIP_CNTRL_3_V_TGL (1 << 2)
64377 +# define VIP_CNTRL_3_EMB (1 << 3)
64378 +# define VIP_CNTRL_3_SYNC_DE (1 << 4)
64379 +# define VIP_CNTRL_3_SYNC_HS (1 << 5)
64380 +# define VIP_CNTRL_3_DE_INT (1 << 6)
64381 +# define VIP_CNTRL_3_EDGE (1 << 7)
64382 +#define REG_VIP_CNTRL_4 REG(0x00, 0x24) /* write */
64383 +# define VIP_CNTRL_4_BLC(x) (((x) & 3) << 0)
64384 +# define VIP_CNTRL_4_BLANKIT(x) (((x) & 3) << 2)
64385 +# define VIP_CNTRL_4_CCIR656 (1 << 4)
64386 +# define VIP_CNTRL_4_656_ALT (1 << 5)
64387 +# define VIP_CNTRL_4_TST_656 (1 << 6)
64388 +# define VIP_CNTRL_4_TST_PAT (1 << 7)
64389 +#define REG_VIP_CNTRL_5 REG(0x00, 0x25) /* write */
64390 +# define VIP_CNTRL_5_CKCASE (1 << 0)
64391 +# define VIP_CNTRL_5_SP_CNT(x) (((x) & 3) << 1)
64392 +#define REG_MUX_AP REG(0x00, 0x26) /* read/write */
64393 +#define REG_MUX_VP_VIP_OUT REG(0x00, 0x27) /* read/write */
64394 +#define REG_MAT_CONTRL REG(0x00, 0x80) /* write */
64395 +# define MAT_CONTRL_MAT_SC(x) (((x) & 3) << 0)
64396 +# define MAT_CONTRL_MAT_BP (1 << 2)
64397 +#define REG_VIDFORMAT REG(0x00, 0xa0) /* write */
64398 +#define REG_REFPIX_MSB REG(0x00, 0xa1) /* write */
64399 +#define REG_REFPIX_LSB REG(0x00, 0xa2) /* write */
64400 +#define REG_REFLINE_MSB REG(0x00, 0xa3) /* write */
64401 +#define REG_REFLINE_LSB REG(0x00, 0xa4) /* write */
64402 +#define REG_NPIX_MSB REG(0x00, 0xa5) /* write */
64403 +#define REG_NPIX_LSB REG(0x00, 0xa6) /* write */
64404 +#define REG_NLINE_MSB REG(0x00, 0xa7) /* write */
64405 +#define REG_NLINE_LSB REG(0x00, 0xa8) /* write */
64406 +#define REG_VS_LINE_STRT_1_MSB REG(0x00, 0xa9) /* write */
64407 +#define REG_VS_LINE_STRT_1_LSB REG(0x00, 0xaa) /* write */
64408 +#define REG_VS_PIX_STRT_1_MSB REG(0x00, 0xab) /* write */
64409 +#define REG_VS_PIX_STRT_1_LSB REG(0x00, 0xac) /* write */
64410 +#define REG_VS_LINE_END_1_MSB REG(0x00, 0xad) /* write */
64411 +#define REG_VS_LINE_END_1_LSB REG(0x00, 0xae) /* write */
64412 +#define REG_VS_PIX_END_1_MSB REG(0x00, 0xaf) /* write */
64413 +#define REG_VS_PIX_END_1_LSB REG(0x00, 0xb0) /* write */
64414 +#define REG_VS_LINE_STRT_2_MSB REG(0x00, 0xb1) /* write */
64415 +#define REG_VS_LINE_STRT_2_LSB REG(0x00, 0xb2) /* write */
64416 +#define REG_VS_PIX_STRT_2_MSB REG(0x00, 0xb3) /* write */
64417 +#define REG_VS_PIX_STRT_2_LSB REG(0x00, 0xb4) /* write */
64418 +#define REG_VS_LINE_END_2_MSB REG(0x00, 0xb5) /* write */
64419 +#define REG_VS_LINE_END_2_LSB REG(0x00, 0xb6) /* write */
64420 +#define REG_VS_PIX_END_2_MSB REG(0x00, 0xb7) /* write */
64421 +#define REG_VS_PIX_END_2_LSB REG(0x00, 0xb8) /* write */
64422 +#define REG_HS_PIX_START_MSB REG(0x00, 0xb9) /* write */
64423 +#define REG_HS_PIX_START_LSB REG(0x00, 0xba) /* write */
64424 +#define REG_HS_PIX_STOP_MSB REG(0x00, 0xbb) /* write */
64425 +#define REG_HS_PIX_STOP_LSB REG(0x00, 0xbc) /* write */
64426 +#define REG_VWIN_START_1_MSB REG(0x00, 0xbd) /* write */
64427 +#define REG_VWIN_START_1_LSB REG(0x00, 0xbe) /* write */
64428 +#define REG_VWIN_END_1_MSB REG(0x00, 0xbf) /* write */
64429 +#define REG_VWIN_END_1_LSB REG(0x00, 0xc0) /* write */
64430 +#define REG_VWIN_START_2_MSB REG(0x00, 0xc1) /* write */
64431 +#define REG_VWIN_START_2_LSB REG(0x00, 0xc2) /* write */
64432 +#define REG_VWIN_END_2_MSB REG(0x00, 0xc3) /* write */
64433 +#define REG_VWIN_END_2_LSB REG(0x00, 0xc4) /* write */
64434 +#define REG_DE_START_MSB REG(0x00, 0xc5) /* write */
64435 +#define REG_DE_START_LSB REG(0x00, 0xc6) /* write */
64436 +#define REG_DE_STOP_MSB REG(0x00, 0xc7) /* write */
64437 +#define REG_DE_STOP_LSB REG(0x00, 0xc8) /* write */
64438 +#define REG_TBG_CNTRL_0 REG(0x00, 0xca) /* write */
64439 +# define TBG_CNTRL_0_TOP_TGL (1 << 0)
64440 +# define TBG_CNTRL_0_TOP_SEL (1 << 1)
64441 +# define TBG_CNTRL_0_DE_EXT (1 << 2)
64442 +# define TBG_CNTRL_0_TOP_EXT (1 << 3)
64443 +# define TBG_CNTRL_0_FRAME_DIS (1 << 5)
64444 +# define TBG_CNTRL_0_SYNC_MTHD (1 << 6)
64445 +# define TBG_CNTRL_0_SYNC_ONCE (1 << 7)
64446 +#define REG_TBG_CNTRL_1 REG(0x00, 0xcb) /* write */
64447 +# define TBG_CNTRL_1_H_TGL (1 << 0)
64448 +# define TBG_CNTRL_1_V_TGL (1 << 1)
64449 +# define TBG_CNTRL_1_TGL_EN (1 << 2)
64450 +# define TBG_CNTRL_1_X_EXT (1 << 3)
64451 +# define TBG_CNTRL_1_H_EXT (1 << 4)
64452 +# define TBG_CNTRL_1_V_EXT (1 << 5)
64453 +# define TBG_CNTRL_1_DWIN_DIS (1 << 6)
64454 +#define REG_ENABLE_SPACE REG(0x00, 0xd6) /* write */
64455 +#define REG_HVF_CNTRL_0 REG(0x00, 0xe4) /* write */
64456 +# define HVF_CNTRL_0_SM (1 << 7)
64457 +# define HVF_CNTRL_0_RWB (1 << 6)
64458 +# define HVF_CNTRL_0_PREFIL(x) (((x) & 3) << 2)
64459 +# define HVF_CNTRL_0_INTPOL(x) (((x) & 3) << 0)
64460 +#define REG_HVF_CNTRL_1 REG(0x00, 0xe5) /* write */
64461 +# define HVF_CNTRL_1_FOR (1 << 0)
64462 +# define HVF_CNTRL_1_YUVBLK (1 << 1)
64463 +# define HVF_CNTRL_1_VQR(x) (((x) & 3) << 2)
64464 +# define HVF_CNTRL_1_PAD(x) (((x) & 3) << 4)
64465 +# define HVF_CNTRL_1_SEMI_PLANAR (1 << 6)
64466 +#define REG_RPT_CNTRL REG(0x00, 0xf0) /* write */
64467 +#define REG_I2S_FORMAT REG(0x00, 0xfc) /* read/write */
64468 +# define I2S_FORMAT(x) (((x) & 3) << 0)
64469 +#define REG_AIP_CLKSEL REG(0x00, 0xfd) /* write */
64470 +# define AIP_CLKSEL_FS(x) (((x) & 3) << 0)
64471 +# define AIP_CLKSEL_CLK_POL(x) (((x) & 1) << 2)
64472 +# define AIP_CLKSEL_AIP(x) (((x) & 7) << 3)
64473 +
64474 +
64475 +/* Page 02h: PLL settings */
64476 +#define REG_PLL_SERIAL_1 REG(0x02, 0x00) /* read/write */
64477 +# define PLL_SERIAL_1_SRL_FDN (1 << 0)
64478 +# define PLL_SERIAL_1_SRL_IZ(x) (((x) & 3) << 1)
64479 +# define PLL_SERIAL_1_SRL_MAN_IZ (1 << 6)
64480 +#define REG_PLL_SERIAL_2 REG(0x02, 0x01) /* read/write */
64481 +# define PLL_SERIAL_2_SRL_NOSC(x) (((x) & 3) << 0)
64482 +# define PLL_SERIAL_2_SRL_PR(x) (((x) & 0xf) << 4)
64483 +#define REG_PLL_SERIAL_3 REG(0x02, 0x02) /* read/write */
64484 +# define PLL_SERIAL_3_SRL_CCIR (1 << 0)
64485 +# define PLL_SERIAL_3_SRL_DE (1 << 2)
64486 +# define PLL_SERIAL_3_SRL_PXIN_SEL (1 << 4)
64487 +#define REG_SERIALIZER REG(0x02, 0x03) /* read/write */
64488 +#define REG_BUFFER_OUT REG(0x02, 0x04) /* read/write */
64489 +#define REG_PLL_SCG1 REG(0x02, 0x05) /* read/write */
64490 +#define REG_PLL_SCG2 REG(0x02, 0x06) /* read/write */
64491 +#define REG_PLL_SCGN1 REG(0x02, 0x07) /* read/write */
64492 +#define REG_PLL_SCGN2 REG(0x02, 0x08) /* read/write */
64493 +#define REG_PLL_SCGR1 REG(0x02, 0x09) /* read/write */
64494 +#define REG_PLL_SCGR2 REG(0x02, 0x0a) /* read/write */
64495 +#define REG_AUDIO_DIV REG(0x02, 0x0e) /* read/write */
64496 +#define REG_SEL_CLK REG(0x02, 0x11) /* read/write */
64497 +# define SEL_CLK_SEL_CLK1 (1 << 0)
64498 +# define SEL_CLK_SEL_VRF_CLK(x) (((x) & 3) << 1)
64499 +# define SEL_CLK_ENA_SC_CLK (1 << 3)
64500 +#define REG_ANA_GENERAL REG(0x02, 0x12) /* read/write */
64501 +
64502 +
64503 +/* Page 09h: EDID Control */
64504 +#define REG_EDID_DATA_0 REG(0x09, 0x00) /* read */
64505 +/* next 127 successive registers are the EDID block */
64506 +#define REG_EDID_CTRL REG(0x09, 0xfa) /* read/write */
64507 +#define REG_DDC_ADDR REG(0x09, 0xfb) /* read/write */
64508 +#define REG_DDC_OFFS REG(0x09, 0xfc) /* read/write */
64509 +#define REG_DDC_SEGM_ADDR REG(0x09, 0xfd) /* read/write */
64510 +#define REG_DDC_SEGM REG(0x09, 0xfe) /* read/write */
64511 +
64512 +
64513 +/* Page 10h: information frames and packets */
64514 +#define REG_IF1_HB0 REG(0x10, 0x20) /* read/write */
64515 +#define REG_IF2_HB0 REG(0x10, 0x40) /* read/write */
64516 +#define REG_IF3_HB0 REG(0x10, 0x60) /* read/write */
64517 +#define REG_IF4_HB0 REG(0x10, 0x80) /* read/write */
64518 +#define REG_IF5_HB0 REG(0x10, 0xa0) /* read/write */
64519 +
64520 +
64521 +/* Page 11h: audio settings and content info packets */
64522 +#define REG_AIP_CNTRL_0 REG(0x11, 0x00) /* read/write */
64523 +# define AIP_CNTRL_0_RST_FIFO (1 << 0)
64524 +# define AIP_CNTRL_0_SWAP (1 << 1)
64525 +# define AIP_CNTRL_0_LAYOUT (1 << 2)
64526 +# define AIP_CNTRL_0_ACR_MAN (1 << 5)
64527 +# define AIP_CNTRL_0_RST_CTS (1 << 6)
64528 +#define REG_CA_I2S REG(0x11, 0x01) /* read/write */
64529 +# define CA_I2S_CA_I2S(x) (((x) & 31) << 0)
64530 +# define CA_I2S_HBR_CHSTAT (1 << 6)
64531 +#define REG_LATENCY_RD REG(0x11, 0x04) /* read/write */
64532 +#define REG_ACR_CTS_0 REG(0x11, 0x05) /* read/write */
64533 +#define REG_ACR_CTS_1 REG(0x11, 0x06) /* read/write */
64534 +#define REG_ACR_CTS_2 REG(0x11, 0x07) /* read/write */
64535 +#define REG_ACR_N_0 REG(0x11, 0x08) /* read/write */
64536 +#define REG_ACR_N_1 REG(0x11, 0x09) /* read/write */
64537 +#define REG_ACR_N_2 REG(0x11, 0x0a) /* read/write */
64538 +#define REG_CTS_N REG(0x11, 0x0c) /* read/write */
64539 +# define CTS_N_K(x) (((x) & 7) << 0)
64540 +# define CTS_N_M(x) (((x) & 3) << 4)
64541 +#define REG_ENC_CNTRL REG(0x11, 0x0d) /* read/write */
64542 +# define ENC_CNTRL_RST_ENC (1 << 0)
64543 +# define ENC_CNTRL_RST_SEL (1 << 1)
64544 +# define ENC_CNTRL_CTL_CODE(x) (((x) & 3) << 2)
64545 +#define REG_DIP_FLAGS REG(0x11, 0x0e) /* read/write */
64546 +# define DIP_FLAGS_ACR (1 << 0)
64547 +# define DIP_FLAGS_GC (1 << 1)
64548 +#define REG_DIP_IF_FLAGS REG(0x11, 0x0f) /* read/write */
64549 +# define DIP_IF_FLAGS_IF1 (1 << 1)
64550 +# define DIP_IF_FLAGS_IF2 (1 << 2)
64551 +# define DIP_IF_FLAGS_IF3 (1 << 3)
64552 +# define DIP_IF_FLAGS_IF4 (1 << 4)
64553 +# define DIP_IF_FLAGS_IF5 (1 << 5)
64554 +#define REG_CH_STAT_B(x) REG(0x11, 0x14 + (x)) /* read/write */
64555 +
64556 +
64557 +/* Page 12h: HDCP and OTP */
64558 +#define REG_TX3 REG(0x12, 0x9a) /* read/write */
64559 +#define REG_TX4 REG(0x12, 0x9b) /* read/write */
64560 +# define TX4_PD_RAM (1 << 1)
64561 +#define REG_TX33 REG(0x12, 0xb8) /* read/write */
64562 +# define TX33_HDMI (1 << 1)
64563 +
64564 +
64565 +/* Page 13h: Gamut related metadata packets */
64566 +
64567 +
64568 +
64569 +/* CEC registers: (not paged)
64570 + */
64571 +#define REG_CEC_FRO_IM_CLK_CTRL 0xfb /* read/write */
64572 +# define CEC_FRO_IM_CLK_CTRL_GHOST_DIS (1 << 7)
64573 +# define CEC_FRO_IM_CLK_CTRL_ENA_OTP (1 << 6)
64574 +# define CEC_FRO_IM_CLK_CTRL_IMCLK_SEL (1 << 1)
64575 +# define CEC_FRO_IM_CLK_CTRL_FRO_DIV (1 << 0)
64576 +#define REG_CEC_RXSHPDLEV 0xfe /* read */
64577 +# define CEC_RXSHPDLEV_RXSENS (1 << 0)
64578 +# define CEC_RXSHPDLEV_HPD (1 << 1)
64579 +
64580 +#define REG_CEC_ENAMODS 0xff /* read/write */
64581 +# define CEC_ENAMODS_DIS_FRO (1 << 6)
64582 +# define CEC_ENAMODS_DIS_CCLK (1 << 5)
64583 +# define CEC_ENAMODS_EN_RXSENS (1 << 2)
64584 +# define CEC_ENAMODS_EN_HDMI (1 << 1)
64585 +# define CEC_ENAMODS_EN_CEC (1 << 0)
64586 +
64587 +
64588 +/* Device versions: */
64589 +#define TDA9989N2 0x0101
64590 +#define TDA19989 0x0201
64591 +#define TDA19989N2 0x0202
64592 +#define TDA19988 0x0301
64593 +
64594 +static void
64595 +cec_write(struct tda998x_encoder *encoder, uint16_t addr, uint8_t val)
64596 +{
64597 + struct i2c_client *client = to_tda998x_priv(encoder)->cec;
64598 + uint8_t buf[] = {addr, val};
64599 + int ret;
64600 +
64601 + ret = i2c_master_send(client, buf, ARRAY_SIZE(buf));
64602 + if (ret < 0)
64603 + dev_err(&client->dev, "Error %d writing to cec:0x%x\n",
64604 + ret, addr);
64605 +}
64606 +
64607 +static void
64608 +set_page(struct tda998x_encoder *encoder, uint16_t reg)
64609 +{
64610 + struct tda998x_priv *priv = to_tda998x_priv(encoder);
64611 +
64612 + if (REG2PAGE(reg) != priv->current_page) {
64613 + struct i2c_client *client =
64614 + tda998x_i2c_encoder_get_client(encoder);
64615 + uint8_t buf[] = {
64616 + REG_CURPAGE, REG2PAGE(reg)
64617 + };
64618 + int ret = i2c_master_send(client, buf, sizeof(buf));
64619 + if (ret < 0)
64620 + dev_err(&client->dev,
64621 + "Error %d writing to REG_CURPAGE\n", ret);
64622 +
64623 + priv->current_page = REG2PAGE(reg);
64624 + }
64625 +}
64626 +
64627 +static int
64628 +reg_read_range(struct tda998x_encoder *encoder,
64629 + uint16_t reg, char *buf, int cnt)
64630 +{
64631 + struct i2c_client *client = tda998x_i2c_encoder_get_client(encoder);
64632 + uint8_t addr = REG2ADDR(reg);
64633 + int ret;
64634 +
64635 + set_page(encoder, reg);
64636 +
64637 + ret = i2c_master_send(client, &addr, sizeof(addr));
64638 + if (ret < 0)
64639 + goto fail;
64640 +
64641 + ret = i2c_master_recv(client, buf, cnt);
64642 + if (ret < 0)
64643 + goto fail;
64644 +
64645 + return ret;
64646 +
64647 +fail:
64648 + dev_err(&client->dev, "Error %d reading from 0x%x\n", ret, reg);
64649 + return ret;
64650 +}
64651 +
64652 +static uint8_t
64653 +reg_read(struct tda998x_encoder *encoder, uint16_t reg)
64654 +{
64655 + uint8_t val = 0;
64656 + reg_read_range(encoder, reg, &val, sizeof(val));
64657 + return val;
64658 +}
64659 +
64660 +static void
64661 +reg_write(struct tda998x_encoder *encoder, uint16_t reg, uint8_t val)
64662 +{
64663 + struct i2c_client *client = tda998x_i2c_encoder_get_client(encoder);
64664 + uint8_t buf[] = {REG2ADDR(reg), val};
64665 + int ret;
64666 +
64667 + set_page(encoder, reg);
64668 +
64669 + ret = i2c_master_send(client, buf, ARRAY_SIZE(buf));
64670 + if (ret < 0)
64671 + dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
64672 +}
64673 +
64674 +static void
64675 +reg_write16(struct tda998x_encoder *encoder, uint16_t reg, uint16_t val)
64676 +{
64677 + struct i2c_client *client = tda998x_i2c_encoder_get_client(encoder);
64678 + uint8_t buf[] = {REG2ADDR(reg), val >> 8, val};
64679 + int ret;
64680 +
64681 + set_page(encoder, reg);
64682 +
64683 + ret = i2c_master_send(client, buf, ARRAY_SIZE(buf));
64684 + if (ret < 0)
64685 + dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
64686 +}
64687 +
64688 +static void
64689 +reg_set(struct tda998x_encoder *encoder, uint16_t reg, uint8_t val)
64690 +{
64691 + reg_write(encoder, reg, reg_read(encoder, reg) | val);
64692 +}
64693 +
64694 +static void
64695 +reg_clear(struct tda998x_encoder *encoder, uint16_t reg, uint8_t val)
64696 +{
64697 + reg_write(encoder, reg, reg_read(encoder, reg) & ~val);
64698 +}
64699 +
64700 +static void
64701 +tda998x_reset(struct tda998x_encoder *encoder)
64702 +{
64703 + /* reset audio and i2c master: */
64704 + reg_set(encoder, REG_SOFTRESET, SOFTRESET_AUDIO | SOFTRESET_I2C_MASTER);
64705 + msleep(50);
64706 + reg_clear(encoder, REG_SOFTRESET,
64707 + SOFTRESET_AUDIO | SOFTRESET_I2C_MASTER);
64708 + msleep(50);
64709 +
64710 + /* reset transmitter: */
64711 + reg_set(encoder, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR);
64712 + reg_clear(encoder, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR);
64713 +
64714 + /* PLL registers common configuration */
64715 + reg_write(encoder, REG_PLL_SERIAL_1, 0x00);
64716 + reg_write(encoder, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(1));
64717 + reg_write(encoder, REG_PLL_SERIAL_3, 0x00);
64718 + reg_write(encoder, REG_SERIALIZER, 0x00);
64719 + reg_write(encoder, REG_BUFFER_OUT, 0x00);
64720 + reg_write(encoder, REG_PLL_SCG1, 0x00);
64721 + reg_write(encoder, REG_AUDIO_DIV, 0x03);
64722 + reg_write(encoder, REG_SEL_CLK,
64723 + SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK);
64724 + reg_write(encoder, REG_PLL_SCGN1, 0xfa);
64725 + reg_write(encoder, REG_PLL_SCGN2, 0x00);
64726 + reg_write(encoder, REG_PLL_SCGR1, 0x5b);
64727 + reg_write(encoder, REG_PLL_SCGR2, 0x00);
64728 + reg_write(encoder, REG_PLL_SCG2, 0x10);
64729 +}
64730 +
64731 +struct tda_mode {
64732 + uint32_t clock;
64733 + uint32_t vrefresh;
64734 + uint32_t hdisplay;
64735 + uint32_t hsync_start;
64736 + uint32_t hsync_end;
64737 + uint32_t htotal;
64738 + uint32_t vdisplay;
64739 + uint32_t vsync_start;
64740 + uint32_t vsync_end;
64741 + uint32_t vtotal;
64742 + uint32_t flags;
64743 + uint32_t hskew;
64744 +};
64745 +
64746 +static void convert_to_display_mode(struct tda_mode *mode,
64747 + struct fb_videomode *timing)
64748 +{
64749 + mode->clock = (PICOS2KHZ(timing->pixclock)/10)*10;
64750 + mode->vrefresh = timing->refresh;
64751 +
64752 + mode->hdisplay = timing->xres;
64753 + mode->hsync_start = mode->hdisplay + timing->right_margin;
64754 + mode->hsync_end = mode->hsync_start + timing->hsync_len;
64755 + mode->htotal = mode->hsync_end + timing->left_margin;
64756 +
64757 + mode->vdisplay = timing->yres;
64758 + mode->vsync_start = mode->vdisplay + timing->lower_margin;
64759 + mode->vsync_end = mode->vsync_start + timing->vsync_len;
64760 + mode->vtotal = mode->vsync_end + timing->upper_margin;
64761 +
64762 + mode->flags = timing->sync;
64763 +
64764 +
64765 +
64766 + pr_debug("mode->htotal %d, mode->vtotal %d, mode->flags %x\n",
64767 + mode->htotal, mode->vtotal, mode->flags);
64768 + pr_debug("mode->clock %d\n", mode->clock);
64769 + pr_debug("mode->vrefresh %d\n", mode->vrefresh);
64770 + pr_debug("mode->hdisplay %d\n", mode->hdisplay);
64771 + pr_debug("mode->hsync_start %d\n", mode->hsync_start);
64772 + pr_debug("mode->hsync_end %d\n", mode->hsync_end);
64773 + pr_debug("mode->vdisplay %d\n", mode->vdisplay);
64774 + pr_debug("mode->vsync_start %d\n", mode->vsync_start);
64775 + pr_debug("mode->vsync_end %d\n", mode->vsync_end);
64776 +
64777 + /*
64778 + * this is a workaround to fix up the mode so that the non-vesa
64779 + * compliant LCD controller can work with the NXP HDMI encoder
64780 + * we invert the horizontal sync pulse, and then add some hskew
64781 + * to move the picture to the right on the screen by a sync pulse
64782 + * worth of pixels
64783 + */
64784 + mode->hskew = mode->hsync_end - mode->hsync_start;
64785 + mode->flags ^= FB_SYNC_HOR_HIGH_ACT;
64786 +
64787 + pr_debug("mode->hskew %d\n", mode->hskew);
64788 +
64789 +}
64790 +
64791 +
64792 +void da8xx_tda998x_setmode(struct tda998x_encoder *encoder,
64793 + struct fb_videomode *vid_mode)
64794 +{
64795 + struct tda998x_priv *priv = to_tda998x_priv(encoder);
64796 + uint16_t ref_pix, ref_line, n_pix, n_line;
64797 + uint16_t hs_pix_s, hs_pix_e;
64798 + uint16_t vs1_pix_s, vs1_pix_e, vs1_line_s, vs1_line_e;
64799 + uint16_t vs2_pix_s, vs2_pix_e, vs2_line_s, vs2_line_e;
64800 + uint16_t vwin1_line_s, vwin1_line_e;
64801 + uint16_t vwin2_line_s, vwin2_line_e;
64802 + uint16_t de_pix_s, de_pix_e;
64803 + uint8_t reg, div, rep;
64804 + struct tda_mode tda_mode;
64805 + struct tda_mode *mode = &tda_mode;
64806 +
64807 + convert_to_display_mode(mode, vid_mode);
64808 +
64809 + /*
64810 + * Internally TDA998x is using ITU-R BT.656 style sync but
64811 + * we get VESA style sync. TDA998x is using a reference pixel
64812 + * relative to ITU to sync to the input frame and for output
64813 + * sync generation.
64814 + *
64815 + * Now there is some issues to take care of:
64816 + * - HDMI data islands require sync-before-active
64817 + * - TDA998x register values must be > 0 to be enabled
64818 + * - REFLINE needs an additional offset of +1
64819 + * - REFPIX needs an addtional offset of +1 for UYUV and +3 for RGB
64820 + *
64821 + * So we add +1 to all horizontal and vertical register values,
64822 + * plus an additional +3 for REFPIX as we are using RGB input only.
64823 + */
64824 + n_pix = mode->htotal;
64825 + n_line = mode->vtotal;
64826 +
64827 + ref_pix = 3 + mode->hsync_start - mode->hdisplay;
64828 +
64829 + /*
64830 + * handle issue on TILCDC where it is outputing
64831 + * non-VESA compliant sync signals the workaround
64832 + * forces us to invert the HSYNC, so need to adjust display to
64833 + * the left by hskew pixels, provided by the tilcdc driver
64834 + */
64835 + ref_pix += mode->hskew;
64836 +
64837 + de_pix_s = mode->htotal - mode->hdisplay;
64838 + de_pix_e = de_pix_s + mode->hdisplay;
64839 + hs_pix_s = mode->hsync_start - mode->hdisplay;
64840 + hs_pix_e = hs_pix_s + mode->hsync_end - mode->hsync_start;
64841 +
64842 + ref_line = 1 + mode->vsync_start - mode->vdisplay;
64843 + vwin1_line_s = mode->vtotal - mode->vdisplay - 1;
64844 + vwin1_line_e = vwin1_line_s + mode->vdisplay;
64845 + vs1_pix_s = vs1_pix_e = hs_pix_s;
64846 + vs1_line_s = mode->vsync_start - mode->vdisplay;
64847 +
64848 + vs1_line_e = vs1_line_s +
64849 + mode->vsync_end - mode->vsync_start;
64850 +
64851 + vwin2_line_s = vwin2_line_e = 0;
64852 + vs2_pix_s = vs2_pix_e = 0;
64853 + vs2_line_s = vs2_line_e = 0;
64854 +
64855 + div = 148500 / mode->clock;
64856 +
64857 + /* Setup the VIP mappings, enable audio and video ports */
64858 + reg_write(encoder, REG_ENA_AP, 0xff);
64859 + reg_write(encoder, REG_ENA_VP_0, 0xff);
64860 + reg_write(encoder, REG_ENA_VP_1, 0xff);
64861 + reg_write(encoder, REG_ENA_VP_2, 0xff);
64862 + /* set muxing after enabling ports: */
64863 + reg_write(encoder, REG_VIP_CNTRL_0,
64864 + VIP_CNTRL_0_SWAP_A(2) | VIP_CNTRL_0_SWAP_B(3));
64865 + reg_write(encoder, REG_VIP_CNTRL_1,
64866 + VIP_CNTRL_1_SWAP_C(4) | VIP_CNTRL_1_SWAP_D(5));
64867 + reg_write(encoder, REG_VIP_CNTRL_2,
64868 + VIP_CNTRL_2_SWAP_E(0) | VIP_CNTRL_2_SWAP_F(1));
64869 +
64870 +
64871 + /* mute the audio FIFO: */
64872 + reg_set(encoder, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
64873 +
64874 + /* set HDMI HDCP mode off: */
64875 + reg_set(encoder, REG_TBG_CNTRL_1, TBG_CNTRL_1_DWIN_DIS);
64876 + reg_clear(encoder, REG_TX33, TX33_HDMI);
64877 +
64878 + reg_write(encoder, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(0));
64879 + /* no pre-filter or interpolator: */
64880 + reg_write(encoder, REG_HVF_CNTRL_0, HVF_CNTRL_0_PREFIL(0) |
64881 + HVF_CNTRL_0_INTPOL(0));
64882 + reg_write(encoder, REG_VIP_CNTRL_5, VIP_CNTRL_5_SP_CNT(0));
64883 + reg_write(encoder, REG_VIP_CNTRL_4, VIP_CNTRL_4_BLANKIT(0) |
64884 + VIP_CNTRL_4_BLC(0));
64885 + reg_clear(encoder, REG_PLL_SERIAL_3, PLL_SERIAL_3_SRL_CCIR);
64886 +
64887 + reg_clear(encoder, REG_PLL_SERIAL_1, PLL_SERIAL_1_SRL_MAN_IZ);
64888 + reg_clear(encoder, REG_PLL_SERIAL_3, PLL_SERIAL_3_SRL_DE);
64889 + reg_write(encoder, REG_SERIALIZER, 0);
64890 + reg_write(encoder, REG_HVF_CNTRL_1, HVF_CNTRL_1_VQR(0));
64891 +
64892 + /* TODO enable pixel repeat for pixel rates less than 25Msamp/s */
64893 + rep = 0;
64894 + reg_write(encoder, REG_RPT_CNTRL, 0);
64895 + reg_write(encoder, REG_SEL_CLK, SEL_CLK_SEL_VRF_CLK(0) |
64896 + SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK);
64897 +
64898 + reg_write(encoder, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(div) |
64899 + PLL_SERIAL_2_SRL_PR(rep));
64900 +
64901 + /* set color matrix bypass flag: */
64902 + reg_set(encoder, REG_MAT_CONTRL, MAT_CONTRL_MAT_BP);
64903 +
64904 + /* set BIAS tmds value: */
64905 + reg_write(encoder, REG_ANA_GENERAL, 0x09);
64906 +
64907 + reg_clear(encoder, REG_TBG_CNTRL_0, TBG_CNTRL_0_SYNC_MTHD);
64908 +
64909 + /*
64910 + * Sync on rising HSYNC/VSYNC
64911 + */
64912 + reg_write(encoder, REG_VIP_CNTRL_3, 0);
64913 + reg_set(encoder, REG_VIP_CNTRL_3, VIP_CNTRL_3_SYNC_HS);
64914 +
64915 + /*
64916 + * TDA19988 requires high-active sync at input stage,
64917 + * so invert low-active sync provided by master encoder here
64918 + */
64919 + if ((mode->flags & FB_SYNC_HOR_HIGH_ACT) == 0)
64920 + reg_set(encoder, REG_VIP_CNTRL_3, VIP_CNTRL_3_H_TGL);
64921 + if ((mode->flags & FB_SYNC_VERT_HIGH_ACT) == 0)
64922 + reg_set(encoder, REG_VIP_CNTRL_3, VIP_CNTRL_3_V_TGL);
64923 +
64924 + /*
64925 + * Always generate sync polarity relative to input sync and
64926 + * revert input stage toggled sync at output stage
64927 + */
64928 + reg = TBG_CNTRL_1_TGL_EN;
64929 + if ((mode->flags & FB_SYNC_HOR_HIGH_ACT) == 0)
64930 + reg |= TBG_CNTRL_1_H_TGL;
64931 + if ((mode->flags & FB_SYNC_VERT_HIGH_ACT) == 0)
64932 + reg |= TBG_CNTRL_1_V_TGL;
64933 + reg_write(encoder, REG_TBG_CNTRL_1, reg);
64934 +
64935 + reg_write(encoder, REG_VIDFORMAT, 0x00);
64936 + reg_write16(encoder, REG_REFPIX_MSB, ref_pix);
64937 + reg_write16(encoder, REG_REFLINE_MSB, ref_line);
64938 + reg_write16(encoder, REG_NPIX_MSB, n_pix);
64939 + reg_write16(encoder, REG_NLINE_MSB, n_line);
64940 + reg_write16(encoder, REG_VS_LINE_STRT_1_MSB, vs1_line_s);
64941 + reg_write16(encoder, REG_VS_PIX_STRT_1_MSB, vs1_pix_s);
64942 + reg_write16(encoder, REG_VS_LINE_END_1_MSB, vs1_line_e);
64943 + reg_write16(encoder, REG_VS_PIX_END_1_MSB, vs1_pix_e);
64944 + reg_write16(encoder, REG_VS_LINE_STRT_2_MSB, vs2_line_s);
64945 + reg_write16(encoder, REG_VS_PIX_STRT_2_MSB, vs2_pix_s);
64946 + reg_write16(encoder, REG_VS_LINE_END_2_MSB, vs2_line_e);
64947 + reg_write16(encoder, REG_VS_PIX_END_2_MSB, vs2_pix_e);
64948 + reg_write16(encoder, REG_HS_PIX_START_MSB, hs_pix_s);
64949 + reg_write16(encoder, REG_HS_PIX_STOP_MSB, hs_pix_e);
64950 + reg_write16(encoder, REG_VWIN_START_1_MSB, vwin1_line_s);
64951 + reg_write16(encoder, REG_VWIN_END_1_MSB, vwin1_line_e);
64952 + reg_write16(encoder, REG_VWIN_START_2_MSB, vwin2_line_s);
64953 + reg_write16(encoder, REG_VWIN_END_2_MSB, vwin2_line_e);
64954 + reg_write16(encoder, REG_DE_START_MSB, de_pix_s);
64955 + reg_write16(encoder, REG_DE_STOP_MSB, de_pix_e);
64956 +
64957 + if (priv->rev == TDA19988) {
64958 + /* let incoming pixels fill the active space (if any) */
64959 + reg_write(encoder, REG_ENABLE_SPACE, 0x01);
64960 + }
64961 +
64962 + /* must be last register set: */
64963 + reg_clear(encoder, REG_TBG_CNTRL_0, TBG_CNTRL_0_SYNC_ONCE);
64964 +
64965 +}
64966 +
64967 +/* I2C driver functions */
64968 +static int
64969 +da8xx_tda998x_probe(struct i2c_client *client, const struct i2c_device_id *id)
64970 +{
64971 + struct tda998x_priv *priv;
64972 + struct da8xx_encoder *encoder;
64973 +
64974 + priv = kzalloc(sizeof(*priv), GFP_KERNEL);
64975 + if (!priv)
64976 + return -ENOMEM;
64977 +
64978 + priv->current_page = 0;
64979 +
64980 + encoder = kzalloc(sizeof(*encoder), GFP_KERNEL);
64981 + if (!encoder) {
64982 + kfree(priv);
64983 + return -ENOMEM;
64984 + }
64985 +
64986 + priv->cec = i2c_new_dummy(client->adapter, 0x34);
64987 +
64988 + encoder->client = client;
64989 + encoder->priv = priv;
64990 + encoder->node = client->dev.of_node;
64991 + encoder->set_mode = da8xx_tda998x_setmode;
64992 +
64993 +
64994 + /* wake up the device: */
64995 + cec_write(encoder, REG_CEC_ENAMODS,
64996 + CEC_ENAMODS_EN_RXSENS | CEC_ENAMODS_EN_HDMI);
64997 +
64998 + tda998x_reset(encoder);
64999 +
65000 + /* read version: */
65001 + priv->rev = reg_read(encoder, REG_VERSION_LSB) |
65002 + reg_read(encoder, REG_VERSION_MSB) << 8;
65003 +
65004 + /* mask off feature bits: */
65005 + priv->rev &= ~0x30; /* not-hdcp and not-scalar bit */
65006 +
65007 + switch (priv->rev) {
65008 + case TDA9989N2:
65009 + dev_info(&client->dev, "found TDA9989 n2");
65010 + break;
65011 + case TDA19989:
65012 + dev_info(&client->dev, "found TDA19989");
65013 + break;
65014 + case TDA19989N2:
65015 + dev_info(&client->dev, "found TDA19989 n2");
65016 + break;
65017 + case TDA19988:
65018 + dev_info(&client->dev, "found TDA19988");
65019 + break;
65020 + default:
65021 + DBG("found unsupported device: %04x", priv->rev);
65022 + goto fail;
65023 + }
65024 +
65025 + da8xx_register_encoder(encoder);
65026 +
65027 + /* after reset, enable DDC: */
65028 + reg_write(encoder, REG_DDC_DISABLE, 0x00);
65029 +
65030 + /* set clock on DDC channel: */
65031 + reg_write(encoder, REG_TX3, 39);
65032 +
65033 + /* if necessary, disable multi-master: */
65034 + if (priv->rev == TDA19989)
65035 + reg_set(encoder, REG_I2C_MASTER, I2C_MASTER_DIS_MM);
65036 +
65037 + cec_write(encoder, REG_CEC_FRO_IM_CLK_CTRL,
65038 + CEC_FRO_IM_CLK_CTRL_GHOST_DIS |
65039 + CEC_FRO_IM_CLK_CTRL_IMCLK_SEL);
65040 +
65041 + i2c_set_clientdata(client, encoder);
65042 +
65043 + return 0;
65044 +
65045 +fail:
65046 + /* if encoder_init fails, the encoder slave is never registered,
65047 + * so cleanup here:
65048 + */
65049 + if (priv->cec)
65050 + i2c_unregister_device(priv->cec);
65051 +
65052 + kfree(priv);
65053 + kfree(encoder);
65054 + return -ENXIO;
65055 +}
65056 +
65057 +static int
65058 +da8xx_tda998x_remove(struct i2c_client *client)
65059 +{
65060 + struct da8xx_encoder *da8xx_encoder;
65061 + struct tda998x_priv *priv;
65062 +
65063 + da8xx_encoder = i2c_get_clientdata(client);
65064 + if (da8xx_encoder) {
65065 + da8xx_unregister_encoder(da8xx_encoder);
65066 + priv = to_tda998x_priv(da8xx_encoder);
65067 + if (priv->cec) {
65068 + /* disable the device: */
65069 + cec_write(da8xx_encoder, REG_CEC_ENAMODS, 0);
65070 + i2c_unregister_device(priv->cec);
65071 + }
65072 + kfree(da8xx_encoder->priv);
65073 + kfree(da8xx_encoder);
65074 + }
65075 + return 0;
65076 +}
65077 +
65078 +
65079 +static struct i2c_device_id da8xx_tda998x_ids[] = {
65080 + { "tda998x", 0 },
65081 + { }
65082 +};
65083 +MODULE_DEVICE_TABLE(i2c, da8xx_tda998x_ids);
65084 +
65085 +static struct i2c_driver da8xx_tda998x_driver = {
65086 + .probe = da8xx_tda998x_probe,
65087 + .remove = da8xx_tda998x_remove,
65088 + .driver = {
65089 + .owner = THIS_MODULE,
65090 + .name = "tda998x",
65091 + },
65092 + .id_table = da8xx_tda998x_ids,
65093 +};
65094 +
65095 +module_i2c_driver(da8xx_tda998x_driver);
65096 +
65097 +MODULE_DESCRIPTION("NXP TDA998x HDMI encoder driver for TI AM335x/DA8xx");
65098 +MODULE_AUTHOR("Texas Instruments");
65099 +MODULE_LICENSE("GPL");
65100 --- a/drivers/video/Kconfig
65101 +++ b/drivers/video/Kconfig
65102 @@ -2234,6 +2234,14 @@ config FB_DA8XX
65103 found on DA8xx/OMAP-L1xx/AM335x SoCs.
65104 If unsure, say N.
65105
65106 +config FB_DA8XX_TDA998X
65107 + tristate "NXP TDA998x HDMI driver for BeagleBone Black"
65108 + depends on FB_DA8XX
65109 + ---help---
65110 + This is a driver for NXP TDA998X HDMI as used on the BeagleBone
65111 + Black.
65112 + If unsure, say N.
65113 +
65114 config FB_VIRTUAL
65115 tristate "Virtual Frame Buffer support (ONLY FOR TESTING!)"
65116 depends on FB
65117 --- a/drivers/video/Makefile
65118 +++ b/drivers/video/Makefile
65119 @@ -164,6 +164,7 @@ obj-$(CONFIG_FB_BFIN_T350MCQB) += bfin
65120 obj-$(CONFIG_FB_BFIN_7393) += bfin_adv7393fb.o
65121 obj-$(CONFIG_FB_MX3) += mx3fb.o
65122 obj-$(CONFIG_FB_DA8XX) += da8xx-fb.o
65123 +obj-$(CONFIG_FB_DA8XX_TDA998X) += da8xx-tda998x-hdmi.o
65124 obj-$(CONFIG_FB_MXS) += mxsfb.o
65125 obj-$(CONFIG_FB_SSD1307) += ssd1307fb.o
65126 obj-$(CONFIG_FB_SIMPLE) += simplefb.o
65127 --- a/drivers/video/omap2/displays-new/connector-analog-tv.c
65128 +++ b/drivers/video/omap2/displays-new/connector-analog-tv.c
65129 @@ -12,6 +12,7 @@
65130 #include <linux/slab.h>
65131 #include <linux/module.h>
65132 #include <linux/platform_device.h>
65133 +#include <linux/of.h>
65134
65135 #include <video/omapdss.h>
65136 #include <video/omap-panel-data.h>
65137 @@ -42,6 +43,12 @@ static const struct omap_video_timings t
65138 .interlace = true,
65139 };
65140
65141 +static const struct of_device_id tvc_of_match[];
65142 +
65143 +struct tvc_of_data {
65144 + enum omap_dss_venc_type connector_type;
65145 +};
65146 +
65147 #define to_panel_data(x) container_of(x, struct panel_drv_data, dssdev)
65148
65149 static int tvc_connect(struct omap_dss_device *dssdev)
65150 @@ -205,6 +212,36 @@ static int tvc_probe_pdata(struct platfo
65151 return 0;
65152 }
65153
65154 +static int tvc_probe_of(struct platform_device *pdev,
65155 + const struct tvc_of_data *data)
65156 +{
65157 + struct panel_drv_data *ddata = platform_get_drvdata(pdev);
65158 + struct device_node *node = pdev->dev.of_node;
65159 + struct omap_dss_device *in;
65160 + struct device_node *src_node;
65161 +
65162 + src_node = of_parse_phandle(node, "video-source", 0);
65163 + if (!src_node) {
65164 + dev_err(&pdev->dev, "failed to parse video source\n");
65165 + return -ENODEV;
65166 + }
65167 +
65168 + in = omap_dss_find_output_by_node(src_node);
65169 + if (in == NULL) {
65170 + dev_err(&pdev->dev, "failed to find video source\n");
65171 + return -EPROBE_DEFER;
65172 + }
65173 + ddata->in = in;
65174 +
65175 + ddata->connector_type = data->connector_type;
65176 +
65177 + ddata->invert_polarity =
65178 + of_property_read_bool(node, "invert-polarity");
65179 +
65180 + return 0;
65181 +}
65182 +
65183 +
65184 static int tvc_probe(struct platform_device *pdev)
65185 {
65186 struct panel_drv_data *ddata;
65187 @@ -222,6 +259,18 @@ static int tvc_probe(struct platform_dev
65188 r = tvc_probe_pdata(pdev);
65189 if (r)
65190 return r;
65191 + } else if (pdev->dev.of_node) {
65192 + const struct of_device_id *match;
65193 +
65194 + match = of_match_node(tvc_of_match, pdev->dev.of_node);
65195 + if (!match) {
65196 + dev_err(&pdev->dev, "unsupported device\n");
65197 + return -ENODEV;
65198 + }
65199 +
65200 + r = tvc_probe_of(pdev, match->data);
65201 + if (r)
65202 + return r;
65203 } else {
65204 return -ENODEV;
65205 }
65206 @@ -263,12 +312,33 @@ static int __exit tvc_remove(struct plat
65207 return 0;
65208 }
65209
65210 +static const struct tvc_of_data tv_svideo_data = {
65211 + .connector_type = OMAP_DSS_VENC_TYPE_SVIDEO,
65212 +};
65213 +
65214 +static const struct tvc_of_data tv_composite_video_data = {
65215 + .connector_type = OMAP_DSS_VENC_TYPE_COMPOSITE,
65216 +};
65217 +
65218 +static const struct of_device_id tvc_of_match[] = {
65219 + {
65220 + .compatible = "ti,svideo-connector",
65221 + .data = &tv_svideo_data,
65222 + },
65223 + {
65224 + .compatible = "ti,composite-video-connector",
65225 + .data = &tv_composite_video_data,
65226 + },
65227 + {},
65228 +};
65229 +
65230 static struct platform_driver tvc_connector_driver = {
65231 .probe = tvc_probe,
65232 .remove = __exit_p(tvc_remove),
65233 .driver = {
65234 .name = "connector-analog-tv",
65235 .owner = THIS_MODULE,
65236 + .of_match_table = tvc_of_match,
65237 },
65238 };
65239
65240 --- a/drivers/video/omap2/displays-new/connector-dvi.c
65241 +++ b/drivers/video/omap2/displays-new/connector-dvi.c
65242 @@ -274,6 +274,42 @@ static int dvic_probe_pdata(struct platf
65243 return 0;
65244 }
65245
65246 +static int dvic_probe_of(struct platform_device *pdev)
65247 +{
65248 + struct panel_drv_data *ddata = platform_get_drvdata(pdev);
65249 + struct device_node *node = pdev->dev.of_node;
65250 + struct omap_dss_device *in;
65251 + struct device_node *src_node;
65252 + struct device_node *adapter_node;
65253 + struct i2c_adapter *adapter;
65254 +
65255 + src_node = of_parse_phandle(node, "video-source", 0);
65256 + if (!src_node) {
65257 + dev_err(&pdev->dev, "failed to parse video source\n");
65258 + return -ENODEV;
65259 + }
65260 +
65261 + in = omap_dss_find_output_by_node(src_node);
65262 + if (in == NULL) {
65263 + dev_err(&pdev->dev, "failed to find video source\n");
65264 + return -EPROBE_DEFER;
65265 + }
65266 + ddata->in = in;
65267 +
65268 + adapter_node = of_parse_phandle(node, "i2c-bus", 0);
65269 + if (adapter_node) {
65270 + adapter = of_find_i2c_adapter_by_node(adapter_node);
65271 + if (adapter == NULL) {
65272 + dev_err(&pdev->dev, "failed to parse i2c-bus\n");
65273 + return -EPROBE_DEFER;
65274 + }
65275 +
65276 + ddata->i2c_adapter = adapter;
65277 + }
65278 +
65279 + return 0;
65280 +}
65281 +
65282 static int dvic_probe(struct platform_device *pdev)
65283 {
65284 struct panel_drv_data *ddata;
65285 @@ -290,6 +326,10 @@ static int dvic_probe(struct platform_de
65286 r = dvic_probe_pdata(pdev);
65287 if (r)
65288 return r;
65289 + } else if (pdev->dev.of_node) {
65290 + r = dvic_probe_of(pdev);
65291 + if (r)
65292 + return r;
65293 } else {
65294 return -ENODEV;
65295 }
65296 @@ -335,12 +375,20 @@ static int __exit dvic_remove(struct pla
65297 return 0;
65298 }
65299
65300 +static const struct of_device_id dvic_of_match[] = {
65301 + { .compatible = "ti,dvi_connector", },
65302 + {},
65303 +};
65304 +
65305 +MODULE_DEVICE_TABLE(of, dvic_of_match);
65306 +
65307 static struct platform_driver dvi_connector_driver = {
65308 .probe = dvic_probe,
65309 .remove = __exit_p(dvic_remove),
65310 .driver = {
65311 .name = "connector-dvi",
65312 .owner = THIS_MODULE,
65313 + .of_match_table = dvic_of_match,
65314 },
65315 };
65316
65317 --- a/drivers/video/omap2/displays-new/connector-hdmi.c
65318 +++ b/drivers/video/omap2/displays-new/connector-hdmi.c
65319 @@ -12,6 +12,7 @@
65320 #include <linux/slab.h>
65321 #include <linux/module.h>
65322 #include <linux/platform_device.h>
65323 +#include <linux/of.h>
65324
65325 #include <drm/drm_edid.h>
65326
65327 @@ -301,6 +302,29 @@ static int hdmic_probe_pdata(struct plat
65328 return 0;
65329 }
65330
65331 +static int hdmic_probe_of(struct platform_device *pdev)
65332 +{
65333 + struct panel_drv_data *ddata = platform_get_drvdata(pdev);
65334 + struct device_node *node = pdev->dev.of_node;
65335 + struct omap_dss_device *in;
65336 + struct device_node *src_node;
65337 +
65338 + src_node = of_parse_phandle(node, "video-source", 0);
65339 + if (!src_node) {
65340 + dev_err(&pdev->dev, "failed to parse video source\n");
65341 + return -ENODEV;
65342 + }
65343 +
65344 + in = omap_dss_find_output_by_node(src_node);
65345 + if (in == NULL) {
65346 + dev_err(&pdev->dev, "failed to find video source\n");
65347 + return -EPROBE_DEFER;
65348 + }
65349 + ddata->in = in;
65350 +
65351 + return 0;
65352 +}
65353 +
65354 static int hdmic_probe(struct platform_device *pdev)
65355 {
65356 struct panel_drv_data *ddata;
65357 @@ -318,6 +342,10 @@ static int hdmic_probe(struct platform_d
65358 r = hdmic_probe_pdata(pdev);
65359 if (r)
65360 return r;
65361 + } else if (pdev->dev.of_node) {
65362 + r = hdmic_probe_of(pdev);
65363 + if (r)
65364 + return r;
65365 } else {
65366 return -ENODEV;
65367 }
65368 @@ -359,12 +387,20 @@ static int __exit hdmic_remove(struct pl
65369 return 0;
65370 }
65371
65372 +static const struct of_device_id hdmic_of_match[] = {
65373 + { .compatible = "ti,hdmi_connector", },
65374 + {},
65375 +};
65376 +
65377 +MODULE_DEVICE_TABLE(of, hdmic_of_match);
65378 +
65379 static struct platform_driver hdmi_connector_driver = {
65380 .probe = hdmic_probe,
65381 .remove = __exit_p(hdmic_remove),
65382 .driver = {
65383 .name = "connector-hdmi",
65384 .owner = THIS_MODULE,
65385 + .of_match_table = hdmic_of_match,
65386 },
65387 };
65388
65389 --- /dev/null
65390 +++ b/drivers/video/omap2/displays-new/dra-evm-encoder-tpd12s015.c
65391 @@ -0,0 +1,556 @@
65392 +/*
65393 + * TPD12S015 HDMI ESD protection & level shifter chip driver
65394 + *
65395 + * Copyright (C) 2013 Texas Instruments
65396 + * Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
65397 + *
65398 + * This program is free software; you can redistribute it and/or modify it
65399 + * under the terms of the GNU General Public License version 2 as published by
65400 + * the Free Software Foundation.
65401 + */
65402 +
65403 +#include <linux/delay.h>
65404 +#include <linux/module.h>
65405 +#include <linux/slab.h>
65406 +#include <linux/gpio.h>
65407 +#include <linux/io.h>
65408 +#include <linux/platform_device.h>
65409 +#include <linux/of_gpio.h>
65410 +
65411 +#include <video/omapdss.h>
65412 +#include <video/omap-panel-data.h>
65413 +
65414 +#define CLK_BASE 0x4a009000
65415 +#define MCASP2_BASE 0x48464000
65416 +#define CTRL_BASE 0x4a003400
65417 +#define PINMUX_BASE 0x4a003600
65418 +
65419 +#define CM_L4PER2_MCASP2_CLKCTRL 0x860
65420 +#define CM_L4PER2_CLKSTCTRL 0x8fc
65421 +#define MCASP_PFUNC 0x10
65422 +#define MCASP_PDIR 0x14
65423 +#define MCASP_PDOUT 0x18
65424 +#define PAD_I2C2_SDA 0x408
65425 +#define PAD_I2C2_SCL 0x40c
65426 +
65427 +#define SEL_I2C2 0
65428 +#define SEL_HDMI 1
65429 +
65430 +struct panel_drv_data {
65431 + struct omap_dss_device dssdev;
65432 + struct omap_dss_device *in;
65433 +
65434 + int ct_cp_hpd_gpio;
65435 + int ls_oe_gpio;
65436 + int hpd_gpio;
65437 +
65438 + struct omap_video_timings timings;
65439 +};
65440 +
65441 +static void config_sel_hdmi_i2c2(struct device *dev)
65442 +{
65443 + void __iomem *clk_base = ioremap(CLK_BASE, SZ_4K);
65444 + void __iomem *mcasp2_base = ioremap(MCASP2_BASE, SZ_1K);
65445 + void __iomem *pmux_base = ioremap(PINMUX_BASE, SZ_1K);
65446 +
65447 + if (!clk_base) {
65448 + dev_err(dev, "couldn't ioremap clock domain regs\n");
65449 + return;
65450 + }
65451 +
65452 + if (!mcasp2_base) {
65453 + dev_err(dev, "couldn't ioremap MCASP2 regs\n");
65454 + goto mcasp_err;
65455 + }
65456 +
65457 + if (!pmux_base) {
65458 + dev_err(dev, "couldn't ioremap PMUX regs\n");
65459 + goto pmux_err;
65460 + }
65461 +
65462 + iowrite32(0x40000, pmux_base + 0xfc);
65463 +
65464 + /* set CM_L4PER2_CLKSTCTRL to sw supervised wkup */
65465 + iowrite32(0x2, clk_base + CM_L4PER2_CLKSTCTRL);
65466 +
65467 + /*
65468 + * Enable the MCASP8_AUX_GFCLK[22:23]: 0x0 - use default
65469 + * CM_L4PER2_MCASP8_CLKCTRL[1:0]: 0x2 - Enable explicitly
65470 + */
65471 + iowrite32(0x2, clk_base + CM_L4PER2_MCASP2_CLKCTRL);
65472 +
65473 + dev_dbg(dev, "CM_L4PER2_CLKSTCTRL %08x\n",
65474 + ioread32(clk_base + CM_L4PER2_CLKSTCTRL));
65475 +
65476 + /* let it propogate */
65477 +
65478 + udelay(5);
65479 + /*
65480 + * make mcasp8_axr2 a gpio and set direction to high
65481 + */
65482 + iowrite32(1 << 29, mcasp2_base + MCASP_PFUNC);
65483 + iowrite32(1 << 29, mcasp2_base + MCASP_PDIR);
65484 +
65485 + iounmap(pmux_base);
65486 +pmux_err:
65487 + iounmap(mcasp2_base);
65488 +mcasp_err:
65489 + iounmap(clk_base);
65490 +}
65491 +
65492 +/*
65493 + * use I2C2 to configure pcf8575@26 to set/unset LS_OE and CT_HPD, use HDMI to
65494 + * read edid via the HDMI ddc lines, and recieve HPD events
65495 + */
65496 +void config_demux(struct device *dev, int sel)
65497 +{
65498 + void __iomem *mcasp2_base = ioremap(MCASP2_BASE, SZ_1K);
65499 + void __iomem *ctrl_base = ioremap(CTRL_BASE, SZ_1K);
65500 +
65501 + if (!mcasp2_base) {
65502 + dev_err(dev, "couldn't ioremap MCASP8 regs\n");
65503 + return;
65504 + }
65505 +
65506 + if (!ctrl_base) {
65507 + dev_err(dev, "couldn't ioremap CTRL base\n");
65508 + goto err_ctrl;
65509 + }
65510 +
65511 + /*
65512 + * switch to I2C2 or HDMI DDC internal pinmux and drive MCASP8_PDOUT
65513 + * to low or high to select I2C2 or HDMI path respectively
65514 + */
65515 + if (sel == SEL_I2C2) {
65516 + iowrite32(0x0, mcasp2_base + MCASP_PDOUT);
65517 + iowrite32(0x60000, ctrl_base + PAD_I2C2_SDA);
65518 + iowrite32(0x60000, ctrl_base + PAD_I2C2_SCL);
65519 + } else {
65520 + iowrite32(1 << 29, mcasp2_base + MCASP_PDOUT);
65521 + iowrite32(0x60001, ctrl_base + PAD_I2C2_SDA);
65522 + iowrite32(0x60001, ctrl_base + PAD_I2C2_SCL);
65523 + }
65524 +
65525 + /* let it propogate */
65526 + udelay(5);
65527 +
65528 + dev_dbg(dev, "select %d, PDOUT %08x\n", sel,
65529 + ioread32(mcasp2_base + MCASP_PDOUT));
65530 +
65531 + iounmap(ctrl_base);
65532 +err_ctrl:
65533 + iounmap(mcasp2_base);
65534 +}
65535 +
65536 +#define to_panel_data(x) container_of(x, struct panel_drv_data, dssdev)
65537 +
65538 +static int tpd_connect(struct omap_dss_device *dssdev,
65539 + struct omap_dss_device *dst)
65540 +{
65541 + struct panel_drv_data *ddata = to_panel_data(dssdev);
65542 + struct omap_dss_device *in = ddata->in;
65543 + bool hpd;
65544 + int r;
65545 +
65546 + r = in->ops.hdmi->connect(in, dssdev);
65547 + if (r)
65548 + return r;
65549 +
65550 + dst->src = dssdev;
65551 + dssdev->dst = dst;
65552 +
65553 + config_demux(dssdev->dev, SEL_I2C2);
65554 +
65555 + gpio_set_value_cansleep(ddata->ct_cp_hpd_gpio, 1);
65556 +
65557 + config_demux(dssdev->dev, SEL_HDMI);
65558 +
65559 + /* DC-DC converter needs at max 300us to get to 90% of 5V */
65560 + udelay(300);
65561 +
65562 + /*
65563 + * If there's a cable connected, hpd will be up, turn the level shifters
65564 + * accordingly
65565 + */
65566 + hpd = gpio_get_value_cansleep(ddata->hpd_gpio);
65567 +
65568 + config_demux(dssdev->dev, SEL_I2C2);
65569 +
65570 + if (gpio_is_valid(ddata->ls_oe_gpio)) {
65571 + if (hpd)
65572 + gpio_set_value_cansleep(ddata->ls_oe_gpio, 1);
65573 + else
65574 + gpio_set_value_cansleep(ddata->ls_oe_gpio, 0);
65575 + }
65576 +
65577 + config_demux(dssdev->dev, SEL_HDMI);
65578 +
65579 + return 0;
65580 +}
65581 +
65582 +static void tpd_disconnect(struct omap_dss_device *dssdev,
65583 + struct omap_dss_device *dst)
65584 +{
65585 + struct panel_drv_data *ddata = to_panel_data(dssdev);
65586 + struct omap_dss_device *in = ddata->in;
65587 +
65588 + WARN_ON(dst != dssdev->dst);
65589 +
65590 + if (dst != dssdev->dst)
65591 + return;
65592 +
65593 + config_demux(dssdev->dev, SEL_I2C2);
65594 +
65595 + gpio_set_value_cansleep(ddata->ct_cp_hpd_gpio, 0);
65596 +
65597 + config_demux(dssdev->dev, SEL_HDMI);
65598 +
65599 + dst->src = NULL;
65600 + dssdev->dst = NULL;
65601 +
65602 + in->ops.hdmi->disconnect(in, &ddata->dssdev);
65603 +}
65604 +
65605 +static int tpd_enable(struct omap_dss_device *dssdev)
65606 +{
65607 + struct panel_drv_data *ddata = to_panel_data(dssdev);
65608 + struct omap_dss_device *in = ddata->in;
65609 + int r;
65610 +
65611 + if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE)
65612 + return 0;
65613 +
65614 + in->ops.hdmi->set_timings(in, &ddata->timings);
65615 +
65616 + r = in->ops.hdmi->enable(in);
65617 + if (r)
65618 + return r;
65619 +
65620 + dssdev->state = OMAP_DSS_DISPLAY_ACTIVE;
65621 +
65622 + return r;
65623 +}
65624 +
65625 +static void tpd_disable(struct omap_dss_device *dssdev)
65626 +{
65627 + struct panel_drv_data *ddata = to_panel_data(dssdev);
65628 + struct omap_dss_device *in = ddata->in;
65629 +
65630 + if (dssdev->state != OMAP_DSS_DISPLAY_ACTIVE)
65631 + return;
65632 +
65633 + in->ops.hdmi->disable(in);
65634 +
65635 + dssdev->state = OMAP_DSS_DISPLAY_DISABLED;
65636 +}
65637 +
65638 +static void tpd_set_timings(struct omap_dss_device *dssdev,
65639 + struct omap_video_timings *timings)
65640 +{
65641 + struct panel_drv_data *ddata = to_panel_data(dssdev);
65642 + struct omap_dss_device *in = ddata->in;
65643 +
65644 + ddata->timings = *timings;
65645 + dssdev->panel.timings = *timings;
65646 +
65647 + in->ops.hdmi->set_timings(in, timings);
65648 +}
65649 +
65650 +static void tpd_get_timings(struct omap_dss_device *dssdev,
65651 + struct omap_video_timings *timings)
65652 +{
65653 + struct panel_drv_data *ddata = to_panel_data(dssdev);
65654 +
65655 + *timings = ddata->timings;
65656 +}
65657 +
65658 +static int tpd_check_timings(struct omap_dss_device *dssdev,
65659 + struct omap_video_timings *timings)
65660 +{
65661 + struct panel_drv_data *ddata = to_panel_data(dssdev);
65662 + struct omap_dss_device *in = ddata->in;
65663 + int r;
65664 +
65665 + r = in->ops.hdmi->check_timings(in, timings);
65666 +
65667 + return r;
65668 +}
65669 +
65670 +static int tpd_read_edid(struct omap_dss_device *dssdev,
65671 + u8 *edid, int len)
65672 +{
65673 + struct panel_drv_data *ddata = to_panel_data(dssdev);
65674 + struct omap_dss_device *in = ddata->in;
65675 +
65676 + if (!gpio_get_value_cansleep(ddata->hpd_gpio))
65677 + return -ENODEV;
65678 +
65679 + return in->ops.hdmi->read_edid(in, edid, len);
65680 +}
65681 +
65682 +static bool tpd_detect(struct omap_dss_device *dssdev)
65683 +{
65684 + struct panel_drv_data *ddata = to_panel_data(dssdev);
65685 +
65686 + return gpio_get_value_cansleep(ddata->hpd_gpio);
65687 +}
65688 +
65689 +static int tpd_audio_enable(struct omap_dss_device *dssdev)
65690 +{
65691 + struct panel_drv_data *ddata = to_panel_data(dssdev);
65692 + struct omap_dss_device *in = ddata->in;
65693 +
65694 + return in->ops.hdmi->audio_enable(in);
65695 +}
65696 +
65697 +static void tpd_audio_disable(struct omap_dss_device *dssdev)
65698 +{
65699 + struct panel_drv_data *ddata = to_panel_data(dssdev);
65700 + struct omap_dss_device *in = ddata->in;
65701 +
65702 + in->ops.hdmi->audio_disable(in);
65703 +}
65704 +
65705 +static int tpd_audio_start(struct omap_dss_device *dssdev)
65706 +{
65707 + struct panel_drv_data *ddata = to_panel_data(dssdev);
65708 + struct omap_dss_device *in = ddata->in;
65709 +
65710 + return in->ops.hdmi->audio_start(in);
65711 +}
65712 +
65713 +static void tpd_audio_stop(struct omap_dss_device *dssdev)
65714 +{
65715 + struct panel_drv_data *ddata = to_panel_data(dssdev);
65716 + struct omap_dss_device *in = ddata->in;
65717 +
65718 + in->ops.hdmi->audio_stop(in);
65719 +}
65720 +
65721 +static bool tpd_audio_supported(struct omap_dss_device *dssdev)
65722 +{
65723 + struct panel_drv_data *ddata = to_panel_data(dssdev);
65724 + struct omap_dss_device *in = ddata->in;
65725 +
65726 + return in->ops.hdmi->audio_supported(in);
65727 +}
65728 +
65729 +static int tpd_audio_config(struct omap_dss_device *dssdev,
65730 + struct omap_dss_audio *audio)
65731 +{
65732 + struct panel_drv_data *ddata = to_panel_data(dssdev);
65733 + struct omap_dss_device *in = ddata->in;
65734 +
65735 + return in->ops.hdmi->audio_config(in, audio);
65736 +}
65737 +
65738 +static const struct omapdss_hdmi_ops tpd_hdmi_ops = {
65739 + .connect = tpd_connect,
65740 + .disconnect = tpd_disconnect,
65741 +
65742 + .enable = tpd_enable,
65743 + .disable = tpd_disable,
65744 +
65745 + .check_timings = tpd_check_timings,
65746 + .set_timings = tpd_set_timings,
65747 + .get_timings = tpd_get_timings,
65748 +
65749 + .read_edid = tpd_read_edid,
65750 + .detect = tpd_detect,
65751 +
65752 + .audio_enable = tpd_audio_enable,
65753 + .audio_disable = tpd_audio_disable,
65754 + .audio_start = tpd_audio_start,
65755 + .audio_stop = tpd_audio_stop,
65756 + .audio_supported = tpd_audio_supported,
65757 + .audio_config = tpd_audio_config,
65758 +};
65759 +
65760 +static int tpd_probe_pdata(struct platform_device *pdev)
65761 +{
65762 + struct panel_drv_data *ddata = platform_get_drvdata(pdev);
65763 + struct encoder_tpd12s015_platform_data *pdata;
65764 + struct omap_dss_device *dssdev, *in;
65765 +
65766 + pdata = dev_get_platdata(&pdev->dev);
65767 +
65768 + ddata->ct_cp_hpd_gpio = pdata->ct_cp_hpd_gpio;
65769 + ddata->ls_oe_gpio = pdata->ls_oe_gpio;
65770 + ddata->hpd_gpio = pdata->hpd_gpio;
65771 +
65772 + in = omap_dss_find_output(pdata->source);
65773 + if (in == NULL) {
65774 + dev_err(&pdev->dev, "Failed to find video source\n");
65775 + return -ENODEV;
65776 + }
65777 +
65778 + ddata->in = in;
65779 +
65780 + dssdev = &ddata->dssdev;
65781 + dssdev->name = pdata->name;
65782 +
65783 + return 0;
65784 +}
65785 +
65786 +static int tpd_probe_of(struct platform_device *pdev)
65787 +{
65788 + struct panel_drv_data *ddata = platform_get_drvdata(pdev);
65789 + struct device_node *node = pdev->dev.of_node;
65790 + struct omap_dss_device *in;
65791 + struct device_node *src_node;
65792 + int gpio;
65793 +
65794 + src_node = of_parse_phandle(node, "video-source", 0);
65795 + if (!src_node) {
65796 + dev_err(&pdev->dev, "failed to parse video source\n");
65797 + return -ENODEV;
65798 + }
65799 +
65800 + in = omap_dss_find_output_by_node(src_node);
65801 + if (in == NULL) {
65802 + dev_err(&pdev->dev, "failed to find video source\n");
65803 + return -EPROBE_DEFER;
65804 + }
65805 + ddata->in = in;
65806 +
65807 + /* CT CP HPD GPIO */
65808 + gpio = of_get_gpio(node, 0);
65809 + if (!gpio_is_valid(gpio)) {
65810 + dev_err(&pdev->dev, "failed to parse CT CP HPD gpio\n");
65811 + return gpio;
65812 + }
65813 + ddata->ct_cp_hpd_gpio = gpio;
65814 +
65815 + /* LS OE GPIO */
65816 + gpio = of_get_gpio(node, 1);
65817 + if (gpio_is_valid(gpio) || gpio == -ENOENT) {
65818 + ddata->ls_oe_gpio = gpio;
65819 + } else {
65820 + dev_err(&pdev->dev, "failed to parse LS OE gpio\n");
65821 + return gpio;
65822 + }
65823 +
65824 + /* HPD GPIO */
65825 + gpio = of_get_gpio(node, 2);
65826 + if (!gpio_is_valid(gpio)) {
65827 + dev_err(&pdev->dev, "failed to parse HPD gpio\n");
65828 + return gpio;
65829 + }
65830 + ddata->hpd_gpio = gpio;
65831 +
65832 + return 0;
65833 +}
65834 +
65835 +static int tpd_probe(struct platform_device *pdev)
65836 +{
65837 + struct omap_dss_device *in, *dssdev;
65838 + struct panel_drv_data *ddata;
65839 + int r;
65840 +
65841 + ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL);
65842 + if (!ddata)
65843 + return -ENOMEM;
65844 +
65845 + platform_set_drvdata(pdev, ddata);
65846 +
65847 + if (dev_get_platdata(&pdev->dev)) {
65848 + r = tpd_probe_pdata(pdev);
65849 + if (r)
65850 + return r;
65851 + } else if (pdev->dev.of_node) {
65852 + r = tpd_probe_of(pdev);
65853 + if (r)
65854 + return r;
65855 + } else {
65856 + return -ENODEV;
65857 + }
65858 +
65859 + /* configure the SEL_HDMI_I2C2 line going to the demux */
65860 + config_sel_hdmi_i2c2(&pdev->dev);
65861 +
65862 + config_demux(&pdev->dev, SEL_I2C2);
65863 +
65864 + r = devm_gpio_request_one(&pdev->dev, ddata->ct_cp_hpd_gpio,
65865 + GPIOF_OUT_INIT_LOW, "hdmi_ct_cp_hpd");
65866 + if (r)
65867 + goto err_gpio;
65868 +
65869 + if (gpio_is_valid(ddata->ls_oe_gpio)) {
65870 + r = devm_gpio_request_one(&pdev->dev, ddata->ls_oe_gpio,
65871 + GPIOF_OUT_INIT_LOW, "hdmi_ls_oe");
65872 + if (r)
65873 + goto err_gpio;
65874 + }
65875 +
65876 + r = devm_gpio_request_one(&pdev->dev, ddata->hpd_gpio,
65877 + GPIOF_DIR_IN, "hdmi_hpd");
65878 + if (r)
65879 + goto err_gpio;
65880 +
65881 + config_demux(&pdev->dev, SEL_HDMI);
65882 +
65883 + dssdev = &ddata->dssdev;
65884 + dssdev->ops.hdmi = &tpd_hdmi_ops;
65885 + dssdev->dev = &pdev->dev;
65886 + dssdev->type = OMAP_DISPLAY_TYPE_HDMI;
65887 + dssdev->output_type = OMAP_DISPLAY_TYPE_HDMI;
65888 + dssdev->owner = THIS_MODULE;
65889 +
65890 + in = ddata->in;
65891 +
65892 + r = omapdss_register_output(dssdev);
65893 + if (r) {
65894 + dev_err(&pdev->dev, "Failed to register output\n");
65895 + goto err_reg;
65896 + }
65897 +
65898 + return 0;
65899 +err_reg:
65900 +err_gpio:
65901 + omap_dss_put_device(ddata->in);
65902 + return r;
65903 +}
65904 +
65905 +static int __exit tpd_remove(struct platform_device *pdev)
65906 +{
65907 + struct panel_drv_data *ddata = platform_get_drvdata(pdev);
65908 + struct omap_dss_device *dssdev = &ddata->dssdev;
65909 + struct omap_dss_device *in = ddata->in;
65910 +
65911 + omapdss_unregister_output(&ddata->dssdev);
65912 +
65913 + WARN_ON(omapdss_device_is_enabled(dssdev));
65914 + if (omapdss_device_is_enabled(dssdev))
65915 + tpd_disable(dssdev);
65916 +
65917 + WARN_ON(omapdss_device_is_connected(dssdev));
65918 + if (omapdss_device_is_connected(dssdev))
65919 + tpd_disconnect(dssdev, dssdev->dst);
65920 +
65921 + omap_dss_put_device(in);
65922 +
65923 + return 0;
65924 +}
65925 +
65926 +static const struct of_device_id tpd_of_match[] = {
65927 + { .compatible = "ti,draevm-tpd12s015", },
65928 + {},
65929 +};
65930 +
65931 +MODULE_DEVICE_TABLE(of, tpd_of_match);
65932 +
65933 +static struct platform_driver tpd_driver = {
65934 + .probe = tpd_probe,
65935 + .remove = __exit_p(tpd_remove),
65936 + .driver = {
65937 + .name = "draevm-tpd12s015",
65938 + .owner = THIS_MODULE,
65939 + .of_match_table = tpd_of_match,
65940 + },
65941 +};
65942 +
65943 +module_platform_driver(tpd_driver);
65944 +
65945 +MODULE_AUTHOR("Tomi Valkeinen <tomi.valkeinen@ti.com>");
65946 +MODULE_DESCRIPTION("DRAEVM-TPD12S015 driver");
65947 +MODULE_LICENSE("GPL");
65948 --- /dev/null
65949 +++ b/drivers/video/omap2/displays-new/encoder-sil9022.c
65950 @@ -0,0 +1,880 @@
65951 +/*
65952 + * Silicon image Sil9022 DPI-to-HDMI encoder driver
65953 + *
65954 + * Copyright (C) 2013 Texas Instruments
65955 + * Author: Sathya Prakash M R <sathyap@ti.com>
65956 + *
65957 + * This file is licensed under the terms of the GNU General Public License
65958 + * version 2. This program is licensed "as is" without any warranty of any
65959 + * kind, whether express or implied.
65960 + *
65961 + */
65962 +
65963 +#include <linux/module.h>
65964 +#include <linux/kernel.h>
65965 +#include <linux/errno.h>
65966 +#include <linux/string.h>
65967 +#include <linux/types.h>
65968 +#include <linux/slab.h>
65969 +#include <linux/io.h>
65970 +#include <linux/init.h>
65971 +#include <linux/interrupt.h>
65972 +#include <linux/i2c.h>
65973 +#include <linux/device.h>
65974 +#include <linux/delay.h>
65975 +#include <linux/gpio.h>
65976 +#include <linux/platform_device.h>
65977 +#include <linux/regmap.h>
65978 +#include <linux/of_gpio.h>
65979 +
65980 +#include <video/omapdss.h>
65981 +#include <video/omap-panel-data.h>
65982 +#include "encoder-sil9022.h"
65983 +
65984 +struct panel_drv_data {
65985 + struct omap_dss_device dssdev;
65986 + struct omap_dss_device *in;
65987 + struct i2c_client *i2c_client;
65988 + int reset_gpio;
65989 + int data_lines;
65990 + struct regmap *regmap;
65991 + struct omap_video_timings timings;
65992 +};
65993 +
65994 +#define to_panel_data(x) container_of(x, struct panel_drv_data, dssdev)
65995 +
65996 +static int sil9022_blockwrite_reg(struct i2c_client *client,
65997 + u8 reg, u16 alength, u8 *val, u16 *out_len)
65998 +{
65999 + int err = 0, i;
66000 + struct i2c_msg msg[1];
66001 + u8 data[2];
66002 +
66003 + if (!client->adapter) {
66004 + dev_err(&client->dev, "ERROR: No HDMI Device\n");
66005 + return -ENODEV;
66006 + }
66007 +
66008 + msg->addr = client->addr;
66009 + msg->flags = 0;
66010 + msg->len = 2;
66011 + msg->buf = data;
66012 +
66013 + /* high byte goes out first */
66014 + data[0] = reg >> 8;
66015 +
66016 + for (i = 0; i < alength - 1; i++) {
66017 + data[1] = val[i];
66018 + err = i2c_transfer(client->adapter, msg, 1);
66019 + udelay(50);
66020 + dev_dbg(&client->dev, "i2c Block write at 0x%x, "
66021 + "*val=%d flags=%d byte[%d] err=%d\n",
66022 + data[0], data[1], msg->flags, i, err);
66023 + if (err < 0)
66024 + break;
66025 + }
66026 + /* set the number of bytes written*/
66027 + *out_len = i;
66028 +
66029 + if (err < 0) {
66030 + dev_err(&client->dev, "ERROR: i2c Block Write at 0x%x, "
66031 + "*val=%d flags=%d bytes written=%d "
66032 + "err=%d\n",
66033 + data[0], data[1], msg->flags, i, err);
66034 + return err;
66035 + }
66036 + return 0;
66037 +}
66038 +
66039 +static int sil9022_blockread_reg(struct i2c_client *client,
66040 + u16 data_length, u16 alength,
66041 + u8 reg, u8 *val, u16 *out_len)
66042 +{
66043 + int err = 0, i;
66044 + struct i2c_msg msg[1];
66045 + u8 data[2];
66046 +
66047 + if (!client->adapter) {
66048 + dev_err(&client->dev, "ERROR: No HDMI Device\n");
66049 + return -ENODEV;
66050 + }
66051 +
66052 + msg->addr = client->addr;
66053 + msg->flags = 0;
66054 + msg->len = 1;
66055 + msg->buf = data;
66056 +
66057 + /* High byte goes out first */
66058 + data[0] = reg;
66059 + err = i2c_transfer(client->adapter, msg, 1);
66060 + dev_dbg(&client->dev, "Block Read1 at 0x%x, "
66061 + "*val=%d flags=%d err=%d\n",
66062 + data[0], data[1], msg->flags, err);
66063 +
66064 + for (i = 0; i < alength; i++) {
66065 + if (err >= 0) {
66066 + mdelay(3);
66067 + msg->flags = I2C_M_RD;
66068 + msg->len = data_length;
66069 + err = i2c_transfer(client->adapter, msg, 1);
66070 + } else {
66071 + break;
66072 + }
66073 + if (err >= 0) {
66074 + val[i] = 0;
66075 + /* High byte comes first */
66076 + if (data_length == 1)
66077 + val[i] = data[0];
66078 + else if (data_length == 2)
66079 + val[i] = data[1] + (data[0] << 8);
66080 + dev_dbg(&client->dev, "i2c Block Read2 at 0x%x, "
66081 + "*val=%d flags=%d byte=%d "
66082 + "err=%d\n",
66083 + reg, val[i], msg->flags, i, err);
66084 + } else {
66085 + break;
66086 + }
66087 + }
66088 + *out_len = i;
66089 + dev_dbg(&client->dev, "i2c Block Read at 0x%x, bytes read = %d\n",
66090 + client->addr, *out_len);
66091 +
66092 + if (err < 0) {
66093 + dev_err(&client->dev, "ERROR: i2c Read at 0x%x, "
66094 + "*val=%d flags=%d bytes read=%d err=%d\n",
66095 + reg, *val, msg->flags, i, err);
66096 + return err;
66097 + }
66098 + return 0;
66099 +}
66100 +
66101 +static int sil9022_write_reg(struct omap_dss_device *dssdev,
66102 + u8 reg, unsigned int val)
66103 +{
66104 + struct panel_drv_data *ddata = to_panel_data(dssdev);
66105 + struct regmap *map = ddata->regmap;
66106 + int err = 0;
66107 + err = regmap_write(map, reg, val);
66108 + return err;
66109 +}
66110 +
66111 +static int sil9022_read_reg(struct omap_dss_device *dssdev,
66112 + u8 reg, unsigned int *val)
66113 +{
66114 + struct panel_drv_data *ddata = to_panel_data(dssdev);
66115 + struct regmap *map = ddata->regmap;
66116 + int err = 0;
66117 + err = regmap_read(map, reg, val);
66118 + return err;
66119 +}
66120 +
66121 +static int sil9022_hw_enable(struct omap_dss_device *dssdev)
66122 +{
66123 + int err;
66124 + u8 vals[14];
66125 + unsigned int val;
66126 + u16 out_len = 0;
66127 + u16 horizontal_res;
66128 + u16 vertical_res;
66129 + u16 pixel_clk;
66130 +
66131 + struct panel_drv_data *ddata = to_panel_data(dssdev);
66132 + struct omap_video_timings *hdmi_timings = &ddata->timings;
66133 + struct i2c_client *sil9022_client = ddata->i2c_client;
66134 +
66135 + memset(vals, 0, 14);
66136 +
66137 + horizontal_res = hdmi_timings->x_res;
66138 + vertical_res = hdmi_timings->y_res;
66139 + pixel_clk = hdmi_timings->pixel_clock;
66140 +
66141 + dev_info(dssdev->dev,
66142 + "HW_ENABLE -> Timings\n"
66143 + "pixel_clk = %d\n"
66144 + "horizontal res = %d\n"
66145 + "vertical res = %d\n",
66146 + hdmi_timings->pixel_clock,
66147 + hdmi_timings->x_res,
66148 + hdmi_timings->y_res
66149 + );
66150 +
66151 + /* Fill the TPI Video Mode Data structure */
66152 + vals[0] = (pixel_clk & 0xFF); /* Pixel clock */
66153 + vals[1] = ((pixel_clk & 0xFF00) >> 8);
66154 + vals[2] = VERTICAL_FREQ; /* Vertical freq */
66155 + /* register programming information on how vertical freq is to be
66156 + programmed to Sil9022 not clear. Hence setting to 60 for now */
66157 + vals[3] = 0x00;
66158 + vals[4] = (horizontal_res & 0xFF); /* Horizontal pixels*/
66159 + vals[5] = ((horizontal_res & 0xFF00) >> 8);
66160 + vals[6] = (vertical_res & 0xFF); /* Vertical pixels */
66161 + vals[7] = ((vertical_res & 0xFF00) >> 8);
66162 +
66163 + /* Write out the TPI Video Mode Data */
66164 + out_len = 0;
66165 + err = sil9022_blockwrite_reg(sil9022_client,
66166 + HDMI_TPI_VIDEO_DATA_BASE_REG,
66167 + 8, vals, &out_len);
66168 + if (err < 0) {
66169 + dev_err(dssdev->dev,
66170 + "ERROR: writing TPI video mode data\n");
66171 + return err;
66172 + }
66173 +
66174 + /* Write out the TPI Input bus and pixel repetition Data:
66175 + (24 bit wide bus, falling edge, no pixel replication, 1:1 CLK ration) */
66176 + val = TPI_AVI_PIXEL_REP_BUS_24BIT |
66177 + TPI_AVI_PIXEL_REP_FALLING_EDGE |
66178 + TPI_AVI_PIXEL_REP_NONE | TPI_CLK_RATIO_1X;
66179 + err = sil9022_write_reg(dssdev,
66180 + HDMI_TPI_PIXEL_REPETITION_REG,
66181 + val);
66182 +
66183 + if (err < 0) {
66184 + dev_err(dssdev->dev,
66185 + "ERROR: writing TPI pixel repetition data\n");
66186 + return err;
66187 + }
66188 +
66189 + /* Write out the TPI AVI Input Format */
66190 + val = TPI_AVI_INPUT_BITMODE_8BIT |
66191 + TPI_AVI_INPUT_RANGE_AUTO |
66192 + TPI_AVI_INPUT_COLORSPACE_RGB;
66193 + err = sil9022_write_reg(dssdev,
66194 + HDMI_TPI_AVI_IN_FORMAT_REG,
66195 + val);
66196 + if (err < 0) {
66197 + dev_err(dssdev->dev,
66198 + "ERROR: writing TPI AVI Input format\n");
66199 + return err;
66200 + }
66201 +
66202 + /* Write out the TPI AVI Output Format */
66203 + val = TPI_AVI_OUTPUT_CONV_BT709 |
66204 + TPI_AVI_OUTPUT_RANGE_AUTO |
66205 + TPI_AVI_OUTPUT_COLORSPACE_RGBHDMI;
66206 + err = sil9022_write_reg(dssdev,
66207 + HDMI_TPI_AVI_OUT_FORMAT_REG, val);
66208 + if (err < 0) {
66209 + dev_err(dssdev->dev,
66210 + "ERROR: writing TPI AVI output format\n");
66211 + return err;
66212 + }
66213 +
66214 + /* Write out the TPI System Control Data to power down */
66215 + val = TPI_SYS_CTRL_POWER_DOWN;
66216 + err = sil9022_write_reg(dssdev, HDMI_SYS_CTRL_DATA_REG, val);
66217 + if (err < 0) {
66218 + dev_err(dssdev->dev,
66219 + "ERROR: writing TPI power down control data\n");
66220 + return err;
66221 + }
66222 +
66223 + /* Move from ENABLED -> FULLY ENABLED Power State */
66224 + val = TPI_AVI_POWER_STATE_D0;
66225 + err = sil9022_write_reg(dssdev,
66226 + HDMI_TPI_POWER_STATE_CTRL_REG, val);
66227 + if (err < 0) {
66228 + dev_err(&sil9022_client->dev,
66229 + "<%s> ERROR: Setting device power state to D0\n",
66230 + __func__);
66231 + return err;
66232 + }
66233 +
66234 + /* Write out the TPI System Control Data to power up and
66235 + * select output mode
66236 + */
66237 + val = TPI_SYS_CTRL_POWER_ACTIVE | TPI_SYS_CTRL_OUTPUT_MODE_HDMI;
66238 + err = sil9022_write_reg(dssdev, HDMI_SYS_CTRL_DATA_REG, val);
66239 + if (err < 0) {
66240 + dev_err(&sil9022_client->dev,
66241 + "<%s> ERROR: Writing system control data\n", __func__);
66242 + return err;
66243 + }
66244 +
66245 + /* Read back TPI System Control Data to latch settings */
66246 + msleep(20);
66247 + err = sil9022_read_reg(dssdev, HDMI_SYS_CTRL_DATA_REG, &val);
66248 + if (err < 0) {
66249 + dev_err(&sil9022_client->dev,
66250 + "<%s> ERROR: Writing system control data\n",
66251 + __func__);
66252 + return err;
66253 + }
66254 +
66255 + /* HDCP */
66256 + val = 0; /* DISABLED */
66257 + err = sil9022_write_reg(dssdev,
66258 + HDMI_TPI_HDCP_CONTROLDATA_REG, val);
66259 + if (err < 0) {
66260 + dev_err(&sil9022_client->dev,
66261 + "<%s> ERROR: Enable (1) / Disable (0) => HDCP: %d\n",
66262 + __func__, val);
66263 + return err;
66264 + }
66265 +
66266 + dev_info(&sil9022_client->dev, "<%s> hdmi enabled\n", __func__);
66267 + return 0;
66268 +
66269 +}
66270 +
66271 +static int sil9022_hw_disable(struct omap_dss_device *dssdev)
66272 +{
66273 + unsigned int val = 0;
66274 + int err = 0;
66275 +
66276 + /* Write out the TPI System Control Data to power down */
66277 + val = TPI_SYS_CTRL_POWER_DOWN;
66278 + err = sil9022_write_reg(dssdev, HDMI_SYS_CTRL_DATA_REG, val);
66279 + if (err < 0) {
66280 + dev_err(dssdev->dev,
66281 + "ERROR: writing control data - power down\n");
66282 + return err;
66283 + }
66284 +
66285 + /* Move from FULLY ENABLED -> ENABLED Power state */
66286 + val = TPI_AVI_POWER_STATE_D2;
66287 + err = sil9022_write_reg(dssdev,
66288 + HDMI_TPI_DEVICE_POWER_STATE_DATA, val);
66289 + if (err < 0) {
66290 + dev_err(dssdev->dev,
66291 + "ERROR: Setting device power state to D2\n");
66292 + return err;
66293 + }
66294 +
66295 + /* Read back TPI System Control Data to latch settings */
66296 + mdelay(10);
66297 + err = sil9022_read_reg(dssdev, HDMI_SYS_CTRL_DATA_REG, &val);
66298 + if (err < 0) {
66299 + dev_err(dssdev->dev,
66300 + "ERROR: Reading System control data "
66301 + "- latch settings\n");
66302 + return err;
66303 + }
66304 +
66305 + dev_info(dssdev->dev, "hdmi disabled\n");
66306 + return 0;
66307 +
66308 +}
66309 +
66310 +static int sil9022_probe_chip_version(struct omap_dss_device *dssdev)
66311 +{
66312 + int err = 0;
66313 + unsigned int ver;
66314 +
66315 + /* probe for sil9022 chip version*/
66316 + err = sil9022_write_reg(dssdev, SIL9022_REG_TPI_RQB, 0x00);
66317 + if (err < 0) {
66318 + dev_err(dssdev->dev,
66319 + "ERROR: Writing HDMI configuration to "
66320 + "reg - SI9022_REG_TPI_RQB\n");
66321 + err = -ENODEV;
66322 + return err;
66323 + }
66324 +
66325 + err = sil9022_read_reg(dssdev, SIL9022_REG_CHIPID0, &ver);
66326 + if (err < 0) {
66327 + dev_err(dssdev->dev,
66328 + "ERROR: Reading HDMI version Id\n");
66329 + err = -ENODEV;
66330 + } else if (ver != SIL9022_CHIPID_902x) {
66331 + dev_err(dssdev->dev,
66332 + "Not a valid verId: 0x%x\n", ver);
66333 + err = -ENODEV;
66334 + } else {
66335 + dev_info(dssdev->dev,
66336 + "sil9022 HDMI Chip version = %x\n", ver);
66337 + }
66338 + return err;
66339 +}
66340 +
66341 +/* Hdmi ops */
66342 +
66343 +static int sil9022_connect(struct omap_dss_device *dssdev,
66344 + struct omap_dss_device *dst)
66345 +{
66346 + struct panel_drv_data *ddata = to_panel_data(dssdev);
66347 + struct omap_dss_device *in = ddata->in;
66348 + int err;
66349 +
66350 + dev_err(dssdev->dev, "CONNECT\n");
66351 +
66352 + if (omapdss_device_is_connected(dssdev))
66353 + return -EBUSY;
66354 +
66355 + err = in->ops.dpi->connect(in, dssdev);
66356 + if (err)
66357 + return err;
66358 +
66359 + dst->src = dssdev;
66360 + dssdev->dst = dst;
66361 +
66362 + /* Move from LOW -> ENABLED Power state */
66363 + err = sil9022_write_reg(dssdev, HDMI_TPI_POWER_STATE_CTRL_REG,
66364 + TPI_AVI_POWER_STATE_D2);
66365 + if (err < 0) {
66366 + dev_err(dssdev->dev, "ERROR: Setting device power state to D2\n");
66367 + return err;
66368 + }
66369 +
66370 + return 0;
66371 +
66372 +}
66373 +
66374 +static void sil9022_disconnect(struct omap_dss_device *dssdev,
66375 + struct omap_dss_device *dst)
66376 +{
66377 + struct panel_drv_data *ddata = to_panel_data(dssdev);
66378 + struct omap_dss_device *in = ddata->in;
66379 + int err;
66380 +
66381 + WARN_ON(!omapdss_device_is_connected(dssdev));
66382 + if (!omapdss_device_is_connected(dssdev))
66383 + return;
66384 +
66385 + WARN_ON(dst != dssdev->dst);
66386 + if (dst != dssdev->dst)
66387 + return;
66388 +
66389 + dst->src = NULL;
66390 + dssdev->dst = NULL;
66391 +
66392 + /* Move from ENABLED -> LOW Power state */
66393 + err = sil9022_write_reg(dssdev, HDMI_TPI_POWER_STATE_CTRL_REG,
66394 + TPI_AVI_POWER_STATE_D3);
66395 + if (err < 0) {
66396 + dev_err(dssdev->dev, "ERROR: Setting device power state to D3\n");
66397 + }
66398 +
66399 + in->ops.dpi->disconnect(in, &ddata->dssdev);
66400 + return;
66401 +
66402 +}
66403 +
66404 +static int sil9022_enable(struct omap_dss_device *dssdev)
66405 +{
66406 + struct panel_drv_data *ddata = to_panel_data(dssdev);
66407 + struct omap_dss_device *in = ddata->in;
66408 + int r;
66409 +
66410 + dev_err(dssdev->dev, "ENABLE\n");
66411 +
66412 + if (!omapdss_device_is_connected(dssdev))
66413 + return -ENODEV;
66414 +
66415 + if (omapdss_device_is_enabled(dssdev))
66416 + return 0;
66417 +
66418 + in->ops.dpi->set_timings(in, &ddata->timings);
66419 + in->ops.dpi->set_data_lines(in, ddata->data_lines);
66420 +
66421 + r = in->ops.dpi->enable(in);
66422 + if (r)
66423 + return r;
66424 +
66425 + if (gpio_is_valid(ddata->reset_gpio))
66426 + gpio_set_value_cansleep(ddata->reset_gpio, 0);
66427 +
66428 + r = sil9022_hw_enable(dssdev);
66429 + if (r)
66430 + return r;
66431 +
66432 + dssdev->state = OMAP_DSS_DISPLAY_ACTIVE;
66433 + return 0;
66434 +}
66435 +
66436 +static void sil9022_disable(struct omap_dss_device *dssdev)
66437 +{
66438 + struct panel_drv_data *ddata = to_panel_data(dssdev);
66439 + struct omap_dss_device *in = ddata->in;
66440 +
66441 + if (!omapdss_device_is_enabled(dssdev))
66442 + return;
66443 +
66444 + if (!sil9022_hw_disable(dssdev))
66445 + return;
66446 +
66447 + if (gpio_is_valid(ddata->reset_gpio))
66448 + gpio_set_value_cansleep(ddata->reset_gpio, 1);
66449 +
66450 + in->ops.dpi->disable(in);
66451 +
66452 + dssdev->state = OMAP_DSS_DISPLAY_DISABLED;
66453 + return;
66454 +}
66455 +
66456 +static void sil9022_set_timings(struct omap_dss_device *dssdev,
66457 + struct omap_video_timings *timings)
66458 +{
66459 + struct panel_drv_data *ddata = to_panel_data(dssdev);
66460 + struct omap_dss_device *in = ddata->in;
66461 + struct omap_video_timings *sil9022_timings = timings;
66462 +
66463 + /* update DPI specific timing info */
66464 + sil9022_timings->data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE;
66465 + sil9022_timings->de_level = OMAPDSS_SIG_ACTIVE_HIGH;
66466 + sil9022_timings->sync_pclk_edge = OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES;
66467 + ddata->timings = *sil9022_timings;
66468 + dssdev->panel.timings = *sil9022_timings;
66469 +
66470 + in->ops.dpi->set_timings(in, sil9022_timings);
66471 + return;
66472 +}
66473 +
66474 +static void sil9022_get_timings(struct omap_dss_device *dssdev,
66475 + struct omap_video_timings *timings)
66476 +{
66477 + struct panel_drv_data *ddata = to_panel_data(dssdev);
66478 + *timings = ddata->timings;
66479 + return;
66480 +}
66481 +
66482 +static int sil9022_check_timings(struct omap_dss_device *dssdev,
66483 + struct omap_video_timings *timings)
66484 +{
66485 + struct panel_drv_data *ddata = to_panel_data(dssdev);
66486 + struct omap_dss_device *in = ddata->in;
66487 + struct omap_video_timings *sil9022_timings = timings;
66488 +
66489 + /* update DPI specific timing info */
66490 + sil9022_timings->data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE;
66491 + sil9022_timings->de_level = OMAPDSS_SIG_ACTIVE_HIGH;
66492 + sil9022_timings->sync_pclk_edge = OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES;
66493 +
66494 + return in->ops.dpi->check_timings(in, sil9022_timings);
66495 +}
66496 +
66497 +static int sil9022_read_edid(struct omap_dss_device *dssdev,
66498 + u8 *edid, int len)
66499 +{
66500 +
66501 + int err = 0;
66502 + unsigned int val = 0;
66503 + int retries = 0;
66504 + u16 out_len = 0;
66505 + int i2c_client_addr;
66506 + struct panel_drv_data *ddata = to_panel_data(dssdev);
66507 + struct i2c_client *client = ddata->i2c_client;
66508 +
66509 + len = (len < HDMI_EDID_MAX_LENGTH) ? len : HDMI_EDID_MAX_LENGTH;
66510 +
66511 + /* Request DDC bus access to read EDID info from HDTV */
66512 + dev_info(&client->dev, "Reading HDMI EDID\n");
66513 +
66514 + val = 0;
66515 + err = sil9022_read_reg(dssdev, 0x3D, &val);
66516 + if (err < 0) {
66517 + dev_err(&client->dev,
66518 + "ERROR: Reading Monitor Status register\n");
66519 + return err;
66520 + }
66521 +
66522 + if (val & 0x2)
66523 + dev_err(&client->dev, " MONITOR PRESENT \n");
66524 + else
66525 + dev_err(&client->dev, " MONITOR NOT PRESENT \n");
66526 +
66527 + /* Disable TMDS clock */
66528 + val = 0x11;
66529 + err = sil9022_write_reg(dssdev, HDMI_SYS_CTRL_DATA_REG, val);
66530 + if (err < 0) {
66531 + dev_err(&client->dev,
66532 + "ERROR: Failed to disable TMDS clock\n");
66533 + return err;
66534 + }
66535 +
66536 + val = 0;
66537 +
66538 + /* Read TPI system control register*/
66539 + err = sil9022_read_reg(dssdev, HDMI_SYS_CTRL_DATA_REG, &val);
66540 + if (err < 0) {
66541 + dev_err(&client->dev,
66542 + "ERROR: Reading DDC BUS REQUEST\n");
66543 + return err;
66544 + }
66545 +
66546 + /* The host writes 0x1A[2]=1 to request the
66547 + * DDC(Display Data Channel) bus
66548 + */
66549 + val |= TPI_SYS_CTRL_DDC_BUS_REQUEST;
66550 + err = sil9022_write_reg(dssdev, HDMI_SYS_CTRL_DATA_REG, val);
66551 + if (err < 0) {
66552 + dev_err(&client->dev,
66553 + "ERROR: Writing DDC BUS REQUEST\n");
66554 + return err;
66555 + }
66556 +
66557 + /* Poll for bus DDC Bus control to be granted */
66558 + dev_info(&client->dev, "Poll for DDC bus access\n");
66559 + val = 0;
66560 + do {
66561 + err = sil9022_read_reg(dssdev, HDMI_SYS_CTRL_DATA_REG, &val);
66562 + if (retries++ > 100)
66563 + return err;
66564 +
66565 + } while ((val & TPI_SYS_CTRL_DDC_BUS_GRANTED) == 0);
66566 +
66567 + /* Close the switch to the DDC */
66568 + val |= TPI_SYS_CTRL_DDC_BUS_REQUEST | TPI_SYS_CTRL_DDC_BUS_GRANTED;
66569 + err = sil9022_write_reg(dssdev, HDMI_SYS_CTRL_DATA_REG, val);
66570 + if (err < 0) {
66571 + dev_err(&client->dev,
66572 + "<%s> ERROR: Close switch to DDC BUS REQUEST\n",
66573 + __func__);
66574 + return err;
66575 + }
66576 +
66577 + memset(edid, 0, len);
66578 + /* change I2C SetSlaveAddress to HDMI_I2C_MONITOR_ADDRESS */
66579 + /* Read the EDID structure from the monitor I2C address */
66580 + i2c_client_addr = client->addr;
66581 + client->addr = HDMI_I2C_MONITOR_ADDRESS;
66582 + err = sil9022_blockread_reg(client, 1, len,
66583 + 0x00, edid, &out_len);
66584 + if (err < 0 || out_len <= 0) {
66585 + dev_err(&client->dev, "ERROR: Reading EDID\n");
66586 + return err;
66587 + }
66588 +
66589 + /* Release DDC bus access */
66590 + client->addr = i2c_client_addr;
66591 + val &= ~(TPI_SYS_CTRL_DDC_BUS_REQUEST | TPI_SYS_CTRL_DDC_BUS_GRANTED);
66592 +
66593 + retries = 0;
66594 + do {
66595 + err = sil9022_write_reg(dssdev, HDMI_SYS_CTRL_DATA_REG, val);
66596 + if (err >= 0)
66597 + break;
66598 + retries++;
66599 + } while (retries < 5);
66600 + if (err < 0) {
66601 + dev_err(&client->dev, "ERROR: Releasing DDC Bus Access\n");
66602 + return err;
66603 + }
66604 +
66605 + print_hex_dump(KERN_ERR, "\t", DUMP_PREFIX_NONE, 16, 1, edid, len, 0);
66606 +
66607 + return 0;
66608 +
66609 +}
66610 +
66611 +static bool sil9022_detect(struct omap_dss_device *dssdev)
66612 +{
66613 + /* Hot plug detection is not implemented */
66614 + /* Hence we assume monitor connected */
66615 + /* This will be fixed once HPD / polling is implemented */
66616 + return true;
66617 +}
66618 +
66619 +static bool sil9022_audio_supported(struct omap_dss_device *dssdev)
66620 +{
66621 + /* Audio configuration not present, hence returning false */
66622 + return false;
66623 +}
66624 +
66625 +static const struct omapdss_hdmi_ops sil9022_hdmi_ops = {
66626 + .connect = sil9022_connect,
66627 + .disconnect = sil9022_disconnect,
66628 +
66629 + .enable = sil9022_enable,
66630 + .disable = sil9022_disable,
66631 +
66632 + .check_timings = sil9022_check_timings,
66633 + .set_timings = sil9022_set_timings,
66634 + .get_timings = sil9022_get_timings,
66635 +
66636 + .read_edid = sil9022_read_edid,
66637 + .detect = sil9022_detect,
66638 +
66639 + .audio_supported = sil9022_audio_supported,
66640 + /* Yet to implement audio ops */
66641 + /* For now audio_supported ops to return false */
66642 +};
66643 +
66644 +
66645 +static int sil9022_probe_of(struct i2c_client *client)
66646 +{
66647 + struct panel_drv_data *ddata = dev_get_drvdata(&client->dev);
66648 + struct device_node *node = client->dev.of_node;
66649 + struct device_node *src_node;
66650 + struct omap_dss_device *dssdev, *in;
66651 +
66652 + int r, reset_gpio, datalines;
66653 +
66654 + src_node = of_parse_phandle(node, "video-source", 0);
66655 + if (!src_node) {
66656 + dev_err(&client->dev, "failed to parse video source\n");
66657 + return -ENODEV;
66658 + }
66659 +
66660 + in = omap_dss_find_output_by_node(src_node);
66661 + if (in == NULL) {
66662 + dev_err(&client->dev, "failed to find video source\n");
66663 + return -EPROBE_DEFER;
66664 + }
66665 + ddata->in = in;
66666 +
66667 + reset_gpio = of_get_named_gpio(node, "reset-gpio", 0);
66668 +
66669 + if (gpio_is_valid(reset_gpio) || reset_gpio == -ENOENT) {
66670 + ddata->reset_gpio = reset_gpio;
66671 + } else {
66672 + dev_err(&client->dev, "failed to parse lcdorhdmi gpio\n");
66673 + return reset_gpio;
66674 + }
66675 +
66676 + r = of_property_read_u32(node, "data-lines", &datalines);
66677 + if (r) {
66678 + dev_err(&client->dev, "failed to parse datalines\n");
66679 + return r;
66680 + }
66681 +
66682 + ddata->data_lines = datalines;
66683 + ddata->reset_gpio = reset_gpio;
66684 + dssdev = &ddata->dssdev;
66685 +
66686 + return 0;
66687 +
66688 +}
66689 +static int sil9022_probe_pdata(struct i2c_client *client)
66690 +{
66691 + struct encoder_sil9022_platform_data *pdata;
66692 + struct panel_drv_data *ddata = dev_get_drvdata(&client->dev);
66693 + struct omap_dss_device *dssdev, *in;
66694 + pdata = dev_get_platdata(&client->dev);
66695 +
66696 + ddata->reset_gpio = pdata->reset_gpio;
66697 + ddata->data_lines = pdata->data_lines;
66698 +
66699 + in = omap_dss_find_output(pdata->source);
66700 + if (in == NULL) {
66701 + dev_err(&client->dev, "Failed to find video source\n");
66702 + return -ENODEV;
66703 + }
66704 +
66705 + ddata->in = in;
66706 + dssdev = &ddata->dssdev;
66707 + dssdev->name = pdata->name;
66708 +
66709 + return 0;
66710 +}
66711 +
66712 +static int sil9022_probe(struct i2c_client *client,
66713 + const struct i2c_device_id *id)
66714 +{
66715 + struct panel_drv_data *ddata;
66716 + struct omap_dss_device *dssdev;
66717 + struct regmap *regmap;
66718 + int err = 0;
66719 +
66720 + regmap = devm_regmap_init_i2c(client, &sil9022_regmap_config);
66721 + if (IS_ERR(regmap)) {
66722 + err = PTR_ERR(regmap);
66723 + dev_err(&client->dev, "Failed to init regmap: %d\n", err);
66724 + return err;
66725 + }
66726 +
66727 + ddata = devm_kzalloc(&client->dev, sizeof(*ddata), GFP_KERNEL);
66728 + if (ddata == NULL)
66729 + return -ENOMEM;
66730 +
66731 + dev_set_drvdata(&client->dev, ddata);
66732 +
66733 + if (dev_get_platdata(&client->dev)) {
66734 + err = sil9022_probe_pdata(client);
66735 + if (err)
66736 + return err;
66737 + } else if (client->dev.of_node) {
66738 + err = sil9022_probe_of(client);
66739 + if (err)
66740 + return err;
66741 + } else {
66742 + return -ENODEV;
66743 + }
66744 +
66745 + if (gpio_is_valid(ddata->reset_gpio)) {
66746 + err = devm_gpio_request_one(&client->dev, ddata->reset_gpio,
66747 + GPIOF_OUT_INIT_HIGH, "Sil9022-Encoder");
66748 + if (err)
66749 + goto err_gpio;
66750 + }
66751 +
66752 + ddata->regmap = regmap;
66753 + ddata->i2c_client = client;
66754 + dssdev = &ddata->dssdev;
66755 + dssdev->dev = &client->dev;
66756 + dssdev->ops.hdmi = &sil9022_hdmi_ops;
66757 + dssdev->type = OMAP_DISPLAY_TYPE_DPI;
66758 + dssdev->output_type = OMAP_DISPLAY_TYPE_HDMI;
66759 + dssdev->owner = THIS_MODULE;
66760 + dssdev->phy.dpi.data_lines = ddata->data_lines;
66761 + err = omapdss_register_output(dssdev);
66762 + if (err) {
66763 + dev_err(&client->dev, "Failed to register output\n");
66764 + goto err_reg;
66765 + }
66766 +
66767 + /* Read sil9022 chip version */
66768 + err = sil9022_probe_chip_version(dssdev);
66769 + if (err) {
66770 + dev_err(&client->dev, "Failed to read CHIP VERSION\n");
66771 + goto err_i2c;
66772 + }
66773 +
66774 + return 0;
66775 +
66776 +err_gpio:
66777 +err_reg:
66778 +err_i2c:
66779 + omap_dss_put_device(ddata->in);
66780 + return err;
66781 +}
66782 +
66783 +
66784 +static int sil9022_remove(struct i2c_client *client)
66785 +{
66786 + struct panel_drv_data *ddata = dev_get_drvdata(&client->dev);
66787 + struct omap_dss_device *dssdev = &ddata->dssdev;
66788 +
66789 + omapdss_unregister_output(&ddata->dssdev);
66790 +
66791 + WARN_ON(omapdss_device_is_enabled(dssdev));
66792 + if (omapdss_device_is_enabled(dssdev))
66793 + sil9022_disable(dssdev);
66794 +
66795 + WARN_ON(omapdss_device_is_connected(dssdev));
66796 + if (omapdss_device_is_connected(dssdev))
66797 + sil9022_disconnect(dssdev, dssdev->dst);
66798 +
66799 + omap_dss_put_device(ddata->in);
66800 +
66801 + if (!client->adapter) {
66802 + dev_err(&client->dev, "No HDMI Device\n");
66803 + return -ENODEV;
66804 + }
66805 +
66806 + return 0;
66807 +}
66808 +
66809 +static const struct i2c_device_id sil9022_id[] = {
66810 + { SIL9022_DRV_NAME, 0 },
66811 + { },
66812 +};
66813 +
66814 +MODULE_DEVICE_TABLE(i2c, sil9022_id);
66815 +
66816 +static struct i2c_driver sil9022_driver = {
66817 + .driver = {
66818 + .name = SIL9022_DRV_NAME,
66819 + .owner = THIS_MODULE,
66820 + },
66821 + .probe = sil9022_probe,
66822 + .remove = sil9022_remove,
66823 + .id_table = sil9022_id,
66824 +};
66825 +
66826 +module_i2c_driver(sil9022_driver);
66827 +
66828 +MODULE_AUTHOR("Sathya Prakash M R <sathyap@ti.com>");
66829 +MODULE_DESCRIPTION("Sil9022 DPI to HDMI encoder Driver");
66830 +MODULE_LICENSE("GPL");
66831 --- /dev/null
66832 +++ b/drivers/video/omap2/displays-new/encoder-sil9022.h
66833 @@ -0,0 +1,123 @@
66834 +/*
66835 + * drivers/video/omap2/displays-new/encoder-sil9022.c
66836 + *
66837 + * Copyright (C) 2013 Texas Instruments
66838 + * Author : Sathya Prakash M R <sathyap@ti.com>
66839 + *
66840 + * This file is licensed under the terms of the GNU General Public License
66841 + * version 2. This program is licensed "as is" without any warranty of any
66842 + * kind, whether express or implied.
66843 + *
66844 + */
66845 +
66846 +#ifndef _SI9022_H_
66847 +#define _SI9022_H_
66848 +
66849 +#define SIL9022_DRV_NAME "sii9022"
66850 +
66851 +#define SIL9022_REG_CHIPID0 0x1B
66852 +#define SIL9022_REG_TPI_RQB 0xC7
66853 +#define SIL9022_CHIPID_902x 0xB0
66854 +
66855 +#define HDMI_I2C_MONITOR_ADDRESS 0x50
66856 +
66857 +/* HDMI EDID Length */
66858 +#define HDMI_EDID_MAX_LENGTH 256
66859 +
66860 +#define VERTICAL_FREQ 0x3C
66861 +
66862 +/* HDMI TPI Registers */
66863 +#define HDMI_TPI_VIDEO_DATA_BASE_REG 0x00
66864 +#define HDMI_TPI_PIXEL_CLK_LSB_REG (HDMI_TPI_VIDEO_DATA_BASE_REG + 0x00)
66865 +#define HDMI_TPI_PIXEL_CLK_MSB_REG (HDMI_TPI_VIDEO_DATA_BASE_REG + 0x01)
66866 +#define HDMI_TPI_VFREQ_LSB_REG (HDMI_TPI_VIDEO_DATA_BASE_REG + 0x02)
66867 +#define HDMI_TPI_VFREQ_MSB_REG (HDMI_TPI_VIDEO_DATA_BASE_REG + 0x03)
66868 +#define HDMI_TPI_PIXELS_LSB_REG (HDMI_TPI_VIDEO_DATA_BASE_REG + 0x04)
66869 +#define HDMI_TPI_PIXELS_MSB_REG (HDMI_TPI_VIDEO_DATA_BASE_REG + 0x05)
66870 +#define HDMI_TPI_LINES_LSB_REG (HDMI_TPI_VIDEO_DATA_BASE_REG + 0x06)
66871 +#define HDMI_TPI_LINES_MSB_REG (HDMI_TPI_VIDEO_DATA_BASE_REG + 0x07)
66872 +
66873 +#define HDMI_TPI_PIXEL_REPETITION_REG 0x08
66874 +
66875 +#define HDMI_TPI_AVI_INOUT_BASE_REG 0x09
66876 +#define HDMI_TPI_AVI_IN_FORMAT_REG (HDMI_TPI_AVI_INOUT_BASE_REG + 0x00)
66877 +#define HDMI_TPI_AVI_OUT_FORMAT_REG (HDMI_TPI_AVI_INOUT_BASE_REG + 0x01)
66878 +
66879 +#define HDMI_SYS_CTRL_DATA_REG 0x1A
66880 +#define HDMI_TPI_POWER_STATE_CTRL_REG 0x1E
66881 +#define HDMI_TPI_DEVICE_POWER_STATE_DATA 0x1E
66882 +
66883 +
66884 +/* HDCP */
66885 +#define HDMI_TPI_HDCP_QUERYDATA_REG 0x29
66886 +#define HDMI_TPI_HDCP_CONTROLDATA_REG 0x2A
66887 +
66888 +/* HDMI_TPI_DEVICE_ID_REG */
66889 +#define TPI_DEVICE_ID 0xB0
66890 +
66891 +/* HDMI_TPI_REVISION_REG */
66892 +#define TPI_REVISION 0x00
66893 +
66894 +/* HDMI_TPI_ID_BYTE2_REG */
66895 +#define TPI_ID_BYTE2_VALUE 0x00
66896 +
66897 +/* HDMI_SYS_CTRL_DATA_REG */
66898 +#define TPI_SYS_CTRL_POWER_DOWN (1 << 4)
66899 +#define TPI_SYS_CTRL_POWER_ACTIVE (0 << 4)
66900 +#define TPI_SYS_CTRL_AV_MUTE (1 << 3)
66901 +#define TPI_SYS_CTRL_DDC_BUS_REQUEST (1 << 2)
66902 +#define TPI_SYS_CTRL_DDC_BUS_GRANTED (1 << 1)
66903 +#define TPI_SYS_CTRL_OUTPUT_MODE_HDMI (1 << 0)
66904 +#define TPI_SYS_CTRL_OUTPUT_MODE_DVI (0 << 0)
66905 +
66906 +/* HDMI_TPI_PIXEL_REPETITION */
66907 +#define TPI_AVI_PIXEL_REP_BUS_24BIT (1 << 5)
66908 +#define TPI_AVI_PIXEL_REP_BUS_12BIT (0 << 5)
66909 +#define TPI_AVI_PIXEL_REP_RISING_EDGE (1 << 4)
66910 +#define TPI_AVI_PIXEL_REP_FALLING_EDGE (0 << 4)
66911 +#define TPI_AVI_PIXEL_REP_4X (3 << 0)
66912 +#define TPI_AVI_PIXEL_REP_2X (1 << 0)
66913 +#define TPI_AVI_PIXEL_REP_NONE (0 << 0)
66914 +
66915 +/*Ratio of TDMS Clock to input Video Clock*/
66916 +#define TPI_CLK_RATIO_HALF (0 << 6)
66917 +#define TPI_CLK_RATIO_1X (1 << 6)
66918 +#define TPI_CLK_RATIO_2X (2 << 6)
66919 +#define TPI_CLK_RATIO_4X (3 << 6)
66920 +
66921 +
66922 +/* HDMI_TPI_AVI_INPUT_FORMAT */
66923 +#define TPI_AVI_INPUT_BITMODE_12BIT (1 << 7)
66924 +#define TPI_AVI_INPUT_BITMODE_8BIT (0 << 7)
66925 +#define TPI_AVI_INPUT_DITHER (1 << 6)
66926 +#define TPI_AVI_INPUT_RANGE_LIMITED (2 << 2)
66927 +#define TPI_AVI_INPUT_RANGE_FULL (1 << 2)
66928 +#define TPI_AVI_INPUT_RANGE_AUTO (0 << 2)
66929 +#define TPI_AVI_INPUT_COLORSPACE_BLACK (3 << 0)
66930 +#define TPI_AVI_INPUT_COLORSPACE_YUV422 (2 << 0)
66931 +#define TPI_AVI_INPUT_COLORSPACE_YUV444 (1 << 0)
66932 +#define TPI_AVI_INPUT_COLORSPACE_RGB (0 << 0)
66933 +
66934 +
66935 +/* HDMI_TPI_AVI_OUTPUT_FORMAT */
66936 +#define TPI_AVI_OUTPUT_CONV_BT709 (1 << 4)
66937 +#define TPI_AVI_OUTPUT_CONV_BT601 (0 << 4)
66938 +#define TPI_AVI_OUTPUT_RANGE_LIMITED (2 << 2)
66939 +#define TPI_AVI_OUTPUT_RANGE_FULL (1 << 2)
66940 +#define TPI_AVI_OUTPUT_RANGE_AUTO (0 << 2)
66941 +#define TPI_AVI_OUTPUT_COLORSPACE_RGBDVI (3 << 0)
66942 +#define TPI_AVI_OUTPUT_COLORSPACE_YUV422 (2 << 0)
66943 +#define TPI_AVI_OUTPUT_COLORSPACE_YUV444 (1 << 0)
66944 +#define TPI_AVI_OUTPUT_COLORSPACE_RGBHDMI (0 << 0)
66945 +
66946 +/* HDMI_TPI_DEVICE_POWER_STATE */
66947 +#define TPI_AVI_POWER_STATE_D3 (3 << 0)
66948 +#define TPI_AVI_POWER_STATE_D2 (2 << 0)
66949 +#define TPI_AVI_POWER_STATE_D0 (0 << 0)
66950 +
66951 +struct regmap_config sil9022_regmap_config = {
66952 + .reg_bits = 8,
66953 + .val_bits = 8,
66954 +};
66955 +
66956 +#endif
66957 --- a/drivers/video/omap2/displays-new/encoder-tfp410.c
66958 +++ b/drivers/video/omap2/displays-new/encoder-tfp410.c
66959 @@ -13,6 +13,7 @@
66960 #include <linux/module.h>
66961 #include <linux/platform_device.h>
66962 #include <linux/slab.h>
66963 +#include <linux/of_gpio.h>
66964
66965 #include <video/omapdss.h>
66966 #include <video/omap-panel-data.h>
66967 @@ -179,6 +180,47 @@ static int tfp410_probe_pdata(struct pla
66968 return 0;
66969 }
66970
66971 +static int tfp410_probe_of(struct platform_device *pdev)
66972 +{
66973 + struct panel_drv_data *ddata = platform_get_drvdata(pdev);
66974 + struct device_node *node = pdev->dev.of_node;
66975 + struct omap_dss_device *in;
66976 + struct device_node *src_node;
66977 + int r, gpio, datalines;
66978 +
66979 + src_node = of_parse_phandle(node, "video-source", 0);
66980 + if (!src_node) {
66981 + dev_err(&pdev->dev, "failed to parse video source\n");
66982 + return -ENODEV;
66983 + }
66984 +
66985 + in = omap_dss_find_output_by_node(src_node);
66986 + if (in == NULL) {
66987 + dev_err(&pdev->dev, "failed to find video source\n");
66988 + return -EPROBE_DEFER;
66989 + }
66990 + ddata->in = in;
66991 +
66992 + gpio = of_get_gpio(node, 0);
66993 +
66994 + if (gpio_is_valid(gpio) || gpio == -ENOENT) {
66995 + ddata->pd_gpio = gpio;
66996 + } else {
66997 + dev_err(&pdev->dev, "failed to parse PD gpio\n");
66998 + return gpio;
66999 + }
67000 +
67001 + r = of_property_read_u32(node, "data-lines", &datalines);
67002 + if (r) {
67003 + dev_err(&pdev->dev, "failed to parse datalines\n");
67004 + return r;
67005 + }
67006 +
67007 + ddata->data_lines = datalines;
67008 +
67009 + return 0;
67010 +}
67011 +
67012 static int tfp410_probe(struct platform_device *pdev)
67013 {
67014 struct panel_drv_data *ddata;
67015 @@ -195,6 +237,10 @@ static int tfp410_probe(struct platform_
67016 r = tfp410_probe_pdata(pdev);
67017 if (r)
67018 return r;
67019 + } else if (pdev->dev.of_node) {
67020 + r = tfp410_probe_of(pdev);
67021 + if (r)
67022 + return r;
67023 } else {
67024 return -ENODEV;
67025 }
67026 @@ -251,12 +297,20 @@ static int __exit tfp410_remove(struct p
67027 return 0;
67028 }
67029
67030 +static const struct of_device_id tfp410_of_match[] = {
67031 + { .compatible = "ti,tfp410", },
67032 + {},
67033 +};
67034 +
67035 +MODULE_DEVICE_TABLE(of, tfp410_of_match);
67036 +
67037 static struct platform_driver tfp410_driver = {
67038 .probe = tfp410_probe,
67039 .remove = __exit_p(tfp410_remove),
67040 .driver = {
67041 .name = "tfp410",
67042 .owner = THIS_MODULE,
67043 + .of_match_table = tfp410_of_match,
67044 },
67045 };
67046
67047 --- a/drivers/video/omap2/displays-new/encoder-tpd12s015.c
67048 +++ b/drivers/video/omap2/displays-new/encoder-tpd12s015.c
67049 @@ -15,6 +15,7 @@
67050 #include <linux/slab.h>
67051 #include <linux/gpio.h>
67052 #include <linux/platform_device.h>
67053 +#include <linux/of_gpio.h>
67054
67055 #include <video/omapdss.h>
67056 #include <video/omap-panel-data.h>
67057 @@ -289,6 +290,55 @@ static int tpd_probe_pdata(struct platfo
67058 return 0;
67059 }
67060
67061 +static int tpd_probe_of(struct platform_device *pdev)
67062 +{
67063 + struct panel_drv_data *ddata = platform_get_drvdata(pdev);
67064 + struct device_node *node = pdev->dev.of_node;
67065 + struct omap_dss_device *in;
67066 + struct device_node *src_node;
67067 + int gpio;
67068 +
67069 + src_node = of_parse_phandle(node, "video-source", 0);
67070 + if (!src_node) {
67071 + dev_err(&pdev->dev, "failed to parse video source\n");
67072 + return -ENODEV;
67073 + }
67074 +
67075 + in = omap_dss_find_output_by_node(src_node);
67076 + if (in == NULL) {
67077 + dev_err(&pdev->dev, "failed to find video source\n");
67078 + return -EPROBE_DEFER;
67079 + }
67080 + ddata->in = in;
67081 +
67082 + /* CT CP HPD GPIO */
67083 + gpio = of_get_gpio(node, 0);
67084 + if (!gpio_is_valid(gpio)) {
67085 + dev_err(&pdev->dev, "failed to parse CT CP HPD gpio\n");
67086 + return gpio;
67087 + }
67088 + ddata->ct_cp_hpd_gpio = gpio;
67089 +
67090 + /* LS OE GPIO */
67091 + gpio = of_get_gpio(node, 1);
67092 + if (gpio_is_valid(gpio) || gpio == -ENOENT) {
67093 + ddata->ls_oe_gpio = gpio;
67094 + } else {
67095 + dev_err(&pdev->dev, "failed to parse LS OE gpio\n");
67096 + return gpio;
67097 + }
67098 +
67099 + /* HPD GPIO */
67100 + gpio = of_get_gpio(node, 2);
67101 + if (!gpio_is_valid(gpio)) {
67102 + dev_err(&pdev->dev, "failed to parse HPD gpio\n");
67103 + return gpio;
67104 + }
67105 + ddata->hpd_gpio = gpio;
67106 +
67107 + return 0;
67108 +}
67109 +
67110 static int tpd_probe(struct platform_device *pdev)
67111 {
67112 struct omap_dss_device *in, *dssdev;
67113 @@ -307,6 +357,10 @@ static int tpd_probe(struct platform_dev
67114 r = tpd_probe_pdata(pdev);
67115 if (r)
67116 return r;
67117 + } else if (pdev->dev.of_node) {
67118 + r = tpd_probe_of(pdev);
67119 + if (r)
67120 + return r;
67121 } else {
67122 return -ENODEV;
67123 }
67124 @@ -379,12 +433,20 @@ static int __exit tpd_remove(struct plat
67125 return 0;
67126 }
67127
67128 +static const struct of_device_id tpd_of_match[] = {
67129 + { .compatible = "ti,tpd12s015", },
67130 + {},
67131 +};
67132 +
67133 +MODULE_DEVICE_TABLE(of, tpd_of_match);
67134 +
67135 static struct platform_driver tpd_driver = {
67136 .probe = tpd_probe,
67137 .remove = __exit_p(tpd_remove),
67138 .driver = {
67139 .name = "tpd12s015",
67140 .owner = THIS_MODULE,
67141 + .of_match_table = tpd_of_match,
67142 },
67143 };
67144
67145 --- a/drivers/video/omap2/displays-new/Kconfig
67146 +++ b/drivers/video/omap2/displays-new/Kconfig
67147 @@ -12,6 +12,20 @@ config DISPLAY_ENCODER_TPD12S015
67148 Driver for TPD12S015, which offers HDMI ESD protection and level
67149 shifting.
67150
67151 +config DISPLAY_DRA_EVM_ENCODER_TPD12S015
67152 + tristate "TPD12S015 HDMI ESD protection and level shifter on DRA7 EVM"
67153 + help
67154 + Driver for TPD12S015, which offers HDMI ESD protection and level
67155 + shifting on DRA EVM.
67156 +
67157 +config DISPLAY_ENCODER_SIL9022
67158 + tristate "Sil9022 DPI to HDMI Encoder"
67159 + depends on I2C
67160 + help
67161 + Driver for Silicon Image Sil9022 DPI to HDMI encoder and
67162 + a brief about Sil9022 can be found here:
67163 + http://www.semiconductorstore.com/pdf/newsite/siliconimage/SiI9022a_pb.pdf
67164 +
67165 config DISPLAY_CONNECTOR_DVI
67166 tristate "DVI Connector"
67167 depends on I2C
67168 @@ -71,4 +85,11 @@ config DISPLAY_PANEL_NEC_NL8048HL11
67169 This NEC NL8048HL11 panel is TFT LCD used in the
67170 Zoom2/3/3630 sdp boards.
67171
67172 +config DISPLAY_PANEL_TFCS9700
67173 + tristate "Three Five DPI panel"
67174 + depends on I2C
67175 + help
67176 + A TFT LCD DPI panel used on the LCD daughter board
67177 + of Vayu EVM
67178 +
67179 endmenu
67180 --- a/drivers/video/omap2/displays-new/Makefile
67181 +++ b/drivers/video/omap2/displays-new/Makefile
67182 @@ -1,5 +1,7 @@
67183 obj-$(CONFIG_DISPLAY_ENCODER_TFP410) += encoder-tfp410.o
67184 obj-$(CONFIG_DISPLAY_ENCODER_TPD12S015) += encoder-tpd12s015.o
67185 +obj-$(CONFIG_DISPLAY_DRA_EVM_ENCODER_TPD12S015) += dra-evm-encoder-tpd12s015.o
67186 +obj-$(CONFIG_DISPLAY_ENCODER_SIL9022) += encoder-sil9022.o
67187 obj-$(CONFIG_DISPLAY_CONNECTOR_DVI) += connector-dvi.o
67188 obj-$(CONFIG_DISPLAY_CONNECTOR_HDMI) += connector-hdmi.o
67189 obj-$(CONFIG_DISPLAY_CONNECTOR_ANALOG_TV) += connector-analog-tv.o
67190 @@ -10,3 +12,4 @@ obj-$(CONFIG_DISPLAY_PANEL_LGPHILIPS_LB0
67191 obj-$(CONFIG_DISPLAY_PANEL_SHARP_LS037V7DW01) += panel-sharp-ls037v7dw01.o
67192 obj-$(CONFIG_DISPLAY_PANEL_TPO_TD043MTEA1) += panel-tpo-td043mtea1.o
67193 obj-$(CONFIG_DISPLAY_PANEL_NEC_NL8048HL11) += panel-nec-nl8048hl11.o
67194 +obj-$(CONFIG_DISPLAY_PANEL_TFCS9700) += panel-tfcs9700.o
67195 --- a/drivers/video/omap2/displays-new/panel-dpi.c
67196 +++ b/drivers/video/omap2/displays-new/panel-dpi.c
67197 @@ -13,9 +13,12 @@
67198 #include <linux/module.h>
67199 #include <linux/platform_device.h>
67200 #include <linux/slab.h>
67201 +#include <linux/of.h>
67202 +#include <linux/of_gpio.h>
67203
67204 #include <video/omapdss.h>
67205 #include <video/omap-panel-data.h>
67206 +#include <video/of_display_timing.h>
67207
67208 struct panel_drv_data {
67209 struct omap_dss_device dssdev;
67210 @@ -26,6 +29,7 @@ struct panel_drv_data {
67211 struct omap_video_timings videomode;
67212
67213 int backlight_gpio;
67214 + bool backlight_enable;
67215 int enable_gpio;
67216 };
67217
67218 @@ -81,7 +85,7 @@ static int panel_dpi_enable(struct omap_
67219 gpio_set_value_cansleep(ddata->enable_gpio, 1);
67220
67221 if (gpio_is_valid(ddata->backlight_gpio))
67222 - gpio_set_value_cansleep(ddata->backlight_gpio, 1);
67223 + gpio_set_value_cansleep(ddata->backlight_gpio, ddata->backlight_enable);
67224
67225 dssdev->state = OMAP_DSS_DISPLAY_ACTIVE;
67226
67227 @@ -100,7 +104,7 @@ static void panel_dpi_disable(struct oma
67228 gpio_set_value_cansleep(ddata->enable_gpio, 0);
67229
67230 if (gpio_is_valid(ddata->backlight_gpio))
67231 - gpio_set_value_cansleep(ddata->backlight_gpio, 0);
67232 + gpio_set_value_cansleep(ddata->backlight_gpio, ~(ddata->backlight_enable));
67233
67234 in->ops.dpi->disable(in);
67235
67236 @@ -182,6 +186,73 @@ static int panel_dpi_probe_pdata(struct
67237 return 0;
67238 }
67239
67240 +static int panel_dpi_probe_of(struct platform_device *pdev)
67241 +{
67242 + struct panel_drv_data *ddata = platform_get_drvdata(pdev);
67243 + struct device_node *node = pdev->dev.of_node;
67244 + struct omap_dss_device *in;
67245 + struct device_node *src_node;
67246 + int r, datalines;
67247 + struct display_timing timing;
67248 + struct videomode vm;
67249 + int gpio;
67250 + enum of_gpio_flags gpio_flags;
67251 +
67252 + src_node = of_parse_phandle(node, "video-source", 0);
67253 + if (!src_node) {
67254 + dev_err(&pdev->dev, "failed to parse video source\n");
67255 + return -ENODEV;
67256 + }
67257 +
67258 + in = omap_dss_find_output_by_node(src_node);
67259 + if (in == NULL) {
67260 + dev_err(&pdev->dev, "failed to find video source\n");
67261 + return -EPROBE_DEFER;
67262 + }
67263 + ddata->in = in;
67264 +
67265 + r = of_property_read_u32(node, "data-lines", &datalines);
67266 + if (r) {
67267 + dev_err(&pdev->dev, "failed to parse datalines\n");
67268 + return r;
67269 + }
67270 +
67271 + ddata->data_lines = datalines;
67272 +
67273 + gpio = of_get_gpio(node, 0);
67274 + if (gpio_is_valid(gpio) || gpio == -ENOENT) {
67275 + ddata->enable_gpio = gpio;
67276 + } else {
67277 + dev_err(&pdev->dev, "failed to parse enable gpio\n");
67278 + return gpio;
67279 + }
67280 +
67281 + gpio = of_get_gpio_flags(node, 1, &gpio_flags);
67282 +
67283 + if (gpio_is_valid(gpio) || gpio == -ENOENT) {
67284 + ddata->backlight_gpio = gpio;
67285 + } else {
67286 + dev_err(&pdev->dev, "failed to parse backlight gpio\n");
67287 + return gpio;
67288 + }
67289 +
67290 + if (gpio_flags == OF_GPIO_ACTIVE_LOW)
67291 + ddata->backlight_enable = 0;
67292 + else
67293 + ddata->backlight_enable = 1;
67294 +
67295 + r = of_get_display_timing(node, "panel-timing", &timing);
67296 + if (r) {
67297 + dev_err(&pdev->dev, "failed to get video timing\n");
67298 + return r;
67299 + }
67300 +
67301 + videomode_from_timing(&timing, &vm);
67302 + videomode_to_omap_video_timings(&vm, &ddata->videomode);
67303 +
67304 + return 0;
67305 +}
67306 +
67307 static int panel_dpi_probe(struct platform_device *pdev)
67308 {
67309 struct panel_drv_data *ddata;
67310 @@ -198,6 +269,10 @@ static int panel_dpi_probe(struct platfo
67311 r = panel_dpi_probe_pdata(pdev);
67312 if (r)
67313 return r;
67314 + } else if (pdev->dev.of_node) {
67315 + r = panel_dpi_probe_of(pdev);
67316 + if (r)
67317 + return r;
67318 } else {
67319 return -ENODEV;
67320 }
67321 @@ -254,12 +329,20 @@ static int __exit panel_dpi_remove(struc
67322 return 0;
67323 }
67324
67325 +static const struct of_device_id panel_dpi_of_match[] = {
67326 + { .compatible = "panel-dpi", },
67327 + {},
67328 +};
67329 +
67330 +MODULE_DEVICE_TABLE(of, panel_dpi_of_match);
67331 +
67332 static struct platform_driver panel_dpi_driver = {
67333 .probe = panel_dpi_probe,
67334 .remove = __exit_p(panel_dpi_remove),
67335 .driver = {
67336 .name = "panel-dpi",
67337 .owner = THIS_MODULE,
67338 + .of_match_table = panel_dpi_of_match,
67339 },
67340 };
67341
67342 --- a/drivers/video/omap2/displays-new/panel-dsi-cm.c
67343 +++ b/drivers/video/omap2/displays-new/panel-dsi-cm.c
67344 @@ -22,6 +22,8 @@
67345 #include <linux/sched.h>
67346 #include <linux/slab.h>
67347 #include <linux/workqueue.h>
67348 +#include <linux/of_device.h>
67349 +#include <linux/of_gpio.h>
67350
67351 #include <video/omapdss.h>
67352 #include <video/omap-panel-data.h>
67353 @@ -1156,6 +1158,79 @@ static int dsicm_probe_pdata(struct plat
67354 return 0;
67355 }
67356
67357 +static int dsicm_probe_of(struct platform_device *pdev)
67358 +{
67359 + struct device_node *node = pdev->dev.of_node;
67360 + struct panel_drv_data *ddata = platform_get_drvdata(pdev);
67361 + struct omap_dss_device *in;
67362 + struct property *prop;
67363 + struct device_node *src_node;
67364 + u32 lane_arr[10];
67365 + int gpio, len, num_pins;
67366 + int r, i;
67367 +
67368 + src_node = of_parse_phandle(node, "video-source", 0);
67369 + if (!src_node) {
67370 + dev_err(&pdev->dev, "failed to parse video source\n");
67371 + return -ENODEV;
67372 + }
67373 +
67374 + in = omap_dss_find_output_by_node(src_node);
67375 + if (in == NULL) {
67376 + dev_err(&pdev->dev, "failed to find video source\n");
67377 + return -EPROBE_DEFER;
67378 + }
67379 + ddata->in = in;
67380 +
67381 + gpio = of_get_gpio(node, 0);
67382 + if (!gpio_is_valid(gpio)) {
67383 + dev_err(&pdev->dev, "failed to parse reset gpio\n");
67384 + return gpio;
67385 + }
67386 + ddata->reset_gpio = gpio;
67387 +
67388 + if (of_gpio_count(node) > 1) {
67389 + gpio = of_get_gpio(node, 1);
67390 +
67391 + if (gpio_is_valid(gpio) || gpio == -ENOENT) {
67392 + ddata->ext_te_gpio = gpio;
67393 + } else {
67394 + dev_err(&pdev->dev, "failed to parse TE gpio\n");
67395 + return gpio;
67396 + }
67397 + } else {
67398 + ddata->ext_te_gpio = -1;
67399 + }
67400 +
67401 + prop = of_find_property(node, "lanes", &len);
67402 + if (prop == NULL) {
67403 + dev_err(&pdev->dev, "failed to find lane data\n");
67404 + return -EINVAL;
67405 + }
67406 +
67407 + num_pins = len / sizeof(u32);
67408 +
67409 + if (num_pins < 4 || num_pins % 2 != 0
67410 + || num_pins > ARRAY_SIZE(lane_arr)) {
67411 + dev_err(&pdev->dev, "bad number of lanes\n");
67412 + return -EINVAL;
67413 + }
67414 +
67415 + r = of_property_read_u32_array(node, "lanes", lane_arr, num_pins);
67416 + if (r) {
67417 + dev_err(&pdev->dev, "failed to read lane data\n");
67418 + return r;
67419 + }
67420 +
67421 + ddata->pin_config.num_pins = num_pins;
67422 + for (i = 0; i < num_pins; ++i)
67423 + ddata->pin_config.pins[i] = (int)lane_arr[i];
67424 +
67425 + /* TODO: ulps, backlight */
67426 +
67427 + return 0;
67428 +}
67429 +
67430 static int dsicm_probe(struct platform_device *pdev)
67431 {
67432 struct backlight_properties props;
67433 @@ -1178,6 +1253,10 @@ static int dsicm_probe(struct platform_d
67434 r = dsicm_probe_pdata(pdev);
67435 if (r)
67436 return r;
67437 + } else if (pdev->dev.of_node) {
67438 + r = dsicm_probe_of(pdev);
67439 + if (r)
67440 + return r;
67441 } else {
67442 return -ENODEV;
67443 }
67444 @@ -1320,12 +1399,20 @@ static int __exit dsicm_remove(struct pl
67445 return 0;
67446 }
67447
67448 +static const struct of_device_id dsicm_of_match[] = {
67449 + { .compatible = "panel-dsi-cm", },
67450 + {},
67451 +};
67452 +
67453 +MODULE_DEVICE_TABLE(of, dsicm_of_match);
67454 +
67455 static struct platform_driver dsicm_driver = {
67456 .probe = dsicm_probe,
67457 .remove = __exit_p(dsicm_remove),
67458 .driver = {
67459 .name = "panel-dsi-cm",
67460 .owner = THIS_MODULE,
67461 + .of_match_table = dsicm_of_match,
67462 },
67463 };
67464
67465 --- /dev/null
67466 +++ b/drivers/video/omap2/displays-new/panel-tfcs9700.c
67467 @@ -0,0 +1,387 @@
67468 +/*
67469 + * TLC59108 TFC-S9700 Panel Driver
67470 + *
67471 + * Copyright (C) 2013 Texas Instruments
67472 + * Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
67473 + *
67474 + * This program is free software; you can redistribute it and/or modify it
67475 + * under the terms of the GNU General Public License version 2 as published by
67476 + * the Free Software Foundation.
67477 + */
67478 +
67479 +#include <linux/gpio.h>
67480 +#include <linux/module.h>
67481 +#include <linux/platform_device.h>
67482 +#include <linux/slab.h>
67483 +#include <linux/of.h>
67484 +#include <linux/of_gpio.h>
67485 +#include <linux/i2c.h>
67486 +#include <linux/regmap.h>
67487 +#include <linux/delay.h>
67488 +
67489 +#include <video/omapdss.h>
67490 +#include <video/omap-panel-data.h>
67491 +#include <video/of_display_timing.h>
67492 +
67493 +#define TLC_NAME "tlc59108"
67494 +#define TLC_I2C_ADDR 0x40
67495 +
67496 +#define TLC59108_MODE1 0x00
67497 +#define TLC59108_PWM2 0x04
67498 +#define TLC59108_LEDOUT0 0x0c
67499 +#define TLC59108_LEDOUT1 0x0d
67500 +
67501 +struct panel_drv_data {
67502 + struct omap_dss_device dssdev;
67503 + struct omap_dss_device *in;
67504 +
67505 + int data_lines;
67506 + struct omap_video_timings videomode;
67507 +
67508 + int enable_gpio;
67509 + struct regmap *regmap;
67510 +};
67511 +
67512 +static const struct omap_video_timings tfc_s9700_timings = {
67513 + .x_res = 800,
67514 + .y_res = 480,
67515 +
67516 + .pixel_clock = 29232,
67517 +
67518 + .hfp = 41,
67519 + .hsw = 49,
67520 + .hbp = 41,
67521 +
67522 + .vfp = 13,
67523 + .vsw = 4,
67524 + .vbp = 29,
67525 +
67526 + .vsync_level = OMAPDSS_SIG_ACTIVE_LOW,
67527 + .hsync_level = OMAPDSS_SIG_ACTIVE_LOW,
67528 + .data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE,
67529 + .de_level = OMAPDSS_SIG_ACTIVE_HIGH,
67530 + .sync_pclk_edge = OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES,
67531 +};
67532 +
67533 +static int tlc_init(struct panel_drv_data *ddata)
67534 +{
67535 + struct regmap *map = ddata->regmap;
67536 +
67537 + /* init the TLC chip */
67538 + regmap_write(map, TLC59108_MODE1, 0x01);
67539 +
67540 + /*
67541 + * set LED1(AVDD) to ON state(default), enable LED2 in PWM mode, enable
67542 + * LED0 to OFF state
67543 + */
67544 + regmap_write(map, TLC59108_LEDOUT0, 0x21);
67545 +
67546 + /* set LED2 PWM to full freq */
67547 + regmap_write(map, TLC59108_PWM2, 0xff);
67548 +
67549 + /* set LED4(UPDN) and LED6(MODE3) to OFF state */
67550 + regmap_write(map, TLC59108_LEDOUT1, 0x11);
67551 +
67552 + return 0;
67553 +}
67554 +
67555 +static int tlc_uninit(struct panel_drv_data *ddata)
67556 +{
67557 + struct regmap *map = ddata->regmap;
67558 +
67559 + /* clear TLC chip regs */
67560 + regmap_write(map, TLC59108_PWM2, 0x0);
67561 + regmap_write(map, TLC59108_LEDOUT0, 0x0);
67562 + regmap_write(map, TLC59108_LEDOUT1, 0x0);
67563 +
67564 + regmap_write(map, TLC59108_MODE1, 0x0);
67565 +
67566 + return 0;
67567 +}
67568 +
67569 +#define to_panel_data(p) container_of(p, struct panel_drv_data, dssdev)
67570 +
67571 +static int panel_dpi_connect(struct omap_dss_device *dssdev)
67572 +{
67573 + struct panel_drv_data *ddata = to_panel_data(dssdev);
67574 + struct omap_dss_device *in = ddata->in;
67575 + int r;
67576 +
67577 + if (omapdss_device_is_connected(dssdev))
67578 + return 0;
67579 +
67580 + r = in->ops.dpi->connect(in, dssdev);
67581 + if (r)
67582 + return r;
67583 +
67584 + return 0;
67585 +}
67586 +
67587 +static void panel_dpi_disconnect(struct omap_dss_device *dssdev)
67588 +{
67589 + struct panel_drv_data *ddata = to_panel_data(dssdev);
67590 + struct omap_dss_device *in = ddata->in;
67591 +
67592 + if (!omapdss_device_is_connected(dssdev))
67593 + return;
67594 +
67595 + in->ops.dpi->disconnect(in, dssdev);
67596 +}
67597 +
67598 +static int panel_dpi_enable(struct omap_dss_device *dssdev)
67599 +{
67600 + struct panel_drv_data *ddata = to_panel_data(dssdev);
67601 + struct omap_dss_device *in = ddata->in;
67602 + int r;
67603 +
67604 + if (!omapdss_device_is_connected(dssdev))
67605 + return -ENODEV;
67606 +
67607 + if (omapdss_device_is_enabled(dssdev))
67608 + return 0;
67609 +
67610 + in->ops.dpi->set_data_lines(in, ddata->data_lines);
67611 + in->ops.dpi->set_timings(in, &ddata->videomode);
67612 +
67613 + r = in->ops.dpi->enable(in);
67614 + if (r)
67615 + return r;
67616 +
67617 + tlc_init(ddata);
67618 +
67619 + dssdev->state = OMAP_DSS_DISPLAY_ACTIVE;
67620 +
67621 + return 0;
67622 +}
67623 +
67624 +static void panel_dpi_disable(struct omap_dss_device *dssdev)
67625 +{
67626 + struct panel_drv_data *ddata = to_panel_data(dssdev);
67627 + struct omap_dss_device *in = ddata->in;
67628 +
67629 + if (!omapdss_device_is_enabled(dssdev))
67630 + return;
67631 +
67632 + tlc_uninit(ddata);
67633 +
67634 + in->ops.dpi->disable(in);
67635 +
67636 + dssdev->state = OMAP_DSS_DISPLAY_DISABLED;
67637 +}
67638 +
67639 +static void panel_dpi_set_timings(struct omap_dss_device *dssdev,
67640 + struct omap_video_timings *timings)
67641 +{
67642 + struct panel_drv_data *ddata = to_panel_data(dssdev);
67643 + struct omap_dss_device *in = ddata->in;
67644 +
67645 + ddata->videomode = *timings;
67646 + dssdev->panel.timings = *timings;
67647 +
67648 + in->ops.dpi->set_timings(in, timings);
67649 +}
67650 +
67651 +static void panel_dpi_get_timings(struct omap_dss_device *dssdev,
67652 + struct omap_video_timings *timings)
67653 +{
67654 + struct panel_drv_data *ddata = to_panel_data(dssdev);
67655 +
67656 + *timings = ddata->videomode;
67657 +}
67658 +
67659 +static int panel_dpi_check_timings(struct omap_dss_device *dssdev,
67660 + struct omap_video_timings *timings)
67661 +{
67662 + struct panel_drv_data *ddata = to_panel_data(dssdev);
67663 + struct omap_dss_device *in = ddata->in;
67664 +
67665 + return in->ops.dpi->check_timings(in, timings);
67666 +}
67667 +
67668 +static struct omap_dss_driver panel_dpi_ops = {
67669 + .connect = panel_dpi_connect,
67670 + .disconnect = panel_dpi_disconnect,
67671 +
67672 + .enable = panel_dpi_enable,
67673 + .disable = panel_dpi_disable,
67674 +
67675 + .set_timings = panel_dpi_set_timings,
67676 + .get_timings = panel_dpi_get_timings,
67677 + .check_timings = panel_dpi_check_timings,
67678 +
67679 + .get_resolution = omapdss_default_get_resolution,
67680 +};
67681 +
67682 +static int tlc_probe_of(struct device *dev)
67683 +{
67684 + struct panel_drv_data *ddata = dev_get_drvdata(dev);
67685 + struct device_node *node = dev->of_node;
67686 + struct omap_dss_device *in;
67687 + struct device_node *src_node;
67688 + int r, datalines;
67689 + int gpio;
67690 +
67691 + src_node = of_parse_phandle(node, "video-source", 0);
67692 + if (!src_node) {
67693 + dev_err(dev, "failed to parse video source\n");
67694 + return -ENODEV;
67695 + }
67696 +
67697 + in = omap_dss_find_output_by_node(src_node);
67698 + if (in == NULL) {
67699 + dev_err(dev, "failed to find video source\n");
67700 + return -EPROBE_DEFER;
67701 + }
67702 +
67703 + ddata->in = in;
67704 +
67705 + r = of_property_read_u32(node, "data-lines", &datalines);
67706 + if (r) {
67707 + dev_err(dev, "failed to parse datalines\n");
67708 + return r;
67709 + }
67710 +
67711 + ddata->data_lines = datalines;
67712 +
67713 + gpio = of_get_gpio(node, 0);
67714 + if (gpio_is_valid(gpio) || gpio == -ENOENT) {
67715 + ddata->enable_gpio = gpio;
67716 + } else {
67717 + dev_err(dev, "failed to parse enable gpio\n");
67718 + return gpio;
67719 + }
67720 +
67721 + return 0;
67722 +}
67723 +
67724 +struct regmap_config tlc59108_regmap_config = {
67725 + .reg_bits = 8,
67726 + .val_bits = 8,
67727 +};
67728 +
67729 +static int tlc59108_i2c_probe(struct i2c_client *client,
67730 + const struct i2c_device_id *id)
67731 +{
67732 + int r;
67733 + struct regmap *regmap;
67734 + struct panel_drv_data *ddata;
67735 + struct device *dev = &client->dev;
67736 + struct omap_dss_device *dssdev;
67737 + unsigned int val;
67738 +
67739 + ddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL);
67740 + if (ddata == NULL)
67741 + return -ENOMEM;
67742 +
67743 + dev_set_drvdata(dev, ddata);
67744 +
67745 + r = tlc_probe_of(dev);
67746 + if (r)
67747 + return r;
67748 +
67749 + ddata->videomode = tfc_s9700_timings;
67750 +
67751 + if (gpio_is_valid(ddata->enable_gpio)) {
67752 + r = devm_gpio_request_one(dev, ddata->enable_gpio,
67753 + GPIOF_OUT_INIT_LOW, "panel enable");
67754 + if (r)
67755 + goto err_gpio;
67756 + }
67757 +
67758 + regmap = devm_regmap_init_i2c(client, &tlc59108_regmap_config);
67759 + if (IS_ERR(regmap)) {
67760 + r = PTR_ERR(regmap);
67761 + dev_err(dev, "Failed to init regmap: %d\n", r);
67762 + goto err_gpio;
67763 + }
67764 +
67765 + ddata->regmap = regmap;
67766 +
67767 + msleep(10);
67768 +
67769 + /* Try to read a TLC register to verify if i2c works */
67770 + r = regmap_read(ddata->regmap, TLC59108_MODE1, &val);
67771 + if (r < 0) {
67772 + dev_err(dev, "Failed to set MODE1: %d\n", r);
67773 + return r;
67774 + }
67775 +
67776 + dssdev = &ddata->dssdev;
67777 + dssdev->dev = dev;
67778 + dssdev->driver = &panel_dpi_ops;
67779 + dssdev->type = OMAP_DISPLAY_TYPE_DPI;
67780 + dssdev->owner = THIS_MODULE;
67781 + dssdev->panel.timings = ddata->videomode;
67782 + dssdev->phy.dpi.data_lines = ddata->data_lines;
67783 +
67784 + r = omapdss_register_display(dssdev);
67785 + if (r) {
67786 + dev_err(dev, "Failed to register panel\n");
67787 + goto err_reg;
67788 + }
67789 +
67790 + dev_info(dev, "Successfully initialized %s\n", TLC_NAME);
67791 +
67792 + return 0;
67793 +err_reg:
67794 +err_gpio:
67795 + omap_dss_put_device(ddata->in);
67796 + return r;
67797 +}
67798 +
67799 +static int tlc59108_i2c_remove(struct i2c_client *client)
67800 +{
67801 + struct panel_drv_data *ddata = dev_get_drvdata(&client->dev);
67802 + struct omap_dss_device *dssdev = &ddata->dssdev;
67803 + struct omap_dss_device *in = ddata->in;
67804 +
67805 + if (gpio_is_valid(ddata->enable_gpio))
67806 + gpio_set_value_cansleep(ddata->enable_gpio, 1);
67807 +
67808 + omapdss_unregister_display(dssdev);
67809 +
67810 + panel_dpi_disable(dssdev);
67811 + panel_dpi_disconnect(dssdev);
67812 +
67813 + omap_dss_put_device(in);
67814 +
67815 + return 0;
67816 +}
67817 +
67818 +static const struct i2c_device_id tlc59108_id[] = {
67819 + { TLC_NAME, 0 },
67820 + { }
67821 +};
67822 +MODULE_DEVICE_TABLE(i2c, tlc59108_id);
67823 +
67824 +static const struct of_device_id tlc59108_of_match[] = {
67825 + { .compatible = "ti,tlc59108", },
67826 + { },
67827 +};
67828 +MODULE_DEVICE_TABLE(of, tlc59108_of_match);
67829 +
67830 +static struct i2c_driver tlc59108_i2c_driver = {
67831 + .driver = {
67832 + .owner = THIS_MODULE,
67833 + .name = TLC_NAME,
67834 + .of_match_table = tlc59108_of_match,
67835 + },
67836 + .id_table = tlc59108_id,
67837 + .probe = tlc59108_i2c_probe,
67838 + .remove = tlc59108_i2c_remove,
67839 +};
67840 +
67841 +static int __init tfc_s9700_init(void)
67842 +{
67843 + return i2c_add_driver(&tlc59108_i2c_driver);
67844 +}
67845 +
67846 +static void __exit tfc_s9700_exit(void)
67847 +{
67848 +}
67849 +module_init(tfc_s9700_init);
67850 +module_exit(tfc_s9700_exit);
67851 +
67852 +MODULE_AUTHOR("Archit Taneja <archit@ti.com>");
67853 +MODULE_DESCRIPTION("TFC-S9700 DPI Panel Driver");
67854 +MODULE_LICENSE("GPL");
67855 --- a/drivers/video/omap2/dss/core.c
67856 +++ b/drivers/video/omap2/dss/core.c
67857 @@ -256,6 +256,9 @@ static int (*dss_output_drv_reg_funcs[])
67858 #ifdef CONFIG_OMAP2_DSS_DPI
67859 dpi_init_platform_driver,
67860 #endif
67861 +#ifdef CONFIG_OMAP2_DSS_DRA7XX_DPI
67862 + dra7xx_dpi_init_platform_driver,
67863 +#endif
67864 #ifdef CONFIG_OMAP2_DSS_SDI
67865 sdi_init_platform_driver,
67866 #endif
67867 @@ -266,7 +269,10 @@ static int (*dss_output_drv_reg_funcs[])
67868 venc_init_platform_driver,
67869 #endif
67870 #ifdef CONFIG_OMAP4_DSS_HDMI
67871 - hdmi_init_platform_driver,
67872 + hdmi4_init_platform_driver,
67873 +#endif
67874 +#ifdef CONFIG_OMAP5_DSS_HDMI
67875 + hdmi5_init_platform_driver,
67876 #endif
67877 };
67878
67879 @@ -277,6 +283,9 @@ static void (*dss_output_drv_unreg_funcs
67880 #ifdef CONFIG_OMAP2_DSS_DPI
67881 dpi_uninit_platform_driver,
67882 #endif
67883 +#ifdef CONFIG_OMAP2_DSS_DRA7XX_DPI
67884 + dra7xx_dpi_uninit_platform_driver,
67885 +#endif
67886 #ifdef CONFIG_OMAP2_DSS_SDI
67887 sdi_uninit_platform_driver,
67888 #endif
67889 @@ -287,7 +296,10 @@ static void (*dss_output_drv_unreg_funcs
67890 venc_uninit_platform_driver,
67891 #endif
67892 #ifdef CONFIG_OMAP4_DSS_HDMI
67893 - hdmi_uninit_platform_driver,
67894 + hdmi4_uninit_platform_driver,
67895 +#endif
67896 +#ifdef CONFIG_OMAP5_DSS_HDMI
67897 + hdmi5_uninit_platform_driver,
67898 #endif
67899 };
67900
67901 --- a/drivers/video/omap2/dss/dispc.c
67902 +++ b/drivers/video/omap2/dss/dispc.c
67903 @@ -3622,6 +3622,7 @@ static int __init dispc_init_features(st
67904 case OMAPDSS_VER_OMAP34xx_ES3:
67905 case OMAPDSS_VER_OMAP3630:
67906 case OMAPDSS_VER_AM35xx:
67907 + case OMAPDSS_VER_AM43xx:
67908 src = &omap34xx_rev3_0_dispc_feats;
67909 break;
67910
67911 @@ -3632,6 +3633,7 @@ static int __init dispc_init_features(st
67912 break;
67913
67914 case OMAPDSS_VER_OMAP5:
67915 + case OMAPDSS_VER_DRA7xx:
67916 src = &omap54xx_dispc_feats;
67917 break;
67918
67919 @@ -3691,7 +3693,6 @@ static int __init omap_dispchw_probe(str
67920 }
67921
67922 pm_runtime_enable(&pdev->dev);
67923 - pm_runtime_irq_safe(&pdev->dev);
67924
67925 r = dispc_runtime_get();
67926 if (r)
67927 @@ -3744,12 +3745,19 @@ static const struct dev_pm_ops dispc_pm_
67928 .runtime_resume = dispc_runtime_resume,
67929 };
67930
67931 +static const struct of_device_id dispc_of_match[] = {
67932 + { .compatible = "ti,omap3-dispc", },
67933 + { .compatible = "ti,omap4-dispc", },
67934 + {},
67935 +};
67936 +
67937 static struct platform_driver omap_dispchw_driver = {
67938 .remove = __exit_p(omap_dispchw_remove),
67939 .driver = {
67940 .name = "omapdss_dispc",
67941 .owner = THIS_MODULE,
67942 .pm = &dispc_pm_ops,
67943 + .of_match_table = dispc_of_match,
67944 },
67945 };
67946
67947 --- a/drivers/video/omap2/dss/display.c
67948 +++ b/drivers/video/omap2/dss/display.c
67949 @@ -26,6 +26,7 @@
67950 #include <linux/module.h>
67951 #include <linux/jiffies.h>
67952 #include <linux/platform_device.h>
67953 +#include <linux/of.h>
67954
67955 #include <video/omapdss.h>
67956 #include "dss.h"
67957 @@ -133,9 +134,27 @@ static int disp_num_counter;
67958 int omapdss_register_display(struct omap_dss_device *dssdev)
67959 {
67960 struct omap_dss_driver *drv = dssdev->driver;
67961 + int id;
67962
67963 - snprintf(dssdev->alias, sizeof(dssdev->alias),
67964 - "display%d", disp_num_counter++);
67965 + /*
67966 + * Note: this presumes all the displays are either using DT or non-DT,
67967 + * which normally should be the case. This also presumes that all
67968 + * displays either have an DT alias, or none has.
67969 + */
67970 +
67971 + if (dssdev->dev->of_node) {
67972 + id = of_alias_get_id(dssdev->dev->of_node, "display");
67973 +
67974 + if (id < 0)
67975 + id = disp_num_counter++;
67976 + } else {
67977 + id = disp_num_counter++;
67978 + }
67979 +
67980 + snprintf(dssdev->alias, sizeof(dssdev->alias), "display%d", id);
67981 +
67982 + if (dssdev->name == NULL)
67983 + dssdev->name = dssdev->alias;
67984
67985 if (drv && drv->get_resolution == NULL)
67986 drv->get_resolution = omapdss_default_get_resolution;
67987 --- a/drivers/video/omap2/dss/display-sysfs.c
67988 +++ b/drivers/video/omap2/dss/display-sysfs.c
67989 @@ -277,7 +277,7 @@ static ssize_t display_wss_store(struct
67990 return size;
67991 }
67992
67993 -static DEVICE_ATTR(name, S_IRUGO, display_name_show, NULL);
67994 +static DEVICE_ATTR(disp_name, S_IRUGO, display_name_show, NULL);
67995 static DEVICE_ATTR(enabled, S_IRUGO|S_IWUSR,
67996 display_enabled_show, display_enabled_store);
67997 static DEVICE_ATTR(tear_elim, S_IRUGO|S_IWUSR,
67998 @@ -292,7 +292,7 @@ static DEVICE_ATTR(wss, S_IRUGO|S_IWUSR,
67999 display_wss_show, display_wss_store);
68000
68001 static const struct attribute *display_sysfs_attrs[] = {
68002 - &dev_attr_name.attr,
68003 + &dev_attr_disp_name.attr,
68004 &dev_attr_enabled.attr,
68005 &dev_attr_tear_elim.attr,
68006 &dev_attr_timings.attr,
68007 --- a/drivers/video/omap2/dss/dpi.c
68008 +++ b/drivers/video/omap2/dss/dpi.c
68009 @@ -30,6 +30,7 @@
68010 #include <linux/platform_device.h>
68011 #include <linux/regulator/consumer.h>
68012 #include <linux/string.h>
68013 +#include <linux/of.h>
68014
68015 #include <video/omapdss.h>
68016
68017 @@ -64,6 +65,7 @@ static struct platform_device *dpi_get_d
68018 case OMAPDSS_VER_OMAP34xx_ES3:
68019 case OMAPDSS_VER_OMAP3630:
68020 case OMAPDSS_VER_AM35xx:
68021 + case OMAPDSS_VER_AM43xx:
68022 return NULL;
68023
68024 case OMAPDSS_VER_OMAP4430_ES1:
68025 @@ -374,7 +376,7 @@ static int dpi_display_enable(struct oma
68026 if (r)
68027 goto err_get_dispc;
68028
68029 - r = dss_dpi_select_source(out->manager->id);
68030 + r = dss_dpi_select_source(0, out->manager->id);
68031 if (r)
68032 goto err_src_sel;
68033
68034 @@ -593,6 +595,7 @@ static enum omap_channel dpi_get_channel
68035 case OMAPDSS_VER_OMAP34xx_ES3:
68036 case OMAPDSS_VER_OMAP3630:
68037 case OMAPDSS_VER_AM35xx:
68038 + case OMAPDSS_VER_AM43xx:
68039 return OMAP_DSS_CHANNEL_LCD;
68040
68041 case OMAPDSS_VER_OMAP4430_ES1:
68042 @@ -708,12 +711,19 @@ static int __exit omap_dpi_remove(struct
68043 return 0;
68044 }
68045
68046 +static const struct of_device_id dpi_of_match[] = {
68047 + { .compatible = "ti,omap3-dpi", },
68048 + { .compatible = "ti,omap4-dpi", },
68049 + {},
68050 +};
68051 +
68052 static struct platform_driver omap_dpi_driver = {
68053 .probe = omap_dpi_probe,
68054 .remove = __exit_p(omap_dpi_remove),
68055 .driver = {
68056 .name = "omapdss_dpi",
68057 .owner = THIS_MODULE,
68058 + .of_match_table = dpi_of_match,
68059 },
68060 };
68061
68062 --- /dev/null
68063 +++ b/drivers/video/omap2/dss/dra7xx_dpi.c
68064 @@ -0,0 +1,632 @@
68065 +/*
68066 + * Some code and ideas taken from drivers/video/omap/ driver
68067 + * by Imre Deak.
68068 + *
68069 + * This program is free software; you can redistribute it and/or modify it
68070 + * under the terms of the GNU General Public License version 2 as published by
68071 + * the Free Software Foundation.
68072 + *
68073 + * This program is distributed in the hope that it will be useful, but WITHOUT
68074 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
68075 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
68076 + * more details.
68077 + *
68078 + * You should have received a copy of the GNU General Public License along with
68079 + * this program. If not, see <http://www.gnu.org/licenses/>.
68080 + */
68081 +
68082 +#define DSS_SUBSYS_NAME "DRA7XX_DPI"
68083 +
68084 +#include <linux/kernel.h>
68085 +#include <linux/delay.h>
68086 +#include <linux/export.h>
68087 +#include <linux/err.h>
68088 +#include <linux/errno.h>
68089 +#include <linux/platform_device.h>
68090 +#include <linux/regulator/consumer.h>
68091 +#include <linux/string.h>
68092 +#include <linux/slab.h>
68093 +#include <linux/of.h>
68094 +
68095 +#include <video/omapdss.h>
68096 +
68097 +#include "dss.h"
68098 +#include "dss_features.h"
68099 +
68100 +struct dpi_data {
68101 + enum dss_dpll dpll;
68102 +
68103 + struct mutex lock;
68104 +
68105 + u32 module_id;
68106 + enum omap_channel channel;
68107 +
68108 + struct omap_video_timings timings;
68109 + struct dss_lcd_mgr_config mgr_config;
68110 + int data_lines;
68111 +
68112 + struct omap_dss_device output;
68113 +};
68114 +
68115 +/*
68116 + * On DRA7xx, we will try to use the DPLL_VIDEOx PLLs, only if we can't get one,
68117 + * we will try to modify the DSS_FCLK to get the pixel clock. Leave HDMI PLL out
68118 + * for now
68119 + */
68120 +enum dss_dpll dpi_get_dpll(struct dpi_data *dpi)
68121 +{
68122 + switch (dpi->module_id) {
68123 + case 0:
68124 + if (dss_dpll_disabled(DSS_DPLL_VIDEO1))
68125 + return DSS_DPLL_VIDEO1;
68126 + else
68127 + return DSS_DPLL_NONE;
68128 + case 1:
68129 + case 2:
68130 + if (dss_dpll_disabled(DSS_DPLL_VIDEO1))
68131 + return DSS_DPLL_VIDEO1;
68132 + else if (dss_dpll_disabled(DSS_DPLL_VIDEO2))
68133 + return DSS_DPLL_VIDEO2;
68134 + else
68135 + return DSS_DPLL_NONE;
68136 + default:
68137 + return DSS_DPLL_NONE;
68138 + }
68139 +
68140 + return DSS_DPLL_NONE;
68141 +}
68142 +
68143 +struct dpi_clk_calc_ctx {
68144 + enum dss_dpll dpll;
68145 +
68146 + /* inputs */
68147 + unsigned long pck_min, pck_max;
68148 +
68149 + /* outputs */
68150 + struct dss_dpll_cinfo dpll_cinfo;
68151 + struct dss_clock_info dss_cinfo;
68152 + struct dispc_clock_info dispc_cinfo;
68153 +};
68154 +
68155 +static bool dpi_calc_dispc_cb(int lckd, int pckd, unsigned long lck,
68156 + unsigned long pck, void *data)
68157 +{
68158 + struct dpi_clk_calc_ctx *ctx = data;
68159 +
68160 + /*
68161 + * Odd dividers give us uneven duty cycle, causing problem when level
68162 + * shifted. So skip all odd dividers when the pixel clock is on the
68163 + * higher side.
68164 + */
68165 + if (ctx->pck_min >= 100000000) {
68166 + if (lckd > 1 && lckd % 2 != 0)
68167 + return false;
68168 +
68169 + if (pckd > 1 && pckd % 2 != 0)
68170 + return false;
68171 + }
68172 +
68173 + ctx->dispc_cinfo.lck_div = lckd;
68174 + ctx->dispc_cinfo.pck_div = pckd;
68175 + ctx->dispc_cinfo.lck = lck;
68176 + ctx->dispc_cinfo.pck = pck;
68177 +
68178 + return true;
68179 +}
68180 +
68181 +static bool dpi_calc_hsdiv_cb(int regm_hsdiv, unsigned long dispc,
68182 + void *data)
68183 +{
68184 + struct dpi_clk_calc_ctx *ctx = data;
68185 +
68186 + /*
68187 + * Odd dividers give us uneven duty cycle, causing problem when level
68188 + * shifted. So skip all odd dividers when the pixel clock is on the
68189 + * higher side.
68190 + */
68191 + if (regm_hsdiv > 1 && regm_hsdiv % 2 != 0 && ctx->pck_min >= 100000000)
68192 + return false;
68193 +
68194 + ctx->dpll_cinfo.regm_hsdiv = regm_hsdiv;
68195 + ctx->dpll_cinfo.hsdiv_clk = dispc;
68196 +
68197 + return dispc_div_calc(dispc, ctx->pck_min, ctx->pck_max,
68198 + dpi_calc_dispc_cb, ctx);
68199 +}
68200 +
68201 +static bool dpi_calc_pll_cb(int regn, int regm, unsigned long fint,
68202 + unsigned long pll,
68203 + void *data)
68204 +{
68205 + struct dpi_clk_calc_ctx *ctx = data;
68206 +
68207 + ctx->dpll_cinfo.regn = regn;
68208 + ctx->dpll_cinfo.regm = regm;
68209 + ctx->dpll_cinfo.fint = fint;
68210 + ctx->dpll_cinfo.clkout = pll;
68211 +
68212 + return dss_dpll_hsdiv_calc(ctx->dpll, pll, ctx->pck_min,
68213 + dpi_calc_hsdiv_cb, ctx);
68214 +}
68215 +
68216 +static bool dpi_calc_dss_cb(int fckd, unsigned long fck, void *data)
68217 +{
68218 + struct dpi_clk_calc_ctx *ctx = data;
68219 +
68220 + ctx->dss_cinfo.fck = fck;
68221 + ctx->dss_cinfo.fck_div = fckd;
68222 +
68223 + return dispc_div_calc(fck, ctx->pck_min, ctx->pck_max,
68224 + dpi_calc_dispc_cb, ctx);
68225 +}
68226 +
68227 +
68228 +static bool dpi_dpll_clk_calc(enum dss_dpll dpll, unsigned long pck,
68229 + struct dpi_clk_calc_ctx *ctx)
68230 +{
68231 + unsigned long clkin;
68232 + unsigned long pll_min, pll_max;
68233 +
68234 + clkin = dpll_get_clkin(dpll);
68235 +
68236 + memset(ctx, 0, sizeof(*ctx));
68237 + ctx->dpll = dpll;
68238 + ctx->pck_min = pck - 1000;
68239 + ctx->pck_max = pck + 1000;
68240 + ctx->dpll_cinfo.clkin = clkin;
68241 +
68242 + pll_min = 0;
68243 + pll_max = 0;
68244 +
68245 + return dss_dpll_calc(dpll, clkin, pll_min, pll_max, dpi_calc_pll_cb,
68246 + ctx);
68247 +}
68248 +
68249 +static bool dpi_dss_clk_calc(unsigned long pck, struct dpi_clk_calc_ctx *ctx)
68250 +{
68251 + int i;
68252 +
68253 + /*
68254 + * DSS fck gives us very few possibilities, so finding a good pixel
68255 + * clock may not be possible. We try multiple times to find the clock,
68256 + * each time widening the pixel clock range we look for, up to
68257 + * +/- ~15MHz.
68258 + */
68259 +
68260 + for (i = 0; i < 25; ++i) {
68261 + bool ok;
68262 +
68263 + memset(ctx, 0, sizeof(*ctx));
68264 + if (pck > 1000 * i * i * i)
68265 + ctx->pck_min = max(pck - 1000 * i * i * i, 0lu);
68266 + else
68267 + ctx->pck_min = 0;
68268 + ctx->pck_max = pck + 1000 * i * i * i;
68269 +
68270 + ok = dss_div_calc(ctx->pck_min, dpi_calc_dss_cb, ctx);
68271 + if (ok)
68272 + return ok;
68273 + }
68274 +
68275 + return false;
68276 +}
68277 +
68278 +static int dpi_set_dss_dpll_clk(struct dpi_data *dpi, unsigned long pck_req,
68279 + unsigned long *fck, u16 *lck_div, u16 *pck_div)
68280 +{
68281 + struct dpi_clk_calc_ctx ctx;
68282 + int r;
68283 + bool ok;
68284 +
68285 + ok = dpi_dpll_clk_calc(dpi->dpll, pck_req, &ctx);
68286 + if (!ok)
68287 + return -EINVAL;
68288 +
68289 + r = dss_dpll_set_clock_div(dpi->dpll, &ctx.dpll_cinfo);
68290 + if (r)
68291 + return r;
68292 +
68293 + dss_use_dpll_lcd(dpi->output.dispc_channel, true);
68294 +
68295 + dpi->mgr_config.clock_info = ctx.dispc_cinfo;
68296 +
68297 + *fck = ctx.dpll_cinfo.hsdiv_clk;
68298 + *lck_div = ctx.dispc_cinfo.lck_div;
68299 + *pck_div = ctx.dispc_cinfo.pck_div;
68300 +
68301 + return 0;
68302 +}
68303 +
68304 +static int dpi_set_dispc_clk(struct dpi_data *dpi, unsigned long pck_req,
68305 + unsigned long *fck, u16 *lck_div, u16 *pck_div)
68306 +{
68307 + struct dpi_clk_calc_ctx ctx;
68308 + int r;
68309 + bool ok;
68310 +
68311 + ok = dpi_dss_clk_calc(pck_req, &ctx);
68312 + if (!ok)
68313 + return -EINVAL;
68314 +
68315 + r = dss_set_clock_div(&ctx.dss_cinfo);
68316 + if (r)
68317 + return r;
68318 +
68319 + dpi->mgr_config.clock_info = ctx.dispc_cinfo;
68320 +
68321 + *fck = ctx.dss_cinfo.fck;
68322 + *lck_div = ctx.dispc_cinfo.lck_div;
68323 + *pck_div = ctx.dispc_cinfo.pck_div;
68324 +
68325 + return 0;
68326 +}
68327 +
68328 +static int dpi_set_mode(struct dpi_data *dpi)
68329 +{
68330 + struct omap_overlay_manager *mgr = dpi->output.manager;
68331 + struct omap_video_timings *t = &dpi->timings;
68332 + u16 lck_div = 0, pck_div = 0;
68333 + unsigned long fck = 0;
68334 + unsigned long pck;
68335 + int r = 0;
68336 +
68337 + if (dpi->dpll != DSS_DPLL_NONE)
68338 + r = dpi_set_dss_dpll_clk(dpi, t->pixel_clock * 1000, &fck,
68339 + &lck_div, &pck_div);
68340 + else
68341 + r = dpi_set_dispc_clk(dpi, t->pixel_clock * 1000, &fck,
68342 + &lck_div, &pck_div);
68343 + if (r)
68344 + return r;
68345 +
68346 + pck = fck / lck_div / pck_div / 1000;
68347 +
68348 + if (pck != t->pixel_clock) {
68349 + DSSWARN("Could not find exact pixel clock. "
68350 + "Requested %d kHz, got %lu kHz\n",
68351 + t->pixel_clock, pck);
68352 +
68353 + t->pixel_clock = pck;
68354 + }
68355 +
68356 + dss_mgr_set_timings(mgr, t);
68357 +
68358 + return 0;
68359 +}
68360 +
68361 +static void dpi_config_lcd_manager(struct dpi_data *dpi)
68362 +{
68363 + struct omap_overlay_manager *mgr = dpi->output.manager;
68364 +
68365 + dpi->mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS;
68366 +
68367 + dpi->mgr_config.stallmode = false;
68368 + dpi->mgr_config.fifohandcheck = false;
68369 +
68370 + dpi->mgr_config.video_port_width = dpi->data_lines;
68371 +
68372 + dpi->mgr_config.lcden_sig_polarity = 0;
68373 +
68374 + dss_mgr_set_lcd_config(mgr, &dpi->mgr_config);
68375 +}
68376 +
68377 +static int dra7xx_dpi_display_enable(struct omap_dss_device *dssdev)
68378 +{
68379 + struct dpi_data *dpi = dev_get_drvdata(dssdev->dev);
68380 + struct omap_dss_device *out = &dpi->output;
68381 + int r;
68382 +
68383 + mutex_lock(&dpi->lock);
68384 +
68385 + if (out == NULL || out->manager == NULL) {
68386 + DSSERR("failed to enable display: no output/manager\n");
68387 + r = -ENODEV;
68388 + goto err_no_out_mgr;
68389 + }
68390 +
68391 + r = dispc_runtime_get();
68392 + if (r)
68393 + goto err_get_dispc;
68394 +
68395 + r = dss_dpi_select_source(dpi->module_id, out->dispc_channel);
68396 + if (r)
68397 + goto err_src_sel;
68398 +
68399 + if (dpi->dpll != DSS_DPLL_NONE) {
68400 + DSSDBG("using DPLL %d for DPI%d\n", dpi->dpll, dpi->module_id);
68401 + dss_dpll_activate(dpi->dpll);
68402 + dss_dpll_set_control_mux(out->dispc_channel, dpi->dpll);
68403 + }
68404 +
68405 + r = dpi_set_mode(dpi);
68406 + if (r)
68407 + goto err_set_mode;
68408 +
68409 +
68410 + dpi_config_lcd_manager(dpi);
68411 +
68412 + mdelay(2);
68413 +
68414 + r = dss_mgr_enable(out->manager);
68415 + if (r)
68416 + goto err_mgr_enable;
68417 +
68418 + mutex_unlock(&dpi->lock);
68419 +
68420 + return 0;
68421 +
68422 +err_mgr_enable:
68423 +err_set_mode:
68424 + if (dpi->dpll != DSS_DPLL_NONE)
68425 + dss_dpll_disable(dpi->dpll);
68426 +err_src_sel:
68427 + dispc_runtime_put();
68428 +err_get_dispc:
68429 +err_no_out_mgr:
68430 + mutex_unlock(&dpi->lock);
68431 + return r;
68432 +}
68433 +
68434 +static void dra7xx_dpi_display_disable(struct omap_dss_device *dssdev)
68435 +{
68436 + struct dpi_data *dpi = dev_get_drvdata(dssdev->dev);
68437 + struct omap_overlay_manager *mgr = dpi->output.manager;
68438 +
68439 + mutex_lock(&dpi->lock);
68440 +
68441 + dss_mgr_disable(mgr);
68442 +
68443 + if (dpi->dpll != DSS_DPLL_NONE) {
68444 + dss_use_dpll_lcd(dssdev->dispc_channel, false);
68445 + dss_dpll_disable(dpi->dpll);
68446 + }
68447 +
68448 + dispc_runtime_put();
68449 +
68450 + mutex_unlock(&dpi->lock);
68451 +}
68452 +
68453 +static void dra7xx_dpi_set_timings(struct omap_dss_device *dssdev,
68454 + struct omap_video_timings *timings)
68455 +{
68456 + struct dpi_data *dpi = dev_get_drvdata(dssdev->dev);
68457 +
68458 + DSSDBG("set_timings\n");
68459 +
68460 + mutex_lock(&dpi->lock);
68461 +
68462 + dpi->timings = *timings;
68463 +
68464 + mutex_unlock(&dpi->lock);
68465 +}
68466 +
68467 +static int dra7xx_dpi_check_timings(struct omap_dss_device *dssdev,
68468 + struct omap_video_timings *timings)
68469 +{
68470 + DSSDBG("check_timings\n");
68471 +
68472 + return 0;
68473 +}
68474 +
68475 +static void dra7xx_dpi_get_timings(struct omap_dss_device *dssdev,
68476 + struct omap_video_timings *timings)
68477 +{
68478 + struct dpi_data *dpi = dev_get_drvdata(dssdev->dev);
68479 +
68480 + DSSDBG("set_timings\n");
68481 +
68482 + mutex_lock(&dpi->lock);
68483 +
68484 + *timings = dpi->timings;
68485 +
68486 + mutex_unlock(&dpi->lock);
68487 +}
68488 +
68489 +static void dra7xx_dpi_set_data_lines(struct omap_dss_device *dssdev,
68490 + int data_lines)
68491 +{
68492 + struct dpi_data *dpi = dev_get_drvdata(dssdev->dev);
68493 +
68494 + mutex_lock(&dpi->lock);
68495 +
68496 + dpi->data_lines = data_lines;
68497 +
68498 + mutex_unlock(&dpi->lock);
68499 +}
68500 +
68501 +static int dra7xx_dpi_connect(struct omap_dss_device *dssdev,
68502 + struct omap_dss_device *dst)
68503 +{
68504 + struct dpi_data *dpi = dev_get_drvdata(dssdev->dev);
68505 + struct omap_overlay_manager *mgr;
68506 + int r;
68507 +
68508 + /* try to get a free dpll */
68509 + dpi->dpll = dpi_get_dpll(dpi);
68510 +
68511 + r = dss_dpll_init_regulator(dpi->dpll);
68512 + if (r)
68513 + return r;
68514 +
68515 + mgr = omap_dss_get_overlay_manager(dssdev->dispc_channel);
68516 + if (!mgr)
68517 + return -ENODEV;
68518 +
68519 + r = dss_mgr_connect(mgr, dssdev);
68520 + if (r)
68521 + return r;
68522 +
68523 + r = omapdss_output_set_device(dssdev, dst);
68524 + if (r) {
68525 + DSSERR("failed to connect output to new device: %s\n",
68526 + dst->name);
68527 + dss_mgr_disconnect(mgr, dssdev);
68528 + return r;
68529 + }
68530 +
68531 + return 0;
68532 +}
68533 +
68534 +static void dra7xx_dpi_disconnect(struct omap_dss_device *dssdev,
68535 + struct omap_dss_device *dst)
68536 +{
68537 + struct dpi_data *dpi = dev_get_drvdata(dssdev->dev);
68538 +
68539 + WARN_ON(dst != dssdev->dst);
68540 +
68541 + if (dst != dssdev->dst)
68542 + return;
68543 +
68544 + dpi->dpll = DSS_DPLL_NONE;
68545 +
68546 + omapdss_output_unset_device(dssdev);
68547 +
68548 + if (dssdev->manager)
68549 + dss_mgr_disconnect(dssdev->manager, dssdev);
68550 +}
68551 +
68552 +static const struct omapdss_dpi_ops dra7xx_dpi_ops = {
68553 + .connect = dra7xx_dpi_connect,
68554 + .disconnect = dra7xx_dpi_disconnect,
68555 +
68556 + .enable = dra7xx_dpi_display_enable,
68557 + .disable = dra7xx_dpi_display_disable,
68558 +
68559 + .check_timings = dra7xx_dpi_check_timings,
68560 + .set_timings = dra7xx_dpi_set_timings,
68561 + .get_timings = dra7xx_dpi_get_timings,
68562 +
68563 + .set_data_lines = dra7xx_dpi_set_data_lines,
68564 +};
68565 +
68566 +static enum omap_channel dra7xx_dpi_get_channel(struct dpi_data *dpi)
68567 +{
68568 + switch (dpi->module_id) {
68569 + case 0:
68570 + return dpi->channel;
68571 + case 1:
68572 + return OMAP_DSS_CHANNEL_LCD2;
68573 + case 2:
68574 + return OMAP_DSS_CHANNEL_LCD3;
68575 + default:
68576 + DSSWARN("unknown DPI instance\n");
68577 + return OMAP_DSS_CHANNEL_LCD;
68578 + }
68579 +}
68580 +
68581 +static void dra7xx_dpi_init_output(struct platform_device *pdev)
68582 +{
68583 + struct dpi_data *dpi = dev_get_drvdata(&pdev->dev);
68584 + struct omap_dss_device *out = &dpi->output;
68585 + char *name;
68586 +
68587 + out->dev = &pdev->dev;
68588 + name = devm_kzalloc(&pdev->dev, 5, GFP_KERNEL);
68589 +
68590 + switch (dpi->module_id) {
68591 + case 0:
68592 + out->id = OMAP_DSS_OUTPUT_DPI;
68593 + break;
68594 + case 1:
68595 + out->id = OMAP_DSS_OUTPUT_DPI1;
68596 + break;
68597 + case 2:
68598 + out->id = OMAP_DSS_OUTPUT_DPI2;
68599 + break;
68600 + };
68601 +
68602 + snprintf(name, 5, "dpi.%d", dpi->module_id);
68603 + out->name = name;
68604 + out->output_type = OMAP_DISPLAY_TYPE_DPI;
68605 + out->dispc_channel = dra7xx_dpi_get_channel(dpi);
68606 + out->ops.dpi = &dra7xx_dpi_ops;
68607 + out->owner = THIS_MODULE;
68608 +
68609 + omapdss_register_output(out);
68610 +}
68611 +
68612 +static void __exit dra7xx_dpi_uninit_output(struct platform_device *pdev)
68613 +{
68614 + struct dpi_data *dpi = dev_get_drvdata(&pdev->dev);
68615 + struct omap_dss_device *out = &dpi->output;
68616 +
68617 + omapdss_unregister_output(out);
68618 +}
68619 +
68620 +static int dra7xx_dpi_probe(struct platform_device *pdev)
68621 +{
68622 + int r;
68623 + struct dpi_data *dpi;
68624 +
68625 + dpi = devm_kzalloc(&pdev->dev, sizeof(*dpi), GFP_KERNEL);
68626 + if (!dpi)
68627 + return -ENOMEM;
68628 +
68629 + dev_set_drvdata(&pdev->dev, dpi);
68630 +
68631 + mutex_init(&dpi->lock);
68632 +
68633 + if (pdev->dev.of_node) {
68634 + u32 id;
68635 + enum omap_channel channel;
68636 +
68637 + r = of_property_read_u32(pdev->dev.of_node, "id", &id);
68638 + if (r) {
68639 + DSSERR("failed to read DPI module ID\n");
68640 + return r;
68641 + }
68642 +
68643 + r = of_property_read_u32(pdev->dev.of_node, "channel", &channel);
68644 + if (r && id == 0) {
68645 + DSSERR("failed to read DPI channel\n");
68646 + return r;
68647 + }
68648 +
68649 + dpi->module_id = id;
68650 + dpi->channel = channel;
68651 + } else {
68652 + dpi->module_id = pdev->id;
68653 + }
68654 +
68655 + dra7xx_dpi_init_output(pdev);
68656 +
68657 + return 0;
68658 +}
68659 +
68660 +static int __exit dra7xx_dpi_remove(struct platform_device *pdev)
68661 +{
68662 + dra7xx_dpi_uninit_output(pdev);
68663 +
68664 + return 0;
68665 +}
68666 +
68667 +#if defined(CONFIG_OF)
68668 +static const struct of_device_id dpi_of_match[] = {
68669 + {
68670 + .compatible = "ti,dra7xx-dpi",
68671 + },
68672 + {},
68673 +};
68674 +#else
68675 +#define dpi_of_match NULL
68676 +#endif
68677 +
68678 +static struct platform_driver dra7xx_dpi_driver = {
68679 + .probe = dra7xx_dpi_probe,
68680 + .remove = __exit_p(dra7xx_dpi_remove),
68681 + .driver = {
68682 + .name = "omapdss_dra7xx_dpi",
68683 + .owner = THIS_MODULE,
68684 + .of_match_table = dpi_of_match,
68685 + },
68686 +};
68687 +
68688 +int __init dra7xx_dpi_init_platform_driver(void)
68689 +{
68690 + return platform_driver_register(&dra7xx_dpi_driver);
68691 +}
68692 +
68693 +void __exit dra7xx_dpi_uninit_platform_driver(void)
68694 +{
68695 + platform_driver_unregister(&dra7xx_dpi_driver);
68696 +}
68697 --- a/drivers/video/omap2/dss/dsi.c
68698 +++ b/drivers/video/omap2/dss/dsi.c
68699 @@ -38,6 +38,7 @@
68700 #include <linux/slab.h>
68701 #include <linux/debugfs.h>
68702 #include <linux/pm_runtime.h>
68703 +#include <linux/of.h>
68704
68705 #include <video/omapdss.h>
68706 #include <video/mipi_display.h>
68707 @@ -373,6 +374,13 @@ struct dsi_packet_sent_handler_data {
68708 struct completion *completion;
68709 };
68710
68711 +struct dsi_module_id_data {
68712 + u32 address;
68713 + int id;
68714 +};
68715 +
68716 +static const struct of_device_id dsi_of_match[];
68717 +
68718 #ifdef DEBUG
68719 static bool dsi_perf;
68720 module_param(dsi_perf, bool, 0644);
68721 @@ -1123,11 +1131,6 @@ static int dsi_regulator_init(struct pla
68722 return 0;
68723
68724 vdds_dsi = devm_regulator_get(&dsi->pdev->dev, "vdds_dsi");
68725 -
68726 - /* DT HACK: try VCXIO to make omapdss work for o4 sdp/panda */
68727 - if (IS_ERR(vdds_dsi))
68728 - vdds_dsi = devm_regulator_get(&dsi->pdev->dev, "VCXIO");
68729 -
68730 if (IS_ERR(vdds_dsi)) {
68731 DSSERR("can't get VDDS_DSI regulator\n");
68732 return PTR_ERR(vdds_dsi);
68733 @@ -5082,6 +5085,7 @@ static enum omap_channel dsi_get_channel
68734 {
68735 switch (omapdss_get_version()) {
68736 case OMAPDSS_VER_OMAP24xx:
68737 + case OMAPDSS_VER_AM43xx:
68738 DSSWARN("DSI not supported\n");
68739 return OMAP_DSS_CHANNEL_LCD;
68740
68741 @@ -5352,7 +5356,6 @@ static int omap_dsihw_probe(struct platf
68742 if (!dsi)
68743 return -ENOMEM;
68744
68745 - dsi->module_id = dsidev->id;
68746 dsi->pdev = dsidev;
68747 dev_set_drvdata(&dsidev->dev, dsi);
68748
68749 @@ -5402,6 +5405,31 @@ static int omap_dsihw_probe(struct platf
68750 return r;
68751 }
68752
68753 + if (dsidev->dev.of_node) {
68754 + const struct of_device_id *match;
68755 + const struct dsi_module_id_data *d;
68756 +
68757 + match = of_match_node(dsi_of_match, dsidev->dev.of_node);
68758 + if (!match) {
68759 + DSSERR("unsupported DSI module\n");
68760 + return -ENODEV;
68761 + }
68762 +
68763 + d = match->data;
68764 +
68765 + while (d->address != 0 && d->address != dsi_mem->start)
68766 + d++;
68767 +
68768 + if (d->address == 0) {
68769 + DSSERR("unsupported DSI module\n");
68770 + return -ENODEV;
68771 + }
68772 +
68773 + dsi->module_id = d->id;
68774 + } else {
68775 + dsi->module_id = dsidev->id;
68776 + }
68777 +
68778 /* DSI VCs initialization */
68779 for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) {
68780 dsi->vc[i].source = DSI_VC_SOURCE_L4;
68781 @@ -5450,6 +5478,7 @@ static int omap_dsihw_probe(struct platf
68782 else if (dsi->module_id == 1)
68783 dss_debugfs_create_file("dsi2_irqs", dsi2_dump_irqs);
68784 #endif
68785 +
68786 return 0;
68787
68788 err_runtime_get:
68789 @@ -5498,6 +5527,23 @@ static const struct dev_pm_ops dsi_pm_op
68790 .runtime_resume = dsi_runtime_resume,
68791 };
68792
68793 +static const struct dsi_module_id_data dsi_of_data_omap3[] = {
68794 + { .address = 0x4804fc00, .id = 0, },
68795 + { },
68796 +};
68797 +
68798 +static const struct dsi_module_id_data dsi_of_data_omap4[] = {
68799 + { .address = 0x58004000, .id = 0, },
68800 + { .address = 0x58005000, .id = 1, },
68801 + { },
68802 +};
68803 +
68804 +static const struct of_device_id dsi_of_match[] = {
68805 + { .compatible = "ti,omap3-dsi", .data = dsi_of_data_omap3, },
68806 + { .compatible = "ti,omap4-dsi", .data = dsi_of_data_omap4, },
68807 + {},
68808 +};
68809 +
68810 static struct platform_driver omap_dsihw_driver = {
68811 .probe = omap_dsihw_probe,
68812 .remove = __exit_p(omap_dsihw_remove),
68813 @@ -5505,6 +5551,7 @@ static struct platform_driver omap_dsihw
68814 .name = "omapdss_dsi",
68815 .owner = THIS_MODULE,
68816 .pm = &dsi_pm_ops,
68817 + .of_match_table = dsi_of_match,
68818 },
68819 };
68820
68821 --- a/drivers/video/omap2/dss/dss.c
68822 +++ b/drivers/video/omap2/dss/dss.c
68823 @@ -23,6 +23,7 @@
68824 #define DSS_SUBSYS_NAME "DSS"
68825
68826 #include <linux/kernel.h>
68827 +#include <linux/module.h>
68828 #include <linux/io.h>
68829 #include <linux/export.h>
68830 #include <linux/err.h>
68831 @@ -33,6 +34,7 @@
68832 #include <linux/pm_runtime.h>
68833 #include <linux/gfp.h>
68834 #include <linux/sizes.h>
68835 +#include <linux/clk-private.h>
68836
68837 #include <video/omapdss.h>
68838
68839 @@ -68,7 +70,8 @@ struct dss_features {
68840 u8 fck_div_max;
68841 u8 dss_fck_multiplier;
68842 const char *clk_name;
68843 - int (*dpi_select_source)(enum omap_channel channel);
68844 + int (*dpi_select_source)(int module_id, enum omap_channel channel);
68845 + bool dpll_clks;
68846 };
68847
68848 static struct {
68849 @@ -428,6 +431,28 @@ void dss_select_lcd_clk_source(enum omap
68850 dss.lcd_clk_source[ix] = clk_src;
68851 }
68852
68853 +void dss_use_dpll_lcd(enum omap_channel channel, bool use_dpll)
68854 +{
68855 + u8 bit;
68856 +
68857 + switch (channel) {
68858 + case OMAP_DSS_CHANNEL_LCD:
68859 + bit = 0;
68860 + break;
68861 + case OMAP_DSS_CHANNEL_LCD2:
68862 + bit = 12;
68863 + break;
68864 + case OMAP_DSS_CHANNEL_LCD3:
68865 + bit = 19;
68866 + break;
68867 + case OMAP_DSS_CHANNEL_DIGIT:
68868 + default:
68869 + return;
68870 + }
68871 +
68872 + REG_FLD_MOD(DSS_CONTROL, use_dpll, bit, bit);
68873 +}
68874 +
68875 enum omap_dss_clk_source dss_get_dispc_clk_source(void)
68876 {
68877 return dss.dispc_clk_source;
68878 @@ -466,7 +491,7 @@ int dss_calc_clock_rates(struct dss_cloc
68879 cinfo->fck = prate / cinfo->fck_div *
68880 dss.feat->dss_fck_multiplier;
68881 } else {
68882 - if (cinfo->fck_div != 0)
68883 + if (cinfo->fck_div != 1)
68884 return -EINVAL;
68885 cinfo->fck = clk_get_rate(dss.dss_clk);
68886 }
68887 @@ -529,7 +554,7 @@ int dss_set_clock_div(struct dss_clock_i
68888 if (r)
68889 return r;
68890 } else {
68891 - if (cinfo->fck_div != 0)
68892 + if (cinfo->fck_div != 1)
68893 return -EINVAL;
68894 }
68895
68896 @@ -635,7 +660,8 @@ enum dss_hdmi_venc_clk_source_select dss
68897 return REG_GET(DSS_CONTROL, 15, 15);
68898 }
68899
68900 -static int dss_dpi_select_source_omap2_omap3(enum omap_channel channel)
68901 +static int dss_dpi_select_source_omap2_omap3(int module_id,
68902 + enum omap_channel channel)
68903 {
68904 if (channel != OMAP_DSS_CHANNEL_LCD)
68905 return -EINVAL;
68906 @@ -643,7 +669,7 @@ static int dss_dpi_select_source_omap2_o
68907 return 0;
68908 }
68909
68910 -static int dss_dpi_select_source_omap4(enum omap_channel channel)
68911 +static int dss_dpi_select_source_omap4(int module_id, enum omap_channel channel)
68912 {
68913 int val;
68914
68915 @@ -663,7 +689,7 @@ static int dss_dpi_select_source_omap4(e
68916 return 0;
68917 }
68918
68919 -static int dss_dpi_select_source_omap5(enum omap_channel channel)
68920 +static int dss_dpi_select_source_omap5(int module_id, enum omap_channel channel)
68921 {
68922 int val;
68923
68924 @@ -689,9 +715,17 @@ static int dss_dpi_select_source_omap5(e
68925 return 0;
68926 }
68927
68928 -int dss_dpi_select_source(enum omap_channel channel)
68929 +static int dss_dpi_select_source_dra7xx(int module_id, enum omap_channel channel)
68930 +{
68931 + if (module_id != 0)
68932 + return 0;
68933 +
68934 + return dss_dpi_select_source_omap5(module_id, channel);
68935 +}
68936 +
68937 +int dss_dpi_select_source(int module_id, enum omap_channel channel)
68938 {
68939 - return dss.feat->dpi_select_source(channel);
68940 + return dss.feat->dpi_select_source(module_id, channel);
68941 }
68942
68943 static int dss_get_clocks(void)
68944 @@ -713,11 +747,26 @@ static int dss_get_clocks(void)
68945 return PTR_ERR(clk);
68946 }
68947 } else {
68948 + int r;
68949 +
68950 + DSSDBG("DSS CLOCK HACK\n");
68951 + printk("FCK %s\n", clk->name);
68952 +
68953 + clk = clk_get_parent(clk);
68954 + DSSDBG("GATE %s\n", clk->name);
68955 +
68956 + clk = clk_get_parent(clk);
68957 + DSSDBG("PLL %s\n", clk->name);
68958 +
68959 + r = clk_set_rate(clk, 150000000);
68960 + if (!r)
68961 + DSSERR("SET CLK RATE Failed");
68962 clk = NULL;
68963 }
68964
68965 dss.dpll4_m4_ck = clk;
68966
68967 +
68968 return 0;
68969 }
68970
68971 @@ -795,6 +844,21 @@ static const struct dss_features omap54x
68972 .dpi_select_source = &dss_dpi_select_source_omap5,
68973 };
68974
68975 +static const struct dss_features dra7xx_dss_feats __initconst = {
68976 + .fck_div_max = 64,
68977 + .dss_fck_multiplier = 1,
68978 + .clk_name = "dpll_per_h12x2_ck",
68979 + .dpi_select_source = &dss_dpi_select_source_dra7xx,
68980 + .dpll_clks = true,
68981 +};
68982 +
68983 +static const struct dss_features am43xx_dss_feats __initconst = {
68984 + .fck_div_max = 0,
68985 + .dss_fck_multiplier = 0,
68986 + .clk_name = NULL,
68987 + .dpi_select_source = &dss_dpi_select_source_omap2_omap3,
68988 +};
68989 +
68990 static int __init dss_init_features(struct platform_device *pdev)
68991 {
68992 const struct dss_features *src;
68993 @@ -831,6 +895,14 @@ static int __init dss_init_features(stru
68994 src = &omap54xx_dss_feats;
68995 break;
68996
68997 + case OMAPDSS_VER_DRA7xx:
68998 + src = &dra7xx_dss_feats;
68999 + break;
69000 +
69001 + case OMAPDSS_VER_AM43xx:
69002 + src = &am43xx_dss_feats;
69003 + break;
69004 +
69005 default:
69006 return -ENODEV;
69007 }
69008 @@ -907,6 +979,15 @@ static int __init omap_dsshw_probe(struc
69009
69010 dss_debugfs_create_file("dss", dss_dump_regs);
69011
69012 + if (dss.feat->dpll_clks) {
69013 + r = dss_dpll_configure(pdev);
69014 + if (r)
69015 + goto err_runtime_get;
69016 + r = dss_dpll_configure_ctrl();
69017 + if (r)
69018 + goto err_runtime_get;
69019 + }
69020 +
69021 return 0;
69022
69023 err_runtime_get:
69024 @@ -920,6 +1001,9 @@ static int __exit omap_dsshw_remove(stru
69025 {
69026 pm_runtime_disable(&pdev->dev);
69027
69028 + if (dss.feat->dpll_clks)
69029 + dss_dpll_unconfigure_ctrl();
69030 +
69031 dss_put_clocks();
69032
69033 return 0;
69034 @@ -955,12 +1039,21 @@ static const struct dev_pm_ops dss_pm_op
69035 .runtime_resume = dss_runtime_resume,
69036 };
69037
69038 +static const struct of_device_id dss_of_match[] = {
69039 + { .compatible = "ti,omap3-dss", },
69040 + { .compatible = "ti,omap4-dss", },
69041 + {},
69042 +};
69043 +
69044 +MODULE_DEVICE_TABLE(of, dss_of_match);
69045 +
69046 static struct platform_driver omap_dsshw_driver = {
69047 .remove = __exit_p(omap_dsshw_remove),
69048 .driver = {
69049 .name = "omapdss_dss",
69050 .owner = THIS_MODULE,
69051 .pm = &dss_pm_ops,
69052 + .of_match_table = dss_of_match,
69053 },
69054 };
69055
69056 --- /dev/null
69057 +++ b/drivers/video/omap2/dss/dss_dpll.c
69058 @@ -0,0 +1,536 @@
69059 +/*
69060 + * Copyright (C) 2013 Texas Instruments Ltd
69061 + *
69062 + * Copy of the DSI PLL code
69063 + *
69064 + * This program is free software; you can redistribute it and/or modify it
69065 + * under the terms of the GNU General Public License version 2 as published by
69066 + * the Free Software Foundation.
69067 + *
69068 + * This program is distributed in the hope that it will be useful, but WITHOUT
69069 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
69070 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
69071 + * more details.
69072 + *
69073 + * You should have received a copy of the GNU General Public License along with
69074 + * this program. If not, see <http://www.gnu.org/licenses/>.
69075 + */
69076 +
69077 +#include <linux/kernel.h>
69078 +#include <linux/err.h>
69079 +#include <linux/delay.h>
69080 +#include <linux/io.h>
69081 +#include <linux/clk.h>
69082 +#include <linux/platform_device.h>
69083 +#include <linux/regulator/consumer.h>
69084 +#include <linux/sched.h>
69085 +#include <linux/wait.h>
69086 +
69087 +#include <video/omapdss.h>
69088 +
69089 +#include "dss.h"
69090 +#include "dss_features.h"
69091 +
69092 +#define CLK_CTRL 0x054
69093 +#define PLL_CONTROL 0x300
69094 +#define PLL_STATUS 0x304
69095 +#define PLL_GO 0x308
69096 +#define PLL_CONFIGURATION1 0x30C
69097 +#define PLL_CONFIGURATION2 0x310
69098 +#define PLL_CONFIGURATION3 0x314
69099 +#define PLL_SSC_CONFIGURATION1 0x318
69100 +#define PLL_SSC_CONFIGURATION2 0x31C
69101 +
69102 +#define CTRL_BASE 0x4a002500
69103 +#define DSS_PLL_CONTROL 0x38
69104 +
69105 +#define REG_GET(dpll, idx, start, end) \
69106 + FLD_GET(dpll_read_reg(dpll, idx), start, end)
69107 +
69108 +#define REG_FLD_MOD(dpll, idx, val, start, end) \
69109 + dpll_write_reg(dpll, idx, FLD_MOD(dpll_read_reg(dpll, idx), val, start, end))
69110 +
69111 +static struct {
69112 + struct platform_device *pdev;
69113 + struct regulator *vdda_video_reg;
69114 +
69115 + void __iomem *base[2], *control_base;
69116 + unsigned scp_refcount[2];
69117 + struct clk *sys_clk[2];
69118 + bool enabled[3];
69119 +} dss_dpll;
69120 +
69121 +static inline u32 dpll_read_reg(enum dss_dpll dpll, u16 offset)
69122 +{
69123 + return __raw_readl(dss_dpll.base[dpll] + offset);
69124 +}
69125 +
69126 +static inline void dpll_write_reg(enum dss_dpll dpll, u16 offset, u32 val)
69127 +{
69128 + __raw_writel(val, dss_dpll.base[dpll] + offset);
69129 +}
69130 +
69131 +#define CTRL_REG_GET(start, end) \
69132 + FLD_GET(ctrl_read_reg(), start, end)
69133 +
69134 +#define CTRL_REG_FLD_MOD(val, start, end) \
69135 + ctrl_write_reg(FLD_MOD(ctrl_read_reg(), val, start, end))
69136 +
69137 +static inline u32 ctrl_read_reg(void)
69138 +{
69139 + return __raw_readl(dss_dpll.control_base + DSS_PLL_CONTROL);
69140 +}
69141 +
69142 +static inline void ctrl_write_reg(u32 val)
69143 +{
69144 + __raw_writel(val, dss_dpll.control_base + DSS_PLL_CONTROL);
69145 +}
69146 +
69147 +static inline int wait_for_bit_change(enum dss_dpll dpll,
69148 + const u16 offset, int bitnum, int value)
69149 +{
69150 + unsigned long timeout;
69151 + ktime_t wait;
69152 + int t;
69153 +
69154 + /* first busyloop to see if the bit changes right away */
69155 + t = 100;
69156 + while (t-- > 0) {
69157 + if (REG_GET(dpll, offset, bitnum, bitnum) == value)
69158 + return value;
69159 + }
69160 +
69161 + /* then loop for 500ms, sleeping for 1ms in between */
69162 + timeout = jiffies + msecs_to_jiffies(500);
69163 + while (time_before(jiffies, timeout)) {
69164 + if (REG_GET(dpll, offset, bitnum, bitnum) == value)
69165 + return value;
69166 +
69167 + wait = ns_to_ktime(1000 * 1000);
69168 + set_current_state(TASK_UNINTERRUPTIBLE);
69169 + schedule_hrtimeout(&wait, HRTIMER_MODE_REL);
69170 + }
69171 +
69172 + return !value;
69173 +}
69174 +
69175 +bool dss_dpll_disabled(enum dss_dpll dpll)
69176 +{
69177 + return !dss_dpll.enabled[dpll];
69178 +}
69179 +
69180 +unsigned long dpll_get_clkin(enum dss_dpll dpll)
69181 +{
69182 + return clk_get_rate(dss_dpll.sys_clk[dpll]);
69183 +}
69184 +
69185 +bool dss_dpll_calc(enum dss_dpll dpll, unsigned long clkin,
69186 + unsigned long pll_min, unsigned long pll_max,
69187 + dss_dpll_calc_func func, void *data)
69188 +{
69189 + int regn, regn_start, regn_stop;
69190 + int regm, regm_start, regm_stop;
69191 + unsigned long fint, pll;
69192 + const unsigned long pll_hw_max = 1800000000;
69193 + unsigned long fint_hw_min, fint_hw_max, regm_max, regn_max;
69194 +
69195 + fint_hw_min = dss_feat_get_param_min(FEAT_PARAM_DSIPLL_FINT);
69196 + fint_hw_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_FINT);
69197 + regm_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM);
69198 + regn_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGN);
69199 +
69200 + regn_start = max(DIV_ROUND_UP(clkin, fint_hw_max), 1ul);
69201 + regn_stop = min(clkin / fint_hw_min, regn_max);
69202 +
69203 + pll_max = pll_max ? pll_max : ULONG_MAX;
69204 +
69205 + for (regn = regn_start; regn <= regn_stop; ++regn) {
69206 + fint = clkin / regn;
69207 +
69208 + regm_start = max(DIV_ROUND_UP(DIV_ROUND_UP(pll_min, fint), 2),
69209 + 1ul);
69210 + regm_stop = min3(pll_max / fint / 2,
69211 + pll_hw_max / fint / 2,
69212 + regm_max);
69213 +
69214 + for (regm = regm_start; regm <= regm_stop; ++regm) {
69215 + pll = 2 * regm * fint;
69216 +
69217 + if (func(regn, regm, fint, pll, data))
69218 + return true;
69219 + }
69220 + }
69221 +
69222 + return false;
69223 +}
69224 +
69225 +bool dss_dpll_hsdiv_calc(enum dss_dpll dpll, unsigned long pll,
69226 + unsigned long out_min, dss_dpll_hsdiv_calc_func func, void *data)
69227 +{
69228 + int regm, regm_start, regm_stop;
69229 + unsigned long out_max;
69230 + unsigned long out;
69231 + unsigned long regm_dispc_max;
69232 +
69233 + regm_dispc_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DISPC);
69234 +
69235 + out_min = out_min ? out_min : 1;
69236 + out_max = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
69237 +
69238 + regm_start = max(DIV_ROUND_UP(pll, out_max), 1ul);
69239 + regm_stop = min(pll / out_min, regm_dispc_max);
69240 +
69241 + for (regm = regm_start; regm <= regm_stop; ++regm) {
69242 + out = pll / regm;
69243 +
69244 + if (func(regm, out, data))
69245 + return true;
69246 + }
69247 +
69248 + return false;
69249 +}
69250 +
69251 +int dss_dpll_set_clock_div(enum dss_dpll dpll, struct dss_dpll_cinfo *cinfo)
69252 +{
69253 + int r = 0;
69254 + u32 l;
69255 + u8 regn_start, regn_end, regm_start, regm_end;
69256 + u8 regm_hsdiv_start, regm_hsdiv_end;
69257 +
69258 + DSSDBG("DPLL_VIDEO%d clock config starts\n", dpll + 1);
69259 +
69260 + DSSDBG("DPLL Fint %ld\n", cinfo->fint);
69261 +
69262 + DSSDBG("clkin rate %ld\n", cinfo->clkin);
69263 +
69264 + DSSDBG("CLKOUT = 2 * %d / %d * %lu = %lu\n",
69265 + cinfo->regm,
69266 + cinfo->regn,
69267 + cinfo->clkin,
69268 + cinfo->clkout);
69269 +
69270 + DSSDBG("regm_hsdiv = %d\n", cinfo->regm_hsdiv);
69271 +
69272 + dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGN, &regn_start, &regn_end);
69273 + dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM, &regm_start, &regm_end);
69274 + dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM_DISPC, &regm_hsdiv_start,
69275 + &regm_hsdiv_end);
69276 +
69277 + /* PLL_AUTOMODE = manual */
69278 + REG_FLD_MOD(dpll, PLL_CONTROL, 0, 0, 0);
69279 +
69280 + /* CONFIGURATION1 */
69281 + l = dpll_read_reg(dpll, PLL_CONFIGURATION1);
69282 + /* PLL_REGN */
69283 + l = FLD_MOD(l, cinfo->regn - 1, regn_start, regn_end);
69284 + /* PLL_REGM */
69285 + l = FLD_MOD(l, cinfo->regm, regm_start, regm_end);
69286 + /* M4_CLOCK_DIV */
69287 + l = FLD_MOD(l, cinfo->regm_hsdiv > 0 ? cinfo->regm_hsdiv - 1 : 0,
69288 + regm_hsdiv_start, regm_hsdiv_end);
69289 + dpll_write_reg(dpll, PLL_CONFIGURATION1, l);
69290 +
69291 + /* CONFIGURATION3 */
69292 + l = dpll_read_reg(dpll, PLL_CONFIGURATION3);
69293 + /* M6_CLOCK_DIV */
69294 + l = FLD_MOD(l, cinfo->regm_hsdiv > 0 ? cinfo->regm_hsdiv - 1 : 0, 4, 0);
69295 + dpll_write_reg(dpll, PLL_CONFIGURATION3, l);
69296 +
69297 + /* CONFIGURATION2 */
69298 + l = dpll_read_reg(dpll, PLL_CONFIGURATION2);
69299 + l = FLD_MOD(l, 1, 13, 13); /* PLL_REFEN */
69300 + l = FLD_MOD(l, 0, 14, 14); /* DSIPHY_CLKINEN */
69301 + l = FLD_MOD(l, 1, 20, 20); /* HSDIVBYPASS */
69302 + l = FLD_MOD(l, 3, 22, 21); /* REF_SYSCLK = sysclk */
69303 + dpll_write_reg(dpll, PLL_CONFIGURATION2, l);
69304 +
69305 + REG_FLD_MOD(dpll, PLL_GO, 1, 0, 0); /* PLL_GO */
69306 +
69307 + if (wait_for_bit_change(dpll, PLL_GO, 0, 0) != 0) {
69308 + DSSERR("dsi pll go bit not going down.\n");
69309 + r = -EIO;
69310 + goto err;
69311 + }
69312 +
69313 + if (wait_for_bit_change(dpll, PLL_STATUS, 1, 1) != 1) {
69314 + DSSERR("cannot lock PLL\n");
69315 + r = -EIO;
69316 + goto err;
69317 + }
69318 +
69319 + l = dpll_read_reg(dpll, PLL_CONFIGURATION2);
69320 + l = FLD_MOD(l, 0, 0, 0); /* PLL_IDLE */
69321 + l = FLD_MOD(l, 0, 5, 5); /* PLL_PLLLPMODE */
69322 + l = FLD_MOD(l, 0, 6, 6); /* PLL_LOWCURRSTBY */
69323 + l = FLD_MOD(l, 0, 7, 7); /* PLL_TIGHTPHASELOCK */
69324 + l = FLD_MOD(l, 0, 8, 8); /* PLL_DRIFTGUARDEN */
69325 + l = FLD_MOD(l, 0, 10, 9); /* PLL_LOCKSEL */
69326 + l = FLD_MOD(l, 1, 13, 13); /* PLL_REFEN */
69327 + l = FLD_MOD(l, 1, 14, 14); /* PHY_CLKINEN */
69328 + l = FLD_MOD(l, 0, 15, 15); /* BYPASSEN */
69329 + l = FLD_MOD(l, 1, 16, 16); /* M4_CLOCK_EN */
69330 + l = FLD_MOD(l, 0, 17, 17); /* CLOCK_PWDN */
69331 + l = FLD_MOD(l, 1, 18, 18); /* PROTO_CLOCK_EN */
69332 + l = FLD_MOD(l, 0, 19, 19); /* PROTO_CLOCK_PWDN */
69333 + l = FLD_MOD(l, 0, 20, 20); /* HSDIVBYPASS */
69334 + l = FLD_MOD(l, 1, 23, 23); /* M6_CLOCK_EN */
69335 + dpll_write_reg(dpll, PLL_CONFIGURATION2, l);
69336 +
69337 + DSSDBG("PLL config done\n");
69338 +
69339 +err:
69340 + return r;
69341 +}
69342 +
69343 +static void dss_dpll_disable_scp_clk(enum dss_dpll dpll)
69344 +{
69345 + unsigned *refcount;
69346 +
69347 + refcount = &dss_dpll.scp_refcount[dpll];
69348 +
69349 + WARN_ON(*refcount == 0);
69350 + if (--(*refcount) == 0)
69351 + REG_FLD_MOD(dpll, CLK_CTRL, 0, 14, 14); /* CIO_CLK_ICG */
69352 +}
69353 +
69354 +static void dss_dpll_enable_scp_clk(enum dss_dpll dpll)
69355 +{
69356 + unsigned *refcount;
69357 +
69358 + refcount = &dss_dpll.scp_refcount[dpll];
69359 +
69360 + if ((*refcount)++ == 0)
69361 + REG_FLD_MOD(dpll, CLK_CTRL, 1, 14, 14); /* CIO_CLK_ICG */
69362 +}
69363 +
69364 +static int dpll_power(enum dss_dpll dpll, int state)
69365 +{
69366 + int t = 0;
69367 + /* PLL_PWR_CMD = enable both hsdiv and clkout*/
69368 + REG_FLD_MOD(dpll, CLK_CTRL, state, 31, 30);
69369 +
69370 + /* PLL_PWR_STATUS: (NOTE: apparently buggy) */
69371 + while (FLD_GET(dpll_read_reg(dpll, CLK_CTRL), 29, 28) != state) {
69372 + if (++t > 1000) {
69373 + DSSERR("Failed to set DPLL power mode to %d\n", state);
69374 + /* return -ENODEV; */
69375 + return 0;
69376 + }
69377 + udelay(1);
69378 + }
69379 +
69380 + return 0;
69381 +}
69382 +
69383 +void dss_dpll_enable_ctrl(enum dss_dpll dpll, bool enable)
69384 +{
69385 + u8 bit;
69386 +
69387 + switch (dpll) {
69388 + case DSS_DPLL_VIDEO1:
69389 + bit = 0;
69390 + break;
69391 + case DSS_DPLL_VIDEO2:
69392 + bit = 1;
69393 + break;
69394 + case DSS_DPLL_HDMI:
69395 + bit = 2;
69396 + break;
69397 + default:
69398 + DSSERR("invalid dpll\n");
69399 + return;
69400 + }
69401 +
69402 + CTRL_REG_FLD_MOD(!enable, bit, bit);
69403 +
69404 + dss_dpll.enabled[dpll] = enable;
69405 +}
69406 +
69407 +static int dpll_init(enum dss_dpll dpll)
69408 +{
69409 + int r;
69410 +
69411 + clk_prepare_enable(dss_dpll.sys_clk[dpll]);
69412 + dss_dpll_enable_scp_clk(dpll);
69413 +
69414 + r = regulator_enable(dss_dpll.vdda_video_reg);
69415 + if (r)
69416 + goto err_reg;
69417 +
69418 + if (wait_for_bit_change(dpll, PLL_STATUS, 0, 1) != 1) {
69419 + DSSERR("PLL not coming out of reset.\n");
69420 + r = -ENODEV;
69421 + goto err_reset;
69422 + }
69423 +
69424 + r = dpll_power(dpll, 0x2);
69425 + if (r)
69426 + goto err_reset;
69427 +
69428 + return 0;
69429 +
69430 +err_reset:
69431 + regulator_disable(dss_dpll.vdda_video_reg);
69432 +err_reg:
69433 + dss_dpll_disable_scp_clk(dpll);
69434 + clk_disable_unprepare(dss_dpll.sys_clk[dpll]);
69435 +
69436 + return r;
69437 +}
69438 +
69439 +int dss_dpll_activate(enum dss_dpll dpll)
69440 +{
69441 + int r;
69442 +
69443 + /* enable from control module */
69444 + dss_dpll_enable_ctrl(dpll, true);
69445 +
69446 + r = dpll_init(dpll);
69447 +
69448 + return r;
69449 +}
69450 +
69451 +void dss_dpll_set_control_mux(enum omap_channel channel, enum dss_dpll dpll)
69452 +{
69453 + u8 start, end;
69454 + u8 val;
69455 +
69456 + if (channel == OMAP_DSS_CHANNEL_LCD) {
69457 + start = 4;
69458 + end = 3;
69459 +
69460 + switch (dpll) {
69461 + case DSS_DPLL_VIDEO1:
69462 + val = 0;
69463 + break;
69464 + default:
69465 + DSSERR("error in mux config for LCD\n");
69466 + return;
69467 + }
69468 + } else if (channel == OMAP_DSS_CHANNEL_LCD2) {
69469 + start = 6;
69470 + end = 5;
69471 +
69472 + switch (dpll) {
69473 + case DSS_DPLL_VIDEO1:
69474 + val = 0;
69475 + break;
69476 + case DSS_DPLL_VIDEO2:
69477 + val = 1;
69478 + break;
69479 + default:
69480 + DSSERR("error in mux config for LCD2\n");
69481 + return;
69482 + }
69483 + } else {
69484 + start = 8;
69485 + end = 7;
69486 +
69487 + switch (dpll) {
69488 + case DSS_DPLL_VIDEO1:
69489 + val = 1;
69490 + break;
69491 + case DSS_DPLL_VIDEO2:
69492 + val = 0;
69493 + break;
69494 + default:
69495 + DSSERR("error in mux config for LCD3\n");
69496 + return;
69497 + }
69498 + }
69499 +
69500 + CTRL_REG_FLD_MOD(val, start, end);
69501 +}
69502 +
69503 +void dss_dpll_disable(enum dss_dpll dpll)
69504 +{
69505 + dpll_power(dpll, 0);
69506 +
69507 + regulator_disable(dss_dpll.vdda_video_reg);
69508 +
69509 + dss_dpll_disable_scp_clk(dpll);
69510 + clk_disable_unprepare(dss_dpll.sys_clk[dpll]);
69511 +
69512 + dss_dpll_enable_ctrl(dpll, false);
69513 +}
69514 +
69515 +static int dss_dpll_configure_one(struct platform_device *pdev,
69516 + enum dss_dpll dpll)
69517 +{
69518 + struct resource *dpll_mem;
69519 +
69520 + dpll_mem = platform_get_resource(pdev, IORESOURCE_MEM, dpll + 1);
69521 + if (!dpll_mem) {
69522 + DSSERR("can't get IORESOURCE_MEM for DPLL %d\n", dpll);
69523 + return -EINVAL;
69524 + }
69525 +
69526 + dss_dpll.base[dpll] = devm_ioremap(&pdev->dev, dpll_mem->start,
69527 + resource_size(dpll_mem));
69528 + if (!dss_dpll.base[dpll]) {
69529 + DSSERR("can't ioremap DPLL %d\n", dpll);
69530 + return -ENOMEM;
69531 + }
69532 +
69533 + dss_dpll.sys_clk[dpll] = devm_clk_get(&pdev->dev,
69534 + dpll == DSS_DPLL_VIDEO1 ? "video1_clk" : "video2_clk");
69535 + if (IS_ERR(dss_dpll.sys_clk[dpll])) {
69536 + DSSERR("can't get sys clock for DPLL_VIDEO%d\n", dpll + 1);
69537 + return PTR_ERR(dss_dpll.sys_clk[dpll]);
69538 + }
69539 +
69540 + return 0;
69541 +}
69542 +
69543 +int dss_dpll_init_regulator(enum dss_dpll dpll)
69544 +{
69545 + struct regulator *reg;
69546 + struct platform_device *pdev = dss_dpll.pdev;
69547 +
69548 + if (dpll == DSS_DPLL_NONE)
69549 + return 0;
69550 +
69551 + reg = devm_regulator_get(&pdev->dev, "vdda_video");
69552 + if (IS_ERR(reg)) {
69553 + DSSERR("can't get vdda_video regulator\n");
69554 + return PTR_ERR(reg);
69555 + }
69556 +
69557 + dss_dpll.vdda_video_reg = reg;
69558 +
69559 + return 0;
69560 +}
69561 +
69562 +int dss_dpll_configure(struct platform_device *pdev)
69563 +{
69564 + int r;
69565 +
69566 + r = dss_dpll_configure_one(pdev, DSS_DPLL_VIDEO1);
69567 + if (r)
69568 + return r;
69569 +
69570 + r = dss_dpll_configure_one(pdev, DSS_DPLL_VIDEO2);
69571 + if (r)
69572 + return r;
69573 +
69574 + dss_dpll.pdev = pdev;
69575 +
69576 + return 0;
69577 +}
69578 +
69579 +int dss_dpll_configure_ctrl(void)
69580 +{
69581 + dss_dpll.control_base = ioremap(CTRL_BASE, SZ_1K);
69582 +
69583 + if (!dss_dpll.control_base) {
69584 + DSSERR("can't ioremap control base\n");
69585 + return -ENOMEM;
69586 + }
69587 +
69588 + return 0;
69589 +}
69590 +
69591 +void dss_dpll_unconfigure_ctrl(void) {
69592 + if (dss_dpll.control_base)
69593 + iounmap(dss_dpll.control_base);
69594 +}
69595 --- a/drivers/video/omap2/dss/dss_features.c
69596 +++ b/drivers/video/omap2/dss/dss_features.c
69597 @@ -93,6 +93,17 @@ static const struct dss_reg_field omap3_
69598 [FEAT_REG_DSIPLL_REGM_DSI] = { 26, 23 },
69599 };
69600
69601 +static const struct dss_reg_field am43xx_dss_reg_fields[] = {
69602 + [FEAT_REG_FIRHINC] = { 12, 0 },
69603 + [FEAT_REG_FIRVINC] = { 28, 16 },
69604 + [FEAT_REG_FIFOLOWTHRESHOLD] = { 11, 0 },
69605 + [FEAT_REG_FIFOHIGHTHRESHOLD] = { 27, 16 },
69606 + [FEAT_REG_FIFOSIZE] = { 10, 0 },
69607 + [FEAT_REG_HORIZONTALACCU] = { 9, 0 },
69608 + [FEAT_REG_VERTICALACCU] = { 25, 16 },
69609 + [FEAT_REG_DISPC_CLK_SWITCH] = { 0, 0 },
69610 +};
69611 +
69612 static const struct dss_reg_field omap4_dss_reg_fields[] = {
69613 [FEAT_REG_FIRHINC] = { 12, 0 },
69614 [FEAT_REG_FIRVINC] = { 28, 16 },
69615 @@ -149,6 +160,11 @@ static const enum omap_display_type omap
69616 OMAP_DISPLAY_TYPE_VENC,
69617 };
69618
69619 +static const enum omap_display_type am43xx_dss_supported_displays[] = {
69620 + /* OMAP_DSS_CHANNEL_LCD */
69621 + OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI,
69622 +};
69623 +
69624 static const enum omap_display_type omap4_dss_supported_displays[] = {
69625 /* OMAP_DSS_CHANNEL_LCD */
69626 OMAP_DISPLAY_TYPE_DBI | OMAP_DISPLAY_TYPE_DSI,
69627 @@ -174,6 +190,20 @@ static const enum omap_display_type omap
69628 OMAP_DISPLAY_TYPE_DSI,
69629 };
69630
69631 +static const enum omap_display_type dra7xx_dss_supported_displays[] = {
69632 + /* OMAP_DSS_CHANNEL_LCD */
69633 + OMAP_DISPLAY_TYPE_DPI,
69634 +
69635 + /* OMAP_DSS_CHANNEL_DIGIT */
69636 + OMAP_DISPLAY_TYPE_HDMI | OMAP_DISPLAY_TYPE_DPI,
69637 +
69638 + /* OMAP_DSS_CHANNEL_LCD2 */
69639 + OMAP_DISPLAY_TYPE_DPI,
69640 +
69641 + /* OMAP_DSS_CHANNEL_LCD3 */
69642 + OMAP_DISPLAY_TYPE_DPI,
69643 +};
69644 +
69645 static const enum omap_dss_output_id omap2_dss_supported_outputs[] = {
69646 /* OMAP_DSS_CHANNEL_LCD */
69647 OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI,
69648 @@ -200,6 +230,11 @@ static const enum omap_dss_output_id oma
69649 OMAP_DSS_OUTPUT_VENC,
69650 };
69651
69652 +static const enum omap_dss_output_id am43xx_dss_supported_outputs[] = {
69653 + /* OMAP_DSS_CHANNEL_LCD */
69654 + OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI,
69655 +};
69656 +
69657 static const enum omap_dss_output_id omap4_dss_supported_outputs[] = {
69658 /* OMAP_DSS_CHANNEL_LCD */
69659 OMAP_DSS_OUTPUT_DBI | OMAP_DSS_OUTPUT_DSI1,
69660 @@ -229,6 +264,20 @@ static const enum omap_dss_output_id oma
69661 OMAP_DSS_OUTPUT_DSI2,
69662 };
69663
69664 +static const enum omap_dss_output_id dra7xx_dss_supported_outputs[] = {
69665 + /* OMAP_DSS_CHANNEL_LCD */
69666 + OMAP_DSS_OUTPUT_DPI,
69667 +
69668 + /* OMAP_DSS_CHANNEL_DIGIT */
69669 + OMAP_DSS_OUTPUT_HDMI | OMAP_DSS_OUTPUT_DPI,
69670 +
69671 + /* OMAP_DSS_CHANNEL_LCD2 */
69672 + OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DPI1,
69673 +
69674 + /* OMAP_DSS_CHANNEL_LCD3 */
69675 + OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DPI2,
69676 +};
69677 +
69678 static const enum omap_color_mode omap2_dss_supported_color_modes[] = {
69679 /* OMAP_DSS_GFX */
69680 OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 |
69681 @@ -444,6 +493,13 @@ static const struct dss_param_range omap
69682 [FEAT_PARAM_LINEWIDTH] = { 1, 1024 },
69683 };
69684
69685 +static const struct dss_param_range am43xx_dss_param_range[] = {
69686 + [FEAT_PARAM_DSS_FCK] = { 0, 200000000 },
69687 + [FEAT_PARAM_DSS_PCD] = { 2, 255 },
69688 + [FEAT_PARAM_DOWNSCALE] = { 1, 4 },
69689 + [FEAT_PARAM_LINEWIDTH] = { 1, 1024 },
69690 +};
69691 +
69692 static const struct dss_param_range omap4_dss_param_range[] = {
69693 [FEAT_PARAM_DSS_FCK] = { 0, 186000000 },
69694 [FEAT_PARAM_DSS_PCD] = { 1, 255 },
69695 @@ -520,6 +576,21 @@ static const enum dss_feat_id am35xx_dss
69696 FEAT_OMAP3_DSI_FIFO_BUG,
69697 };
69698
69699 +static const enum dss_feat_id am43xx_dss_feat_list[] = {
69700 + FEAT_LCDENABLEPOL,
69701 + FEAT_LCDENABLESIGNAL,
69702 + FEAT_PCKFREEENABLE,
69703 + FEAT_FUNCGATED,
69704 + FEAT_LINEBUFFERSPLIT,
69705 + FEAT_ROWREPEATENABLE,
69706 + FEAT_RESIZECONF,
69707 + FEAT_CPR,
69708 + FEAT_PRELOAD,
69709 + FEAT_FIR_COEF_V,
69710 + FEAT_ALPHA_FIXED_ZORDER,
69711 + FEAT_FIFO_MERGE,
69712 +};
69713 +
69714 static const enum dss_feat_id omap3630_dss_feat_list[] = {
69715 FEAT_LCDENABLEPOL,
69716 FEAT_LCDENABLESIGNAL,
69717 @@ -595,6 +666,7 @@ static const enum dss_feat_id omap4_dss_
69718
69719 static const enum dss_feat_id omap5_dss_feat_list[] = {
69720 FEAT_MGR_LCD2,
69721 + FEAT_MGR_LCD3,
69722 FEAT_CORE_CLK_DIV,
69723 FEAT_LCD_CLK_SRC,
69724 FEAT_DSI_DCS_CMD_CONFIG_VC,
69725 @@ -681,6 +753,26 @@ static const struct omap_dss_features am
69726 .burst_size_unit = 8,
69727 };
69728
69729 +static const struct omap_dss_features am43xx_dss_features = {
69730 + .reg_fields = am43xx_dss_reg_fields,
69731 + .num_reg_fields = ARRAY_SIZE(am43xx_dss_reg_fields),
69732 +
69733 + .features = am43xx_dss_feat_list,
69734 + .num_features = ARRAY_SIZE(am43xx_dss_feat_list),
69735 +
69736 + .num_mgrs = 1,
69737 + .num_ovls = 3,
69738 + .supported_displays = am43xx_dss_supported_displays,
69739 + .supported_outputs = am43xx_dss_supported_outputs,
69740 + .supported_color_modes = omap3_dss_supported_color_modes,
69741 + .overlay_caps = omap3430_dss_overlay_caps,
69742 + .clksrc_names = omap2_dss_clk_source_names,
69743 + .dss_params = am43xx_dss_param_range,
69744 + .supported_rotation_types = OMAP_DSS_ROT_DMA,
69745 + .buffer_size_unit = 1,
69746 + .burst_size_unit = 8,
69747 +};
69748 +
69749 static const struct omap_dss_features omap3630_dss_features = {
69750 .reg_fields = omap3_dss_reg_fields,
69751 .num_reg_fields = ARRAY_SIZE(omap3_dss_reg_fields),
69752 @@ -789,49 +881,26 @@ static const struct omap_dss_features om
69753 .burst_size_unit = 16,
69754 };
69755
69756 -#if defined(CONFIG_OMAP4_DSS_HDMI)
69757 -/* HDMI OMAP4 Functions*/
69758 -static const struct ti_hdmi_ip_ops omap4_hdmi_functions = {
69759 -
69760 - .video_configure = ti_hdmi_4xxx_basic_configure,
69761 - .phy_enable = ti_hdmi_4xxx_phy_enable,
69762 - .phy_disable = ti_hdmi_4xxx_phy_disable,
69763 - .read_edid = ti_hdmi_4xxx_read_edid,
69764 - .pll_enable = ti_hdmi_4xxx_pll_enable,
69765 - .pll_disable = ti_hdmi_4xxx_pll_disable,
69766 - .video_enable = ti_hdmi_4xxx_wp_video_start,
69767 - .video_disable = ti_hdmi_4xxx_wp_video_stop,
69768 - .dump_wrapper = ti_hdmi_4xxx_wp_dump,
69769 - .dump_core = ti_hdmi_4xxx_core_dump,
69770 - .dump_pll = ti_hdmi_4xxx_pll_dump,
69771 - .dump_phy = ti_hdmi_4xxx_phy_dump,
69772 -#if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO)
69773 - .audio_enable = ti_hdmi_4xxx_wp_audio_enable,
69774 - .audio_disable = ti_hdmi_4xxx_wp_audio_disable,
69775 - .audio_start = ti_hdmi_4xxx_audio_start,
69776 - .audio_stop = ti_hdmi_4xxx_audio_stop,
69777 - .audio_config = ti_hdmi_4xxx_audio_config,
69778 - .audio_get_dma_port = ti_hdmi_4xxx_audio_get_dma_port,
69779 -#endif
69780 -
69781 -};
69782 +/* DRA DSS Features */
69783 +static const struct omap_dss_features dra7xx_dss_features = {
69784 + .reg_fields = omap5_dss_reg_fields,
69785 + .num_reg_fields = ARRAY_SIZE(omap5_dss_reg_fields),
69786
69787 -void dss_init_hdmi_ip_ops(struct hdmi_ip_data *ip_data,
69788 - enum omapdss_version version)
69789 -{
69790 - switch (version) {
69791 - case OMAPDSS_VER_OMAP4430_ES1:
69792 - case OMAPDSS_VER_OMAP4430_ES2:
69793 - case OMAPDSS_VER_OMAP4:
69794 - ip_data->ops = &omap4_hdmi_functions;
69795 - break;
69796 - default:
69797 - ip_data->ops = NULL;
69798 - }
69799 + .features = omap5_dss_feat_list,
69800 + .num_features = ARRAY_SIZE(omap5_dss_feat_list),
69801
69802 - WARN_ON(ip_data->ops == NULL);
69803 -}
69804 -#endif
69805 + .num_mgrs = 4,
69806 + .num_ovls = 4,
69807 + .supported_displays = dra7xx_dss_supported_displays,
69808 + .supported_outputs = dra7xx_dss_supported_outputs,
69809 + .supported_color_modes = omap4_dss_supported_color_modes,
69810 + .overlay_caps = omap4_dss_overlay_caps,
69811 + .clksrc_names = omap5_dss_clk_source_names,
69812 + .dss_params = omap5_dss_param_range,
69813 + .supported_rotation_types = OMAP_DSS_ROT_DMA | OMAP_DSS_ROT_TILER,
69814 + .buffer_size_unit = 16,
69815 + .burst_size_unit = 16,
69816 +};
69817
69818 /* Functions returning values related to a DSS feature */
69819 int dss_feat_get_num_mgrs(void)
69820 @@ -967,10 +1036,18 @@ void dss_features_init(enum omapdss_vers
69821 omap_current_dss_features = &omap5_dss_features;
69822 break;
69823
69824 + case OMAPDSS_VER_DRA7xx:
69825 + omap_current_dss_features = &dra7xx_dss_features;
69826 + break;
69827 +
69828 case OMAPDSS_VER_AM35xx:
69829 omap_current_dss_features = &am35xx_dss_features;
69830 break;
69831
69832 + case OMAPDSS_VER_AM43xx:
69833 + omap_current_dss_features = &am43xx_dss_features;
69834 + break;
69835 +
69836 default:
69837 DSSWARN("Unsupported OMAP version");
69838 break;
69839 --- a/drivers/video/omap2/dss/dss_features.h
69840 +++ b/drivers/video/omap2/dss/dss_features.h
69841 @@ -20,10 +20,6 @@
69842 #ifndef __OMAP2_DSS_FEATURES_H
69843 #define __OMAP2_DSS_FEATURES_H
69844
69845 -#if defined(CONFIG_OMAP4_DSS_HDMI)
69846 -#include "ti_hdmi.h"
69847 -#endif
69848 -
69849 #define MAX_DSS_MANAGERS 4
69850 #define MAX_DSS_OVERLAYS 4
69851 #define MAX_DSS_LCD_MANAGERS 3
69852 @@ -117,8 +113,4 @@ bool dss_feat_rotation_type_supported(en
69853 bool dss_has_feature(enum dss_feat_id id);
69854 void dss_feat_get_reg_field(enum dss_feat_reg_field id, u8 *start, u8 *end);
69855 void dss_features_init(enum omapdss_version version);
69856 -#if defined(CONFIG_OMAP4_DSS_HDMI)
69857 -void dss_init_hdmi_ip_ops(struct hdmi_ip_data *ip_data,
69858 - enum omapdss_version version);
69859 -#endif
69860 #endif
69861 --- a/drivers/video/omap2/dss/dss.h
69862 +++ b/drivers/video/omap2/dss/dss.h
69863 @@ -100,6 +100,13 @@ enum dss_writeback_channel {
69864 DSS_WB_LCD3_MGR = 7,
69865 };
69866
69867 +enum dss_dpll {
69868 + DSS_DPLL_VIDEO1 = 0,
69869 + DSS_DPLL_VIDEO2,
69870 + DSS_DPLL_HDMI,
69871 + DSS_DPLL_NONE,
69872 +};
69873 +
69874 struct dss_clock_info {
69875 /* rates that we get with dividers below */
69876 unsigned long fck;
69877 @@ -139,6 +146,12 @@ struct dsi_clock_info {
69878 u16 lp_clk_div;
69879 };
69880
69881 +struct dss_dpll_cinfo {
69882 + unsigned long fint, clkin, clkout, hsdiv_clk;
69883 +
69884 + u16 regm, regn, regm_hsdiv;
69885 +};
69886 +
69887 struct reg_field {
69888 u16 reg;
69889 u8 high;
69890 @@ -223,9 +236,10 @@ int dss_init_platform_driver(void) __ini
69891 void dss_uninit_platform_driver(void);
69892
69893 unsigned long dss_get_dispc_clk_rate(void);
69894 -int dss_dpi_select_source(enum omap_channel channel);
69895 +int dss_dpi_select_source(int module_id, enum omap_channel channel);
69896 void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select);
69897 enum dss_hdmi_venc_clk_source_select dss_get_hdmi_venc_clk_source(void);
69898 +void dss_use_dpll_lcd(enum omap_channel channel, bool use_dpll);
69899 const char *dss_get_generic_clk_source_name(enum omap_dss_clk_source clk_src);
69900 void dss_dump_clocks(struct seq_file *s);
69901
69902 @@ -372,6 +386,10 @@ static inline bool dsi_pll_calc(struct p
69903 int dpi_init_platform_driver(void) __init;
69904 void dpi_uninit_platform_driver(void) __exit;
69905
69906 +/* DRA7x DPI */
69907 +int dra7xx_dpi_init_platform_driver(void) __init;
69908 +void dra7xx_dpi_uninit_platform_driver(void) __exit;
69909 +
69910 /* DISPC */
69911 int dispc_init_platform_driver(void) __init;
69912 void dispc_uninit_platform_driver(void) __exit;
69913 @@ -398,12 +416,6 @@ unsigned long dispc_fclk_rate(void);
69914 int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
69915 struct dispc_clock_info *cinfo);
69916
69917 -
69918 -void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high);
69919 -void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
69920 - u32 *fifo_low, u32 *fifo_high, bool use_fifomerge,
69921 - bool manual_update);
69922 -
69923 unsigned long dispc_mgr_lclk_rate(enum omap_channel channel);
69924 unsigned long dispc_mgr_pclk_rate(enum omap_channel channel);
69925 unsigned long dispc_core_clk_rate(void);
69926 @@ -427,8 +439,11 @@ int venc_init_platform_driver(void) __in
69927 void venc_uninit_platform_driver(void) __exit;
69928
69929 /* HDMI */
69930 -int hdmi_init_platform_driver(void) __init;
69931 -void hdmi_uninit_platform_driver(void) __exit;
69932 +int hdmi4_init_platform_driver(void) __init;
69933 +void hdmi4_uninit_platform_driver(void) __exit;
69934 +
69935 +int hdmi5_init_platform_driver(void) __init;
69936 +void hdmi5_uninit_platform_driver(void) __exit;
69937
69938 /* RFBI */
69939 int rfbi_init_platform_driver(void) __init;
69940 @@ -446,4 +461,27 @@ static inline void dss_collect_irq_stats
69941 }
69942 #endif
69943
69944 +typedef bool (*dss_dpll_calc_func)(int regn, int regm, unsigned long fint,
69945 + unsigned long pll, void *data);
69946 +typedef bool (*dss_dpll_hsdiv_calc_func)(int regm_dispc, unsigned long dispc,
69947 + void *data);
69948 +bool dss_dpll_disabled(enum dss_dpll dpll);
69949 +unsigned long dpll_get_clkin(enum dss_dpll dpll);
69950 +bool dss_dpll_calc(enum dss_dpll dpll, unsigned long clkin,
69951 + unsigned long pll_min, unsigned long pll_max,
69952 + dss_dpll_calc_func func, void *data);
69953 +bool dss_dpll_hsdiv_calc(enum dss_dpll dpll, unsigned long pll,
69954 + unsigned long out_min, dss_dpll_hsdiv_calc_func func,
69955 + void *data);
69956 +int dss_dpll_set_clock_div(enum dss_dpll dpll, struct dss_dpll_cinfo *cinfo);
69957 +
69958 +void dss_dpll_enable_ctrl(enum dss_dpll dpll, bool enable);
69959 +int dss_dpll_activate(enum dss_dpll dpll);
69960 +void dss_dpll_set_control_mux(enum omap_channel channel, enum dss_dpll dpll);
69961 +void dss_dpll_disable(enum dss_dpll dpll);
69962 +int dss_dpll_init_regulator(enum dss_dpll dpll);
69963 +int dss_dpll_configure(struct platform_device *pdev);
69964 +int dss_dpll_configure_ctrl(void);
69965 +void dss_dpll_unconfigure_ctrl(void);
69966 +
69967 #endif
69968 --- /dev/null
69969 +++ b/drivers/video/omap2/dss/hdmi4.c
69970 @@ -0,0 +1,761 @@
69971 +/*
69972 + * HDMI interface DSS driver for TI's OMAP4 family of SoCs.
69973 + * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
69974 + * Authors: Yong Zhi
69975 + * Mythri pk <mythripk@ti.com>
69976 + *
69977 + * This program is free software; you can redistribute it and/or modify it
69978 + * under the terms of the GNU General Public License version 2 as published by
69979 + * the Free Software Foundation.
69980 + *
69981 + * This program is distributed in the hope that it will be useful, but WITHOUT
69982 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
69983 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
69984 + * more details.
69985 + *
69986 + * You should have received a copy of the GNU General Public License along with
69987 + * this program. If not, see <http://www.gnu.org/licenses/>.
69988 + */
69989 +
69990 +#define DSS_SUBSYS_NAME "HDMI"
69991 +
69992 +#include <linux/kernel.h>
69993 +#include <linux/module.h>
69994 +#include <linux/err.h>
69995 +#include <linux/io.h>
69996 +#include <linux/interrupt.h>
69997 +#include <linux/mutex.h>
69998 +#include <linux/delay.h>
69999 +#include <linux/string.h>
70000 +#include <linux/platform_device.h>
70001 +#include <linux/pm_runtime.h>
70002 +#include <linux/clk.h>
70003 +#include <linux/gpio.h>
70004 +#include <linux/regulator/consumer.h>
70005 +#include <video/omapdss.h>
70006 +
70007 +#include "hdmi4_core.h"
70008 +#include "dss.h"
70009 +#include "dss_features.h"
70010 +
70011 +static struct {
70012 + struct mutex lock;
70013 + struct platform_device *pdev;
70014 +
70015 + struct hdmi_wp_data wp;
70016 + struct hdmi_pll_data pll;
70017 + struct hdmi_phy_data phy;
70018 + struct hdmi_core_data core;
70019 +
70020 + struct hdmi_config cfg;
70021 +
70022 + struct clk *sys_clk;
70023 + struct regulator *vdda_hdmi_dac_reg;
70024 +
70025 + bool core_enabled;
70026 +
70027 + struct omap_dss_device output;
70028 +} hdmi;
70029 +
70030 +static int hdmi_runtime_get(void)
70031 +{
70032 + int r;
70033 +
70034 + DSSDBG("hdmi_runtime_get\n");
70035 +
70036 + r = pm_runtime_get_sync(&hdmi.pdev->dev);
70037 + WARN_ON(r < 0);
70038 + if (r < 0)
70039 + return r;
70040 +
70041 + return 0;
70042 +}
70043 +
70044 +static void hdmi_runtime_put(void)
70045 +{
70046 + int r;
70047 +
70048 + DSSDBG("hdmi_runtime_put\n");
70049 +
70050 + r = pm_runtime_put_sync(&hdmi.pdev->dev);
70051 + WARN_ON(r < 0 && r != -ENOSYS);
70052 +}
70053 +
70054 +static irqreturn_t hdmi_irq_handler(int irq, void *data)
70055 +{
70056 + struct hdmi_wp_data *wp = data;
70057 + u32 irqstatus;
70058 +
70059 + irqstatus = hdmi_wp_get_irqstatus(wp);
70060 + hdmi_wp_set_irqstatus(wp, irqstatus);
70061 +
70062 + if ((irqstatus & HDMI_IRQ_LINK_CONNECT) &&
70063 + irqstatus & HDMI_IRQ_LINK_DISCONNECT) {
70064 + /*
70065 + * If we get both connect and disconnect interrupts at the same
70066 + * time, turn off the PHY, clear interrupts, and restart, which
70067 + * raises connect interrupt if a cable is connected, or nothing
70068 + * if cable is not connected.
70069 + */
70070 + hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_OFF);
70071 +
70072 + hdmi_wp_set_irqstatus(wp, HDMI_IRQ_LINK_CONNECT |
70073 + HDMI_IRQ_LINK_DISCONNECT);
70074 +
70075 + hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON);
70076 + } else if (irqstatus & HDMI_IRQ_LINK_CONNECT) {
70077 + hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_TXON);
70078 + } else if (irqstatus & HDMI_IRQ_LINK_DISCONNECT) {
70079 + hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON);
70080 + }
70081 +
70082 + return IRQ_HANDLED;
70083 +}
70084 +
70085 +static int hdmi_init_regulator(void)
70086 +{
70087 + int r;
70088 + struct regulator *reg;
70089 +
70090 + if (hdmi.vdda_hdmi_dac_reg != NULL)
70091 + return 0;
70092 +
70093 + reg = devm_regulator_get(&hdmi.pdev->dev, "vdda_hdmi_dac");
70094 + if (IS_ERR(reg)) {
70095 + DSSERR("can't get VDDA_HDMI_DAC regulator\n");
70096 + return PTR_ERR(reg);
70097 + }
70098 +
70099 + r = regulator_set_voltage(reg, 1800000, 1980000);
70100 + if (r)
70101 + DSSWARN("can't set the regulator voltage");
70102 +
70103 + hdmi.vdda_hdmi_dac_reg = reg;
70104 +
70105 + return 0;
70106 +}
70107 +
70108 +static int hdmi_power_on_core(struct omap_dss_device *dssdev)
70109 +{
70110 + int r;
70111 +
70112 + r = regulator_enable(hdmi.vdda_hdmi_dac_reg);
70113 + if (r)
70114 + return r;
70115 +
70116 + r = hdmi_runtime_get();
70117 + if (r)
70118 + goto err_runtime_get;
70119 +
70120 + /* Make selection of HDMI in DSS */
70121 + dss_select_hdmi_venc_clk_source(DSS_HDMI_M_PCLK);
70122 +
70123 + hdmi.core_enabled = true;
70124 +
70125 + return 0;
70126 +
70127 +err_runtime_get:
70128 + regulator_disable(hdmi.vdda_hdmi_dac_reg);
70129 +
70130 + return r;
70131 +}
70132 +
70133 +static void hdmi_power_off_core(struct omap_dss_device *dssdev)
70134 +{
70135 + hdmi.core_enabled = false;
70136 +
70137 + hdmi_runtime_put();
70138 + regulator_disable(hdmi.vdda_hdmi_dac_reg);
70139 +}
70140 +
70141 +static int hdmi_power_on_full(struct omap_dss_device *dssdev)
70142 +{
70143 + int r;
70144 + struct omap_video_timings *p;
70145 + struct omap_overlay_manager *mgr = hdmi.output.manager;
70146 + unsigned long phy;
70147 + struct hdmi_wp_data *wp = &hdmi.wp;
70148 +
70149 + r = hdmi_power_on_core(dssdev);
70150 + if (r)
70151 + return r;
70152 +
70153 + /* disable and clear irqs */
70154 + hdmi_wp_clear_irqenable(wp, 0xffffffff);
70155 + hdmi_wp_set_irqstatus(wp, 0xffffffff);
70156 +
70157 + p = &hdmi.cfg.timings;
70158 +
70159 + DSSDBG("hdmi_power_on x_res= %d y_res = %d\n", p->x_res, p->y_res);
70160 +
70161 + phy = p->pixel_clock;
70162 +
70163 + hdmi_pll_compute(&hdmi.pll, clk_get_rate(hdmi.sys_clk), phy);
70164 +
70165 + /* config the PLL and PHY hdmi_set_pll_pwrfirst */
70166 + r = hdmi_pll_enable(&hdmi.pll, &hdmi.wp);
70167 + if (r) {
70168 + DSSDBG("Failed to lock PLL\n");
70169 + goto err_pll_enable;
70170 + }
70171 +
70172 + r = hdmi_phy_configure(&hdmi.phy, &hdmi.cfg);
70173 + if (r) {
70174 + DSSDBG("Failed to configure PHY\n");
70175 + goto err_phy_cfg;
70176 + }
70177 +
70178 + r = hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON);
70179 + if (r)
70180 + goto err_phy_pwr;
70181 +
70182 + hdmi4_configure(&hdmi.core, &hdmi.wp, &hdmi.cfg);
70183 +
70184 + /* bypass TV gamma table */
70185 + dispc_enable_gamma_table(0);
70186 +
70187 + /* tv size */
70188 + dss_mgr_set_timings(mgr, p);
70189 +
70190 + r = hdmi_wp_video_start(&hdmi.wp);
70191 + if (r)
70192 + goto err_vid_enable;
70193 +
70194 + r = dss_mgr_enable(mgr);
70195 + if (r)
70196 + goto err_mgr_enable;
70197 +
70198 + hdmi_wp_set_irqenable(wp,
70199 + HDMI_IRQ_LINK_CONNECT | HDMI_IRQ_LINK_DISCONNECT);
70200 +
70201 + return 0;
70202 +
70203 +err_mgr_enable:
70204 + hdmi_wp_video_stop(&hdmi.wp);
70205 +err_vid_enable:
70206 +err_phy_cfg:
70207 + hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_OFF);
70208 +err_phy_pwr:
70209 + hdmi_pll_disable(&hdmi.pll, &hdmi.wp);
70210 +err_pll_enable:
70211 + hdmi_power_off_core(dssdev);
70212 + return -EIO;
70213 +}
70214 +
70215 +static void hdmi_power_off_full(struct omap_dss_device *dssdev)
70216 +{
70217 + struct omap_overlay_manager *mgr = hdmi.output.manager;
70218 +
70219 + hdmi_wp_clear_irqenable(&hdmi.wp, 0xffffffff);
70220 +
70221 + dss_mgr_disable(mgr);
70222 +
70223 + hdmi_wp_video_stop(&hdmi.wp);
70224 +
70225 + hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_OFF);
70226 +
70227 + hdmi_pll_disable(&hdmi.pll, &hdmi.wp);
70228 +
70229 + hdmi_power_off_core(dssdev);
70230 +}
70231 +
70232 +static int hdmi_display_check_timing(struct omap_dss_device *dssdev,
70233 + struct omap_video_timings *timings)
70234 +{
70235 + struct hdmi_cm cm;
70236 +
70237 + cm = hdmi_get_code(timings);
70238 + if (cm.code == -1)
70239 + return -EINVAL;
70240 +
70241 + return 0;
70242 +
70243 +}
70244 +
70245 +static void hdmi_display_set_timing(struct omap_dss_device *dssdev,
70246 + struct omap_video_timings *timings)
70247 +{
70248 + struct hdmi_cm cm;
70249 + const struct hdmi_config *t;
70250 +
70251 + mutex_lock(&hdmi.lock);
70252 +
70253 + cm = hdmi_get_code(timings);
70254 + hdmi.cfg.cm = cm;
70255 +
70256 + t = hdmi_get_timings(cm.mode, cm.code);
70257 + if (t != NULL) {
70258 + hdmi.cfg = *t;
70259 +
70260 + dispc_set_tv_pclk(t->timings.pixel_clock * 1000);
70261 + }
70262 +
70263 + mutex_unlock(&hdmi.lock);
70264 +}
70265 +
70266 +static void hdmi_display_get_timings(struct omap_dss_device *dssdev,
70267 + struct omap_video_timings *timings)
70268 +{
70269 + const struct hdmi_config *cfg;
70270 + struct hdmi_cm cm = hdmi.cfg.cm;
70271 +
70272 + cfg = hdmi_get_timings(cm.mode, cm.code);
70273 + if (cfg == NULL)
70274 + cfg = hdmi_default_timing();
70275 +
70276 + memcpy(timings, &cfg->timings, sizeof(cfg->timings));
70277 +}
70278 +
70279 +static void hdmi_dump_regs(struct seq_file *s)
70280 +{
70281 + mutex_lock(&hdmi.lock);
70282 +
70283 + if (hdmi_runtime_get()) {
70284 + mutex_unlock(&hdmi.lock);
70285 + return;
70286 + }
70287 +
70288 + hdmi_wp_dump(&hdmi.wp, s);
70289 + hdmi_pll_dump(&hdmi.pll, s);
70290 + hdmi_phy_dump(&hdmi.phy, s);
70291 + hdmi4_core_dump(&hdmi.core, s);
70292 +
70293 + hdmi_runtime_put();
70294 + mutex_unlock(&hdmi.lock);
70295 +}
70296 +
70297 +static int read_edid(u8 *buf, int len)
70298 +{
70299 + int r;
70300 +
70301 + mutex_lock(&hdmi.lock);
70302 +
70303 + r = hdmi_runtime_get();
70304 + BUG_ON(r);
70305 +
70306 + r = hdmi4_read_edid(&hdmi.core, buf, len);
70307 +
70308 + hdmi_runtime_put();
70309 + mutex_unlock(&hdmi.lock);
70310 +
70311 + return r;
70312 +}
70313 +
70314 +static int hdmi_display_enable(struct omap_dss_device *dssdev)
70315 +{
70316 + struct omap_dss_device *out = &hdmi.output;
70317 + int r = 0;
70318 +
70319 + DSSDBG("ENTER hdmi_display_enable\n");
70320 +
70321 + mutex_lock(&hdmi.lock);
70322 +
70323 + if (out == NULL || out->manager == NULL) {
70324 + DSSERR("failed to enable display: no output/manager\n");
70325 + r = -ENODEV;
70326 + goto err0;
70327 + }
70328 +
70329 + r = hdmi_power_on_full(dssdev);
70330 + if (r) {
70331 + DSSERR("failed to power on device\n");
70332 + goto err0;
70333 + }
70334 +
70335 + mutex_unlock(&hdmi.lock);
70336 + return 0;
70337 +
70338 +err0:
70339 + mutex_unlock(&hdmi.lock);
70340 + return r;
70341 +}
70342 +
70343 +static void hdmi_display_disable(struct omap_dss_device *dssdev)
70344 +{
70345 + DSSDBG("Enter hdmi_display_disable\n");
70346 +
70347 + mutex_lock(&hdmi.lock);
70348 +
70349 + hdmi_power_off_full(dssdev);
70350 +
70351 + mutex_unlock(&hdmi.lock);
70352 +}
70353 +
70354 +static int hdmi_core_enable(struct omap_dss_device *dssdev)
70355 +{
70356 + int r = 0;
70357 +
70358 + DSSDBG("ENTER omapdss_hdmi_core_enable\n");
70359 +
70360 + mutex_lock(&hdmi.lock);
70361 +
70362 + r = hdmi_power_on_core(dssdev);
70363 + if (r) {
70364 + DSSERR("failed to power on device\n");
70365 + goto err0;
70366 + }
70367 +
70368 + mutex_unlock(&hdmi.lock);
70369 + return 0;
70370 +
70371 +err0:
70372 + mutex_unlock(&hdmi.lock);
70373 + return r;
70374 +}
70375 +
70376 +static void hdmi_core_disable(struct omap_dss_device *dssdev)
70377 +{
70378 + DSSDBG("Enter omapdss_hdmi_core_disable\n");
70379 +
70380 + mutex_lock(&hdmi.lock);
70381 +
70382 + hdmi_power_off_core(dssdev);
70383 +
70384 + mutex_unlock(&hdmi.lock);
70385 +}
70386 +
70387 +static int hdmi_get_clocks(struct platform_device *pdev)
70388 +{
70389 + struct clk *clk;
70390 +
70391 + clk = devm_clk_get(&pdev->dev, "sys_clk");
70392 + if (IS_ERR(clk)) {
70393 + DSSERR("can't get sys_clk\n");
70394 + return PTR_ERR(clk);
70395 + }
70396 +
70397 + hdmi.sys_clk = clk;
70398 +
70399 + return 0;
70400 +}
70401 +
70402 +static int hdmi_connect(struct omap_dss_device *dssdev,
70403 + struct omap_dss_device *dst)
70404 +{
70405 + struct omap_overlay_manager *mgr;
70406 + int r;
70407 +
70408 + r = hdmi_init_regulator();
70409 + if (r)
70410 + return r;
70411 +
70412 + mgr = omap_dss_get_overlay_manager(dssdev->dispc_channel);
70413 + if (!mgr)
70414 + return -ENODEV;
70415 +
70416 + r = dss_mgr_connect(mgr, dssdev);
70417 + if (r)
70418 + return r;
70419 +
70420 + r = omapdss_output_set_device(dssdev, dst);
70421 + if (r) {
70422 + DSSERR("failed to connect output to new device: %s\n",
70423 + dst->name);
70424 + dss_mgr_disconnect(mgr, dssdev);
70425 + return r;
70426 + }
70427 +
70428 + return 0;
70429 +}
70430 +
70431 +static void hdmi_disconnect(struct omap_dss_device *dssdev,
70432 + struct omap_dss_device *dst)
70433 +{
70434 + WARN_ON(dst != dssdev->dst);
70435 +
70436 + if (dst != dssdev->dst)
70437 + return;
70438 +
70439 + omapdss_output_unset_device(dssdev);
70440 +
70441 + if (dssdev->manager)
70442 + dss_mgr_disconnect(dssdev->manager, dssdev);
70443 +}
70444 +
70445 +static int hdmi_read_edid(struct omap_dss_device *dssdev,
70446 + u8 *edid, int len)
70447 +{
70448 + bool need_enable;
70449 + int r;
70450 +
70451 + need_enable = hdmi.core_enabled == false;
70452 +
70453 + if (need_enable) {
70454 + r = hdmi_core_enable(dssdev);
70455 + if (r)
70456 + return r;
70457 + }
70458 +
70459 + r = read_edid(edid, len);
70460 +
70461 + if (need_enable)
70462 + hdmi_core_disable(dssdev);
70463 +
70464 + return r;
70465 +}
70466 +
70467 +#if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO)
70468 +static int hdmi_audio_enable(struct omap_dss_device *dssdev)
70469 +{
70470 + int r;
70471 +
70472 + mutex_lock(&hdmi.lock);
70473 +
70474 + if (!hdmi_mode_has_audio(hdmi.cfg.cm.mode)) {
70475 + r = -EPERM;
70476 + goto err;
70477 + }
70478 +
70479 + r = hdmi_wp_audio_enable(&hdmi.wp, true);
70480 + if (r)
70481 + goto err;
70482 +
70483 + mutex_unlock(&hdmi.lock);
70484 + return 0;
70485 +
70486 +err:
70487 + mutex_unlock(&hdmi.lock);
70488 + return r;
70489 +}
70490 +
70491 +static void hdmi_audio_disable(struct omap_dss_device *dssdev)
70492 +{
70493 + hdmi_wp_audio_enable(&hdmi.wp, false);
70494 +}
70495 +
70496 +static int hdmi_audio_start(struct omap_dss_device *dssdev)
70497 +{
70498 + return hdmi4_audio_start(&hdmi.core, &hdmi.wp);
70499 +}
70500 +
70501 +static void hdmi_audio_stop(struct omap_dss_device *dssdev)
70502 +{
70503 + hdmi4_audio_stop(&hdmi.core, &hdmi.wp);
70504 +}
70505 +
70506 +static bool hdmi_audio_supported(struct omap_dss_device *dssdev)
70507 +{
70508 + bool r;
70509 +
70510 + mutex_lock(&hdmi.lock);
70511 +
70512 + r = hdmi_mode_has_audio(hdmi.cfg.cm.mode);
70513 +
70514 + mutex_unlock(&hdmi.lock);
70515 + return r;
70516 +}
70517 +
70518 +static int hdmi_audio_config(struct omap_dss_device *dssdev,
70519 + struct omap_dss_audio *audio)
70520 +{
70521 + int r;
70522 + u32 pclk = hdmi.cfg.timings.pixel_clock;
70523 +
70524 + mutex_lock(&hdmi.lock);
70525 +
70526 + if (!hdmi_mode_has_audio(hdmi.cfg.cm.mode)) {
70527 + r = -EPERM;
70528 + goto err;
70529 + }
70530 +
70531 + r = hdmi4_audio_config(&hdmi.core, &hdmi.wp, audio, pclk);
70532 + if (r)
70533 + goto err;
70534 +
70535 + mutex_unlock(&hdmi.lock);
70536 + return 0;
70537 +
70538 +err:
70539 + mutex_unlock(&hdmi.lock);
70540 + return r;
70541 +}
70542 +#else
70543 +static int hdmi_audio_enable(struct omap_dss_device *dssdev)
70544 +{
70545 + return -EPERM;
70546 +}
70547 +
70548 +static void hdmi_audio_disable(struct omap_dss_device *dssdev)
70549 +{
70550 +}
70551 +
70552 +static int hdmi_audio_start(struct omap_dss_device *dssdev)
70553 +{
70554 + return -EPERM;
70555 +}
70556 +
70557 +static void hdmi_audio_stop(struct omap_dss_device *dssdev)
70558 +{
70559 +}
70560 +
70561 +static bool hdmi_audio_supported(struct omap_dss_device *dssdev)
70562 +{
70563 + return false;
70564 +}
70565 +
70566 +static int hdmi_audio_config(struct omap_dss_device *dssdev,
70567 + struct omap_dss_audio *audio)
70568 +{
70569 + return -EPERM;
70570 +}
70571 +#endif
70572 +
70573 +static const struct omapdss_hdmi_ops hdmi_ops = {
70574 + .connect = hdmi_connect,
70575 + .disconnect = hdmi_disconnect,
70576 +
70577 + .enable = hdmi_display_enable,
70578 + .disable = hdmi_display_disable,
70579 +
70580 + .check_timings = hdmi_display_check_timing,
70581 + .set_timings = hdmi_display_set_timing,
70582 + .get_timings = hdmi_display_get_timings,
70583 +
70584 + .read_edid = hdmi_read_edid,
70585 +
70586 + .audio_enable = hdmi_audio_enable,
70587 + .audio_disable = hdmi_audio_disable,
70588 + .audio_start = hdmi_audio_start,
70589 + .audio_stop = hdmi_audio_stop,
70590 + .audio_supported = hdmi_audio_supported,
70591 + .audio_config = hdmi_audio_config,
70592 +};
70593 +
70594 +static void hdmi_init_output(struct platform_device *pdev)
70595 +{
70596 + struct omap_dss_device *out = &hdmi.output;
70597 +
70598 + out->dev = &pdev->dev;
70599 + out->id = OMAP_DSS_OUTPUT_HDMI;
70600 + out->output_type = OMAP_DISPLAY_TYPE_HDMI;
70601 + out->name = "hdmi.0";
70602 + out->dispc_channel = OMAP_DSS_CHANNEL_DIGIT;
70603 + out->ops.hdmi = &hdmi_ops;
70604 + out->owner = THIS_MODULE;
70605 +
70606 + omapdss_register_output(out);
70607 +}
70608 +
70609 +static void __exit hdmi_uninit_output(struct platform_device *pdev)
70610 +{
70611 + struct omap_dss_device *out = &hdmi.output;
70612 +
70613 + omapdss_unregister_output(out);
70614 +}
70615 +
70616 +/* HDMI HW IP initialisation */
70617 +static int omapdss_hdmihw_probe(struct platform_device *pdev)
70618 +{
70619 + int r;
70620 + int irq;
70621 +
70622 + hdmi.pdev = pdev;
70623 +
70624 + mutex_init(&hdmi.lock);
70625 +
70626 + r = hdmi_wp_init(pdev, &hdmi.wp);
70627 + if (r)
70628 + return r;
70629 +
70630 + r = hdmi_pll_init(pdev, &hdmi.pll);
70631 + if (r)
70632 + return r;
70633 +
70634 + r = hdmi_phy_init(pdev, &hdmi.phy);
70635 + if (r)
70636 + return r;
70637 +
70638 + r = hdmi4_core_init(pdev, &hdmi.core);
70639 + if (r)
70640 + return r;
70641 +
70642 + r = hdmi_get_clocks(pdev);
70643 + if (r) {
70644 + DSSERR("can't get clocks\n");
70645 + return r;
70646 + }
70647 +
70648 + irq = platform_get_irq(pdev, 0);
70649 + if (irq < 0) {
70650 + DSSERR("platform_get_irq failed\n");
70651 + return -ENODEV;
70652 + }
70653 +
70654 + r = devm_request_threaded_irq(&pdev->dev, irq,
70655 + NULL, hdmi_irq_handler,
70656 + IRQF_ONESHOT, "OMAP HDMI", &hdmi.wp);
70657 + if (r) {
70658 + DSSERR("HDMI IRQ request failed\n");
70659 + return r;
70660 + }
70661 +
70662 + pm_runtime_enable(&pdev->dev);
70663 +
70664 + hdmi_init_output(pdev);
70665 +
70666 + dss_debugfs_create_file("hdmi", hdmi_dump_regs);
70667 +
70668 + return 0;
70669 +}
70670 +
70671 +static int __exit omapdss_hdmihw_remove(struct platform_device *pdev)
70672 +{
70673 + hdmi_uninit_output(pdev);
70674 +
70675 + pm_runtime_disable(&pdev->dev);
70676 +
70677 + return 0;
70678 +}
70679 +
70680 +static int hdmi_runtime_suspend(struct device *dev)
70681 +{
70682 + clk_disable_unprepare(hdmi.sys_clk);
70683 +
70684 + dispc_runtime_put();
70685 +
70686 + return 0;
70687 +}
70688 +
70689 +static int hdmi_runtime_resume(struct device *dev)
70690 +{
70691 + int r;
70692 +
70693 + r = dispc_runtime_get();
70694 + if (r < 0)
70695 + return r;
70696 +
70697 + clk_prepare_enable(hdmi.sys_clk);
70698 +
70699 + return 0;
70700 +}
70701 +
70702 +static const struct dev_pm_ops hdmi_pm_ops = {
70703 + .runtime_suspend = hdmi_runtime_suspend,
70704 + .runtime_resume = hdmi_runtime_resume,
70705 +};
70706 +
70707 +static const struct of_device_id hdmi_of_match[] = {
70708 + { .compatible = "ti,omap4-hdmi", },
70709 + {},
70710 +};
70711 +
70712 +static struct platform_driver omapdss_hdmihw_driver = {
70713 + .probe = omapdss_hdmihw_probe,
70714 + .remove = __exit_p(omapdss_hdmihw_remove),
70715 + .driver = {
70716 + .name = "omapdss_hdmi",
70717 + .owner = THIS_MODULE,
70718 + .pm = &hdmi_pm_ops,
70719 + .of_match_table = hdmi_of_match,
70720 + },
70721 +};
70722 +
70723 +int __init hdmi4_init_platform_driver(void)
70724 +{
70725 + return platform_driver_register(&omapdss_hdmihw_driver);
70726 +}
70727 +
70728 +void __exit hdmi4_uninit_platform_driver(void)
70729 +{
70730 + platform_driver_unregister(&omapdss_hdmihw_driver);
70731 +}
70732 --- /dev/null
70733 +++ b/drivers/video/omap2/dss/hdmi4_core.c
70734 @@ -0,0 +1,1016 @@
70735 +/*
70736 + * ti_hdmi_4xxx_ip.c
70737 + *
70738 + * HDMI TI81xx, TI38xx, TI OMAP4 etc IP driver Library
70739 + * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
70740 + * Authors: Yong Zhi
70741 + * Mythri pk <mythripk@ti.com>
70742 + *
70743 + * This program is free software; you can redistribute it and/or modify it
70744 + * under the terms of the GNU General Public License version 2 as published by
70745 + * the Free Software Foundation.
70746 + *
70747 + * This program is distributed in the hope that it will be useful, but WITHOUT
70748 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
70749 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
70750 + * more details.
70751 + *
70752 + * You should have received a copy of the GNU General Public License along with
70753 + * this program. If not, see <http://www.gnu.org/licenses/>.
70754 + */
70755 +
70756 +#include <linux/kernel.h>
70757 +#include <linux/module.h>
70758 +#include <linux/err.h>
70759 +#include <linux/io.h>
70760 +#include <linux/interrupt.h>
70761 +#include <linux/mutex.h>
70762 +#include <linux/delay.h>
70763 +#include <linux/platform_device.h>
70764 +#include <linux/string.h>
70765 +#include <linux/seq_file.h>
70766 +#if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO)
70767 +#include <sound/asound.h>
70768 +#include <sound/asoundef.h>
70769 +#endif
70770 +
70771 +#include "hdmi4_core.h"
70772 +#include "dss_features.h"
70773 +
70774 +#define HDMI_CORE_AV 0x500
70775 +
70776 +static inline void __iomem *hdmi_av_base(struct hdmi_core_data *core)
70777 +{
70778 + return core->base + HDMI_CORE_AV;
70779 +}
70780 +
70781 +static int hdmi_core_ddc_init(struct hdmi_core_data *core)
70782 +{
70783 + void __iomem *base = core->base;
70784 +
70785 + /* Turn on CLK for DDC */
70786 + REG_FLD_MOD(base, HDMI_CORE_AV_DPD, 0x7, 2, 0);
70787 +
70788 + /* IN_PROG */
70789 + if (REG_GET(base, HDMI_CORE_DDC_STATUS, 4, 4) == 1) {
70790 + /* Abort transaction */
70791 + REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0xf, 3, 0);
70792 + /* IN_PROG */
70793 + if (hdmi_wait_for_bit_change(base, HDMI_CORE_DDC_STATUS,
70794 + 4, 4, 0) != 0) {
70795 + DSSERR("Timeout aborting DDC transaction\n");
70796 + return -ETIMEDOUT;
70797 + }
70798 + }
70799 +
70800 + /* Clk SCL Devices */
70801 + REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0xA, 3, 0);
70802 +
70803 + /* HDMI_CORE_DDC_STATUS_IN_PROG */
70804 + if (hdmi_wait_for_bit_change(base, HDMI_CORE_DDC_STATUS,
70805 + 4, 4, 0) != 0) {
70806 + DSSERR("Timeout starting SCL clock\n");
70807 + return -ETIMEDOUT;
70808 + }
70809 +
70810 + /* Clear FIFO */
70811 + REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0x9, 3, 0);
70812 +
70813 + /* HDMI_CORE_DDC_STATUS_IN_PROG */
70814 + if (hdmi_wait_for_bit_change(base, HDMI_CORE_DDC_STATUS,
70815 + 4, 4, 0) != 0) {
70816 + DSSERR("Timeout clearing DDC fifo\n");
70817 + return -ETIMEDOUT;
70818 + }
70819 +
70820 + return 0;
70821 +}
70822 +
70823 +static int hdmi_core_ddc_edid(struct hdmi_core_data *core,
70824 + u8 *pedid, int ext)
70825 +{
70826 + void __iomem *base = core->base;
70827 + u32 i;
70828 + char checksum;
70829 + u32 offset = 0;
70830 +
70831 + /* HDMI_CORE_DDC_STATUS_IN_PROG */
70832 + if (hdmi_wait_for_bit_change(base, HDMI_CORE_DDC_STATUS,
70833 + 4, 4, 0) != 0) {
70834 + DSSERR("Timeout waiting DDC to be ready\n");
70835 + return -ETIMEDOUT;
70836 + }
70837 +
70838 + if (ext % 2 != 0)
70839 + offset = 0x80;
70840 +
70841 + /* Load Segment Address Register */
70842 + REG_FLD_MOD(base, HDMI_CORE_DDC_SEGM, ext / 2, 7, 0);
70843 +
70844 + /* Load Slave Address Register */
70845 + REG_FLD_MOD(base, HDMI_CORE_DDC_ADDR, 0xA0 >> 1, 7, 1);
70846 +
70847 + /* Load Offset Address Register */
70848 + REG_FLD_MOD(base, HDMI_CORE_DDC_OFFSET, offset, 7, 0);
70849 +
70850 + /* Load Byte Count */
70851 + REG_FLD_MOD(base, HDMI_CORE_DDC_COUNT1, 0x80, 7, 0);
70852 + REG_FLD_MOD(base, HDMI_CORE_DDC_COUNT2, 0x0, 1, 0);
70853 +
70854 + /* Set DDC_CMD */
70855 + if (ext)
70856 + REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0x4, 3, 0);
70857 + else
70858 + REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0x2, 3, 0);
70859 +
70860 + /* HDMI_CORE_DDC_STATUS_BUS_LOW */
70861 + if (REG_GET(base, HDMI_CORE_DDC_STATUS, 6, 6) == 1) {
70862 + pr_err("I2C Bus Low?\n");
70863 + return -EIO;
70864 + }
70865 + /* HDMI_CORE_DDC_STATUS_NO_ACK */
70866 + if (REG_GET(base, HDMI_CORE_DDC_STATUS, 5, 5) == 1) {
70867 + pr_err("I2C No Ack\n");
70868 + return -EIO;
70869 + }
70870 +
70871 + for (i = 0; i < 0x80; ++i) {
70872 + int t;
70873 +
70874 + /* IN_PROG */
70875 + if (REG_GET(base, HDMI_CORE_DDC_STATUS, 4, 4) == 0) {
70876 + DSSERR("operation stopped when reading edid\n");
70877 + return -EIO;
70878 + }
70879 +
70880 + t = 0;
70881 + /* FIFO_EMPTY */
70882 + while (REG_GET(base, HDMI_CORE_DDC_STATUS, 2, 2) == 1) {
70883 + if (t++ > 10000) {
70884 + DSSERR("timeout reading edid\n");
70885 + return -ETIMEDOUT;
70886 + }
70887 + udelay(1);
70888 + }
70889 +
70890 + pedid[i] = REG_GET(base, HDMI_CORE_DDC_DATA, 7, 0);
70891 + }
70892 +
70893 + checksum = 0;
70894 + for (i = 0; i < 0x80; ++i)
70895 + checksum += pedid[i];
70896 +
70897 + if (checksum != 0) {
70898 + pr_err("E-EDID checksum failed!!\n");
70899 + return -EIO;
70900 + }
70901 +
70902 + return 0;
70903 +}
70904 +
70905 +int hdmi4_read_edid(struct hdmi_core_data *core, u8 *edid, int len)
70906 +{
70907 + int r, l;
70908 +
70909 + if (len < 128)
70910 + return -EINVAL;
70911 +
70912 + r = hdmi_core_ddc_init(core);
70913 + if (r)
70914 + return r;
70915 +
70916 + r = hdmi_core_ddc_edid(core, edid, 0);
70917 + if (r)
70918 + return r;
70919 +
70920 + l = 128;
70921 +
70922 + if (len >= 128 * 2 && edid[0x7e] > 0) {
70923 + r = hdmi_core_ddc_edid(core, edid + 0x80, 1);
70924 + if (r)
70925 + return r;
70926 + l += 128;
70927 + }
70928 +
70929 + return l;
70930 +}
70931 +
70932 +static void hdmi_core_init(struct hdmi_core_video_config *video_cfg,
70933 + struct hdmi_core_infoframe_avi *avi_cfg,
70934 + struct hdmi_core_packet_enable_repeat *repeat_cfg)
70935 +{
70936 + pr_debug("Enter hdmi_core_init\n");
70937 +
70938 + /* video core */
70939 + video_cfg->ip_bus_width = HDMI_INPUT_8BIT;
70940 + video_cfg->op_dither_truc = HDMI_OUTPUTTRUNCATION_8BIT;
70941 + video_cfg->deep_color_pkt = HDMI_DEEPCOLORPACKECTDISABLE;
70942 + video_cfg->pkt_mode = HDMI_PACKETMODERESERVEDVALUE;
70943 + video_cfg->hdmi_dvi = HDMI_DVI;
70944 + video_cfg->tclk_sel_clkmult = HDMI_FPLL10IDCK;
70945 +
70946 + /* info frame */
70947 + avi_cfg->db1_format = 0;
70948 + avi_cfg->db1_active_info = 0;
70949 + avi_cfg->db1_bar_info_dv = 0;
70950 + avi_cfg->db1_scan_info = 0;
70951 + avi_cfg->db2_colorimetry = 0;
70952 + avi_cfg->db2_aspect_ratio = 0;
70953 + avi_cfg->db2_active_fmt_ar = 0;
70954 + avi_cfg->db3_itc = 0;
70955 + avi_cfg->db3_ec = 0;
70956 + avi_cfg->db3_q_range = 0;
70957 + avi_cfg->db3_nup_scaling = 0;
70958 + avi_cfg->db4_videocode = 0;
70959 + avi_cfg->db5_pixel_repeat = 0;
70960 + avi_cfg->db6_7_line_eoftop = 0;
70961 + avi_cfg->db8_9_line_sofbottom = 0;
70962 + avi_cfg->db10_11_pixel_eofleft = 0;
70963 + avi_cfg->db12_13_pixel_sofright = 0;
70964 +
70965 + /* packet enable and repeat */
70966 + repeat_cfg->audio_pkt = 0;
70967 + repeat_cfg->audio_pkt_repeat = 0;
70968 + repeat_cfg->avi_infoframe = 0;
70969 + repeat_cfg->avi_infoframe_repeat = 0;
70970 + repeat_cfg->gen_cntrl_pkt = 0;
70971 + repeat_cfg->gen_cntrl_pkt_repeat = 0;
70972 + repeat_cfg->generic_pkt = 0;
70973 + repeat_cfg->generic_pkt_repeat = 0;
70974 +}
70975 +
70976 +static void hdmi_core_powerdown_disable(struct hdmi_core_data *core)
70977 +{
70978 + pr_debug("Enter hdmi_core_powerdown_disable\n");
70979 + REG_FLD_MOD(core->base, HDMI_CORE_SYS_SYS_CTRL1, 0x0, 0, 0);
70980 +}
70981 +
70982 +static void hdmi_core_swreset_release(struct hdmi_core_data *core)
70983 +{
70984 + pr_debug("Enter hdmi_core_swreset_release\n");
70985 + REG_FLD_MOD(core->base, HDMI_CORE_SYS_SRST, 0x0, 0, 0);
70986 +}
70987 +
70988 +static void hdmi_core_swreset_assert(struct hdmi_core_data *core)
70989 +{
70990 + pr_debug("Enter hdmi_core_swreset_assert\n");
70991 + REG_FLD_MOD(core->base, HDMI_CORE_SYS_SRST, 0x1, 0, 0);
70992 +}
70993 +
70994 +/* HDMI_CORE_VIDEO_CONFIG */
70995 +static void hdmi_core_video_config(struct hdmi_core_data *core,
70996 + struct hdmi_core_video_config *cfg)
70997 +{
70998 + u32 r = 0;
70999 + void __iomem *core_sys_base = core->base;
71000 + void __iomem *core_av_base = hdmi_av_base(core);
71001 +
71002 + /* sys_ctrl1 default configuration not tunable */
71003 + r = hdmi_read_reg(core_sys_base, HDMI_CORE_SYS_SYS_CTRL1);
71004 + r = FLD_MOD(r, HDMI_CORE_SYS_SYS_CTRL1_VEN_FOLLOWVSYNC, 5, 5);
71005 + r = FLD_MOD(r, HDMI_CORE_SYS_SYS_CTRL1_HEN_FOLLOWHSYNC, 4, 4);
71006 + r = FLD_MOD(r, HDMI_CORE_SYS_SYS_CTRL1_BSEL_24BITBUS, 2, 2);
71007 + r = FLD_MOD(r, HDMI_CORE_SYS_SYS_CTRL1_EDGE_RISINGEDGE, 1, 1);
71008 + hdmi_write_reg(core_sys_base, HDMI_CORE_SYS_SYS_CTRL1, r);
71009 +
71010 + REG_FLD_MOD(core_sys_base,
71011 + HDMI_CORE_SYS_VID_ACEN, cfg->ip_bus_width, 7, 6);
71012 +
71013 + /* Vid_Mode */
71014 + r = hdmi_read_reg(core_sys_base, HDMI_CORE_SYS_VID_MODE);
71015 +
71016 + /* dither truncation configuration */
71017 + if (cfg->op_dither_truc > HDMI_OUTPUTTRUNCATION_12BIT) {
71018 + r = FLD_MOD(r, cfg->op_dither_truc - 3, 7, 6);
71019 + r = FLD_MOD(r, 1, 5, 5);
71020 + } else {
71021 + r = FLD_MOD(r, cfg->op_dither_truc, 7, 6);
71022 + r = FLD_MOD(r, 0, 5, 5);
71023 + }
71024 + hdmi_write_reg(core_sys_base, HDMI_CORE_SYS_VID_MODE, r);
71025 +
71026 + /* HDMI_Ctrl */
71027 + r = hdmi_read_reg(core_av_base, HDMI_CORE_AV_HDMI_CTRL);
71028 + r = FLD_MOD(r, cfg->deep_color_pkt, 6, 6);
71029 + r = FLD_MOD(r, cfg->pkt_mode, 5, 3);
71030 + r = FLD_MOD(r, cfg->hdmi_dvi, 0, 0);
71031 + hdmi_write_reg(core_av_base, HDMI_CORE_AV_HDMI_CTRL, r);
71032 +
71033 + /* TMDS_CTRL */
71034 + REG_FLD_MOD(core_sys_base,
71035 + HDMI_CORE_SYS_TMDS_CTRL, cfg->tclk_sel_clkmult, 6, 5);
71036 +}
71037 +
71038 +static void hdmi_core_aux_infoframe_avi_config(struct hdmi_core_data *core)
71039 +{
71040 + u32 val;
71041 + char sum = 0, checksum = 0;
71042 + void __iomem *av_base = hdmi_av_base(core);
71043 + struct hdmi_core_infoframe_avi info_avi = core->avi_cfg;
71044 +
71045 + sum += 0x82 + 0x002 + 0x00D;
71046 + hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_TYPE, 0x082);
71047 + hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_VERS, 0x002);
71048 + hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_LEN, 0x00D);
71049 +
71050 + val = (info_avi.db1_format << 5) |
71051 + (info_avi.db1_active_info << 4) |
71052 + (info_avi.db1_bar_info_dv << 2) |
71053 + (info_avi.db1_scan_info);
71054 + hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(0), val);
71055 + sum += val;
71056 +
71057 + val = (info_avi.db2_colorimetry << 6) |
71058 + (info_avi.db2_aspect_ratio << 4) |
71059 + (info_avi.db2_active_fmt_ar);
71060 + hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(1), val);
71061 + sum += val;
71062 +
71063 + val = (info_avi.db3_itc << 7) |
71064 + (info_avi.db3_ec << 4) |
71065 + (info_avi.db3_q_range << 2) |
71066 + (info_avi.db3_nup_scaling);
71067 + hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(2), val);
71068 + sum += val;
71069 +
71070 + hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(3),
71071 + info_avi.db4_videocode);
71072 + sum += info_avi.db4_videocode;
71073 +
71074 + val = info_avi.db5_pixel_repeat;
71075 + hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(4), val);
71076 + sum += val;
71077 +
71078 + val = info_avi.db6_7_line_eoftop & 0x00FF;
71079 + hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(5), val);
71080 + sum += val;
71081 +
71082 + val = ((info_avi.db6_7_line_eoftop >> 8) & 0x00FF);
71083 + hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(6), val);
71084 + sum += val;
71085 +
71086 + val = info_avi.db8_9_line_sofbottom & 0x00FF;
71087 + hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(7), val);
71088 + sum += val;
71089 +
71090 + val = ((info_avi.db8_9_line_sofbottom >> 8) & 0x00FF);
71091 + hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(8), val);
71092 + sum += val;
71093 +
71094 + val = info_avi.db10_11_pixel_eofleft & 0x00FF;
71095 + hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(9), val);
71096 + sum += val;
71097 +
71098 + val = ((info_avi.db10_11_pixel_eofleft >> 8) & 0x00FF);
71099 + hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(10), val);
71100 + sum += val;
71101 +
71102 + val = info_avi.db12_13_pixel_sofright & 0x00FF;
71103 + hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(11), val);
71104 + sum += val;
71105 +
71106 + val = ((info_avi.db12_13_pixel_sofright >> 8) & 0x00FF);
71107 + hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(12), val);
71108 + sum += val;
71109 +
71110 + checksum = 0x100 - sum;
71111 + hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_CHSUM, checksum);
71112 +}
71113 +
71114 +static void hdmi_core_av_packet_config(struct hdmi_core_data *core,
71115 + struct hdmi_core_packet_enable_repeat repeat_cfg)
71116 +{
71117 + /* enable/repeat the infoframe */
71118 + hdmi_write_reg(hdmi_av_base(core), HDMI_CORE_AV_PB_CTRL1,
71119 + (repeat_cfg.audio_pkt << 5) |
71120 + (repeat_cfg.audio_pkt_repeat << 4) |
71121 + (repeat_cfg.avi_infoframe << 1) |
71122 + (repeat_cfg.avi_infoframe_repeat));
71123 +
71124 + /* enable/repeat the packet */
71125 + hdmi_write_reg(hdmi_av_base(core), HDMI_CORE_AV_PB_CTRL2,
71126 + (repeat_cfg.gen_cntrl_pkt << 3) |
71127 + (repeat_cfg.gen_cntrl_pkt_repeat << 2) |
71128 + (repeat_cfg.generic_pkt << 1) |
71129 + (repeat_cfg.generic_pkt_repeat));
71130 +}
71131 +
71132 +void hdmi4_configure(struct hdmi_core_data *core,
71133 + struct hdmi_wp_data *wp, struct hdmi_config *cfg)
71134 +{
71135 + /* HDMI */
71136 + struct omap_video_timings video_timing;
71137 + struct hdmi_video_format video_format;
71138 + /* HDMI core */
71139 + struct hdmi_core_infoframe_avi *avi_cfg = &core->avi_cfg;
71140 + struct hdmi_core_video_config v_core_cfg;
71141 + struct hdmi_core_packet_enable_repeat repeat_cfg;
71142 +
71143 + hdmi_core_init(&v_core_cfg, avi_cfg, &repeat_cfg);
71144 +
71145 + hdmi_wp_init_vid_fmt_timings(&video_format, &video_timing, cfg);
71146 +
71147 + hdmi_wp_video_config_timing(wp, &video_timing);
71148 +
71149 + /* video config */
71150 + video_format.packing_mode = HDMI_PACK_24b_RGB_YUV444_YUV422;
71151 +
71152 + hdmi_wp_video_config_format(wp, &video_format);
71153 +
71154 + hdmi_wp_video_config_interface(wp, &video_timing);
71155 +
71156 + /*
71157 + * configure core video part
71158 + * set software reset in the core
71159 + */
71160 + hdmi_core_swreset_assert(core);
71161 +
71162 + /* power down off */
71163 + hdmi_core_powerdown_disable(core);
71164 +
71165 + v_core_cfg.pkt_mode = HDMI_PACKETMODE24BITPERPIXEL;
71166 + v_core_cfg.hdmi_dvi = cfg->cm.mode;
71167 +
71168 + hdmi_core_video_config(core, &v_core_cfg);
71169 +
71170 + /* release software reset in the core */
71171 + hdmi_core_swreset_release(core);
71172 +
71173 + /*
71174 + * configure packet
71175 + * info frame video see doc CEA861-D page 65
71176 + */
71177 + avi_cfg->db1_format = HDMI_INFOFRAME_AVI_DB1Y_RGB;
71178 + avi_cfg->db1_active_info =
71179 + HDMI_INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_OFF;
71180 + avi_cfg->db1_bar_info_dv = HDMI_INFOFRAME_AVI_DB1B_NO;
71181 + avi_cfg->db1_scan_info = HDMI_INFOFRAME_AVI_DB1S_0;
71182 + avi_cfg->db2_colorimetry = HDMI_INFOFRAME_AVI_DB2C_NO;
71183 + avi_cfg->db2_aspect_ratio = HDMI_INFOFRAME_AVI_DB2M_NO;
71184 + avi_cfg->db2_active_fmt_ar = HDMI_INFOFRAME_AVI_DB2R_SAME;
71185 + avi_cfg->db3_itc = HDMI_INFOFRAME_AVI_DB3ITC_NO;
71186 + avi_cfg->db3_ec = HDMI_INFOFRAME_AVI_DB3EC_XVYUV601;
71187 + avi_cfg->db3_q_range = HDMI_INFOFRAME_AVI_DB3Q_DEFAULT;
71188 + avi_cfg->db3_nup_scaling = HDMI_INFOFRAME_AVI_DB3SC_NO;
71189 + avi_cfg->db4_videocode = cfg->cm.code;
71190 + avi_cfg->db5_pixel_repeat = HDMI_INFOFRAME_AVI_DB5PR_NO;
71191 + avi_cfg->db6_7_line_eoftop = 0;
71192 + avi_cfg->db8_9_line_sofbottom = 0;
71193 + avi_cfg->db10_11_pixel_eofleft = 0;
71194 + avi_cfg->db12_13_pixel_sofright = 0;
71195 +
71196 + hdmi_core_aux_infoframe_avi_config(core);
71197 +
71198 + /* enable/repeat the infoframe */
71199 + repeat_cfg.avi_infoframe = HDMI_PACKETENABLE;
71200 + repeat_cfg.avi_infoframe_repeat = HDMI_PACKETREPEATON;
71201 + /* wakeup */
71202 + repeat_cfg.audio_pkt = HDMI_PACKETENABLE;
71203 + repeat_cfg.audio_pkt_repeat = HDMI_PACKETREPEATON;
71204 + hdmi_core_av_packet_config(core, repeat_cfg);
71205 +}
71206 +
71207 +void hdmi4_core_dump(struct hdmi_core_data *core, struct seq_file *s)
71208 +{
71209 + int i;
71210 +
71211 +#define CORE_REG(i, name) name(i)
71212 +#define DUMPCORE(r) seq_printf(s, "%-35s %08x\n", #r,\
71213 + hdmi_read_reg(core->base, r))
71214 +#define DUMPCOREAV(r) seq_printf(s, "%-35s %08x\n", #r,\
71215 + hdmi_read_reg(hdmi_av_base(core), r))
71216 +#define DUMPCOREAV2(i, r) seq_printf(s, "%s[%d]%*s %08x\n", #r, i, \
71217 + (i < 10) ? 32 - (int)strlen(#r) : 31 - (int)strlen(#r), " ", \
71218 + hdmi_read_reg(hdmi_av_base(core), CORE_REG(i, r)))
71219 +
71220 + DUMPCORE(HDMI_CORE_SYS_VND_IDL);
71221 + DUMPCORE(HDMI_CORE_SYS_DEV_IDL);
71222 + DUMPCORE(HDMI_CORE_SYS_DEV_IDH);
71223 + DUMPCORE(HDMI_CORE_SYS_DEV_REV);
71224 + DUMPCORE(HDMI_CORE_SYS_SRST);
71225 + DUMPCORE(HDMI_CORE_SYS_SYS_CTRL1);
71226 + DUMPCORE(HDMI_CORE_SYS_SYS_STAT);
71227 + DUMPCORE(HDMI_CORE_SYS_SYS_CTRL3);
71228 + DUMPCORE(HDMI_CORE_SYS_DE_DLY);
71229 + DUMPCORE(HDMI_CORE_SYS_DE_CTRL);
71230 + DUMPCORE(HDMI_CORE_SYS_DE_TOP);
71231 + DUMPCORE(HDMI_CORE_SYS_DE_CNTL);
71232 + DUMPCORE(HDMI_CORE_SYS_DE_CNTH);
71233 + DUMPCORE(HDMI_CORE_SYS_DE_LINL);
71234 + DUMPCORE(HDMI_CORE_SYS_DE_LINH_1);
71235 + DUMPCORE(HDMI_CORE_SYS_HRES_L);
71236 + DUMPCORE(HDMI_CORE_SYS_HRES_H);
71237 + DUMPCORE(HDMI_CORE_SYS_VRES_L);
71238 + DUMPCORE(HDMI_CORE_SYS_VRES_H);
71239 + DUMPCORE(HDMI_CORE_SYS_IADJUST);
71240 + DUMPCORE(HDMI_CORE_SYS_POLDETECT);
71241 + DUMPCORE(HDMI_CORE_SYS_HWIDTH1);
71242 + DUMPCORE(HDMI_CORE_SYS_HWIDTH2);
71243 + DUMPCORE(HDMI_CORE_SYS_VWIDTH);
71244 + DUMPCORE(HDMI_CORE_SYS_VID_CTRL);
71245 + DUMPCORE(HDMI_CORE_SYS_VID_ACEN);
71246 + DUMPCORE(HDMI_CORE_SYS_VID_MODE);
71247 + DUMPCORE(HDMI_CORE_SYS_VID_BLANK1);
71248 + DUMPCORE(HDMI_CORE_SYS_VID_BLANK3);
71249 + DUMPCORE(HDMI_CORE_SYS_VID_BLANK1);
71250 + DUMPCORE(HDMI_CORE_SYS_DC_HEADER);
71251 + DUMPCORE(HDMI_CORE_SYS_VID_DITHER);
71252 + DUMPCORE(HDMI_CORE_SYS_RGB2XVYCC_CT);
71253 + DUMPCORE(HDMI_CORE_SYS_R2Y_COEFF_LOW);
71254 + DUMPCORE(HDMI_CORE_SYS_R2Y_COEFF_UP);
71255 + DUMPCORE(HDMI_CORE_SYS_G2Y_COEFF_LOW);
71256 + DUMPCORE(HDMI_CORE_SYS_G2Y_COEFF_UP);
71257 + DUMPCORE(HDMI_CORE_SYS_B2Y_COEFF_LOW);
71258 + DUMPCORE(HDMI_CORE_SYS_B2Y_COEFF_UP);
71259 + DUMPCORE(HDMI_CORE_SYS_R2CB_COEFF_LOW);
71260 + DUMPCORE(HDMI_CORE_SYS_R2CB_COEFF_UP);
71261 + DUMPCORE(HDMI_CORE_SYS_G2CB_COEFF_LOW);
71262 + DUMPCORE(HDMI_CORE_SYS_G2CB_COEFF_UP);
71263 + DUMPCORE(HDMI_CORE_SYS_B2CB_COEFF_LOW);
71264 + DUMPCORE(HDMI_CORE_SYS_B2CB_COEFF_UP);
71265 + DUMPCORE(HDMI_CORE_SYS_R2CR_COEFF_LOW);
71266 + DUMPCORE(HDMI_CORE_SYS_R2CR_COEFF_UP);
71267 + DUMPCORE(HDMI_CORE_SYS_G2CR_COEFF_LOW);
71268 + DUMPCORE(HDMI_CORE_SYS_G2CR_COEFF_UP);
71269 + DUMPCORE(HDMI_CORE_SYS_B2CR_COEFF_LOW);
71270 + DUMPCORE(HDMI_CORE_SYS_B2CR_COEFF_UP);
71271 + DUMPCORE(HDMI_CORE_SYS_RGB_OFFSET_LOW);
71272 + DUMPCORE(HDMI_CORE_SYS_RGB_OFFSET_UP);
71273 + DUMPCORE(HDMI_CORE_SYS_Y_OFFSET_LOW);
71274 + DUMPCORE(HDMI_CORE_SYS_Y_OFFSET_UP);
71275 + DUMPCORE(HDMI_CORE_SYS_CBCR_OFFSET_LOW);
71276 + DUMPCORE(HDMI_CORE_SYS_CBCR_OFFSET_UP);
71277 + DUMPCORE(HDMI_CORE_SYS_INTR_STATE);
71278 + DUMPCORE(HDMI_CORE_SYS_INTR1);
71279 + DUMPCORE(HDMI_CORE_SYS_INTR2);
71280 + DUMPCORE(HDMI_CORE_SYS_INTR3);
71281 + DUMPCORE(HDMI_CORE_SYS_INTR4);
71282 + DUMPCORE(HDMI_CORE_SYS_INTR_UNMASK1);
71283 + DUMPCORE(HDMI_CORE_SYS_INTR_UNMASK2);
71284 + DUMPCORE(HDMI_CORE_SYS_INTR_UNMASK3);
71285 + DUMPCORE(HDMI_CORE_SYS_INTR_UNMASK4);
71286 + DUMPCORE(HDMI_CORE_SYS_INTR_CTRL);
71287 + DUMPCORE(HDMI_CORE_SYS_TMDS_CTRL);
71288 +
71289 + DUMPCORE(HDMI_CORE_DDC_ADDR);
71290 + DUMPCORE(HDMI_CORE_DDC_SEGM);
71291 + DUMPCORE(HDMI_CORE_DDC_OFFSET);
71292 + DUMPCORE(HDMI_CORE_DDC_COUNT1);
71293 + DUMPCORE(HDMI_CORE_DDC_COUNT2);
71294 + DUMPCORE(HDMI_CORE_DDC_STATUS);
71295 + DUMPCORE(HDMI_CORE_DDC_CMD);
71296 + DUMPCORE(HDMI_CORE_DDC_DATA);
71297 +
71298 + DUMPCOREAV(HDMI_CORE_AV_ACR_CTRL);
71299 + DUMPCOREAV(HDMI_CORE_AV_FREQ_SVAL);
71300 + DUMPCOREAV(HDMI_CORE_AV_N_SVAL1);
71301 + DUMPCOREAV(HDMI_CORE_AV_N_SVAL2);
71302 + DUMPCOREAV(HDMI_CORE_AV_N_SVAL3);
71303 + DUMPCOREAV(HDMI_CORE_AV_CTS_SVAL1);
71304 + DUMPCOREAV(HDMI_CORE_AV_CTS_SVAL2);
71305 + DUMPCOREAV(HDMI_CORE_AV_CTS_SVAL3);
71306 + DUMPCOREAV(HDMI_CORE_AV_CTS_HVAL1);
71307 + DUMPCOREAV(HDMI_CORE_AV_CTS_HVAL2);
71308 + DUMPCOREAV(HDMI_CORE_AV_CTS_HVAL3);
71309 + DUMPCOREAV(HDMI_CORE_AV_AUD_MODE);
71310 + DUMPCOREAV(HDMI_CORE_AV_SPDIF_CTRL);
71311 + DUMPCOREAV(HDMI_CORE_AV_HW_SPDIF_FS);
71312 + DUMPCOREAV(HDMI_CORE_AV_SWAP_I2S);
71313 + DUMPCOREAV(HDMI_CORE_AV_SPDIF_ERTH);
71314 + DUMPCOREAV(HDMI_CORE_AV_I2S_IN_MAP);
71315 + DUMPCOREAV(HDMI_CORE_AV_I2S_IN_CTRL);
71316 + DUMPCOREAV(HDMI_CORE_AV_I2S_CHST0);
71317 + DUMPCOREAV(HDMI_CORE_AV_I2S_CHST1);
71318 + DUMPCOREAV(HDMI_CORE_AV_I2S_CHST2);
71319 + DUMPCOREAV(HDMI_CORE_AV_I2S_CHST4);
71320 + DUMPCOREAV(HDMI_CORE_AV_I2S_CHST5);
71321 + DUMPCOREAV(HDMI_CORE_AV_ASRC);
71322 + DUMPCOREAV(HDMI_CORE_AV_I2S_IN_LEN);
71323 + DUMPCOREAV(HDMI_CORE_AV_HDMI_CTRL);
71324 + DUMPCOREAV(HDMI_CORE_AV_AUDO_TXSTAT);
71325 + DUMPCOREAV(HDMI_CORE_AV_AUD_PAR_BUSCLK_1);
71326 + DUMPCOREAV(HDMI_CORE_AV_AUD_PAR_BUSCLK_2);
71327 + DUMPCOREAV(HDMI_CORE_AV_AUD_PAR_BUSCLK_3);
71328 + DUMPCOREAV(HDMI_CORE_AV_TEST_TXCTRL);
71329 + DUMPCOREAV(HDMI_CORE_AV_DPD);
71330 + DUMPCOREAV(HDMI_CORE_AV_PB_CTRL1);
71331 + DUMPCOREAV(HDMI_CORE_AV_PB_CTRL2);
71332 + DUMPCOREAV(HDMI_CORE_AV_AVI_TYPE);
71333 + DUMPCOREAV(HDMI_CORE_AV_AVI_VERS);
71334 + DUMPCOREAV(HDMI_CORE_AV_AVI_LEN);
71335 + DUMPCOREAV(HDMI_CORE_AV_AVI_CHSUM);
71336 +
71337 + for (i = 0; i < HDMI_CORE_AV_AVI_DBYTE_NELEMS; i++)
71338 + DUMPCOREAV2(i, HDMI_CORE_AV_AVI_DBYTE);
71339 +
71340 + DUMPCOREAV(HDMI_CORE_AV_SPD_TYPE);
71341 + DUMPCOREAV(HDMI_CORE_AV_SPD_VERS);
71342 + DUMPCOREAV(HDMI_CORE_AV_SPD_LEN);
71343 + DUMPCOREAV(HDMI_CORE_AV_SPD_CHSUM);
71344 +
71345 + for (i = 0; i < HDMI_CORE_AV_SPD_DBYTE_NELEMS; i++)
71346 + DUMPCOREAV2(i, HDMI_CORE_AV_SPD_DBYTE);
71347 +
71348 + DUMPCOREAV(HDMI_CORE_AV_AUDIO_TYPE);
71349 + DUMPCOREAV(HDMI_CORE_AV_AUDIO_VERS);
71350 + DUMPCOREAV(HDMI_CORE_AV_AUDIO_LEN);
71351 + DUMPCOREAV(HDMI_CORE_AV_AUDIO_CHSUM);
71352 +
71353 + for (i = 0; i < HDMI_CORE_AV_AUD_DBYTE_NELEMS; i++)
71354 + DUMPCOREAV2(i, HDMI_CORE_AV_AUD_DBYTE);
71355 +
71356 + DUMPCOREAV(HDMI_CORE_AV_MPEG_TYPE);
71357 + DUMPCOREAV(HDMI_CORE_AV_MPEG_VERS);
71358 + DUMPCOREAV(HDMI_CORE_AV_MPEG_LEN);
71359 + DUMPCOREAV(HDMI_CORE_AV_MPEG_CHSUM);
71360 +
71361 + for (i = 0; i < HDMI_CORE_AV_MPEG_DBYTE_NELEMS; i++)
71362 + DUMPCOREAV2(i, HDMI_CORE_AV_MPEG_DBYTE);
71363 +
71364 + for (i = 0; i < HDMI_CORE_AV_GEN_DBYTE_NELEMS; i++)
71365 + DUMPCOREAV2(i, HDMI_CORE_AV_GEN_DBYTE);
71366 +
71367 + DUMPCOREAV(HDMI_CORE_AV_CP_BYTE1);
71368 +
71369 + for (i = 0; i < HDMI_CORE_AV_GEN2_DBYTE_NELEMS; i++)
71370 + DUMPCOREAV2(i, HDMI_CORE_AV_GEN2_DBYTE);
71371 +
71372 + DUMPCOREAV(HDMI_CORE_AV_CEC_ADDR_ID);
71373 +}
71374 +
71375 +#if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO)
71376 +static void hdmi_core_audio_config(struct hdmi_core_data *core,
71377 + struct hdmi_core_audio_config *cfg)
71378 +{
71379 + u32 r;
71380 + void __iomem *av_base = hdmi_av_base(core);
71381 +
71382 + /*
71383 + * Parameters for generation of Audio Clock Recovery packets
71384 + */
71385 + REG_FLD_MOD(av_base, HDMI_CORE_AV_N_SVAL1, cfg->n, 7, 0);
71386 + REG_FLD_MOD(av_base, HDMI_CORE_AV_N_SVAL2, cfg->n >> 8, 7, 0);
71387 + REG_FLD_MOD(av_base, HDMI_CORE_AV_N_SVAL3, cfg->n >> 16, 7, 0);
71388 +
71389 + if (cfg->cts_mode == HDMI_AUDIO_CTS_MODE_SW) {
71390 + REG_FLD_MOD(av_base, HDMI_CORE_AV_CTS_SVAL1, cfg->cts, 7, 0);
71391 + REG_FLD_MOD(av_base,
71392 + HDMI_CORE_AV_CTS_SVAL2, cfg->cts >> 8, 7, 0);
71393 + REG_FLD_MOD(av_base,
71394 + HDMI_CORE_AV_CTS_SVAL3, cfg->cts >> 16, 7, 0);
71395 + } else {
71396 + REG_FLD_MOD(av_base, HDMI_CORE_AV_AUD_PAR_BUSCLK_1,
71397 + cfg->aud_par_busclk, 7, 0);
71398 + REG_FLD_MOD(av_base, HDMI_CORE_AV_AUD_PAR_BUSCLK_2,
71399 + (cfg->aud_par_busclk >> 8), 7, 0);
71400 + REG_FLD_MOD(av_base, HDMI_CORE_AV_AUD_PAR_BUSCLK_3,
71401 + (cfg->aud_par_busclk >> 16), 7, 0);
71402 + }
71403 +
71404 + /* Set ACR clock divisor */
71405 + REG_FLD_MOD(av_base,
71406 + HDMI_CORE_AV_FREQ_SVAL, cfg->mclk_mode, 2, 0);
71407 +
71408 + r = hdmi_read_reg(av_base, HDMI_CORE_AV_ACR_CTRL);
71409 + /*
71410 + * Use TMDS clock for ACR packets. For devices that use
71411 + * the MCLK, this is the first part of the MCLK initialization.
71412 + */
71413 + r = FLD_MOD(r, 0, 2, 2);
71414 +
71415 + r = FLD_MOD(r, cfg->en_acr_pkt, 1, 1);
71416 + r = FLD_MOD(r, cfg->cts_mode, 0, 0);
71417 + hdmi_write_reg(av_base, HDMI_CORE_AV_ACR_CTRL, r);
71418 +
71419 + /* For devices using MCLK, this completes its initialization. */
71420 + if (cfg->use_mclk)
71421 + REG_FLD_MOD(av_base, HDMI_CORE_AV_ACR_CTRL, 1, 2, 2);
71422 +
71423 + /* Override of SPDIF sample frequency with value in I2S_CHST4 */
71424 + REG_FLD_MOD(av_base, HDMI_CORE_AV_SPDIF_CTRL,
71425 + cfg->fs_override, 1, 1);
71426 +
71427 + /*
71428 + * Set IEC-60958-3 channel status word. It is passed to the IP
71429 + * just as it is received. The user of the driver is responsible
71430 + * for its contents.
71431 + */
71432 + hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_CHST0,
71433 + cfg->iec60958_cfg->status[0]);
71434 + hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_CHST1,
71435 + cfg->iec60958_cfg->status[1]);
71436 + hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_CHST2,
71437 + cfg->iec60958_cfg->status[2]);
71438 + /* yes, this is correct: status[3] goes to CHST4 register */
71439 + hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_CHST4,
71440 + cfg->iec60958_cfg->status[3]);
71441 + /* yes, this is correct: status[4] goes to CHST5 register */
71442 + hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_CHST5,
71443 + cfg->iec60958_cfg->status[4]);
71444 +
71445 + /* set I2S parameters */
71446 + r = hdmi_read_reg(av_base, HDMI_CORE_AV_I2S_IN_CTRL);
71447 + r = FLD_MOD(r, cfg->i2s_cfg.sck_edge_mode, 6, 6);
71448 + r = FLD_MOD(r, cfg->i2s_cfg.vbit, 4, 4);
71449 + r = FLD_MOD(r, cfg->i2s_cfg.justification, 2, 2);
71450 + r = FLD_MOD(r, cfg->i2s_cfg.direction, 1, 1);
71451 + r = FLD_MOD(r, cfg->i2s_cfg.shift, 0, 0);
71452 + hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_IN_CTRL, r);
71453 +
71454 + REG_FLD_MOD(av_base, HDMI_CORE_AV_I2S_IN_LEN,
71455 + cfg->i2s_cfg.in_length_bits, 3, 0);
71456 +
71457 + /* Audio channels and mode parameters */
71458 + REG_FLD_MOD(av_base, HDMI_CORE_AV_HDMI_CTRL, cfg->layout, 2, 1);
71459 + r = hdmi_read_reg(av_base, HDMI_CORE_AV_AUD_MODE);
71460 + r = FLD_MOD(r, cfg->i2s_cfg.active_sds, 7, 4);
71461 + r = FLD_MOD(r, cfg->en_dsd_audio, 3, 3);
71462 + r = FLD_MOD(r, cfg->en_parallel_aud_input, 2, 2);
71463 + r = FLD_MOD(r, cfg->en_spdif, 1, 1);
71464 + hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_MODE, r);
71465 +
71466 + /* Audio channel mappings */
71467 + /* TODO: Make channel mapping dynamic. For now, map channels
71468 + * in the ALSA order: FL/FR/RL/RR/C/LFE/SL/SR. Remapping is needed as
71469 + * HDMI speaker order is different. See CEA-861 Section 6.6.2.
71470 + */
71471 + hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_IN_MAP, 0x78);
71472 + REG_FLD_MOD(av_base, HDMI_CORE_AV_SWAP_I2S, 1, 5, 5);
71473 +}
71474 +
71475 +static void hdmi_core_audio_infoframe_cfg(struct hdmi_core_data *core,
71476 + struct snd_cea_861_aud_if *info_aud)
71477 +{
71478 + u8 sum = 0, checksum = 0;
71479 + void __iomem *av_base = hdmi_av_base(core);
71480 +
71481 + /*
71482 + * Set audio info frame type, version and length as
71483 + * described in HDMI 1.4a Section 8.2.2 specification.
71484 + * Checksum calculation is defined in Section 5.3.5.
71485 + */
71486 + hdmi_write_reg(av_base, HDMI_CORE_AV_AUDIO_TYPE, 0x84);
71487 + hdmi_write_reg(av_base, HDMI_CORE_AV_AUDIO_VERS, 0x01);
71488 + hdmi_write_reg(av_base, HDMI_CORE_AV_AUDIO_LEN, 0x0a);
71489 + sum += 0x84 + 0x001 + 0x00a;
71490 +
71491 + hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(0),
71492 + info_aud->db1_ct_cc);
71493 + sum += info_aud->db1_ct_cc;
71494 +
71495 + hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(1),
71496 + info_aud->db2_sf_ss);
71497 + sum += info_aud->db2_sf_ss;
71498 +
71499 + hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(2), info_aud->db3);
71500 + sum += info_aud->db3;
71501 +
71502 + hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(3), info_aud->db4_ca);
71503 + sum += info_aud->db4_ca;
71504 +
71505 + hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(4),
71506 + info_aud->db5_dminh_lsv);
71507 + sum += info_aud->db5_dminh_lsv;
71508 +
71509 + hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(5), 0x00);
71510 + hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(6), 0x00);
71511 + hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(7), 0x00);
71512 + hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(8), 0x00);
71513 + hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(9), 0x00);
71514 +
71515 + checksum = 0x100 - sum;
71516 + hdmi_write_reg(av_base,
71517 + HDMI_CORE_AV_AUDIO_CHSUM, checksum);
71518 +
71519 + /*
71520 + * TODO: Add MPEG and SPD enable and repeat cfg when EDID parsing
71521 + * is available.
71522 + */
71523 +}
71524 +
71525 +int hdmi4_audio_config(struct hdmi_core_data *core, struct hdmi_wp_data *wp,
71526 + struct omap_dss_audio *audio, u32 pclk)
71527 +{
71528 + struct hdmi_audio_format audio_format;
71529 + struct hdmi_audio_dma audio_dma;
71530 + struct hdmi_core_audio_config acore;
71531 + int err, n, cts, channel_count;
71532 + unsigned int fs_nr;
71533 + bool word_length_16b = false;
71534 +
71535 + if (!audio || !audio->iec || !audio->cea || !core)
71536 + return -EINVAL;
71537 +
71538 + acore.iec60958_cfg = audio->iec;
71539 + /*
71540 + * In the IEC-60958 status word, check if the audio sample word length
71541 + * is 16-bit as several optimizations can be performed in such case.
71542 + */
71543 + if (!(audio->iec->status[4] & IEC958_AES4_CON_MAX_WORDLEN_24))
71544 + if (audio->iec->status[4] & IEC958_AES4_CON_WORDLEN_20_16)
71545 + word_length_16b = true;
71546 +
71547 + /* I2S configuration. See Phillips' specification */
71548 + if (word_length_16b)
71549 + acore.i2s_cfg.justification = HDMI_AUDIO_JUSTIFY_LEFT;
71550 + else
71551 + acore.i2s_cfg.justification = HDMI_AUDIO_JUSTIFY_RIGHT;
71552 + /*
71553 + * The I2S input word length is twice the lenght given in the IEC-60958
71554 + * status word. If the word size is greater than
71555 + * 20 bits, increment by one.
71556 + */
71557 + acore.i2s_cfg.in_length_bits = audio->iec->status[4]
71558 + & IEC958_AES4_CON_WORDLEN;
71559 + if (audio->iec->status[4] & IEC958_AES4_CON_MAX_WORDLEN_24)
71560 + acore.i2s_cfg.in_length_bits++;
71561 + acore.i2s_cfg.sck_edge_mode = HDMI_AUDIO_I2S_SCK_EDGE_RISING;
71562 + acore.i2s_cfg.vbit = HDMI_AUDIO_I2S_VBIT_FOR_PCM;
71563 + acore.i2s_cfg.direction = HDMI_AUDIO_I2S_MSB_SHIFTED_FIRST;
71564 + acore.i2s_cfg.shift = HDMI_AUDIO_I2S_FIRST_BIT_SHIFT;
71565 +
71566 + /* convert sample frequency to a number */
71567 + switch (audio->iec->status[3] & IEC958_AES3_CON_FS) {
71568 + case IEC958_AES3_CON_FS_32000:
71569 + fs_nr = 32000;
71570 + break;
71571 + case IEC958_AES3_CON_FS_44100:
71572 + fs_nr = 44100;
71573 + break;
71574 + case IEC958_AES3_CON_FS_48000:
71575 + fs_nr = 48000;
71576 + break;
71577 + case IEC958_AES3_CON_FS_88200:
71578 + fs_nr = 88200;
71579 + break;
71580 + case IEC958_AES3_CON_FS_96000:
71581 + fs_nr = 96000;
71582 + break;
71583 + case IEC958_AES3_CON_FS_176400:
71584 + fs_nr = 176400;
71585 + break;
71586 + case IEC958_AES3_CON_FS_192000:
71587 + fs_nr = 192000;
71588 + break;
71589 + default:
71590 + return -EINVAL;
71591 + }
71592 +
71593 + err = hdmi_compute_acr(pclk, fs_nr, &n, &cts);
71594 +
71595 + /* Audio clock regeneration settings */
71596 + acore.n = n;
71597 + acore.cts = cts;
71598 + if (dss_has_feature(FEAT_HDMI_CTS_SWMODE)) {
71599 + acore.aud_par_busclk = 0;
71600 + acore.cts_mode = HDMI_AUDIO_CTS_MODE_SW;
71601 + acore.use_mclk = dss_has_feature(FEAT_HDMI_AUDIO_USE_MCLK);
71602 + } else {
71603 + acore.aud_par_busclk = (((128 * 31) - 1) << 8);
71604 + acore.cts_mode = HDMI_AUDIO_CTS_MODE_HW;
71605 + acore.use_mclk = true;
71606 + }
71607 +
71608 + if (acore.use_mclk)
71609 + acore.mclk_mode = HDMI_AUDIO_MCLK_128FS;
71610 +
71611 + /* Audio channels settings */
71612 + channel_count = (audio->cea->db1_ct_cc &
71613 + CEA861_AUDIO_INFOFRAME_DB1CC) + 1;
71614 +
71615 + switch (channel_count) {
71616 + case 2:
71617 + audio_format.active_chnnls_msk = 0x03;
71618 + break;
71619 + case 3:
71620 + audio_format.active_chnnls_msk = 0x07;
71621 + break;
71622 + case 4:
71623 + audio_format.active_chnnls_msk = 0x0f;
71624 + break;
71625 + case 5:
71626 + audio_format.active_chnnls_msk = 0x1f;
71627 + break;
71628 + case 6:
71629 + audio_format.active_chnnls_msk = 0x3f;
71630 + break;
71631 + case 7:
71632 + audio_format.active_chnnls_msk = 0x7f;
71633 + break;
71634 + case 8:
71635 + audio_format.active_chnnls_msk = 0xff;
71636 + break;
71637 + default:
71638 + return -EINVAL;
71639 + }
71640 +
71641 + /*
71642 + * the HDMI IP needs to enable four stereo channels when transmitting
71643 + * more than 2 audio channels
71644 + */
71645 + if (channel_count == 2) {
71646 + audio_format.stereo_channels = HDMI_AUDIO_STEREO_ONECHANNEL;
71647 + acore.i2s_cfg.active_sds = HDMI_AUDIO_I2S_SD0_EN;
71648 + acore.layout = HDMI_AUDIO_LAYOUT_2CH;
71649 + } else {
71650 + audio_format.stereo_channels = HDMI_AUDIO_STEREO_FOURCHANNELS;
71651 + acore.i2s_cfg.active_sds = HDMI_AUDIO_I2S_SD0_EN |
71652 + HDMI_AUDIO_I2S_SD1_EN | HDMI_AUDIO_I2S_SD2_EN |
71653 + HDMI_AUDIO_I2S_SD3_EN;
71654 + acore.layout = HDMI_AUDIO_LAYOUT_8CH;
71655 + }
71656 +
71657 + acore.en_spdif = false;
71658 + /* use sample frequency from channel status word */
71659 + acore.fs_override = true;
71660 + /* enable ACR packets */
71661 + acore.en_acr_pkt = true;
71662 + /* disable direct streaming digital audio */
71663 + acore.en_dsd_audio = false;
71664 + /* use parallel audio interface */
71665 + acore.en_parallel_aud_input = true;
71666 +
71667 + /* DMA settings */
71668 + if (word_length_16b)
71669 + audio_dma.transfer_size = 0x10;
71670 + else
71671 + audio_dma.transfer_size = 0x20;
71672 + audio_dma.block_size = 0xC0;
71673 + audio_dma.mode = HDMI_AUDIO_TRANSF_DMA;
71674 + audio_dma.fifo_threshold = 0x20; /* in number of samples */
71675 +
71676 + /* audio FIFO format settings */
71677 + if (word_length_16b) {
71678 + audio_format.samples_per_word = HDMI_AUDIO_ONEWORD_TWOSAMPLES;
71679 + audio_format.sample_size = HDMI_AUDIO_SAMPLE_16BITS;
71680 + audio_format.justification = HDMI_AUDIO_JUSTIFY_LEFT;
71681 + } else {
71682 + audio_format.samples_per_word = HDMI_AUDIO_ONEWORD_ONESAMPLE;
71683 + audio_format.sample_size = HDMI_AUDIO_SAMPLE_24BITS;
71684 + audio_format.justification = HDMI_AUDIO_JUSTIFY_RIGHT;
71685 + }
71686 + audio_format.type = HDMI_AUDIO_TYPE_LPCM;
71687 + audio_format.sample_order = HDMI_AUDIO_SAMPLE_LEFT_FIRST;
71688 + /* disable start/stop signals of IEC 60958 blocks */
71689 + audio_format.en_sig_blk_strt_end = HDMI_AUDIO_BLOCK_SIG_STARTEND_ON;
71690 +
71691 + /* configure DMA and audio FIFO format*/
71692 + hdmi_wp_audio_config_dma(wp, &audio_dma);
71693 + hdmi_wp_audio_config_format(wp, &audio_format);
71694 +
71695 + /* configure the core*/
71696 + hdmi_core_audio_config(core, &acore);
71697 +
71698 + /* configure CEA 861 audio infoframe*/
71699 + hdmi_core_audio_infoframe_cfg(core, audio->cea);
71700 +
71701 + return 0;
71702 +}
71703 +
71704 +int hdmi4_audio_start(struct hdmi_core_data *core, struct hdmi_wp_data *wp)
71705 +{
71706 + REG_FLD_MOD(hdmi_av_base(core),
71707 + HDMI_CORE_AV_AUD_MODE, true, 0, 0);
71708 +
71709 + hdmi_wp_audio_core_req_enable(wp, true);
71710 +
71711 + return 0;
71712 +}
71713 +
71714 +void hdmi4_audio_stop(struct hdmi_core_data *core, struct hdmi_wp_data *wp)
71715 +{
71716 + REG_FLD_MOD(hdmi_av_base(core),
71717 + HDMI_CORE_AV_AUD_MODE, false, 0, 0);
71718 +
71719 + hdmi_wp_audio_core_req_enable(wp, false);
71720 +}
71721 +
71722 +int hdmi4_audio_get_dma_port(u32 *offset, u32 *size)
71723 +{
71724 + if (!offset || !size)
71725 + return -EINVAL;
71726 + *offset = HDMI_WP_AUDIO_DATA;
71727 + *size = 4;
71728 + return 0;
71729 +}
71730 +
71731 +#endif
71732 +
71733 +int hdmi4_core_init(struct platform_device *pdev, struct hdmi_core_data *core)
71734 +{
71735 + struct resource *res;
71736 +
71737 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi_core");
71738 + if (!res) {
71739 + DSSERR("can't get CORE IORESOURCE_MEM HDMI\n");
71740 + return -EINVAL;
71741 + }
71742 +
71743 + core->base = devm_request_and_ioremap(&pdev->dev, res);
71744 + if (!core->base) {
71745 + DSSERR("can't ioremap HDMI core\n");
71746 + return -ENOMEM;
71747 + }
71748 +
71749 + return 0;
71750 +}
71751 --- /dev/null
71752 +++ b/drivers/video/omap2/dss/hdmi4_core.h
71753 @@ -0,0 +1,276 @@
71754 +/*
71755 + * HDMI header definition for OMAP4 HDMI core IP
71756 + *
71757 + * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
71758 + *
71759 + * This program is free software; you can redistribute it and/or modify it
71760 + * under the terms of the GNU General Public License version 2 as published by
71761 + * the Free Software Foundation.
71762 + *
71763 + * This program is distributed in the hope that it will be useful, but WITHOUT
71764 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
71765 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
71766 + * more details.
71767 + *
71768 + * You should have received a copy of the GNU General Public License along with
71769 + * this program. If not, see <http://www.gnu.org/licenses/>.
71770 + */
71771 +
71772 +#ifndef _HDMI4_CORE_H_
71773 +#define _HDMI4_CORE_H_
71774 +
71775 +#include "hdmi.h"
71776 +
71777 +/* OMAP4 HDMI IP Core System */
71778 +
71779 +#define HDMI_CORE_SYS_VND_IDL 0x0
71780 +#define HDMI_CORE_SYS_DEV_IDL 0x8
71781 +#define HDMI_CORE_SYS_DEV_IDH 0xC
71782 +#define HDMI_CORE_SYS_DEV_REV 0x10
71783 +#define HDMI_CORE_SYS_SRST 0x14
71784 +#define HDMI_CORE_SYS_SYS_CTRL1 0x20
71785 +#define HDMI_CORE_SYS_SYS_STAT 0x24
71786 +#define HDMI_CORE_SYS_SYS_CTRL3 0x28
71787 +#define HDMI_CORE_SYS_DCTL 0x34
71788 +#define HDMI_CORE_SYS_DE_DLY 0xC8
71789 +#define HDMI_CORE_SYS_DE_CTRL 0xCC
71790 +#define HDMI_CORE_SYS_DE_TOP 0xD0
71791 +#define HDMI_CORE_SYS_DE_CNTL 0xD8
71792 +#define HDMI_CORE_SYS_DE_CNTH 0xDC
71793 +#define HDMI_CORE_SYS_DE_LINL 0xE0
71794 +#define HDMI_CORE_SYS_DE_LINH_1 0xE4
71795 +#define HDMI_CORE_SYS_HRES_L 0xE8
71796 +#define HDMI_CORE_SYS_HRES_H 0xEC
71797 +#define HDMI_CORE_SYS_VRES_L 0xF0
71798 +#define HDMI_CORE_SYS_VRES_H 0xF4
71799 +#define HDMI_CORE_SYS_IADJUST 0xF8
71800 +#define HDMI_CORE_SYS_POLDETECT 0xFC
71801 +#define HDMI_CORE_SYS_HWIDTH1 0x110
71802 +#define HDMI_CORE_SYS_HWIDTH2 0x114
71803 +#define HDMI_CORE_SYS_VWIDTH 0x11C
71804 +#define HDMI_CORE_SYS_VID_CTRL 0x120
71805 +#define HDMI_CORE_SYS_VID_ACEN 0x124
71806 +#define HDMI_CORE_SYS_VID_MODE 0x128
71807 +#define HDMI_CORE_SYS_VID_BLANK1 0x12C
71808 +#define HDMI_CORE_SYS_VID_BLANK2 0x130
71809 +#define HDMI_CORE_SYS_VID_BLANK3 0x134
71810 +#define HDMI_CORE_SYS_DC_HEADER 0x138
71811 +#define HDMI_CORE_SYS_VID_DITHER 0x13C
71812 +#define HDMI_CORE_SYS_RGB2XVYCC_CT 0x140
71813 +#define HDMI_CORE_SYS_R2Y_COEFF_LOW 0x144
71814 +#define HDMI_CORE_SYS_R2Y_COEFF_UP 0x148
71815 +#define HDMI_CORE_SYS_G2Y_COEFF_LOW 0x14C
71816 +#define HDMI_CORE_SYS_G2Y_COEFF_UP 0x150
71817 +#define HDMI_CORE_SYS_B2Y_COEFF_LOW 0x154
71818 +#define HDMI_CORE_SYS_B2Y_COEFF_UP 0x158
71819 +#define HDMI_CORE_SYS_R2CB_COEFF_LOW 0x15C
71820 +#define HDMI_CORE_SYS_R2CB_COEFF_UP 0x160
71821 +#define HDMI_CORE_SYS_G2CB_COEFF_LOW 0x164
71822 +#define HDMI_CORE_SYS_G2CB_COEFF_UP 0x168
71823 +#define HDMI_CORE_SYS_B2CB_COEFF_LOW 0x16C
71824 +#define HDMI_CORE_SYS_B2CB_COEFF_UP 0x170
71825 +#define HDMI_CORE_SYS_R2CR_COEFF_LOW 0x174
71826 +#define HDMI_CORE_SYS_R2CR_COEFF_UP 0x178
71827 +#define HDMI_CORE_SYS_G2CR_COEFF_LOW 0x17C
71828 +#define HDMI_CORE_SYS_G2CR_COEFF_UP 0x180
71829 +#define HDMI_CORE_SYS_B2CR_COEFF_LOW 0x184
71830 +#define HDMI_CORE_SYS_B2CR_COEFF_UP 0x188
71831 +#define HDMI_CORE_SYS_RGB_OFFSET_LOW 0x18C
71832 +#define HDMI_CORE_SYS_RGB_OFFSET_UP 0x190
71833 +#define HDMI_CORE_SYS_Y_OFFSET_LOW 0x194
71834 +#define HDMI_CORE_SYS_Y_OFFSET_UP 0x198
71835 +#define HDMI_CORE_SYS_CBCR_OFFSET_LOW 0x19C
71836 +#define HDMI_CORE_SYS_CBCR_OFFSET_UP 0x1A0
71837 +#define HDMI_CORE_SYS_INTR_STATE 0x1C0
71838 +#define HDMI_CORE_SYS_INTR1 0x1C4
71839 +#define HDMI_CORE_SYS_INTR2 0x1C8
71840 +#define HDMI_CORE_SYS_INTR3 0x1CC
71841 +#define HDMI_CORE_SYS_INTR4 0x1D0
71842 +#define HDMI_CORE_SYS_INTR_UNMASK1 0x1D4
71843 +#define HDMI_CORE_SYS_INTR_UNMASK2 0x1D8
71844 +#define HDMI_CORE_SYS_INTR_UNMASK3 0x1DC
71845 +#define HDMI_CORE_SYS_INTR_UNMASK4 0x1E0
71846 +#define HDMI_CORE_SYS_INTR_CTRL 0x1E4
71847 +#define HDMI_CORE_SYS_TMDS_CTRL 0x208
71848 +
71849 +/* value definitions for HDMI_CORE_SYS_SYS_CTRL1 fields */
71850 +#define HDMI_CORE_SYS_SYS_CTRL1_VEN_FOLLOWVSYNC 0x1
71851 +#define HDMI_CORE_SYS_SYS_CTRL1_HEN_FOLLOWHSYNC 0x1
71852 +#define HDMI_CORE_SYS_SYS_CTRL1_BSEL_24BITBUS 0x1
71853 +#define HDMI_CORE_SYS_SYS_CTRL1_EDGE_RISINGEDGE 0x1
71854 +
71855 +/* HDMI DDC E-DID */
71856 +#define HDMI_CORE_DDC_ADDR 0x3B4
71857 +#define HDMI_CORE_DDC_SEGM 0x3B8
71858 +#define HDMI_CORE_DDC_OFFSET 0x3BC
71859 +#define HDMI_CORE_DDC_COUNT1 0x3C0
71860 +#define HDMI_CORE_DDC_COUNT2 0x3C4
71861 +#define HDMI_CORE_DDC_STATUS 0x3C8
71862 +#define HDMI_CORE_DDC_CMD 0x3CC
71863 +#define HDMI_CORE_DDC_DATA 0x3D0
71864 +
71865 +/* HDMI IP Core Audio Video */
71866 +
71867 +#define HDMI_CORE_AV_ACR_CTRL 0x4
71868 +#define HDMI_CORE_AV_FREQ_SVAL 0x8
71869 +#define HDMI_CORE_AV_N_SVAL1 0xC
71870 +#define HDMI_CORE_AV_N_SVAL2 0x10
71871 +#define HDMI_CORE_AV_N_SVAL3 0x14
71872 +#define HDMI_CORE_AV_CTS_SVAL1 0x18
71873 +#define HDMI_CORE_AV_CTS_SVAL2 0x1C
71874 +#define HDMI_CORE_AV_CTS_SVAL3 0x20
71875 +#define HDMI_CORE_AV_CTS_HVAL1 0x24
71876 +#define HDMI_CORE_AV_CTS_HVAL2 0x28
71877 +#define HDMI_CORE_AV_CTS_HVAL3 0x2C
71878 +#define HDMI_CORE_AV_AUD_MODE 0x50
71879 +#define HDMI_CORE_AV_SPDIF_CTRL 0x54
71880 +#define HDMI_CORE_AV_HW_SPDIF_FS 0x60
71881 +#define HDMI_CORE_AV_SWAP_I2S 0x64
71882 +#define HDMI_CORE_AV_SPDIF_ERTH 0x6C
71883 +#define HDMI_CORE_AV_I2S_IN_MAP 0x70
71884 +#define HDMI_CORE_AV_I2S_IN_CTRL 0x74
71885 +#define HDMI_CORE_AV_I2S_CHST0 0x78
71886 +#define HDMI_CORE_AV_I2S_CHST1 0x7C
71887 +#define HDMI_CORE_AV_I2S_CHST2 0x80
71888 +#define HDMI_CORE_AV_I2S_CHST4 0x84
71889 +#define HDMI_CORE_AV_I2S_CHST5 0x88
71890 +#define HDMI_CORE_AV_ASRC 0x8C
71891 +#define HDMI_CORE_AV_I2S_IN_LEN 0x90
71892 +#define HDMI_CORE_AV_HDMI_CTRL 0xBC
71893 +#define HDMI_CORE_AV_AUDO_TXSTAT 0xC0
71894 +#define HDMI_CORE_AV_AUD_PAR_BUSCLK_1 0xCC
71895 +#define HDMI_CORE_AV_AUD_PAR_BUSCLK_2 0xD0
71896 +#define HDMI_CORE_AV_AUD_PAR_BUSCLK_3 0xD4
71897 +#define HDMI_CORE_AV_TEST_TXCTRL 0xF0
71898 +#define HDMI_CORE_AV_DPD 0xF4
71899 +#define HDMI_CORE_AV_PB_CTRL1 0xF8
71900 +#define HDMI_CORE_AV_PB_CTRL2 0xFC
71901 +#define HDMI_CORE_AV_AVI_TYPE 0x100
71902 +#define HDMI_CORE_AV_AVI_VERS 0x104
71903 +#define HDMI_CORE_AV_AVI_LEN 0x108
71904 +#define HDMI_CORE_AV_AVI_CHSUM 0x10C
71905 +#define HDMI_CORE_AV_AVI_DBYTE(n) (n * 4 + 0x110)
71906 +#define HDMI_CORE_AV_SPD_TYPE 0x180
71907 +#define HDMI_CORE_AV_SPD_VERS 0x184
71908 +#define HDMI_CORE_AV_SPD_LEN 0x188
71909 +#define HDMI_CORE_AV_SPD_CHSUM 0x18C
71910 +#define HDMI_CORE_AV_SPD_DBYTE(n) (n * 4 + 0x190)
71911 +#define HDMI_CORE_AV_AUDIO_TYPE 0x200
71912 +#define HDMI_CORE_AV_AUDIO_VERS 0x204
71913 +#define HDMI_CORE_AV_AUDIO_LEN 0x208
71914 +#define HDMI_CORE_AV_AUDIO_CHSUM 0x20C
71915 +#define HDMI_CORE_AV_AUD_DBYTE(n) (n * 4 + 0x210)
71916 +#define HDMI_CORE_AV_MPEG_TYPE 0x280
71917 +#define HDMI_CORE_AV_MPEG_VERS 0x284
71918 +#define HDMI_CORE_AV_MPEG_LEN 0x288
71919 +#define HDMI_CORE_AV_MPEG_CHSUM 0x28C
71920 +#define HDMI_CORE_AV_MPEG_DBYTE(n) (n * 4 + 0x290)
71921 +#define HDMI_CORE_AV_GEN_DBYTE(n) (n * 4 + 0x300)
71922 +#define HDMI_CORE_AV_CP_BYTE1 0x37C
71923 +#define HDMI_CORE_AV_GEN2_DBYTE(n) (n * 4 + 0x380)
71924 +#define HDMI_CORE_AV_CEC_ADDR_ID 0x3FC
71925 +
71926 +#define HDMI_CORE_AV_SPD_DBYTE_ELSIZE 0x4
71927 +#define HDMI_CORE_AV_GEN2_DBYTE_ELSIZE 0x4
71928 +#define HDMI_CORE_AV_MPEG_DBYTE_ELSIZE 0x4
71929 +#define HDMI_CORE_AV_GEN_DBYTE_ELSIZE 0x4
71930 +
71931 +#define HDMI_CORE_AV_AVI_DBYTE_NELEMS 15
71932 +#define HDMI_CORE_AV_SPD_DBYTE_NELEMS 27
71933 +#define HDMI_CORE_AV_AUD_DBYTE_NELEMS 10
71934 +#define HDMI_CORE_AV_MPEG_DBYTE_NELEMS 27
71935 +#define HDMI_CORE_AV_GEN_DBYTE_NELEMS 31
71936 +#define HDMI_CORE_AV_GEN2_DBYTE_NELEMS 31
71937 +
71938 +enum hdmi_core_inputbus_width {
71939 + HDMI_INPUT_8BIT = 0,
71940 + HDMI_INPUT_10BIT = 1,
71941 + HDMI_INPUT_12BIT = 2
71942 +};
71943 +
71944 +enum hdmi_core_dither_trunc {
71945 + HDMI_OUTPUTTRUNCATION_8BIT = 0,
71946 + HDMI_OUTPUTTRUNCATION_10BIT = 1,
71947 + HDMI_OUTPUTTRUNCATION_12BIT = 2,
71948 + HDMI_OUTPUTDITHER_8BIT = 3,
71949 + HDMI_OUTPUTDITHER_10BIT = 4,
71950 + HDMI_OUTPUTDITHER_12BIT = 5
71951 +};
71952 +
71953 +enum hdmi_core_deepcolor_ed {
71954 + HDMI_DEEPCOLORPACKECTDISABLE = 0,
71955 + HDMI_DEEPCOLORPACKECTENABLE = 1
71956 +};
71957 +
71958 +enum hdmi_core_packet_mode {
71959 + HDMI_PACKETMODERESERVEDVALUE = 0,
71960 + HDMI_PACKETMODE24BITPERPIXEL = 4,
71961 + HDMI_PACKETMODE30BITPERPIXEL = 5,
71962 + HDMI_PACKETMODE36BITPERPIXEL = 6,
71963 + HDMI_PACKETMODE48BITPERPIXEL = 7
71964 +};
71965 +
71966 +enum hdmi_core_tclkselclkmult {
71967 + HDMI_FPLL05IDCK = 0,
71968 + HDMI_FPLL10IDCK = 1,
71969 + HDMI_FPLL20IDCK = 2,
71970 + HDMI_FPLL40IDCK = 3
71971 +};
71972 +
71973 +enum hdmi_core_packet_ctrl {
71974 + HDMI_PACKETENABLE = 1,
71975 + HDMI_PACKETDISABLE = 0,
71976 + HDMI_PACKETREPEATON = 1,
71977 + HDMI_PACKETREPEATOFF = 0
71978 +};
71979 +
71980 +enum hdmi_audio_i2s_config {
71981 + HDMI_AUDIO_I2S_MSB_SHIFTED_FIRST = 0,
71982 + HDMI_AUDIO_I2S_LSB_SHIFTED_FIRST = 1,
71983 + HDMI_AUDIO_I2S_SCK_EDGE_FALLING = 0,
71984 + HDMI_AUDIO_I2S_SCK_EDGE_RISING = 1,
71985 + HDMI_AUDIO_I2S_VBIT_FOR_PCM = 0,
71986 + HDMI_AUDIO_I2S_VBIT_FOR_COMPRESSED = 1,
71987 + HDMI_AUDIO_I2S_FIRST_BIT_SHIFT = 0,
71988 + HDMI_AUDIO_I2S_FIRST_BIT_NO_SHIFT = 1,
71989 + HDMI_AUDIO_I2S_SD0_EN = 1,
71990 + HDMI_AUDIO_I2S_SD1_EN = 1 << 1,
71991 + HDMI_AUDIO_I2S_SD2_EN = 1 << 2,
71992 + HDMI_AUDIO_I2S_SD3_EN = 1 << 3,
71993 +};
71994 +
71995 +struct hdmi_core_video_config {
71996 + enum hdmi_core_inputbus_width ip_bus_width;
71997 + enum hdmi_core_dither_trunc op_dither_truc;
71998 + enum hdmi_core_deepcolor_ed deep_color_pkt;
71999 + enum hdmi_core_packet_mode pkt_mode;
72000 + enum hdmi_core_hdmi_dvi hdmi_dvi;
72001 + enum hdmi_core_tclkselclkmult tclk_sel_clkmult;
72002 +};
72003 +
72004 +struct hdmi_core_packet_enable_repeat {
72005 + u32 audio_pkt;
72006 + u32 audio_pkt_repeat;
72007 + u32 avi_infoframe;
72008 + u32 avi_infoframe_repeat;
72009 + u32 gen_cntrl_pkt;
72010 + u32 gen_cntrl_pkt_repeat;
72011 + u32 generic_pkt;
72012 + u32 generic_pkt_repeat;
72013 +};
72014 +
72015 +int hdmi4_read_edid(struct hdmi_core_data *core, u8 *edid, int len);
72016 +void hdmi4_configure(struct hdmi_core_data *core, struct hdmi_wp_data *wp,
72017 + struct hdmi_config *cfg);
72018 +void hdmi4_core_dump(struct hdmi_core_data *core, struct seq_file *s);
72019 +int hdmi4_core_init(struct platform_device *pdev, struct hdmi_core_data *core);
72020 +
72021 +#if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO)
72022 +int hdmi4_audio_start(struct hdmi_core_data *core, struct hdmi_wp_data *wp);
72023 +void hdmi4_audio_stop(struct hdmi_core_data *core, struct hdmi_wp_data *wp);
72024 +int hdmi4_audio_config(struct hdmi_core_data *core, struct hdmi_wp_data *wp,
72025 + struct omap_dss_audio *audio, u32 pclk);
72026 +int hdmi4_audio_get_dma_port(u32 *offset, u32 *size);
72027 +#endif
72028 +
72029 +#endif
72030 --- /dev/null
72031 +++ b/drivers/video/omap2/dss/hdmi5.c
72032 @@ -0,0 +1,786 @@
72033 +/*
72034 + * hdmi.c
72035 + *
72036 + * HDMI interface DSS driver setting for TI's OMAP4 family of processor.
72037 + * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
72038 + * Authors: Yong Zhi
72039 + * Mythri pk <mythripk@ti.com>
72040 + *
72041 + * This program is free software; you can redistribute it and/or modify it
72042 + * under the terms of the GNU General Public License version 2 as published by
72043 + * the Free Software Foundation.
72044 + *
72045 + * This program is distributed in the hope that it will be useful, but WITHOUT
72046 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
72047 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
72048 + * more details.
72049 + *
72050 + * You should have received a copy of the GNU General Public License along with
72051 + * this program. If not, see <http://www.gnu.org/licenses/>.
72052 + */
72053 +
72054 +#define DSS_SUBSYS_NAME "HDMI"
72055 +
72056 +#include <linux/kernel.h>
72057 +#include <linux/module.h>
72058 +#include <linux/err.h>
72059 +#include <linux/io.h>
72060 +#include <linux/interrupt.h>
72061 +#include <linux/mutex.h>
72062 +#include <linux/delay.h>
72063 +#include <linux/string.h>
72064 +#include <linux/platform_device.h>
72065 +#include <linux/pm_runtime.h>
72066 +#include <linux/clk.h>
72067 +#include <linux/gpio.h>
72068 +#include <linux/regulator/consumer.h>
72069 +#include <video/omapdss.h>
72070 +
72071 +#include "hdmi5_core.h"
72072 +#include "dss.h"
72073 +#include "dss_features.h"
72074 +
72075 +static struct {
72076 + struct mutex lock;
72077 + struct platform_device *pdev;
72078 +
72079 + struct hdmi_wp_data wp;
72080 + struct hdmi_pll_data pll;
72081 + struct hdmi_phy_data phy;
72082 + struct hdmi_core_data core;
72083 +
72084 + struct hdmi_config cfg;
72085 +
72086 + struct clk *sys_clk;
72087 + struct regulator *vdda_hdmi_dac_reg;
72088 +
72089 + bool core_enabled;
72090 +
72091 + struct omap_dss_device output;
72092 +} hdmi;
72093 +
72094 +static int hdmi_runtime_get(void)
72095 +{
72096 + int r;
72097 +
72098 + DSSDBG("hdmi_runtime_get\n");
72099 +
72100 + r = pm_runtime_get_sync(&hdmi.pdev->dev);
72101 + WARN_ON(r < 0);
72102 + if (r < 0)
72103 + return r;
72104 +
72105 + return 0;
72106 +}
72107 +
72108 +static void hdmi_runtime_put(void)
72109 +{
72110 + int r;
72111 +
72112 + DSSDBG("hdmi_runtime_put\n");
72113 +
72114 + r = pm_runtime_put_sync(&hdmi.pdev->dev);
72115 + WARN_ON(r < 0 && r != -ENOSYS);
72116 +}
72117 +
72118 +static irqreturn_t hdmi_irq_handler(int irq, void *data)
72119 +{
72120 + struct hdmi_wp_data *wp = data;
72121 + u32 irqstatus;
72122 +
72123 + irqstatus = hdmi_wp_get_irqstatus(wp);
72124 + hdmi_wp_set_irqstatus(wp, irqstatus);
72125 +
72126 + if ((irqstatus & HDMI_IRQ_LINK_CONNECT) &&
72127 + irqstatus & HDMI_IRQ_LINK_DISCONNECT) {
72128 + u32 v;
72129 + /*
72130 + * If we get both connect and disconnect interrupts at the same
72131 + * time, turn off the PHY, clear interrupts, and restart, which
72132 + * raises connect interrupt if a cable is connected, or nothing
72133 + * if cable is not connected.
72134 + */
72135 +
72136 + hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_OFF);
72137 +
72138 + /*
72139 + * We always get bogus CONNECT & DISCONNECT interrupts when
72140 + * setting the PHY to LDOON. To ignore those, we force the RXDET
72141 + * line to 0 until the PHY power state has been changed.
72142 + */
72143 + v = hdmi_read_reg(hdmi.phy.base, HDMI_TXPHY_PAD_CFG_CTRL);
72144 + v = FLD_MOD(v, 1, 15, 15); /* FORCE_RXDET_HIGH */
72145 + v = FLD_MOD(v, 0, 14, 7); /* RXDET_LINE */
72146 + hdmi_write_reg(hdmi.phy.base, HDMI_TXPHY_PAD_CFG_CTRL, v);
72147 +
72148 + hdmi_wp_set_irqstatus(wp, HDMI_IRQ_LINK_CONNECT |
72149 + HDMI_IRQ_LINK_DISCONNECT);
72150 +
72151 + hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON);
72152 +
72153 + REG_FLD_MOD(hdmi.phy.base, HDMI_TXPHY_PAD_CFG_CTRL, 0, 15, 15);
72154 +
72155 + } else if (irqstatus & HDMI_IRQ_LINK_CONNECT) {
72156 + hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_TXON);
72157 + } else if (irqstatus & HDMI_IRQ_LINK_DISCONNECT) {
72158 + hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON);
72159 + }
72160 +
72161 + return IRQ_HANDLED;
72162 +}
72163 +
72164 +static int hdmi_init_regulator(void)
72165 +{
72166 + int r;
72167 + struct regulator *reg;
72168 +
72169 + if (hdmi.vdda_hdmi_dac_reg != NULL)
72170 + return 0;
72171 +
72172 + reg = devm_regulator_get(&hdmi.pdev->dev, "vdda_hdmi_dac");
72173 + if (IS_ERR(reg)) {
72174 + DSSERR("can't get VDDA_HDMI_DAC regulator\n");
72175 + return PTR_ERR(reg);
72176 + }
72177 +
72178 + r = regulator_set_voltage(reg, 1500000, 1800000);
72179 + if (r)
72180 + DSSWARN("can't set the regulator voltage");
72181 +
72182 + hdmi.vdda_hdmi_dac_reg = reg;
72183 +
72184 + return 0;
72185 +}
72186 +
72187 +static int hdmi_power_on_core(struct omap_dss_device *dssdev)
72188 +{
72189 + int r;
72190 +
72191 + r = regulator_enable(hdmi.vdda_hdmi_dac_reg);
72192 + if (r)
72193 + return r;
72194 +
72195 + r = hdmi_runtime_get();
72196 + if (r)
72197 + goto err_runtime_get;
72198 +
72199 + /* Make selection of HDMI in DSS */
72200 + dss_select_hdmi_venc_clk_source(DSS_HDMI_M_PCLK);
72201 +
72202 + hdmi.core_enabled = true;
72203 +
72204 + return 0;
72205 +
72206 +err_runtime_get:
72207 + regulator_disable(hdmi.vdda_hdmi_dac_reg);
72208 +
72209 + return r;
72210 +}
72211 +
72212 +static void hdmi_power_off_core(struct omap_dss_device *dssdev)
72213 +{
72214 + hdmi.core_enabled = false;
72215 +
72216 + hdmi_runtime_put();
72217 + regulator_disable(hdmi.vdda_hdmi_dac_reg);
72218 +}
72219 +
72220 +static int hdmi_power_on_full(struct omap_dss_device *dssdev)
72221 +{
72222 + int r;
72223 + struct omap_video_timings *p;
72224 + struct omap_overlay_manager *mgr = hdmi.output.manager;
72225 + unsigned long phy;
72226 +
72227 + r = hdmi_power_on_core(dssdev);
72228 + if (r)
72229 + return r;
72230 +
72231 + p = &hdmi.cfg.timings;
72232 +
72233 + DSSDBG("hdmi_power_on x_res= %d y_res = %d\n", p->x_res, p->y_res);
72234 +
72235 + phy = p->pixel_clock;
72236 +
72237 + hdmi_pll_compute(&hdmi.pll, clk_get_rate(hdmi.sys_clk), phy);
72238 +
72239 + /* disable and clear irqs */
72240 + hdmi_wp_clear_irqenable(&hdmi.wp, 0xffffffff);
72241 + hdmi_wp_set_irqstatus(&hdmi.wp,
72242 + hdmi_wp_get_irqstatus(&hdmi.wp));
72243 +
72244 + /* config the PLL and PHY hdmi_set_pll_pwrfirst */
72245 + r = hdmi_pll_enable(&hdmi.pll, &hdmi.wp);
72246 + if (r) {
72247 + DSSDBG("Failed to lock PLL\n");
72248 + goto err_pll_enable;
72249 + }
72250 +
72251 + r = hdmi_phy_configure(&hdmi.phy, &hdmi.cfg);
72252 + if (r) {
72253 + DSSDBG("Failed to start PHY\n");
72254 + goto err_phy_cfg;
72255 + }
72256 +
72257 + r = hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_LDOON);
72258 + if (r)
72259 + goto err_phy_pwr;
72260 +
72261 + hdmi5_configure(&hdmi.core, &hdmi.wp, &hdmi.cfg);
72262 +
72263 + /* bypass TV gamma table */
72264 + dispc_enable_gamma_table(0);
72265 +
72266 + /* tv size */
72267 + dss_mgr_set_timings(mgr, p);
72268 +
72269 + r = hdmi_wp_video_start(&hdmi.wp);
72270 + if (r)
72271 + goto err_vid_enable;
72272 +
72273 + r = dss_mgr_enable(mgr);
72274 + if (r)
72275 + goto err_mgr_enable;
72276 +
72277 + hdmi_wp_set_irqenable(&hdmi.wp,
72278 + HDMI_IRQ_LINK_CONNECT | HDMI_IRQ_LINK_DISCONNECT);
72279 +
72280 + return 0;
72281 +
72282 +err_mgr_enable:
72283 + hdmi_wp_video_stop(&hdmi.wp);
72284 +err_vid_enable:
72285 + hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_OFF);
72286 +err_phy_pwr:
72287 +err_phy_cfg:
72288 + hdmi_pll_disable(&hdmi.pll, &hdmi.wp);
72289 +err_pll_enable:
72290 + hdmi_power_off_core(dssdev);
72291 + return -EIO;
72292 +}
72293 +
72294 +static void hdmi_power_off_full(struct omap_dss_device *dssdev)
72295 +{
72296 + struct omap_overlay_manager *mgr = hdmi.output.manager;
72297 +
72298 + hdmi_wp_clear_irqenable(&hdmi.wp, 0xffffffff);
72299 +
72300 + dss_mgr_disable(mgr);
72301 +
72302 + hdmi_wp_video_stop(&hdmi.wp);
72303 +
72304 + hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_OFF);
72305 +
72306 + hdmi_pll_disable(&hdmi.pll, &hdmi.wp);
72307 +
72308 + hdmi_power_off_core(dssdev);
72309 +}
72310 +
72311 +static int hdmi_display_check_timing(struct omap_dss_device *dssdev,
72312 + struct omap_video_timings *timings)
72313 +{
72314 + struct hdmi_cm cm;
72315 +
72316 + cm = hdmi_get_code(timings);
72317 + if (cm.code == -1) {
72318 + return -EINVAL;
72319 + }
72320 +
72321 + return 0;
72322 +
72323 +}
72324 +
72325 +static void hdmi_display_set_timing(struct omap_dss_device *dssdev,
72326 + struct omap_video_timings *timings)
72327 +{
72328 + struct hdmi_cm cm;
72329 + const struct hdmi_config *t;
72330 +
72331 + mutex_lock(&hdmi.lock);
72332 +
72333 + cm = hdmi_get_code(timings);
72334 + hdmi.cfg.cm = cm;
72335 +
72336 + t = hdmi_get_timings(cm.mode, cm.code);
72337 + if (t != NULL) {
72338 + hdmi.cfg = *t;
72339 +
72340 + dispc_set_tv_pclk(t->timings.pixel_clock * 1000);
72341 + }
72342 +
72343 + mutex_unlock(&hdmi.lock);
72344 +}
72345 +
72346 +static void hdmi_display_get_timings(struct omap_dss_device *dssdev,
72347 + struct omap_video_timings *timings)
72348 +{
72349 + const struct hdmi_config *cfg;
72350 + struct hdmi_cm cm = hdmi.cfg.cm;
72351 +
72352 + cfg = hdmi_get_timings(cm.mode, cm.code);
72353 + if (cfg == NULL)
72354 + cfg = hdmi_default_timing();
72355 +
72356 + memcpy(timings, &cfg->timings, sizeof(cfg->timings));
72357 +}
72358 +
72359 +static void hdmi_dump_regs(struct seq_file *s)
72360 +{
72361 + mutex_lock(&hdmi.lock);
72362 +
72363 + if (hdmi_runtime_get()) {
72364 + mutex_unlock(&hdmi.lock);
72365 + return;
72366 + }
72367 +
72368 + hdmi_wp_dump(&hdmi.wp, s);
72369 + hdmi_pll_dump(&hdmi.pll, s);
72370 + hdmi_phy_dump(&hdmi.phy, s);
72371 + hdmi5_core_dump(&hdmi.core, s);
72372 +
72373 + hdmi_runtime_put();
72374 + mutex_unlock(&hdmi.lock);
72375 +}
72376 +
72377 +static int read_edid(u8 *buf, int len)
72378 +{
72379 + int r;
72380 + int idlemode;
72381 +
72382 + mutex_lock(&hdmi.lock);
72383 +
72384 + r = hdmi_runtime_get();
72385 + BUG_ON(r);
72386 +
72387 + idlemode = REG_GET(hdmi.wp.base, HDMI_WP_SYSCONFIG, 3, 2);
72388 + /* No-idle mode */
72389 + REG_FLD_MOD(hdmi.wp.base, HDMI_WP_SYSCONFIG, 1, 3, 2);
72390 +
72391 + r = hdmi5_read_edid(&hdmi.core, buf, len);
72392 +
72393 + REG_FLD_MOD(hdmi.wp.base, HDMI_WP_SYSCONFIG, idlemode, 3, 2);
72394 +
72395 + hdmi_runtime_put();
72396 + mutex_unlock(&hdmi.lock);
72397 +
72398 + return r;
72399 +}
72400 +
72401 +static int hdmi_display_enable(struct omap_dss_device *dssdev)
72402 +{
72403 + struct omap_dss_device *out = &hdmi.output;
72404 + int r = 0;
72405 +
72406 + DSSDBG("ENTER hdmi_display_enable\n");
72407 +
72408 + mutex_lock(&hdmi.lock);
72409 +
72410 + if (out == NULL || out->manager == NULL) {
72411 + DSSERR("failed to enable display: no output/manager\n");
72412 + r = -ENODEV;
72413 + goto err0;
72414 + }
72415 +
72416 + r = hdmi_power_on_full(dssdev);
72417 + if (r) {
72418 + DSSERR("failed to power on device\n");
72419 + goto err0;
72420 + }
72421 +
72422 + mutex_unlock(&hdmi.lock);
72423 + return 0;
72424 +
72425 +err0:
72426 + mutex_unlock(&hdmi.lock);
72427 + return r;
72428 +}
72429 +
72430 +static void hdmi_display_disable(struct omap_dss_device *dssdev)
72431 +{
72432 + DSSDBG("Enter hdmi_display_disable\n");
72433 +
72434 + mutex_lock(&hdmi.lock);
72435 +
72436 + hdmi_power_off_full(dssdev);
72437 +
72438 + mutex_unlock(&hdmi.lock);
72439 +}
72440 +
72441 +static int hdmi_core_enable(struct omap_dss_device *dssdev)
72442 +{
72443 + int r = 0;
72444 +
72445 + DSSDBG("ENTER omapdss_hdmi_core_enable\n");
72446 +
72447 + mutex_lock(&hdmi.lock);
72448 +
72449 + r = hdmi_power_on_core(dssdev);
72450 + if (r) {
72451 + DSSERR("failed to power on device\n");
72452 + goto err0;
72453 + }
72454 +
72455 + mutex_unlock(&hdmi.lock);
72456 + return 0;
72457 +
72458 +err0:
72459 + mutex_unlock(&hdmi.lock);
72460 + return r;
72461 +}
72462 +
72463 +static void hdmi_core_disable(struct omap_dss_device *dssdev)
72464 +{
72465 + DSSDBG("Enter omapdss_hdmi_core_disable\n");
72466 +
72467 + mutex_lock(&hdmi.lock);
72468 +
72469 + hdmi_power_off_core(dssdev);
72470 +
72471 + mutex_unlock(&hdmi.lock);
72472 +}
72473 +
72474 +static int hdmi_get_clocks(struct platform_device *pdev)
72475 +{
72476 + struct clk *clk;
72477 +
72478 + clk = devm_clk_get(&pdev->dev, "sys_clk");
72479 + if (IS_ERR(clk)) {
72480 + DSSERR("can't get sys_clk\n");
72481 + return PTR_ERR(clk);
72482 + }
72483 +
72484 + hdmi.sys_clk = clk;
72485 +
72486 + return 0;
72487 +}
72488 +
72489 +static int hdmi_connect(struct omap_dss_device *dssdev,
72490 + struct omap_dss_device *dst)
72491 +{
72492 + struct omap_overlay_manager *mgr;
72493 + int r;
72494 +
72495 + r = hdmi_init_regulator();
72496 + if (r)
72497 + return r;
72498 +
72499 + mgr = omap_dss_get_overlay_manager(dssdev->dispc_channel);
72500 + if (!mgr)
72501 + return -ENODEV;
72502 +
72503 + r = dss_mgr_connect(mgr, dssdev);
72504 + if (r)
72505 + return r;
72506 +
72507 + r = omapdss_output_set_device(dssdev, dst);
72508 + if (r) {
72509 + DSSERR("failed to connect output to new device: %s\n",
72510 + dst->name);
72511 + dss_mgr_disconnect(mgr, dssdev);
72512 + return r;
72513 + }
72514 +
72515 + return 0;
72516 +}
72517 +
72518 +static void hdmi_disconnect(struct omap_dss_device *dssdev,
72519 + struct omap_dss_device *dst)
72520 +{
72521 + WARN_ON(dst != dssdev->dst);
72522 +
72523 + if (dst != dssdev->dst)
72524 + return;
72525 +
72526 + omapdss_output_unset_device(dssdev);
72527 +
72528 + if (dssdev->manager)
72529 + dss_mgr_disconnect(dssdev->manager, dssdev);
72530 +}
72531 +
72532 +static int hdmi_read_edid(struct omap_dss_device *dssdev,
72533 + u8 *edid, int len)
72534 +{
72535 + bool need_enable;
72536 + int r;
72537 +
72538 + need_enable = hdmi.core_enabled == false;
72539 +
72540 + if (need_enable) {
72541 + r = hdmi_core_enable(dssdev);
72542 + if (r)
72543 + return r;
72544 + }
72545 +
72546 + r = read_edid(edid, len);
72547 +
72548 + if (need_enable)
72549 + hdmi_core_disable(dssdev);
72550 +
72551 + return r;
72552 +}
72553 +
72554 +#if defined(CONFIG_OMAP5_DSS_HDMI_AUDIO)
72555 +static int hdmi_audio_enable(struct omap_dss_device *dssdev)
72556 +{
72557 + int r;
72558 +
72559 + mutex_lock(&hdmi.lock);
72560 +
72561 + if (!hdmi_mode_has_audio(hdmi.cfg.cm.mode)) {
72562 + r = -EPERM;
72563 + goto err;
72564 + }
72565 +
72566 + r = hdmi_wp_audio_enable(&hdmi.wp, true);
72567 + if (r)
72568 + goto err;
72569 +
72570 + mutex_unlock(&hdmi.lock);
72571 + return 0;
72572 +
72573 +err:
72574 + mutex_unlock(&hdmi.lock);
72575 + return r;
72576 +}
72577 +
72578 +static void hdmi_audio_disable(struct omap_dss_device *dssdev)
72579 +{
72580 + hdmi_wp_audio_enable(&hdmi.wp, false);
72581 +}
72582 +
72583 +static int hdmi_audio_start(struct omap_dss_device *dssdev)
72584 +{
72585 + return hdmi_wp_audio_core_req_enable(&hdmi.wp, true);
72586 +}
72587 +
72588 +static void hdmi_audio_stop(struct omap_dss_device *dssdev)
72589 +{
72590 + hdmi_wp_audio_core_req_enable(&hdmi.wp, false);
72591 +}
72592 +
72593 +static bool hdmi_audio_supported(struct omap_dss_device *dssdev)
72594 +{
72595 + bool r;
72596 +
72597 + mutex_lock(&hdmi.lock);
72598 +
72599 + r = hdmi_mode_has_audio(hdmi.cfg.cm.mode);
72600 +
72601 + mutex_unlock(&hdmi.lock);
72602 + return r;
72603 +}
72604 +
72605 +static int hdmi_audio_config(struct omap_dss_device *dssdev,
72606 + struct omap_dss_audio *audio)
72607 +{
72608 + int r;
72609 + u32 pclk = hdmi.cfg.timings.pixel_clock;
72610 +
72611 + mutex_lock(&hdmi.lock);
72612 +
72613 + if (!hdmi_mode_has_audio(hdmi.cfg.cm.mode)) {
72614 + r = -EPERM;
72615 + goto err;
72616 + }
72617 +
72618 + r = hdmi5_audio_config(&hdmi.core, &hdmi.wp, audio, pclk);
72619 + if (r)
72620 + goto err;
72621 +
72622 + mutex_unlock(&hdmi.lock);
72623 + return 0;
72624 +
72625 +err:
72626 + mutex_unlock(&hdmi.lock);
72627 + return r;
72628 +}
72629 +#else
72630 +static int hdmi_audio_enable(struct omap_dss_device *dssdev)
72631 +{
72632 + return -EPERM;
72633 +}
72634 +
72635 +static void hdmi_audio_disable(struct omap_dss_device *dssdev)
72636 +{
72637 +}
72638 +
72639 +static int hdmi_audio_start(struct omap_dss_device *dssdev)
72640 +{
72641 + return -EPERM;
72642 +}
72643 +
72644 +static void hdmi_audio_stop(struct omap_dss_device *dssdev)
72645 +{
72646 +}
72647 +
72648 +static bool hdmi_audio_supported(struct omap_dss_device *dssdev)
72649 +{
72650 + return false;
72651 +}
72652 +
72653 +static int hdmi_audio_config(struct omap_dss_device *dssdev,
72654 + struct omap_dss_audio *audio)
72655 +{
72656 + return -EPERM;
72657 +}
72658 +#endif
72659 +
72660 +static const struct omapdss_hdmi_ops hdmi_ops = {
72661 + .connect = hdmi_connect,
72662 + .disconnect = hdmi_disconnect,
72663 +
72664 + .enable = hdmi_display_enable,
72665 + .disable = hdmi_display_disable,
72666 +
72667 + .check_timings = hdmi_display_check_timing,
72668 + .set_timings = hdmi_display_set_timing,
72669 + .get_timings = hdmi_display_get_timings,
72670 +
72671 + .read_edid = hdmi_read_edid,
72672 +
72673 + .audio_enable = hdmi_audio_enable,
72674 + .audio_disable = hdmi_audio_disable,
72675 + .audio_start = hdmi_audio_start,
72676 + .audio_stop = hdmi_audio_stop,
72677 + .audio_supported = hdmi_audio_supported,
72678 + .audio_config = hdmi_audio_config,
72679 +};
72680 +
72681 +static void hdmi_init_output(struct platform_device *pdev)
72682 +{
72683 + struct omap_dss_device *out = &hdmi.output;
72684 +
72685 + out->dev = &pdev->dev;
72686 + out->id = OMAP_DSS_OUTPUT_HDMI;
72687 + out->output_type = OMAP_DISPLAY_TYPE_HDMI;
72688 + out->name = "hdmi.0";
72689 + out->dispc_channel = OMAP_DSS_CHANNEL_DIGIT;
72690 + out->ops.hdmi = &hdmi_ops;
72691 + out->owner = THIS_MODULE;
72692 +
72693 + omapdss_register_output(out);
72694 +}
72695 +
72696 +static void __exit hdmi_uninit_output(struct platform_device *pdev)
72697 +{
72698 + struct omap_dss_device *out = &hdmi.output;
72699 +
72700 + omapdss_unregister_output(out);
72701 +}
72702 +
72703 +/* HDMI HW IP initialisation */
72704 +static int omapdss_hdmihw_probe(struct platform_device *pdev)
72705 +{
72706 + int r;
72707 + int irq;
72708 +
72709 + hdmi.pdev = pdev;
72710 +
72711 + mutex_init(&hdmi.lock);
72712 +
72713 + r = hdmi_wp_init(pdev, &hdmi.wp);
72714 + if (r)
72715 + return r;
72716 +
72717 + r = hdmi_pll_init(pdev, &hdmi.pll);
72718 + if (r)
72719 + return r;
72720 +
72721 + r = hdmi_phy_init(pdev, &hdmi.phy);
72722 + if (r)
72723 + return r;
72724 +
72725 + r = hdmi5_core_init(pdev, &hdmi.core);
72726 + if (r)
72727 + return r;
72728 +
72729 + r = hdmi_get_clocks(pdev);
72730 + if (r) {
72731 + DSSERR("can't get clocks\n");
72732 + return r;
72733 + }
72734 +
72735 + irq = platform_get_irq(pdev, 0);
72736 + if (irq < 0) {
72737 + DSSERR("platform_get_irq failed\n");
72738 + return -ENODEV;
72739 + }
72740 +
72741 + r = devm_request_threaded_irq(&pdev->dev, irq,
72742 + NULL, hdmi_irq_handler,
72743 + IRQF_ONESHOT, "OMAP HDMI", &hdmi.wp);
72744 + if (r) {
72745 + DSSERR("HDMI IRQ request failed\n");
72746 + return r;
72747 + }
72748 +
72749 + pm_runtime_enable(&pdev->dev);
72750 +
72751 + hdmi_init_output(pdev);
72752 +
72753 + dss_debugfs_create_file("hdmi", hdmi_dump_regs);
72754 +
72755 + return 0;
72756 +}
72757 +
72758 +static int __exit omapdss_hdmihw_remove(struct platform_device *pdev)
72759 +{
72760 + hdmi_uninit_output(pdev);
72761 +
72762 + pm_runtime_disable(&pdev->dev);
72763 +
72764 + return 0;
72765 +}
72766 +
72767 +static int hdmi_runtime_suspend(struct device *dev)
72768 +{
72769 + clk_disable_unprepare(hdmi.sys_clk);
72770 +
72771 + dispc_runtime_put();
72772 +
72773 + return 0;
72774 +}
72775 +
72776 +static int hdmi_runtime_resume(struct device *dev)
72777 +{
72778 + int r;
72779 +
72780 + r = dispc_runtime_get();
72781 + if (r < 0)
72782 + return r;
72783 +
72784 + clk_prepare_enable(hdmi.sys_clk);
72785 +
72786 + return 0;
72787 +}
72788 +
72789 +static const struct dev_pm_ops hdmi_pm_ops = {
72790 + .runtime_suspend = hdmi_runtime_suspend,
72791 + .runtime_resume = hdmi_runtime_resume,
72792 +};
72793 +
72794 +static const struct of_device_id hdmi_of_match[] = {
72795 + { .compatible = "ti,omap5-hdmi", },
72796 + {},
72797 +};
72798 +
72799 +static struct platform_driver omapdss_hdmihw_driver = {
72800 + .probe = omapdss_hdmihw_probe,
72801 + .remove = __exit_p(omapdss_hdmihw_remove),
72802 + .driver = {
72803 + .name = "omapdss_hdmi5",
72804 + .owner = THIS_MODULE,
72805 + .pm = &hdmi_pm_ops,
72806 + .of_match_table = hdmi_of_match,
72807 + },
72808 +};
72809 +
72810 +int __init hdmi5_init_platform_driver(void)
72811 +{
72812 + return platform_driver_register(&omapdss_hdmihw_driver);
72813 +}
72814 +
72815 +void __exit hdmi5_uninit_platform_driver(void)
72816 +{
72817 + platform_driver_unregister(&omapdss_hdmihw_driver);
72818 +}
72819 --- /dev/null
72820 +++ b/drivers/video/omap2/dss/hdmi5_core.c
72821 @@ -0,0 +1,915 @@
72822 +/*
72823 + * OMAP5 HDMI CORE IP driver Library
72824 + * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
72825 + * Author: Mythri pk <mythripk@ti.com>
72826 + * This program is free software; you can redistribute it and/or modify it
72827 + * under the terms of the GNU General Public License version 2 as published by
72828 + * the Free Software Foundation.
72829 + *
72830 + * This program is distributed in the hope that it will be useful, but WITHOUT
72831 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
72832 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
72833 + * more details.
72834 + *
72835 + * You should have received a copy of the GNU General Public License along with
72836 + * this program. If not, see <http://www.gnu.org/licenses/>.
72837 + */
72838 +
72839 +#include <linux/kernel.h>
72840 +#include <linux/module.h>
72841 +#include <linux/err.h>
72842 +#include <linux/io.h>
72843 +#include <linux/delay.h>
72844 +#include <linux/string.h>
72845 +#include <linux/seq_file.h>
72846 +#include <drm/drm_edid.h>
72847 +#if defined(CONFIG_OMAP5_DSS_HDMI_AUDIO)
72848 +#include <sound/asound.h>
72849 +#include <sound/asoundef.h>
72850 +#endif
72851 +
72852 +#include "hdmi5_core.h"
72853 +
72854 +/* only 24 bit color depth used for now */
72855 +static const struct csc_table csc_table_deepcolor[] = {
72856 + /* HDMI_DEEP_COLOR_24BIT */
72857 + [0] = { 7036, 0, 0, 32, 0, 7036, 0, 32, 0, 0, 7036, 32, },
72858 + /* HDMI_DEEP_COLOR_30BIT */
72859 + [1] = { 7015, 0, 0, 128, 0, 7015, 0, 128, 0, 0, 7015, 128, },
72860 + /* HDMI_DEEP_COLOR_36BIT */
72861 + [2] = { 7010, 0, 0, 512, 0, 7010, 0, 512, 0, 0, 7010, 512, },
72862 + /* FULL RANGE */
72863 + [3] = { 8192, 0, 0, 0, 0, 8192, 0, 0, 0, 0, 8192, 0, },
72864 +};
72865 +
72866 +static void hdmi_core_ddc_init(struct hdmi_core_data *core)
72867 +{
72868 + void __iomem *base = core->base;
72869 + const unsigned long long iclk = 266000000; /* DSS L3 ICLK */
72870 + const unsigned ss_scl_high = 4000; /* ns */
72871 + const unsigned ss_scl_low = 4700; /* ns */
72872 + const unsigned fs_scl_high = 600; /* ns */
72873 + const unsigned fs_scl_low = 1300; /* ns */
72874 + const unsigned sda_hold = 300; /* ns */
72875 + const unsigned sfr_div = 10;
72876 + unsigned long long sfr;
72877 + unsigned v;
72878 +
72879 + sfr = iclk / sfr_div; /* SFR_DIV */
72880 + sfr /= 1000; /* SFR clock in kHz */
72881 +
72882 + /* Reset */
72883 + REG_FLD_MOD(base, HDMI_CORE_I2CM_SOFTRSTZ, 0, 0, 0);
72884 + if (hdmi_wait_for_bit_change(base, HDMI_CORE_I2CM_SOFTRSTZ,
72885 + 0, 0, 1) != 1)
72886 + DSSERR("HDMI I2CM reset failed\n");
72887 +
72888 + /* Standard (0) or Fast (1) Mode */
72889 + REG_FLD_MOD(base, HDMI_CORE_I2CM_DIV, 0, 3, 3);
72890 +
72891 + /* Standard Mode SCL High counter */
72892 + v = DIV_ROUND_UP_ULL(ss_scl_high * sfr, 1000000);
72893 + REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_HCNT_1_ADDR,
72894 + (v >> 8) & 0xff, 7, 0);
72895 + REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_HCNT_0_ADDR,
72896 + v & 0xff, 7, 0);
72897 +
72898 + /* Standard Mode SCL Low counter */
72899 + v = DIV_ROUND_UP_ULL(ss_scl_low * sfr, 1000000);
72900 + REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_LCNT_1_ADDR,
72901 + (v >> 8) & 0xff, 7, 0);
72902 + REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_LCNT_0_ADDR,
72903 + v & 0xff, 7, 0);
72904 +
72905 + /* Fast Mode SCL High Counter */
72906 + v = DIV_ROUND_UP_ULL(fs_scl_high * sfr, 1000000);
72907 + REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_HCNT_1_ADDR,
72908 + (v >> 8) & 0xff, 7, 0);
72909 + REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_HCNT_0_ADDR,
72910 + v & 0xff, 7, 0);
72911 +
72912 + /* Fast Mode SCL Low Counter */
72913 + v = DIV_ROUND_UP_ULL(fs_scl_low * sfr, 1000000);
72914 + REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_LCNT_1_ADDR,
72915 + (v >> 8) & 0xff, 7, 0);
72916 + REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_LCNT_0_ADDR,
72917 + v & 0xff, 7, 0);
72918 +
72919 + /* SDA Hold Time */
72920 + v = DIV_ROUND_UP_ULL(sda_hold * sfr, 1000000);
72921 + REG_FLD_MOD(base, HDMI_CORE_I2CM_SDA_HOLD_ADDR, v & 0xff, 7, 0);
72922 +
72923 + REG_FLD_MOD(base, HDMI_CORE_I2CM_SLAVE, 0x50, 6, 0);
72924 + REG_FLD_MOD(base, HDMI_CORE_I2CM_SEGADDR, 0x30, 6, 0);
72925 +
72926 + /* NACK_POL to high */
72927 + REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 7, 7);
72928 +
72929 + /* NACK_MASK to unmasked */
72930 + REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x0, 6, 6);
72931 +
72932 + /* ARBITRATION_POL to high */
72933 + REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 3, 3);
72934 +
72935 + /* ARBITRATION_MASK to unmasked */
72936 + REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x0, 2, 2);
72937 +
72938 + /* DONE_POL to high */
72939 + REG_FLD_MOD(base, HDMI_CORE_I2CM_INT, 0x1, 3, 3);
72940 +
72941 + /* DONE_MASK to unmasked */
72942 + REG_FLD_MOD(base, HDMI_CORE_I2CM_INT, 0x0, 2, 2);
72943 +}
72944 +
72945 +static void hdmi_core_ddc_uninit(struct hdmi_core_data *core)
72946 +{
72947 + void __iomem *base = core->base;
72948 +
72949 + /* Mask I2C interrupts */
72950 + REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 6, 6);
72951 + REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 2, 2);
72952 + REG_FLD_MOD(base, HDMI_CORE_I2CM_INT, 0x1, 2, 2);
72953 +}
72954 +
72955 +static int hdmi_core_ddc_edid(struct hdmi_core_data *core, u8 *pedid, u8 ext)
72956 +{
72957 + void __iomem *base = core->base;
72958 + u8 cur_addr;
72959 + char checksum = 0;
72960 + const int retries = 1000;
72961 + u8 seg_ptr = ext / 2;
72962 + u8 edidbase = ((ext % 2) * 0x80);
72963 +
72964 + REG_FLD_MOD(base, HDMI_CORE_I2CM_SEGPTR, seg_ptr, 7, 0);
72965 +
72966 + /*
72967 + * TODO: We use polling here, although we probably should use proper
72968 + * interrupts.
72969 + */
72970 + for (cur_addr = 0; cur_addr < 128; ++cur_addr) {
72971 + int i;
72972 +
72973 + /* clear ERROR and DONE */
72974 + REG_FLD_MOD(base, HDMI_CORE_IH_I2CM_STAT0, 0x3, 1, 0);
72975 +
72976 + REG_FLD_MOD(base, HDMI_CORE_I2CM_ADDRESS,
72977 + edidbase + cur_addr, 7, 0);
72978 +
72979 + if (seg_ptr)
72980 + REG_FLD_MOD(base, HDMI_CORE_I2CM_OPERATION, 1, 1, 1);
72981 + else
72982 + REG_FLD_MOD(base, HDMI_CORE_I2CM_OPERATION, 1, 0, 0);
72983 +
72984 + for (i = 0; i < retries; ++i) {
72985 + u32 stat;
72986 +
72987 + stat = REG_GET(base, HDMI_CORE_IH_I2CM_STAT0, 1, 0);
72988 +
72989 + /* I2CM_ERROR */
72990 + if (stat & 1) {
72991 + DSSERR("HDMI I2C Master Error\n");
72992 + return -EIO;
72993 + }
72994 +
72995 + /* I2CM_DONE */
72996 + if (stat & (1 << 1))
72997 + break;
72998 +
72999 + usleep_range(250, 1000);
73000 + }
73001 +
73002 + if (i == retries) {
73003 + DSSERR("HDMI I2C timeout reading EDID\n");
73004 + return -EIO;
73005 + }
73006 +
73007 + pedid[cur_addr] = REG_GET(base, HDMI_CORE_I2CM_DATAI, 7, 0);
73008 + checksum += pedid[cur_addr];
73009 + }
73010 +
73011 + return 0;
73012 +
73013 +}
73014 +
73015 +int hdmi5_read_edid(struct hdmi_core_data *core, u8 *edid, int len)
73016 +{
73017 + int r, n, i;
73018 + int max_ext_blocks = (len / 128) - 1;
73019 +
73020 + if (len < 128)
73021 + return -EINVAL;
73022 +
73023 + hdmi_core_ddc_init(core);
73024 +
73025 + r = hdmi_core_ddc_edid(core, edid, 0);
73026 + if (r)
73027 + goto out;
73028 +
73029 + n = edid[0x7e];
73030 +
73031 + if (n > max_ext_blocks)
73032 + n = max_ext_blocks;
73033 +
73034 + for (i = 1; i <= n; i++) {
73035 + r = hdmi_core_ddc_edid(core, edid + i * EDID_LENGTH, i);
73036 + if (r)
73037 + goto out;
73038 + }
73039 +
73040 +out:
73041 + hdmi_core_ddc_uninit(core);
73042 +
73043 + return r;
73044 +}
73045 +
73046 +void hdmi5_core_dump(struct hdmi_core_data *core, struct seq_file *s)
73047 +{
73048 +
73049 +#define DUMPCORE(r) seq_printf(s, "%-35s %08x\n", #r,\
73050 + hdmi_read_reg(core->base, r))
73051 +
73052 + DUMPCORE(HDMI_CORE_FC_INVIDCONF);
73053 + DUMPCORE(HDMI_CORE_FC_INHACTIV0);
73054 + DUMPCORE(HDMI_CORE_FC_INHACTIV1);
73055 + DUMPCORE(HDMI_CORE_FC_INHBLANK0);
73056 + DUMPCORE(HDMI_CORE_FC_INHBLANK1);
73057 + DUMPCORE(HDMI_CORE_FC_INVACTIV0);
73058 + DUMPCORE(HDMI_CORE_FC_INVACTIV1);
73059 + DUMPCORE(HDMI_CORE_FC_INVBLANK);
73060 + DUMPCORE(HDMI_CORE_FC_HSYNCINDELAY0);
73061 + DUMPCORE(HDMI_CORE_FC_HSYNCINDELAY1);
73062 + DUMPCORE(HDMI_CORE_FC_HSYNCINWIDTH0);
73063 + DUMPCORE(HDMI_CORE_FC_HSYNCINWIDTH1);
73064 + DUMPCORE(HDMI_CORE_FC_VSYNCINDELAY);
73065 + DUMPCORE(HDMI_CORE_FC_VSYNCINWIDTH);
73066 + DUMPCORE(HDMI_CORE_FC_CTRLDUR);
73067 + DUMPCORE(HDMI_CORE_FC_EXCTRLDUR);
73068 + DUMPCORE(HDMI_CORE_FC_EXCTRLSPAC);
73069 + DUMPCORE(HDMI_CORE_FC_CH0PREAM);
73070 + DUMPCORE(HDMI_CORE_FC_CH1PREAM);
73071 + DUMPCORE(HDMI_CORE_FC_CH2PREAM);
73072 + DUMPCORE(HDMI_CORE_FC_AVICONF0);
73073 + DUMPCORE(HDMI_CORE_FC_AVICONF1);
73074 + DUMPCORE(HDMI_CORE_FC_AVICONF2);
73075 + DUMPCORE(HDMI_CORE_FC_AVIVID);
73076 + DUMPCORE(HDMI_CORE_FC_PRCONF);
73077 +
73078 + DUMPCORE(HDMI_CORE_MC_CLKDIS);
73079 + DUMPCORE(HDMI_CORE_MC_SWRSTZREQ);
73080 + DUMPCORE(HDMI_CORE_MC_FLOWCTRL);
73081 + DUMPCORE(HDMI_CORE_MC_PHYRSTZ);
73082 + DUMPCORE(HDMI_CORE_MC_LOCKONCLOCK);
73083 +
73084 + DUMPCORE(HDMI_CORE_I2CM_SLAVE);
73085 + DUMPCORE(HDMI_CORE_I2CM_ADDRESS);
73086 + DUMPCORE(HDMI_CORE_I2CM_DATAO);
73087 + DUMPCORE(HDMI_CORE_I2CM_DATAI);
73088 + DUMPCORE(HDMI_CORE_I2CM_OPERATION);
73089 + DUMPCORE(HDMI_CORE_I2CM_INT);
73090 + DUMPCORE(HDMI_CORE_I2CM_CTLINT);
73091 + DUMPCORE(HDMI_CORE_I2CM_DIV);
73092 + DUMPCORE(HDMI_CORE_I2CM_SEGADDR);
73093 + DUMPCORE(HDMI_CORE_I2CM_SOFTRSTZ);
73094 + DUMPCORE(HDMI_CORE_I2CM_SEGPTR);
73095 + DUMPCORE(HDMI_CORE_I2CM_SS_SCL_HCNT_1_ADDR);
73096 + DUMPCORE(HDMI_CORE_I2CM_SS_SCL_HCNT_0_ADDR);
73097 + DUMPCORE(HDMI_CORE_I2CM_SS_SCL_LCNT_1_ADDR);
73098 + DUMPCORE(HDMI_CORE_I2CM_SS_SCL_LCNT_0_ADDR);
73099 + DUMPCORE(HDMI_CORE_I2CM_FS_SCL_HCNT_1_ADDR);
73100 + DUMPCORE(HDMI_CORE_I2CM_FS_SCL_HCNT_0_ADDR);
73101 + DUMPCORE(HDMI_CORE_I2CM_FS_SCL_LCNT_1_ADDR);
73102 + DUMPCORE(HDMI_CORE_I2CM_FS_SCL_LCNT_0_ADDR);
73103 + DUMPCORE(HDMI_CORE_I2CM_SDA_HOLD_ADDR);
73104 +}
73105 +
73106 +static void hdmi_core_init(struct hdmi_core_vid_config *video_cfg,
73107 + struct hdmi_core_infoframe_avi *avi_cfg,
73108 + struct hdmi_config *cfg)
73109 +{
73110 + DSSDBG("hdmi_core_init\n");
73111 +
73112 + /* video core */
73113 + video_cfg->data_enable_pol = 1; /* It is always 1*/
73114 + video_cfg->v_fc_config.timings.hsync_level = cfg->timings.hsync_level;
73115 + video_cfg->v_fc_config.timings.x_res = cfg->timings.x_res;
73116 + video_cfg->v_fc_config.timings.hsw = cfg->timings.hsw - 1;
73117 + video_cfg->v_fc_config.timings.hbp = cfg->timings.hbp;
73118 + video_cfg->v_fc_config.timings.hfp = cfg->timings.hfp;
73119 + video_cfg->hblank = cfg->timings.hfp +
73120 + cfg->timings.hbp + cfg->timings.hsw - 1;
73121 + video_cfg->v_fc_config.timings.vsync_level = cfg->timings.vsync_level;
73122 + video_cfg->v_fc_config.timings.y_res = cfg->timings.y_res;
73123 + video_cfg->v_fc_config.timings.vsw = cfg->timings.vsw;
73124 + video_cfg->v_fc_config.timings.vfp = cfg->timings.vfp;
73125 + video_cfg->v_fc_config.timings.vbp = cfg->timings.vbp;
73126 + video_cfg->vblank_osc = 0; /* Always 0 - need to confirm */
73127 + video_cfg->vblank = cfg->timings.vsw +
73128 + cfg->timings.vfp + cfg->timings.vbp;
73129 + video_cfg->v_fc_config.cm.mode = cfg->cm.mode;
73130 + video_cfg->v_fc_config.timings.interlace = cfg->timings.interlace;
73131 +
73132 + /* info frame */
73133 + avi_cfg->db1_format = 0;
73134 + avi_cfg->db1_active_info = 0;
73135 + avi_cfg->db1_bar_info_dv = 0;
73136 + avi_cfg->db1_scan_info = 0;
73137 + avi_cfg->db2_colorimetry = 0;
73138 + avi_cfg->db2_aspect_ratio = 0;
73139 + avi_cfg->db2_active_fmt_ar = 0;
73140 + avi_cfg->db3_itc = 0;
73141 + avi_cfg->db3_ec = 0;
73142 + avi_cfg->db3_q_range = 0;
73143 + avi_cfg->db3_nup_scaling = 0;
73144 + avi_cfg->db4_videocode = 0;
73145 + avi_cfg->db5_pixel_repeat = 0;
73146 + avi_cfg->db6_7_line_eoftop = 0 ;
73147 + avi_cfg->db8_9_line_sofbottom = 0;
73148 + avi_cfg->db10_11_pixel_eofleft = 0;
73149 + avi_cfg->db12_13_pixel_sofright = 0;
73150 +}
73151 +
73152 +/* DSS_HDMI_CORE_VIDEO_CONFIG */
73153 +static void hdmi_core_video_config(struct hdmi_core_data *core,
73154 + struct hdmi_core_vid_config *cfg)
73155 +{
73156 + void __iomem *base = core->base;
73157 + unsigned char r = 0;
73158 + bool vsync_pol, hsync_pol;
73159 +
73160 + vsync_pol =
73161 + cfg->v_fc_config.timings.vsync_level == OMAPDSS_SIG_ACTIVE_HIGH;
73162 + hsync_pol =
73163 + cfg->v_fc_config.timings.hsync_level == OMAPDSS_SIG_ACTIVE_HIGH;
73164 +
73165 + /* Set hsync, vsync and data-enable polarity */
73166 + r = hdmi_read_reg(base, HDMI_CORE_FC_INVIDCONF);
73167 + r = FLD_MOD(r, vsync_pol, 6, 6);
73168 + r = FLD_MOD(r, hsync_pol, 5, 5);
73169 + r = FLD_MOD(r, cfg->data_enable_pol, 4, 4);
73170 + r = FLD_MOD(r, cfg->vblank_osc, 1, 1);
73171 + r = FLD_MOD(r, cfg->v_fc_config.timings.interlace, 0, 0);
73172 + hdmi_write_reg(base, HDMI_CORE_FC_INVIDCONF, r);
73173 +
73174 + /* set x resolution */
73175 + REG_FLD_MOD(base, HDMI_CORE_FC_INHACTIV1,
73176 + cfg->v_fc_config.timings.x_res >> 8, 4, 0);
73177 + REG_FLD_MOD(base, HDMI_CORE_FC_INHACTIV0,
73178 + cfg->v_fc_config.timings.x_res & 0xFF, 7, 0);
73179 +
73180 + /* set y resolution */
73181 + REG_FLD_MOD(base, HDMI_CORE_FC_INVACTIV1,
73182 + cfg->v_fc_config.timings.y_res >> 8, 4, 0);
73183 + REG_FLD_MOD(base, HDMI_CORE_FC_INVACTIV0,
73184 + cfg->v_fc_config.timings.y_res & 0xFF, 7, 0);
73185 +
73186 + /* set horizontal blanking pixels */
73187 + REG_FLD_MOD(base, HDMI_CORE_FC_INHBLANK1, cfg->hblank >> 8, 4, 0);
73188 + REG_FLD_MOD(base, HDMI_CORE_FC_INHBLANK0, cfg->hblank & 0xFF, 7, 0);
73189 +
73190 + /* set vertial blanking pixels */
73191 + REG_FLD_MOD(base, HDMI_CORE_FC_INVBLANK, cfg->vblank, 7, 0);
73192 +
73193 + /* set horizontal sync offset */
73194 + REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINDELAY1,
73195 + cfg->v_fc_config.timings.hfp >> 8, 4, 0);
73196 + REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINDELAY0,
73197 + cfg->v_fc_config.timings.hfp & 0xFF, 7, 0);
73198 +
73199 + /* set vertical sync offset */
73200 + REG_FLD_MOD(base, HDMI_CORE_FC_VSYNCINDELAY,
73201 + cfg->v_fc_config.timings.vfp, 7, 0);
73202 +
73203 + /* set horizontal sync pulse width */
73204 + REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINWIDTH1,
73205 + (cfg->v_fc_config.timings.hsw >> 8), 1, 0);
73206 + REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINWIDTH0,
73207 + cfg->v_fc_config.timings.hsw & 0xFF, 7, 0);
73208 +
73209 + /* set vertical sync pulse width */
73210 + REG_FLD_MOD(base, HDMI_CORE_FC_VSYNCINWIDTH,
73211 + cfg->v_fc_config.timings.vsw, 5, 0);
73212 +
73213 + /* select DVI mode */
73214 + REG_FLD_MOD(base, HDMI_CORE_FC_INVIDCONF,
73215 + cfg->v_fc_config.cm.mode, 3, 3);
73216 +}
73217 +
73218 +static void hdmi_core_config_video_packetizer(struct hdmi_core_data *core)
73219 +{
73220 + void __iomem *base = core->base;
73221 + int clr_depth = 0; /* 24 bit color depth */
73222 +
73223 + /* COLOR_DEPTH */
73224 + REG_FLD_MOD(base, HDMI_CORE_VP_PR_CD, clr_depth, 7, 4);
73225 + /* BYPASS_EN */
73226 + REG_FLD_MOD(base, HDMI_CORE_VP_CONF, clr_depth ? 0 : 1, 6, 6);
73227 + /* PP_EN */
73228 + REG_FLD_MOD(base, HDMI_CORE_VP_CONF, clr_depth ? 1 : 0, 5, 5);
73229 + /* YCC422_EN */
73230 + REG_FLD_MOD(base, HDMI_CORE_VP_CONF, 0, 3, 3);
73231 + /* PP_STUFFING */
73232 + REG_FLD_MOD(base, HDMI_CORE_VP_STUFF, clr_depth ? 1 : 0, 1, 1);
73233 + /* YCC422_STUFFING */
73234 + REG_FLD_MOD(base, HDMI_CORE_VP_STUFF, 1, 2, 2);
73235 + /* OUTPUT_SELECTOR */
73236 + REG_FLD_MOD(base, HDMI_CORE_VP_CONF, clr_depth ? 0 : 2, 1, 0);
73237 +}
73238 +
73239 +static void hdmi_core_config_csc(struct hdmi_core_data *core)
73240 +{
73241 + int clr_depth = 0; /* 24 bit color depth */
73242 +
73243 + /* CSC_COLORDEPTH */
73244 + REG_FLD_MOD(core->base, HDMI_CORE_CSC_SCALE, clr_depth, 7, 4);
73245 +}
73246 +
73247 +static void hdmi_core_config_video_sampler(struct hdmi_core_data *core)
73248 +{
73249 + int video_mapping = 1; /* for 24 bit color depth */
73250 +
73251 + /* VIDEO_MAPPING */
73252 + REG_FLD_MOD(core->base, HDMI_CORE_TX_INVID0, video_mapping, 4, 0);
73253 +}
73254 +
73255 +static void hdmi_core_aux_infoframe_avi_config(struct hdmi_core_data *core)
73256 +{
73257 + void __iomem *base = core->base;
73258 + struct hdmi_core_infoframe_avi avi = core->avi_cfg;
73259 +
73260 + REG_FLD_MOD(base, HDMI_CORE_FC_AVICONF0, avi.db1_format, 1, 0);
73261 + REG_FLD_MOD(base, HDMI_CORE_FC_AVICONF0, avi.db1_active_info, 6, 6);
73262 + REG_FLD_MOD(base, HDMI_CORE_FC_AVICONF0, avi.db1_bar_info_dv, 3, 2);
73263 + REG_FLD_MOD(base, HDMI_CORE_FC_AVICONF0, avi.db1_scan_info, 5, 4);
73264 + REG_FLD_MOD(base, HDMI_CORE_FC_AVICONF1, avi.db2_colorimetry, 7, 6);
73265 + REG_FLD_MOD(base, HDMI_CORE_FC_AVICONF1, avi.db2_aspect_ratio, 5, 4);
73266 + REG_FLD_MOD(base, HDMI_CORE_FC_AVICONF1, avi.db2_active_fmt_ar, 3, 0);
73267 + REG_FLD_MOD(base, HDMI_CORE_FC_AVICONF2, avi.db3_itc, 7, 7);
73268 + REG_FLD_MOD(base, HDMI_CORE_FC_AVICONF2, avi.db3_ec, 6, 4);
73269 + REG_FLD_MOD(base, HDMI_CORE_FC_AVICONF2, avi.db3_q_range, 3, 2);
73270 + REG_FLD_MOD(base, HDMI_CORE_FC_AVICONF2, avi.db3_nup_scaling, 1, 0);
73271 + REG_FLD_MOD(base, HDMI_CORE_FC_AVIVID, avi.db4_videocode, 6, 0);
73272 + REG_FLD_MOD(base, HDMI_CORE_FC_PRCONF, avi.db5_pixel_repeat, 3, 0);
73273 +}
73274 +
73275 +static void hdmi_core_csc_config(struct hdmi_core_data *core,
73276 + struct csc_table csc_coeff)
73277 +{
73278 + void __iomem *base = core->base;
73279 +
73280 + REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A1_MSB, csc_coeff.a1 >> 8 , 6, 0);
73281 + REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A1_LSB, csc_coeff.a1, 7, 0);
73282 + REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A2_MSB, csc_coeff.a2 >> 8, 6, 0);
73283 + REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A2_LSB, csc_coeff.a2, 7, 0);
73284 + REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A3_MSB, csc_coeff.a3 >> 8, 6, 0);
73285 + REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A3_LSB, csc_coeff.a3, 7, 0);
73286 + REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A4_MSB, csc_coeff.a4 >> 8, 6, 0);
73287 + REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A4_LSB, csc_coeff.a4, 7, 0);
73288 + REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B1_MSB, csc_coeff.b1 >> 8, 6, 0);
73289 + REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B1_LSB, csc_coeff.b1, 7, 0);
73290 + REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B2_MSB, csc_coeff.b2 >> 8, 6, 0);
73291 + REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B2_LSB, csc_coeff.b2, 7, 0);
73292 + REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B3_MSB, csc_coeff.b3 >> 8, 6, 0);
73293 + REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B3_LSB, csc_coeff.b3, 7, 0);
73294 + REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B4_MSB, csc_coeff.b4 >> 8, 6, 0);
73295 + REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B4_LSB, csc_coeff.b4, 7, 0);
73296 + REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C1_MSB, csc_coeff.c1 >> 8, 6, 0);
73297 + REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C1_LSB, csc_coeff.c1, 7, 0);
73298 + REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C2_MSB, csc_coeff.c2 >> 8, 6, 0);
73299 + REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C2_LSB, csc_coeff.c2, 7, 0);
73300 + REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C3_MSB, csc_coeff.c3 >> 8, 6, 0);
73301 + REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C3_LSB, csc_coeff.c3, 7, 0);
73302 + REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C4_MSB, csc_coeff.c4 >> 8, 6, 0);
73303 + REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C4_LSB, csc_coeff.c4, 7, 0);
73304 +
73305 + REG_FLD_MOD(base, HDMI_CORE_MC_FLOWCTRL, 0x1, 0, 0);
73306 +}
73307 +
73308 +static void hdmi_core_configure_range(struct hdmi_core_data *core)
73309 +{
73310 + struct csc_table csc_coeff = { 0 };
73311 +
73312 + /* support limited range with 24 bit color depth for now */
73313 + csc_coeff = csc_table_deepcolor[0];
73314 + core->avi_cfg.db3_q_range = HDMI_INFOFRAME_AVI_DB3Q_LR;
73315 +
73316 + hdmi_core_csc_config(core, csc_coeff);
73317 + hdmi_core_aux_infoframe_avi_config(core);
73318 +}
73319 +
73320 +static void hdmi_core_enable_video_path(struct hdmi_core_data *core)
73321 +{
73322 + void __iomem *base = core->base;
73323 +
73324 + DSSDBG("hdmi_core_enable_video_path\n");
73325 +
73326 + REG_FLD_MOD(base, HDMI_CORE_FC_CTRLDUR, 0x0C, 7, 0);
73327 + REG_FLD_MOD(base, HDMI_CORE_FC_EXCTRLDUR, 0x20, 7, 0);
73328 + REG_FLD_MOD(base, HDMI_CORE_FC_EXCTRLSPAC, 0x01, 7, 0);
73329 + REG_FLD_MOD(base, HDMI_CORE_FC_CH0PREAM, 0x0B, 7, 0);
73330 + REG_FLD_MOD(base, HDMI_CORE_FC_CH1PREAM, 0x16, 5, 0);
73331 + REG_FLD_MOD(base, HDMI_CORE_FC_CH2PREAM, 0x21, 5, 0);
73332 + REG_FLD_MOD(base, HDMI_CORE_MC_CLKDIS, 0x00, 0, 0);
73333 + REG_FLD_MOD(base, HDMI_CORE_MC_CLKDIS, 0x00, 1, 1);
73334 +}
73335 +
73336 +static void hdmi_core_mask_interrupts(struct hdmi_core_data *core)
73337 +{
73338 + void __iomem *base = core->base;
73339 +
73340 + /* Master IRQ mask */
73341 + REG_FLD_MOD(base, HDMI_CORE_IH_MUTE, 0x3, 1, 0);
73342 +
73343 + /* Mask all the interrupts in HDMI core */
73344 +
73345 + REG_FLD_MOD(base, HDMI_CORE_VP_MASK, 0xff, 7, 0);
73346 + REG_FLD_MOD(base, HDMI_CORE_FC_MASK0, 0xe7, 7, 0);
73347 + REG_FLD_MOD(base, HDMI_CORE_FC_MASK1, 0xfb, 7, 0);
73348 + REG_FLD_MOD(base, HDMI_CORE_FC_MASK2, 0x3, 1, 0);
73349 +
73350 + REG_FLD_MOD(base, HDMI_CORE_AUD_INT, 0x3, 3, 2);
73351 + REG_FLD_MOD(base, HDMI_CORE_AUD_GP_MASK, 0x3, 1, 0);
73352 +
73353 + REG_FLD_MOD(base, HDMI_CORE_CEC_MASK, 0x7f, 6, 0);
73354 +
73355 + REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 6, 6);
73356 + REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 2, 2);
73357 + REG_FLD_MOD(base, HDMI_CORE_I2CM_INT, 0x1, 2, 2);
73358 +
73359 + REG_FLD_MOD(base, HDMI_CORE_PHY_MASK0, 0xf3, 7, 0);
73360 +
73361 + REG_FLD_MOD(base, HDMI_CORE_IH_PHY_STAT0, 0xff, 7, 0);
73362 +
73363 + /* Clear all the current interrupt bits */
73364 +
73365 + REG_FLD_MOD(base, HDMI_CORE_IH_VP_STAT0, 0xff, 7, 0);
73366 + REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT0, 0xe7, 7, 0);
73367 + REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT1, 0xfb, 7, 0);
73368 + REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT2, 0x3, 1, 0);
73369 +
73370 + REG_FLD_MOD(base, HDMI_CORE_IH_AS_STAT0, 0x7, 2, 0);
73371 +
73372 + REG_FLD_MOD(base, HDMI_CORE_IH_CEC_STAT0, 0x7f, 6, 0);
73373 +
73374 + REG_FLD_MOD(base, HDMI_CORE_IH_I2CM_STAT0, 0x3, 1, 0);
73375 +
73376 + REG_FLD_MOD(base, HDMI_CORE_IH_PHY_STAT0, 0xff, 7, 0);
73377 +}
73378 +
73379 +static void hdmi_core_enable_interrupts(struct hdmi_core_data *core)
73380 +{
73381 + /* Unmute interrupts */
73382 + REG_FLD_MOD(core->base, HDMI_CORE_IH_MUTE, 0x0, 1, 0);
73383 +}
73384 +
73385 +int hdmi5_core_handle_irqs(struct hdmi_core_data *core)
73386 +{
73387 + void __iomem *base = core->base;
73388 +
73389 + REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT0, 0xff, 7, 0);
73390 + REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT1, 0xff, 7, 0);
73391 + REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT2, 0xff, 7, 0);
73392 + REG_FLD_MOD(base, HDMI_CORE_IH_AS_STAT0, 0xff, 7, 0);
73393 + REG_FLD_MOD(base, HDMI_CORE_IH_PHY_STAT0, 0xff, 7, 0);
73394 + REG_FLD_MOD(base, HDMI_CORE_IH_I2CM_STAT0, 0xff, 7, 0);
73395 + REG_FLD_MOD(base, HDMI_CORE_IH_CEC_STAT0, 0xff, 7, 0);
73396 + REG_FLD_MOD(base, HDMI_CORE_IH_VP_STAT0, 0xff, 7, 0);
73397 + REG_FLD_MOD(base, HDMI_CORE_IH_I2CMPHY_STAT0, 0xff, 7, 0);
73398 +
73399 + return 0;
73400 +}
73401 +
73402 +void hdmi5_configure(struct hdmi_core_data *core, struct hdmi_wp_data *wp,
73403 + struct hdmi_config *cfg)
73404 +{
73405 + struct omap_video_timings video_timing;
73406 + struct hdmi_video_format video_format;
73407 + struct hdmi_core_vid_config v_core_cfg;
73408 + struct hdmi_core_infoframe_avi *avi_cfg = &core->avi_cfg;
73409 +
73410 + hdmi_core_mask_interrupts(core);
73411 +
73412 + hdmi_core_init(&v_core_cfg, avi_cfg, cfg);
73413 +
73414 + hdmi_wp_init_vid_fmt_timings(&video_format, &video_timing, cfg);
73415 +
73416 + hdmi_wp_video_config_timing(wp, &video_timing);
73417 +
73418 + /* video config */
73419 + video_format.packing_mode = HDMI_PACK_24b_RGB_YUV444_YUV422;
73420 +
73421 + hdmi_wp_video_config_format(wp, &video_format);
73422 +
73423 + hdmi_wp_video_config_interface(wp, &video_timing);
73424 +
73425 + hdmi_core_configure_range(core);
73426 +
73427 + /*
73428 + * configure core video part, set software reset in the core
73429 + */
73430 + v_core_cfg.packet_mode = HDMI_PACKETMODE24BITPERPIXEL;
73431 +
73432 + hdmi_core_video_config(core, &v_core_cfg);
73433 +
73434 + hdmi_core_config_video_packetizer(core);
73435 + hdmi_core_config_csc(core);
73436 + hdmi_core_config_video_sampler(core);
73437 +
73438 + /*
73439 + * configure packet info frame video see doc CEA861-D page 65
73440 + */
73441 + avi_cfg->db1_format = HDMI_INFOFRAME_AVI_DB1Y_RGB;
73442 + avi_cfg->db1_active_info =
73443 + HDMI_INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_OFF;
73444 + avi_cfg->db1_bar_info_dv = HDMI_INFOFRAME_AVI_DB1B_NO;
73445 + avi_cfg->db1_scan_info = HDMI_INFOFRAME_AVI_DB1S_0;
73446 + avi_cfg->db2_colorimetry = HDMI_INFOFRAME_AVI_DB2C_NO;
73447 + avi_cfg->db2_aspect_ratio = HDMI_INFOFRAME_AVI_DB2M_NO;
73448 + avi_cfg->db2_active_fmt_ar = HDMI_INFOFRAME_AVI_DB2R_SAME;
73449 + avi_cfg->db3_itc = HDMI_INFOFRAME_AVI_DB3ITC_NO;
73450 + avi_cfg->db3_ec = HDMI_INFOFRAME_AVI_DB3EC_XVYUV601;
73451 + avi_cfg->db3_q_range = HDMI_INFOFRAME_AVI_DB3Q_DEFAULT;
73452 + avi_cfg->db3_nup_scaling = HDMI_INFOFRAME_AVI_DB3SC_NO;
73453 + avi_cfg->db4_videocode = cfg->cm.code;
73454 + avi_cfg->db5_pixel_repeat = HDMI_INFOFRAME_AVI_DB5PR_NO;
73455 + avi_cfg->db6_7_line_eoftop = 0;
73456 + avi_cfg->db8_9_line_sofbottom = 0;
73457 + avi_cfg->db10_11_pixel_eofleft = 0;
73458 + avi_cfg->db12_13_pixel_sofright = 0;
73459 +
73460 + hdmi_core_aux_infoframe_avi_config(core);
73461 +
73462 + hdmi_core_enable_video_path(core);
73463 +
73464 + hdmi_core_enable_interrupts(core);
73465 +}
73466 +
73467 +
73468 +#if defined(CONFIG_OMAP5_DSS_HDMI_AUDIO)
73469 +
73470 +static void hdmi5_core_audio_config(struct hdmi_core_data *core,
73471 + struct hdmi_core_audio_config *cfg)
73472 +{
73473 + void __iomem *base = core->base;
73474 + u8 val;
73475 +
73476 + /* Mute audio before configuring */
73477 + REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCONF, 0xf, 7, 4);
73478 +
73479 + /* Set the N parameter */
73480 + REG_FLD_MOD(base, HDMI_CORE_AUD_N1, cfg->n, 7, 0);
73481 + REG_FLD_MOD(base, HDMI_CORE_AUD_N2, cfg->n >> 8, 7, 0);
73482 + REG_FLD_MOD(base, HDMI_CORE_AUD_N3, cfg->n >> 16, 3, 0);
73483 +
73484 + /*
73485 + * CTS manual mode. Automatic mode is not supported when using audio
73486 + * parallel interface.
73487 + */
73488 + REG_FLD_MOD(base, HDMI_CORE_AUD_CTS3, 1, 4, 4);
73489 + REG_FLD_MOD(base, HDMI_CORE_AUD_CTS1, cfg->cts, 7, 0);
73490 + REG_FLD_MOD(base, HDMI_CORE_AUD_CTS2, cfg->cts >> 8, 7, 0);
73491 + REG_FLD_MOD(base, HDMI_CORE_AUD_CTS3, cfg->cts >> 16, 3, 0);
73492 +
73493 + /* Layout of Audio Sample Packets: 2-channel or multichannels */
73494 + if (cfg->layout == HDMI_AUDIO_LAYOUT_2CH)
73495 + REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCONF, 0, 0, 0);
73496 + else
73497 + REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCONF, 1, 0, 0);
73498 +
73499 + /* Configure IEC-609580 Validity bits */
73500 + /* Channel 0 is valid */
73501 + REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, 0, 0, 0);
73502 + REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, 0, 4, 4);
73503 +
73504 + if (cfg->layout == HDMI_AUDIO_LAYOUT_2CH)
73505 + val = 1;
73506 + else
73507 + val = 0;
73508 +
73509 + /* Channels 1, 2 setting */
73510 + REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 1, 1);
73511 + REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 5, 5);
73512 + REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 2, 2);
73513 + REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 6, 6);
73514 + /* Channel 3 setting */
73515 + if (cfg->layout == HDMI_AUDIO_LAYOUT_6CH)
73516 + val = 1;
73517 + REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 3, 3);
73518 + REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 7, 7);
73519 +
73520 + /* Configure IEC-60958 User bits */
73521 + /* TODO: should be set by user. */
73522 + REG_FLD_MOD(base, HDMI_CORE_FC_AUDSU, 0, 7, 0);
73523 +
73524 + /* Configure IEC-60958 Channel Status word */
73525 + /* CGMSA */
73526 + val = cfg->iec60958_cfg->status[5] & IEC958_AES5_CON_CGMSA;
73527 + REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(0), val, 5, 4);
73528 +
73529 + /* Copyright */
73530 + val = (cfg->iec60958_cfg->status[0] &
73531 + IEC958_AES0_CON_NOT_COPYRIGHT) >> 2;
73532 + REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(0), val, 0, 0);
73533 +
73534 + /* Category */
73535 + hdmi_write_reg(base, HDMI_CORE_FC_AUDSCHNLS(1),
73536 + cfg->iec60958_cfg->status[1]);
73537 +
73538 + /* PCM audio mode */
73539 + val = (cfg->iec60958_cfg->status[0] & IEC958_AES0_CON_MODE) >> 6;
73540 + REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(2), val, 6, 4);
73541 +
73542 + /* Source number */
73543 + val = cfg->iec60958_cfg->status[2] & IEC958_AES2_CON_SOURCE;
73544 + REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(2), val, 3, 4);
73545 +
73546 + /* Channel number right 0 */
73547 + REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(3), 2, 3, 0);
73548 + /* Channel number right 1*/
73549 + REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(3), 4, 7, 4);
73550 + /* Channel number right 2 */
73551 + REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(4), 6, 3, 0);
73552 + /* Channel number right 3*/
73553 + REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(4), 8, 7, 4);
73554 + /* Channel number left 0 */
73555 + REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(5), 1, 3, 0);
73556 + /* Channel number left 1*/
73557 + REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(5), 3, 7, 4);
73558 + /* Channel number left 2 */
73559 + REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(6), 5, 3, 0);
73560 + /* Channel number left 3*/
73561 + REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(6), 7, 7, 4);
73562 +
73563 + /* Clock accuracy and sample rate */
73564 + hdmi_write_reg(base, HDMI_CORE_FC_AUDSCHNLS(7),
73565 + cfg->iec60958_cfg->status[3]);
73566 +
73567 + /* Original sample rate and word length */
73568 + hdmi_write_reg(base, HDMI_CORE_FC_AUDSCHNLS(8),
73569 + cfg->iec60958_cfg->status[4]);
73570 +
73571 + /* Enable FIFO empty and full interrupts */
73572 + REG_FLD_MOD(base, HDMI_CORE_AUD_INT, 3, 3, 2);
73573 +
73574 + /* Configure GPA */
73575 + /* select HBR/SPDIF interfaces */
73576 + if (cfg->layout == HDMI_AUDIO_LAYOUT_2CH) {
73577 + /* select HBR/SPDIF interfaces */
73578 + REG_FLD_MOD(base, HDMI_CORE_AUD_CONF0, 0, 5, 5);
73579 + /* enable two channels in GPA */
73580 + REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF1, 3, 7, 0);
73581 + } else if (cfg->layout == HDMI_AUDIO_LAYOUT_6CH) {
73582 + /* select HBR/SPDIF interfaces */
73583 + REG_FLD_MOD(base, HDMI_CORE_AUD_CONF0, 0, 5, 5);
73584 + /* enable six channels in GPA */
73585 + REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF1, 0x3F, 7, 0);
73586 + } else {
73587 + /* select HBR/SPDIF interfaces */
73588 + REG_FLD_MOD(base, HDMI_CORE_AUD_CONF0, 0, 5, 5);
73589 + /* enable eight channels in GPA */
73590 + REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF1, 0xFF, 7, 0);
73591 + }
73592 +
73593 + /* disable HBR */
73594 + REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF2, 0, 0, 0);
73595 + /* enable PCUV */
73596 + REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF2, 1, 1, 1);
73597 + /* enable GPA FIFO full and empty mask */
73598 + REG_FLD_MOD(base, HDMI_CORE_AUD_GP_MASK, 3, 1, 0);
73599 + /* set polarity of GPA FIFO empty interrupts */
73600 + REG_FLD_MOD(base, HDMI_CORE_AUD_GP_POL, 1, 0, 0);
73601 +
73602 + /* unmute audio */
73603 + REG_FLD_MOD(core_sys_base, HDMI_CORE_FC_AUDSCONF, 0, 7, 4);
73604 +}
73605 +
73606 +static void hdmi5_core_audio_infoframe_cfg(struct hdmi_core_data *core,
73607 + struct snd_cea_861_aud_if *info_aud)
73608 +{
73609 + void __iomem *base = core->base;
73610 +
73611 + /* channel count and coding type fields in AUDICONF0 are swapped */
73612 + hdmi_write_reg(base, HDMI_CORE_FC_AUDICONF0,
73613 + (info_aud->db1_ct_cc & CEA861_AUDIO_INFOFRAME_DB1CC) << 4 |
73614 + (info_aud->db1_ct_cc & CEA861_AUDIO_INFOFRAME_DB1CT) >> 4);
73615 +
73616 + hdmi_write_reg(base, HDMI_CORE_FC_AUDICONF1, info_aud->db2_sf_ss);
73617 + hdmi_write_reg(base, HDMI_CORE_FC_AUDICONF2, info_aud->db4_ca);
73618 + hdmi_write_reg(base, HDMI_CORE_FC_AUDICONF3, info_aud->db5_dminh_lsv);
73619 +}
73620 +
73621 +int hdmi5_audio_config(struct hdmi_core_data *core, struct hdmi_wp_data *wp,
73622 + struct omap_dss_audio *audio, u32 pclk)
73623 +{
73624 + struct hdmi_audio_format audio_format;
73625 + struct hdmi_audio_dma audio_dma;
73626 + struct hdmi_core_audio_config core_cfg;
73627 + int err, n, cts, channel_count;
73628 + unsigned int fs_nr;
73629 + bool word_length_16b = false;
73630 +
73631 + if (!audio || !audio->iec || !audio->cea || !core)
73632 + return -EINVAL;
73633 +
73634 + core_cfg.iec60958_cfg = audio->iec;
73635 +
73636 + if (!(audio->iec->status[4] & IEC958_AES4_CON_MAX_WORDLEN_24) &&
73637 + (audio->iec->status[4] & IEC958_AES4_CON_WORDLEN_20_16))
73638 + word_length_16b = true;
73639 +
73640 + /* only 16-bit word length supported atm */
73641 + if (!word_length_16b)
73642 + return -EINVAL;
73643 +
73644 + switch (audio->iec->status[3] & IEC958_AES3_CON_FS) {
73645 + case IEC958_AES3_CON_FS_32000:
73646 + fs_nr = 32000;
73647 + break;
73648 + case IEC958_AES3_CON_FS_44100:
73649 + fs_nr = 44100;
73650 + break;
73651 + case IEC958_AES3_CON_FS_48000:
73652 + fs_nr = 48000;
73653 + break;
73654 + case IEC958_AES3_CON_FS_88200:
73655 + fs_nr = 88200;
73656 + break;
73657 + case IEC958_AES3_CON_FS_96000:
73658 + fs_nr = 96000;
73659 + break;
73660 + case IEC958_AES3_CON_FS_176400:
73661 + fs_nr = 176400;
73662 + break;
73663 + case IEC958_AES3_CON_FS_192000:
73664 + fs_nr = 192000;
73665 + break;
73666 + default:
73667 + return -EINVAL;
73668 + }
73669 +
73670 + err = hdmi_compute_acr(pclk, fs_nr, &n, &cts);
73671 + core_cfg.n = n;
73672 + core_cfg.cts = cts;
73673 +
73674 + /* Audio channels settings */
73675 + channel_count = (audio->cea->db1_ct_cc & CEA861_AUDIO_INFOFRAME_DB1CC)
73676 + + 1;
73677 +
73678 + if (channel_count == 2)
73679 + core_cfg.layout = HDMI_AUDIO_LAYOUT_2CH;
73680 + else if (channel_count == 6)
73681 + core_cfg.layout = HDMI_AUDIO_LAYOUT_6CH;
73682 + else
73683 + core_cfg.layout = HDMI_AUDIO_LAYOUT_8CH;
73684 +
73685 + /* DMA settings */
73686 + if (word_length_16b)
73687 + audio_dma.transfer_size = 0x10;
73688 + else
73689 + audio_dma.transfer_size = 0x20;
73690 + audio_dma.block_size = 0xC0;
73691 + audio_dma.mode = HDMI_AUDIO_TRANSF_DMA;
73692 + audio_dma.fifo_threshold = 0x20; /* in number of samples */
73693 +
73694 + /* audio FIFO format settings for 16-bit samples*/
73695 + audio_format.samples_per_word = HDMI_AUDIO_ONEWORD_TWOSAMPLES;
73696 + audio_format.sample_size = HDMI_AUDIO_SAMPLE_16BITS;
73697 + audio_format.justification = HDMI_AUDIO_JUSTIFY_LEFT;
73698 +
73699 + /* only LPCM atm */
73700 + audio_format.type = HDMI_AUDIO_TYPE_LPCM;
73701 +
73702 + /* disable start/stop signals of IEC 60958 blocks */
73703 + audio_format.en_sig_blk_strt_end = HDMI_AUDIO_BLOCK_SIG_STARTEND_ON;
73704 +
73705 + /* configure DMA and audio FIFO format*/
73706 + hdmi_wp_audio_config_dma(wp, &audio_dma);
73707 + hdmi_wp_audio_config_format(wp, &audio_format);
73708 +
73709 + /* configure the core */
73710 + hdmi5_core_audio_config(core, &core_cfg);
73711 +
73712 + /* configure CEA 861 audio infoframe */
73713 + hdmi5_core_audio_infoframe_cfg(core, audio->cea);
73714 +
73715 + return 0;
73716 +}
73717 +#endif
73718 +
73719 +int hdmi5_core_init(struct platform_device *pdev, struct hdmi_core_data *core)
73720 +{
73721 + struct resource *res;
73722 +
73723 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi_core");
73724 + if (!res) {
73725 + DSSERR("can't get CORE IORESOURCE_MEM HDMI\n");
73726 + return -EINVAL;
73727 + }
73728 +
73729 + core->base = devm_request_and_ioremap(&pdev->dev, res);
73730 + if (!core->base) {
73731 + DSSERR("can't ioremap HDMI core\n");
73732 + return -ENOMEM;
73733 + }
73734 +
73735 + return 0;
73736 +}
73737 --- /dev/null
73738 +++ b/drivers/video/omap2/dss/hdmi5_core.h
73739 @@ -0,0 +1,306 @@
73740 +/*
73741 + * HDMI driver definition for TI OMAP5 processors.
73742 + *
73743 + * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
73744 + *
73745 + * This program is free software; you can redistribute it and/or modify it
73746 + * under the terms of the GNU General Public License version 2 as published by
73747 + * the Free Software Foundation.
73748 + *
73749 + * This program is distributed in the hope that it will be useful, but WITHOUT
73750 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
73751 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
73752 + * more details.
73753 + *
73754 + * You should have received a copy of the GNU General Public License along with
73755 + * this program. If not, see <http://www.gnu.org/licenses/>.
73756 + */
73757 +
73758 +#ifndef _HDMI5_CORE_H_
73759 +#define _HDMI5_CORE_H_
73760 +
73761 +#include "hdmi.h"
73762 +
73763 +/* HDMI IP Core System */
73764 +
73765 +/* HDMI Identification */
73766 +#define HDMI_CORE_DESIGN_ID 0x00000
73767 +#define HDMI_CORE_REVISION_ID 0x00004
73768 +#define HDMI_CORE_PRODUCT_ID0 0x00008
73769 +#define HDMI_CORE_PRODUCT_ID1 0x0000C
73770 +#define HDMI_CORE_CONFIG0_ID 0x00010
73771 +#define HDMI_CORE_CONFIG1_ID 0x00014
73772 +#define HDMI_CORE_CONFIG2_ID 0x00018
73773 +#define HDMI_CORE_CONFIG3_ID 0x0001C
73774 +
73775 +/* HDMI Interrupt */
73776 +#define HDMI_CORE_IH_FC_STAT0 0x00400
73777 +#define HDMI_CORE_IH_FC_STAT1 0x00404
73778 +#define HDMI_CORE_IH_FC_STAT2 0x00408
73779 +#define HDMI_CORE_IH_AS_STAT0 0x0040C
73780 +#define HDMI_CORE_IH_PHY_STAT0 0x00410
73781 +#define HDMI_CORE_IH_I2CM_STAT0 0x00414
73782 +#define HDMI_CORE_IH_CEC_STAT0 0x00418
73783 +#define HDMI_CORE_IH_VP_STAT0 0x0041C
73784 +#define HDMI_CORE_IH_I2CMPHY_STAT0 0x00420
73785 +#define HDMI_CORE_IH_MUTE 0x007FC
73786 +
73787 +/* HDMI Video Sampler */
73788 +#define HDMI_CORE_TX_INVID0 0x00800
73789 +#define HDMI_CORE_TX_INSTUFFING 0x00804
73790 +#define HDMI_CORE_TX_RGYDATA0 0x00808
73791 +#define HDMI_CORE_TX_RGYDATA1 0x0080C
73792 +#define HDMI_CORE_TX_RCRDATA0 0x00810
73793 +#define HDMI_CORE_TX_RCRDATA1 0x00814
73794 +#define HDMI_CORE_TX_BCBDATA0 0x00818
73795 +#define HDMI_CORE_TX_BCBDATA1 0x0081C
73796 +
73797 +/* HDMI Video Packetizer */
73798 +#define HDMI_CORE_VP_STATUS 0x02000
73799 +#define HDMI_CORE_VP_PR_CD 0x02004
73800 +#define HDMI_CORE_VP_STUFF 0x02008
73801 +#define HDMI_CORE_VP_REMAP 0x0200C
73802 +#define HDMI_CORE_VP_CONF 0x02010
73803 +#define HDMI_CORE_VP_STAT 0x02014
73804 +#define HDMI_CORE_VP_INT 0x02018
73805 +#define HDMI_CORE_VP_MASK 0x0201C
73806 +#define HDMI_CORE_VP_POL 0x02020
73807 +
73808 +/* Frame Composer */
73809 +#define HDMI_CORE_FC_INVIDCONF 0x04000
73810 +#define HDMI_CORE_FC_INHACTIV0 0x04004
73811 +#define HDMI_CORE_FC_INHACTIV1 0x04008
73812 +#define HDMI_CORE_FC_INHBLANK0 0x0400C
73813 +#define HDMI_CORE_FC_INHBLANK1 0x04010
73814 +#define HDMI_CORE_FC_INVACTIV0 0x04014
73815 +#define HDMI_CORE_FC_INVACTIV1 0x04018
73816 +#define HDMI_CORE_FC_INVBLANK 0x0401C
73817 +#define HDMI_CORE_FC_HSYNCINDELAY0 0x04020
73818 +#define HDMI_CORE_FC_HSYNCINDELAY1 0x04024
73819 +#define HDMI_CORE_FC_HSYNCINWIDTH0 0x04028
73820 +#define HDMI_CORE_FC_HSYNCINWIDTH1 0x0402C
73821 +#define HDMI_CORE_FC_VSYNCINDELAY 0x04030
73822 +#define HDMI_CORE_FC_VSYNCINWIDTH 0x04034
73823 +#define HDMI_CORE_FC_INFREQ0 0x04038
73824 +#define HDMI_CORE_FC_INFREQ1 0x0403C
73825 +#define HDMI_CORE_FC_INFREQ2 0x04040
73826 +#define HDMI_CORE_FC_CTRLDUR 0x04044
73827 +#define HDMI_CORE_FC_EXCTRLDUR 0x04048
73828 +#define HDMI_CORE_FC_EXCTRLSPAC 0x0404C
73829 +#define HDMI_CORE_FC_CH0PREAM 0x04050
73830 +#define HDMI_CORE_FC_CH1PREAM 0x04054
73831 +#define HDMI_CORE_FC_CH2PREAM 0x04058
73832 +#define HDMI_CORE_FC_AVICONF3 0x0405C
73833 +#define HDMI_CORE_FC_GCP 0x04060
73834 +#define HDMI_CORE_FC_AVICONF0 0x04064
73835 +#define HDMI_CORE_FC_AVICONF1 0x04068
73836 +#define HDMI_CORE_FC_AVICONF2 0x0406C
73837 +#define HDMI_CORE_FC_AVIVID 0x04070
73838 +#define HDMI_CORE_FC_AVIETB0 0x04074
73839 +#define HDMI_CORE_FC_AVIETB1 0x04078
73840 +#define HDMI_CORE_FC_AVISBB0 0x0407C
73841 +#define HDMI_CORE_FC_AVISBB1 0x04080
73842 +#define HDMI_CORE_FC_AVIELB0 0x04084
73843 +#define HDMI_CORE_FC_AVIELB1 0x04088
73844 +#define HDMI_CORE_FC_AVISRB0 0x0408C
73845 +#define HDMI_CORE_FC_AVISRB1 0x04090
73846 +#define HDMI_CORE_FC_AUDICONF0 0x04094
73847 +#define HDMI_CORE_FC_AUDICONF1 0x04098
73848 +#define HDMI_CORE_FC_AUDICONF2 0x0409C
73849 +#define HDMI_CORE_FC_AUDICONF3 0x040A0
73850 +#define HDMI_CORE_FC_VSDIEEEID0 0x040A4
73851 +#define HDMI_CORE_FC_VSDSIZE 0x040A8
73852 +#define HDMI_CORE_FC_VSDIEEEID1 0x040C0
73853 +#define HDMI_CORE_FC_VSDIEEEID2 0x040C4
73854 +#define HDMI_CORE_FC_VSDPAYLOAD(n) (n * 4 + 0x040C8)
73855 +#define HDMI_CORE_FC_SPDVENDORNAME(n) (n * 4 + 0x04128)
73856 +#define HDMI_CORE_FC_SPDPRODUCTNAME(n) (n * 4 + 0x04148)
73857 +#define HDMI_CORE_FC_SPDDEVICEINF 0x04188
73858 +#define HDMI_CORE_FC_AUDSCONF 0x0418C
73859 +#define HDMI_CORE_FC_AUDSSTAT 0x04190
73860 +#define HDMI_CORE_FC_AUDSV 0x04194
73861 +#define HDMI_CORE_FC_AUDSU 0x04198
73862 +#define HDMI_CORE_FC_AUDSCHNLS(n) (n * 4 + 0x0419C)
73863 +#define HDMI_CORE_FC_CTRLQHIGH 0x041CC
73864 +#define HDMI_CORE_FC_CTRLQLOW 0x041D0
73865 +#define HDMI_CORE_FC_ACP0 0x041D4
73866 +#define HDMI_CORE_FC_ACP(n) ((16-n) * 4 + 0x04208)
73867 +#define HDMI_CORE_FC_ISCR1_0 0x04248
73868 +#define HDMI_CORE_FC_ISCR1(n) ((16-n) * 4 + 0x0424C)
73869 +#define HDMI_CORE_FC_ISCR2(n) ((15-n) * 4 + 0x0428C)
73870 +#define HDMI_CORE_FC_DATAUTO0 0x042CC
73871 +#define HDMI_CORE_FC_DATAUTO1 0x042D0
73872 +#define HDMI_CORE_FC_DATAUTO2 0x042D4
73873 +#define HDMI_CORE_FC_DATMAN 0x042D8
73874 +#define HDMI_CORE_FC_DATAUTO3 0x042DC
73875 +#define HDMI_CORE_FC_RDRB(n) (n * 4 + 0x042E0)
73876 +#define HDMI_CORE_FC_STAT0 0x04340
73877 +#define HDMI_CORE_FC_INT0 0x04344
73878 +#define HDMI_CORE_FC_MASK0 0x04348
73879 +#define HDMI_CORE_FC_POL0 0x0434C
73880 +#define HDMI_CORE_FC_STAT1 0x04350
73881 +#define HDMI_CORE_FC_INT1 0x04354
73882 +#define HDMI_CORE_FC_MASK1 0x04358
73883 +#define HDMI_CORE_FC_POL1 0x0435C
73884 +#define HDMI_CORE_FC_STAT2 0x04360
73885 +#define HDMI_CORE_FC_INT2 0x04364
73886 +#define HDMI_CORE_FC_MASK2 0x04368
73887 +#define HDMI_CORE_FC_POL2 0x0436C
73888 +#define HDMI_CORE_FC_PRCONF 0x04380
73889 +#define HDMI_CORE_FC_GMD_STAT 0x04400
73890 +#define HDMI_CORE_FC_GMD_EN 0x04404
73891 +#define HDMI_CORE_FC_GMD_UP 0x04408
73892 +#define HDMI_CORE_FC_GMD_CONF 0x0440C
73893 +#define HDMI_CORE_FC_GMD_HB 0x04410
73894 +#define HDMI_CORE_FC_GMD_PB(n) (n * 4 + 0x04414)
73895 +#define HDMI_CORE_FC_DBGFORCE 0x04800
73896 +#define HDMI_CORE_FC_DBGAUD0CH0 0x04804
73897 +#define HDMI_CORE_FC_DBGAUD1CH0 0x04808
73898 +#define HDMI_CORE_FC_DBGAUD2CH0 0x0480C
73899 +#define HDMI_CORE_FC_DBGAUD0CH1 0x04810
73900 +#define HDMI_CORE_FC_DBGAUD1CH1 0x04814
73901 +#define HDMI_CORE_FC_DBGAUD2CH1 0x04818
73902 +#define HDMI_CORE_FC_DBGAUD0CH2 0x0481C
73903 +#define HDMI_CORE_FC_DBGAUD1CH2 0x04820
73904 +#define HDMI_CORE_FC_DBGAUD2CH2 0x04824
73905 +#define HDMI_CORE_FC_DBGAUD0CH3 0x04828
73906 +#define HDMI_CORE_FC_DBGAUD1CH3 0x0482C
73907 +#define HDMI_CORE_FC_DBGAUD2CH3 0x04830
73908 +#define HDMI_CORE_FC_DBGAUD0CH4 0x04834
73909 +#define HDMI_CORE_FC_DBGAUD1CH4 0x04838
73910 +#define HDMI_CORE_FC_DBGAUD2CH4 0x0483C
73911 +#define HDMI_CORE_FC_DBGAUD0CH5 0x04840
73912 +#define HDMI_CORE_FC_DBGAUD1CH5 0x04844
73913 +#define HDMI_CORE_FC_DBGAUD2CH5 0x04848
73914 +#define HDMI_CORE_FC_DBGAUD0CH6 0x0484C
73915 +#define HDMI_CORE_FC_DBGAUD1CH6 0x04850
73916 +#define HDMI_CORE_FC_DBGAUD2CH6 0x04854
73917 +#define HDMI_CORE_FC_DBGAUD0CH7 0x04858
73918 +#define HDMI_CORE_FC_DBGAUD1CH7 0x0485C
73919 +#define HDMI_CORE_FC_DBGAUD2CH7 0x04860
73920 +#define HDMI_CORE_FC_DBGTMDS0 0x04864
73921 +#define HDMI_CORE_FC_DBGTMDS1 0x04868
73922 +#define HDMI_CORE_FC_DBGTMDS2 0x0486C
73923 +#define HDMI_CORE_PHY_MASK0 0x0C018
73924 +#define HDMI_CORE_PHY_I2CM_INT_ADDR 0x0C09C
73925 +#define HDMI_CORE_PHY_I2CM_CTLINT_ADDR 0x0C0A0
73926 +
73927 +/* HDMI Audio */
73928 +#define HDMI_CORE_AUD_CONF0 0x0C400
73929 +#define HDMI_CORE_AUD_CONF1 0x0C404
73930 +#define HDMI_CORE_AUD_INT 0x0C408
73931 +#define HDMI_CORE_AUD_N1 0x0C800
73932 +#define HDMI_CORE_AUD_N2 0x0C804
73933 +#define HDMI_CORE_AUD_N3 0x0C808
73934 +#define HDMI_CORE_AUD_CTS1 0x0C80C
73935 +#define HDMI_CORE_AUD_CTS2 0x0C810
73936 +#define HDMI_CORE_AUD_CTS3 0x0C814
73937 +#define HDMI_CORE_AUD_INCLKFS 0x0C818
73938 +#define HDMI_CORE_AUD_CC08 0x0CC08
73939 +#define HDMI_CORE_AUD_GP_CONF0 0x0D400
73940 +#define HDMI_CORE_AUD_GP_CONF1 0x0D404
73941 +#define HDMI_CORE_AUD_GP_CONF2 0x0D408
73942 +#define HDMI_CORE_AUD_D010 0x0D010
73943 +#define HDMI_CORE_AUD_GP_STAT 0x0D40C
73944 +#define HDMI_CORE_AUD_GP_INT 0x0D410
73945 +#define HDMI_CORE_AUD_GP_POL 0x0D414
73946 +#define HDMI_CORE_AUD_GP_MASK 0x0D418
73947 +
73948 +/* HDMI Main Controller */
73949 +#define HDMI_CORE_MC_CLKDIS 0x10004
73950 +#define HDMI_CORE_MC_SWRSTZREQ 0x10008
73951 +#define HDMI_CORE_MC_FLOWCTRL 0x10010
73952 +#define HDMI_CORE_MC_PHYRSTZ 0x10014
73953 +#define HDMI_CORE_MC_LOCKONCLOCK 0x10018
73954 +
73955 +/* HDMI COLOR SPACE CONVERTER */
73956 +#define HDMI_CORE_CSC_CFG 0x10400
73957 +#define HDMI_CORE_CSC_SCALE 0x10404
73958 +#define HDMI_CORE_CSC_COEF_A1_MSB 0x10408
73959 +#define HDMI_CORE_CSC_COEF_A1_LSB 0x1040C
73960 +#define HDMI_CORE_CSC_COEF_A2_MSB 0x10410
73961 +#define HDMI_CORE_CSC_COEF_A2_LSB 0x10414
73962 +#define HDMI_CORE_CSC_COEF_A3_MSB 0x10418
73963 +#define HDMI_CORE_CSC_COEF_A3_LSB 0x1041C
73964 +#define HDMI_CORE_CSC_COEF_A4_MSB 0x10420
73965 +#define HDMI_CORE_CSC_COEF_A4_LSB 0x10424
73966 +#define HDMI_CORE_CSC_COEF_B1_MSB 0x10428
73967 +#define HDMI_CORE_CSC_COEF_B1_LSB 0x1042C
73968 +#define HDMI_CORE_CSC_COEF_B2_MSB 0x10430
73969 +#define HDMI_CORE_CSC_COEF_B2_LSB 0x10434
73970 +#define HDMI_CORE_CSC_COEF_B3_MSB 0x10438
73971 +#define HDMI_CORE_CSC_COEF_B3_LSB 0x1043C
73972 +#define HDMI_CORE_CSC_COEF_B4_MSB 0x10440
73973 +#define HDMI_CORE_CSC_COEF_B4_LSB 0x10444
73974 +#define HDMI_CORE_CSC_COEF_C1_MSB 0x10448
73975 +#define HDMI_CORE_CSC_COEF_C1_LSB 0x1044C
73976 +#define HDMI_CORE_CSC_COEF_C2_MSB 0x10450
73977 +#define HDMI_CORE_CSC_COEF_C2_LSB 0x10454
73978 +#define HDMI_CORE_CSC_COEF_C3_MSB 0x10458
73979 +#define HDMI_CORE_CSC_COEF_C3_LSB 0x1045C
73980 +#define HDMI_CORE_CSC_COEF_C4_MSB 0x10460
73981 +#define HDMI_CORE_CSC_COEF_C4_LSB 0x10464
73982 +
73983 +/* HDMI HDCP */
73984 +#define HDMI_CORE_HDCP_MASK 0x14020
73985 +
73986 +/* HDMI CEC */
73987 +#define HDMI_CORE_CEC_MASK 0x17408
73988 +
73989 +/* HDMI I2C Master */
73990 +#define HDMI_CORE_I2CM_SLAVE 0x157C8
73991 +#define HDMI_CORE_I2CM_ADDRESS 0x157CC
73992 +#define HDMI_CORE_I2CM_DATAO 0x157D0
73993 +#define HDMI_CORE_I2CM_DATAI 0X157D4
73994 +#define HDMI_CORE_I2CM_OPERATION 0x157D8
73995 +#define HDMI_CORE_I2CM_INT 0x157DC
73996 +#define HDMI_CORE_I2CM_CTLINT 0x157E0
73997 +#define HDMI_CORE_I2CM_DIV 0x157E4
73998 +#define HDMI_CORE_I2CM_SEGADDR 0x157E8
73999 +#define HDMI_CORE_I2CM_SOFTRSTZ 0x157EC
74000 +#define HDMI_CORE_I2CM_SEGPTR 0x157F0
74001 +#define HDMI_CORE_I2CM_SS_SCL_HCNT_1_ADDR 0x157F4
74002 +#define HDMI_CORE_I2CM_SS_SCL_HCNT_0_ADDR 0x157F8
74003 +#define HDMI_CORE_I2CM_SS_SCL_LCNT_1_ADDR 0x157FC
74004 +#define HDMI_CORE_I2CM_SS_SCL_LCNT_0_ADDR 0x15800
74005 +#define HDMI_CORE_I2CM_FS_SCL_HCNT_1_ADDR 0x15804
74006 +#define HDMI_CORE_I2CM_FS_SCL_HCNT_0_ADDR 0x15808
74007 +#define HDMI_CORE_I2CM_FS_SCL_LCNT_1_ADDR 0x1580C
74008 +#define HDMI_CORE_I2CM_FS_SCL_LCNT_0_ADDR 0x15810
74009 +#define HDMI_CORE_I2CM_SDA_HOLD_ADDR 0x15814
74010 +
74011 +enum hdmi_core_packet_mode {
74012 + HDMI_PACKETMODERESERVEDVALUE = 0,
74013 + HDMI_PACKETMODE24BITPERPIXEL = 4,
74014 + HDMI_PACKETMODE30BITPERPIXEL = 5,
74015 + HDMI_PACKETMODE36BITPERPIXEL = 6,
74016 + HDMI_PACKETMODE48BITPERPIXEL = 7,
74017 +};
74018 +
74019 +struct hdmi_core_vid_config {
74020 + struct hdmi_config v_fc_config;
74021 + enum hdmi_core_packet_mode packet_mode;
74022 + int data_enable_pol;
74023 + int vblank_osc;
74024 + int hblank;
74025 + int vblank;
74026 +};
74027 +
74028 +struct csc_table {
74029 + u16 a1, a2, a3, a4;
74030 + u16 b1, b2, b3, b4;
74031 + u16 c1, c2, c3, c4;
74032 +};
74033 +
74034 +int hdmi5_read_edid(struct hdmi_core_data *core, u8 *edid, int len);
74035 +void hdmi5_core_dump(struct hdmi_core_data *core, struct seq_file *s);
74036 +int hdmi5_core_handle_irqs(struct hdmi_core_data *core);
74037 +void hdmi5_configure(struct hdmi_core_data *core, struct hdmi_wp_data *wp,
74038 + struct hdmi_config *cfg);
74039 +int hdmi5_core_init(struct platform_device *pdev, struct hdmi_core_data *core);
74040 +
74041 +#if defined(CONFIG_OMAP5_DSS_HDMI_AUDIO)
74042 +int hdmi5_audio_config(struct hdmi_core_data *core, struct hdmi_wp_data *wp,
74043 + struct omap_dss_audio *audio, u32 pclk);
74044 +#endif
74045 +#endif
74046 --- a/drivers/video/omap2/dss/hdmi.c
74047 +++ /dev/null
74048 @@ -1,1184 +0,0 @@
74049 -/*
74050 - * hdmi.c
74051 - *
74052 - * HDMI interface DSS driver setting for TI's OMAP4 family of processor.
74053 - * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
74054 - * Authors: Yong Zhi
74055 - * Mythri pk <mythripk@ti.com>
74056 - *
74057 - * This program is free software; you can redistribute it and/or modify it
74058 - * under the terms of the GNU General Public License version 2 as published by
74059 - * the Free Software Foundation.
74060 - *
74061 - * This program is distributed in the hope that it will be useful, but WITHOUT
74062 - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
74063 - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
74064 - * more details.
74065 - *
74066 - * You should have received a copy of the GNU General Public License along with
74067 - * this program. If not, see <http://www.gnu.org/licenses/>.
74068 - */
74069 -
74070 -#define DSS_SUBSYS_NAME "HDMI"
74071 -
74072 -#include <linux/kernel.h>
74073 -#include <linux/module.h>
74074 -#include <linux/err.h>
74075 -#include <linux/io.h>
74076 -#include <linux/interrupt.h>
74077 -#include <linux/mutex.h>
74078 -#include <linux/delay.h>
74079 -#include <linux/string.h>
74080 -#include <linux/platform_device.h>
74081 -#include <linux/pm_runtime.h>
74082 -#include <linux/clk.h>
74083 -#include <linux/gpio.h>
74084 -#include <linux/regulator/consumer.h>
74085 -#include <video/omapdss.h>
74086 -
74087 -#include "ti_hdmi.h"
74088 -#include "dss.h"
74089 -#include "dss_features.h"
74090 -
74091 -#define HDMI_WP 0x0
74092 -#define HDMI_CORE_SYS 0x400
74093 -#define HDMI_CORE_AV 0x900
74094 -#define HDMI_PLLCTRL 0x200
74095 -#define HDMI_PHY 0x300
74096 -
74097 -/* HDMI EDID Length move this */
74098 -#define HDMI_EDID_MAX_LENGTH 256
74099 -#define EDID_TIMING_DESCRIPTOR_SIZE 0x12
74100 -#define EDID_DESCRIPTOR_BLOCK0_ADDRESS 0x36
74101 -#define EDID_DESCRIPTOR_BLOCK1_ADDRESS 0x80
74102 -#define EDID_SIZE_BLOCK0_TIMING_DESCRIPTOR 4
74103 -#define EDID_SIZE_BLOCK1_TIMING_DESCRIPTOR 4
74104 -
74105 -#define HDMI_DEFAULT_REGN 16
74106 -#define HDMI_DEFAULT_REGM2 1
74107 -
74108 -static struct {
74109 - struct mutex lock;
74110 - struct platform_device *pdev;
74111 -
74112 - struct hdmi_ip_data ip_data;
74113 -
74114 - struct clk *sys_clk;
74115 - struct regulator *vdda_hdmi_dac_reg;
74116 -
74117 - bool core_enabled;
74118 -
74119 - struct omap_dss_device output;
74120 -} hdmi;
74121 -
74122 -/*
74123 - * Logic for the below structure :
74124 - * user enters the CEA or VESA timings by specifying the HDMI/DVI code.
74125 - * There is a correspondence between CEA/VESA timing and code, please
74126 - * refer to section 6.3 in HDMI 1.3 specification for timing code.
74127 - *
74128 - * In the below structure, cea_vesa_timings corresponds to all OMAP4
74129 - * supported CEA and VESA timing values.code_cea corresponds to the CEA
74130 - * code, It is used to get the timing from cea_vesa_timing array.Similarly
74131 - * with code_vesa. Code_index is used for back mapping, that is once EDID
74132 - * is read from the TV, EDID is parsed to find the timing values and then
74133 - * map it to corresponding CEA or VESA index.
74134 - */
74135 -
74136 -static const struct hdmi_config cea_timings[] = {
74137 - {
74138 - { 640, 480, 25200, 96, 16, 48, 2, 10, 33,
74139 - OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
74140 - false, },
74141 - { 1, HDMI_HDMI },
74142 - },
74143 - {
74144 - { 720, 480, 27027, 62, 16, 60, 6, 9, 30,
74145 - OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
74146 - false, },
74147 - { 2, HDMI_HDMI },
74148 - },
74149 - {
74150 - { 1280, 720, 74250, 40, 110, 220, 5, 5, 20,
74151 - OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
74152 - false, },
74153 - { 4, HDMI_HDMI },
74154 - },
74155 - {
74156 - { 1920, 540, 74250, 44, 88, 148, 5, 2, 15,
74157 - OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
74158 - true, },
74159 - { 5, HDMI_HDMI },
74160 - },
74161 - {
74162 - { 1440, 240, 27027, 124, 38, 114, 3, 4, 15,
74163 - OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
74164 - true, },
74165 - { 6, HDMI_HDMI },
74166 - },
74167 - {
74168 - { 1920, 1080, 148500, 44, 88, 148, 5, 4, 36,
74169 - OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
74170 - false, },
74171 - { 16, HDMI_HDMI },
74172 - },
74173 - {
74174 - { 720, 576, 27000, 64, 12, 68, 5, 5, 39,
74175 - OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
74176 - false, },
74177 - { 17, HDMI_HDMI },
74178 - },
74179 - {
74180 - { 1280, 720, 74250, 40, 440, 220, 5, 5, 20,
74181 - OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
74182 - false, },
74183 - { 19, HDMI_HDMI },
74184 - },
74185 - {
74186 - { 1920, 540, 74250, 44, 528, 148, 5, 2, 15,
74187 - OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
74188 - true, },
74189 - { 20, HDMI_HDMI },
74190 - },
74191 - {
74192 - { 1440, 288, 27000, 126, 24, 138, 3, 2, 19,
74193 - OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
74194 - true, },
74195 - { 21, HDMI_HDMI },
74196 - },
74197 - {
74198 - { 1440, 576, 54000, 128, 24, 136, 5, 5, 39,
74199 - OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
74200 - false, },
74201 - { 29, HDMI_HDMI },
74202 - },
74203 - {
74204 - { 1920, 1080, 148500, 44, 528, 148, 5, 4, 36,
74205 - OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
74206 - false, },
74207 - { 31, HDMI_HDMI },
74208 - },
74209 - {
74210 - { 1920, 1080, 74250, 44, 638, 148, 5, 4, 36,
74211 - OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
74212 - false, },
74213 - { 32, HDMI_HDMI },
74214 - },
74215 - {
74216 - { 2880, 480, 108108, 248, 64, 240, 6, 9, 30,
74217 - OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
74218 - false, },
74219 - { 35, HDMI_HDMI },
74220 - },
74221 - {
74222 - { 2880, 576, 108000, 256, 48, 272, 5, 5, 39,
74223 - OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
74224 - false, },
74225 - { 37, HDMI_HDMI },
74226 - },
74227 -};
74228 -
74229 -static const struct hdmi_config vesa_timings[] = {
74230 -/* VESA From Here */
74231 - {
74232 - { 640, 480, 25175, 96, 16, 48, 2, 11, 31,
74233 - OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
74234 - false, },
74235 - { 4, HDMI_DVI },
74236 - },
74237 - {
74238 - { 800, 600, 40000, 128, 40, 88, 4, 1, 23,
74239 - OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
74240 - false, },
74241 - { 9, HDMI_DVI },
74242 - },
74243 - {
74244 - { 848, 480, 33750, 112, 16, 112, 8, 6, 23,
74245 - OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
74246 - false, },
74247 - { 0xE, HDMI_DVI },
74248 - },
74249 - {
74250 - { 1280, 768, 79500, 128, 64, 192, 7, 3, 20,
74251 - OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
74252 - false, },
74253 - { 0x17, HDMI_DVI },
74254 - },
74255 - {
74256 - { 1280, 800, 83500, 128, 72, 200, 6, 3, 22,
74257 - OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
74258 - false, },
74259 - { 0x1C, HDMI_DVI },
74260 - },
74261 - {
74262 - { 1360, 768, 85500, 112, 64, 256, 6, 3, 18,
74263 - OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
74264 - false, },
74265 - { 0x27, HDMI_DVI },
74266 - },
74267 - {
74268 - { 1280, 960, 108000, 112, 96, 312, 3, 1, 36,
74269 - OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
74270 - false, },
74271 - { 0x20, HDMI_DVI },
74272 - },
74273 - {
74274 - { 1280, 1024, 108000, 112, 48, 248, 3, 1, 38,
74275 - OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
74276 - false, },
74277 - { 0x23, HDMI_DVI },
74278 - },
74279 - {
74280 - { 1024, 768, 65000, 136, 24, 160, 6, 3, 29,
74281 - OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
74282 - false, },
74283 - { 0x10, HDMI_DVI },
74284 - },
74285 - {
74286 - { 1400, 1050, 121750, 144, 88, 232, 4, 3, 32,
74287 - OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
74288 - false, },
74289 - { 0x2A, HDMI_DVI },
74290 - },
74291 - {
74292 - { 1440, 900, 106500, 152, 80, 232, 6, 3, 25,
74293 - OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
74294 - false, },
74295 - { 0x2F, HDMI_DVI },
74296 - },
74297 - {
74298 - { 1680, 1050, 146250, 176 , 104, 280, 6, 3, 30,
74299 - OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
74300 - false, },
74301 - { 0x3A, HDMI_DVI },
74302 - },
74303 - {
74304 - { 1366, 768, 85500, 143, 70, 213, 3, 3, 24,
74305 - OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
74306 - false, },
74307 - { 0x51, HDMI_DVI },
74308 - },
74309 - {
74310 - { 1920, 1080, 148500, 44, 148, 80, 5, 4, 36,
74311 - OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
74312 - false, },
74313 - { 0x52, HDMI_DVI },
74314 - },
74315 - {
74316 - { 1280, 768, 68250, 32, 48, 80, 7, 3, 12,
74317 - OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
74318 - false, },
74319 - { 0x16, HDMI_DVI },
74320 - },
74321 - {
74322 - { 1400, 1050, 101000, 32, 48, 80, 4, 3, 23,
74323 - OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
74324 - false, },
74325 - { 0x29, HDMI_DVI },
74326 - },
74327 - {
74328 - { 1680, 1050, 119000, 32, 48, 80, 6, 3, 21,
74329 - OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
74330 - false, },
74331 - { 0x39, HDMI_DVI },
74332 - },
74333 - {
74334 - { 1280, 800, 79500, 32, 48, 80, 6, 3, 14,
74335 - OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
74336 - false, },
74337 - { 0x1B, HDMI_DVI },
74338 - },
74339 - {
74340 - { 1280, 720, 74250, 40, 110, 220, 5, 5, 20,
74341 - OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
74342 - false, },
74343 - { 0x55, HDMI_DVI },
74344 - },
74345 - {
74346 - { 1920, 1200, 154000, 32, 48, 80, 6, 3, 26,
74347 - OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
74348 - false, },
74349 - { 0x44, HDMI_DVI },
74350 - },
74351 -};
74352 -
74353 -static int hdmi_runtime_get(void)
74354 -{
74355 - int r;
74356 -
74357 - DSSDBG("hdmi_runtime_get\n");
74358 -
74359 - r = pm_runtime_get_sync(&hdmi.pdev->dev);
74360 - WARN_ON(r < 0);
74361 - if (r < 0)
74362 - return r;
74363 -
74364 - return 0;
74365 -}
74366 -
74367 -static void hdmi_runtime_put(void)
74368 -{
74369 - int r;
74370 -
74371 - DSSDBG("hdmi_runtime_put\n");
74372 -
74373 - r = pm_runtime_put_sync(&hdmi.pdev->dev);
74374 - WARN_ON(r < 0 && r != -ENOSYS);
74375 -}
74376 -
74377 -static int hdmi_init_regulator(void)
74378 -{
74379 - struct regulator *reg;
74380 -
74381 - if (hdmi.vdda_hdmi_dac_reg != NULL)
74382 - return 0;
74383 -
74384 - reg = devm_regulator_get(&hdmi.pdev->dev, "vdda_hdmi_dac");
74385 -
74386 - /* DT HACK: try VDAC to make omapdss work for o4 sdp/panda */
74387 - if (IS_ERR(reg))
74388 - reg = devm_regulator_get(&hdmi.pdev->dev, "VDAC");
74389 -
74390 - if (IS_ERR(reg)) {
74391 - DSSERR("can't get VDDA_HDMI_DAC regulator\n");
74392 - return PTR_ERR(reg);
74393 - }
74394 -
74395 - hdmi.vdda_hdmi_dac_reg = reg;
74396 -
74397 - return 0;
74398 -}
74399 -
74400 -static const struct hdmi_config *hdmi_find_timing(
74401 - const struct hdmi_config *timings_arr,
74402 - int len)
74403 -{
74404 - int i;
74405 -
74406 - for (i = 0; i < len; i++) {
74407 - if (timings_arr[i].cm.code == hdmi.ip_data.cfg.cm.code)
74408 - return &timings_arr[i];
74409 - }
74410 - return NULL;
74411 -}
74412 -
74413 -static const struct hdmi_config *hdmi_get_timings(void)
74414 -{
74415 - const struct hdmi_config *arr;
74416 - int len;
74417 -
74418 - if (hdmi.ip_data.cfg.cm.mode == HDMI_DVI) {
74419 - arr = vesa_timings;
74420 - len = ARRAY_SIZE(vesa_timings);
74421 - } else {
74422 - arr = cea_timings;
74423 - len = ARRAY_SIZE(cea_timings);
74424 - }
74425 -
74426 - return hdmi_find_timing(arr, len);
74427 -}
74428 -
74429 -static bool hdmi_timings_compare(struct omap_video_timings *timing1,
74430 - const struct omap_video_timings *timing2)
74431 -{
74432 - int timing1_vsync, timing1_hsync, timing2_vsync, timing2_hsync;
74433 -
74434 - if ((DIV_ROUND_CLOSEST(timing2->pixel_clock, 1000) ==
74435 - DIV_ROUND_CLOSEST(timing1->pixel_clock, 1000)) &&
74436 - (timing2->x_res == timing1->x_res) &&
74437 - (timing2->y_res == timing1->y_res)) {
74438 -
74439 - timing2_hsync = timing2->hfp + timing2->hsw + timing2->hbp;
74440 - timing1_hsync = timing1->hfp + timing1->hsw + timing1->hbp;
74441 - timing2_vsync = timing2->vfp + timing2->vsw + timing2->vbp;
74442 - timing1_vsync = timing2->vfp + timing2->vsw + timing2->vbp;
74443 -
74444 - DSSDBG("timing1_hsync = %d timing1_vsync = %d"\
74445 - "timing2_hsync = %d timing2_vsync = %d\n",
74446 - timing1_hsync, timing1_vsync,
74447 - timing2_hsync, timing2_vsync);
74448 -
74449 - if ((timing1_hsync == timing2_hsync) &&
74450 - (timing1_vsync == timing2_vsync)) {
74451 - return true;
74452 - }
74453 - }
74454 - return false;
74455 -}
74456 -
74457 -static struct hdmi_cm hdmi_get_code(struct omap_video_timings *timing)
74458 -{
74459 - int i;
74460 - struct hdmi_cm cm = {-1};
74461 - DSSDBG("hdmi_get_code\n");
74462 -
74463 - for (i = 0; i < ARRAY_SIZE(cea_timings); i++) {
74464 - if (hdmi_timings_compare(timing, &cea_timings[i].timings)) {
74465 - cm = cea_timings[i].cm;
74466 - goto end;
74467 - }
74468 - }
74469 - for (i = 0; i < ARRAY_SIZE(vesa_timings); i++) {
74470 - if (hdmi_timings_compare(timing, &vesa_timings[i].timings)) {
74471 - cm = vesa_timings[i].cm;
74472 - goto end;
74473 - }
74474 - }
74475 -
74476 -end: return cm;
74477 -
74478 -}
74479 -
74480 -static void hdmi_compute_pll(struct omap_dss_device *dssdev, int phy,
74481 - struct hdmi_pll_info *pi)
74482 -{
74483 - unsigned long clkin, refclk;
74484 - u32 mf;
74485 -
74486 - clkin = clk_get_rate(hdmi.sys_clk) / 10000;
74487 - /*
74488 - * Input clock is predivided by N + 1
74489 - * out put of which is reference clk
74490 - */
74491 -
74492 - pi->regn = HDMI_DEFAULT_REGN;
74493 -
74494 - refclk = clkin / pi->regn;
74495 -
74496 - pi->regm2 = HDMI_DEFAULT_REGM2;
74497 -
74498 - /*
74499 - * multiplier is pixel_clk/ref_clk
74500 - * Multiplying by 100 to avoid fractional part removal
74501 - */
74502 - pi->regm = phy * pi->regm2 / refclk;
74503 -
74504 - /*
74505 - * fractional multiplier is remainder of the difference between
74506 - * multiplier and actual phy(required pixel clock thus should be
74507 - * multiplied by 2^18(262144) divided by the reference clock
74508 - */
74509 - mf = (phy - pi->regm / pi->regm2 * refclk) * 262144;
74510 - pi->regmf = pi->regm2 * mf / refclk;
74511 -
74512 - /*
74513 - * Dcofreq should be set to 1 if required pixel clock
74514 - * is greater than 1000MHz
74515 - */
74516 - pi->dcofreq = phy > 1000 * 100;
74517 - pi->regsd = ((pi->regm * clkin / 10) / (pi->regn * 250) + 5) / 10;
74518 -
74519 - /* Set the reference clock to sysclk reference */
74520 - pi->refsel = HDMI_REFSEL_SYSCLK;
74521 -
74522 - DSSDBG("M = %d Mf = %d\n", pi->regm, pi->regmf);
74523 - DSSDBG("range = %d sd = %d\n", pi->dcofreq, pi->regsd);
74524 -}
74525 -
74526 -static int hdmi_power_on_core(struct omap_dss_device *dssdev)
74527 -{
74528 - int r;
74529 -
74530 - r = regulator_enable(hdmi.vdda_hdmi_dac_reg);
74531 - if (r)
74532 - return r;
74533 -
74534 - r = hdmi_runtime_get();
74535 - if (r)
74536 - goto err_runtime_get;
74537 -
74538 - /* Make selection of HDMI in DSS */
74539 - dss_select_hdmi_venc_clk_source(DSS_HDMI_M_PCLK);
74540 -
74541 - hdmi.core_enabled = true;
74542 -
74543 - return 0;
74544 -
74545 -err_runtime_get:
74546 - regulator_disable(hdmi.vdda_hdmi_dac_reg);
74547 -
74548 - return r;
74549 -}
74550 -
74551 -static void hdmi_power_off_core(struct omap_dss_device *dssdev)
74552 -{
74553 - hdmi.core_enabled = false;
74554 -
74555 - hdmi_runtime_put();
74556 - regulator_disable(hdmi.vdda_hdmi_dac_reg);
74557 -}
74558 -
74559 -static int hdmi_power_on_full(struct omap_dss_device *dssdev)
74560 -{
74561 - int r;
74562 - struct omap_video_timings *p;
74563 - struct omap_overlay_manager *mgr = hdmi.output.manager;
74564 - unsigned long phy;
74565 -
74566 - r = hdmi_power_on_core(dssdev);
74567 - if (r)
74568 - return r;
74569 -
74570 - dss_mgr_disable(mgr);
74571 -
74572 - p = &hdmi.ip_data.cfg.timings;
74573 -
74574 - DSSDBG("hdmi_power_on x_res= %d y_res = %d\n", p->x_res, p->y_res);
74575 -
74576 - phy = p->pixel_clock;
74577 -
74578 - hdmi_compute_pll(dssdev, phy, &hdmi.ip_data.pll_data);
74579 -
74580 - hdmi.ip_data.ops->video_disable(&hdmi.ip_data);
74581 -
74582 - /* config the PLL and PHY hdmi_set_pll_pwrfirst */
74583 - r = hdmi.ip_data.ops->pll_enable(&hdmi.ip_data);
74584 - if (r) {
74585 - DSSDBG("Failed to lock PLL\n");
74586 - goto err_pll_enable;
74587 - }
74588 -
74589 - r = hdmi.ip_data.ops->phy_enable(&hdmi.ip_data);
74590 - if (r) {
74591 - DSSDBG("Failed to start PHY\n");
74592 - goto err_phy_enable;
74593 - }
74594 -
74595 - hdmi.ip_data.ops->video_configure(&hdmi.ip_data);
74596 -
74597 - /* bypass TV gamma table */
74598 - dispc_enable_gamma_table(0);
74599 -
74600 - /* tv size */
74601 - dss_mgr_set_timings(mgr, p);
74602 -
74603 - r = hdmi.ip_data.ops->video_enable(&hdmi.ip_data);
74604 - if (r)
74605 - goto err_vid_enable;
74606 -
74607 - r = dss_mgr_enable(mgr);
74608 - if (r)
74609 - goto err_mgr_enable;
74610 -
74611 - return 0;
74612 -
74613 -err_mgr_enable:
74614 - hdmi.ip_data.ops->video_disable(&hdmi.ip_data);
74615 -err_vid_enable:
74616 - hdmi.ip_data.ops->phy_disable(&hdmi.ip_data);
74617 -err_phy_enable:
74618 - hdmi.ip_data.ops->pll_disable(&hdmi.ip_data);
74619 -err_pll_enable:
74620 - hdmi_power_off_core(dssdev);
74621 - return -EIO;
74622 -}
74623 -
74624 -static void hdmi_power_off_full(struct omap_dss_device *dssdev)
74625 -{
74626 - struct omap_overlay_manager *mgr = hdmi.output.manager;
74627 -
74628 - dss_mgr_disable(mgr);
74629 -
74630 - hdmi.ip_data.ops->video_disable(&hdmi.ip_data);
74631 - hdmi.ip_data.ops->phy_disable(&hdmi.ip_data);
74632 - hdmi.ip_data.ops->pll_disable(&hdmi.ip_data);
74633 -
74634 - hdmi_power_off_core(dssdev);
74635 -}
74636 -
74637 -static int hdmi_display_check_timing(struct omap_dss_device *dssdev,
74638 - struct omap_video_timings *timings)
74639 -{
74640 - struct hdmi_cm cm;
74641 -
74642 - cm = hdmi_get_code(timings);
74643 - if (cm.code == -1) {
74644 - return -EINVAL;
74645 - }
74646 -
74647 - return 0;
74648 -
74649 -}
74650 -
74651 -static void hdmi_display_set_timing(struct omap_dss_device *dssdev,
74652 - struct omap_video_timings *timings)
74653 -{
74654 - struct hdmi_cm cm;
74655 - const struct hdmi_config *t;
74656 -
74657 - mutex_lock(&hdmi.lock);
74658 -
74659 - cm = hdmi_get_code(timings);
74660 - hdmi.ip_data.cfg.cm = cm;
74661 -
74662 - t = hdmi_get_timings();
74663 - if (t != NULL) {
74664 - hdmi.ip_data.cfg = *t;
74665 -
74666 - dispc_set_tv_pclk(t->timings.pixel_clock * 1000);
74667 - }
74668 -
74669 - mutex_unlock(&hdmi.lock);
74670 -}
74671 -
74672 -static void hdmi_display_get_timings(struct omap_dss_device *dssdev,
74673 - struct omap_video_timings *timings)
74674 -{
74675 - const struct hdmi_config *cfg;
74676 -
74677 - cfg = hdmi_get_timings();
74678 - if (cfg == NULL)
74679 - cfg = &vesa_timings[0];
74680 -
74681 - memcpy(timings, &cfg->timings, sizeof(cfg->timings));
74682 -}
74683 -
74684 -static void hdmi_dump_regs(struct seq_file *s)
74685 -{
74686 - mutex_lock(&hdmi.lock);
74687 -
74688 - if (hdmi_runtime_get()) {
74689 - mutex_unlock(&hdmi.lock);
74690 - return;
74691 - }
74692 -
74693 - hdmi.ip_data.ops->dump_wrapper(&hdmi.ip_data, s);
74694 - hdmi.ip_data.ops->dump_pll(&hdmi.ip_data, s);
74695 - hdmi.ip_data.ops->dump_phy(&hdmi.ip_data, s);
74696 - hdmi.ip_data.ops->dump_core(&hdmi.ip_data, s);
74697 -
74698 - hdmi_runtime_put();
74699 - mutex_unlock(&hdmi.lock);
74700 -}
74701 -
74702 -static int read_edid(u8 *buf, int len)
74703 -{
74704 - int r;
74705 -
74706 - mutex_lock(&hdmi.lock);
74707 -
74708 - r = hdmi_runtime_get();
74709 - BUG_ON(r);
74710 -
74711 - r = hdmi.ip_data.ops->read_edid(&hdmi.ip_data, buf, len);
74712 -
74713 - hdmi_runtime_put();
74714 - mutex_unlock(&hdmi.lock);
74715 -
74716 - return r;
74717 -}
74718 -
74719 -static int hdmi_display_enable(struct omap_dss_device *dssdev)
74720 -{
74721 - struct omap_dss_device *out = &hdmi.output;
74722 - int r = 0;
74723 -
74724 - DSSDBG("ENTER hdmi_display_enable\n");
74725 -
74726 - mutex_lock(&hdmi.lock);
74727 -
74728 - if (out == NULL || out->manager == NULL) {
74729 - DSSERR("failed to enable display: no output/manager\n");
74730 - r = -ENODEV;
74731 - goto err0;
74732 - }
74733 -
74734 - r = hdmi_power_on_full(dssdev);
74735 - if (r) {
74736 - DSSERR("failed to power on device\n");
74737 - goto err0;
74738 - }
74739 -
74740 - mutex_unlock(&hdmi.lock);
74741 - return 0;
74742 -
74743 -err0:
74744 - mutex_unlock(&hdmi.lock);
74745 - return r;
74746 -}
74747 -
74748 -static void hdmi_display_disable(struct omap_dss_device *dssdev)
74749 -{
74750 - DSSDBG("Enter hdmi_display_disable\n");
74751 -
74752 - mutex_lock(&hdmi.lock);
74753 -
74754 - hdmi_power_off_full(dssdev);
74755 -
74756 - mutex_unlock(&hdmi.lock);
74757 -}
74758 -
74759 -static int hdmi_core_enable(struct omap_dss_device *dssdev)
74760 -{
74761 - int r = 0;
74762 -
74763 - DSSDBG("ENTER omapdss_hdmi_core_enable\n");
74764 -
74765 - mutex_lock(&hdmi.lock);
74766 -
74767 - r = hdmi_power_on_core(dssdev);
74768 - if (r) {
74769 - DSSERR("failed to power on device\n");
74770 - goto err0;
74771 - }
74772 -
74773 - mutex_unlock(&hdmi.lock);
74774 - return 0;
74775 -
74776 -err0:
74777 - mutex_unlock(&hdmi.lock);
74778 - return r;
74779 -}
74780 -
74781 -static void hdmi_core_disable(struct omap_dss_device *dssdev)
74782 -{
74783 - DSSDBG("Enter omapdss_hdmi_core_disable\n");
74784 -
74785 - mutex_lock(&hdmi.lock);
74786 -
74787 - hdmi_power_off_core(dssdev);
74788 -
74789 - mutex_unlock(&hdmi.lock);
74790 -}
74791 -
74792 -static int hdmi_get_clocks(struct platform_device *pdev)
74793 -{
74794 - struct clk *clk;
74795 -
74796 - clk = devm_clk_get(&pdev->dev, "sys_clk");
74797 - if (IS_ERR(clk)) {
74798 - DSSERR("can't get sys_clk\n");
74799 - return PTR_ERR(clk);
74800 - }
74801 -
74802 - hdmi.sys_clk = clk;
74803 -
74804 - return 0;
74805 -}
74806 -
74807 -#if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO)
74808 -int hdmi_compute_acr(u32 sample_freq, u32 *n, u32 *cts)
74809 -{
74810 - u32 deep_color;
74811 - bool deep_color_correct = false;
74812 - u32 pclk = hdmi.ip_data.cfg.timings.pixel_clock;
74813 -
74814 - if (n == NULL || cts == NULL)
74815 - return -EINVAL;
74816 -
74817 - /* TODO: When implemented, query deep color mode here. */
74818 - deep_color = 100;
74819 -
74820 - /*
74821 - * When using deep color, the default N value (as in the HDMI
74822 - * specification) yields to an non-integer CTS. Hence, we
74823 - * modify it while keeping the restrictions described in
74824 - * section 7.2.1 of the HDMI 1.4a specification.
74825 - */
74826 - switch (sample_freq) {
74827 - case 32000:
74828 - case 48000:
74829 - case 96000:
74830 - case 192000:
74831 - if (deep_color == 125)
74832 - if (pclk == 27027 || pclk == 74250)
74833 - deep_color_correct = true;
74834 - if (deep_color == 150)
74835 - if (pclk == 27027)
74836 - deep_color_correct = true;
74837 - break;
74838 - case 44100:
74839 - case 88200:
74840 - case 176400:
74841 - if (deep_color == 125)
74842 - if (pclk == 27027)
74843 - deep_color_correct = true;
74844 - break;
74845 - default:
74846 - return -EINVAL;
74847 - }
74848 -
74849 - if (deep_color_correct) {
74850 - switch (sample_freq) {
74851 - case 32000:
74852 - *n = 8192;
74853 - break;
74854 - case 44100:
74855 - *n = 12544;
74856 - break;
74857 - case 48000:
74858 - *n = 8192;
74859 - break;
74860 - case 88200:
74861 - *n = 25088;
74862 - break;
74863 - case 96000:
74864 - *n = 16384;
74865 - break;
74866 - case 176400:
74867 - *n = 50176;
74868 - break;
74869 - case 192000:
74870 - *n = 32768;
74871 - break;
74872 - default:
74873 - return -EINVAL;
74874 - }
74875 - } else {
74876 - switch (sample_freq) {
74877 - case 32000:
74878 - *n = 4096;
74879 - break;
74880 - case 44100:
74881 - *n = 6272;
74882 - break;
74883 - case 48000:
74884 - *n = 6144;
74885 - break;
74886 - case 88200:
74887 - *n = 12544;
74888 - break;
74889 - case 96000:
74890 - *n = 12288;
74891 - break;
74892 - case 176400:
74893 - *n = 25088;
74894 - break;
74895 - case 192000:
74896 - *n = 24576;
74897 - break;
74898 - default:
74899 - return -EINVAL;
74900 - }
74901 - }
74902 - /* Calculate CTS. See HDMI 1.3a or 1.4a specifications */
74903 - *cts = pclk * (*n / 128) * deep_color / (sample_freq / 10);
74904 -
74905 - return 0;
74906 -}
74907 -
74908 -static bool hdmi_mode_has_audio(void)
74909 -{
74910 - if (hdmi.ip_data.cfg.cm.mode == HDMI_HDMI)
74911 - return true;
74912 - else
74913 - return false;
74914 -}
74915 -
74916 -#endif
74917 -
74918 -static int hdmi_connect(struct omap_dss_device *dssdev,
74919 - struct omap_dss_device *dst)
74920 -{
74921 - struct omap_overlay_manager *mgr;
74922 - int r;
74923 -
74924 - dss_init_hdmi_ip_ops(&hdmi.ip_data, omapdss_get_version());
74925 -
74926 - r = hdmi_init_regulator();
74927 - if (r)
74928 - return r;
74929 -
74930 - mgr = omap_dss_get_overlay_manager(dssdev->dispc_channel);
74931 - if (!mgr)
74932 - return -ENODEV;
74933 -
74934 - r = dss_mgr_connect(mgr, dssdev);
74935 - if (r)
74936 - return r;
74937 -
74938 - r = omapdss_output_set_device(dssdev, dst);
74939 - if (r) {
74940 - DSSERR("failed to connect output to new device: %s\n",
74941 - dst->name);
74942 - dss_mgr_disconnect(mgr, dssdev);
74943 - return r;
74944 - }
74945 -
74946 - return 0;
74947 -}
74948 -
74949 -static void hdmi_disconnect(struct omap_dss_device *dssdev,
74950 - struct omap_dss_device *dst)
74951 -{
74952 - WARN_ON(dst != dssdev->dst);
74953 -
74954 - if (dst != dssdev->dst)
74955 - return;
74956 -
74957 - omapdss_output_unset_device(dssdev);
74958 -
74959 - if (dssdev->manager)
74960 - dss_mgr_disconnect(dssdev->manager, dssdev);
74961 -}
74962 -
74963 -static int hdmi_read_edid(struct omap_dss_device *dssdev,
74964 - u8 *edid, int len)
74965 -{
74966 - bool need_enable;
74967 - int r;
74968 -
74969 - need_enable = hdmi.core_enabled == false;
74970 -
74971 - if (need_enable) {
74972 - r = hdmi_core_enable(dssdev);
74973 - if (r)
74974 - return r;
74975 - }
74976 -
74977 - r = read_edid(edid, len);
74978 -
74979 - if (need_enable)
74980 - hdmi_core_disable(dssdev);
74981 -
74982 - return r;
74983 -}
74984 -
74985 -#if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO)
74986 -static int hdmi_audio_enable(struct omap_dss_device *dssdev)
74987 -{
74988 - int r;
74989 -
74990 - mutex_lock(&hdmi.lock);
74991 -
74992 - if (!hdmi_mode_has_audio()) {
74993 - r = -EPERM;
74994 - goto err;
74995 - }
74996 -
74997 -
74998 - r = hdmi.ip_data.ops->audio_enable(&hdmi.ip_data);
74999 - if (r)
75000 - goto err;
75001 -
75002 - mutex_unlock(&hdmi.lock);
75003 - return 0;
75004 -
75005 -err:
75006 - mutex_unlock(&hdmi.lock);
75007 - return r;
75008 -}
75009 -
75010 -static void hdmi_audio_disable(struct omap_dss_device *dssdev)
75011 -{
75012 - hdmi.ip_data.ops->audio_disable(&hdmi.ip_data);
75013 -}
75014 -
75015 -static int hdmi_audio_start(struct omap_dss_device *dssdev)
75016 -{
75017 - return hdmi.ip_data.ops->audio_start(&hdmi.ip_data);
75018 -}
75019 -
75020 -static void hdmi_audio_stop(struct omap_dss_device *dssdev)
75021 -{
75022 - hdmi.ip_data.ops->audio_stop(&hdmi.ip_data);
75023 -}
75024 -
75025 -static bool hdmi_audio_supported(struct omap_dss_device *dssdev)
75026 -{
75027 - bool r;
75028 -
75029 - mutex_lock(&hdmi.lock);
75030 -
75031 - r = hdmi_mode_has_audio();
75032 -
75033 - mutex_unlock(&hdmi.lock);
75034 - return r;
75035 -}
75036 -
75037 -static int hdmi_audio_config(struct omap_dss_device *dssdev,
75038 - struct omap_dss_audio *audio)
75039 -{
75040 - int r;
75041 -
75042 - mutex_lock(&hdmi.lock);
75043 -
75044 - if (!hdmi_mode_has_audio()) {
75045 - r = -EPERM;
75046 - goto err;
75047 - }
75048 -
75049 - r = hdmi.ip_data.ops->audio_config(&hdmi.ip_data, audio);
75050 - if (r)
75051 - goto err;
75052 -
75053 - mutex_unlock(&hdmi.lock);
75054 - return 0;
75055 -
75056 -err:
75057 - mutex_unlock(&hdmi.lock);
75058 - return r;
75059 -}
75060 -#else
75061 -static int hdmi_audio_enable(struct omap_dss_device *dssdev)
75062 -{
75063 - return -EPERM;
75064 -}
75065 -
75066 -static void hdmi_audio_disable(struct omap_dss_device *dssdev)
75067 -{
75068 -}
75069 -
75070 -static int hdmi_audio_start(struct omap_dss_device *dssdev)
75071 -{
75072 - return -EPERM;
75073 -}
75074 -
75075 -static void hdmi_audio_stop(struct omap_dss_device *dssdev)
75076 -{
75077 -}
75078 -
75079 -static bool hdmi_audio_supported(struct omap_dss_device *dssdev)
75080 -{
75081 - return false;
75082 -}
75083 -
75084 -static int hdmi_audio_config(struct omap_dss_device *dssdev,
75085 - struct omap_dss_audio *audio)
75086 -{
75087 - return -EPERM;
75088 -}
75089 -#endif
75090 -
75091 -static const struct omapdss_hdmi_ops hdmi_ops = {
75092 - .connect = hdmi_connect,
75093 - .disconnect = hdmi_disconnect,
75094 -
75095 - .enable = hdmi_display_enable,
75096 - .disable = hdmi_display_disable,
75097 -
75098 - .check_timings = hdmi_display_check_timing,
75099 - .set_timings = hdmi_display_set_timing,
75100 - .get_timings = hdmi_display_get_timings,
75101 -
75102 - .read_edid = hdmi_read_edid,
75103 -
75104 - .audio_enable = hdmi_audio_enable,
75105 - .audio_disable = hdmi_audio_disable,
75106 - .audio_start = hdmi_audio_start,
75107 - .audio_stop = hdmi_audio_stop,
75108 - .audio_supported = hdmi_audio_supported,
75109 - .audio_config = hdmi_audio_config,
75110 -};
75111 -
75112 -static void hdmi_init_output(struct platform_device *pdev)
75113 -{
75114 - struct omap_dss_device *out = &hdmi.output;
75115 -
75116 - out->dev = &pdev->dev;
75117 - out->id = OMAP_DSS_OUTPUT_HDMI;
75118 - out->output_type = OMAP_DISPLAY_TYPE_HDMI;
75119 - out->name = "hdmi.0";
75120 - out->dispc_channel = OMAP_DSS_CHANNEL_DIGIT;
75121 - out->ops.hdmi = &hdmi_ops;
75122 - out->owner = THIS_MODULE;
75123 -
75124 - omapdss_register_output(out);
75125 -}
75126 -
75127 -static void __exit hdmi_uninit_output(struct platform_device *pdev)
75128 -{
75129 - struct omap_dss_device *out = &hdmi.output;
75130 -
75131 - omapdss_unregister_output(out);
75132 -}
75133 -
75134 -/* HDMI HW IP initialisation */
75135 -static int omapdss_hdmihw_probe(struct platform_device *pdev)
75136 -{
75137 - struct resource *res;
75138 - int r;
75139 -
75140 - hdmi.pdev = pdev;
75141 -
75142 - mutex_init(&hdmi.lock);
75143 - mutex_init(&hdmi.ip_data.lock);
75144 -
75145 - res = platform_get_resource(hdmi.pdev, IORESOURCE_MEM, 0);
75146 -
75147 - /* Base address taken from platform */
75148 - hdmi.ip_data.base_wp = devm_ioremap_resource(&pdev->dev, res);
75149 - if (IS_ERR(hdmi.ip_data.base_wp))
75150 - return PTR_ERR(hdmi.ip_data.base_wp);
75151 -
75152 - hdmi.ip_data.irq = platform_get_irq(pdev, 0);
75153 - if (hdmi.ip_data.irq < 0) {
75154 - DSSERR("platform_get_irq failed\n");
75155 - return -ENODEV;
75156 - }
75157 -
75158 - r = hdmi_get_clocks(pdev);
75159 - if (r) {
75160 - DSSERR("can't get clocks\n");
75161 - return r;
75162 - }
75163 -
75164 - pm_runtime_enable(&pdev->dev);
75165 -
75166 - hdmi.ip_data.core_sys_offset = HDMI_CORE_SYS;
75167 - hdmi.ip_data.core_av_offset = HDMI_CORE_AV;
75168 - hdmi.ip_data.pll_offset = HDMI_PLLCTRL;
75169 - hdmi.ip_data.phy_offset = HDMI_PHY;
75170 -
75171 - hdmi_init_output(pdev);
75172 -
75173 - dss_debugfs_create_file("hdmi", hdmi_dump_regs);
75174 -
75175 - return 0;
75176 -}
75177 -
75178 -static int __exit omapdss_hdmihw_remove(struct platform_device *pdev)
75179 -{
75180 - hdmi_uninit_output(pdev);
75181 -
75182 - pm_runtime_disable(&pdev->dev);
75183 -
75184 - return 0;
75185 -}
75186 -
75187 -static int hdmi_runtime_suspend(struct device *dev)
75188 -{
75189 - clk_disable_unprepare(hdmi.sys_clk);
75190 -
75191 - dispc_runtime_put();
75192 -
75193 - return 0;
75194 -}
75195 -
75196 -static int hdmi_runtime_resume(struct device *dev)
75197 -{
75198 - int r;
75199 -
75200 - r = dispc_runtime_get();
75201 - if (r < 0)
75202 - return r;
75203 -
75204 - clk_prepare_enable(hdmi.sys_clk);
75205 -
75206 - return 0;
75207 -}
75208 -
75209 -static const struct dev_pm_ops hdmi_pm_ops = {
75210 - .runtime_suspend = hdmi_runtime_suspend,
75211 - .runtime_resume = hdmi_runtime_resume,
75212 -};
75213 -
75214 -static struct platform_driver omapdss_hdmihw_driver = {
75215 - .probe = omapdss_hdmihw_probe,
75216 - .remove = __exit_p(omapdss_hdmihw_remove),
75217 - .driver = {
75218 - .name = "omapdss_hdmi",
75219 - .owner = THIS_MODULE,
75220 - .pm = &hdmi_pm_ops,
75221 - },
75222 -};
75223 -
75224 -int __init hdmi_init_platform_driver(void)
75225 -{
75226 - return platform_driver_register(&omapdss_hdmihw_driver);
75227 -}
75228 -
75229 -void __exit hdmi_uninit_platform_driver(void)
75230 -{
75231 - platform_driver_unregister(&omapdss_hdmihw_driver);
75232 -}
75233 --- /dev/null
75234 +++ b/drivers/video/omap2/dss/hdmi_common.c
75235 @@ -0,0 +1,423 @@
75236 +
75237 +/*
75238 + * Logic for the below structure :
75239 + * user enters the CEA or VESA timings by specifying the HDMI/DVI code.
75240 + * There is a correspondence between CEA/VESA timing and code, please
75241 + * refer to section 6.3 in HDMI 1.3 specification for timing code.
75242 + *
75243 + * In the below structure, cea_vesa_timings corresponds to all OMAP4
75244 + * supported CEA and VESA timing values.code_cea corresponds to the CEA
75245 + * code, It is used to get the timing from cea_vesa_timing array.Similarly
75246 + * with code_vesa. Code_index is used for back mapping, that is once EDID
75247 + * is read from the TV, EDID is parsed to find the timing values and then
75248 + * map it to corresponding CEA or VESA index.
75249 + */
75250 +
75251 +#include <linux/kernel.h>
75252 +#include <linux/err.h>
75253 +#include <video/omapdss.h>
75254 +
75255 +#include "hdmi.h"
75256 +
75257 +static const struct hdmi_config cea_timings[] = {
75258 + {
75259 + { 640, 480, 25200, 96, 16, 48, 2, 10, 33,
75260 + OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
75261 + false, },
75262 + { 1, HDMI_HDMI },
75263 + },
75264 + {
75265 + { 720, 480, 27027, 62, 16, 60, 6, 9, 30,
75266 + OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
75267 + false, },
75268 + { 2, HDMI_HDMI },
75269 + },
75270 + {
75271 + { 1280, 720, 74250, 40, 110, 220, 5, 5, 20,
75272 + OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
75273 + false, },
75274 + { 4, HDMI_HDMI },
75275 + },
75276 + {
75277 + { 1920, 540, 74250, 44, 88, 148, 5, 2, 15,
75278 + OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
75279 + true, },
75280 + { 5, HDMI_HDMI },
75281 + },
75282 + {
75283 + { 1440, 240, 27027, 124, 38, 114, 3, 4, 15,
75284 + OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
75285 + true, },
75286 + { 6, HDMI_HDMI },
75287 + },
75288 + {
75289 + { 1920, 1080, 148500, 44, 88, 148, 5, 4, 36,
75290 + OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
75291 + false, },
75292 + { 16, HDMI_HDMI },
75293 + },
75294 + {
75295 + { 720, 576, 27000, 64, 12, 68, 5, 5, 39,
75296 + OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
75297 + false, },
75298 + { 17, HDMI_HDMI },
75299 + },
75300 + {
75301 + { 1280, 720, 74250, 40, 440, 220, 5, 5, 20,
75302 + OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
75303 + false, },
75304 + { 19, HDMI_HDMI },
75305 + },
75306 + {
75307 + { 1920, 540, 74250, 44, 528, 148, 5, 2, 15,
75308 + OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
75309 + true, },
75310 + { 20, HDMI_HDMI },
75311 + },
75312 + {
75313 + { 1440, 288, 27000, 126, 24, 138, 3, 2, 19,
75314 + OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
75315 + true, },
75316 + { 21, HDMI_HDMI },
75317 + },
75318 + {
75319 + { 1440, 576, 54000, 128, 24, 136, 5, 5, 39,
75320 + OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
75321 + false, },
75322 + { 29, HDMI_HDMI },
75323 + },
75324 + {
75325 + { 1920, 1080, 148500, 44, 528, 148, 5, 4, 36,
75326 + OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
75327 + false, },
75328 + { 31, HDMI_HDMI },
75329 + },
75330 + {
75331 + { 1920, 1080, 74250, 44, 638, 148, 5, 4, 36,
75332 + OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
75333 + false, },
75334 + { 32, HDMI_HDMI },
75335 + },
75336 + {
75337 + { 2880, 480, 108108, 248, 64, 240, 6, 9, 30,
75338 + OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
75339 + false, },
75340 + { 35, HDMI_HDMI },
75341 + },
75342 + {
75343 + { 2880, 576, 108000, 256, 48, 272, 5, 5, 39,
75344 + OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
75345 + false, },
75346 + { 37, HDMI_HDMI },
75347 + },
75348 +};
75349 +
75350 +static const struct hdmi_config vesa_timings[] = {
75351 +/* VESA From Here */
75352 + {
75353 + { 640, 480, 25175, 96, 16, 48, 2, 11, 31,
75354 + OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
75355 + false, },
75356 + { 4, HDMI_DVI },
75357 + },
75358 + {
75359 + { 800, 600, 40000, 128, 40, 88, 4, 1, 23,
75360 + OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
75361 + false, },
75362 + { 9, HDMI_DVI },
75363 + },
75364 + {
75365 + { 848, 480, 33750, 112, 16, 112, 8, 6, 23,
75366 + OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
75367 + false, },
75368 + { 0xE, HDMI_DVI },
75369 + },
75370 + {
75371 + { 1280, 768, 79500, 128, 64, 192, 7, 3, 20,
75372 + OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
75373 + false, },
75374 + { 0x17, HDMI_DVI },
75375 + },
75376 + {
75377 + { 1280, 800, 83500, 128, 72, 200, 6, 3, 22,
75378 + OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
75379 + false, },
75380 + { 0x1C, HDMI_DVI },
75381 + },
75382 + {
75383 + { 1360, 768, 85500, 112, 64, 256, 6, 3, 18,
75384 + OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
75385 + false, },
75386 + { 0x27, HDMI_DVI },
75387 + },
75388 + {
75389 + { 1280, 960, 108000, 112, 96, 312, 3, 1, 36,
75390 + OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
75391 + false, },
75392 + { 0x20, HDMI_DVI },
75393 + },
75394 + {
75395 + { 1280, 1024, 108000, 112, 48, 248, 3, 1, 38,
75396 + OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
75397 + false, },
75398 + { 0x23, HDMI_DVI },
75399 + },
75400 + {
75401 + { 1024, 768, 65000, 136, 24, 160, 6, 3, 29,
75402 + OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
75403 + false, },
75404 + { 0x10, HDMI_DVI },
75405 + },
75406 + {
75407 + { 1400, 1050, 121750, 144, 88, 232, 4, 3, 32,
75408 + OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
75409 + false, },
75410 + { 0x2A, HDMI_DVI },
75411 + },
75412 + {
75413 + { 1440, 900, 106500, 152, 80, 232, 6, 3, 25,
75414 + OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
75415 + false, },
75416 + { 0x2F, HDMI_DVI },
75417 + },
75418 + {
75419 + { 1680, 1050, 146250, 176 , 104, 280, 6, 3, 30,
75420 + OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
75421 + false, },
75422 + { 0x3A, HDMI_DVI },
75423 + },
75424 + {
75425 + { 1366, 768, 85500, 143, 70, 213, 3, 3, 24,
75426 + OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
75427 + false, },
75428 + { 0x51, HDMI_DVI },
75429 + },
75430 + {
75431 + { 1920, 1080, 148500, 44, 148, 80, 5, 4, 36,
75432 + OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
75433 + false, },
75434 + { 0x52, HDMI_DVI },
75435 + },
75436 + {
75437 + { 1280, 768, 68250, 32, 48, 80, 7, 3, 12,
75438 + OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
75439 + false, },
75440 + { 0x16, HDMI_DVI },
75441 + },
75442 + {
75443 + { 1400, 1050, 101000, 32, 48, 80, 4, 3, 23,
75444 + OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
75445 + false, },
75446 + { 0x29, HDMI_DVI },
75447 + },
75448 + {
75449 + { 1680, 1050, 119000, 32, 48, 80, 6, 3, 21,
75450 + OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
75451 + false, },
75452 + { 0x39, HDMI_DVI },
75453 + },
75454 + {
75455 + { 1280, 800, 79500, 32, 48, 80, 6, 3, 14,
75456 + OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
75457 + false, },
75458 + { 0x1B, HDMI_DVI },
75459 + },
75460 + {
75461 + { 1280, 720, 74250, 40, 110, 220, 5, 5, 20,
75462 + OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
75463 + false, },
75464 + { 0x55, HDMI_DVI },
75465 + },
75466 + {
75467 + { 1920, 1200, 154000, 32, 48, 80, 6, 3, 26,
75468 + OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
75469 + false, },
75470 + { 0x44, HDMI_DVI },
75471 + },
75472 +};
75473 +
75474 +const struct hdmi_config *hdmi_default_timing(void)
75475 +{
75476 + return &vesa_timings[0];
75477 +}
75478 +
75479 +static const struct hdmi_config *hdmi_find_timing(int code,
75480 + const struct hdmi_config *timings_arr, int len)
75481 +{
75482 + int i;
75483 +
75484 + for (i = 0; i < len; i++) {
75485 + if (timings_arr[i].cm.code == code)
75486 + return &timings_arr[i];
75487 + }
75488 +
75489 + return NULL;
75490 +}
75491 +
75492 +const struct hdmi_config *hdmi_get_timings(int mode, int code)
75493 +{
75494 + const struct hdmi_config *arr;
75495 + int len;
75496 +
75497 + if (mode == HDMI_DVI) {
75498 + arr = vesa_timings;
75499 + len = ARRAY_SIZE(vesa_timings);
75500 + } else {
75501 + arr = cea_timings;
75502 + len = ARRAY_SIZE(cea_timings);
75503 + }
75504 +
75505 + return hdmi_find_timing(code, arr, len);
75506 +}
75507 +
75508 +static bool hdmi_timings_compare(struct omap_video_timings *timing1,
75509 + const struct omap_video_timings *timing2)
75510 +{
75511 + int timing1_vsync, timing1_hsync, timing2_vsync, timing2_hsync;
75512 +
75513 + if ((DIV_ROUND_CLOSEST(timing2->pixel_clock, 1000) ==
75514 + DIV_ROUND_CLOSEST(timing1->pixel_clock, 1000)) &&
75515 + (timing2->x_res == timing1->x_res) &&
75516 + (timing2->y_res == timing1->y_res)) {
75517 +
75518 + timing2_hsync = timing2->hfp + timing2->hsw + timing2->hbp;
75519 + timing1_hsync = timing1->hfp + timing1->hsw + timing1->hbp;
75520 + timing2_vsync = timing2->vfp + timing2->vsw + timing2->vbp;
75521 + timing1_vsync = timing2->vfp + timing2->vsw + timing2->vbp;
75522 +
75523 + DSSDBG("timing1_hsync = %d timing1_vsync = %d"\
75524 + "timing2_hsync = %d timing2_vsync = %d\n",
75525 + timing1_hsync, timing1_vsync,
75526 + timing2_hsync, timing2_vsync);
75527 +
75528 + if ((timing1_hsync == timing2_hsync) &&
75529 + (timing1_vsync == timing2_vsync)) {
75530 + return true;
75531 + }
75532 + }
75533 + return false;
75534 +}
75535 +
75536 +struct hdmi_cm hdmi_get_code(struct omap_video_timings *timing)
75537 +{
75538 + int i;
75539 + struct hdmi_cm cm = {-1};
75540 + DSSDBG("hdmi_get_code\n");
75541 +
75542 + for (i = 0; i < ARRAY_SIZE(cea_timings); i++) {
75543 + if (hdmi_timings_compare(timing, &cea_timings[i].timings)) {
75544 + cm = cea_timings[i].cm;
75545 + goto end;
75546 + }
75547 + }
75548 + for (i = 0; i < ARRAY_SIZE(vesa_timings); i++) {
75549 + if (hdmi_timings_compare(timing, &vesa_timings[i].timings)) {
75550 + cm = vesa_timings[i].cm;
75551 + goto end;
75552 + }
75553 + }
75554 +
75555 +end:
75556 + return cm;
75557 +}
75558 +
75559 +#if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO)
75560 +int hdmi_compute_acr(u32 pclk, u32 sample_freq, u32 *n, u32 *cts)
75561 +{
75562 + u32 deep_color;
75563 + bool deep_color_correct = false;
75564 +
75565 + if (n == NULL || cts == NULL)
75566 + return -EINVAL;
75567 +
75568 + /* TODO: When implemented, query deep color mode here. */
75569 + deep_color = 100;
75570 +
75571 + /*
75572 + * When using deep color, the default N value (as in the HDMI
75573 + * specification) yields to an non-integer CTS. Hence, we
75574 + * modify it while keeping the restrictions described in
75575 + * section 7.2.1 of the HDMI 1.4a specification.
75576 + */
75577 + switch (sample_freq) {
75578 + case 32000:
75579 + case 48000:
75580 + case 96000:
75581 + case 192000:
75582 + if (deep_color == 125)
75583 + if (pclk == 27027 || pclk == 74250)
75584 + deep_color_correct = true;
75585 + if (deep_color == 150)
75586 + if (pclk == 27027)
75587 + deep_color_correct = true;
75588 + break;
75589 + case 44100:
75590 + case 88200:
75591 + case 176400:
75592 + if (deep_color == 125)
75593 + if (pclk == 27027)
75594 + deep_color_correct = true;
75595 + break;
75596 + default:
75597 + return -EINVAL;
75598 + }
75599 +
75600 + if (deep_color_correct) {
75601 + switch (sample_freq) {
75602 + case 32000:
75603 + *n = 8192;
75604 + break;
75605 + case 44100:
75606 + *n = 12544;
75607 + break;
75608 + case 48000:
75609 + *n = 8192;
75610 + break;
75611 + case 88200:
75612 + *n = 25088;
75613 + break;
75614 + case 96000:
75615 + *n = 16384;
75616 + break;
75617 + case 176400:
75618 + *n = 50176;
75619 + break;
75620 + case 192000:
75621 + *n = 32768;
75622 + break;
75623 + default:
75624 + return -EINVAL;
75625 + }
75626 + } else {
75627 + switch (sample_freq) {
75628 + case 32000:
75629 + *n = 4096;
75630 + break;
75631 + case 44100:
75632 + *n = 6272;
75633 + break;
75634 + case 48000:
75635 + *n = 6144;
75636 + break;
75637 + case 88200:
75638 + *n = 12544;
75639 + break;
75640 + case 96000:
75641 + *n = 12288;
75642 + break;
75643 + case 176400:
75644 + *n = 25088;
75645 + break;
75646 + case 192000:
75647 + *n = 24576;
75648 + break;
75649 + default:
75650 + return -EINVAL;
75651 + }
75652 + }
75653 + /* Calculate CTS. See HDMI 1.3a or 1.4a specifications */
75654 + *cts = pclk * (*n / 128) * deep_color / (sample_freq / 10);
75655 +
75656 + return 0;
75657 +}
75658 +#endif
75659 --- /dev/null
75660 +++ b/drivers/video/omap2/dss/hdmi.h
75661 @@ -0,0 +1,441 @@
75662 +/*
75663 + * HDMI driver definition for TI OMAP4 Processor.
75664 + *
75665 + * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
75666 + *
75667 + * This program is free software; you can redistribute it and/or modify it
75668 + * under the terms of the GNU General Public License version 2 as published by
75669 + * the Free Software Foundation.
75670 + *
75671 + * This program is distributed in the hope that it will be useful, but WITHOUT
75672 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
75673 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
75674 + * more details.
75675 + *
75676 + * You should have received a copy of the GNU General Public License along with
75677 + * this program. If not, see <http://www.gnu.org/licenses/>.
75678 + */
75679 +
75680 +#ifndef _HDMI_H
75681 +#define _HDMI_H
75682 +
75683 +#include <linux/delay.h>
75684 +#include <linux/io.h>
75685 +#include <linux/platform_device.h>
75686 +#include <video/omapdss.h>
75687 +
75688 +#include "dss.h"
75689 +
75690 +/* HDMI Wrapper */
75691 +
75692 +#define HDMI_WP_REVISION 0x0
75693 +#define HDMI_WP_SYSCONFIG 0x10
75694 +#define HDMI_WP_IRQSTATUS_RAW 0x24
75695 +#define HDMI_WP_IRQSTATUS 0x28
75696 +#define HDMI_WP_IRQENABLE_SET 0x2C
75697 +#define HDMI_WP_IRQENABLE_CLR 0x30
75698 +#define HDMI_WP_IRQWAKEEN 0x34
75699 +#define HDMI_WP_PWR_CTRL 0x40
75700 +#define HDMI_WP_DEBOUNCE 0x44
75701 +#define HDMI_WP_VIDEO_CFG 0x50
75702 +#define HDMI_WP_VIDEO_SIZE 0x60
75703 +#define HDMI_WP_VIDEO_TIMING_H 0x68
75704 +#define HDMI_WP_VIDEO_TIMING_V 0x6C
75705 +#define HDMI_WP_CLK 0x70
75706 +#define HDMI_WP_AUDIO_CFG 0x80
75707 +#define HDMI_WP_AUDIO_CFG2 0x84
75708 +#define HDMI_WP_AUDIO_CTRL 0x88
75709 +#define HDMI_WP_AUDIO_DATA 0x8C
75710 +
75711 +/* HDMI WP IRQ flags */
75712 +#define HDMI_IRQ_CORE (1 << 0)
75713 +#define HDMI_IRQ_OCP_TIMEOUT (1 << 4)
75714 +#define HDMI_IRQ_AUDIO_FIFO_UNDERFLOW (1 << 8)
75715 +#define HDMI_IRQ_AUDIO_FIFO_OVERFLOW (1 << 9)
75716 +#define HDMI_IRQ_AUDIO_FIFO_SAMPLE_REQ (1 << 10)
75717 +#define HDMI_IRQ_VIDEO_VSYNC (1 << 16)
75718 +#define HDMI_IRQ_VIDEO_FRAME_DONE (1 << 17)
75719 +#define HDMI_IRQ_PHY_LINE5V_ASSERT (1 << 24)
75720 +#define HDMI_IRQ_LINK_CONNECT (1 << 25)
75721 +#define HDMI_IRQ_LINK_DISCONNECT (1 << 26)
75722 +#define HDMI_IRQ_PLL_LOCK (1 << 29)
75723 +#define HDMI_IRQ_PLL_UNLOCK (1 << 30)
75724 +#define HDMI_IRQ_PLL_RECAL (1 << 31)
75725 +
75726 +/* HDMI PLL */
75727 +
75728 +#define PLLCTRL_PLL_CONTROL 0x0
75729 +#define PLLCTRL_PLL_STATUS 0x4
75730 +#define PLLCTRL_PLL_GO 0x8
75731 +#define PLLCTRL_CFG1 0xC
75732 +#define PLLCTRL_CFG2 0x10
75733 +#define PLLCTRL_CFG3 0x14
75734 +#define PLLCTRL_SSC_CFG1 0x18
75735 +#define PLLCTRL_SSC_CFG2 0x1C
75736 +#define PLLCTRL_CFG4 0x20
75737 +
75738 +/* HDMI PHY */
75739 +
75740 +#define HDMI_TXPHY_TX_CTRL 0x0
75741 +#define HDMI_TXPHY_DIGITAL_CTRL 0x4
75742 +#define HDMI_TXPHY_POWER_CTRL 0x8
75743 +#define HDMI_TXPHY_PAD_CFG_CTRL 0xC
75744 +#define HDMI_TXPHY_BIST_CONTROL 0x1C
75745 +
75746 +enum hdmi_pll_pwr {
75747 + HDMI_PLLPWRCMD_ALLOFF = 0,
75748 + HDMI_PLLPWRCMD_PLLONLY = 1,
75749 + HDMI_PLLPWRCMD_BOTHON_ALLCLKS = 2,
75750 + HDMI_PLLPWRCMD_BOTHON_NOPHYCLK = 3
75751 +};
75752 +
75753 +enum hdmi_phy_pwr {
75754 + HDMI_PHYPWRCMD_OFF = 0,
75755 + HDMI_PHYPWRCMD_LDOON = 1,
75756 + HDMI_PHYPWRCMD_TXON = 2
75757 +};
75758 +
75759 +enum hdmi_core_hdmi_dvi {
75760 + HDMI_DVI = 0,
75761 + HDMI_HDMI = 1
75762 +};
75763 +
75764 +enum hdmi_clk_refsel {
75765 + HDMI_REFSEL_PCLK = 0,
75766 + HDMI_REFSEL_REF1 = 1,
75767 + HDMI_REFSEL_REF2 = 2,
75768 + HDMI_REFSEL_SYSCLK = 3
75769 +};
75770 +
75771 +enum hdmi_packing_mode {
75772 + HDMI_PACK_10b_RGB_YUV444 = 0,
75773 + HDMI_PACK_24b_RGB_YUV444_YUV422 = 1,
75774 + HDMI_PACK_20b_YUV422 = 2,
75775 + HDMI_PACK_ALREADYPACKED = 7
75776 +};
75777 +
75778 +enum hdmi_stereo_channels {
75779 + HDMI_AUDIO_STEREO_NOCHANNELS = 0,
75780 + HDMI_AUDIO_STEREO_ONECHANNEL = 1,
75781 + HDMI_AUDIO_STEREO_TWOCHANNELS = 2,
75782 + HDMI_AUDIO_STEREO_THREECHANNELS = 3,
75783 + HDMI_AUDIO_STEREO_FOURCHANNELS = 4
75784 +};
75785 +
75786 +enum hdmi_audio_type {
75787 + HDMI_AUDIO_TYPE_LPCM = 0,
75788 + HDMI_AUDIO_TYPE_IEC = 1
75789 +};
75790 +
75791 +enum hdmi_audio_justify {
75792 + HDMI_AUDIO_JUSTIFY_LEFT = 0,
75793 + HDMI_AUDIO_JUSTIFY_RIGHT = 1
75794 +};
75795 +
75796 +enum hdmi_audio_sample_order {
75797 + HDMI_AUDIO_SAMPLE_RIGHT_FIRST = 0,
75798 + HDMI_AUDIO_SAMPLE_LEFT_FIRST = 1
75799 +};
75800 +
75801 +enum hdmi_audio_samples_perword {
75802 + HDMI_AUDIO_ONEWORD_ONESAMPLE = 0,
75803 + HDMI_AUDIO_ONEWORD_TWOSAMPLES = 1
75804 +};
75805 +
75806 +enum hdmi_audio_sample_size {
75807 + HDMI_AUDIO_SAMPLE_16BITS = 0,
75808 + HDMI_AUDIO_SAMPLE_24BITS = 1
75809 +};
75810 +
75811 +enum hdmi_audio_transf_mode {
75812 + HDMI_AUDIO_TRANSF_DMA = 0,
75813 + HDMI_AUDIO_TRANSF_IRQ = 1
75814 +};
75815 +
75816 +enum hdmi_audio_blk_strt_end_sig {
75817 + HDMI_AUDIO_BLOCK_SIG_STARTEND_ON = 0,
75818 + HDMI_AUDIO_BLOCK_SIG_STARTEND_OFF = 1
75819 +};
75820 +
75821 +enum hdmi_core_audio_layout {
75822 + HDMI_AUDIO_LAYOUT_2CH = 0,
75823 + HDMI_AUDIO_LAYOUT_8CH = 1
75824 +};
75825 +
75826 +enum hdmi_core_cts_mode {
75827 + HDMI_AUDIO_CTS_MODE_HW = 0,
75828 + HDMI_AUDIO_CTS_MODE_SW = 1
75829 +};
75830 +
75831 +enum hdmi_audio_mclk_mode {
75832 + HDMI_AUDIO_MCLK_128FS = 0,
75833 + HDMI_AUDIO_MCLK_256FS = 1,
75834 + HDMI_AUDIO_MCLK_384FS = 2,
75835 + HDMI_AUDIO_MCLK_512FS = 3,
75836 + HDMI_AUDIO_MCLK_768FS = 4,
75837 + HDMI_AUDIO_MCLK_1024FS = 5,
75838 + HDMI_AUDIO_MCLK_1152FS = 6,
75839 + HDMI_AUDIO_MCLK_192FS = 7
75840 +};
75841 +
75842 +/* INFOFRAME_AVI_ and INFOFRAME_AUDIO_ definitions */
75843 +enum hdmi_core_infoframe {
75844 + HDMI_INFOFRAME_AVI_DB1Y_RGB = 0,
75845 + HDMI_INFOFRAME_AVI_DB1Y_YUV422 = 1,
75846 + HDMI_INFOFRAME_AVI_DB1Y_YUV444 = 2,
75847 + HDMI_INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_OFF = 0,
75848 + HDMI_INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_ON = 1,
75849 + HDMI_INFOFRAME_AVI_DB1B_NO = 0,
75850 + HDMI_INFOFRAME_AVI_DB1B_VERT = 1,
75851 + HDMI_INFOFRAME_AVI_DB1B_HORI = 2,
75852 + HDMI_INFOFRAME_AVI_DB1B_VERTHORI = 3,
75853 + HDMI_INFOFRAME_AVI_DB1S_0 = 0,
75854 + HDMI_INFOFRAME_AVI_DB1S_1 = 1,
75855 + HDMI_INFOFRAME_AVI_DB1S_2 = 2,
75856 + HDMI_INFOFRAME_AVI_DB2C_NO = 0,
75857 + HDMI_INFOFRAME_AVI_DB2C_ITU601 = 1,
75858 + HDMI_INFOFRAME_AVI_DB2C_ITU709 = 2,
75859 + HDMI_INFOFRAME_AVI_DB2C_EC_EXTENDED = 3,
75860 + HDMI_INFOFRAME_AVI_DB2M_NO = 0,
75861 + HDMI_INFOFRAME_AVI_DB2M_43 = 1,
75862 + HDMI_INFOFRAME_AVI_DB2M_169 = 2,
75863 + HDMI_INFOFRAME_AVI_DB2R_SAME = 8,
75864 + HDMI_INFOFRAME_AVI_DB2R_43 = 9,
75865 + HDMI_INFOFRAME_AVI_DB2R_169 = 10,
75866 + HDMI_INFOFRAME_AVI_DB2R_149 = 11,
75867 + HDMI_INFOFRAME_AVI_DB3ITC_NO = 0,
75868 + HDMI_INFOFRAME_AVI_DB3ITC_YES = 1,
75869 + HDMI_INFOFRAME_AVI_DB3EC_XVYUV601 = 0,
75870 + HDMI_INFOFRAME_AVI_DB3EC_XVYUV709 = 1,
75871 + HDMI_INFOFRAME_AVI_DB3Q_DEFAULT = 0,
75872 + HDMI_INFOFRAME_AVI_DB3Q_LR = 1,
75873 + HDMI_INFOFRAME_AVI_DB3Q_FR = 2,
75874 + HDMI_INFOFRAME_AVI_DB3SC_NO = 0,
75875 + HDMI_INFOFRAME_AVI_DB3SC_HORI = 1,
75876 + HDMI_INFOFRAME_AVI_DB3SC_VERT = 2,
75877 + HDMI_INFOFRAME_AVI_DB3SC_HORIVERT = 3,
75878 + HDMI_INFOFRAME_AVI_DB5PR_NO = 0,
75879 + HDMI_INFOFRAME_AVI_DB5PR_2 = 1,
75880 + HDMI_INFOFRAME_AVI_DB5PR_3 = 2,
75881 + HDMI_INFOFRAME_AVI_DB5PR_4 = 3,
75882 + HDMI_INFOFRAME_AVI_DB5PR_5 = 4,
75883 + HDMI_INFOFRAME_AVI_DB5PR_6 = 5,
75884 + HDMI_INFOFRAME_AVI_DB5PR_7 = 6,
75885 + HDMI_INFOFRAME_AVI_DB5PR_8 = 7,
75886 + HDMI_INFOFRAME_AVI_DB5PR_9 = 8,
75887 + HDMI_INFOFRAME_AVI_DB5PR_10 = 9,
75888 +};
75889 +
75890 +struct hdmi_cm {
75891 + int code;
75892 + int mode;
75893 +};
75894 +
75895 +struct hdmi_video_format {
75896 + enum hdmi_packing_mode packing_mode;
75897 + u32 y_res; /* Line per panel */
75898 + u32 x_res; /* pixel per line */
75899 +};
75900 +
75901 +struct hdmi_config {
75902 + struct omap_video_timings timings;
75903 + struct hdmi_cm cm;
75904 +};
75905 +
75906 +/* HDMI PLL structure */
75907 +struct hdmi_pll_info {
75908 + u16 regn;
75909 + u16 regm;
75910 + u32 regmf;
75911 + u16 regm2;
75912 + u16 regsd;
75913 + u16 dcofreq;
75914 + enum hdmi_clk_refsel refsel;
75915 +};
75916 +
75917 +struct hdmi_audio_format {
75918 + enum hdmi_stereo_channels stereo_channels;
75919 + u8 active_chnnls_msk;
75920 + enum hdmi_audio_type type;
75921 + enum hdmi_audio_justify justification;
75922 + enum hdmi_audio_sample_order sample_order;
75923 + enum hdmi_audio_samples_perword samples_per_word;
75924 + enum hdmi_audio_sample_size sample_size;
75925 + enum hdmi_audio_blk_strt_end_sig en_sig_blk_strt_end;
75926 +};
75927 +
75928 +struct hdmi_audio_dma {
75929 + u8 transfer_size;
75930 + u8 block_size;
75931 + enum hdmi_audio_transf_mode mode;
75932 + u16 fifo_threshold;
75933 +};
75934 +
75935 +struct hdmi_core_audio_i2s_config {
75936 + u8 in_length_bits;
75937 + u8 justification;
75938 + u8 sck_edge_mode;
75939 + u8 vbit;
75940 + u8 direction;
75941 + u8 shift;
75942 + u8 active_sds;
75943 +};
75944 +
75945 +struct hdmi_core_audio_config {
75946 + struct hdmi_core_audio_i2s_config i2s_cfg;
75947 + struct snd_aes_iec958 *iec60958_cfg;
75948 + bool fs_override;
75949 + u32 n;
75950 + u32 cts;
75951 + u32 aud_par_busclk;
75952 + enum hdmi_core_audio_layout layout;
75953 + enum hdmi_core_cts_mode cts_mode;
75954 + bool use_mclk;
75955 + enum hdmi_audio_mclk_mode mclk_mode;
75956 + bool en_acr_pkt;
75957 + bool en_dsd_audio;
75958 + bool en_parallel_aud_input;
75959 + bool en_spdif;
75960 +};
75961 +
75962 +/*
75963 + * Refer to section 8.2 in HDMI 1.3 specification for
75964 + * details about infoframe databytes
75965 + */
75966 +struct hdmi_core_infoframe_avi {
75967 + /* Y0, Y1 rgb,yCbCr */
75968 + u8 db1_format;
75969 + /* A0 Active information Present */
75970 + u8 db1_active_info;
75971 + /* B0, B1 Bar info data valid */
75972 + u8 db1_bar_info_dv;
75973 + /* S0, S1 scan information */
75974 + u8 db1_scan_info;
75975 + /* C0, C1 colorimetry */
75976 + u8 db2_colorimetry;
75977 + /* M0, M1 Aspect ratio (4:3, 16:9) */
75978 + u8 db2_aspect_ratio;
75979 + /* R0...R3 Active format aspect ratio */
75980 + u8 db2_active_fmt_ar;
75981 + /* ITC IT content. */
75982 + u8 db3_itc;
75983 + /* EC0, EC1, EC2 Extended colorimetry */
75984 + u8 db3_ec;
75985 + /* Q1, Q0 Quantization range */
75986 + u8 db3_q_range;
75987 + /* SC1, SC0 Non-uniform picture scaling */
75988 + u8 db3_nup_scaling;
75989 + /* VIC0..6 Video format identification */
75990 + u8 db4_videocode;
75991 + /* PR0..PR3 Pixel repetition factor */
75992 + u8 db5_pixel_repeat;
75993 + /* Line number end of top bar */
75994 + u16 db6_7_line_eoftop;
75995 + /* Line number start of bottom bar */
75996 + u16 db8_9_line_sofbottom;
75997 + /* Pixel number end of left bar */
75998 + u16 db10_11_pixel_eofleft;
75999 + /* Pixel number start of right bar */
76000 + u16 db12_13_pixel_sofright;
76001 +};
76002 +
76003 +struct hdmi_wp_data {
76004 + void __iomem *base;
76005 +};
76006 +
76007 +struct hdmi_pll_data {
76008 + void __iomem *base;
76009 +
76010 + struct hdmi_pll_info info;
76011 +};
76012 +
76013 +struct hdmi_phy_data {
76014 + void __iomem *base;
76015 +};
76016 +
76017 +struct hdmi_core_data {
76018 + void __iomem *base;
76019 +
76020 + struct hdmi_core_infoframe_avi avi_cfg;
76021 +};
76022 +
76023 +static inline void hdmi_write_reg(void __iomem *base_addr, const u32 idx,
76024 + u32 val)
76025 +{
76026 + __raw_writel(val, base_addr + idx);
76027 +}
76028 +
76029 +static inline u32 hdmi_read_reg(void __iomem *base_addr, const u32 idx)
76030 +{
76031 + return __raw_readl(base_addr + idx);
76032 +}
76033 +
76034 +#define REG_FLD_MOD(base, idx, val, start, end) \
76035 + hdmi_write_reg(base, idx, FLD_MOD(hdmi_read_reg(base, idx),\
76036 + val, start, end))
76037 +#define REG_GET(base, idx, start, end) \
76038 + FLD_GET(hdmi_read_reg(base, idx), start, end)
76039 +
76040 +static inline int hdmi_wait_for_bit_change(void __iomem *base_addr,
76041 + const u32 idx, int b2, int b1, u32 val)
76042 +{
76043 + u32 t = 0, v;
76044 + while (val != (v = REG_GET(base_addr, idx, b2, b1))) {
76045 + if (t++ > 10000)
76046 + return v;
76047 + udelay(1);
76048 + }
76049 + return v;
76050 +}
76051 +
76052 +/* HDMI wrapper funcs */
76053 +int hdmi_wp_video_start(struct hdmi_wp_data *wp);
76054 +void hdmi_wp_video_stop(struct hdmi_wp_data *wp);
76055 +void hdmi_wp_dump(struct hdmi_wp_data *wp, struct seq_file *s);
76056 +u32 hdmi_wp_get_irqstatus(struct hdmi_wp_data *wp);
76057 +void hdmi_wp_set_irqstatus(struct hdmi_wp_data *wp, u32 irqstatus);
76058 +void hdmi_wp_set_irqenable(struct hdmi_wp_data *wp, u32 mask);
76059 +void hdmi_wp_clear_irqenable(struct hdmi_wp_data *wp, u32 mask);
76060 +int hdmi_wp_set_phy_pwr(struct hdmi_wp_data *wp, enum hdmi_phy_pwr val);
76061 +int hdmi_wp_set_pll_pwr(struct hdmi_wp_data *wp, enum hdmi_pll_pwr val);
76062 +void hdmi_wp_video_config_format(struct hdmi_wp_data *wp,
76063 + struct hdmi_video_format *video_fmt);
76064 +void hdmi_wp_video_config_interface(struct hdmi_wp_data *wp,
76065 + struct omap_video_timings *timings);
76066 +void hdmi_wp_video_config_timing(struct hdmi_wp_data *wp,
76067 + struct omap_video_timings *timings);
76068 +void hdmi_wp_init_vid_fmt_timings(struct hdmi_video_format *video_fmt,
76069 + struct omap_video_timings *timings, struct hdmi_config *param);
76070 +int hdmi_wp_init(struct platform_device *pdev, struct hdmi_wp_data *wp);
76071 +
76072 +/* HDMI PLL funcs */
76073 +int hdmi_pll_enable(struct hdmi_pll_data *pll, struct hdmi_wp_data *wp);
76074 +void hdmi_pll_disable(struct hdmi_pll_data *pll, struct hdmi_wp_data *wp);
76075 +void hdmi_pll_dump(struct hdmi_pll_data *pll, struct seq_file *s);
76076 +void hdmi_pll_compute(struct hdmi_pll_data *pll, unsigned long clkin, int phy);
76077 +int hdmi_pll_init(struct platform_device *pdev, struct hdmi_pll_data *pll);
76078 +
76079 +/* HDMI PHY funcs */
76080 +int hdmi_phy_configure(struct hdmi_phy_data *phy, struct hdmi_config *cfg);
76081 +void hdmi_phy_dump(struct hdmi_phy_data *phy, struct seq_file *s);
76082 +int hdmi_phy_init(struct platform_device *pdev, struct hdmi_phy_data *phy);
76083 +
76084 +/* HDMI common funcs */
76085 +const struct hdmi_config *hdmi_default_timing(void);
76086 +const struct hdmi_config *hdmi_get_timings(int mode, int code);
76087 +struct hdmi_cm hdmi_get_code(struct omap_video_timings *timing);
76088 +
76089 +#if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO) || defined(CONFIG_OMAP5_DSS_HDMI_AUDIO)
76090 +int hdmi_compute_acr(u32 pclk, u32 sample_freq, u32 *n, u32 *cts);
76091 +int hdmi_wp_audio_enable(struct hdmi_wp_data *wp, bool enable);
76092 +int hdmi_wp_audio_core_req_enable(struct hdmi_wp_data *wp, bool enable);
76093 +void hdmi_wp_audio_config_format(struct hdmi_wp_data *wp,
76094 + struct hdmi_audio_format *aud_fmt);
76095 +void hdmi_wp_audio_config_dma(struct hdmi_wp_data *wp,
76096 + struct hdmi_audio_dma *aud_dma);
76097 +static inline bool hdmi_mode_has_audio(int mode)
76098 +{
76099 + return mode == HDMI_HDMI ? true : false;
76100 +}
76101 +#endif
76102 +#endif
76103 --- /dev/null
76104 +++ b/drivers/video/omap2/dss/hdmi_phy.c
76105 @@ -0,0 +1,167 @@
76106 +/*
76107 + * HDMI PHY
76108 + *
76109 + * Copyright (C) 2013 Texas Instruments Incorporated
76110 + *
76111 + * This program is free software; you can redistribute it and/or modify it
76112 + * under the terms of the GNU General Public License version 2 as published by
76113 + * the Free Software Foundation.
76114 + */
76115 +
76116 +#include <linux/kernel.h>
76117 +#include <linux/err.h>
76118 +#include <linux/io.h>
76119 +#include <linux/platform_device.h>
76120 +#include <linux/slab.h>
76121 +#include <video/omapdss.h>
76122 +
76123 +#include "dss.h"
76124 +#include "hdmi.h"
76125 +
76126 +struct hdmi_phy_features {
76127 + bool bist_ctrl;
76128 + bool calc_freqout;
76129 + bool ldo_voltage;
76130 + unsigned long dcofreq_min; /* in KHz */
76131 + unsigned long max_phy; /* in KHz */
76132 +};
76133 +
76134 +static const struct hdmi_phy_features *phy_feat;
76135 +
76136 +void hdmi_phy_dump(struct hdmi_phy_data *phy, struct seq_file *s)
76137 +{
76138 +#define DUMPPHY(r) seq_printf(s, "%-35s %08x\n", #r,\
76139 + hdmi_read_reg(phy->base, r))
76140 +
76141 + DUMPPHY(HDMI_TXPHY_TX_CTRL);
76142 + DUMPPHY(HDMI_TXPHY_DIGITAL_CTRL);
76143 + DUMPPHY(HDMI_TXPHY_POWER_CTRL);
76144 + DUMPPHY(HDMI_TXPHY_PAD_CFG_CTRL);
76145 + if (phy_feat->bist_ctrl)
76146 + DUMPPHY(HDMI_TXPHY_BIST_CONTROL);
76147 +}
76148 +
76149 +int hdmi_phy_configure(struct hdmi_phy_data *phy, struct hdmi_config *cfg)
76150 +{
76151 + u8 freqout;
76152 +
76153 + /*
76154 + * Read address 0 in order to get the SCP reset done completed
76155 + * Dummy access performed to make sure reset is done
76156 + */
76157 + hdmi_read_reg(phy->base, HDMI_TXPHY_TX_CTRL);
76158 +
76159 + /*
76160 + * In OMAP5+, the HFBITCLK must be divided by 2 before issuing the
76161 + * HDMI_PHYPWRCMD_LDOON command.
76162 + */
76163 + if (phy_feat->bist_ctrl)
76164 + REG_FLD_MOD(phy->base, HDMI_TXPHY_BIST_CONTROL, 1, 11, 11);
76165 +
76166 + if (phy_feat->calc_freqout) {
76167 + /* DCOCLK/10 is pixel clock, compare pclk with DCOCLK_MIN/10 */
76168 + u32 dco_min = phy_feat->dcofreq_min / 10;
76169 + u32 pclk = cfg->timings.pixel_clock;
76170 +
76171 + if (pclk < dco_min) {
76172 + freqout = 0;
76173 + } else if ((pclk >= dco_min) && (pclk < phy_feat->max_phy)) {
76174 + freqout = 1;
76175 + } else {
76176 + freqout = 2;
76177 + }
76178 + } else {
76179 + freqout = 1;
76180 + }
76181 +
76182 + /*
76183 + * Write to phy address 0 to configure the clock
76184 + * use HFBITCLK write HDMI_TXPHY_TX_CONTROL_FREQOUT field
76185 + */
76186 + REG_FLD_MOD(phy->base, HDMI_TXPHY_TX_CTRL, freqout, 31, 30);
76187 +
76188 + /* Write to phy address 1 to start HDMI line (TXVALID and TMDSCLKEN) */
76189 + hdmi_write_reg(phy->base, HDMI_TXPHY_DIGITAL_CTRL, 0xF0000000);
76190 +
76191 + /* Setup max LDO voltage */
76192 + if (phy_feat->ldo_voltage)
76193 + REG_FLD_MOD(phy->base, HDMI_TXPHY_POWER_CTRL, 0xB, 3, 0);
76194 +
76195 + /* Write to phy address 3 to change the polarity control */
76196 + REG_FLD_MOD(phy->base, HDMI_TXPHY_PAD_CFG_CTRL, 0x1, 27, 27);
76197 +
76198 + return 0;
76199 +}
76200 +
76201 +static const struct hdmi_phy_features omap44xx_phy_feats = {
76202 + .bist_ctrl = false,
76203 + .calc_freqout = false,
76204 + .ldo_voltage = true,
76205 + .dcofreq_min = 500000,
76206 + .max_phy = 185675,
76207 +};
76208 +
76209 +static const struct hdmi_phy_features omap54xx_phy_feats = {
76210 + .bist_ctrl = true,
76211 + .calc_freqout = true,
76212 + .ldo_voltage = false,
76213 + .dcofreq_min = 750000,
76214 + .max_phy = 186000,
76215 +};
76216 +
76217 +static int hdmi_phy_init_features(struct platform_device *pdev)
76218 +{
76219 + struct hdmi_phy_features *dst;
76220 + const struct hdmi_phy_features *src;
76221 +
76222 + dst = devm_kzalloc(&pdev->dev, sizeof(*dst), GFP_KERNEL);
76223 + if (!dst) {
76224 + dev_err(&pdev->dev, "Failed to allocate HDMI PHY Features\n");
76225 + return -ENOMEM;
76226 + }
76227 +
76228 + switch (omapdss_get_version()) {
76229 + case OMAPDSS_VER_OMAP4430_ES1:
76230 + case OMAPDSS_VER_OMAP4430_ES2:
76231 + case OMAPDSS_VER_OMAP4:
76232 + src = &omap44xx_phy_feats;
76233 + break;
76234 +
76235 + case OMAPDSS_VER_OMAP5:
76236 + case OMAPDSS_VER_DRA7xx:
76237 + src = &omap54xx_phy_feats;
76238 + break;
76239 +
76240 + default:
76241 + return -ENODEV;
76242 + }
76243 +
76244 + memcpy(dst, src, sizeof(*dst));
76245 + phy_feat = dst;
76246 +
76247 + return 0;
76248 +}
76249 +
76250 +int hdmi_phy_init(struct platform_device *pdev, struct hdmi_phy_data *phy)
76251 +{
76252 + int r;
76253 + struct resource *res;
76254 +
76255 + r = hdmi_phy_init_features(pdev);
76256 + if (r)
76257 + return r;
76258 +
76259 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi_txphy");
76260 + if (!res) {
76261 + DSSERR("can't get PLL CTRL IORESOURCE_MEM HDMI\n");
76262 + return -EINVAL;
76263 + }
76264 +
76265 + phy->base = devm_request_and_ioremap(&pdev->dev, res);
76266 + if (!phy->base) {
76267 + DSSERR("can't ioremap PLL ctrl\n");
76268 + return -ENOMEM;
76269 + }
76270 +
76271 + return 0;
76272 +}
76273 --- /dev/null
76274 +++ b/drivers/video/omap2/dss/hdmi_pll.c
76275 @@ -0,0 +1,315 @@
76276 +/*
76277 + * HDMI PLL
76278 + *
76279 + * Copyright (C) 2013 Texas Instruments Incorporated
76280 + *
76281 + * This program is free software; you can redistribute it and/or modify it
76282 + * under the terms of the GNU General Public License version 2 as published by
76283 + * the Free Software Foundation.
76284 + */
76285 +
76286 +#include <linux/kernel.h>
76287 +#include <linux/module.h>
76288 +#include <linux/err.h>
76289 +#include <linux/io.h>
76290 +#include <linux/platform_device.h>
76291 +#include <video/omapdss.h>
76292 +
76293 +#include "dss.h"
76294 +#include "hdmi.h"
76295 +
76296 +#define HDMI_DEFAULT_REGN 16
76297 +#define HDMI_DEFAULT_REGM2 1
76298 +
76299 +struct hdmi_pll_features {
76300 + bool sys_reset;
76301 + /* this is a hack, need to replace it with a better computation of M2 */
76302 + bool bound_dcofreq;
76303 + bool ext_mux_ctrl;
76304 +
76305 + unsigned long fint_min, fint_max;
76306 + u16 regm_max;
76307 + unsigned long dcofreq_low_min, dcofreq_low_max;
76308 + unsigned long dcofreq_high_min, dcofreq_high_max;
76309 +};
76310 +
76311 +static const struct hdmi_pll_features *pll_feat;
76312 +
76313 +void hdmi_pll_dump(struct hdmi_pll_data *pll, struct seq_file *s)
76314 +{
76315 +#define DUMPPLL(r) seq_printf(s, "%-35s %08x\n", #r,\
76316 + hdmi_read_reg(pll->base, r))
76317 +
76318 + DUMPPLL(PLLCTRL_PLL_CONTROL);
76319 + DUMPPLL(PLLCTRL_PLL_STATUS);
76320 + DUMPPLL(PLLCTRL_PLL_GO);
76321 + DUMPPLL(PLLCTRL_CFG1);
76322 + DUMPPLL(PLLCTRL_CFG2);
76323 + DUMPPLL(PLLCTRL_CFG3);
76324 + DUMPPLL(PLLCTRL_SSC_CFG1);
76325 + DUMPPLL(PLLCTRL_SSC_CFG2);
76326 + DUMPPLL(PLLCTRL_CFG4);
76327 +}
76328 +
76329 +void hdmi_pll_compute(struct hdmi_pll_data *pll, unsigned long clkin, int phy)
76330 +{
76331 + struct hdmi_pll_info *pi = &pll->info;
76332 + unsigned long refclk;
76333 + u32 mf;
76334 +
76335 + /* use our funky units */
76336 + clkin /= 10000;
76337 +
76338 + /*
76339 + * Input clock is predivided by N + 1
76340 + * out put of which is reference clk
76341 + */
76342 +
76343 + pi->regn = HDMI_DEFAULT_REGN;
76344 +
76345 + refclk = clkin / pi->regn;
76346 +
76347 + /* temorary hack to make sure DCO freq isn't calculated too low */
76348 + if (pll_feat->bound_dcofreq && phy <= 65000)
76349 + pi->regm2 = 3;
76350 + else
76351 + pi->regm2 = HDMI_DEFAULT_REGM2;
76352 +
76353 + /*
76354 + * multiplier is pixel_clk/ref_clk
76355 + * Multiplying by 100 to avoid fractional part removal
76356 + */
76357 + pi->regm = phy * pi->regm2 / refclk;
76358 +
76359 + /*
76360 + * fractional multiplier is remainder of the difference between
76361 + * multiplier and actual phy(required pixel clock thus should be
76362 + * multiplied by 2^18(262144) divided by the reference clock
76363 + */
76364 + mf = (phy - pi->regm / pi->regm2 * refclk) * 262144;
76365 + pi->regmf = pi->regm2 * mf / refclk;
76366 +
76367 + /*
76368 + * Dcofreq should be set to 1 if required pixel clock
76369 + * is greater than 1000MHz
76370 + */
76371 + pi->dcofreq = phy > 1000 * 100;
76372 + pi->regsd = ((pi->regm * clkin / 10) / (pi->regn * 250) + 5) / 10;
76373 +
76374 + /* Set the reference clock to sysclk reference */
76375 + pi->refsel = HDMI_REFSEL_SYSCLK;
76376 +
76377 + DSSDBG("M = %d Mf = %d\n", pi->regm, pi->regmf);
76378 + DSSDBG("range = %d sd = %d\n", pi->dcofreq, pi->regsd);
76379 +}
76380 +
76381 +
76382 +static int hdmi_pll_config(struct hdmi_pll_data *pll)
76383 +{
76384 + u32 r;
76385 + struct hdmi_pll_info *fmt = &pll->info;
76386 +
76387 + /* PLL start always use manual mode */
76388 + REG_FLD_MOD(pll->base, PLLCTRL_PLL_CONTROL, 0x0, 0, 0);
76389 +
76390 + r = hdmi_read_reg(pll->base, PLLCTRL_CFG1);
76391 + r = FLD_MOD(r, fmt->regm, 20, 9); /* CFG1_PLL_REGM */
76392 + r = FLD_MOD(r, fmt->regn - 1, 8, 1); /* CFG1_PLL_REGN */
76393 + hdmi_write_reg(pll->base, PLLCTRL_CFG1, r);
76394 +
76395 + r = hdmi_read_reg(pll->base, PLLCTRL_CFG2);
76396 +
76397 + r = FLD_MOD(r, 0x0, 12, 12); /* PLL_HIGHFREQ divide by 2 */
76398 + r = FLD_MOD(r, 0x1, 13, 13); /* PLL_REFEN */
76399 + r = FLD_MOD(r, 0x0, 14, 14); /* PHY_CLKINEN de-assert during locking */
76400 + r = FLD_MOD(r, fmt->refsel, 22, 21); /* REFSEL */
76401 +
76402 + if (fmt->dcofreq) {
76403 + /* divider programming for frequency beyond 1000Mhz */
76404 + REG_FLD_MOD(pll->base, PLLCTRL_CFG3, fmt->regsd, 17, 10);
76405 + r = FLD_MOD(r, 0x4, 3, 1); /* 1000MHz and 2000MHz */
76406 + } else {
76407 + r = FLD_MOD(r, 0x2, 3, 1); /* 500MHz and 1000MHz */
76408 + }
76409 +
76410 + hdmi_write_reg(pll->base, PLLCTRL_CFG2, r);
76411 +
76412 + r = hdmi_read_reg(pll->base, PLLCTRL_CFG4);
76413 + r = FLD_MOD(r, fmt->regm2, 24, 18);
76414 + r = FLD_MOD(r, fmt->regmf, 17, 0);
76415 + hdmi_write_reg(pll->base, PLLCTRL_CFG4, r);
76416 +
76417 + /* go now */
76418 + REG_FLD_MOD(pll->base, PLLCTRL_PLL_GO, 0x1, 0, 0);
76419 +
76420 + /* wait for bit change */
76421 + if (hdmi_wait_for_bit_change(pll->base, PLLCTRL_PLL_GO,
76422 + 0, 0, 1) != 1) {
76423 + pr_err("PLL GO bit not set\n");
76424 + return -ETIMEDOUT;
76425 + }
76426 +
76427 + /* Wait till the lock bit is set in PLL status */
76428 + if (hdmi_wait_for_bit_change(pll->base,
76429 + PLLCTRL_PLL_STATUS, 1, 1, 1) != 1) {
76430 + pr_err("cannot lock PLL\n");
76431 + pr_err("CFG1 0x%x\n",
76432 + hdmi_read_reg(pll->base, PLLCTRL_CFG1));
76433 + pr_err("CFG2 0x%x\n",
76434 + hdmi_read_reg(pll->base, PLLCTRL_CFG2));
76435 + pr_err("CFG4 0x%x\n",
76436 + hdmi_read_reg(pll->base, PLLCTRL_CFG4));
76437 + return -ETIMEDOUT;
76438 + }
76439 +
76440 + pr_debug("PLL locked!\n");
76441 +
76442 + return 0;
76443 +}
76444 +
76445 +static int hdmi_pll_reset(struct hdmi_pll_data *pll)
76446 +{
76447 + /* SYSRESET controlled by power FSM */
76448 + REG_FLD_MOD(pll->base, PLLCTRL_PLL_CONTROL, pll_feat->sys_reset, 3, 3);
76449 +
76450 + /* READ 0x0 reset is in progress */
76451 + if (hdmi_wait_for_bit_change(pll->base, PLLCTRL_PLL_STATUS, 0, 0, 1)
76452 + != 1) {
76453 + pr_err("Failed to sysreset PLL\n");
76454 + return -ETIMEDOUT;
76455 + }
76456 +
76457 + return 0;
76458 +}
76459 +
76460 +int hdmi_pll_enable(struct hdmi_pll_data *pll, struct hdmi_wp_data *wp)
76461 +{
76462 + u16 r = 0;
76463 +
76464 + if (pll_feat->ext_mux_ctrl)
76465 + dss_dpll_enable_ctrl(DSS_DPLL_HDMI, true);
76466 +
76467 + r = hdmi_wp_set_pll_pwr(wp, HDMI_PLLPWRCMD_ALLOFF);
76468 + if (r)
76469 + return r;
76470 +
76471 + r = hdmi_wp_set_pll_pwr(wp, HDMI_PLLPWRCMD_BOTHON_ALLCLKS);
76472 + if (r)
76473 + return r;
76474 +
76475 + r = hdmi_pll_reset(pll);
76476 + if (r)
76477 + return r;
76478 +
76479 + r = hdmi_pll_config(pll);
76480 + if (r)
76481 + return r;
76482 +
76483 + return 0;
76484 +}
76485 +
76486 +void hdmi_pll_disable(struct hdmi_pll_data *pll, struct hdmi_wp_data *wp)
76487 +{
76488 + if (pll_feat->ext_mux_ctrl)
76489 + dss_dpll_enable_ctrl(DSS_DPLL_HDMI, false);
76490 +
76491 + hdmi_wp_set_pll_pwr(wp, HDMI_PLLPWRCMD_ALLOFF);
76492 +}
76493 +
76494 +static const struct hdmi_pll_features omap44xx_pll_feats = {
76495 + .sys_reset = false,
76496 + .bound_dcofreq = false,
76497 + .ext_mux_ctrl = false,
76498 + .fint_min = 500000,
76499 + .fint_max = 2500000,
76500 + .regm_max = 4095,
76501 + .dcofreq_low_min = 500000000,
76502 + .dcofreq_low_max = 1000000000,
76503 + .dcofreq_high_min = 1000000000,
76504 + .dcofreq_high_max = 2000000000,
76505 +};
76506 +
76507 +static const struct hdmi_pll_features omap54xx_pll_feats = {
76508 + .sys_reset = true,
76509 + .bound_dcofreq = true,
76510 + .ext_mux_ctrl = false,
76511 + .fint_min = 620000,
76512 + .fint_max = 2500000,
76513 + .regm_max = 2046,
76514 + .dcofreq_low_min = 750000000,
76515 + .dcofreq_low_max = 1500000000,
76516 + .dcofreq_high_min = 1250000000,
76517 + .dcofreq_high_max = 2500000000UL,
76518 +};
76519 +
76520 +static const struct hdmi_pll_features dra7xx_pll_feats = {
76521 + .sys_reset = true,
76522 + .bound_dcofreq = true,
76523 + .ext_mux_ctrl = true,
76524 + .fint_min = 620000,
76525 + .fint_max = 2500000,
76526 + .regm_max = 2046,
76527 + .dcofreq_low_min = 750000000,
76528 + .dcofreq_low_max = 1500000000,
76529 + .dcofreq_high_min = 1250000000,
76530 + .dcofreq_high_max = 2500000000UL,
76531 +};
76532 +
76533 +static int hdmi_pll_init_features(struct platform_device *pdev)
76534 +{
76535 + struct hdmi_pll_features *dst;
76536 + const struct hdmi_pll_features *src;
76537 +
76538 + dst = devm_kzalloc(&pdev->dev, sizeof(*dst), GFP_KERNEL);
76539 + if (!dst) {
76540 + dev_err(&pdev->dev, "Failed to allocate HDMI PHY Features\n");
76541 + return -ENOMEM;
76542 + }
76543 +
76544 + switch (omapdss_get_version()) {
76545 + case OMAPDSS_VER_OMAP4430_ES1:
76546 + case OMAPDSS_VER_OMAP4430_ES2:
76547 + case OMAPDSS_VER_OMAP4:
76548 + src = &omap44xx_pll_feats;
76549 + break;
76550 +
76551 + case OMAPDSS_VER_OMAP5:
76552 + src = &omap54xx_pll_feats;
76553 + break;
76554 + case OMAPDSS_VER_DRA7xx:
76555 + src = &dra7xx_pll_feats;
76556 + break;
76557 +
76558 + default:
76559 + return -ENODEV;
76560 + }
76561 +
76562 + memcpy(dst, src, sizeof(*dst));
76563 + pll_feat = dst;
76564 +
76565 + return 0;
76566 +}
76567 +
76568 +int hdmi_pll_init(struct platform_device *pdev, struct hdmi_pll_data *pll)
76569 +{
76570 + int r;
76571 + struct resource *res;
76572 +
76573 + r = hdmi_pll_init_features(pdev);
76574 + if (r)
76575 + return r;
76576 +
76577 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi_pllctrl");
76578 + if (!res) {
76579 + DSSERR("can't get PLL CTRL IORESOURCE_MEM HDMI\n");
76580 + return -EINVAL;
76581 + }
76582 +
76583 + pll->base = devm_request_and_ioremap(&pdev->dev, res);
76584 + if (!pll->base) {
76585 + DSSERR("can't ioremap PLL ctrl\n");
76586 + return -ENOMEM;
76587 + }
76588 +
76589 + return 0;
76590 +}
76591 --- /dev/null
76592 +++ b/drivers/video/omap2/dss/hdmi_wp.c
76593 @@ -0,0 +1,254 @@
76594 +/*
76595 + * HDMI wrapper
76596 + *
76597 + * Copyright (C) 2013 Texas Instruments Incorporated
76598 + *
76599 + * This program is free software; you can redistribute it and/or modify it
76600 + * under the terms of the GNU General Public License version 2 as published by
76601 + * the Free Software Foundation.
76602 + */
76603 +
76604 +#include <linux/kernel.h>
76605 +#include <linux/err.h>
76606 +#include <linux/io.h>
76607 +#include <linux/platform_device.h>
76608 +#include <video/omapdss.h>
76609 +
76610 +#include "dss.h"
76611 +#include "hdmi.h"
76612 +
76613 +void hdmi_wp_dump(struct hdmi_wp_data *wp, struct seq_file *s)
76614 +{
76615 +#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, hdmi_read_reg(wp->base, r))
76616 +
76617 + DUMPREG(HDMI_WP_REVISION);
76618 + DUMPREG(HDMI_WP_SYSCONFIG);
76619 + DUMPREG(HDMI_WP_IRQSTATUS_RAW);
76620 + DUMPREG(HDMI_WP_IRQSTATUS);
76621 + DUMPREG(HDMI_WP_IRQENABLE_SET);
76622 + DUMPREG(HDMI_WP_IRQENABLE_CLR);
76623 + DUMPREG(HDMI_WP_IRQWAKEEN);
76624 + DUMPREG(HDMI_WP_PWR_CTRL);
76625 + DUMPREG(HDMI_WP_DEBOUNCE);
76626 + DUMPREG(HDMI_WP_VIDEO_CFG);
76627 + DUMPREG(HDMI_WP_VIDEO_SIZE);
76628 + DUMPREG(HDMI_WP_VIDEO_TIMING_H);
76629 + DUMPREG(HDMI_WP_VIDEO_TIMING_V);
76630 + DUMPREG(HDMI_WP_CLK);
76631 + DUMPREG(HDMI_WP_AUDIO_CFG);
76632 + DUMPREG(HDMI_WP_AUDIO_CFG2);
76633 + DUMPREG(HDMI_WP_AUDIO_CTRL);
76634 + DUMPREG(HDMI_WP_AUDIO_DATA);
76635 +}
76636 +
76637 +u32 hdmi_wp_get_irqstatus(struct hdmi_wp_data *wp)
76638 +{
76639 + return hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS);
76640 +}
76641 +
76642 +void hdmi_wp_set_irqstatus(struct hdmi_wp_data *wp, u32 irqstatus)
76643 +{
76644 + hdmi_write_reg(wp->base, HDMI_WP_IRQSTATUS, irqstatus);
76645 + /* flush posted write */
76646 + hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS);
76647 +}
76648 +
76649 +void hdmi_wp_set_irqenable(struct hdmi_wp_data *wp, u32 mask)
76650 +{
76651 + hdmi_write_reg(wp->base, HDMI_WP_IRQENABLE_SET, mask);
76652 +}
76653 +
76654 +void hdmi_wp_clear_irqenable(struct hdmi_wp_data *wp, u32 mask)
76655 +{
76656 + hdmi_write_reg(wp->base, HDMI_WP_IRQENABLE_CLR, mask);
76657 +}
76658 +
76659 +/* PHY_PWR_CMD */
76660 +int hdmi_wp_set_phy_pwr(struct hdmi_wp_data *wp, enum hdmi_phy_pwr val)
76661 +{
76662 + /* Return if already the state */
76663 + if (REG_GET(wp->base, HDMI_WP_PWR_CTRL, 5, 4) == val)
76664 + return 0;
76665 +
76666 + /* Command for power control of HDMI PHY */
76667 + REG_FLD_MOD(wp->base, HDMI_WP_PWR_CTRL, val, 7, 6);
76668 +
76669 + /* Status of the power control of HDMI PHY */
76670 + if (hdmi_wait_for_bit_change(wp->base, HDMI_WP_PWR_CTRL, 5, 4, val)
76671 + != val) {
76672 + pr_err("Failed to set PHY power mode to %d\n", val);
76673 + return -ETIMEDOUT;
76674 + }
76675 +
76676 + return 0;
76677 +}
76678 +
76679 +/* PLL_PWR_CMD */
76680 +int hdmi_wp_set_pll_pwr(struct hdmi_wp_data *wp, enum hdmi_pll_pwr val)
76681 +{
76682 + /* Command for power control of HDMI PLL */
76683 + REG_FLD_MOD(wp->base, HDMI_WP_PWR_CTRL, val, 3, 2);
76684 +
76685 + /* wait till PHY_PWR_STATUS is set */
76686 + if (hdmi_wait_for_bit_change(wp->base, HDMI_WP_PWR_CTRL, 1, 0, val)
76687 + != val) {
76688 + pr_err("Failed to set PLL_PWR_STATUS\n");
76689 + return -ETIMEDOUT;
76690 + }
76691 +
76692 + return 0;
76693 +}
76694 +
76695 +int hdmi_wp_video_start(struct hdmi_wp_data *wp)
76696 +{
76697 + REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, true, 31, 31);
76698 +
76699 + return 0;
76700 +}
76701 +
76702 +void hdmi_wp_video_stop(struct hdmi_wp_data *wp)
76703 +{
76704 + REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, false, 31, 31);
76705 +}
76706 +
76707 +void hdmi_wp_video_config_format(struct hdmi_wp_data *wp,
76708 + struct hdmi_video_format *video_fmt)
76709 +{
76710 + u32 l = 0;
76711 +
76712 + REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, video_fmt->packing_mode,
76713 + 10, 8);
76714 +
76715 + l |= FLD_VAL(video_fmt->y_res, 31, 16);
76716 + l |= FLD_VAL(video_fmt->x_res, 15, 0);
76717 + hdmi_write_reg(wp->base, HDMI_WP_VIDEO_SIZE, l);
76718 +}
76719 +
76720 +void hdmi_wp_video_config_interface(struct hdmi_wp_data *wp,
76721 + struct omap_video_timings *timings)
76722 +{
76723 + u32 r;
76724 + bool vsync_pol, hsync_pol;
76725 + pr_debug("Enter hdmi_wp_video_config_interface\n");
76726 +
76727 + vsync_pol = timings->vsync_level == OMAPDSS_SIG_ACTIVE_HIGH;
76728 + hsync_pol = timings->hsync_level == OMAPDSS_SIG_ACTIVE_HIGH;
76729 +
76730 + r = hdmi_read_reg(wp->base, HDMI_WP_VIDEO_CFG);
76731 + r = FLD_MOD(r, vsync_pol, 7, 7);
76732 + r = FLD_MOD(r, hsync_pol, 6, 6);
76733 + r = FLD_MOD(r, timings->interlace, 3, 3);
76734 + r = FLD_MOD(r, 1, 1, 0); /* HDMI_TIMING_MASTER_24BIT */
76735 + hdmi_write_reg(wp->base, HDMI_WP_VIDEO_CFG, r);
76736 +}
76737 +
76738 +void hdmi_wp_video_config_timing(struct hdmi_wp_data *wp,
76739 + struct omap_video_timings *timings)
76740 +{
76741 + u32 timing_h = 0;
76742 + u32 timing_v = 0;
76743 +
76744 + pr_debug("Enter hdmi_wp_video_config_timing\n");
76745 +
76746 + timing_h |= FLD_VAL(timings->hbp, 31, 20);
76747 + timing_h |= FLD_VAL(timings->hfp, 19, 8);
76748 + timing_h |= FLD_VAL(timings->hsw, 7, 0);
76749 + hdmi_write_reg(wp->base, HDMI_WP_VIDEO_TIMING_H, timing_h);
76750 +
76751 + timing_v |= FLD_VAL(timings->vbp, 31, 20);
76752 + timing_v |= FLD_VAL(timings->vfp, 19, 8);
76753 + timing_v |= FLD_VAL(timings->vsw, 7, 0);
76754 + hdmi_write_reg(wp->base, HDMI_WP_VIDEO_TIMING_V, timing_v);
76755 +}
76756 +
76757 +void hdmi_wp_init_vid_fmt_timings(struct hdmi_video_format *video_fmt,
76758 + struct omap_video_timings *timings, struct hdmi_config *param)
76759 +{
76760 + pr_debug("Enter hdmi_wp_video_init_format\n");
76761 +
76762 + video_fmt->packing_mode = HDMI_PACK_10b_RGB_YUV444;
76763 + video_fmt->y_res = param->timings.y_res;
76764 + video_fmt->x_res = param->timings.x_res;
76765 +
76766 + timings->hbp = param->timings.hbp;
76767 + timings->hfp = param->timings.hfp;
76768 + timings->hsw = param->timings.hsw;
76769 + timings->vbp = param->timings.vbp;
76770 + timings->vfp = param->timings.vfp;
76771 + timings->vsw = param->timings.vsw;
76772 + timings->vsync_level = param->timings.vsync_level;
76773 + timings->hsync_level = param->timings.hsync_level;
76774 + timings->interlace = param->timings.interlace;
76775 +}
76776 +
76777 +#if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO) || defined(CONFIG_OMAP5_DSS_HDMI_AUDIO)
76778 +void hdmi_wp_audio_config_format(struct hdmi_wp_data *wp,
76779 + struct hdmi_audio_format *aud_fmt)
76780 +{
76781 + u32 r;
76782 +
76783 + DSSDBG("Enter hdmi_wp_audio_config_format\n");
76784 +
76785 + r = hdmi_read_reg(wp->base, HDMI_WP_AUDIO_CFG);
76786 + r = FLD_MOD(r, aud_fmt->stereo_channels, 26, 24);
76787 + r = FLD_MOD(r, aud_fmt->active_chnnls_msk, 23, 16);
76788 + r = FLD_MOD(r, aud_fmt->en_sig_blk_strt_end, 5, 5);
76789 + r = FLD_MOD(r, aud_fmt->type, 4, 4);
76790 + r = FLD_MOD(r, aud_fmt->justification, 3, 3);
76791 + r = FLD_MOD(r, aud_fmt->sample_order, 2, 2);
76792 + r = FLD_MOD(r, aud_fmt->samples_per_word, 1, 1);
76793 + r = FLD_MOD(r, aud_fmt->sample_size, 0, 0);
76794 + hdmi_write_reg(wp->base, HDMI_WP_AUDIO_CFG, r);
76795 +}
76796 +
76797 +void hdmi_wp_audio_config_dma(struct hdmi_wp_data *wp,
76798 + struct hdmi_audio_dma *aud_dma)
76799 +{
76800 + u32 r;
76801 +
76802 + DSSDBG("Enter hdmi_wp_audio_config_dma\n");
76803 +
76804 + r = hdmi_read_reg(wp->base, HDMI_WP_AUDIO_CFG2);
76805 + r = FLD_MOD(r, aud_dma->transfer_size, 15, 8);
76806 + r = FLD_MOD(r, aud_dma->block_size, 7, 0);
76807 + hdmi_write_reg(wp->base, HDMI_WP_AUDIO_CFG2, r);
76808 +
76809 + r = hdmi_read_reg(wp->base, HDMI_WP_AUDIO_CTRL);
76810 + r = FLD_MOD(r, aud_dma->mode, 9, 9);
76811 + r = FLD_MOD(r, aud_dma->fifo_threshold, 8, 0);
76812 + hdmi_write_reg(wp->base, HDMI_WP_AUDIO_CTRL, r);
76813 +}
76814 +
76815 +int hdmi_wp_audio_enable(struct hdmi_wp_data *wp, bool enable)
76816 +{
76817 + REG_FLD_MOD(wp->base, HDMI_WP_AUDIO_CTRL, enable, 31, 31);
76818 +
76819 + return 0;
76820 +}
76821 +
76822 +int hdmi_wp_audio_core_req_enable(struct hdmi_wp_data *wp, bool enable)
76823 +{
76824 + REG_FLD_MOD(wp->base, HDMI_WP_AUDIO_CTRL, enable, 30, 30);
76825 +
76826 + return 0;
76827 +}
76828 +#endif
76829 +
76830 +int hdmi_wp_init(struct platform_device *pdev, struct hdmi_wp_data *wp)
76831 +{
76832 + struct resource *res;
76833 +
76834 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi_wp");
76835 + if (!res) {
76836 + DSSERR("can't get WP IORESOURCE_MEM HDMI\n");
76837 + return -EINVAL;
76838 + }
76839 +
76840 + wp->base = devm_request_and_ioremap(&pdev->dev, res);
76841 + if (!wp->base) {
76842 + DSSERR("can't ioremap HDMI wrapper\n");
76843 + return -ENOMEM;
76844 + }
76845 +
76846 + return 0;
76847 +}
76848 --- a/drivers/video/omap2/dss/Kconfig
76849 +++ b/drivers/video/omap2/dss/Kconfig
76850 @@ -40,6 +40,12 @@ config OMAP2_DSS_DPI
76851 help
76852 DPI Interface. This is the Parallel Display Interface.
76853
76854 +config OMAP2_DSS_DRA7XX_DPI
76855 + bool "DRA75X DPI support"
76856 + default y
76857 + help
76858 + Vayu DPI Interface. This is the Parallel Display Interface.
76859 +
76860 config OMAP2_DSS_RFBI
76861 bool "RFBI support"
76862 depends on BROKEN
76863 @@ -69,6 +75,18 @@ config OMAP4_DSS_HDMI
76864 config OMAP4_DSS_HDMI_AUDIO
76865 bool
76866
76867 +config OMAP5_DSS_HDMI
76868 + bool "OMAP5 HDMI support"
76869 + default y
76870 + help
76871 + HDMI Interface for OMAP5 and similar cores. This adds the High
76872 + Definition Multimedia Interface. See http://www.hdmi.org/ for HDMI
76873 + specification.
76874 +
76875 +config OMAP5_DSS_HDMI_AUDIO
76876 + depends on OMAP5_DSS_HDMI
76877 + bool
76878 +
76879 config OMAP2_DSS_SDI
76880 bool "SDI support"
76881 default n
76882 --- a/drivers/video/omap2/dss/Makefile
76883 +++ b/drivers/video/omap2/dss/Makefile
76884 @@ -1,14 +1,18 @@
76885 obj-$(CONFIG_OMAP2_DSS) += omapdss.o
76886 # Core DSS files
76887 -omapdss-y := core.o dss.o dss_features.o dispc.o dispc_coefs.o display.o \
76888 - output.o
76889 +omapdss-y := core.o dss.o dss_dpll.o dss_features.o dispc.o dispc_coefs.o \
76890 + display.o output.o
76891 # DSS compat layer files
76892 omapdss-y += manager.o manager-sysfs.o overlay.o overlay-sysfs.o apply.o \
76893 dispc-compat.o display-sysfs.o
76894 omapdss-$(CONFIG_OMAP2_DSS_DPI) += dpi.o
76895 +omapdss-$(CONFIG_OMAP2_DSS_DRA7XX_DPI) += dra7xx_dpi.o
76896 omapdss-$(CONFIG_OMAP2_DSS_RFBI) += rfbi.o
76897 omapdss-$(CONFIG_OMAP2_DSS_VENC) += venc.o
76898 omapdss-$(CONFIG_OMAP2_DSS_SDI) += sdi.o
76899 omapdss-$(CONFIG_OMAP2_DSS_DSI) += dsi.o
76900 -omapdss-$(CONFIG_OMAP4_DSS_HDMI) += hdmi.o ti_hdmi_4xxx_ip.o
76901 +omapdss-$(CONFIG_OMAP4_DSS_HDMI) += hdmi4.o hdmi_common.o hdmi_wp.o hdmi_pll.o \
76902 + hdmi_phy.o hdmi4_core.o
76903 +omapdss-$(CONFIG_OMAP5_DSS_HDMI) += hdmi5.o hdmi_common.o hdmi_wp.o hdmi_pll.o \
76904 + hdmi_phy.o hdmi5_core.o
76905 ccflags-$(CONFIG_OMAP2_DSS_DEBUG) += -DDEBUG
76906 --- a/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c
76907 +++ /dev/null
76908 @@ -1,1427 +0,0 @@
76909 -/*
76910 - * ti_hdmi_4xxx_ip.c
76911 - *
76912 - * HDMI TI81xx, TI38xx, TI OMAP4 etc IP driver Library
76913 - * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
76914 - * Authors: Yong Zhi
76915 - * Mythri pk <mythripk@ti.com>
76916 - *
76917 - * This program is free software; you can redistribute it and/or modify it
76918 - * under the terms of the GNU General Public License version 2 as published by
76919 - * the Free Software Foundation.
76920 - *
76921 - * This program is distributed in the hope that it will be useful, but WITHOUT
76922 - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
76923 - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
76924 - * more details.
76925 - *
76926 - * You should have received a copy of the GNU General Public License along with
76927 - * this program. If not, see <http://www.gnu.org/licenses/>.
76928 - */
76929 -
76930 -#include <linux/kernel.h>
76931 -#include <linux/module.h>
76932 -#include <linux/err.h>
76933 -#include <linux/io.h>
76934 -#include <linux/interrupt.h>
76935 -#include <linux/mutex.h>
76936 -#include <linux/delay.h>
76937 -#include <linux/string.h>
76938 -#include <linux/seq_file.h>
76939 -#if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO)
76940 -#include <sound/asound.h>
76941 -#include <sound/asoundef.h>
76942 -#endif
76943 -
76944 -#include "ti_hdmi_4xxx_ip.h"
76945 -#include "dss.h"
76946 -#include "dss_features.h"
76947 -
76948 -#define HDMI_IRQ_LINK_CONNECT (1 << 25)
76949 -#define HDMI_IRQ_LINK_DISCONNECT (1 << 26)
76950 -
76951 -static inline void hdmi_write_reg(void __iomem *base_addr,
76952 - const u16 idx, u32 val)
76953 -{
76954 - __raw_writel(val, base_addr + idx);
76955 -}
76956 -
76957 -static inline u32 hdmi_read_reg(void __iomem *base_addr,
76958 - const u16 idx)
76959 -{
76960 - return __raw_readl(base_addr + idx);
76961 -}
76962 -
76963 -static inline void __iomem *hdmi_wp_base(struct hdmi_ip_data *ip_data)
76964 -{
76965 - return ip_data->base_wp;
76966 -}
76967 -
76968 -static inline void __iomem *hdmi_phy_base(struct hdmi_ip_data *ip_data)
76969 -{
76970 - return ip_data->base_wp + ip_data->phy_offset;
76971 -}
76972 -
76973 -static inline void __iomem *hdmi_pll_base(struct hdmi_ip_data *ip_data)
76974 -{
76975 - return ip_data->base_wp + ip_data->pll_offset;
76976 -}
76977 -
76978 -static inline void __iomem *hdmi_av_base(struct hdmi_ip_data *ip_data)
76979 -{
76980 - return ip_data->base_wp + ip_data->core_av_offset;
76981 -}
76982 -
76983 -static inline void __iomem *hdmi_core_sys_base(struct hdmi_ip_data *ip_data)
76984 -{
76985 - return ip_data->base_wp + ip_data->core_sys_offset;
76986 -}
76987 -
76988 -static inline int hdmi_wait_for_bit_change(void __iomem *base_addr,
76989 - const u16 idx,
76990 - int b2, int b1, u32 val)
76991 -{
76992 - u32 t = 0;
76993 - while (val != REG_GET(base_addr, idx, b2, b1)) {
76994 - udelay(1);
76995 - if (t++ > 10000)
76996 - return !val;
76997 - }
76998 - return val;
76999 -}
77000 -
77001 -static int hdmi_pll_init(struct hdmi_ip_data *ip_data)
77002 -{
77003 - u32 r;
77004 - void __iomem *pll_base = hdmi_pll_base(ip_data);
77005 - struct hdmi_pll_info *fmt = &ip_data->pll_data;
77006 -
77007 - /* PLL start always use manual mode */
77008 - REG_FLD_MOD(pll_base, PLLCTRL_PLL_CONTROL, 0x0, 0, 0);
77009 -
77010 - r = hdmi_read_reg(pll_base, PLLCTRL_CFG1);
77011 - r = FLD_MOD(r, fmt->regm, 20, 9); /* CFG1_PLL_REGM */
77012 - r = FLD_MOD(r, fmt->regn - 1, 8, 1); /* CFG1_PLL_REGN */
77013 -
77014 - hdmi_write_reg(pll_base, PLLCTRL_CFG1, r);
77015 -
77016 - r = hdmi_read_reg(pll_base, PLLCTRL_CFG2);
77017 -
77018 - r = FLD_MOD(r, 0x0, 12, 12); /* PLL_HIGHFREQ divide by 2 */
77019 - r = FLD_MOD(r, 0x1, 13, 13); /* PLL_REFEN */
77020 - r = FLD_MOD(r, 0x0, 14, 14); /* PHY_CLKINEN de-assert during locking */
77021 - r = FLD_MOD(r, fmt->refsel, 22, 21); /* REFSEL */
77022 -
77023 - if (fmt->dcofreq) {
77024 - /* divider programming for frequency beyond 1000Mhz */
77025 - REG_FLD_MOD(pll_base, PLLCTRL_CFG3, fmt->regsd, 17, 10);
77026 - r = FLD_MOD(r, 0x4, 3, 1); /* 1000MHz and 2000MHz */
77027 - } else {
77028 - r = FLD_MOD(r, 0x2, 3, 1); /* 500MHz and 1000MHz */
77029 - }
77030 -
77031 - hdmi_write_reg(pll_base, PLLCTRL_CFG2, r);
77032 -
77033 - r = hdmi_read_reg(pll_base, PLLCTRL_CFG4);
77034 - r = FLD_MOD(r, fmt->regm2, 24, 18);
77035 - r = FLD_MOD(r, fmt->regmf, 17, 0);
77036 -
77037 - hdmi_write_reg(pll_base, PLLCTRL_CFG4, r);
77038 -
77039 - /* go now */
77040 - REG_FLD_MOD(pll_base, PLLCTRL_PLL_GO, 0x1, 0, 0);
77041 -
77042 - /* wait for bit change */
77043 - if (hdmi_wait_for_bit_change(pll_base, PLLCTRL_PLL_GO,
77044 - 0, 0, 1) != 1) {
77045 - pr_err("PLL GO bit not set\n");
77046 - return -ETIMEDOUT;
77047 - }
77048 -
77049 - /* Wait till the lock bit is set in PLL status */
77050 - if (hdmi_wait_for_bit_change(pll_base,
77051 - PLLCTRL_PLL_STATUS, 1, 1, 1) != 1) {
77052 - pr_err("cannot lock PLL\n");
77053 - pr_err("CFG1 0x%x\n",
77054 - hdmi_read_reg(pll_base, PLLCTRL_CFG1));
77055 - pr_err("CFG2 0x%x\n",
77056 - hdmi_read_reg(pll_base, PLLCTRL_CFG2));
77057 - pr_err("CFG4 0x%x\n",
77058 - hdmi_read_reg(pll_base, PLLCTRL_CFG4));
77059 - return -ETIMEDOUT;
77060 - }
77061 -
77062 - pr_debug("PLL locked!\n");
77063 -
77064 - return 0;
77065 -}
77066 -
77067 -/* PHY_PWR_CMD */
77068 -static int hdmi_set_phy_pwr(struct hdmi_ip_data *ip_data, enum hdmi_phy_pwr val)
77069 -{
77070 - /* Return if already the state */
77071 - if (REG_GET(hdmi_wp_base(ip_data), HDMI_WP_PWR_CTRL, 5, 4) == val)
77072 - return 0;
77073 -
77074 - /* Command for power control of HDMI PHY */
77075 - REG_FLD_MOD(hdmi_wp_base(ip_data), HDMI_WP_PWR_CTRL, val, 7, 6);
77076 -
77077 - /* Status of the power control of HDMI PHY */
77078 - if (hdmi_wait_for_bit_change(hdmi_wp_base(ip_data),
77079 - HDMI_WP_PWR_CTRL, 5, 4, val) != val) {
77080 - pr_err("Failed to set PHY power mode to %d\n", val);
77081 - return -ETIMEDOUT;
77082 - }
77083 -
77084 - return 0;
77085 -}
77086 -
77087 -/* PLL_PWR_CMD */
77088 -static int hdmi_set_pll_pwr(struct hdmi_ip_data *ip_data, enum hdmi_pll_pwr val)
77089 -{
77090 - /* Command for power control of HDMI PLL */
77091 - REG_FLD_MOD(hdmi_wp_base(ip_data), HDMI_WP_PWR_CTRL, val, 3, 2);
77092 -
77093 - /* wait till PHY_PWR_STATUS is set */
77094 - if (hdmi_wait_for_bit_change(hdmi_wp_base(ip_data), HDMI_WP_PWR_CTRL,
77095 - 1, 0, val) != val) {
77096 - pr_err("Failed to set PLL_PWR_STATUS\n");
77097 - return -ETIMEDOUT;
77098 - }
77099 -
77100 - return 0;
77101 -}
77102 -
77103 -static int hdmi_pll_reset(struct hdmi_ip_data *ip_data)
77104 -{
77105 - /* SYSRESET controlled by power FSM */
77106 - REG_FLD_MOD(hdmi_pll_base(ip_data), PLLCTRL_PLL_CONTROL, 0x0, 3, 3);
77107 -
77108 - /* READ 0x0 reset is in progress */
77109 - if (hdmi_wait_for_bit_change(hdmi_pll_base(ip_data),
77110 - PLLCTRL_PLL_STATUS, 0, 0, 1) != 1) {
77111 - pr_err("Failed to sysreset PLL\n");
77112 - return -ETIMEDOUT;
77113 - }
77114 -
77115 - return 0;
77116 -}
77117 -
77118 -int ti_hdmi_4xxx_pll_enable(struct hdmi_ip_data *ip_data)
77119 -{
77120 - u16 r = 0;
77121 -
77122 - r = hdmi_set_pll_pwr(ip_data, HDMI_PLLPWRCMD_ALLOFF);
77123 - if (r)
77124 - return r;
77125 -
77126 - r = hdmi_set_pll_pwr(ip_data, HDMI_PLLPWRCMD_BOTHON_ALLCLKS);
77127 - if (r)
77128 - return r;
77129 -
77130 - r = hdmi_pll_reset(ip_data);
77131 - if (r)
77132 - return r;
77133 -
77134 - r = hdmi_pll_init(ip_data);
77135 - if (r)
77136 - return r;
77137 -
77138 - return 0;
77139 -}
77140 -
77141 -void ti_hdmi_4xxx_pll_disable(struct hdmi_ip_data *ip_data)
77142 -{
77143 - hdmi_set_pll_pwr(ip_data, HDMI_PLLPWRCMD_ALLOFF);
77144 -}
77145 -
77146 -static irqreturn_t hdmi_irq_handler(int irq, void *data)
77147 -{
77148 - struct hdmi_ip_data *ip_data = data;
77149 - void __iomem *wp_base = hdmi_wp_base(ip_data);
77150 - u32 irqstatus;
77151 -
77152 - irqstatus = hdmi_read_reg(wp_base, HDMI_WP_IRQSTATUS);
77153 - hdmi_write_reg(wp_base, HDMI_WP_IRQSTATUS, irqstatus);
77154 - /* flush posted write */
77155 - hdmi_read_reg(wp_base, HDMI_WP_IRQSTATUS);
77156 -
77157 - if ((irqstatus & HDMI_IRQ_LINK_CONNECT) &&
77158 - irqstatus & HDMI_IRQ_LINK_DISCONNECT) {
77159 - /*
77160 - * If we get both connect and disconnect interrupts at the same
77161 - * time, turn off the PHY, clear interrupts, and restart, which
77162 - * raises connect interrupt if a cable is connected, or nothing
77163 - * if cable is not connected.
77164 - */
77165 - hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_OFF);
77166 -
77167 - hdmi_write_reg(wp_base, HDMI_WP_IRQSTATUS,
77168 - HDMI_IRQ_LINK_CONNECT | HDMI_IRQ_LINK_DISCONNECT);
77169 - /* flush posted write */
77170 - hdmi_read_reg(wp_base, HDMI_WP_IRQSTATUS);
77171 -
77172 - hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_LDOON);
77173 - } else if (irqstatus & HDMI_IRQ_LINK_CONNECT) {
77174 - hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_TXON);
77175 - } else if (irqstatus & HDMI_IRQ_LINK_DISCONNECT) {
77176 - hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_LDOON);
77177 - }
77178 -
77179 - return IRQ_HANDLED;
77180 -}
77181 -
77182 -int ti_hdmi_4xxx_phy_enable(struct hdmi_ip_data *ip_data)
77183 -{
77184 - u16 r = 0;
77185 - void __iomem *phy_base = hdmi_phy_base(ip_data);
77186 -
77187 - hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_IRQENABLE_CLR,
77188 - 0xffffffff);
77189 -
77190 - hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_IRQSTATUS,
77191 - HDMI_IRQ_LINK_CONNECT | HDMI_IRQ_LINK_DISCONNECT);
77192 -
77193 - r = hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_LDOON);
77194 - if (r)
77195 - return r;
77196 -
77197 - /*
77198 - * Read address 0 in order to get the SCP reset done completed
77199 - * Dummy access performed to make sure reset is done
77200 - */
77201 - hdmi_read_reg(phy_base, HDMI_TXPHY_TX_CTRL);
77202 -
77203 - /*
77204 - * Write to phy address 0 to configure the clock
77205 - * use HFBITCLK write HDMI_TXPHY_TX_CONTROL_FREQOUT field
77206 - */
77207 - REG_FLD_MOD(phy_base, HDMI_TXPHY_TX_CTRL, 0x1, 31, 30);
77208 -
77209 - /* Write to phy address 1 to start HDMI line (TXVALID and TMDSCLKEN) */
77210 - hdmi_write_reg(phy_base, HDMI_TXPHY_DIGITAL_CTRL, 0xF0000000);
77211 -
77212 - /* Setup max LDO voltage */
77213 - REG_FLD_MOD(phy_base, HDMI_TXPHY_POWER_CTRL, 0xB, 3, 0);
77214 -
77215 - /* Write to phy address 3 to change the polarity control */
77216 - REG_FLD_MOD(phy_base, HDMI_TXPHY_PAD_CFG_CTRL, 0x1, 27, 27);
77217 -
77218 - r = request_threaded_irq(ip_data->irq, NULL, hdmi_irq_handler,
77219 - IRQF_ONESHOT, "OMAP HDMI", ip_data);
77220 - if (r) {
77221 - DSSERR("HDMI IRQ request failed\n");
77222 - hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_OFF);
77223 - return r;
77224 - }
77225 -
77226 - hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_IRQENABLE_SET,
77227 - HDMI_IRQ_LINK_CONNECT | HDMI_IRQ_LINK_DISCONNECT);
77228 -
77229 - return 0;
77230 -}
77231 -
77232 -void ti_hdmi_4xxx_phy_disable(struct hdmi_ip_data *ip_data)
77233 -{
77234 - free_irq(ip_data->irq, ip_data);
77235 -
77236 - hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_OFF);
77237 -}
77238 -
77239 -static int hdmi_core_ddc_init(struct hdmi_ip_data *ip_data)
77240 -{
77241 - void __iomem *base = hdmi_core_sys_base(ip_data);
77242 -
77243 - /* Turn on CLK for DDC */
77244 - REG_FLD_MOD(base, HDMI_CORE_AV_DPD, 0x7, 2, 0);
77245 -
77246 - /* IN_PROG */
77247 - if (REG_GET(base, HDMI_CORE_DDC_STATUS, 4, 4) == 1) {
77248 - /* Abort transaction */
77249 - REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0xf, 3, 0);
77250 - /* IN_PROG */
77251 - if (hdmi_wait_for_bit_change(base, HDMI_CORE_DDC_STATUS,
77252 - 4, 4, 0) != 0) {
77253 - DSSERR("Timeout aborting DDC transaction\n");
77254 - return -ETIMEDOUT;
77255 - }
77256 - }
77257 -
77258 - /* Clk SCL Devices */
77259 - REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0xA, 3, 0);
77260 -
77261 - /* HDMI_CORE_DDC_STATUS_IN_PROG */
77262 - if (hdmi_wait_for_bit_change(base, HDMI_CORE_DDC_STATUS,
77263 - 4, 4, 0) != 0) {
77264 - DSSERR("Timeout starting SCL clock\n");
77265 - return -ETIMEDOUT;
77266 - }
77267 -
77268 - /* Clear FIFO */
77269 - REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0x9, 3, 0);
77270 -
77271 - /* HDMI_CORE_DDC_STATUS_IN_PROG */
77272 - if (hdmi_wait_for_bit_change(base, HDMI_CORE_DDC_STATUS,
77273 - 4, 4, 0) != 0) {
77274 - DSSERR("Timeout clearing DDC fifo\n");
77275 - return -ETIMEDOUT;
77276 - }
77277 -
77278 - return 0;
77279 -}
77280 -
77281 -static int hdmi_core_ddc_edid(struct hdmi_ip_data *ip_data,
77282 - u8 *pedid, int ext)
77283 -{
77284 - void __iomem *base = hdmi_core_sys_base(ip_data);
77285 - u32 i;
77286 - char checksum;
77287 - u32 offset = 0;
77288 -
77289 - /* HDMI_CORE_DDC_STATUS_IN_PROG */
77290 - if (hdmi_wait_for_bit_change(base, HDMI_CORE_DDC_STATUS,
77291 - 4, 4, 0) != 0) {
77292 - DSSERR("Timeout waiting DDC to be ready\n");
77293 - return -ETIMEDOUT;
77294 - }
77295 -
77296 - if (ext % 2 != 0)
77297 - offset = 0x80;
77298 -
77299 - /* Load Segment Address Register */
77300 - REG_FLD_MOD(base, HDMI_CORE_DDC_SEGM, ext / 2, 7, 0);
77301 -
77302 - /* Load Slave Address Register */
77303 - REG_FLD_MOD(base, HDMI_CORE_DDC_ADDR, 0xA0 >> 1, 7, 1);
77304 -
77305 - /* Load Offset Address Register */
77306 - REG_FLD_MOD(base, HDMI_CORE_DDC_OFFSET, offset, 7, 0);
77307 -
77308 - /* Load Byte Count */
77309 - REG_FLD_MOD(base, HDMI_CORE_DDC_COUNT1, 0x80, 7, 0);
77310 - REG_FLD_MOD(base, HDMI_CORE_DDC_COUNT2, 0x0, 1, 0);
77311 -
77312 - /* Set DDC_CMD */
77313 - if (ext)
77314 - REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0x4, 3, 0);
77315 - else
77316 - REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0x2, 3, 0);
77317 -
77318 - /* HDMI_CORE_DDC_STATUS_BUS_LOW */
77319 - if (REG_GET(base, HDMI_CORE_DDC_STATUS, 6, 6) == 1) {
77320 - pr_err("I2C Bus Low?\n");
77321 - return -EIO;
77322 - }
77323 - /* HDMI_CORE_DDC_STATUS_NO_ACK */
77324 - if (REG_GET(base, HDMI_CORE_DDC_STATUS, 5, 5) == 1) {
77325 - pr_err("I2C No Ack\n");
77326 - return -EIO;
77327 - }
77328 -
77329 - for (i = 0; i < 0x80; ++i) {
77330 - int t;
77331 -
77332 - /* IN_PROG */
77333 - if (REG_GET(base, HDMI_CORE_DDC_STATUS, 4, 4) == 0) {
77334 - DSSERR("operation stopped when reading edid\n");
77335 - return -EIO;
77336 - }
77337 -
77338 - t = 0;
77339 - /* FIFO_EMPTY */
77340 - while (REG_GET(base, HDMI_CORE_DDC_STATUS, 2, 2) == 1) {
77341 - if (t++ > 10000) {
77342 - DSSERR("timeout reading edid\n");
77343 - return -ETIMEDOUT;
77344 - }
77345 - udelay(1);
77346 - }
77347 -
77348 - pedid[i] = REG_GET(base, HDMI_CORE_DDC_DATA, 7, 0);
77349 - }
77350 -
77351 - checksum = 0;
77352 - for (i = 0; i < 0x80; ++i)
77353 - checksum += pedid[i];
77354 -
77355 - if (checksum != 0) {
77356 - pr_err("E-EDID checksum failed!!\n");
77357 - return -EIO;
77358 - }
77359 -
77360 - return 0;
77361 -}
77362 -
77363 -int ti_hdmi_4xxx_read_edid(struct hdmi_ip_data *ip_data,
77364 - u8 *edid, int len)
77365 -{
77366 - int r, l;
77367 -
77368 - if (len < 128)
77369 - return -EINVAL;
77370 -
77371 - r = hdmi_core_ddc_init(ip_data);
77372 - if (r)
77373 - return r;
77374 -
77375 - r = hdmi_core_ddc_edid(ip_data, edid, 0);
77376 - if (r)
77377 - return r;
77378 -
77379 - l = 128;
77380 -
77381 - if (len >= 128 * 2 && edid[0x7e] > 0) {
77382 - r = hdmi_core_ddc_edid(ip_data, edid + 0x80, 1);
77383 - if (r)
77384 - return r;
77385 - l += 128;
77386 - }
77387 -
77388 - return l;
77389 -}
77390 -
77391 -static void hdmi_core_init(struct hdmi_core_video_config *video_cfg,
77392 - struct hdmi_core_infoframe_avi *avi_cfg,
77393 - struct hdmi_core_packet_enable_repeat *repeat_cfg)
77394 -{
77395 - pr_debug("Enter hdmi_core_init\n");
77396 -
77397 - /* video core */
77398 - video_cfg->ip_bus_width = HDMI_INPUT_8BIT;
77399 - video_cfg->op_dither_truc = HDMI_OUTPUTTRUNCATION_8BIT;
77400 - video_cfg->deep_color_pkt = HDMI_DEEPCOLORPACKECTDISABLE;
77401 - video_cfg->pkt_mode = HDMI_PACKETMODERESERVEDVALUE;
77402 - video_cfg->hdmi_dvi = HDMI_DVI;
77403 - video_cfg->tclk_sel_clkmult = HDMI_FPLL10IDCK;
77404 -
77405 - /* info frame */
77406 - avi_cfg->db1_format = 0;
77407 - avi_cfg->db1_active_info = 0;
77408 - avi_cfg->db1_bar_info_dv = 0;
77409 - avi_cfg->db1_scan_info = 0;
77410 - avi_cfg->db2_colorimetry = 0;
77411 - avi_cfg->db2_aspect_ratio = 0;
77412 - avi_cfg->db2_active_fmt_ar = 0;
77413 - avi_cfg->db3_itc = 0;
77414 - avi_cfg->db3_ec = 0;
77415 - avi_cfg->db3_q_range = 0;
77416 - avi_cfg->db3_nup_scaling = 0;
77417 - avi_cfg->db4_videocode = 0;
77418 - avi_cfg->db5_pixel_repeat = 0;
77419 - avi_cfg->db6_7_line_eoftop = 0 ;
77420 - avi_cfg->db8_9_line_sofbottom = 0;
77421 - avi_cfg->db10_11_pixel_eofleft = 0;
77422 - avi_cfg->db12_13_pixel_sofright = 0;
77423 -
77424 - /* packet enable and repeat */
77425 - repeat_cfg->audio_pkt = 0;
77426 - repeat_cfg->audio_pkt_repeat = 0;
77427 - repeat_cfg->avi_infoframe = 0;
77428 - repeat_cfg->avi_infoframe_repeat = 0;
77429 - repeat_cfg->gen_cntrl_pkt = 0;
77430 - repeat_cfg->gen_cntrl_pkt_repeat = 0;
77431 - repeat_cfg->generic_pkt = 0;
77432 - repeat_cfg->generic_pkt_repeat = 0;
77433 -}
77434 -
77435 -static void hdmi_core_powerdown_disable(struct hdmi_ip_data *ip_data)
77436 -{
77437 - pr_debug("Enter hdmi_core_powerdown_disable\n");
77438 - REG_FLD_MOD(hdmi_core_sys_base(ip_data), HDMI_CORE_CTRL1, 0x0, 0, 0);
77439 -}
77440 -
77441 -static void hdmi_core_swreset_release(struct hdmi_ip_data *ip_data)
77442 -{
77443 - pr_debug("Enter hdmi_core_swreset_release\n");
77444 - REG_FLD_MOD(hdmi_core_sys_base(ip_data), HDMI_CORE_SYS_SRST, 0x0, 0, 0);
77445 -}
77446 -
77447 -static void hdmi_core_swreset_assert(struct hdmi_ip_data *ip_data)
77448 -{
77449 - pr_debug("Enter hdmi_core_swreset_assert\n");
77450 - REG_FLD_MOD(hdmi_core_sys_base(ip_data), HDMI_CORE_SYS_SRST, 0x1, 0, 0);
77451 -}
77452 -
77453 -/* HDMI_CORE_VIDEO_CONFIG */
77454 -static void hdmi_core_video_config(struct hdmi_ip_data *ip_data,
77455 - struct hdmi_core_video_config *cfg)
77456 -{
77457 - u32 r = 0;
77458 - void __iomem *core_sys_base = hdmi_core_sys_base(ip_data);
77459 -
77460 - /* sys_ctrl1 default configuration not tunable */
77461 - r = hdmi_read_reg(core_sys_base, HDMI_CORE_CTRL1);
77462 - r = FLD_MOD(r, HDMI_CORE_CTRL1_VEN_FOLLOWVSYNC, 5, 5);
77463 - r = FLD_MOD(r, HDMI_CORE_CTRL1_HEN_FOLLOWHSYNC, 4, 4);
77464 - r = FLD_MOD(r, HDMI_CORE_CTRL1_BSEL_24BITBUS, 2, 2);
77465 - r = FLD_MOD(r, HDMI_CORE_CTRL1_EDGE_RISINGEDGE, 1, 1);
77466 - hdmi_write_reg(core_sys_base, HDMI_CORE_CTRL1, r);
77467 -
77468 - REG_FLD_MOD(core_sys_base,
77469 - HDMI_CORE_SYS_VID_ACEN, cfg->ip_bus_width, 7, 6);
77470 -
77471 - /* Vid_Mode */
77472 - r = hdmi_read_reg(core_sys_base, HDMI_CORE_SYS_VID_MODE);
77473 -
77474 - /* dither truncation configuration */
77475 - if (cfg->op_dither_truc > HDMI_OUTPUTTRUNCATION_12BIT) {
77476 - r = FLD_MOD(r, cfg->op_dither_truc - 3, 7, 6);
77477 - r = FLD_MOD(r, 1, 5, 5);
77478 - } else {
77479 - r = FLD_MOD(r, cfg->op_dither_truc, 7, 6);
77480 - r = FLD_MOD(r, 0, 5, 5);
77481 - }
77482 - hdmi_write_reg(core_sys_base, HDMI_CORE_SYS_VID_MODE, r);
77483 -
77484 - /* HDMI_Ctrl */
77485 - r = hdmi_read_reg(hdmi_av_base(ip_data), HDMI_CORE_AV_HDMI_CTRL);
77486 - r = FLD_MOD(r, cfg->deep_color_pkt, 6, 6);
77487 - r = FLD_MOD(r, cfg->pkt_mode, 5, 3);
77488 - r = FLD_MOD(r, cfg->hdmi_dvi, 0, 0);
77489 - hdmi_write_reg(hdmi_av_base(ip_data), HDMI_CORE_AV_HDMI_CTRL, r);
77490 -
77491 - /* TMDS_CTRL */
77492 - REG_FLD_MOD(core_sys_base,
77493 - HDMI_CORE_SYS_TMDS_CTRL, cfg->tclk_sel_clkmult, 6, 5);
77494 -}
77495 -
77496 -static void hdmi_core_aux_infoframe_avi_config(struct hdmi_ip_data *ip_data)
77497 -{
77498 - u32 val;
77499 - char sum = 0, checksum = 0;
77500 - void __iomem *av_base = hdmi_av_base(ip_data);
77501 - struct hdmi_core_infoframe_avi info_avi = ip_data->avi_cfg;
77502 -
77503 - sum += 0x82 + 0x002 + 0x00D;
77504 - hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_TYPE, 0x082);
77505 - hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_VERS, 0x002);
77506 - hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_LEN, 0x00D);
77507 -
77508 - val = (info_avi.db1_format << 5) |
77509 - (info_avi.db1_active_info << 4) |
77510 - (info_avi.db1_bar_info_dv << 2) |
77511 - (info_avi.db1_scan_info);
77512 - hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(0), val);
77513 - sum += val;
77514 -
77515 - val = (info_avi.db2_colorimetry << 6) |
77516 - (info_avi.db2_aspect_ratio << 4) |
77517 - (info_avi.db2_active_fmt_ar);
77518 - hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(1), val);
77519 - sum += val;
77520 -
77521 - val = (info_avi.db3_itc << 7) |
77522 - (info_avi.db3_ec << 4) |
77523 - (info_avi.db3_q_range << 2) |
77524 - (info_avi.db3_nup_scaling);
77525 - hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(2), val);
77526 - sum += val;
77527 -
77528 - hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(3),
77529 - info_avi.db4_videocode);
77530 - sum += info_avi.db4_videocode;
77531 -
77532 - val = info_avi.db5_pixel_repeat;
77533 - hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(4), val);
77534 - sum += val;
77535 -
77536 - val = info_avi.db6_7_line_eoftop & 0x00FF;
77537 - hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(5), val);
77538 - sum += val;
77539 -
77540 - val = ((info_avi.db6_7_line_eoftop >> 8) & 0x00FF);
77541 - hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(6), val);
77542 - sum += val;
77543 -
77544 - val = info_avi.db8_9_line_sofbottom & 0x00FF;
77545 - hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(7), val);
77546 - sum += val;
77547 -
77548 - val = ((info_avi.db8_9_line_sofbottom >> 8) & 0x00FF);
77549 - hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(8), val);
77550 - sum += val;
77551 -
77552 - val = info_avi.db10_11_pixel_eofleft & 0x00FF;
77553 - hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(9), val);
77554 - sum += val;
77555 -
77556 - val = ((info_avi.db10_11_pixel_eofleft >> 8) & 0x00FF);
77557 - hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(10), val);
77558 - sum += val;
77559 -
77560 - val = info_avi.db12_13_pixel_sofright & 0x00FF;
77561 - hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(11), val);
77562 - sum += val;
77563 -
77564 - val = ((info_avi.db12_13_pixel_sofright >> 8) & 0x00FF);
77565 - hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(12), val);
77566 - sum += val;
77567 -
77568 - checksum = 0x100 - sum;
77569 - hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_CHSUM, checksum);
77570 -}
77571 -
77572 -static void hdmi_core_av_packet_config(struct hdmi_ip_data *ip_data,
77573 - struct hdmi_core_packet_enable_repeat repeat_cfg)
77574 -{
77575 - /* enable/repeat the infoframe */
77576 - hdmi_write_reg(hdmi_av_base(ip_data), HDMI_CORE_AV_PB_CTRL1,
77577 - (repeat_cfg.audio_pkt << 5) |
77578 - (repeat_cfg.audio_pkt_repeat << 4) |
77579 - (repeat_cfg.avi_infoframe << 1) |
77580 - (repeat_cfg.avi_infoframe_repeat));
77581 -
77582 - /* enable/repeat the packet */
77583 - hdmi_write_reg(hdmi_av_base(ip_data), HDMI_CORE_AV_PB_CTRL2,
77584 - (repeat_cfg.gen_cntrl_pkt << 3) |
77585 - (repeat_cfg.gen_cntrl_pkt_repeat << 2) |
77586 - (repeat_cfg.generic_pkt << 1) |
77587 - (repeat_cfg.generic_pkt_repeat));
77588 -}
77589 -
77590 -static void hdmi_wp_init(struct omap_video_timings *timings,
77591 - struct hdmi_video_format *video_fmt)
77592 -{
77593 - pr_debug("Enter hdmi_wp_init\n");
77594 -
77595 - timings->hbp = 0;
77596 - timings->hfp = 0;
77597 - timings->hsw = 0;
77598 - timings->vbp = 0;
77599 - timings->vfp = 0;
77600 - timings->vsw = 0;
77601 -
77602 - video_fmt->packing_mode = HDMI_PACK_10b_RGB_YUV444;
77603 - video_fmt->y_res = 0;
77604 - video_fmt->x_res = 0;
77605 -
77606 -}
77607 -
77608 -int ti_hdmi_4xxx_wp_video_start(struct hdmi_ip_data *ip_data)
77609 -{
77610 - REG_FLD_MOD(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG, true, 31, 31);
77611 - return 0;
77612 -}
77613 -
77614 -void ti_hdmi_4xxx_wp_video_stop(struct hdmi_ip_data *ip_data)
77615 -{
77616 - REG_FLD_MOD(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG, false, 31, 31);
77617 -}
77618 -
77619 -static void hdmi_wp_video_init_format(struct hdmi_video_format *video_fmt,
77620 - struct omap_video_timings *timings, struct hdmi_config *param)
77621 -{
77622 - pr_debug("Enter hdmi_wp_video_init_format\n");
77623 -
77624 - video_fmt->y_res = param->timings.y_res;
77625 - video_fmt->x_res = param->timings.x_res;
77626 -
77627 - timings->hbp = param->timings.hbp;
77628 - timings->hfp = param->timings.hfp;
77629 - timings->hsw = param->timings.hsw;
77630 - timings->vbp = param->timings.vbp;
77631 - timings->vfp = param->timings.vfp;
77632 - timings->vsw = param->timings.vsw;
77633 -}
77634 -
77635 -static void hdmi_wp_video_config_format(struct hdmi_ip_data *ip_data,
77636 - struct hdmi_video_format *video_fmt)
77637 -{
77638 - u32 l = 0;
77639 -
77640 - REG_FLD_MOD(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG,
77641 - video_fmt->packing_mode, 10, 8);
77642 -
77643 - l |= FLD_VAL(video_fmt->y_res, 31, 16);
77644 - l |= FLD_VAL(video_fmt->x_res, 15, 0);
77645 - hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_SIZE, l);
77646 -}
77647 -
77648 -static void hdmi_wp_video_config_interface(struct hdmi_ip_data *ip_data)
77649 -{
77650 - u32 r;
77651 - bool vsync_pol, hsync_pol;
77652 - pr_debug("Enter hdmi_wp_video_config_interface\n");
77653 -
77654 - vsync_pol = ip_data->cfg.timings.vsync_level == OMAPDSS_SIG_ACTIVE_HIGH;
77655 - hsync_pol = ip_data->cfg.timings.hsync_level == OMAPDSS_SIG_ACTIVE_HIGH;
77656 -
77657 - r = hdmi_read_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG);
77658 - r = FLD_MOD(r, vsync_pol, 7, 7);
77659 - r = FLD_MOD(r, hsync_pol, 6, 6);
77660 - r = FLD_MOD(r, ip_data->cfg.timings.interlace, 3, 3);
77661 - r = FLD_MOD(r, 1, 1, 0); /* HDMI_TIMING_MASTER_24BIT */
77662 - hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG, r);
77663 -}
77664 -
77665 -static void hdmi_wp_video_config_timing(struct hdmi_ip_data *ip_data,
77666 - struct omap_video_timings *timings)
77667 -{
77668 - u32 timing_h = 0;
77669 - u32 timing_v = 0;
77670 -
77671 - pr_debug("Enter hdmi_wp_video_config_timing\n");
77672 -
77673 - timing_h |= FLD_VAL(timings->hbp, 31, 20);
77674 - timing_h |= FLD_VAL(timings->hfp, 19, 8);
77675 - timing_h |= FLD_VAL(timings->hsw, 7, 0);
77676 - hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_TIMING_H, timing_h);
77677 -
77678 - timing_v |= FLD_VAL(timings->vbp, 31, 20);
77679 - timing_v |= FLD_VAL(timings->vfp, 19, 8);
77680 - timing_v |= FLD_VAL(timings->vsw, 7, 0);
77681 - hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_TIMING_V, timing_v);
77682 -}
77683 -
77684 -void ti_hdmi_4xxx_basic_configure(struct hdmi_ip_data *ip_data)
77685 -{
77686 - /* HDMI */
77687 - struct omap_video_timings video_timing;
77688 - struct hdmi_video_format video_format;
77689 - /* HDMI core */
77690 - struct hdmi_core_infoframe_avi *avi_cfg = &ip_data->avi_cfg;
77691 - struct hdmi_core_video_config v_core_cfg;
77692 - struct hdmi_core_packet_enable_repeat repeat_cfg;
77693 - struct hdmi_config *cfg = &ip_data->cfg;
77694 -
77695 - hdmi_wp_init(&video_timing, &video_format);
77696 -
77697 - hdmi_core_init(&v_core_cfg, avi_cfg, &repeat_cfg);
77698 -
77699 - hdmi_wp_video_init_format(&video_format, &video_timing, cfg);
77700 -
77701 - hdmi_wp_video_config_timing(ip_data, &video_timing);
77702 -
77703 - /* video config */
77704 - video_format.packing_mode = HDMI_PACK_24b_RGB_YUV444_YUV422;
77705 -
77706 - hdmi_wp_video_config_format(ip_data, &video_format);
77707 -
77708 - hdmi_wp_video_config_interface(ip_data);
77709 -
77710 - /*
77711 - * configure core video part
77712 - * set software reset in the core
77713 - */
77714 - hdmi_core_swreset_assert(ip_data);
77715 -
77716 - /* power down off */
77717 - hdmi_core_powerdown_disable(ip_data);
77718 -
77719 - v_core_cfg.pkt_mode = HDMI_PACKETMODE24BITPERPIXEL;
77720 - v_core_cfg.hdmi_dvi = cfg->cm.mode;
77721 -
77722 - hdmi_core_video_config(ip_data, &v_core_cfg);
77723 -
77724 - /* release software reset in the core */
77725 - hdmi_core_swreset_release(ip_data);
77726 -
77727 - /*
77728 - * configure packet
77729 - * info frame video see doc CEA861-D page 65
77730 - */
77731 - avi_cfg->db1_format = HDMI_INFOFRAME_AVI_DB1Y_RGB;
77732 - avi_cfg->db1_active_info =
77733 - HDMI_INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_OFF;
77734 - avi_cfg->db1_bar_info_dv = HDMI_INFOFRAME_AVI_DB1B_NO;
77735 - avi_cfg->db1_scan_info = HDMI_INFOFRAME_AVI_DB1S_0;
77736 - avi_cfg->db2_colorimetry = HDMI_INFOFRAME_AVI_DB2C_NO;
77737 - avi_cfg->db2_aspect_ratio = HDMI_INFOFRAME_AVI_DB2M_NO;
77738 - avi_cfg->db2_active_fmt_ar = HDMI_INFOFRAME_AVI_DB2R_SAME;
77739 - avi_cfg->db3_itc = HDMI_INFOFRAME_AVI_DB3ITC_NO;
77740 - avi_cfg->db3_ec = HDMI_INFOFRAME_AVI_DB3EC_XVYUV601;
77741 - avi_cfg->db3_q_range = HDMI_INFOFRAME_AVI_DB3Q_DEFAULT;
77742 - avi_cfg->db3_nup_scaling = HDMI_INFOFRAME_AVI_DB3SC_NO;
77743 - avi_cfg->db4_videocode = cfg->cm.code;
77744 - avi_cfg->db5_pixel_repeat = HDMI_INFOFRAME_AVI_DB5PR_NO;
77745 - avi_cfg->db6_7_line_eoftop = 0;
77746 - avi_cfg->db8_9_line_sofbottom = 0;
77747 - avi_cfg->db10_11_pixel_eofleft = 0;
77748 - avi_cfg->db12_13_pixel_sofright = 0;
77749 -
77750 - hdmi_core_aux_infoframe_avi_config(ip_data);
77751 -
77752 - /* enable/repeat the infoframe */
77753 - repeat_cfg.avi_infoframe = HDMI_PACKETENABLE;
77754 - repeat_cfg.avi_infoframe_repeat = HDMI_PACKETREPEATON;
77755 - /* wakeup */
77756 - repeat_cfg.audio_pkt = HDMI_PACKETENABLE;
77757 - repeat_cfg.audio_pkt_repeat = HDMI_PACKETREPEATON;
77758 - hdmi_core_av_packet_config(ip_data, repeat_cfg);
77759 -}
77760 -
77761 -void ti_hdmi_4xxx_wp_dump(struct hdmi_ip_data *ip_data, struct seq_file *s)
77762 -{
77763 -#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r,\
77764 - hdmi_read_reg(hdmi_wp_base(ip_data), r))
77765 -
77766 - DUMPREG(HDMI_WP_REVISION);
77767 - DUMPREG(HDMI_WP_SYSCONFIG);
77768 - DUMPREG(HDMI_WP_IRQSTATUS_RAW);
77769 - DUMPREG(HDMI_WP_IRQSTATUS);
77770 - DUMPREG(HDMI_WP_PWR_CTRL);
77771 - DUMPREG(HDMI_WP_IRQENABLE_SET);
77772 - DUMPREG(HDMI_WP_VIDEO_CFG);
77773 - DUMPREG(HDMI_WP_VIDEO_SIZE);
77774 - DUMPREG(HDMI_WP_VIDEO_TIMING_H);
77775 - DUMPREG(HDMI_WP_VIDEO_TIMING_V);
77776 - DUMPREG(HDMI_WP_WP_CLK);
77777 - DUMPREG(HDMI_WP_AUDIO_CFG);
77778 - DUMPREG(HDMI_WP_AUDIO_CFG2);
77779 - DUMPREG(HDMI_WP_AUDIO_CTRL);
77780 - DUMPREG(HDMI_WP_AUDIO_DATA);
77781 -}
77782 -
77783 -void ti_hdmi_4xxx_pll_dump(struct hdmi_ip_data *ip_data, struct seq_file *s)
77784 -{
77785 -#define DUMPPLL(r) seq_printf(s, "%-35s %08x\n", #r,\
77786 - hdmi_read_reg(hdmi_pll_base(ip_data), r))
77787 -
77788 - DUMPPLL(PLLCTRL_PLL_CONTROL);
77789 - DUMPPLL(PLLCTRL_PLL_STATUS);
77790 - DUMPPLL(PLLCTRL_PLL_GO);
77791 - DUMPPLL(PLLCTRL_CFG1);
77792 - DUMPPLL(PLLCTRL_CFG2);
77793 - DUMPPLL(PLLCTRL_CFG3);
77794 - DUMPPLL(PLLCTRL_CFG4);
77795 -}
77796 -
77797 -void ti_hdmi_4xxx_core_dump(struct hdmi_ip_data *ip_data, struct seq_file *s)
77798 -{
77799 - int i;
77800 -
77801 -#define CORE_REG(i, name) name(i)
77802 -#define DUMPCORE(r) seq_printf(s, "%-35s %08x\n", #r,\
77803 - hdmi_read_reg(hdmi_core_sys_base(ip_data), r))
77804 -#define DUMPCOREAV(r) seq_printf(s, "%-35s %08x\n", #r,\
77805 - hdmi_read_reg(hdmi_av_base(ip_data), r))
77806 -#define DUMPCOREAV2(i, r) seq_printf(s, "%s[%d]%*s %08x\n", #r, i, \
77807 - (i < 10) ? 32 - (int)strlen(#r) : 31 - (int)strlen(#r), " ", \
77808 - hdmi_read_reg(hdmi_av_base(ip_data), CORE_REG(i, r)))
77809 -
77810 - DUMPCORE(HDMI_CORE_SYS_VND_IDL);
77811 - DUMPCORE(HDMI_CORE_SYS_DEV_IDL);
77812 - DUMPCORE(HDMI_CORE_SYS_DEV_IDH);
77813 - DUMPCORE(HDMI_CORE_SYS_DEV_REV);
77814 - DUMPCORE(HDMI_CORE_SYS_SRST);
77815 - DUMPCORE(HDMI_CORE_CTRL1);
77816 - DUMPCORE(HDMI_CORE_SYS_SYS_STAT);
77817 - DUMPCORE(HDMI_CORE_SYS_DE_DLY);
77818 - DUMPCORE(HDMI_CORE_SYS_DE_CTRL);
77819 - DUMPCORE(HDMI_CORE_SYS_DE_TOP);
77820 - DUMPCORE(HDMI_CORE_SYS_DE_CNTL);
77821 - DUMPCORE(HDMI_CORE_SYS_DE_CNTH);
77822 - DUMPCORE(HDMI_CORE_SYS_DE_LINL);
77823 - DUMPCORE(HDMI_CORE_SYS_DE_LINH_1);
77824 - DUMPCORE(HDMI_CORE_SYS_VID_ACEN);
77825 - DUMPCORE(HDMI_CORE_SYS_VID_MODE);
77826 - DUMPCORE(HDMI_CORE_SYS_INTR_STATE);
77827 - DUMPCORE(HDMI_CORE_SYS_INTR1);
77828 - DUMPCORE(HDMI_CORE_SYS_INTR2);
77829 - DUMPCORE(HDMI_CORE_SYS_INTR3);
77830 - DUMPCORE(HDMI_CORE_SYS_INTR4);
77831 - DUMPCORE(HDMI_CORE_SYS_UMASK1);
77832 - DUMPCORE(HDMI_CORE_SYS_TMDS_CTRL);
77833 -
77834 - DUMPCORE(HDMI_CORE_DDC_ADDR);
77835 - DUMPCORE(HDMI_CORE_DDC_SEGM);
77836 - DUMPCORE(HDMI_CORE_DDC_OFFSET);
77837 - DUMPCORE(HDMI_CORE_DDC_COUNT1);
77838 - DUMPCORE(HDMI_CORE_DDC_COUNT2);
77839 - DUMPCORE(HDMI_CORE_DDC_STATUS);
77840 - DUMPCORE(HDMI_CORE_DDC_CMD);
77841 - DUMPCORE(HDMI_CORE_DDC_DATA);
77842 -
77843 - DUMPCOREAV(HDMI_CORE_AV_ACR_CTRL);
77844 - DUMPCOREAV(HDMI_CORE_AV_FREQ_SVAL);
77845 - DUMPCOREAV(HDMI_CORE_AV_N_SVAL1);
77846 - DUMPCOREAV(HDMI_CORE_AV_N_SVAL2);
77847 - DUMPCOREAV(HDMI_CORE_AV_N_SVAL3);
77848 - DUMPCOREAV(HDMI_CORE_AV_CTS_SVAL1);
77849 - DUMPCOREAV(HDMI_CORE_AV_CTS_SVAL2);
77850 - DUMPCOREAV(HDMI_CORE_AV_CTS_SVAL3);
77851 - DUMPCOREAV(HDMI_CORE_AV_CTS_HVAL1);
77852 - DUMPCOREAV(HDMI_CORE_AV_CTS_HVAL2);
77853 - DUMPCOREAV(HDMI_CORE_AV_CTS_HVAL3);
77854 - DUMPCOREAV(HDMI_CORE_AV_AUD_MODE);
77855 - DUMPCOREAV(HDMI_CORE_AV_SPDIF_CTRL);
77856 - DUMPCOREAV(HDMI_CORE_AV_HW_SPDIF_FS);
77857 - DUMPCOREAV(HDMI_CORE_AV_SWAP_I2S);
77858 - DUMPCOREAV(HDMI_CORE_AV_SPDIF_ERTH);
77859 - DUMPCOREAV(HDMI_CORE_AV_I2S_IN_MAP);
77860 - DUMPCOREAV(HDMI_CORE_AV_I2S_IN_CTRL);
77861 - DUMPCOREAV(HDMI_CORE_AV_I2S_CHST0);
77862 - DUMPCOREAV(HDMI_CORE_AV_I2S_CHST1);
77863 - DUMPCOREAV(HDMI_CORE_AV_I2S_CHST2);
77864 - DUMPCOREAV(HDMI_CORE_AV_I2S_CHST4);
77865 - DUMPCOREAV(HDMI_CORE_AV_I2S_CHST5);
77866 - DUMPCOREAV(HDMI_CORE_AV_ASRC);
77867 - DUMPCOREAV(HDMI_CORE_AV_I2S_IN_LEN);
77868 - DUMPCOREAV(HDMI_CORE_AV_HDMI_CTRL);
77869 - DUMPCOREAV(HDMI_CORE_AV_AUDO_TXSTAT);
77870 - DUMPCOREAV(HDMI_CORE_AV_AUD_PAR_BUSCLK_1);
77871 - DUMPCOREAV(HDMI_CORE_AV_AUD_PAR_BUSCLK_2);
77872 - DUMPCOREAV(HDMI_CORE_AV_AUD_PAR_BUSCLK_3);
77873 - DUMPCOREAV(HDMI_CORE_AV_TEST_TXCTRL);
77874 - DUMPCOREAV(HDMI_CORE_AV_DPD);
77875 - DUMPCOREAV(HDMI_CORE_AV_PB_CTRL1);
77876 - DUMPCOREAV(HDMI_CORE_AV_PB_CTRL2);
77877 - DUMPCOREAV(HDMI_CORE_AV_AVI_TYPE);
77878 - DUMPCOREAV(HDMI_CORE_AV_AVI_VERS);
77879 - DUMPCOREAV(HDMI_CORE_AV_AVI_LEN);
77880 - DUMPCOREAV(HDMI_CORE_AV_AVI_CHSUM);
77881 -
77882 - for (i = 0; i < HDMI_CORE_AV_AVI_DBYTE_NELEMS; i++)
77883 - DUMPCOREAV2(i, HDMI_CORE_AV_AVI_DBYTE);
77884 -
77885 - DUMPCOREAV(HDMI_CORE_AV_SPD_TYPE);
77886 - DUMPCOREAV(HDMI_CORE_AV_SPD_VERS);
77887 - DUMPCOREAV(HDMI_CORE_AV_SPD_LEN);
77888 - DUMPCOREAV(HDMI_CORE_AV_SPD_CHSUM);
77889 -
77890 - for (i = 0; i < HDMI_CORE_AV_SPD_DBYTE_NELEMS; i++)
77891 - DUMPCOREAV2(i, HDMI_CORE_AV_SPD_DBYTE);
77892 -
77893 - DUMPCOREAV(HDMI_CORE_AV_AUDIO_TYPE);
77894 - DUMPCOREAV(HDMI_CORE_AV_AUDIO_VERS);
77895 - DUMPCOREAV(HDMI_CORE_AV_AUDIO_LEN);
77896 - DUMPCOREAV(HDMI_CORE_AV_AUDIO_CHSUM);
77897 -
77898 - for (i = 0; i < HDMI_CORE_AV_AUD_DBYTE_NELEMS; i++)
77899 - DUMPCOREAV2(i, HDMI_CORE_AV_AUD_DBYTE);
77900 -
77901 - DUMPCOREAV(HDMI_CORE_AV_MPEG_TYPE);
77902 - DUMPCOREAV(HDMI_CORE_AV_MPEG_VERS);
77903 - DUMPCOREAV(HDMI_CORE_AV_MPEG_LEN);
77904 - DUMPCOREAV(HDMI_CORE_AV_MPEG_CHSUM);
77905 -
77906 - for (i = 0; i < HDMI_CORE_AV_MPEG_DBYTE_NELEMS; i++)
77907 - DUMPCOREAV2(i, HDMI_CORE_AV_MPEG_DBYTE);
77908 -
77909 - for (i = 0; i < HDMI_CORE_AV_GEN_DBYTE_NELEMS; i++)
77910 - DUMPCOREAV2(i, HDMI_CORE_AV_GEN_DBYTE);
77911 -
77912 - DUMPCOREAV(HDMI_CORE_AV_CP_BYTE1);
77913 -
77914 - for (i = 0; i < HDMI_CORE_AV_GEN2_DBYTE_NELEMS; i++)
77915 - DUMPCOREAV2(i, HDMI_CORE_AV_GEN2_DBYTE);
77916 -
77917 - DUMPCOREAV(HDMI_CORE_AV_CEC_ADDR_ID);
77918 -}
77919 -
77920 -void ti_hdmi_4xxx_phy_dump(struct hdmi_ip_data *ip_data, struct seq_file *s)
77921 -{
77922 -#define DUMPPHY(r) seq_printf(s, "%-35s %08x\n", #r,\
77923 - hdmi_read_reg(hdmi_phy_base(ip_data), r))
77924 -
77925 - DUMPPHY(HDMI_TXPHY_TX_CTRL);
77926 - DUMPPHY(HDMI_TXPHY_DIGITAL_CTRL);
77927 - DUMPPHY(HDMI_TXPHY_POWER_CTRL);
77928 - DUMPPHY(HDMI_TXPHY_PAD_CFG_CTRL);
77929 -}
77930 -
77931 -#if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO)
77932 -static void ti_hdmi_4xxx_wp_audio_config_format(struct hdmi_ip_data *ip_data,
77933 - struct hdmi_audio_format *aud_fmt)
77934 -{
77935 - u32 r;
77936 -
77937 - DSSDBG("Enter hdmi_wp_audio_config_format\n");
77938 -
77939 - r = hdmi_read_reg(hdmi_wp_base(ip_data), HDMI_WP_AUDIO_CFG);
77940 - r = FLD_MOD(r, aud_fmt->stereo_channels, 26, 24);
77941 - r = FLD_MOD(r, aud_fmt->active_chnnls_msk, 23, 16);
77942 - r = FLD_MOD(r, aud_fmt->en_sig_blk_strt_end, 5, 5);
77943 - r = FLD_MOD(r, aud_fmt->type, 4, 4);
77944 - r = FLD_MOD(r, aud_fmt->justification, 3, 3);
77945 - r = FLD_MOD(r, aud_fmt->sample_order, 2, 2);
77946 - r = FLD_MOD(r, aud_fmt->samples_per_word, 1, 1);
77947 - r = FLD_MOD(r, aud_fmt->sample_size, 0, 0);
77948 - hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_AUDIO_CFG, r);
77949 -}
77950 -
77951 -static void ti_hdmi_4xxx_wp_audio_config_dma(struct hdmi_ip_data *ip_data,
77952 - struct hdmi_audio_dma *aud_dma)
77953 -{
77954 - u32 r;
77955 -
77956 - DSSDBG("Enter hdmi_wp_audio_config_dma\n");
77957 -
77958 - r = hdmi_read_reg(hdmi_wp_base(ip_data), HDMI_WP_AUDIO_CFG2);
77959 - r = FLD_MOD(r, aud_dma->transfer_size, 15, 8);
77960 - r = FLD_MOD(r, aud_dma->block_size, 7, 0);
77961 - hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_AUDIO_CFG2, r);
77962 -
77963 - r = hdmi_read_reg(hdmi_wp_base(ip_data), HDMI_WP_AUDIO_CTRL);
77964 - r = FLD_MOD(r, aud_dma->mode, 9, 9);
77965 - r = FLD_MOD(r, aud_dma->fifo_threshold, 8, 0);
77966 - hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_AUDIO_CTRL, r);
77967 -}
77968 -
77969 -static void ti_hdmi_4xxx_core_audio_config(struct hdmi_ip_data *ip_data,
77970 - struct hdmi_core_audio_config *cfg)
77971 -{
77972 - u32 r;
77973 - void __iomem *av_base = hdmi_av_base(ip_data);
77974 -
77975 - /*
77976 - * Parameters for generation of Audio Clock Recovery packets
77977 - */
77978 - REG_FLD_MOD(av_base, HDMI_CORE_AV_N_SVAL1, cfg->n, 7, 0);
77979 - REG_FLD_MOD(av_base, HDMI_CORE_AV_N_SVAL2, cfg->n >> 8, 7, 0);
77980 - REG_FLD_MOD(av_base, HDMI_CORE_AV_N_SVAL3, cfg->n >> 16, 7, 0);
77981 -
77982 - if (cfg->cts_mode == HDMI_AUDIO_CTS_MODE_SW) {
77983 - REG_FLD_MOD(av_base, HDMI_CORE_AV_CTS_SVAL1, cfg->cts, 7, 0);
77984 - REG_FLD_MOD(av_base,
77985 - HDMI_CORE_AV_CTS_SVAL2, cfg->cts >> 8, 7, 0);
77986 - REG_FLD_MOD(av_base,
77987 - HDMI_CORE_AV_CTS_SVAL3, cfg->cts >> 16, 7, 0);
77988 - } else {
77989 - REG_FLD_MOD(av_base, HDMI_CORE_AV_AUD_PAR_BUSCLK_1,
77990 - cfg->aud_par_busclk, 7, 0);
77991 - REG_FLD_MOD(av_base, HDMI_CORE_AV_AUD_PAR_BUSCLK_2,
77992 - (cfg->aud_par_busclk >> 8), 7, 0);
77993 - REG_FLD_MOD(av_base, HDMI_CORE_AV_AUD_PAR_BUSCLK_3,
77994 - (cfg->aud_par_busclk >> 16), 7, 0);
77995 - }
77996 -
77997 - /* Set ACR clock divisor */
77998 - REG_FLD_MOD(av_base,
77999 - HDMI_CORE_AV_FREQ_SVAL, cfg->mclk_mode, 2, 0);
78000 -
78001 - r = hdmi_read_reg(av_base, HDMI_CORE_AV_ACR_CTRL);
78002 - /*
78003 - * Use TMDS clock for ACR packets. For devices that use
78004 - * the MCLK, this is the first part of the MCLK initialization.
78005 - */
78006 - r = FLD_MOD(r, 0, 2, 2);
78007 -
78008 - r = FLD_MOD(r, cfg->en_acr_pkt, 1, 1);
78009 - r = FLD_MOD(r, cfg->cts_mode, 0, 0);
78010 - hdmi_write_reg(av_base, HDMI_CORE_AV_ACR_CTRL, r);
78011 -
78012 - /* For devices using MCLK, this completes its initialization. */
78013 - if (cfg->use_mclk)
78014 - REG_FLD_MOD(av_base, HDMI_CORE_AV_ACR_CTRL, 1, 2, 2);
78015 -
78016 - /* Override of SPDIF sample frequency with value in I2S_CHST4 */
78017 - REG_FLD_MOD(av_base, HDMI_CORE_AV_SPDIF_CTRL,
78018 - cfg->fs_override, 1, 1);
78019 -
78020 - /*
78021 - * Set IEC-60958-3 channel status word. It is passed to the IP
78022 - * just as it is received. The user of the driver is responsible
78023 - * for its contents.
78024 - */
78025 - hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_CHST0,
78026 - cfg->iec60958_cfg->status[0]);
78027 - hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_CHST1,
78028 - cfg->iec60958_cfg->status[1]);
78029 - hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_CHST2,
78030 - cfg->iec60958_cfg->status[2]);
78031 - /* yes, this is correct: status[3] goes to CHST4 register */
78032 - hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_CHST4,
78033 - cfg->iec60958_cfg->status[3]);
78034 - /* yes, this is correct: status[4] goes to CHST5 register */
78035 - hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_CHST5,
78036 - cfg->iec60958_cfg->status[4]);
78037 -
78038 - /* set I2S parameters */
78039 - r = hdmi_read_reg(av_base, HDMI_CORE_AV_I2S_IN_CTRL);
78040 - r = FLD_MOD(r, cfg->i2s_cfg.sck_edge_mode, 6, 6);
78041 - r = FLD_MOD(r, cfg->i2s_cfg.vbit, 4, 4);
78042 - r = FLD_MOD(r, cfg->i2s_cfg.justification, 2, 2);
78043 - r = FLD_MOD(r, cfg->i2s_cfg.direction, 1, 1);
78044 - r = FLD_MOD(r, cfg->i2s_cfg.shift, 0, 0);
78045 - hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_IN_CTRL, r);
78046 -
78047 - REG_FLD_MOD(av_base, HDMI_CORE_AV_I2S_IN_LEN,
78048 - cfg->i2s_cfg.in_length_bits, 3, 0);
78049 -
78050 - /* Audio channels and mode parameters */
78051 - REG_FLD_MOD(av_base, HDMI_CORE_AV_HDMI_CTRL, cfg->layout, 2, 1);
78052 - r = hdmi_read_reg(av_base, HDMI_CORE_AV_AUD_MODE);
78053 - r = FLD_MOD(r, cfg->i2s_cfg.active_sds, 7, 4);
78054 - r = FLD_MOD(r, cfg->en_dsd_audio, 3, 3);
78055 - r = FLD_MOD(r, cfg->en_parallel_aud_input, 2, 2);
78056 - r = FLD_MOD(r, cfg->en_spdif, 1, 1);
78057 - hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_MODE, r);
78058 -
78059 - /* Audio channel mappings */
78060 - /* TODO: Make channel mapping dynamic. For now, map channels
78061 - * in the ALSA order: FL/FR/RL/RR/C/LFE/SL/SR. Remapping is needed as
78062 - * HDMI speaker order is different. See CEA-861 Section 6.6.2.
78063 - */
78064 - hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_IN_MAP, 0x78);
78065 - REG_FLD_MOD(av_base, HDMI_CORE_AV_SWAP_I2S, 1, 5, 5);
78066 -}
78067 -
78068 -static void ti_hdmi_4xxx_core_audio_infoframe_cfg(struct hdmi_ip_data *ip_data,
78069 - struct snd_cea_861_aud_if *info_aud)
78070 -{
78071 - u8 sum = 0, checksum = 0;
78072 - void __iomem *av_base = hdmi_av_base(ip_data);
78073 -
78074 - /*
78075 - * Set audio info frame type, version and length as
78076 - * described in HDMI 1.4a Section 8.2.2 specification.
78077 - * Checksum calculation is defined in Section 5.3.5.
78078 - */
78079 - hdmi_write_reg(av_base, HDMI_CORE_AV_AUDIO_TYPE, 0x84);
78080 - hdmi_write_reg(av_base, HDMI_CORE_AV_AUDIO_VERS, 0x01);
78081 - hdmi_write_reg(av_base, HDMI_CORE_AV_AUDIO_LEN, 0x0a);
78082 - sum += 0x84 + 0x001 + 0x00a;
78083 -
78084 - hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(0),
78085 - info_aud->db1_ct_cc);
78086 - sum += info_aud->db1_ct_cc;
78087 -
78088 - hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(1),
78089 - info_aud->db2_sf_ss);
78090 - sum += info_aud->db2_sf_ss;
78091 -
78092 - hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(2), info_aud->db3);
78093 - sum += info_aud->db3;
78094 -
78095 - hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(3), info_aud->db4_ca);
78096 - sum += info_aud->db4_ca;
78097 -
78098 - hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(4),
78099 - info_aud->db5_dminh_lsv);
78100 - sum += info_aud->db5_dminh_lsv;
78101 -
78102 - hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(5), 0x00);
78103 - hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(6), 0x00);
78104 - hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(7), 0x00);
78105 - hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(8), 0x00);
78106 - hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(9), 0x00);
78107 -
78108 - checksum = 0x100 - sum;
78109 - hdmi_write_reg(av_base,
78110 - HDMI_CORE_AV_AUDIO_CHSUM, checksum);
78111 -
78112 - /*
78113 - * TODO: Add MPEG and SPD enable and repeat cfg when EDID parsing
78114 - * is available.
78115 - */
78116 -}
78117 -
78118 -int ti_hdmi_4xxx_audio_config(struct hdmi_ip_data *ip_data,
78119 - struct omap_dss_audio *audio)
78120 -{
78121 - struct hdmi_audio_format audio_format;
78122 - struct hdmi_audio_dma audio_dma;
78123 - struct hdmi_core_audio_config core;
78124 - int err, n, cts, channel_count;
78125 - unsigned int fs_nr;
78126 - bool word_length_16b = false;
78127 -
78128 - if (!audio || !audio->iec || !audio->cea || !ip_data)
78129 - return -EINVAL;
78130 -
78131 - core.iec60958_cfg = audio->iec;
78132 - /*
78133 - * In the IEC-60958 status word, check if the audio sample word length
78134 - * is 16-bit as several optimizations can be performed in such case.
78135 - */
78136 - if (!(audio->iec->status[4] & IEC958_AES4_CON_MAX_WORDLEN_24))
78137 - if (audio->iec->status[4] & IEC958_AES4_CON_WORDLEN_20_16)
78138 - word_length_16b = true;
78139 -
78140 - /* I2S configuration. See Phillips' specification */
78141 - if (word_length_16b)
78142 - core.i2s_cfg.justification = HDMI_AUDIO_JUSTIFY_LEFT;
78143 - else
78144 - core.i2s_cfg.justification = HDMI_AUDIO_JUSTIFY_RIGHT;
78145 - /*
78146 - * The I2S input word length is twice the lenght given in the IEC-60958
78147 - * status word. If the word size is greater than
78148 - * 20 bits, increment by one.
78149 - */
78150 - core.i2s_cfg.in_length_bits = audio->iec->status[4]
78151 - & IEC958_AES4_CON_WORDLEN;
78152 - if (audio->iec->status[4] & IEC958_AES4_CON_MAX_WORDLEN_24)
78153 - core.i2s_cfg.in_length_bits++;
78154 - core.i2s_cfg.sck_edge_mode = HDMI_AUDIO_I2S_SCK_EDGE_RISING;
78155 - core.i2s_cfg.vbit = HDMI_AUDIO_I2S_VBIT_FOR_PCM;
78156 - core.i2s_cfg.direction = HDMI_AUDIO_I2S_MSB_SHIFTED_FIRST;
78157 - core.i2s_cfg.shift = HDMI_AUDIO_I2S_FIRST_BIT_SHIFT;
78158 -
78159 - /* convert sample frequency to a number */
78160 - switch (audio->iec->status[3] & IEC958_AES3_CON_FS) {
78161 - case IEC958_AES3_CON_FS_32000:
78162 - fs_nr = 32000;
78163 - break;
78164 - case IEC958_AES3_CON_FS_44100:
78165 - fs_nr = 44100;
78166 - break;
78167 - case IEC958_AES3_CON_FS_48000:
78168 - fs_nr = 48000;
78169 - break;
78170 - case IEC958_AES3_CON_FS_88200:
78171 - fs_nr = 88200;
78172 - break;
78173 - case IEC958_AES3_CON_FS_96000:
78174 - fs_nr = 96000;
78175 - break;
78176 - case IEC958_AES3_CON_FS_176400:
78177 - fs_nr = 176400;
78178 - break;
78179 - case IEC958_AES3_CON_FS_192000:
78180 - fs_nr = 192000;
78181 - break;
78182 - default:
78183 - return -EINVAL;
78184 - }
78185 -
78186 - err = hdmi_compute_acr(fs_nr, &n, &cts);
78187 -
78188 - /* Audio clock regeneration settings */
78189 - core.n = n;
78190 - core.cts = cts;
78191 - if (dss_has_feature(FEAT_HDMI_CTS_SWMODE)) {
78192 - core.aud_par_busclk = 0;
78193 - core.cts_mode = HDMI_AUDIO_CTS_MODE_SW;
78194 - core.use_mclk = dss_has_feature(FEAT_HDMI_AUDIO_USE_MCLK);
78195 - } else {
78196 - core.aud_par_busclk = (((128 * 31) - 1) << 8);
78197 - core.cts_mode = HDMI_AUDIO_CTS_MODE_HW;
78198 - core.use_mclk = true;
78199 - }
78200 -
78201 - if (core.use_mclk)
78202 - core.mclk_mode = HDMI_AUDIO_MCLK_128FS;
78203 -
78204 - /* Audio channels settings */
78205 - channel_count = (audio->cea->db1_ct_cc &
78206 - CEA861_AUDIO_INFOFRAME_DB1CC) + 1;
78207 -
78208 - switch (channel_count) {
78209 - case 2:
78210 - audio_format.active_chnnls_msk = 0x03;
78211 - break;
78212 - case 3:
78213 - audio_format.active_chnnls_msk = 0x07;
78214 - break;
78215 - case 4:
78216 - audio_format.active_chnnls_msk = 0x0f;
78217 - break;
78218 - case 5:
78219 - audio_format.active_chnnls_msk = 0x1f;
78220 - break;
78221 - case 6:
78222 - audio_format.active_chnnls_msk = 0x3f;
78223 - break;
78224 - case 7:
78225 - audio_format.active_chnnls_msk = 0x7f;
78226 - break;
78227 - case 8:
78228 - audio_format.active_chnnls_msk = 0xff;
78229 - break;
78230 - default:
78231 - return -EINVAL;
78232 - }
78233 -
78234 - /*
78235 - * the HDMI IP needs to enable four stereo channels when transmitting
78236 - * more than 2 audio channels
78237 - */
78238 - if (channel_count == 2) {
78239 - audio_format.stereo_channels = HDMI_AUDIO_STEREO_ONECHANNEL;
78240 - core.i2s_cfg.active_sds = HDMI_AUDIO_I2S_SD0_EN;
78241 - core.layout = HDMI_AUDIO_LAYOUT_2CH;
78242 - } else {
78243 - audio_format.stereo_channels = HDMI_AUDIO_STEREO_FOURCHANNELS;
78244 - core.i2s_cfg.active_sds = HDMI_AUDIO_I2S_SD0_EN |
78245 - HDMI_AUDIO_I2S_SD1_EN | HDMI_AUDIO_I2S_SD2_EN |
78246 - HDMI_AUDIO_I2S_SD3_EN;
78247 - core.layout = HDMI_AUDIO_LAYOUT_8CH;
78248 - }
78249 -
78250 - core.en_spdif = false;
78251 - /* use sample frequency from channel status word */
78252 - core.fs_override = true;
78253 - /* enable ACR packets */
78254 - core.en_acr_pkt = true;
78255 - /* disable direct streaming digital audio */
78256 - core.en_dsd_audio = false;
78257 - /* use parallel audio interface */
78258 - core.en_parallel_aud_input = true;
78259 -
78260 - /* DMA settings */
78261 - if (word_length_16b)
78262 - audio_dma.transfer_size = 0x10;
78263 - else
78264 - audio_dma.transfer_size = 0x20;
78265 - audio_dma.block_size = 0xC0;
78266 - audio_dma.mode = HDMI_AUDIO_TRANSF_DMA;
78267 - audio_dma.fifo_threshold = 0x20; /* in number of samples */
78268 -
78269 - /* audio FIFO format settings */
78270 - if (word_length_16b) {
78271 - audio_format.samples_per_word = HDMI_AUDIO_ONEWORD_TWOSAMPLES;
78272 - audio_format.sample_size = HDMI_AUDIO_SAMPLE_16BITS;
78273 - audio_format.justification = HDMI_AUDIO_JUSTIFY_LEFT;
78274 - } else {
78275 - audio_format.samples_per_word = HDMI_AUDIO_ONEWORD_ONESAMPLE;
78276 - audio_format.sample_size = HDMI_AUDIO_SAMPLE_24BITS;
78277 - audio_format.justification = HDMI_AUDIO_JUSTIFY_RIGHT;
78278 - }
78279 - audio_format.type = HDMI_AUDIO_TYPE_LPCM;
78280 - audio_format.sample_order = HDMI_AUDIO_SAMPLE_LEFT_FIRST;
78281 - /* disable start/stop signals of IEC 60958 blocks */
78282 - audio_format.en_sig_blk_strt_end = HDMI_AUDIO_BLOCK_SIG_STARTEND_ON;
78283 -
78284 - /* configure DMA and audio FIFO format*/
78285 - ti_hdmi_4xxx_wp_audio_config_dma(ip_data, &audio_dma);
78286 - ti_hdmi_4xxx_wp_audio_config_format(ip_data, &audio_format);
78287 -
78288 - /* configure the core*/
78289 - ti_hdmi_4xxx_core_audio_config(ip_data, &core);
78290 -
78291 - /* configure CEA 861 audio infoframe*/
78292 - ti_hdmi_4xxx_core_audio_infoframe_cfg(ip_data, audio->cea);
78293 -
78294 - return 0;
78295 -}
78296 -
78297 -int ti_hdmi_4xxx_wp_audio_enable(struct hdmi_ip_data *ip_data)
78298 -{
78299 - REG_FLD_MOD(hdmi_wp_base(ip_data),
78300 - HDMI_WP_AUDIO_CTRL, true, 31, 31);
78301 - return 0;
78302 -}
78303 -
78304 -void ti_hdmi_4xxx_wp_audio_disable(struct hdmi_ip_data *ip_data)
78305 -{
78306 - REG_FLD_MOD(hdmi_wp_base(ip_data),
78307 - HDMI_WP_AUDIO_CTRL, false, 31, 31);
78308 -}
78309 -
78310 -int ti_hdmi_4xxx_audio_start(struct hdmi_ip_data *ip_data)
78311 -{
78312 - REG_FLD_MOD(hdmi_av_base(ip_data),
78313 - HDMI_CORE_AV_AUD_MODE, true, 0, 0);
78314 - REG_FLD_MOD(hdmi_wp_base(ip_data),
78315 - HDMI_WP_AUDIO_CTRL, true, 30, 30);
78316 - return 0;
78317 -}
78318 -
78319 -void ti_hdmi_4xxx_audio_stop(struct hdmi_ip_data *ip_data)
78320 -{
78321 - REG_FLD_MOD(hdmi_av_base(ip_data),
78322 - HDMI_CORE_AV_AUD_MODE, false, 0, 0);
78323 - REG_FLD_MOD(hdmi_wp_base(ip_data),
78324 - HDMI_WP_AUDIO_CTRL, false, 30, 30);
78325 -}
78326 -
78327 -int ti_hdmi_4xxx_audio_get_dma_port(u32 *offset, u32 *size)
78328 -{
78329 - if (!offset || !size)
78330 - return -EINVAL;
78331 - *offset = HDMI_WP_AUDIO_DATA;
78332 - *size = 4;
78333 - return 0;
78334 -}
78335 -#endif
78336 --- a/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.h
78337 +++ /dev/null
78338 @@ -1,437 +0,0 @@
78339 -/*
78340 - * ti_hdmi_4xxx_ip.h
78341 - *
78342 - * HDMI header definition for DM81xx, DM38xx, TI OMAP4 etc processors.
78343 - *
78344 - * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
78345 - *
78346 - * This program is free software; you can redistribute it and/or modify it
78347 - * under the terms of the GNU General Public License version 2 as published by
78348 - * the Free Software Foundation.
78349 - *
78350 - * This program is distributed in the hope that it will be useful, but WITHOUT
78351 - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
78352 - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
78353 - * more details.
78354 - *
78355 - * You should have received a copy of the GNU General Public License along with
78356 - * this program. If not, see <http://www.gnu.org/licenses/>.
78357 - */
78358 -
78359 -#ifndef _HDMI_TI_4xxx_H_
78360 -#define _HDMI_TI_4xxx_H_
78361 -
78362 -#include <linux/string.h>
78363 -#include <video/omapdss.h>
78364 -#include "ti_hdmi.h"
78365 -
78366 -/* HDMI Wrapper */
78367 -
78368 -#define HDMI_WP_REVISION 0x0
78369 -#define HDMI_WP_SYSCONFIG 0x10
78370 -#define HDMI_WP_IRQSTATUS_RAW 0x24
78371 -#define HDMI_WP_IRQSTATUS 0x28
78372 -#define HDMI_WP_PWR_CTRL 0x40
78373 -#define HDMI_WP_IRQENABLE_SET 0x2C
78374 -#define HDMI_WP_IRQENABLE_CLR 0x30
78375 -#define HDMI_WP_VIDEO_CFG 0x50
78376 -#define HDMI_WP_VIDEO_SIZE 0x60
78377 -#define HDMI_WP_VIDEO_TIMING_H 0x68
78378 -#define HDMI_WP_VIDEO_TIMING_V 0x6C
78379 -#define HDMI_WP_WP_CLK 0x70
78380 -#define HDMI_WP_AUDIO_CFG 0x80
78381 -#define HDMI_WP_AUDIO_CFG2 0x84
78382 -#define HDMI_WP_AUDIO_CTRL 0x88
78383 -#define HDMI_WP_AUDIO_DATA 0x8C
78384 -
78385 -/* HDMI IP Core System */
78386 -
78387 -#define HDMI_CORE_SYS_VND_IDL 0x0
78388 -#define HDMI_CORE_SYS_DEV_IDL 0x8
78389 -#define HDMI_CORE_SYS_DEV_IDH 0xC
78390 -#define HDMI_CORE_SYS_DEV_REV 0x10
78391 -#define HDMI_CORE_SYS_SRST 0x14
78392 -#define HDMI_CORE_CTRL1 0x20
78393 -#define HDMI_CORE_SYS_SYS_STAT 0x24
78394 -#define HDMI_CORE_SYS_DE_DLY 0xC8
78395 -#define HDMI_CORE_SYS_DE_CTRL 0xCC
78396 -#define HDMI_CORE_SYS_DE_TOP 0xD0
78397 -#define HDMI_CORE_SYS_DE_CNTL 0xD8
78398 -#define HDMI_CORE_SYS_DE_CNTH 0xDC
78399 -#define HDMI_CORE_SYS_DE_LINL 0xE0
78400 -#define HDMI_CORE_SYS_DE_LINH_1 0xE4
78401 -#define HDMI_CORE_SYS_VID_ACEN 0x124
78402 -#define HDMI_CORE_SYS_VID_MODE 0x128
78403 -#define HDMI_CORE_SYS_INTR_STATE 0x1C0
78404 -#define HDMI_CORE_SYS_INTR1 0x1C4
78405 -#define HDMI_CORE_SYS_INTR2 0x1C8
78406 -#define HDMI_CORE_SYS_INTR3 0x1CC
78407 -#define HDMI_CORE_SYS_INTR4 0x1D0
78408 -#define HDMI_CORE_SYS_UMASK1 0x1D4
78409 -#define HDMI_CORE_SYS_TMDS_CTRL 0x208
78410 -
78411 -#define HDMI_CORE_CTRL1_VEN_FOLLOWVSYNC 0x1
78412 -#define HDMI_CORE_CTRL1_HEN_FOLLOWHSYNC 0x1
78413 -#define HDMI_CORE_CTRL1_BSEL_24BITBUS 0x1
78414 -#define HDMI_CORE_CTRL1_EDGE_RISINGEDGE 0x1
78415 -
78416 -/* HDMI DDC E-DID */
78417 -#define HDMI_CORE_DDC_ADDR 0x3B4
78418 -#define HDMI_CORE_DDC_SEGM 0x3B8
78419 -#define HDMI_CORE_DDC_OFFSET 0x3BC
78420 -#define HDMI_CORE_DDC_COUNT1 0x3C0
78421 -#define HDMI_CORE_DDC_COUNT2 0x3C4
78422 -#define HDMI_CORE_DDC_STATUS 0x3C8
78423 -#define HDMI_CORE_DDC_CMD 0x3CC
78424 -#define HDMI_CORE_DDC_DATA 0x3D0
78425 -
78426 -/* HDMI IP Core Audio Video */
78427 -
78428 -#define HDMI_CORE_AV_ACR_CTRL 0x4
78429 -#define HDMI_CORE_AV_FREQ_SVAL 0x8
78430 -#define HDMI_CORE_AV_N_SVAL1 0xC
78431 -#define HDMI_CORE_AV_N_SVAL2 0x10
78432 -#define HDMI_CORE_AV_N_SVAL3 0x14
78433 -#define HDMI_CORE_AV_CTS_SVAL1 0x18
78434 -#define HDMI_CORE_AV_CTS_SVAL2 0x1C
78435 -#define HDMI_CORE_AV_CTS_SVAL3 0x20
78436 -#define HDMI_CORE_AV_CTS_HVAL1 0x24
78437 -#define HDMI_CORE_AV_CTS_HVAL2 0x28
78438 -#define HDMI_CORE_AV_CTS_HVAL3 0x2C
78439 -#define HDMI_CORE_AV_AUD_MODE 0x50
78440 -#define HDMI_CORE_AV_SPDIF_CTRL 0x54
78441 -#define HDMI_CORE_AV_HW_SPDIF_FS 0x60
78442 -#define HDMI_CORE_AV_SWAP_I2S 0x64
78443 -#define HDMI_CORE_AV_SPDIF_ERTH 0x6C
78444 -#define HDMI_CORE_AV_I2S_IN_MAP 0x70
78445 -#define HDMI_CORE_AV_I2S_IN_CTRL 0x74
78446 -#define HDMI_CORE_AV_I2S_CHST0 0x78
78447 -#define HDMI_CORE_AV_I2S_CHST1 0x7C
78448 -#define HDMI_CORE_AV_I2S_CHST2 0x80
78449 -#define HDMI_CORE_AV_I2S_CHST4 0x84
78450 -#define HDMI_CORE_AV_I2S_CHST5 0x88
78451 -#define HDMI_CORE_AV_ASRC 0x8C
78452 -#define HDMI_CORE_AV_I2S_IN_LEN 0x90
78453 -#define HDMI_CORE_AV_HDMI_CTRL 0xBC
78454 -#define HDMI_CORE_AV_AUDO_TXSTAT 0xC0
78455 -#define HDMI_CORE_AV_AUD_PAR_BUSCLK_1 0xCC
78456 -#define HDMI_CORE_AV_AUD_PAR_BUSCLK_2 0xD0
78457 -#define HDMI_CORE_AV_AUD_PAR_BUSCLK_3 0xD4
78458 -#define HDMI_CORE_AV_TEST_TXCTRL 0xF0
78459 -#define HDMI_CORE_AV_DPD 0xF4
78460 -#define HDMI_CORE_AV_PB_CTRL1 0xF8
78461 -#define HDMI_CORE_AV_PB_CTRL2 0xFC
78462 -#define HDMI_CORE_AV_AVI_TYPE 0x100
78463 -#define HDMI_CORE_AV_AVI_VERS 0x104
78464 -#define HDMI_CORE_AV_AVI_LEN 0x108
78465 -#define HDMI_CORE_AV_AVI_CHSUM 0x10C
78466 -#define HDMI_CORE_AV_AVI_DBYTE(n) (n * 4 + 0x110)
78467 -#define HDMI_CORE_AV_SPD_TYPE 0x180
78468 -#define HDMI_CORE_AV_SPD_VERS 0x184
78469 -#define HDMI_CORE_AV_SPD_LEN 0x188
78470 -#define HDMI_CORE_AV_SPD_CHSUM 0x18C
78471 -#define HDMI_CORE_AV_SPD_DBYTE(n) (n * 4 + 0x190)
78472 -#define HDMI_CORE_AV_AUDIO_TYPE 0x200
78473 -#define HDMI_CORE_AV_AUDIO_VERS 0x204
78474 -#define HDMI_CORE_AV_AUDIO_LEN 0x208
78475 -#define HDMI_CORE_AV_AUDIO_CHSUM 0x20C
78476 -#define HDMI_CORE_AV_AUD_DBYTE(n) (n * 4 + 0x210)
78477 -#define HDMI_CORE_AV_MPEG_TYPE 0x280
78478 -#define HDMI_CORE_AV_MPEG_VERS 0x284
78479 -#define HDMI_CORE_AV_MPEG_LEN 0x288
78480 -#define HDMI_CORE_AV_MPEG_CHSUM 0x28C
78481 -#define HDMI_CORE_AV_MPEG_DBYTE(n) (n * 4 + 0x290)
78482 -#define HDMI_CORE_AV_GEN_DBYTE(n) (n * 4 + 0x300)
78483 -#define HDMI_CORE_AV_CP_BYTE1 0x37C
78484 -#define HDMI_CORE_AV_GEN2_DBYTE(n) (n * 4 + 0x380)
78485 -#define HDMI_CORE_AV_CEC_ADDR_ID 0x3FC
78486 -
78487 -#define HDMI_CORE_AV_SPD_DBYTE_ELSIZE 0x4
78488 -#define HDMI_CORE_AV_GEN2_DBYTE_ELSIZE 0x4
78489 -#define HDMI_CORE_AV_MPEG_DBYTE_ELSIZE 0x4
78490 -#define HDMI_CORE_AV_GEN_DBYTE_ELSIZE 0x4
78491 -
78492 -#define HDMI_CORE_AV_AVI_DBYTE_NELEMS 15
78493 -#define HDMI_CORE_AV_SPD_DBYTE_NELEMS 27
78494 -#define HDMI_CORE_AV_AUD_DBYTE_NELEMS 10
78495 -#define HDMI_CORE_AV_MPEG_DBYTE_NELEMS 27
78496 -#define HDMI_CORE_AV_GEN_DBYTE_NELEMS 31
78497 -#define HDMI_CORE_AV_GEN2_DBYTE_NELEMS 31
78498 -
78499 -/* PLL */
78500 -
78501 -#define PLLCTRL_PLL_CONTROL 0x0
78502 -#define PLLCTRL_PLL_STATUS 0x4
78503 -#define PLLCTRL_PLL_GO 0x8
78504 -#define PLLCTRL_CFG1 0xC
78505 -#define PLLCTRL_CFG2 0x10
78506 -#define PLLCTRL_CFG3 0x14
78507 -#define PLLCTRL_CFG4 0x20
78508 -
78509 -/* HDMI PHY */
78510 -
78511 -#define HDMI_TXPHY_TX_CTRL 0x0
78512 -#define HDMI_TXPHY_DIGITAL_CTRL 0x4
78513 -#define HDMI_TXPHY_POWER_CTRL 0x8
78514 -#define HDMI_TXPHY_PAD_CFG_CTRL 0xC
78515 -
78516 -#define REG_FLD_MOD(base, idx, val, start, end) \
78517 - hdmi_write_reg(base, idx, FLD_MOD(hdmi_read_reg(base, idx),\
78518 - val, start, end))
78519 -#define REG_GET(base, idx, start, end) \
78520 - FLD_GET(hdmi_read_reg(base, idx), start, end)
78521 -
78522 -enum hdmi_phy_pwr {
78523 - HDMI_PHYPWRCMD_OFF = 0,
78524 - HDMI_PHYPWRCMD_LDOON = 1,
78525 - HDMI_PHYPWRCMD_TXON = 2
78526 -};
78527 -
78528 -enum hdmi_core_inputbus_width {
78529 - HDMI_INPUT_8BIT = 0,
78530 - HDMI_INPUT_10BIT = 1,
78531 - HDMI_INPUT_12BIT = 2
78532 -};
78533 -
78534 -enum hdmi_core_dither_trunc {
78535 - HDMI_OUTPUTTRUNCATION_8BIT = 0,
78536 - HDMI_OUTPUTTRUNCATION_10BIT = 1,
78537 - HDMI_OUTPUTTRUNCATION_12BIT = 2,
78538 - HDMI_OUTPUTDITHER_8BIT = 3,
78539 - HDMI_OUTPUTDITHER_10BIT = 4,
78540 - HDMI_OUTPUTDITHER_12BIT = 5
78541 -};
78542 -
78543 -enum hdmi_core_deepcolor_ed {
78544 - HDMI_DEEPCOLORPACKECTDISABLE = 0,
78545 - HDMI_DEEPCOLORPACKECTENABLE = 1
78546 -};
78547 -
78548 -enum hdmi_core_packet_mode {
78549 - HDMI_PACKETMODERESERVEDVALUE = 0,
78550 - HDMI_PACKETMODE24BITPERPIXEL = 4,
78551 - HDMI_PACKETMODE30BITPERPIXEL = 5,
78552 - HDMI_PACKETMODE36BITPERPIXEL = 6,
78553 - HDMI_PACKETMODE48BITPERPIXEL = 7
78554 -};
78555 -
78556 -enum hdmi_core_tclkselclkmult {
78557 - HDMI_FPLL05IDCK = 0,
78558 - HDMI_FPLL10IDCK = 1,
78559 - HDMI_FPLL20IDCK = 2,
78560 - HDMI_FPLL40IDCK = 3
78561 -};
78562 -
78563 -enum hdmi_core_packet_ctrl {
78564 - HDMI_PACKETENABLE = 1,
78565 - HDMI_PACKETDISABLE = 0,
78566 - HDMI_PACKETREPEATON = 1,
78567 - HDMI_PACKETREPEATOFF = 0
78568 -};
78569 -
78570 -/* INFOFRAME_AVI_ and INFOFRAME_AUDIO_ definitions */
78571 -enum hdmi_core_infoframe {
78572 - HDMI_INFOFRAME_AVI_DB1Y_RGB = 0,
78573 - HDMI_INFOFRAME_AVI_DB1Y_YUV422 = 1,
78574 - HDMI_INFOFRAME_AVI_DB1Y_YUV444 = 2,
78575 - HDMI_INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_OFF = 0,
78576 - HDMI_INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_ON = 1,
78577 - HDMI_INFOFRAME_AVI_DB1B_NO = 0,
78578 - HDMI_INFOFRAME_AVI_DB1B_VERT = 1,
78579 - HDMI_INFOFRAME_AVI_DB1B_HORI = 2,
78580 - HDMI_INFOFRAME_AVI_DB1B_VERTHORI = 3,
78581 - HDMI_INFOFRAME_AVI_DB1S_0 = 0,
78582 - HDMI_INFOFRAME_AVI_DB1S_1 = 1,
78583 - HDMI_INFOFRAME_AVI_DB1S_2 = 2,
78584 - HDMI_INFOFRAME_AVI_DB2C_NO = 0,
78585 - HDMI_INFOFRAME_AVI_DB2C_ITU601 = 1,
78586 - HDMI_INFOFRAME_AVI_DB2C_ITU709 = 2,
78587 - HDMI_INFOFRAME_AVI_DB2C_EC_EXTENDED = 3,
78588 - HDMI_INFOFRAME_AVI_DB2M_NO = 0,
78589 - HDMI_INFOFRAME_AVI_DB2M_43 = 1,
78590 - HDMI_INFOFRAME_AVI_DB2M_169 = 2,
78591 - HDMI_INFOFRAME_AVI_DB2R_SAME = 8,
78592 - HDMI_INFOFRAME_AVI_DB2R_43 = 9,
78593 - HDMI_INFOFRAME_AVI_DB2R_169 = 10,
78594 - HDMI_INFOFRAME_AVI_DB2R_149 = 11,
78595 - HDMI_INFOFRAME_AVI_DB3ITC_NO = 0,
78596 - HDMI_INFOFRAME_AVI_DB3ITC_YES = 1,
78597 - HDMI_INFOFRAME_AVI_DB3EC_XVYUV601 = 0,
78598 - HDMI_INFOFRAME_AVI_DB3EC_XVYUV709 = 1,
78599 - HDMI_INFOFRAME_AVI_DB3Q_DEFAULT = 0,
78600 - HDMI_INFOFRAME_AVI_DB3Q_LR = 1,
78601 - HDMI_INFOFRAME_AVI_DB3Q_FR = 2,
78602 - HDMI_INFOFRAME_AVI_DB3SC_NO = 0,
78603 - HDMI_INFOFRAME_AVI_DB3SC_HORI = 1,
78604 - HDMI_INFOFRAME_AVI_DB3SC_VERT = 2,
78605 - HDMI_INFOFRAME_AVI_DB3SC_HORIVERT = 3,
78606 - HDMI_INFOFRAME_AVI_DB5PR_NO = 0,
78607 - HDMI_INFOFRAME_AVI_DB5PR_2 = 1,
78608 - HDMI_INFOFRAME_AVI_DB5PR_3 = 2,
78609 - HDMI_INFOFRAME_AVI_DB5PR_4 = 3,
78610 - HDMI_INFOFRAME_AVI_DB5PR_5 = 4,
78611 - HDMI_INFOFRAME_AVI_DB5PR_6 = 5,
78612 - HDMI_INFOFRAME_AVI_DB5PR_7 = 6,
78613 - HDMI_INFOFRAME_AVI_DB5PR_8 = 7,
78614 - HDMI_INFOFRAME_AVI_DB5PR_9 = 8,
78615 - HDMI_INFOFRAME_AVI_DB5PR_10 = 9,
78616 -};
78617 -
78618 -enum hdmi_packing_mode {
78619 - HDMI_PACK_10b_RGB_YUV444 = 0,
78620 - HDMI_PACK_24b_RGB_YUV444_YUV422 = 1,
78621 - HDMI_PACK_20b_YUV422 = 2,
78622 - HDMI_PACK_ALREADYPACKED = 7
78623 -};
78624 -
78625 -enum hdmi_core_audio_layout {
78626 - HDMI_AUDIO_LAYOUT_2CH = 0,
78627 - HDMI_AUDIO_LAYOUT_8CH = 1
78628 -};
78629 -
78630 -enum hdmi_core_cts_mode {
78631 - HDMI_AUDIO_CTS_MODE_HW = 0,
78632 - HDMI_AUDIO_CTS_MODE_SW = 1
78633 -};
78634 -
78635 -enum hdmi_stereo_channels {
78636 - HDMI_AUDIO_STEREO_NOCHANNELS = 0,
78637 - HDMI_AUDIO_STEREO_ONECHANNEL = 1,
78638 - HDMI_AUDIO_STEREO_TWOCHANNELS = 2,
78639 - HDMI_AUDIO_STEREO_THREECHANNELS = 3,
78640 - HDMI_AUDIO_STEREO_FOURCHANNELS = 4
78641 -};
78642 -
78643 -enum hdmi_audio_type {
78644 - HDMI_AUDIO_TYPE_LPCM = 0,
78645 - HDMI_AUDIO_TYPE_IEC = 1
78646 -};
78647 -
78648 -enum hdmi_audio_justify {
78649 - HDMI_AUDIO_JUSTIFY_LEFT = 0,
78650 - HDMI_AUDIO_JUSTIFY_RIGHT = 1
78651 -};
78652 -
78653 -enum hdmi_audio_sample_order {
78654 - HDMI_AUDIO_SAMPLE_RIGHT_FIRST = 0,
78655 - HDMI_AUDIO_SAMPLE_LEFT_FIRST = 1
78656 -};
78657 -
78658 -enum hdmi_audio_samples_perword {
78659 - HDMI_AUDIO_ONEWORD_ONESAMPLE = 0,
78660 - HDMI_AUDIO_ONEWORD_TWOSAMPLES = 1
78661 -};
78662 -
78663 -enum hdmi_audio_sample_size {
78664 - HDMI_AUDIO_SAMPLE_16BITS = 0,
78665 - HDMI_AUDIO_SAMPLE_24BITS = 1
78666 -};
78667 -
78668 -enum hdmi_audio_transf_mode {
78669 - HDMI_AUDIO_TRANSF_DMA = 0,
78670 - HDMI_AUDIO_TRANSF_IRQ = 1
78671 -};
78672 -
78673 -enum hdmi_audio_blk_strt_end_sig {
78674 - HDMI_AUDIO_BLOCK_SIG_STARTEND_ON = 0,
78675 - HDMI_AUDIO_BLOCK_SIG_STARTEND_OFF = 1
78676 -};
78677 -
78678 -enum hdmi_audio_i2s_config {
78679 - HDMI_AUDIO_I2S_MSB_SHIFTED_FIRST = 0,
78680 - HDMI_AUDIO_I2S_LSB_SHIFTED_FIRST = 1,
78681 - HDMI_AUDIO_I2S_SCK_EDGE_FALLING = 0,
78682 - HDMI_AUDIO_I2S_SCK_EDGE_RISING = 1,
78683 - HDMI_AUDIO_I2S_VBIT_FOR_PCM = 0,
78684 - HDMI_AUDIO_I2S_VBIT_FOR_COMPRESSED = 1,
78685 - HDMI_AUDIO_I2S_FIRST_BIT_SHIFT = 0,
78686 - HDMI_AUDIO_I2S_FIRST_BIT_NO_SHIFT = 1,
78687 - HDMI_AUDIO_I2S_SD0_EN = 1,
78688 - HDMI_AUDIO_I2S_SD1_EN = 1 << 1,
78689 - HDMI_AUDIO_I2S_SD2_EN = 1 << 2,
78690 - HDMI_AUDIO_I2S_SD3_EN = 1 << 3,
78691 -};
78692 -
78693 -enum hdmi_audio_mclk_mode {
78694 - HDMI_AUDIO_MCLK_128FS = 0,
78695 - HDMI_AUDIO_MCLK_256FS = 1,
78696 - HDMI_AUDIO_MCLK_384FS = 2,
78697 - HDMI_AUDIO_MCLK_512FS = 3,
78698 - HDMI_AUDIO_MCLK_768FS = 4,
78699 - HDMI_AUDIO_MCLK_1024FS = 5,
78700 - HDMI_AUDIO_MCLK_1152FS = 6,
78701 - HDMI_AUDIO_MCLK_192FS = 7
78702 -};
78703 -
78704 -struct hdmi_core_video_config {
78705 - enum hdmi_core_inputbus_width ip_bus_width;
78706 - enum hdmi_core_dither_trunc op_dither_truc;
78707 - enum hdmi_core_deepcolor_ed deep_color_pkt;
78708 - enum hdmi_core_packet_mode pkt_mode;
78709 - enum hdmi_core_hdmi_dvi hdmi_dvi;
78710 - enum hdmi_core_tclkselclkmult tclk_sel_clkmult;
78711 -};
78712 -
78713 -struct hdmi_core_packet_enable_repeat {
78714 - u32 audio_pkt;
78715 - u32 audio_pkt_repeat;
78716 - u32 avi_infoframe;
78717 - u32 avi_infoframe_repeat;
78718 - u32 gen_cntrl_pkt;
78719 - u32 gen_cntrl_pkt_repeat;
78720 - u32 generic_pkt;
78721 - u32 generic_pkt_repeat;
78722 -};
78723 -
78724 -struct hdmi_video_format {
78725 - enum hdmi_packing_mode packing_mode;
78726 - u32 y_res; /* Line per panel */
78727 - u32 x_res; /* pixel per line */
78728 -};
78729 -
78730 -struct hdmi_audio_format {
78731 - enum hdmi_stereo_channels stereo_channels;
78732 - u8 active_chnnls_msk;
78733 - enum hdmi_audio_type type;
78734 - enum hdmi_audio_justify justification;
78735 - enum hdmi_audio_sample_order sample_order;
78736 - enum hdmi_audio_samples_perword samples_per_word;
78737 - enum hdmi_audio_sample_size sample_size;
78738 - enum hdmi_audio_blk_strt_end_sig en_sig_blk_strt_end;
78739 -};
78740 -
78741 -struct hdmi_audio_dma {
78742 - u8 transfer_size;
78743 - u8 block_size;
78744 - enum hdmi_audio_transf_mode mode;
78745 - u16 fifo_threshold;
78746 -};
78747 -
78748 -struct hdmi_core_audio_i2s_config {
78749 - u8 in_length_bits;
78750 - u8 justification;
78751 - u8 sck_edge_mode;
78752 - u8 vbit;
78753 - u8 direction;
78754 - u8 shift;
78755 - u8 active_sds;
78756 -};
78757 -
78758 -struct hdmi_core_audio_config {
78759 - struct hdmi_core_audio_i2s_config i2s_cfg;
78760 - struct snd_aes_iec958 *iec60958_cfg;
78761 - bool fs_override;
78762 - u32 n;
78763 - u32 cts;
78764 - u32 aud_par_busclk;
78765 - enum hdmi_core_audio_layout layout;
78766 - enum hdmi_core_cts_mode cts_mode;
78767 - bool use_mclk;
78768 - enum hdmi_audio_mclk_mode mclk_mode;
78769 - bool en_acr_pkt;
78770 - bool en_dsd_audio;
78771 - bool en_parallel_aud_input;
78772 - bool en_spdif;
78773 -};
78774 -
78775 -#endif
78776 --- a/drivers/video/omap2/dss/ti_hdmi.h
78777 +++ /dev/null
78778 @@ -1,187 +0,0 @@
78779 -/*
78780 - * ti_hdmi.h
78781 - *
78782 - * HDMI driver definition for TI OMAP4, DM81xx, DM38xx Processor.
78783 - *
78784 - * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
78785 - *
78786 - * This program is free software; you can redistribute it and/or modify it
78787 - * under the terms of the GNU General Public License version 2 as published by
78788 - * the Free Software Foundation.
78789 - *
78790 - * This program is distributed in the hope that it will be useful, but WITHOUT
78791 - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
78792 - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
78793 - * more details.
78794 - *
78795 - * You should have received a copy of the GNU General Public License along with
78796 - * this program. If not, see <http://www.gnu.org/licenses/>.
78797 - */
78798 -
78799 -#ifndef _TI_HDMI_H
78800 -#define _TI_HDMI_H
78801 -
78802 -struct hdmi_ip_data;
78803 -
78804 -enum hdmi_pll_pwr {
78805 - HDMI_PLLPWRCMD_ALLOFF = 0,
78806 - HDMI_PLLPWRCMD_PLLONLY = 1,
78807 - HDMI_PLLPWRCMD_BOTHON_ALLCLKS = 2,
78808 - HDMI_PLLPWRCMD_BOTHON_NOPHYCLK = 3
78809 -};
78810 -
78811 -enum hdmi_core_hdmi_dvi {
78812 - HDMI_DVI = 0,
78813 - HDMI_HDMI = 1
78814 -};
78815 -
78816 -enum hdmi_clk_refsel {
78817 - HDMI_REFSEL_PCLK = 0,
78818 - HDMI_REFSEL_REF1 = 1,
78819 - HDMI_REFSEL_REF2 = 2,
78820 - HDMI_REFSEL_SYSCLK = 3
78821 -};
78822 -
78823 -struct hdmi_cm {
78824 - int code;
78825 - int mode;
78826 -};
78827 -
78828 -struct hdmi_config {
78829 - struct omap_video_timings timings;
78830 - struct hdmi_cm cm;
78831 -};
78832 -
78833 -/* HDMI PLL structure */
78834 -struct hdmi_pll_info {
78835 - u16 regn;
78836 - u16 regm;
78837 - u32 regmf;
78838 - u16 regm2;
78839 - u16 regsd;
78840 - u16 dcofreq;
78841 - enum hdmi_clk_refsel refsel;
78842 -};
78843 -
78844 -struct ti_hdmi_ip_ops {
78845 -
78846 - void (*video_configure)(struct hdmi_ip_data *ip_data);
78847 -
78848 - int (*phy_enable)(struct hdmi_ip_data *ip_data);
78849 -
78850 - void (*phy_disable)(struct hdmi_ip_data *ip_data);
78851 -
78852 - int (*read_edid)(struct hdmi_ip_data *ip_data, u8 *edid, int len);
78853 -
78854 - int (*pll_enable)(struct hdmi_ip_data *ip_data);
78855 -
78856 - void (*pll_disable)(struct hdmi_ip_data *ip_data);
78857 -
78858 - int (*video_enable)(struct hdmi_ip_data *ip_data);
78859 -
78860 - void (*video_disable)(struct hdmi_ip_data *ip_data);
78861 -
78862 - void (*dump_wrapper)(struct hdmi_ip_data *ip_data, struct seq_file *s);
78863 -
78864 - void (*dump_core)(struct hdmi_ip_data *ip_data, struct seq_file *s);
78865 -
78866 - void (*dump_pll)(struct hdmi_ip_data *ip_data, struct seq_file *s);
78867 -
78868 - void (*dump_phy)(struct hdmi_ip_data *ip_data, struct seq_file *s);
78869 -
78870 -#if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO)
78871 - int (*audio_enable)(struct hdmi_ip_data *ip_data);
78872 -
78873 - void (*audio_disable)(struct hdmi_ip_data *ip_data);
78874 -
78875 - int (*audio_start)(struct hdmi_ip_data *ip_data);
78876 -
78877 - void (*audio_stop)(struct hdmi_ip_data *ip_data);
78878 -
78879 - int (*audio_config)(struct hdmi_ip_data *ip_data,
78880 - struct omap_dss_audio *audio);
78881 -
78882 - int (*audio_get_dma_port)(u32 *offset, u32 *size);
78883 -#endif
78884 -
78885 -};
78886 -
78887 -/*
78888 - * Refer to section 8.2 in HDMI 1.3 specification for
78889 - * details about infoframe databytes
78890 - */
78891 -struct hdmi_core_infoframe_avi {
78892 - /* Y0, Y1 rgb,yCbCr */
78893 - u8 db1_format;
78894 - /* A0 Active information Present */
78895 - u8 db1_active_info;
78896 - /* B0, B1 Bar info data valid */
78897 - u8 db1_bar_info_dv;
78898 - /* S0, S1 scan information */
78899 - u8 db1_scan_info;
78900 - /* C0, C1 colorimetry */
78901 - u8 db2_colorimetry;
78902 - /* M0, M1 Aspect ratio (4:3, 16:9) */
78903 - u8 db2_aspect_ratio;
78904 - /* R0...R3 Active format aspect ratio */
78905 - u8 db2_active_fmt_ar;
78906 - /* ITC IT content. */
78907 - u8 db3_itc;
78908 - /* EC0, EC1, EC2 Extended colorimetry */
78909 - u8 db3_ec;
78910 - /* Q1, Q0 Quantization range */
78911 - u8 db3_q_range;
78912 - /* SC1, SC0 Non-uniform picture scaling */
78913 - u8 db3_nup_scaling;
78914 - /* VIC0..6 Video format identification */
78915 - u8 db4_videocode;
78916 - /* PR0..PR3 Pixel repetition factor */
78917 - u8 db5_pixel_repeat;
78918 - /* Line number end of top bar */
78919 - u16 db6_7_line_eoftop;
78920 - /* Line number start of bottom bar */
78921 - u16 db8_9_line_sofbottom;
78922 - /* Pixel number end of left bar */
78923 - u16 db10_11_pixel_eofleft;
78924 - /* Pixel number start of right bar */
78925 - u16 db12_13_pixel_sofright;
78926 -};
78927 -
78928 -struct hdmi_ip_data {
78929 - void __iomem *base_wp; /* HDMI wrapper */
78930 - unsigned long core_sys_offset;
78931 - unsigned long core_av_offset;
78932 - unsigned long pll_offset;
78933 - unsigned long phy_offset;
78934 - int irq;
78935 - const struct ti_hdmi_ip_ops *ops;
78936 - struct hdmi_config cfg;
78937 - struct hdmi_pll_info pll_data;
78938 - struct hdmi_core_infoframe_avi avi_cfg;
78939 -
78940 - /* ti_hdmi_4xxx_ip private data. These should be in a separate struct */
78941 - struct mutex lock;
78942 -};
78943 -int ti_hdmi_4xxx_phy_enable(struct hdmi_ip_data *ip_data);
78944 -void ti_hdmi_4xxx_phy_disable(struct hdmi_ip_data *ip_data);
78945 -int ti_hdmi_4xxx_read_edid(struct hdmi_ip_data *ip_data, u8 *edid, int len);
78946 -int ti_hdmi_4xxx_wp_video_start(struct hdmi_ip_data *ip_data);
78947 -void ti_hdmi_4xxx_wp_video_stop(struct hdmi_ip_data *ip_data);
78948 -int ti_hdmi_4xxx_pll_enable(struct hdmi_ip_data *ip_data);
78949 -void ti_hdmi_4xxx_pll_disable(struct hdmi_ip_data *ip_data);
78950 -void ti_hdmi_4xxx_basic_configure(struct hdmi_ip_data *ip_data);
78951 -void ti_hdmi_4xxx_wp_dump(struct hdmi_ip_data *ip_data, struct seq_file *s);
78952 -void ti_hdmi_4xxx_pll_dump(struct hdmi_ip_data *ip_data, struct seq_file *s);
78953 -void ti_hdmi_4xxx_core_dump(struct hdmi_ip_data *ip_data, struct seq_file *s);
78954 -void ti_hdmi_4xxx_phy_dump(struct hdmi_ip_data *ip_data, struct seq_file *s);
78955 -#if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO)
78956 -int hdmi_compute_acr(u32 sample_freq, u32 *n, u32 *cts);
78957 -int ti_hdmi_4xxx_wp_audio_enable(struct hdmi_ip_data *ip_data);
78958 -void ti_hdmi_4xxx_wp_audio_disable(struct hdmi_ip_data *ip_data);
78959 -int ti_hdmi_4xxx_audio_start(struct hdmi_ip_data *ip_data);
78960 -void ti_hdmi_4xxx_audio_stop(struct hdmi_ip_data *ip_data);
78961 -int ti_hdmi_4xxx_audio_config(struct hdmi_ip_data *ip_data,
78962 - struct omap_dss_audio *audio);
78963 -int ti_hdmi_4xxx_audio_get_dma_port(u32 *offset, u32 *size);
78964 -#endif
78965 -#endif
78966 --- a/drivers/video/omap2/dss/venc.c
78967 +++ b/drivers/video/omap2/dss/venc.c
78968 @@ -894,6 +894,12 @@ static const struct dev_pm_ops venc_pm_o
78969 .runtime_resume = venc_runtime_resume,
78970 };
78971
78972 +
78973 +static const struct of_device_id venc_of_match[] = {
78974 + { .compatible = "ti,omap3-venc", },
78975 + {},
78976 +};
78977 +
78978 static struct platform_driver omap_venchw_driver = {
78979 .probe = omap_venchw_probe,
78980 .remove = __exit_p(omap_venchw_remove),
78981 @@ -901,6 +907,7 @@ static struct platform_driver omap_vench
78982 .name = "omapdss_venc",
78983 .owner = THIS_MODULE,
78984 .pm = &venc_pm_ops,
78985 + .of_match_table = venc_of_match,
78986 },
78987 };
78988
78989 --- a/drivers/video/omap2/omapfb/omapfb-main.c
78990 +++ b/drivers/video/omap2/omapfb/omapfb-main.c
78991 @@ -2407,6 +2407,55 @@ static int omapfb_init_connections(struc
78992 return 0;
78993 }
78994
78995 +static struct omap_dss_device *
78996 +omapfb_find_default_display(struct omapfb2_device *fbdev)
78997 +{
78998 + const char *def_name;
78999 + int i;
79000 +
79001 + /*
79002 + * Search with the display name from the user or the board file,
79003 + * comparing to display names and aliases
79004 + */
79005 +
79006 + def_name = omapdss_get_default_display_name();
79007 +
79008 + if (def_name) {
79009 + for (i = 0; i < fbdev->num_displays; ++i) {
79010 + struct omap_dss_device *dssdev;
79011 +
79012 + dssdev = fbdev->displays[i].dssdev;
79013 +
79014 + if (dssdev->name && strcmp(def_name, dssdev->name) == 0)
79015 + return dssdev;
79016 +
79017 + if (strcmp(def_name, dssdev->alias) == 0)
79018 + return dssdev;
79019 + }
79020 +
79021 + /* def_name given but not found */
79022 + return NULL;
79023 + }
79024 +
79025 + /* then look for DT alias display0 */
79026 + for (i = 0; i < fbdev->num_displays; ++i) {
79027 + struct omap_dss_device *dssdev;
79028 + int id;
79029 +
79030 + dssdev = fbdev->displays[i].dssdev;
79031 +
79032 + if (dssdev->dev->of_node == NULL)
79033 + continue;
79034 +
79035 + id = of_alias_get_id(dssdev->dev->of_node, "display");
79036 + if (id == 0)
79037 + return dssdev;
79038 + }
79039 +
79040 + /* return the first display we have in the list */
79041 + return fbdev->displays[0].dssdev;
79042 +}
79043 +
79044 static int omapfb_probe(struct platform_device *pdev)
79045 {
79046 struct omapfb2_device *fbdev = NULL;
79047 @@ -2484,23 +2533,7 @@ static int omapfb_probe(struct platform_
79048 for (i = 0; i < fbdev->num_managers; i++)
79049 fbdev->managers[i] = omap_dss_get_overlay_manager(i);
79050
79051 - def_display = NULL;
79052 -
79053 - for (i = 0; i < fbdev->num_displays; ++i) {
79054 - struct omap_dss_device *dssdev;
79055 - const char *def_name;
79056 -
79057 - def_name = omapdss_get_default_display_name();
79058 -
79059 - dssdev = fbdev->displays[i].dssdev;
79060 -
79061 - if (def_name == NULL ||
79062 - (dssdev->name && strcmp(def_name, dssdev->name) == 0)) {
79063 - def_display = dssdev;
79064 - break;
79065 - }
79066 - }
79067 -
79068 + def_display = omapfb_find_default_display(fbdev);
79069 if (def_display == NULL) {
79070 dev_err(fbdev->dev, "failed to find default display\n");
79071 r = -EPROBE_DEFER;
79072 --- a/drivers/watchdog/omap_wdt.c
79073 +++ b/drivers/watchdog/omap_wdt.c
79074 @@ -41,7 +41,9 @@
79075 #include <linux/io.h>
79076 #include <linux/slab.h>
79077 #include <linux/pm_runtime.h>
79078 +#include <linux/interrupt.h>
79079 #include <linux/platform_data/omap-wd-timer.h>
79080 +#include <linux/of.h>
79081
79082 #include "omap_wdt.h"
79083
79084 @@ -54,6 +56,10 @@ static unsigned timer_margin;
79085 module_param(timer_margin, uint, 0);
79086 MODULE_PARM_DESC(timer_margin, "initial watchdog timeout (in seconds)");
79087
79088 +static int kernelpet = 1;
79089 +module_param(kernelpet, int, 0);
79090 +MODULE_PARM_DESC(kernelpet, "pet watchdog in kernel via irq");
79091 +
79092 struct omap_wdt_dev {
79093 void __iomem *base; /* physical */
79094 struct device *dev;
79095 @@ -112,6 +118,7 @@ static void omap_wdt_set_timer(struct om
79096 unsigned int timeout)
79097 {
79098 u32 pre_margin = GET_WLDR_VAL(timeout);
79099 + u32 delay_period = GET_WLDR_VAL(timeout / 2);
79100 void __iomem *base = wdev->base;
79101
79102 /* just count up at 32 KHz */
79103 @@ -121,6 +128,26 @@ static void omap_wdt_set_timer(struct om
79104 __raw_writel(pre_margin, base + OMAP_WATCHDOG_LDR);
79105 while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x04)
79106 cpu_relax();
79107 +
79108 + /* Set delay interrupt to half the watchdog interval. */
79109 + while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 1 << 5)
79110 + cpu_relax();
79111 + __raw_writel(delay_period, base + OMAP_WATCHDOG_WDLY);
79112 +}
79113 +
79114 +static irqreturn_t omap_wdt_interrupt(int irq, void *dev_id)
79115 +{
79116 + struct watchdog_device *wdog = dev_id;
79117 + struct omap_wdt_dev *wdev = watchdog_get_drvdata(wdog);
79118 + void __iomem *base = wdev->base;
79119 + u32 i;
79120 +
79121 + i = __raw_readl(base + OMAP_WATCHDOG_WIRQSTAT);
79122 + __raw_writel(i, base + OMAP_WATCHDOG_WIRQSTAT);
79123 +
79124 + omap_wdt_reload(wdev);
79125 +
79126 + return IRQ_HANDLED;
79127 }
79128
79129 static int omap_wdt_start(struct watchdog_device *wdog)
79130 @@ -144,6 +171,13 @@ static int omap_wdt_start(struct watchdo
79131
79132 omap_wdt_set_timer(wdev, wdog->timeout);
79133 omap_wdt_reload(wdev); /* trigger loading of new timeout value */
79134 +
79135 + /* Enable delay interrupt */
79136 + if (kernelpet) {
79137 + __raw_writel(0x2, base + OMAP_WATCHDOG_WIRQENSET);
79138 + __raw_writel(0x2, base + OMAP_WATCHDOG_WIRQWAKEEN);
79139 + }
79140 +
79141 omap_wdt_enable(wdev);
79142
79143 mutex_unlock(&wdev->lock);
79144 @@ -154,9 +188,16 @@ static int omap_wdt_start(struct watchdo
79145 static int omap_wdt_stop(struct watchdog_device *wdog)
79146 {
79147 struct omap_wdt_dev *wdev = watchdog_get_drvdata(wdog);
79148 + void __iomem *base = wdev->base;
79149
79150 mutex_lock(&wdev->lock);
79151 omap_wdt_disable(wdev);
79152 + /* Disable delay interrupt */
79153 + if (kernelpet) {
79154 + __raw_writel(0x0, base + OMAP_WATCHDOG_WIRQWAKEEN);
79155 + __raw_writel(0x2, base + OMAP_WATCHDOG_WIRQENCLR);
79156 + }
79157 +
79158 pm_runtime_put_sync(wdev->dev);
79159 wdev->omap_wdt_users = false;
79160 mutex_unlock(&wdev->lock);
79161 @@ -167,6 +208,11 @@ static int omap_wdt_ping(struct watchdog
79162 {
79163 struct omap_wdt_dev *wdev = watchdog_get_drvdata(wdog);
79164
79165 + if (kernelpet) {
79166 + pr_info("Hw ping is enabled,Skipping userspace ping\n");
79167 + return 0;
79168 + }
79169 +
79170 mutex_lock(&wdev->lock);
79171 omap_wdt_reload(wdev);
79172 mutex_unlock(&wdev->lock);
79173 @@ -210,7 +256,7 @@ static int omap_wdt_probe(struct platfor
79174 struct resource *res, *mem;
79175 struct omap_wdt_dev *wdev;
79176 u32 rs;
79177 - int ret;
79178 + int ret, irq;
79179
79180 omap_wdt = devm_kzalloc(&pdev->dev, sizeof(*omap_wdt), GFP_KERNEL);
79181 if (!omap_wdt)
79182 @@ -240,6 +286,23 @@ static int omap_wdt_probe(struct platfor
79183 if (!wdev->base)
79184 return -ENOMEM;
79185
79186 + if (pdev->dev.of_node) {
79187 + if (of_device_is_compatible(pdev->dev.of_node, "ti,omap3-wdt"))
79188 + kernelpet = 0;
79189 + } else {
79190 + if (pdata->ip_rev == WDTIMER2_IP3)
79191 + kernelpet = 0;
79192 + }
79193 +
79194 + if (kernelpet) {
79195 + irq = platform_get_irq(pdev, 0);
79196 + ret = devm_request_irq(&pdev->dev, irq, omap_wdt_interrupt, 0,
79197 + dev_name(&pdev->dev), omap_wdt);
79198 + if (ret < 0)
79199 + dev_err(&pdev->dev, "can't get irq %d, err %d\n",
79200 + irq, ret);
79201 + }
79202 +
79203 omap_wdt->info = &omap_wdt_info;
79204 omap_wdt->ops = &omap_wdt_ops;
79205 omap_wdt->min_timeout = TIMER_MARGIN_MIN;
79206 @@ -280,6 +343,12 @@ static int omap_wdt_probe(struct platfor
79207
79208 pm_runtime_put_sync(wdev->dev);
79209
79210 + if (kernelpet) {
79211 + ret = omap_wdt_start(omap_wdt);
79212 + if (ret == 0)
79213 + set_bit(WDOG_ACTIVE, &omap_wdt->status);
79214 + }
79215 +
79216 return 0;
79217 }
79218
79219 @@ -300,6 +369,13 @@ static int omap_wdt_remove(struct platfo
79220 {
79221 struct watchdog_device *wdog = platform_get_drvdata(pdev);
79222 struct omap_wdt_dev *wdev = watchdog_get_drvdata(wdog);
79223 + int ret;
79224 +
79225 + if (kernelpet) {
79226 + ret = omap_wdt_stop(wdog);
79227 + if (ret == 0)
79228 + clear_bit(WDOG_ACTIVE, &wdog->status);
79229 + }
79230
79231 pm_runtime_disable(wdev->dev);
79232 watchdog_unregister_device(wdog);
79233 @@ -352,7 +428,8 @@ static int omap_wdt_resume(struct platfo
79234 #endif
79235
79236 static const struct of_device_id omap_wdt_of_match[] = {
79237 - { .compatible = "ti,omap3-wdt", },
79238 + { .compatible = "ti,omap3-wdt" },
79239 + { .compatible = "ti,omap4-wdt" },
79240 {},
79241 };
79242 MODULE_DEVICE_TABLE(of, omap_wdt_of_match);
79243 --- a/drivers/watchdog/omap_wdt.h
79244 +++ b/drivers/watchdog/omap_wdt.h
79245 @@ -38,7 +38,12 @@
79246 #define OMAP_WATCHDOG_LDR (0x2c)
79247 #define OMAP_WATCHDOG_TGR (0x30)
79248 #define OMAP_WATCHDOG_WPS (0x34)
79249 +#define OMAP_WATCHDOG_WDLY (0x44)
79250 #define OMAP_WATCHDOG_SPR (0x48)
79251 +#define OMAP_WATCHDOG_WIRQSTAT (0x58)
79252 +#define OMAP_WATCHDOG_WIRQENSET (0x5c)
79253 +#define OMAP_WATCHDOG_WIRQENCLR (0x60)
79254 +#define OMAP_WATCHDOG_WIRQWAKEEN (0x64)
79255
79256 /* Using the prescaler, the OMAP watchdog could go for many
79257 * months before firing. These limits work without scaling,
79258 --- /dev/null
79259 +++ b/include/dt-bindings/mfd/palmas.h
79260 @@ -0,0 +1,18 @@
79261 +/*
79262 + * This header provides macros for Palmas device bindings.
79263 + *
79264 + * Copyright (c) 2013, NVIDIA Corporation.
79265 + *
79266 + * Author: Laxman Dewangan <ldewangan@nvidia.com>
79267 + *
79268 + */
79269 +
79270 +#ifndef __DT_BINDINGS_PALMAS_H__
79271 +#define __DT_BINDINGS_PALMAS_H
79272 +
79273 +/* External control pins */
79274 +#define PALMAS_EXT_CONTROL_PIN_ENABLE1 1
79275 +#define PALMAS_EXT_CONTROL_PIN_ENABLE2 2
79276 +#define PALMAS_EXT_CONTROL_PIN_NSLEEP 3
79277 +
79278 +#endif /* __DT_BINDINGS_PALMAS_H */
79279 --- /dev/null
79280 +++ b/include/dt-bindings/pinctrl/am43xx.h
79281 @@ -0,0 +1,30 @@
79282 +/*
79283 + * This header provides constants specific to AM43XX pinctrl bindings.
79284 + */
79285 +
79286 +#ifndef _DT_BINDINGS_PINCTRL_AM43XX_H
79287 +#define _DT_BINDINGS_PINCTRL_AM43XX_H
79288 +
79289 +#define MUX_MODE0 0
79290 +#define MUX_MODE1 1
79291 +#define MUX_MODE2 2
79292 +#define MUX_MODE3 3
79293 +#define MUX_MODE4 4
79294 +#define MUX_MODE5 5
79295 +#define MUX_MODE6 6
79296 +#define MUX_MODE7 7
79297 +
79298 +#define PULL_DISABLE (1 << 16)
79299 +#define PULL_UP (1 << 17)
79300 +#define INPUT_EN (1 << 18)
79301 +#define SLEWCTRL_FAST (1 << 19)
79302 +#define DS0_PULL_UP_DOWN_EN (1 << 27)
79303 +
79304 +#define PIN_OUTPUT (PULL_DISABLE)
79305 +#define PIN_OUTPUT_PULLUP (PULL_UP)
79306 +#define PIN_OUTPUT_PULLDOWN 0
79307 +#define PIN_INPUT (INPUT_EN | PULL_DISABLE)
79308 +#define PIN_INPUT_PULLUP (INPUT_EN | PULL_UP)
79309 +#define PIN_INPUT_PULLDOWN (INPUT_EN)
79310 +
79311 +#endif
79312 --- /dev/null
79313 +++ b/include/dt-bindings/pinctrl/dra7xx.h
79314 @@ -0,0 +1,48 @@
79315 +/*
79316 + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
79317 + *
79318 + * This program is free software; you can redistribute it and/or modify
79319 + * it under the terms of the GNU General Public License version 2 as
79320 + * published by the Free Software Foundation.
79321 + */
79322 +/*
79323 + * This header provides constants specific to DRA7XX pinctrl bindings.
79324 + */
79325 +
79326 +#ifndef _DT_BINDINGS_PINCTRL_DRA7XX_H_
79327 +#define _DT_BINDINGS_PINCTRL_DRA7XX_H_
79328 +
79329 +/* dra7xx specific mux bit defines */
79330 +#define MUX_MODE0 0
79331 +#define MUX_MODE1 1
79332 +#define MUX_MODE2 2
79333 +#define MUX_MODE3 3
79334 +#define MUX_MODE4 4
79335 +#define MUX_MODE5 5
79336 +#define MUX_MODE6 6
79337 +#define MUX_MODE7 7
79338 +
79339 +#define PULL_ENA (1 << 16)
79340 +#define PULL_UP (1 << 17)
79341 +#define INPUT_EN (1 << 18)
79342 +#define SLEWCTRL_FAST (1 << 19)
79343 +#define WAKEUP_EN (1 << 24)
79344 +#define WAKEUP_EVENT (1 << 25)
79345 +
79346 +/* Active pin states */
79347 +#define PIN_OUTPUT 0
79348 +#define PIN_OUTPUT_PULLUP (PIN_OUTPUT | PULL_ENA | PULL_UP)
79349 +#define PIN_OUTPUT_PULLDOWN (PIN_OUTPUT | PULL_ENA)
79350 +#define PIN_INPUT INPUT_EN
79351 +#define PIN_INPUT_PULLUP (PULL_ENA | INPUT_EN | PULL_UP)
79352 +#define PIN_INPUT_PULLDOWN (PULL_ENA | INPUT_EN)
79353 +
79354 +/* Off mode states */
79355 +#define PIN_OFF_NONE 0
79356 +#define PIN_OFF_OUTPUT_HIGH (OFF_EN | OFFOUT_EN | OFFOUT_VAL)
79357 +#define PIN_OFF_OUTPUT_LOW (OFF_EN | OFFOUT_EN)
79358 +#define PIN_OFF_INPUT_PULLUP (OFF_EN | OFF_PULL_EN | OFF_PULL_UP)
79359 +#define PIN_OFF_INPUT_PULLDOWN (OFF_EN | OFF_PULL_EN)
79360 +#define PIN_OFF_WAKEUPENABLE WAKEUP_EN
79361 +
79362 +#endif
79363 --- /dev/null
79364 +++ b/include/linux/clk/ti.h
79365 @@ -0,0 +1,245 @@
79366 +/*
79367 + * TI clock drivers support
79368 + *
79369 + * Copyright (C) 2013 Texas Instruments, Inc.
79370 + *
79371 + * This program is free software; you can redistribute it and/or modify
79372 + * it under the terms of the GNU General Public License version 2 as
79373 + * published by the Free Software Foundation.
79374 + *
79375 + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
79376 + * kind, whether express or implied; without even the implied warranty
79377 + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
79378 + * GNU General Public License for more details.
79379 + */
79380 +#ifndef __LINUX_CLK_TI_H__
79381 +#define __LINUX_CLK_TI_H__
79382 +
79383 +#include <linux/clkdev.h>
79384 +
79385 +/**
79386 + * struct dpll_data - DPLL registers and integration data
79387 + * @mult_div1_reg: register containing the DPLL M and N bitfields
79388 + * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg
79389 + * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg
79390 + * @clk_bypass: struct clk pointer to the clock's bypass clock input
79391 + * @clk_ref: struct clk pointer to the clock's reference clock input
79392 + * @control_reg: register containing the DPLL mode bitfield
79393 + * @enable_mask: mask of the DPLL mode bitfield in @control_reg
79394 + * @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate()
79395 + * @last_rounded_m: cache of the last M result of omap2_dpll_round_rate()
79396 + * @last_rounded_m4xen: cache of the last M4X result of
79397 + * omap4_dpll_regm4xen_round_rate()
79398 + * @last_rounded_lpmode: cache of the last lpmode result of
79399 + * omap4_dpll_lpmode_recalc()
79400 + * @max_multiplier: maximum valid non-bypass multiplier value (actual)
79401 + * @last_rounded_n: cache of the last N result of omap2_dpll_round_rate()
79402 + * @min_divider: minimum valid non-bypass divider value (actual)
79403 + * @max_divider: maximum valid non-bypass divider value (actual)
79404 + * @modes: possible values of @enable_mask
79405 + * @autoidle_reg: register containing the DPLL autoidle mode bitfield
79406 + * @idlest_reg: register containing the DPLL idle status bitfield
79407 + * @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg
79408 + * @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg
79409 + * @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg
79410 + * @lpmode_mask: mask of the DPLL low-power mode bitfield in @control_reg
79411 + * @m4xen_mask: mask of the DPLL M4X multiplier bitfield in @control_reg
79412 + * @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg
79413 + * @recal_en_bit: bitshift of the PRM_IRQENABLE_* bit for recalibration IRQs
79414 + * @recal_st_bit: bitshift of the PRM_IRQSTATUS_* bit for recalibration IRQs
79415 + * @flags: DPLL type/features (see below)
79416 + *
79417 + * Possible values for @flags:
79418 + * DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs)
79419 + *
79420 + * @freqsel_mask is only used on the OMAP34xx family and AM35xx.
79421 + *
79422 + * XXX Some DPLLs have multiple bypass inputs, so it's not technically
79423 + * correct to only have one @clk_bypass pointer.
79424 + *
79425 + * XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m,
79426 + * @last_rounded_n) should be separated from the runtime-fixed fields
79427 + * and placed into a different structure, so that the runtime-fixed data
79428 + * can be placed into read-only space.
79429 + */
79430 +struct dpll_data {
79431 + void __iomem *mult_div1_reg;
79432 + u32 mult_mask;
79433 + u32 div1_mask;
79434 + struct clk *clk_bypass;
79435 + struct clk *clk_ref;
79436 + void __iomem *control_reg;
79437 + u32 enable_mask;
79438 + unsigned long last_rounded_rate;
79439 + u16 last_rounded_m;
79440 + u8 last_rounded_m4xen;
79441 + u8 last_rounded_lpmode;
79442 + u16 max_multiplier;
79443 + u8 last_rounded_n;
79444 + u8 min_divider;
79445 + u16 max_divider;
79446 + u8 modes;
79447 + void __iomem *autoidle_reg;
79448 + void __iomem *idlest_reg;
79449 + u32 autoidle_mask;
79450 + u32 freqsel_mask;
79451 + u32 idlest_mask;
79452 + u32 dco_mask;
79453 + u32 sddiv_mask;
79454 + u32 lpmode_mask;
79455 + u32 m4xen_mask;
79456 + u8 auto_recal_bit;
79457 + u8 recal_en_bit;
79458 + u8 recal_st_bit;
79459 + u8 flags;
79460 +};
79461 +
79462 +struct clk_hw_omap_ops;
79463 +
79464 +/**
79465 + * struct clk_hw_omap - OMAP struct clk
79466 + * @node: list_head connecting this clock into the full clock list
79467 + * @enable_reg: register to write to enable the clock (see @enable_bit)
79468 + * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg)
79469 + * @flags: see "struct clk.flags possibilities" above
79470 + * @clksel_reg: for clksel clks, register va containing src/divisor select
79471 + * @clksel_mask: bitmask in @clksel_reg for the src/divisor selector
79472 + * @clksel: for clksel clks, pointer to struct clksel for this clock
79473 + * @dpll_data: for DPLLs, pointer to struct dpll_data for this clock
79474 + * @clkdm_name: clockdomain name that this clock is contained in
79475 + * @clkdm: pointer to struct clockdomain, resolved from @clkdm_name at runtime
79476 + * @rate_offset: bitshift for rate selection bitfield (OMAP1 only)
79477 + * @src_offset: bitshift for source selection bitfield (OMAP1 only)
79478 + *
79479 + * XXX @rate_offset, @src_offset should probably be removed and OMAP1
79480 + * clock code converted to use clksel.
79481 + *
79482 + */
79483 +struct clk_hw_omap {
79484 + struct clk_hw hw;
79485 + struct list_head node;
79486 + unsigned long fixed_rate;
79487 + u8 fixed_div;
79488 + void __iomem *enable_reg;
79489 + u8 enable_bit;
79490 + u8 flags;
79491 + void __iomem *clksel_reg;
79492 + u32 clksel_mask;
79493 + const struct clksel *clksel;
79494 + struct dpll_data *dpll_data;
79495 + const char *clkdm_name;
79496 + struct clockdomain *clkdm;
79497 + const struct clk_hw_omap_ops *ops;
79498 +};
79499 +
79500 +/*
79501 + * struct clk_hw_omap.flags possibilities
79502 + *
79503 + * XXX document the rest of the clock flags here
79504 + *
79505 + * ENABLE_REG_32BIT: (OMAP1 only) clock control register must be accessed
79506 + * with 32bit ops, by default OMAP1 uses 16bit ops.
79507 + * CLOCK_IDLE_CONTROL: (OMAP1 only) clock has autoidle support.
79508 + * CLOCK_NO_IDLE_PARENT: (OMAP1 only) when clock is enabled, its parent
79509 + * clock is put to no-idle mode.
79510 + * ENABLE_ON_INIT: Clock is enabled on init.
79511 + * INVERT_ENABLE: By default, clock enable bit behavior is '1' enable, '0'
79512 + * disable. This inverts the behavior making '0' enable and '1' disable.
79513 + * CLOCK_CLKOUTX2: (OMAP4 only) DPLL CLKOUT and CLKOUTX2 GATE_CTRL
79514 + * bits share the same register. This flag allows the
79515 + * omap4_dpllmx*() code to determine which GATE_CTRL bit field
79516 + * should be used. This is a temporary solution - a better approach
79517 + * would be to associate clock type-specific data with the clock,
79518 + * similar to the struct dpll_data approach.
79519 + */
79520 +#define ENABLE_REG_32BIT (1 << 0) /* Use 32-bit access */
79521 +#define CLOCK_IDLE_CONTROL (1 << 1)
79522 +#define CLOCK_NO_IDLE_PARENT (1 << 2)
79523 +#define ENABLE_ON_INIT (1 << 3) /* Enable upon framework init */
79524 +#define INVERT_ENABLE (1 << 4) /* 0 enables, 1 disables */
79525 +#define CLOCK_CLKOUTX2 (1 << 5)
79526 +
79527 +/* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
79528 +#define DPLL_LOW_POWER_STOP 0x1
79529 +#define DPLL_LOW_POWER_BYPASS 0x5
79530 +#define DPLL_LOCKED 0x7
79531 +
79532 +/* DPLL Type and DCO Selection Flags */
79533 +#define DPLL_J_TYPE 0x1
79534 +
79535 +/**
79536 + * struct omap_dt_clk - OMAP DT clock alias declarations
79537 + * @lk: clock lookup definition
79538 + * @node_name: clock DT node to map to
79539 + */
79540 +struct omap_dt_clk {
79541 + struct clk_lookup lk;
79542 + char *node_name;
79543 +};
79544 +
79545 +#define DT_CLK(dev, con, name) \
79546 + { \
79547 + .lk = { \
79548 + .dev_id = dev, \
79549 + .con_id = con, \
79550 + }, \
79551 + .node_name = name, \
79552 + }
79553 +
79554 +#define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw)
79555 +
79556 +void omap2_init_clk_hw_omap_clocks(struct clk *clk);
79557 +int omap3_noncore_dpll_enable(struct clk_hw *hw);
79558 +void omap3_noncore_dpll_disable(struct clk_hw *hw);
79559 +int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
79560 + unsigned long parent_rate);
79561 +unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
79562 + unsigned long parent_rate);
79563 +long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
79564 + unsigned long target_rate,
79565 + unsigned long *parent_rate);
79566 +u8 omap2_init_dpll_parent(struct clk_hw *hw);
79567 +unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate);
79568 +long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
79569 + unsigned long *parent_rate);
79570 +void omap2_init_clk_clkdm(struct clk_hw *clk);
79571 +unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
79572 + unsigned long parent_rate);
79573 +int omap2_clkops_enable_clkdm(struct clk_hw *hw);
79574 +void omap2_clkops_disable_clkdm(struct clk_hw *hw);
79575 +int omap2_clk_disable_autoidle_all(void);
79576 +void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks);
79577 +int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate,
79578 + unsigned long parent_rate);
79579 +int omap2_dflt_clk_enable(struct clk_hw *hw);
79580 +void omap2_dflt_clk_disable(struct clk_hw *hw);
79581 +int omap2_dflt_clk_is_enabled(struct clk_hw *hw);
79582 +void omap3_clk_lock_dpll5(void);
79583 +
79584 +void omap_dt_clocks_register(struct omap_dt_clk *oclks);
79585 +#ifdef CONFIG_OF
79586 +void of_omap_clk_allow_autoidle_all(void);
79587 +void of_omap_clk_deny_autoidle_all(void);
79588 +#else
79589 +static inline void of_omap_clk_allow_autoidle_all(void) { }
79590 +static inline void of_omap_clk_deny_autoidle_all(void) { }
79591 +#endif
79592 +
79593 +int omap5xxx_clk_init(void);
79594 +int dra7xx_clk_init(void);
79595 +int am43xx_clk_init(void);
79596 +
79597 +extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;
79598 +extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
79599 +extern const struct clk_hw_omap_ops clkhwops_wait;
79600 +extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait;
79601 +extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait;
79602 +extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait;
79603 +
79604 +extern const struct clk_hw_omap_ops clkhwops_iclk_wait;
79605 +extern const struct clk_hw_omap_ops clkhwops_iclk;
79606 +extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait;
79607 +extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait;
79608 +extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait;
79609 +
79610 +#endif
79611 --- a/include/linux/clk-private.h
79612 +++ b/include/linux/clk-private.h
79613 @@ -122,7 +122,7 @@ struct clk {
79614 }, \
79615 .reg = _reg, \
79616 .shift = _shift, \
79617 - .width = _width, \
79618 + .mask = ((1 << _width) - 1), \
79619 .flags = _divider_flags, \
79620 .table = _table, \
79621 .lock = _lock, \
79622 --- a/include/linux/clk-provider.h
79623 +++ b/include/linux/clk-provider.h
79624 @@ -241,6 +241,8 @@ struct clk *clk_register_gate(struct dev
79625 void __iomem *reg, u8 bit_idx,
79626 u8 clk_gate_flags, spinlock_t *lock);
79627
79628 +void of_gate_clk_setup(struct device_node *node);
79629 +
79630 struct clk_div_table {
79631 unsigned int val;
79632 unsigned int div;
79633 @@ -280,7 +282,7 @@ struct clk_divider {
79634 struct clk_hw hw;
79635 void __iomem *reg;
79636 u8 shift;
79637 - u8 width;
79638 + u32 mask;
79639 u8 flags;
79640 const struct clk_div_table *table;
79641 spinlock_t *lock;
79642 @@ -302,6 +304,8 @@ struct clk *clk_register_divider_table(s
79643 u8 clk_divider_flags, const struct clk_div_table *table,
79644 spinlock_t *lock);
79645
79646 +void of_divider_clk_setup(struct device_node *node);
79647 +
79648 /**
79649 * struct clk_mux - multiplexer clock
79650 *
79651 @@ -351,7 +355,7 @@ struct clk *clk_register_mux_table(struc
79652 void __iomem *reg, u8 shift, u32 mask,
79653 u8 clk_mux_flags, u32 *table, spinlock_t *lock);
79654
79655 -void of_fixed_factor_clk_setup(struct device_node *node);
79656 +void of_mux_clk_setup(struct device_node *node);
79657
79658 /**
79659 * struct clk_fixed_factor - fixed multiplier and divider clock
79660 @@ -372,10 +376,13 @@ struct clk_fixed_factor {
79661 };
79662
79663 extern struct clk_ops clk_fixed_factor_ops;
79664 +
79665 struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
79666 const char *parent_name, unsigned long flags,
79667 unsigned int mult, unsigned int div);
79668
79669 +void of_fixed_factor_clk_setup(struct device_node *node);
79670 +
79671 /***
79672 * struct clk_composite - aggregate clock of mux, divider and gate clocks
79673 *
79674 @@ -472,6 +479,7 @@ void of_clk_del_provider(struct device_n
79675 struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec,
79676 void *data);
79677 struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data);
79678 +int of_clk_get_parent_count(struct device_node *np);
79679 const char *of_clk_get_parent_name(struct device_node *np, int index);
79680
79681 void of_clk_init(const struct of_device_id *matches);
79682 --- /dev/null
79683 +++ b/include/linux/crossbar.h
79684 @@ -0,0 +1,71 @@
79685 +/*
79686 + * IRQ/DMA CROSSBAR DRIVER
79687 + *
79688 + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
79689 + * Sricharan <r.sricharan@ti.com>
79690 + *
79691 + * This program is free software; you can redistribute it and/or modify
79692 + * it under the terms of the GNU General Public License as published by
79693 + * the Free Software Foundation; either version 2 of the License, or
79694 + * (at your option) any later version.
79695 + *
79696 + * This program is distributed in the hope that it will be useful,
79697 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
79698 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
79699 + * GNU General Public License for more details.
79700 + *
79701 + * You should have received a copy of the GNU General Public License
79702 + * along with this program; if not, write to the Free Software
79703 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
79704 + * USA
79705 + */
79706 +#include <linux/io.h>
79707 +#include <linux/of.h>
79708 +#include <linux/of_irq.h>
79709 +#include <linux/of_address.h>
79710 +#include <linux/list.h>
79711 +#include <linux/err.h>
79712 +#include <linux/gfp.h>
79713 +#include <linux/platform_device.h>
79714 +
79715 +/*
79716 + * @base: base address of the crossbar device
79717 + * @dev: device ptr
79718 + * @name: name of the crossbar device
79719 + * @node: list node for the crossbar devices linked list
79720 + * @cb_entries: list of entries that belong to the crossbar
79721 + * @cb_lock: mutex
79722 + * @regmap pointer
79723 + */
79724 +struct cb_device {
79725 + void __iomem *base;
79726 + struct device *dev;
79727 + const char *name;
79728 + struct list_head node;
79729 + struct list_head cb_entries;
79730 + struct mutex cb_lock;
79731 + struct regmap *cb_regmap;
79732 +};
79733 +
79734 +/*
79735 + * @cb_name: name of crossbar target to which this line is mapped
79736 + * @dev_name: mapped device input request name
79737 + * @cb_no: crossbar device input number
79738 + * @int_no: request number to which this input should be routed
79739 + * @offset: register offset address
79740 + */
79741 +struct cb_line {
79742 + const char *cb_name;
79743 + const char *dev_name;
79744 + unsigned cb_no;
79745 + unsigned int_no;
79746 + unsigned offset;
79747 +};
79748 +
79749 +struct cb_entry {
79750 + struct cb_line line;
79751 + struct list_head cb_list;
79752 +};
79753 +
79754 +int crossbar_map(struct device_node *cbdev_node);
79755 +int crossbar_unmap(struct device_node *cbdev_node, unsigned index);
79756 --- a/include/linux/i2c/twl.h
79757 +++ b/include/linux/i2c/twl.h
79758 @@ -26,6 +26,7 @@
79759 #define __TWL_H_
79760
79761 #include <linux/types.h>
79762 +#include <linux/phy/phy.h>
79763 #include <linux/input/matrix_keypad.h>
79764
79765 /*
79766 @@ -615,6 +616,7 @@ enum twl4030_usb_mode {
79767 struct twl4030_usb_data {
79768 enum twl4030_usb_mode usb_mode;
79769 unsigned long features;
79770 + struct phy_init_data *init_data;
79771
79772 int (*phy_init)(struct device *dev);
79773 int (*phy_exit)(struct device *dev);
79774 --- a/include/linux/input/pixcir_ts.h
79775 +++ b/include/linux/input/pixcir_ts.h
79776 @@ -1,10 +1,63 @@
79777 #ifndef _PIXCIR_I2C_TS_H
79778 #define _PIXCIR_I2C_TS_H
79779
79780 +/*
79781 + * Register map
79782 + */
79783 +#define PIXCIR_REG_POWER_MODE 51
79784 +#define PIXCIR_REG_INT_MODE 52
79785 +
79786 +/*
79787 + * Power modes:
79788 + * active: max scan speed
79789 + * idle: lower scan speed with automatic transition to active on touch
79790 + * halt: datasheet says sleep but this is more like halt as the chip
79791 + * clocks are cut and it can only be brought out of this mode
79792 + * using the RESET pin.
79793 + */
79794 +enum pixcir_power_mode {
79795 + PIXCIR_POWER_ACTIVE,
79796 + PIXCIR_POWER_IDLE,
79797 + PIXCIR_POWER_HALT,
79798 +};
79799 +
79800 +#define PIXCIR_POWER_MODE_MASK 0x03
79801 +#define PIXCIR_POWER_ALLOW_IDLE (1UL << 2)
79802 +
79803 +/*
79804 + * Interrupt modes:
79805 + * periodical: interrupt is asserted periodicaly
79806 + * diff coordinates: interrupt is asserted when coordinates change
79807 + * level on touch: interrupt level asserted during touch
79808 + * pulse on touch: interrupt pulse asserted druing touch
79809 + *
79810 + */
79811 +enum pixcir_int_mode {
79812 + PIXCIR_INT_PERIODICAL,
79813 + PIXCIR_INT_DIFF_COORD,
79814 + PIXCIR_INT_LEVEL_TOUCH,
79815 + PIXCIR_INT_PULSE_TOUCH,
79816 +};
79817 +
79818 +#define PIXCIR_INT_MODE_MASK 0x03
79819 +#define PIXCIR_INT_ENABLE (1UL << 3)
79820 +#define PIXCIR_INT_POL_HIGH (1UL << 2)
79821 +
79822 +/**
79823 + * struct pixcir_irc_chip_data - chip related data
79824 + * @num_report_ids: Max number of finger ids reported simultaneously.
79825 + * if 0 it means chip doesn't support finger id reporting
79826 + * and driver will resort to Type A Multi-Touch reporting.
79827 + */
79828 +struct pixcir_i2c_chip_data {
79829 + u8 num_report_ids;
79830 +};
79831 +
79832 struct pixcir_ts_platform_data {
79833 - int (*attb_read_val)(void);
79834 - int x_max;
79835 - int y_max;
79836 + unsigned int x_size; /* X axis resolution */
79837 + unsigned int y_size; /* Y axis resolution */
79838 + int gpio_attb; /* GPIO connected to ATTB line */
79839 + struct pixcir_i2c_chip_data chip;
79840 };
79841
79842 #endif
79843 --- /dev/null
79844 +++ b/include/linux/mfd/tps65218.h
79845 @@ -0,0 +1,288 @@
79846 +/*
79847 + * linux/mfd/tps65218.h
79848 + *
79849 + * Functions to access TPS65219 power management chip.
79850 + *
79851 + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
79852 + *
79853 + * This program is free software; you can redistribute it and/or
79854 + * modify it under the terms of the GNU General Public License version 2 as
79855 + * published by the Free Software Foundation.
79856 + *
79857 + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
79858 + * kind, whether expressed or implied; without even the implied warranty
79859 + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
79860 + * GNU General Public License version 2 for more details.
79861 + */
79862 +
79863 +#ifndef __LINUX_MFD_TPS65218_H
79864 +#define __LINUX_MFD_TPS65218_H
79865 +
79866 +#include <linux/i2c.h>
79867 +#include <linux/regulator/driver.h>
79868 +#include <linux/regulator/machine.h>
79869 +#include <linux/bitops.h>
79870 +
79871 +/* TPS chip id list */
79872 +#define TPS65218 0xF0
79873 +
79874 +/* I2C ID for TPS65218 part */
79875 +#define TPS65218_I2C_ID 0x24
79876 +
79877 +/* All register addresses */
79878 +#define TPS65218_REG_CHIPID 0x00
79879 +#define TPS65218_REG_INT1 0x01
79880 +#define TPS65218_REG_INT2 0x02
79881 +#define TPS65218_REG_INT_MASK1 0x03
79882 +#define TPS65218_REG_INT_MASK2 0x04
79883 +#define TPS65218_REG_STATUS 0x05
79884 +#define TPS65218_REG_CONTROL 0x06
79885 +#define TPS65218_REG_FLAG 0x07
79886 +
79887 +#define TPS65218_REG_PASSWORD 0x10
79888 +#define TPS65218_REG_ENABLE1 0x11
79889 +#define TPS65218_REG_ENABLE2 0x12
79890 +#define TPS65218_REG_CONFIG1 0x13
79891 +#define TPS65218_REG_CONFIG2 0x14
79892 +#define TPS65218_REG_CONFIG3 0x15
79893 +#define TPS65218_REG_CONTROL_DCDC1 0x16
79894 +#define TPS65218_REG_CONTROL_DCDC2 0x17
79895 +#define TPS65218_REG_CONTROL_DCDC3 0x18
79896 +#define TPS65218_REG_CONTROL_DCDC4 0x19
79897 +#define TPS65218_REG_CONTRL_SLEW_RATE 0x1A
79898 +#define TPS65218_REG_CONTROL_LDO1 0x1B
79899 +#define TPS65218_REG_SEQ1 0x20
79900 +#define TPS65218_REG_SEQ2 0x21
79901 +#define TPS65218_REG_SEQ3 0x22
79902 +#define TPS65218_REG_SEQ4 0x23
79903 +#define TPS65218_REG_SEQ5 0x24
79904 +#define TPS65218_REG_SEQ6 0x25
79905 +#define TPS65218_REG_SEQ7 0x26
79906 +
79907 +/* Register field definitions */
79908 +#define TPS65218_CHIPID_CHIP_MASK 0xF8
79909 +#define TPS65218_CHIPID_REV_MASK 0x07
79910 +
79911 +#define TPS65218_INT1_VPRG BIT(5)
79912 +#define TPS65218_INT1_AC BIT(4)
79913 +#define TPS65218_INT1_PB BIT(3)
79914 +#define TPS65218_INT1_HOT BIT(2)
79915 +#define TPS65218_INT1_CC_AQC BIT(1)
79916 +#define TPS65218_INT1_PRGC BIT(0)
79917 +
79918 +#define TPS65218_INT2_LS3_F BIT(5)
79919 +#define TPS65218_INT2_LS2_F BIT(4)
79920 +#define TPS65218_INT2_LS1_F BIT(3)
79921 +#define TPS65218_INT2_LS3_I BIT(2)
79922 +#define TPS65218_INT2_LS2_I BIT(1)
79923 +#define TPS65218_INT2_LS1_I BIT(0)
79924 +
79925 +#define TPS65218_INT_MASK1_VPRG BIT(5)
79926 +#define TPS65218_INT_MASK1_AC BIT(4)
79927 +#define TPS65218_INT_MASK1_PB BIT(3)
79928 +#define TPS65218_INT_MASK1_HOT BIT(2)
79929 +#define TPS65218_INT_MASK1_CC_AQC BIT(1)
79930 +#define TPS65218_INT_MASK1_PRGC BIT(0)
79931 +
79932 +#define TPS65218_INT_MASK2_LS3_F BIT(5)
79933 +#define TPS65218_INT_MASK2_LS2_F BIT(4)
79934 +#define TPS65218_INT_MASK2_LS1_F BIT(3)
79935 +#define TPS65218_INT_MASK2_LS3_I BIT(2)
79936 +#define TPS65218_INT_MASK2_LS2_I BIT(1)
79937 +#define TPS65218_INT_MASK2_LS1_I BIT(0)
79938 +
79939 +#define TPS65218_STATUS_FSEAL BIT(7)
79940 +#define TPS65218_STATUS_EE BIT(6)
79941 +#define TPS65218_STATUS_AC_STATE BIT(5)
79942 +#define TPS65218_STATUS_PB_STATE BIT(4)
79943 +#define TPS65218_STATUS_STATE_MASK 0xC
79944 +#define TPS65218_STATUS_CC_STAT 0x3
79945 +
79946 +#define TPS65218_CONTROL_OFFNPFO BIT(1)
79947 +#define TPS65218_CONTROL_CC_AQ BIT(0)
79948 +
79949 +#define TPS65218_FLAG_GPO3_FLG BIT(7)
79950 +#define TPS65218_FLAG_GPO2_FLG BIT(6)
79951 +#define TPS65218_FLAG_GPO1_FLG BIT(5)
79952 +#define TPS65218_FLAG_LDO1_FLG BIT(4)
79953 +#define TPS65218_FLAG_DC4_FLG BIT(3)
79954 +#define TPS65218_FLAG_DC3_FLG BIT(2)
79955 +#define TPS65218_FLAG_DC2_FLG BIT(1)
79956 +#define TPS65218_FLAG_DC1_FLG BIT(0)
79957 +
79958 +#define TPS65218_ENABLE1_DC6_EN BIT(5)
79959 +#define TPS65218_ENABLE1_DC5_EN BIT(4)
79960 +#define TPS65218_ENABLE1_DC4_EN BIT(3)
79961 +#define TPS65218_ENABLE1_DC3_EN BIT(2)
79962 +#define TPS65218_ENABLE1_DC2_EN BIT(1)
79963 +#define TPS65218_ENABLE1_DC1_EN BIT(0)
79964 +
79965 +#define TPS65218_ENABLE2_GPIO3 BIT(6)
79966 +#define TPS65218_ENABLE2_GPIO2 BIT(5)
79967 +#define TPS65218_ENABLE2_GPIO1 BIT(4)
79968 +#define TPS65218_ENABLE2_LS3_EN BIT(3)
79969 +#define TPS65218_ENABLE2_LS2_EN BIT(2)
79970 +#define TPS65218_ENABLE2_LS1_EN BIT(1)
79971 +#define TPS65218_ENABLE2_LDO1_EN BIT(0)
79972 +
79973 +
79974 +#define TPS65218_CONFIG1_TRST BIT(7)
79975 +#define TPS65218_CONFIG1_GPO2_BUF BIT(6)
79976 +#define TPS65218_CONFIG1_IO1_SEL BIT(5)
79977 +#define TPS65218_CONFIG1_PGDLY_MASK 0x18
79978 +#define TPS65218_CONFIG1_STRICT BIT(2)
79979 +#define TPS65218_CONFIG1_UVLO_MASK 0x3
79980 +
79981 +#define TPS65218_CONFIG2_DC12_RST BIT(7)
79982 +#define TPS65218_CONFIG2_UVLOHYS BIT(6)
79983 +#define TPS65218_CONFIG2_LS3ILIM_MASK 0xC
79984 +#define TPS65218_CONFIG2_LS2ILIM_MASK 0x3
79985 +
79986 +#define TPS65218_CONFIG3_LS3NPFO BIT(5)
79987 +#define TPS65218_CONFIG3_LS2NPFO BIT(4)
79988 +#define TPS65218_CONFIG3_LS1NPFO BIT(3)
79989 +#define TPS65218_CONFIG3_LS3DCHRG BIT(2)
79990 +#define TPS65218_CONFIG3_LS2DCHRG BIT(1)
79991 +#define TPS65218_CONFIG3_LS1DCHRG BIT(0)
79992 +
79993 +#define TPS65218_CONTROL_DCDC1_PFM BIT(7)
79994 +#define TPS65218_CONTROL_DCDC1_MASK 0x7F
79995 +
79996 +#define TPS65218_CONTROL_DCDC2_PFM BIT(7)
79997 +#define TPS65218_CONTROL_DCDC2_MASK 0x3F
79998 +
79999 +#define TPS65218_CONTROL_DCDC3_PFM BIT(7)
80000 +#define TPS65218_CONTROL_DCDC3_MASK 0x3F
80001 +
80002 +#define TPS65218_CONTROL_DCDC4_PFM BIT(7)
80003 +#define TPS65218_CONTROL_DCDC4_MASK 0x3F
80004 +
80005 +#define TPS65218_SLEW_RATE_GO BIT(7)
80006 +#define TPS65218_SLEW_RATE_GODSBL BIT(6)
80007 +#define TPS65218_SLEW_RATE_SLEW_MASK 0x7
80008 +
80009 +#define TPS65218_CONTROL_LDO1_MASK 0x3F
80010 +
80011 +#define TPS65218_SEQ1_DLY8 BIT(7)
80012 +#define TPS65218_SEQ1_DLY7 BIT(6)
80013 +#define TPS65218_SEQ1_DLY6 BIT(5)
80014 +#define TPS65218_SEQ1_DLY5 BIT(4)
80015 +#define TPS65218_SEQ1_DLY4 BIT(3)
80016 +#define TPS65218_SEQ1_DLY3 BIT(2)
80017 +#define TPS65218_SEQ1_DLY2 BIT(1)
80018 +#define TPS65218_SEQ1_DLY1 BIT(0)
80019 +
80020 +#define TPS65218_SEQ2_DLYFCTR BIT(7)
80021 +#define TPS65218_SEQ2_DLY9 BIT(0)
80022 +
80023 +#define TPS65218_SEQ3_DC2_SEQ_MASK 0xF0
80024 +#define TPS65218_SEQ3_DC1_SEQ_MASK 0xF
80025 +
80026 +#define TPS65218_SEQ4_DC4_SEQ_MASK 0xF0
80027 +#define TPS65218_SEQ4_DC3_SEQ_MASK 0xF
80028 +
80029 +#define TPS65218_SEQ5_DC6_SEQ_MASK 0xF0
80030 +#define TPS65218_SEQ5_DC5_SEQ_MASK 0xF
80031 +
80032 +#define TPS65218_SEQ6_LS1_SEQ_MASK 0xF0
80033 +#define TPS65218_SEQ6_LDO1_SEQ_MASK 0xF
80034 +
80035 +#define TPS65218_SEQ7_GPO3_SEQ_MASK 0xF0
80036 +#define TPS65218_SEQ7_GPO1_SEQ_MASK 0xF
80037 +#define TPS65218_PROTECT_NONE 0
80038 +#define TPS65218_PROTECT_L1 1
80039 +
80040 +enum tps65218_regulator_id {
80041 + /* DCDC's */
80042 + TPS65218_DCDC_1,
80043 + TPS65218_DCDC_2,
80044 + TPS65218_DCDC_3,
80045 + TPS65218_DCDC_4,
80046 + TPS65218_DCDC_5,
80047 + TPS65218_DCDC_6,
80048 + /* LDOs */
80049 + TPS65218_LDO_1,
80050 +};
80051 +
80052 +#define TPS65218_MAX_REG_ID TPS65218_LDO_1
80053 +
80054 +/* Number of step-down converters available */
80055 +#define TPS65218_NUM_DCDC 6
80056 +/* Number of LDO voltage regulators available */
80057 +#define TPS65218_NUM_LDO 1
80058 +/* Number of total regulators available */
80059 +#define TPS65218_NUM_REGULATOR (TPS65218_NUM_DCDC + TPS65218_NUM_LDO)
80060 +
80061 +/* Define the TPS65218 IRQ numbers */
80062 +enum tps65218_irqs {
80063 + /* INT1 registers */
80064 + TPS65218_PRGC_IRQ,
80065 + TPS65218_CC_AQC_IRQ,
80066 + TPS65218_HOT_IRQ,
80067 + TPS65218_PB_IRQ,
80068 + TPS65218_AC_IRQ,
80069 + TPS65218_VPRG_IRQ,
80070 + TPS65218_INVALID1_IRQ,
80071 + TPS65218_INVALID2_IRQ,
80072 + /* INT2 registers */
80073 + TPS65218_LS1_I_IRQ,
80074 + TPS65218_LS2_I_IRQ,
80075 + TPS65218_LS3_I_IRQ,
80076 + TPS65218_LS1_F_IRQ,
80077 + TPS65218_LS2_F_IRQ,
80078 + TPS65218_LS3_F_IRQ,
80079 + TPS65218_INVALID3_IRQ,
80080 + TPS65218_INVALID4_IRQ,
80081 +};
80082 +
80083 +/**
80084 + * struct tps_info - packages regulator constraints
80085 + * @id: Id of the regulator
80086 + * @name: Voltage regulator name
80087 + * @min_uV: minimum micro volts
80088 + * @max_uV: minimum micro volts
80089 + * @vsel_to_uv: Function pointer to get voltage from selector
80090 + * @uv_to_vsel: Function pointer to get selector from voltage
80091 + *
80092 + * This data is used to check the regualtor voltage limits while setting.
80093 + */
80094 +struct tps_info {
80095 + int id;
80096 + const char *name;
80097 + int min_uV;
80098 + int max_uV;
80099 + int (*vsel_to_uv)(unsigned int vsel);
80100 + int (*uv_to_vsel)(int uV, unsigned int *vsel);
80101 +};
80102 +
80103 +/**
80104 + * struct tps65218 - tps65218 sub-driver chip access routines
80105 + *
80106 + * Device data may be used to access the TPS65218 chip
80107 + */
80108 +
80109 +struct tps65218 {
80110 + struct device *dev;
80111 + unsigned int id;
80112 +
80113 + struct mutex tps_lock; /* lock guarding the data structure */
80114 + /* IRQ Data */
80115 + int irq;
80116 + u32 irq_mask;
80117 + struct regmap_irq_chip_data *irq_data;
80118 + struct regulator_desc desc[TPS65218_NUM_REGULATOR];
80119 + struct regulator_dev *rdev[TPS65218_NUM_REGULATOR];
80120 + struct tps_info *info[TPS65218_NUM_REGULATOR];
80121 + struct regmap *regmap;
80122 +};
80123 +
80124 +int tps65218_reg_read(struct tps65218 *tps, unsigned int reg,
80125 + unsigned int *val);
80126 +int tps65218_reg_write(struct tps65218 *tps, unsigned int reg,
80127 + unsigned int val, unsigned int level);
80128 +int tps65218_set_bits(struct tps65218 *tps, unsigned int reg,
80129 + unsigned int mask, unsigned int val, unsigned int level);
80130 +int tps65218_clear_bits(struct tps65218 *tps, unsigned int reg,
80131 + unsigned int mask, unsigned int level);
80132 +
80133 +#endif /* __LINUX_MFD_TPS65218_H */
80134 --- a/include/linux/mfd/twl6040.h
80135 +++ b/include/linux/mfd/twl6040.h
80136 @@ -28,6 +28,7 @@
80137 #include <linux/interrupt.h>
80138 #include <linux/mfd/core.h>
80139 #include <linux/regulator/consumer.h>
80140 +#include <linux/clk.h>
80141
80142 #define TWL6040_REG_ASICID 0x01
80143 #define TWL6040_REG_ASICREV 0x02
80144 @@ -222,6 +223,7 @@ struct twl6040 {
80145 struct regmap *regmap;
80146 struct regmap_irq_chip_data *irq_data;
80147 struct regulator_bulk_data supplies[2]; /* supplies for vio, v2v1 */
80148 + struct clk *clk32k;
80149 struct mutex mutex;
80150 struct mutex irq_mutex;
80151 struct mfd_cell cells[TWL6040_CELLS];
80152 --- a/include/linux/omap-mailbox.h
80153 +++ b/include/linux/omap-mailbox.h
80154 @@ -9,20 +9,27 @@
80155 #ifndef OMAP_MAILBOX_H
80156 #define OMAP_MAILBOX_H
80157
80158 +/* forward declaration for clients */
80159 typedef u32 mbox_msg_t;
80160 struct omap_mbox;
80161
80162 +/* interrupt direction identifiers */
80163 typedef int __bitwise omap_mbox_irq_t;
80164 #define IRQ_TX ((__force omap_mbox_irq_t) 1)
80165 #define IRQ_RX ((__force omap_mbox_irq_t) 2)
80166
80167 +/* client api for message transmission */
80168 int omap_mbox_msg_send(struct omap_mbox *, mbox_msg_t msg);
80169
80170 +/* client api for acquiring and releasing a mailbox */
80171 struct omap_mbox *omap_mbox_get(const char *, struct notifier_block *nb);
80172 void omap_mbox_put(struct omap_mbox *mbox, struct notifier_block *nb);
80173
80174 +/* client api for saving and restoring context */
80175 void omap_mbox_save_ctx(struct omap_mbox *mbox);
80176 void omap_mbox_restore_ctx(struct omap_mbox *mbox);
80177 +
80178 +/* client api for manipulating mailbox interrupts */
80179 void omap_mbox_enable_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq);
80180 void omap_mbox_disable_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq);
80181
80182 --- /dev/null
80183 +++ b/include/linux/phy/omap_control_phy.h
80184 @@ -0,0 +1,89 @@
80185 +/*
80186 + * omap_control_phy.h - Header file for the PHY part of control module.
80187 + *
80188 + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
80189 + * This program is free software; you can redistribute it and/or modify
80190 + * it under the terms of the GNU General Public License as published by
80191 + * the Free Software Foundation; either version 2 of the License, or
80192 + * (at your option) any later version.
80193 + *
80194 + * Author: Kishon Vijay Abraham I <kishon@ti.com>
80195 + *
80196 + * This program is distributed in the hope that it will be useful,
80197 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
80198 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
80199 + * GNU General Public License for more details.
80200 + *
80201 + */
80202 +
80203 +#ifndef __OMAP_CONTROL_PHY_H__
80204 +#define __OMAP_CONTROL_PHY_H__
80205 +
80206 +enum omap_control_phy_type {
80207 + OMAP_CTRL_TYPE_OTGHS = 1, /* Mailbox OTGHS_CONTROL */
80208 + OMAP_CTRL_TYPE_USB2, /* USB2_PHY, power down in CONTROL_DEV_CONF */
80209 + OMAP_CTRL_TYPE_PIPE3, /* PIPE3 PHY, DPLL & seperate Rx/Tx power */
80210 + OMAP_CTRL_TYPE_DRA7USB2, /* USB2 PHY, power and power_aux e.g. DRA7 */
80211 + OMAP_CTRL_TYPE_AM437USB2, /* USB2 PHY, power e.g. AM437x */
80212 +};
80213 +
80214 +struct omap_control_phy {
80215 + struct device *dev;
80216 +
80217 + u32 __iomem *otghs_control;
80218 + u32 __iomem *power;
80219 + u32 __iomem *power_aux;
80220 +
80221 + struct clk *sys_clk;
80222 +
80223 + enum omap_control_phy_type type;
80224 +};
80225 +
80226 +enum omap_control_usb_mode {
80227 + USB_MODE_UNDEFINED = 0,
80228 + USB_MODE_HOST,
80229 + USB_MODE_DEVICE,
80230 + USB_MODE_DISCONNECT,
80231 +};
80232 +
80233 +#define OMAP_CTRL_DEV_PHY_PD BIT(0)
80234 +
80235 +#define OMAP_CTRL_DEV_AVALID BIT(0)
80236 +#define OMAP_CTRL_DEV_BVALID BIT(1)
80237 +#define OMAP_CTRL_DEV_VBUSVALID BIT(2)
80238 +#define OMAP_CTRL_DEV_SESSEND BIT(3)
80239 +#define OMAP_CTRL_DEV_IDDIG BIT(4)
80240 +
80241 +#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK 0x003FC000
80242 +#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT 0xE
80243 +
80244 +#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK 0xFFC00000
80245 +#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT 0x16
80246 +
80247 +#define OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON 0x3
80248 +#define OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF 0x0
80249 +
80250 +#define OMAP_CTRL_USB2_PHY_PD BIT(28)
80251 +
80252 +#define AM437X_CTRL_USB2_PHY_PD BIT(0)
80253 +#define AM437X_CTRL_USB2_OTG_PD BIT(1)
80254 +#define AM437X_CTRL_USB2_OTGVDET_EN BIT(19)
80255 +#define AM437X_CTRL_USB2_OTGSESSEND_EN BIT(20)
80256 +
80257 +#if IS_ENABLED(CONFIG_OMAP_CONTROL_PHY)
80258 +extern void omap_control_phy_power(struct device *dev, int on);
80259 +extern void omap_control_usb_set_mode(struct device *dev,
80260 + enum omap_control_usb_mode mode);
80261 +#else
80262 +
80263 +static inline void omap_control_phy_power(struct device *dev, int on)
80264 +{
80265 +}
80266 +
80267 +static inline void omap_control_usb_set_mode(struct device *dev,
80268 + enum omap_control_usb_mode mode)
80269 +{
80270 +}
80271 +#endif
80272 +
80273 +#endif /* __OMAP_CONTROL_PHY_H__ */
80274 --- /dev/null
80275 +++ b/include/linux/phy/omap_pipe3.h
80276 @@ -0,0 +1,59 @@
80277 +/*
80278 + * omap_pipe3.h -- omap pipe3 phy header file
80279 + *
80280 + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
80281 + * This program is free software; you can redistribute it and/or modify
80282 + * it under the terms of the GNU General Public License as published by
80283 + * the Free Software Foundation; either version 2 of the License, or
80284 + * (at your option) any later version.
80285 + *
80286 + * Author: Kishon Vijay Abraham I <kishon@ti.com>
80287 + *
80288 + * This program is distributed in the hope that it will be useful,
80289 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
80290 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
80291 + * GNU General Public License for more details.
80292 + *
80293 + */
80294 +
80295 +#ifndef __DRIVERS_OMAP_PIPE3_H
80296 +#define __DRIVERS_OMAP_PIPE3_H
80297 +
80298 +#include <linux/io.h>
80299 +
80300 +struct pipe3_dpll_params {
80301 + u16 m;
80302 + u8 n;
80303 + u8 freq:3;
80304 + u8 sd;
80305 + u32 mf;
80306 +};
80307 +
80308 +struct pipe3_dpll_map {
80309 + unsigned long rate;
80310 + struct pipe3_dpll_params params;
80311 +};
80312 +
80313 +struct omap_pipe3 {
80314 + void __iomem *pll_ctrl_base;
80315 + struct device *dev;
80316 + struct device *control_dev;
80317 + struct clk *wkupclk;
80318 + struct clk *sys_clk;
80319 + struct clk *optclk;
80320 + struct clk *optclk2;
80321 + struct pipe3_dpll_map *dpll_map;
80322 +};
80323 +
80324 +static inline u32 omap_pipe3_readl(void __iomem *addr, unsigned offset)
80325 +{
80326 + return __raw_readl(addr + offset);
80327 +}
80328 +
80329 +static inline void omap_pipe3_writel(void __iomem *addr, unsigned offset,
80330 + u32 data)
80331 +{
80332 + __raw_writel(data, addr + offset);
80333 +}
80334 +
80335 +#endif /* __DRIVERS_OMAP_PIPE3_H */
80336 --- /dev/null
80337 +++ b/include/linux/phy/omap_usb.h
80338 @@ -0,0 +1,74 @@
80339 +/*
80340 + * omap_usb.h -- omap usb2 phy header file
80341 + *
80342 + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com
80343 + * This program is free software; you can redistribute it and/or modify
80344 + * it under the terms of the GNU General Public License as published by
80345 + * the Free Software Foundation; either version 2 of the License, or
80346 + * (at your option) any later version.
80347 + *
80348 + * Author: Kishon Vijay Abraham I <kishon@ti.com>
80349 + *
80350 + * This program is distributed in the hope that it will be useful,
80351 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
80352 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
80353 + * GNU General Public License for more details.
80354 + *
80355 + */
80356 +
80357 +#ifndef __DRIVERS_OMAP_USB2_H
80358 +#define __DRIVERS_OMAP_USB2_H
80359 +
80360 +#include <linux/io.h>
80361 +#include <linux/usb/otg.h>
80362 +
80363 +struct usb_dpll_params {
80364 + u16 m;
80365 + u8 n;
80366 + u8 freq:3;
80367 + u8 sd;
80368 + u32 mf;
80369 +};
80370 +
80371 +struct omap_usb {
80372 + struct usb_phy phy;
80373 + struct phy_companion *comparator;
80374 + struct device *dev;
80375 + struct device *control_dev;
80376 + struct clk *wkupclk;
80377 + struct clk *optclk;
80378 +};
80379 +
80380 +struct usb_phy_data {
80381 + const char *label;
80382 + u32 flags;
80383 +};
80384 +
80385 +enum usb_phy_data_flags {
80386 + OMAP_USB2_HAS_START_SRP = 1,
80387 + OMAP_USB2_HAS_SET_VBUS,
80388 +};
80389 +
80390 +#define phy_to_omapusb(x) container_of((x), struct omap_usb, phy)
80391 +
80392 +#if defined(CONFIG_OMAP_USB2) || defined(CONFIG_OMAP_USB2_MODULE)
80393 +extern int omap_usb2_set_comparator(struct phy_companion *comparator);
80394 +#else
80395 +static inline int omap_usb2_set_comparator(struct phy_companion *comparator)
80396 +{
80397 + return -ENODEV;
80398 +}
80399 +#endif
80400 +
80401 +static inline u32 omap_usb_readl(void __iomem *addr, unsigned offset)
80402 +{
80403 + return __raw_readl(addr + offset);
80404 +}
80405 +
80406 +static inline void omap_usb_writel(void __iomem *addr, unsigned offset,
80407 + u32 data)
80408 +{
80409 + __raw_writel(data, addr + offset);
80410 +}
80411 +
80412 +#endif /* __DRIVERS_OMAP_USB_H */
80413 --- /dev/null
80414 +++ b/include/linux/phy/phy.h
80415 @@ -0,0 +1,270 @@
80416 +/*
80417 + * phy.h -- generic phy header file
80418 + *
80419 + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
80420 + *
80421 + * Author: Kishon Vijay Abraham I <kishon@ti.com>
80422 + *
80423 + * This program is free software; you can redistribute it and/or modify
80424 + * it under the terms of the GNU General Public License as published by
80425 + * the Free Software Foundation; either version 2 of the License, or
80426 + * (at your option) any later version.
80427 + */
80428 +
80429 +#ifndef __DRIVERS_PHY_H
80430 +#define __DRIVERS_PHY_H
80431 +
80432 +#include <linux/err.h>
80433 +#include <linux/of.h>
80434 +#include <linux/device.h>
80435 +#include <linux/pm_runtime.h>
80436 +
80437 +struct phy;
80438 +
80439 +/**
80440 + * struct phy_ops - set of function pointers for performing phy operations
80441 + * @init: operation to be performed for initializing phy
80442 + * @exit: operation to be performed while exiting
80443 + * @power_on: powering on the phy
80444 + * @power_off: powering off the phy
80445 + * @owner: the module owner containing the ops
80446 + */
80447 +struct phy_ops {
80448 + int (*init)(struct phy *phy);
80449 + int (*exit)(struct phy *phy);
80450 + int (*power_on)(struct phy *phy);
80451 + int (*power_off)(struct phy *phy);
80452 + struct module *owner;
80453 +};
80454 +
80455 +/**
80456 + * struct phy - represents the phy device
80457 + * @dev: phy device
80458 + * @id: id of the phy device
80459 + * @ops: function pointers for performing phy operations
80460 + * @init_data: list of PHY consumers (non-dt only)
80461 + * @mutex: mutex to protect phy_ops
80462 + * @init_count: used to protect when the PHY is used by multiple consumers
80463 + * @power_count: used to protect when the PHY is used by multiple consumers
80464 + */
80465 +struct phy {
80466 + struct device dev;
80467 + int id;
80468 + const struct phy_ops *ops;
80469 + struct phy_init_data *init_data;
80470 + struct mutex mutex;
80471 + int init_count;
80472 + int power_count;
80473 +};
80474 +
80475 +/**
80476 + * struct phy_provider - represents the phy provider
80477 + * @dev: phy provider device
80478 + * @owner: the module owner having of_xlate
80479 + * @of_xlate: function pointer to obtain phy instance from phy pointer
80480 + * @list: to maintain a linked list of PHY providers
80481 + */
80482 +struct phy_provider {
80483 + struct device *dev;
80484 + struct module *owner;
80485 + struct list_head list;
80486 + struct phy * (*of_xlate)(struct device *dev,
80487 + struct of_phandle_args *args);
80488 +};
80489 +
80490 +/**
80491 + * struct phy_consumer - represents the phy consumer
80492 + * @dev_name: the device name of the controller that will use this PHY device
80493 + * @port: name given to the consumer port
80494 + */
80495 +struct phy_consumer {
80496 + const char *dev_name;
80497 + const char *port;
80498 +};
80499 +
80500 +/**
80501 + * struct phy_init_data - contains the list of PHY consumers
80502 + * @num_consumers: number of consumers for this PHY device
80503 + * @consumers: list of PHY consumers
80504 + */
80505 +struct phy_init_data {
80506 + unsigned int num_consumers;
80507 + struct phy_consumer *consumers;
80508 +};
80509 +
80510 +#define PHY_CONSUMER(_dev_name, _port) \
80511 +{ \
80512 + .dev_name = _dev_name, \
80513 + .port = _port, \
80514 +}
80515 +
80516 +#define to_phy(dev) (container_of((dev), struct phy, dev))
80517 +
80518 +#define of_phy_provider_register(dev, xlate) \
80519 + __of_phy_provider_register((dev), THIS_MODULE, (xlate))
80520 +
80521 +#define devm_of_phy_provider_register(dev, xlate) \
80522 + __devm_of_phy_provider_register((dev), THIS_MODULE, (xlate))
80523 +
80524 +static inline void phy_set_drvdata(struct phy *phy, void *data)
80525 +{
80526 + dev_set_drvdata(&phy->dev, data);
80527 +}
80528 +
80529 +static inline void *phy_get_drvdata(struct phy *phy)
80530 +{
80531 + return dev_get_drvdata(&phy->dev);
80532 +}
80533 +
80534 +#if IS_ENABLED(CONFIG_GENERIC_PHY)
80535 +extern int phy_pm_runtime_get(struct phy *phy);
80536 +extern int phy_pm_runtime_get_sync(struct phy *phy);
80537 +extern int phy_pm_runtime_put(struct phy *phy);
80538 +extern int phy_pm_runtime_put_sync(struct phy *phy);
80539 +extern void phy_pm_runtime_allow(struct phy *phy);
80540 +extern void phy_pm_runtime_forbid(struct phy *phy);
80541 +extern int phy_init(struct phy *phy);
80542 +extern int phy_exit(struct phy *phy);
80543 +extern int phy_power_on(struct phy *phy);
80544 +extern int phy_power_off(struct phy *phy);
80545 +extern struct phy *phy_get(struct device *dev, const char *string);
80546 +extern struct phy *devm_phy_get(struct device *dev, const char *string);
80547 +extern void phy_put(struct phy *phy);
80548 +extern void devm_phy_put(struct device *dev, struct phy *phy);
80549 +extern struct phy *of_phy_simple_xlate(struct device *dev,
80550 + struct of_phandle_args *args);
80551 +extern struct phy *phy_create(struct device *dev, const struct phy_ops *ops,
80552 + struct phy_init_data *init_data);
80553 +extern struct phy *devm_phy_create(struct device *dev,
80554 + const struct phy_ops *ops, struct phy_init_data *init_data);
80555 +extern void phy_destroy(struct phy *phy);
80556 +extern void devm_phy_destroy(struct device *dev, struct phy *phy);
80557 +extern struct phy_provider *__of_phy_provider_register(struct device *dev,
80558 + struct module *owner, struct phy * (*of_xlate)(struct device *dev,
80559 + struct of_phandle_args *args));
80560 +extern struct phy_provider *__devm_of_phy_provider_register(struct device *dev,
80561 + struct module *owner, struct phy * (*of_xlate)(struct device *dev,
80562 + struct of_phandle_args *args));
80563 +extern void of_phy_provider_unregister(struct phy_provider *phy_provider);
80564 +extern void devm_of_phy_provider_unregister(struct device *dev,
80565 + struct phy_provider *phy_provider);
80566 +#else
80567 +static inline int phy_pm_runtime_get(struct phy *phy)
80568 +{
80569 + return -ENOSYS;
80570 +}
80571 +
80572 +static inline int phy_pm_runtime_get_sync(struct phy *phy)
80573 +{
80574 + return -ENOSYS;
80575 +}
80576 +
80577 +static inline int phy_pm_runtime_put(struct phy *phy)
80578 +{
80579 + return -ENOSYS;
80580 +}
80581 +
80582 +static inline int phy_pm_runtime_put_sync(struct phy *phy)
80583 +{
80584 + return -ENOSYS;
80585 +}
80586 +
80587 +static inline void phy_pm_runtime_allow(struct phy *phy)
80588 +{
80589 + return;
80590 +}
80591 +
80592 +static inline void phy_pm_runtime_forbid(struct phy *phy)
80593 +{
80594 + return;
80595 +}
80596 +
80597 +static inline int phy_init(struct phy *phy)
80598 +{
80599 + return -ENOSYS;
80600 +}
80601 +
80602 +static inline int phy_exit(struct phy *phy)
80603 +{
80604 + return -ENOSYS;
80605 +}
80606 +
80607 +static inline int phy_power_on(struct phy *phy)
80608 +{
80609 + return -ENOSYS;
80610 +}
80611 +
80612 +static inline int phy_power_off(struct phy *phy)
80613 +{
80614 + return -ENOSYS;
80615 +}
80616 +
80617 +static inline struct phy *phy_get(struct device *dev, const char *string)
80618 +{
80619 + return ERR_PTR(-ENOSYS);
80620 +}
80621 +
80622 +static inline struct phy *devm_phy_get(struct device *dev, const char *string)
80623 +{
80624 + return ERR_PTR(-ENOSYS);
80625 +}
80626 +
80627 +static inline void phy_put(struct phy *phy)
80628 +{
80629 +}
80630 +
80631 +static inline void devm_phy_put(struct device *dev, struct phy *phy)
80632 +{
80633 +}
80634 +
80635 +static inline struct phy *of_phy_simple_xlate(struct device *dev,
80636 + struct of_phandle_args *args)
80637 +{
80638 + return ERR_PTR(-ENOSYS);
80639 +}
80640 +
80641 +static inline struct phy *phy_create(struct device *dev,
80642 + const struct phy_ops *ops, struct phy_init_data *init_data)
80643 +{
80644 + return ERR_PTR(-ENOSYS);
80645 +}
80646 +
80647 +static inline struct phy *devm_phy_create(struct device *dev,
80648 + const struct phy_ops *ops, struct phy_init_data *init_data)
80649 +{
80650 + return ERR_PTR(-ENOSYS);
80651 +}
80652 +
80653 +static inline void phy_destroy(struct phy *phy)
80654 +{
80655 +}
80656 +
80657 +static inline void devm_phy_destroy(struct device *dev, struct phy *phy)
80658 +{
80659 +}
80660 +
80661 +static inline struct phy_provider *__of_phy_provider_register(
80662 + struct device *dev, struct module *owner, struct phy * (*of_xlate)(
80663 + struct device *dev, struct of_phandle_args *args))
80664 +{
80665 + return ERR_PTR(-ENOSYS);
80666 +}
80667 +
80668 +static inline struct phy_provider *__devm_of_phy_provider_register(struct device
80669 + *dev, struct module *owner, struct phy * (*of_xlate)(struct device *dev,
80670 + struct of_phandle_args *args))
80671 +{
80672 + return ERR_PTR(-ENOSYS);
80673 +}
80674 +
80675 +static inline void of_phy_provider_unregister(struct phy_provider *phy_provider)
80676 +{
80677 +}
80678 +
80679 +static inline void devm_of_phy_provider_unregister(struct device *dev,
80680 + struct phy_provider *phy_provider)
80681 +{
80682 +}
80683 +#endif
80684 +
80685 +#endif /* __DRIVERS_PHY_H */
80686 --- a/include/linux/platform_data/davinci_asp.h
80687 +++ b/include/linux/platform_data/davinci_asp.h
80688 @@ -84,6 +84,8 @@ struct snd_platform_data {
80689 u8 version;
80690 u8 txnumevt;
80691 u8 rxnumevt;
80692 + int tx_dma_channel;
80693 + int rx_dma_channel;
80694 };
80695
80696 enum {
80697 --- a/include/linux/platform_data/elm.h
80698 +++ b/include/linux/platform_data/elm.h
80699 @@ -21,17 +21,12 @@
80700 enum bch_ecc {
80701 BCH4_ECC = 0,
80702 BCH8_ECC,
80703 + BCH16_ECC
80704 };
80705
80706 /* ELM support 8 error syndrome process */
80707 #define ERROR_VECTOR_MAX 8
80708 -
80709 -#define BCH8_ECC_OOB_BYTES 13
80710 -#define BCH4_ECC_OOB_BYTES 7
80711 -/* RBL requires 14 byte even though BCH8 uses only 13 byte */
80712 -#define BCH8_SIZE (BCH8_ECC_OOB_BYTES + 1)
80713 -/* Uses 1 extra byte to handle erased pages */
80714 -#define BCH4_SIZE (BCH4_ECC_OOB_BYTES + 1)
80715 +#define ELM_MAX_DETECTABLE_ERRORS 16
80716
80717 /**
80718 * struct elm_errorvec - error vector for elm
80719 @@ -45,10 +40,11 @@ struct elm_errorvec {
80720 bool error_reported;
80721 bool error_uncorrectable;
80722 int error_count;
80723 - int error_loc[ERROR_VECTOR_MAX];
80724 + int error_loc[ELM_MAX_DETECTABLE_ERRORS];
80725 };
80726
80727 void elm_decode_bch_error_page(struct device *dev, u8 *ecc_calc,
80728 struct elm_errorvec *err_vec);
80729 -int elm_config(struct device *dev, enum bch_ecc bch_type);
80730 +int elm_config(struct device *dev, struct mtd_info *mtd,
80731 + enum bch_ecc bch_type);
80732 #endif /* __ELM_H */
80733 --- a/include/linux/platform_data/mtd-nand-omap2.h
80734 +++ b/include/linux/platform_data/mtd-nand-omap2.h
80735 @@ -23,13 +23,18 @@ enum nand_io {
80736 };
80737
80738 enum omap_ecc {
80739 - /* 1-bit ecc: stored at end of spare area */
80740 - OMAP_ECC_HAMMING_CODE_DEFAULT = 0, /* Default, s/w method */
80741 - OMAP_ECC_HAMMING_CODE_HW, /* gpmc to detect the error */
80742 - /* 1-bit ecc: stored at beginning of spare area as romcode */
80743 - OMAP_ECC_HAMMING_CODE_HW_ROMCODE, /* gpmc method & romcode layout */
80744 - OMAP_ECC_BCH4_CODE_HW, /* 4-bit BCH ecc code */
80745 - OMAP_ECC_BCH8_CODE_HW, /* 8-bit BCH ecc code */
80746 + /* 1-bit ECC calculation by GPMC, Error detection by Software */
80747 + OMAP_ECC_HAMMING_CODE_HW = 0,
80748 + /* 4-bit ECC calculation by GPMC, Error detection by Software */
80749 + OMAP_ECC_BCH4_CODE_HW_DETECTION_SW,
80750 + /* 4-bit ECC calculation by GPMC, Error detection by ELM */
80751 + OMAP_ECC_BCH4_CODE_HW,
80752 + /* 8-bit ECC calculation by GPMC, Error detection by Software */
80753 + OMAP_ECC_BCH8_CODE_HW_DETECTION_SW,
80754 + /* 8-bit ECC calculation by GPMC, Error detection by ELM */
80755 + OMAP_ECC_BCH8_CODE_HW,
80756 + /* 16-bit ECC calculation by GPMC, Error detection by ELM */
80757 + OMAP_ECC_BCH16_CODE_HW,
80758 };
80759
80760 struct gpmc_nand_regs {
80761 @@ -49,6 +54,9 @@ struct gpmc_nand_regs {
80762 void __iomem *gpmc_bch_result1[GPMC_BCH_NUM_REMAINDER];
80763 void __iomem *gpmc_bch_result2[GPMC_BCH_NUM_REMAINDER];
80764 void __iomem *gpmc_bch_result3[GPMC_BCH_NUM_REMAINDER];
80765 + void __iomem *gpmc_bch_result4[GPMC_BCH_NUM_REMAINDER];
80766 + void __iomem *gpmc_bch_result5[GPMC_BCH_NUM_REMAINDER];
80767 + void __iomem *gpmc_bch_result6[GPMC_BCH_NUM_REMAINDER];
80768 };
80769
80770 struct omap_nand_platform_data {
80771 @@ -63,5 +71,6 @@ struct omap_nand_platform_data {
80772
80773 /* for passing the partitions */
80774 struct device_node *of_node;
80775 + struct device_node *elm_of_node;
80776 };
80777 #endif
80778 --- a/include/linux/platform_data/omap-wd-timer.h
80779 +++ b/include/linux/platform_data/omap-wd-timer.h
80780 @@ -16,6 +16,14 @@
80781 #include <linux/types.h>
80782
80783 /*
80784 + * WATCHDOG IP Revisions
80785 + * WDTIMER2_IP3 - Used in OMAP3
80786 + * WDTIMER2_IP4 - Used in OMAP4+ Soc's
80787 + */
80788 +#define WDTIMER2_IP3 1
80789 +#define WDTIMER2_IP4 2
80790 +
80791 +/*
80792 * Standardized OMAP reset source bits
80793 *
80794 * This is a subset of the ones listed in arch/arm/mach-omap2/prm.h
80795 @@ -33,6 +41,7 @@
80796 */
80797 struct omap_wd_timer_platform_data {
80798 u32 (*read_reset_sources)(void);
80799 + u32 ip_rev;
80800 };
80801
80802 #endif
80803 --- /dev/null
80804 +++ b/include/linux/platform_data/usb-rcar-gen2-phy.h
80805 @@ -0,0 +1,22 @@
80806 +/*
80807 + * Copyright (C) 2013 Renesas Solutions Corp.
80808 + * Copyright (C) 2013 Cogent Embedded, Inc.
80809 + *
80810 + * This program is free software; you can redistribute it and/or modify
80811 + * it under the terms of the GNU General Public License version 2 as
80812 + * published by the Free Software Foundation.
80813 + */
80814 +
80815 +#ifndef __USB_RCAR_GEN2_PHY_H
80816 +#define __USB_RCAR_GEN2_PHY_H
80817 +
80818 +#include <linux/types.h>
80819 +
80820 +struct rcar_gen2_phy_platform_data {
80821 + /* USB channel 0 configuration */
80822 + bool chan0_pci:1; /* true: PCI USB host 0, false: USBHS */
80823 + /* USB channel 2 configuration */
80824 + bool chan2_pci:1; /* true: PCI USB host 2, false: USBSS */
80825 +};
80826 +
80827 +#endif
80828 --- a/include/linux/regulator/driver.h
80829 +++ b/include/linux/regulator/driver.h
80830 @@ -316,6 +316,8 @@ struct regulator_dev {
80831
80832 struct blocking_notifier_head notifier;
80833 struct mutex mutex; /* consumer lock */
80834 + struct task_struct *lock_owner;
80835 + int lock_count;
80836 struct module *owner;
80837 struct device dev;
80838 struct regulation_constraints *constraints;
80839 --- a/include/linux/reset-controller.h
80840 +++ b/include/linux/reset-controller.h
80841 @@ -17,6 +17,8 @@ struct reset_control_ops {
80842 int (*reset)(struct reset_controller_dev *rcdev, unsigned long id);
80843 int (*assert)(struct reset_controller_dev *rcdev, unsigned long id);
80844 int (*deassert)(struct reset_controller_dev *rcdev, unsigned long id);
80845 + int (*is_reset)(struct reset_controller_dev *rcdev, unsigned long id);
80846 + int (*clear_reset)(struct reset_controller_dev *rcdev, unsigned long i);
80847 };
80848
80849 struct module;
80850 --- a/include/linux/reset.h
80851 +++ b/include/linux/reset.h
80852 @@ -7,6 +7,8 @@ struct reset_control;
80853 int reset_control_reset(struct reset_control *rstc);
80854 int reset_control_assert(struct reset_control *rstc);
80855 int reset_control_deassert(struct reset_control *rstc);
80856 +int reset_control_is_reset(struct reset_control *rstc);
80857 +int reset_control_clear_reset(struct reset_control *rstc);
80858
80859 struct reset_control *reset_control_get(struct device *dev, const char *id);
80860 void reset_control_put(struct reset_control *rstc);
80861 --- a/include/linux/spi/spi.h
80862 +++ b/include/linux/spi/spi.h
80863 @@ -91,6 +91,7 @@ struct spi_device {
80864 #define SPI_TX_QUAD 0x200 /* transmit with 4 wires */
80865 #define SPI_RX_DUAL 0x400 /* receive with 2 wires */
80866 #define SPI_RX_QUAD 0x800 /* receive with 4 wires */
80867 +#define SPI_RX_MMAP 0x1000 /* Memory mapped Reas */
80868 u8 bits_per_word;
80869 int irq;
80870 void *controller_state;
80871 @@ -554,6 +555,7 @@ struct spi_transfer {
80872 u8 bits_per_word;
80873 u16 delay_usecs;
80874 u32 speed_hz;
80875 + bool memory_map;
80876
80877 struct list_head transfer_list;
80878 };
80879 --- /dev/null
80880 +++ b/include/linux/ti_emif.h
80881 @@ -0,0 +1,558 @@
80882 +/*
80883 + * Register defines for the EMIF driver
80884 + *
80885 + * Copyright (C) 2012 Texas Instruments, Inc.
80886 + *
80887 + * Benoit Cousson (b-cousson@ti.com)
80888 + *
80889 + * This program is free software; you can redistribute it and/or modify
80890 + * it under the terms of the GNU General Public License version 2 as
80891 + * published by the Free Software Foundation.
80892 + */
80893 +#ifndef __TI_EMIF_H
80894 +#define __TI_EMIF_H
80895 +
80896 +/*
80897 + * Maximum number of different frequencies supported by EMIF driver
80898 + * Determines the number of entries in the pointer array for register
80899 + * cache
80900 + */
80901 +#define EMIF_MAX_NUM_FREQUENCIES 6
80902 +
80903 +/* State of the core voltage */
80904 +#define DDR_VOLTAGE_STABLE 0
80905 +#define DDR_VOLTAGE_RAMPING 1
80906 +
80907 +/* Defines for timing De-rating */
80908 +#define EMIF_NORMAL_TIMINGS 0
80909 +#define EMIF_DERATED_TIMINGS 1
80910 +
80911 +/* Length of the forced read idle period in terms of cycles */
80912 +#define EMIF_READ_IDLE_LEN_VAL 5
80913 +
80914 +/*
80915 + * forced read idle interval to be used when voltage
80916 + * is changed as part of DVFS/DPS - 1ms
80917 + */
80918 +#define READ_IDLE_INTERVAL_DVFS (1*1000000)
80919 +
80920 +/*
80921 + * Forced read idle interval to be used when voltage is stable
80922 + * 50us - or maximum value will do
80923 + */
80924 +#define READ_IDLE_INTERVAL_NORMAL (50*1000000)
80925 +
80926 +/* DLL calibration interval when voltage is NOT stable - 1us */
80927 +#define DLL_CALIB_INTERVAL_DVFS (1*1000000)
80928 +
80929 +#define DLL_CALIB_ACK_WAIT_VAL 5
80930 +
80931 +/* Interval between ZQCS commands - hw team recommended value */
80932 +#define EMIF_ZQCS_INTERVAL_US (50*1000)
80933 +/* Enable ZQ Calibration on exiting Self-refresh */
80934 +#define ZQ_SFEXITEN_ENABLE 1
80935 +/*
80936 + * ZQ Calibration simultaneously on both chip-selects:
80937 + * Needs one calibration resistor per CS
80938 + */
80939 +#define ZQ_DUALCALEN_DISABLE 0
80940 +#define ZQ_DUALCALEN_ENABLE 1
80941 +
80942 +#define T_ZQCS_DEFAULT_NS 90
80943 +#define T_ZQCL_DEFAULT_NS 360
80944 +#define T_ZQINIT_DEFAULT_NS 1000
80945 +
80946 +/* DPD_EN */
80947 +#define DPD_DISABLE 0
80948 +#define DPD_ENABLE 1
80949 +
80950 +/*
80951 + * Default values for the low-power entry to be used if not provided by user.
80952 + * OMAP4/5 has a hw bug(i735) due to which this value can not be less than 512
80953 + * Timeout values are in DDR clock 'cycles' and frequency threshold in Hz
80954 + */
80955 +#define EMIF_LP_MODE_TIMEOUT_PERFORMANCE 2048
80956 +#define EMIF_LP_MODE_TIMEOUT_POWER 512
80957 +#define EMIF_LP_MODE_FREQ_THRESHOLD 400000000
80958 +
80959 +/* DDR_PHY_CTRL_1 values for EMIF4D - ATTILA PHY combination */
80960 +#define EMIF_DDR_PHY_CTRL_1_BASE_VAL_ATTILAPHY 0x049FF000
80961 +#define EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ_ATTILAPHY 0x41
80962 +#define EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ_ATTILAPHY 0x80
80963 +#define EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS_ATTILAPHY 0xFF
80964 +
80965 +/* DDR_PHY_CTRL_1 values for EMIF4D5 INTELLIPHY combination */
80966 +#define EMIF_DDR_PHY_CTRL_1_BASE_VAL_INTELLIPHY 0x0E084200
80967 +#define EMIF_PHY_TOTAL_READ_LATENCY_INTELLIPHY_PS 10000
80968 +
80969 +/* TEMP_ALERT_CONFIG - corresponding to temp gradient 5 C/s */
80970 +#define TEMP_ALERT_POLL_INTERVAL_DEFAULT_MS 360
80971 +
80972 +#define EMIF_T_CSTA 3
80973 +#define EMIF_T_PDLL_UL 128
80974 +
80975 +/* External PHY control registers magic values */
80976 +#define EMIF_EXT_PHY_CTRL_1_VAL 0x04020080
80977 +#define EMIF_EXT_PHY_CTRL_5_VAL 0x04010040
80978 +#define EMIF_EXT_PHY_CTRL_6_VAL 0x01004010
80979 +#define EMIF_EXT_PHY_CTRL_7_VAL 0x00001004
80980 +#define EMIF_EXT_PHY_CTRL_8_VAL 0x04010040
80981 +#define EMIF_EXT_PHY_CTRL_9_VAL 0x01004010
80982 +#define EMIF_EXT_PHY_CTRL_10_VAL 0x00001004
80983 +#define EMIF_EXT_PHY_CTRL_11_VAL 0x00000000
80984 +#define EMIF_EXT_PHY_CTRL_12_VAL 0x00000000
80985 +#define EMIF_EXT_PHY_CTRL_13_VAL 0x00000000
80986 +#define EMIF_EXT_PHY_CTRL_14_VAL 0x80080080
80987 +#define EMIF_EXT_PHY_CTRL_15_VAL 0x00800800
80988 +#define EMIF_EXT_PHY_CTRL_16_VAL 0x08102040
80989 +#define EMIF_EXT_PHY_CTRL_17_VAL 0x00000001
80990 +#define EMIF_EXT_PHY_CTRL_18_VAL 0x540A8150
80991 +#define EMIF_EXT_PHY_CTRL_19_VAL 0xA81502A0
80992 +#define EMIF_EXT_PHY_CTRL_20_VAL 0x002A0540
80993 +#define EMIF_EXT_PHY_CTRL_21_VAL 0x00000000
80994 +#define EMIF_EXT_PHY_CTRL_22_VAL 0x00000000
80995 +#define EMIF_EXT_PHY_CTRL_23_VAL 0x00000000
80996 +#define EMIF_EXT_PHY_CTRL_24_VAL 0x00000077
80997 +
80998 +#define EMIF_INTELLI_PHY_DQS_GATE_OPENING_DELAY_PS 1200
80999 +
81000 +/* Registers offset */
81001 +#define EMIF_MODULE_ID_AND_REVISION 0x0000
81002 +#define EMIF_STATUS 0x0004
81003 +#define EMIF_SDRAM_CONFIG 0x0008
81004 +#define EMIF_SDRAM_CONFIG_2 0x000c
81005 +#define EMIF_SDRAM_REFRESH_CONTROL 0x0010
81006 +#define EMIF_SDRAM_REFRESH_CTRL_SHDW 0x0014
81007 +#define EMIF_SDRAM_TIMING_1 0x0018
81008 +#define EMIF_SDRAM_TIMING_1_SHDW 0x001c
81009 +#define EMIF_SDRAM_TIMING_2 0x0020
81010 +#define EMIF_SDRAM_TIMING_2_SHDW 0x0024
81011 +#define EMIF_SDRAM_TIMING_3 0x0028
81012 +#define EMIF_SDRAM_TIMING_3_SHDW 0x002c
81013 +#define EMIF_LPDDR2_NVM_TIMING 0x0030
81014 +#define EMIF_LPDDR2_NVM_TIMING_SHDW 0x0034
81015 +#define EMIF_POWER_MANAGEMENT_CONTROL 0x0038
81016 +#define EMIF_POWER_MANAGEMENT_CTRL_SHDW 0x003c
81017 +#define EMIF_LPDDR2_MODE_REG_DATA 0x0040
81018 +#define EMIF_LPDDR2_MODE_REG_CONFIG 0x0050
81019 +#define EMIF_OCP_CONFIG 0x0054
81020 +#define EMIF_OCP_CONFIG_VALUE_1 0x0058
81021 +#define EMIF_OCP_CONFIG_VALUE_2 0x005c
81022 +#define EMIF_IODFT_TEST_LOGIC_GLOBAL_CONTROL 0x0060
81023 +#define EMIF_IODFT_TEST_LOGIC_CTRL_MISR_RESULT 0x0064
81024 +#define EMIF_IODFT_TEST_LOGIC_ADDRESS_MISR_RESULT 0x0068
81025 +#define EMIF_IODFT_TEST_LOGIC_DATA_MISR_RESULT_1 0x006c
81026 +#define EMIF_IODFT_TEST_LOGIC_DATA_MISR_RESULT_2 0x0070
81027 +#define EMIF_IODFT_TEST_LOGIC_DATA_MISR_RESULT_3 0x0074
81028 +#define EMIF_PERFORMANCE_COUNTER_1 0x0080
81029 +#define EMIF_PERFORMANCE_COUNTER_2 0x0084
81030 +#define EMIF_PERFORMANCE_COUNTER_CONFIG 0x0088
81031 +#define EMIF_PERFORMANCE_COUNTER_MASTER_REGION_SELECT 0x008c
81032 +#define EMIF_PERFORMANCE_COUNTER_TIME 0x0090
81033 +#define EMIF_MISC_REG 0x0094
81034 +#define EMIF_DLL_CALIB_CTRL 0x0098
81035 +#define EMIF_DLL_CALIB_CTRL_SHDW 0x009c
81036 +#define EMIF_END_OF_INTERRUPT 0x00a0
81037 +#define EMIF_SYSTEM_OCP_INTERRUPT_RAW_STATUS 0x00a4
81038 +#define EMIF_LL_OCP_INTERRUPT_RAW_STATUS 0x00a8
81039 +#define EMIF_SYSTEM_OCP_INTERRUPT_STATUS 0x00ac
81040 +#define EMIF_LL_OCP_INTERRUPT_STATUS 0x00b0
81041 +#define EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_SET 0x00b4
81042 +#define EMIF_LL_OCP_INTERRUPT_ENABLE_SET 0x00b8
81043 +#define EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_CLEAR 0x00bc
81044 +#define EMIF_LL_OCP_INTERRUPT_ENABLE_CLEAR 0x00c0
81045 +#define EMIF_SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG 0x00c8
81046 +#define EMIF_TEMPERATURE_ALERT_CONFIG 0x00cc
81047 +#define EMIF_OCP_ERROR_LOG 0x00d0
81048 +#define EMIF_READ_WRITE_LEVELING_RAMP_WINDOW 0x00d4
81049 +#define EMIF_READ_WRITE_LEVELING_RAMP_CONTROL 0x00d8
81050 +#define EMIF_READ_WRITE_LEVELING_CONTROL 0x00dc
81051 +#define EMIF_DDR_PHY_CTRL_1 0x00e4
81052 +#define EMIF_DDR_PHY_CTRL_1_SHDW 0x00e8
81053 +#define EMIF_DDR_PHY_CTRL_2 0x00ec
81054 +#define EMIF_PRIORITY_TO_CLASS_OF_SERVICE_MAPPING 0x0100
81055 +#define EMIF_CONNECTION_ID_TO_CLASS_OF_SERVICE_1_MAPPING 0x0104
81056 +#define EMIF_CONNECTION_ID_TO_CLASS_OF_SERVICE_2_MAPPING 0x0108
81057 +#define EMIF_READ_WRITE_EXECUTION_THRESHOLD 0x0120
81058 +#define EMIF_COS_CONFIG 0x0124
81059 +#define EMIF_PHY_STATUS_1 0x0140
81060 +#define EMIF_PHY_STATUS_2 0x0144
81061 +#define EMIF_PHY_STATUS_3 0x0148
81062 +#define EMIF_PHY_STATUS_4 0x014c
81063 +#define EMIF_PHY_STATUS_5 0x0150
81064 +#define EMIF_PHY_STATUS_6 0x0154
81065 +#define EMIF_PHY_STATUS_7 0x0158
81066 +#define EMIF_PHY_STATUS_8 0x015c
81067 +#define EMIF_PHY_STATUS_9 0x0160
81068 +#define EMIF_PHY_STATUS_10 0x0164
81069 +#define EMIF_PHY_STATUS_11 0x0168
81070 +#define EMIF_PHY_STATUS_12 0x016c
81071 +#define EMIF_PHY_STATUS_13 0x0170
81072 +#define EMIF_PHY_STATUS_14 0x0174
81073 +#define EMIF_PHY_STATUS_15 0x0178
81074 +#define EMIF_PHY_STATUS_16 0x017c
81075 +#define EMIF_PHY_STATUS_17 0x0180
81076 +#define EMIF_PHY_STATUS_18 0x0184
81077 +#define EMIF_PHY_STATUS_19 0x0188
81078 +#define EMIF_PHY_STATUS_20 0x018c
81079 +#define EMIF_PHY_STATUS_21 0x0190
81080 +#define EMIF_EXT_PHY_CTRL_1 0x0200
81081 +#define EMIF_EXT_PHY_CTRL_1_SHDW 0x0204
81082 +#define EMIF_EXT_PHY_CTRL_2 0x0208
81083 +#define EMIF_EXT_PHY_CTRL_2_SHDW 0x020c
81084 +#define EMIF_EXT_PHY_CTRL_3 0x0210
81085 +#define EMIF_EXT_PHY_CTRL_3_SHDW 0x0214
81086 +#define EMIF_EXT_PHY_CTRL_4 0x0218
81087 +#define EMIF_EXT_PHY_CTRL_4_SHDW 0x021c
81088 +#define EMIF_EXT_PHY_CTRL_5 0x0220
81089 +#define EMIF_EXT_PHY_CTRL_5_SHDW 0x0224
81090 +#define EMIF_EXT_PHY_CTRL_6 0x0228
81091 +#define EMIF_EXT_PHY_CTRL_6_SHDW 0x022c
81092 +#define EMIF_EXT_PHY_CTRL_7 0x0230
81093 +#define EMIF_EXT_PHY_CTRL_7_SHDW 0x0234
81094 +#define EMIF_EXT_PHY_CTRL_8 0x0238
81095 +#define EMIF_EXT_PHY_CTRL_8_SHDW 0x023c
81096 +#define EMIF_EXT_PHY_CTRL_9 0x0240
81097 +#define EMIF_EXT_PHY_CTRL_9_SHDW 0x0244
81098 +#define EMIF_EXT_PHY_CTRL_10 0x0248
81099 +#define EMIF_EXT_PHY_CTRL_10_SHDW 0x024c
81100 +#define EMIF_EXT_PHY_CTRL_11 0x0250
81101 +#define EMIF_EXT_PHY_CTRL_11_SHDW 0x0254
81102 +#define EMIF_EXT_PHY_CTRL_12 0x0258
81103 +#define EMIF_EXT_PHY_CTRL_12_SHDW 0x025c
81104 +#define EMIF_EXT_PHY_CTRL_13 0x0260
81105 +#define EMIF_EXT_PHY_CTRL_13_SHDW 0x0264
81106 +#define EMIF_EXT_PHY_CTRL_14 0x0268
81107 +#define EMIF_EXT_PHY_CTRL_14_SHDW 0x026c
81108 +#define EMIF_EXT_PHY_CTRL_15 0x0270
81109 +#define EMIF_EXT_PHY_CTRL_15_SHDW 0x0274
81110 +#define EMIF_EXT_PHY_CTRL_16 0x0278
81111 +#define EMIF_EXT_PHY_CTRL_16_SHDW 0x027c
81112 +#define EMIF_EXT_PHY_CTRL_17 0x0280
81113 +#define EMIF_EXT_PHY_CTRL_17_SHDW 0x0284
81114 +#define EMIF_EXT_PHY_CTRL_18 0x0288
81115 +#define EMIF_EXT_PHY_CTRL_18_SHDW 0x028c
81116 +#define EMIF_EXT_PHY_CTRL_19 0x0290
81117 +#define EMIF_EXT_PHY_CTRL_19_SHDW 0x0294
81118 +#define EMIF_EXT_PHY_CTRL_20 0x0298
81119 +#define EMIF_EXT_PHY_CTRL_20_SHDW 0x029c
81120 +#define EMIF_EXT_PHY_CTRL_21 0x02a0
81121 +#define EMIF_EXT_PHY_CTRL_21_SHDW 0x02a4
81122 +#define EMIF_EXT_PHY_CTRL_22 0x02a8
81123 +#define EMIF_EXT_PHY_CTRL_22_SHDW 0x02ac
81124 +#define EMIF_EXT_PHY_CTRL_23 0x02b0
81125 +#define EMIF_EXT_PHY_CTRL_23_SHDW 0x02b4
81126 +#define EMIF_EXT_PHY_CTRL_24 0x02b8
81127 +#define EMIF_EXT_PHY_CTRL_24_SHDW 0x02bc
81128 +#define EMIF_EXT_PHY_CTRL_25 0x02c0
81129 +#define EMIF_EXT_PHY_CTRL_25_SHDW 0x02c4
81130 +#define EMIF_EXT_PHY_CTRL_26 0x02c8
81131 +#define EMIF_EXT_PHY_CTRL_26_SHDW 0x02cc
81132 +#define EMIF_EXT_PHY_CTRL_27 0x02d0
81133 +#define EMIF_EXT_PHY_CTRL_27_SHDW 0x02d4
81134 +#define EMIF_EXT_PHY_CTRL_28 0x02d8
81135 +#define EMIF_EXT_PHY_CTRL_28_SHDW 0x02dc
81136 +#define EMIF_EXT_PHY_CTRL_29 0x02e0
81137 +#define EMIF_EXT_PHY_CTRL_29_SHDW 0x02e4
81138 +#define EMIF_EXT_PHY_CTRL_30 0x02e8
81139 +#define EMIF_EXT_PHY_CTRL_30_SHDW 0x02ec
81140 +
81141 +/* Registers shifts and masks */
81142 +
81143 +/* EMIF_MODULE_ID_AND_REVISION */
81144 +#define SCHEME_SHIFT 30
81145 +#define SCHEME_MASK (0x3 << 30)
81146 +#define MODULE_ID_SHIFT 16
81147 +#define MODULE_ID_MASK (0xfff << 16)
81148 +#define RTL_VERSION_SHIFT 11
81149 +#define RTL_VERSION_MASK (0x1f << 11)
81150 +#define MAJOR_REVISION_SHIFT 8
81151 +#define MAJOR_REVISION_MASK (0x7 << 8)
81152 +#define MINOR_REVISION_SHIFT 0
81153 +#define MINOR_REVISION_MASK (0x3f << 0)
81154 +
81155 +/* STATUS */
81156 +#define BE_SHIFT 31
81157 +#define BE_MASK (1 << 31)
81158 +#define DUAL_CLK_MODE_SHIFT 30
81159 +#define DUAL_CLK_MODE_MASK (1 << 30)
81160 +#define FAST_INIT_SHIFT 29
81161 +#define FAST_INIT_MASK (1 << 29)
81162 +#define RDLVLGATETO_SHIFT 6
81163 +#define RDLVLGATETO_MASK (1 << 6)
81164 +#define RDLVLTO_SHIFT 5
81165 +#define RDLVLTO_MASK (1 << 5)
81166 +#define WRLVLTO_SHIFT 4
81167 +#define WRLVLTO_MASK (1 << 4)
81168 +#define PHY_DLL_READY_SHIFT 2
81169 +#define PHY_DLL_READY_MASK (1 << 2)
81170 +
81171 +/* SDRAM_CONFIG */
81172 +#define SDRAM_TYPE_SHIFT 29
81173 +#define SDRAM_TYPE_MASK (0x7 << 29)
81174 +#define IBANK_POS_SHIFT 27
81175 +#define IBANK_POS_MASK (0x3 << 27)
81176 +#define DDR_TERM_SHIFT 24
81177 +#define DDR_TERM_MASK (0x7 << 24)
81178 +#define DDR2_DDQS_SHIFT 23
81179 +#define DDR2_DDQS_MASK (1 << 23)
81180 +#define DYN_ODT_SHIFT 21
81181 +#define DYN_ODT_MASK (0x3 << 21)
81182 +#define DDR_DISABLE_DLL_SHIFT 20
81183 +#define DDR_DISABLE_DLL_MASK (1 << 20)
81184 +#define SDRAM_DRIVE_SHIFT 18
81185 +#define SDRAM_DRIVE_MASK (0x3 << 18)
81186 +#define CWL_SHIFT 16
81187 +#define CWL_MASK (0x3 << 16)
81188 +#define NARROW_MODE_SHIFT 14
81189 +#define NARROW_MODE_MASK (0x3 << 14)
81190 +#define CL_SHIFT 10
81191 +#define CL_MASK (0xf << 10)
81192 +#define ROWSIZE_SHIFT 7
81193 +#define ROWSIZE_MASK (0x7 << 7)
81194 +#define IBANK_SHIFT 4
81195 +#define IBANK_MASK (0x7 << 4)
81196 +#define EBANK_SHIFT 3
81197 +#define EBANK_MASK (1 << 3)
81198 +#define PAGESIZE_SHIFT 0
81199 +#define PAGESIZE_MASK (0x7 << 0)
81200 +
81201 +/* SDRAM_CONFIG_2 */
81202 +#define CS1NVMEN_SHIFT 30
81203 +#define CS1NVMEN_MASK (1 << 30)
81204 +#define EBANK_POS_SHIFT 27
81205 +#define EBANK_POS_MASK (1 << 27)
81206 +#define RDBNUM_SHIFT 4
81207 +#define RDBNUM_MASK (0x3 << 4)
81208 +#define RDBSIZE_SHIFT 0
81209 +#define RDBSIZE_MASK (0x7 << 0)
81210 +
81211 +/* SDRAM_REFRESH_CONTROL */
81212 +#define INITREF_DIS_SHIFT 31
81213 +#define INITREF_DIS_MASK (1 << 31)
81214 +#define SRT_SHIFT 29
81215 +#define SRT_MASK (1 << 29)
81216 +#define ASR_SHIFT 28
81217 +#define ASR_MASK (1 << 28)
81218 +#define PASR_SHIFT 24
81219 +#define PASR_MASK (0x7 << 24)
81220 +#define REFRESH_RATE_SHIFT 0
81221 +#define REFRESH_RATE_MASK (0xffff << 0)
81222 +
81223 +/* SDRAM_TIMING_1 */
81224 +#define T_RTW_SHIFT 29
81225 +#define T_RTW_MASK (0x7 << 29)
81226 +#define T_RP_SHIFT 25
81227 +#define T_RP_MASK (0xf << 25)
81228 +#define T_RCD_SHIFT 21
81229 +#define T_RCD_MASK (0xf << 21)
81230 +#define T_WR_SHIFT 17
81231 +#define T_WR_MASK (0xf << 17)
81232 +#define T_RAS_SHIFT 12
81233 +#define T_RAS_MASK (0x1f << 12)
81234 +#define T_RC_SHIFT 6
81235 +#define T_RC_MASK (0x3f << 6)
81236 +#define T_RRD_SHIFT 3
81237 +#define T_RRD_MASK (0x7 << 3)
81238 +#define T_WTR_SHIFT 0
81239 +#define T_WTR_MASK (0x7 << 0)
81240 +
81241 +/* SDRAM_TIMING_2 */
81242 +#define T_XP_SHIFT 28
81243 +#define T_XP_MASK (0x7 << 28)
81244 +#define T_ODT_SHIFT 25
81245 +#define T_ODT_MASK (0x7 << 25)
81246 +#define T_XSNR_SHIFT 16
81247 +#define T_XSNR_MASK (0x1ff << 16)
81248 +#define T_XSRD_SHIFT 6
81249 +#define T_XSRD_MASK (0x3ff << 6)
81250 +#define T_RTP_SHIFT 3
81251 +#define T_RTP_MASK (0x7 << 3)
81252 +#define T_CKE_SHIFT 0
81253 +#define T_CKE_MASK (0x7 << 0)
81254 +
81255 +/* SDRAM_TIMING_3 */
81256 +#define T_PDLL_UL_SHIFT 28
81257 +#define T_PDLL_UL_MASK (0xf << 28)
81258 +#define T_CSTA_SHIFT 24
81259 +#define T_CSTA_MASK (0xf << 24)
81260 +#define T_CKESR_SHIFT 21
81261 +#define T_CKESR_MASK (0x7 << 21)
81262 +#define ZQ_ZQCS_SHIFT 15
81263 +#define ZQ_ZQCS_MASK (0x3f << 15)
81264 +#define T_TDQSCKMAX_SHIFT 13
81265 +#define T_TDQSCKMAX_MASK (0x3 << 13)
81266 +#define T_RFC_SHIFT 4
81267 +#define T_RFC_MASK (0x1ff << 4)
81268 +#define T_RAS_MAX_SHIFT 0
81269 +#define T_RAS_MAX_MASK (0xf << 0)
81270 +
81271 +/* POWER_MANAGEMENT_CONTROL */
81272 +#define PD_TIM_SHIFT 12
81273 +#define PD_TIM_MASK (0xf << 12)
81274 +#define DPD_EN_SHIFT 11
81275 +#define DPD_EN_MASK (1 << 11)
81276 +#define LP_MODE_SHIFT 8
81277 +#define LP_MODE_MASK (0x7 << 8)
81278 +#define SR_TIM_SHIFT 4
81279 +#define SR_TIM_MASK (0xf << 4)
81280 +#define CS_TIM_SHIFT 0
81281 +#define CS_TIM_MASK (0xf << 0)
81282 +
81283 +/* LPDDR2_MODE_REG_DATA */
81284 +#define VALUE_0_SHIFT 0
81285 +#define VALUE_0_MASK (0x7f << 0)
81286 +
81287 +/* LPDDR2_MODE_REG_CONFIG */
81288 +#define CS_SHIFT 31
81289 +#define CS_MASK (1 << 31)
81290 +#define REFRESH_EN_SHIFT 30
81291 +#define REFRESH_EN_MASK (1 << 30)
81292 +#define ADDRESS_SHIFT 0
81293 +#define ADDRESS_MASK (0xff << 0)
81294 +
81295 +/* OCP_CONFIG */
81296 +#define SYS_THRESH_MAX_SHIFT 24
81297 +#define SYS_THRESH_MAX_MASK (0xf << 24)
81298 +#define MPU_THRESH_MAX_SHIFT 20
81299 +#define MPU_THRESH_MAX_MASK (0xf << 20)
81300 +#define LL_THRESH_MAX_SHIFT 16
81301 +#define LL_THRESH_MAX_MASK (0xf << 16)
81302 +
81303 +/* PERFORMANCE_COUNTER_1 */
81304 +#define COUNTER1_SHIFT 0
81305 +#define COUNTER1_MASK (0xffffffff << 0)
81306 +
81307 +/* PERFORMANCE_COUNTER_2 */
81308 +#define COUNTER2_SHIFT 0
81309 +#define COUNTER2_MASK (0xffffffff << 0)
81310 +
81311 +/* PERFORMANCE_COUNTER_CONFIG */
81312 +#define CNTR2_MCONNID_EN_SHIFT 31
81313 +#define CNTR2_MCONNID_EN_MASK (1 << 31)
81314 +#define CNTR2_REGION_EN_SHIFT 30
81315 +#define CNTR2_REGION_EN_MASK (1 << 30)
81316 +#define CNTR2_CFG_SHIFT 16
81317 +#define CNTR2_CFG_MASK (0xf << 16)
81318 +#define CNTR1_MCONNID_EN_SHIFT 15
81319 +#define CNTR1_MCONNID_EN_MASK (1 << 15)
81320 +#define CNTR1_REGION_EN_SHIFT 14
81321 +#define CNTR1_REGION_EN_MASK (1 << 14)
81322 +#define CNTR1_CFG_SHIFT 0
81323 +#define CNTR1_CFG_MASK (0xf << 0)
81324 +
81325 +/* PERFORMANCE_COUNTER_MASTER_REGION_SELECT */
81326 +#define MCONNID2_SHIFT 24
81327 +#define MCONNID2_MASK (0xff << 24)
81328 +#define REGION_SEL2_SHIFT 16
81329 +#define REGION_SEL2_MASK (0x3 << 16)
81330 +#define MCONNID1_SHIFT 8
81331 +#define MCONNID1_MASK (0xff << 8)
81332 +#define REGION_SEL1_SHIFT 0
81333 +#define REGION_SEL1_MASK (0x3 << 0)
81334 +
81335 +/* PERFORMANCE_COUNTER_TIME */
81336 +#define TOTAL_TIME_SHIFT 0
81337 +#define TOTAL_TIME_MASK (0xffffffff << 0)
81338 +
81339 +/* DLL_CALIB_CTRL */
81340 +#define ACK_WAIT_SHIFT 16
81341 +#define ACK_WAIT_MASK (0xf << 16)
81342 +#define DLL_CALIB_INTERVAL_SHIFT 0
81343 +#define DLL_CALIB_INTERVAL_MASK (0x1ff << 0)
81344 +
81345 +/* END_OF_INTERRUPT */
81346 +#define EOI_SHIFT 0
81347 +#define EOI_MASK (1 << 0)
81348 +
81349 +/* SYSTEM_OCP_INTERRUPT_RAW_STATUS */
81350 +#define DNV_SYS_SHIFT 2
81351 +#define DNV_SYS_MASK (1 << 2)
81352 +#define TA_SYS_SHIFT 1
81353 +#define TA_SYS_MASK (1 << 1)
81354 +#define ERR_SYS_SHIFT 0
81355 +#define ERR_SYS_MASK (1 << 0)
81356 +
81357 +/* LOW_LATENCY_OCP_INTERRUPT_RAW_STATUS */
81358 +#define DNV_LL_SHIFT 2
81359 +#define DNV_LL_MASK (1 << 2)
81360 +#define TA_LL_SHIFT 1
81361 +#define TA_LL_MASK (1 << 1)
81362 +#define ERR_LL_SHIFT 0
81363 +#define ERR_LL_MASK (1 << 0)
81364 +
81365 +/* SYSTEM_OCP_INTERRUPT_ENABLE_SET */
81366 +#define EN_DNV_SYS_SHIFT 2
81367 +#define EN_DNV_SYS_MASK (1 << 2)
81368 +#define EN_TA_SYS_SHIFT 1
81369 +#define EN_TA_SYS_MASK (1 << 1)
81370 +#define EN_ERR_SYS_SHIFT 0
81371 +#define EN_ERR_SYS_MASK (1 << 0)
81372 +
81373 +/* LOW_LATENCY_OCP_INTERRUPT_ENABLE_SET */
81374 +#define EN_DNV_LL_SHIFT 2
81375 +#define EN_DNV_LL_MASK (1 << 2)
81376 +#define EN_TA_LL_SHIFT 1
81377 +#define EN_TA_LL_MASK (1 << 1)
81378 +#define EN_ERR_LL_SHIFT 0
81379 +#define EN_ERR_LL_MASK (1 << 0)
81380 +
81381 +/* SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG */
81382 +#define ZQ_CS1EN_SHIFT 31
81383 +#define ZQ_CS1EN_MASK (1 << 31)
81384 +#define ZQ_CS0EN_SHIFT 30
81385 +#define ZQ_CS0EN_MASK (1 << 30)
81386 +#define ZQ_DUALCALEN_SHIFT 29
81387 +#define ZQ_DUALCALEN_MASK (1 << 29)
81388 +#define ZQ_SFEXITEN_SHIFT 28
81389 +#define ZQ_SFEXITEN_MASK (1 << 28)
81390 +#define ZQ_ZQINIT_MULT_SHIFT 18
81391 +#define ZQ_ZQINIT_MULT_MASK (0x3 << 18)
81392 +#define ZQ_ZQCL_MULT_SHIFT 16
81393 +#define ZQ_ZQCL_MULT_MASK (0x3 << 16)
81394 +#define ZQ_REFINTERVAL_SHIFT 0
81395 +#define ZQ_REFINTERVAL_MASK (0xffff << 0)
81396 +
81397 +/* TEMPERATURE_ALERT_CONFIG */
81398 +#define TA_CS1EN_SHIFT 31
81399 +#define TA_CS1EN_MASK (1 << 31)
81400 +#define TA_CS0EN_SHIFT 30
81401 +#define TA_CS0EN_MASK (1 << 30)
81402 +#define TA_SFEXITEN_SHIFT 28
81403 +#define TA_SFEXITEN_MASK (1 << 28)
81404 +#define TA_DEVWDT_SHIFT 26
81405 +#define TA_DEVWDT_MASK (0x3 << 26)
81406 +#define TA_DEVCNT_SHIFT 24
81407 +#define TA_DEVCNT_MASK (0x3 << 24)
81408 +#define TA_REFINTERVAL_SHIFT 0
81409 +#define TA_REFINTERVAL_MASK (0x3fffff << 0)
81410 +
81411 +/* OCP_ERROR_LOG */
81412 +#define MADDRSPACE_SHIFT 14
81413 +#define MADDRSPACE_MASK (0x3 << 14)
81414 +#define MBURSTSEQ_SHIFT 11
81415 +#define MBURSTSEQ_MASK (0x7 << 11)
81416 +#define MCMD_SHIFT 8
81417 +#define MCMD_MASK (0x7 << 8)
81418 +#define MCONNID_SHIFT 0
81419 +#define MCONNID_MASK (0xff << 0)
81420 +
81421 +/* DDR_PHY_CTRL_1 - EMIF4D */
81422 +#define DLL_SLAVE_DLY_CTRL_SHIFT_4D 4
81423 +#define DLL_SLAVE_DLY_CTRL_MASK_4D (0xFF << 4)
81424 +#define READ_LATENCY_SHIFT_4D 0
81425 +#define READ_LATENCY_MASK_4D (0xf << 0)
81426 +
81427 +/* DDR_PHY_CTRL_1 - EMIF4D5 */
81428 +#define DLL_HALF_DELAY_SHIFT_4D5 21
81429 +#define DLL_HALF_DELAY_MASK_4D5 (1 << 21)
81430 +#define READ_LATENCY_SHIFT_4D5 0
81431 +#define READ_LATENCY_MASK_4D5 (0x1f << 0)
81432 +
81433 +/* DDR_PHY_CTRL_1_SHDW */
81434 +#define DDR_PHY_CTRL_1_SHDW_SHIFT 5
81435 +#define DDR_PHY_CTRL_1_SHDW_MASK (0x7ffffff << 5)
81436 +#define READ_LATENCY_SHDW_SHIFT 0
81437 +#define READ_LATENCY_SHDW_MASK (0x1f << 0)
81438 +
81439 +#endif /* __TI_EMIF_H */
81440 --- a/include/linux/usb/musb.h
81441 +++ b/include/linux/usb/musb.h
81442 @@ -99,8 +99,6 @@ struct musb_hdrc_platform_data {
81443 /* MUSB_HOST, MUSB_PERIPHERAL, or MUSB_OTG */
81444 u8 mode;
81445
81446 - u8 has_mailbox:1;
81447 -
81448 /* for clk_get() */
81449 const char *clock;
81450
81451 --- a/include/linux/usb/omap_control_usb.h
81452 +++ /dev/null
81453 @@ -1,92 +0,0 @@
81454 -/*
81455 - * omap_control_usb.h - Header file for the USB part of control module.
81456 - *
81457 - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
81458 - * This program is free software; you can redistribute it and/or modify
81459 - * it under the terms of the GNU General Public License as published by
81460 - * the Free Software Foundation; either version 2 of the License, or
81461 - * (at your option) any later version.
81462 - *
81463 - * Author: Kishon Vijay Abraham I <kishon@ti.com>
81464 - *
81465 - * This program is distributed in the hope that it will be useful,
81466 - * but WITHOUT ANY WARRANTY; without even the implied warranty of
81467 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
81468 - * GNU General Public License for more details.
81469 - *
81470 - */
81471 -
81472 -#ifndef __OMAP_CONTROL_USB_H__
81473 -#define __OMAP_CONTROL_USB_H__
81474 -
81475 -struct omap_control_usb {
81476 - struct device *dev;
81477 -
81478 - u32 __iomem *dev_conf;
81479 - u32 __iomem *otghs_control;
81480 - u32 __iomem *phy_power;
81481 -
81482 - struct clk *sys_clk;
81483 -
81484 - u32 type;
81485 -};
81486 -
81487 -struct omap_control_usb_platform_data {
81488 - u8 type;
81489 -};
81490 -
81491 -enum omap_control_usb_mode {
81492 - USB_MODE_UNDEFINED = 0,
81493 - USB_MODE_HOST,
81494 - USB_MODE_DEVICE,
81495 - USB_MODE_DISCONNECT,
81496 -};
81497 -
81498 -/* To differentiate ctrl module IP having either mailbox or USB3 PHY power */
81499 -#define OMAP_CTRL_DEV_TYPE1 0x1
81500 -#define OMAP_CTRL_DEV_TYPE2 0x2
81501 -
81502 -#define OMAP_CTRL_DEV_PHY_PD BIT(0)
81503 -
81504 -#define OMAP_CTRL_DEV_AVALID BIT(0)
81505 -#define OMAP_CTRL_DEV_BVALID BIT(1)
81506 -#define OMAP_CTRL_DEV_VBUSVALID BIT(2)
81507 -#define OMAP_CTRL_DEV_SESSEND BIT(3)
81508 -#define OMAP_CTRL_DEV_IDDIG BIT(4)
81509 -
81510 -#define OMAP_CTRL_USB_PWRCTL_CLK_CMD_MASK 0x003FC000
81511 -#define OMAP_CTRL_USB_PWRCTL_CLK_CMD_SHIFT 0xE
81512 -
81513 -#define OMAP_CTRL_USB_PWRCTL_CLK_FREQ_MASK 0xFFC00000
81514 -#define OMAP_CTRL_USB_PWRCTL_CLK_FREQ_SHIFT 0x16
81515 -
81516 -#define OMAP_CTRL_USB3_PHY_TX_RX_POWERON 0x3
81517 -#define OMAP_CTRL_USB3_PHY_TX_RX_POWEROFF 0x0
81518 -
81519 -#if IS_ENABLED(CONFIG_OMAP_CONTROL_USB)
81520 -extern struct device *omap_get_control_dev(void);
81521 -extern void omap_control_usb_phy_power(struct device *dev, int on);
81522 -extern void omap_control_usb3_phy_power(struct device *dev, bool on);
81523 -extern void omap_control_usb_set_mode(struct device *dev,
81524 - enum omap_control_usb_mode mode);
81525 -#else
81526 -static inline struct device *omap_get_control_dev(void)
81527 -{
81528 - return ERR_PTR(-ENODEV);
81529 -}
81530 -
81531 -static inline void omap_control_usb_phy_power(struct device *dev, int on)
81532 -{
81533 -}
81534 -
81535 -static inline void omap_control_usb3_phy_power(struct device *dev, int on)
81536 -{
81537 -}
81538 -
81539 -static inline void omap_control_usb_set_mode(struct device *dev,
81540 - enum omap_control_usb_mode mode)
81541 -{
81542 -}
81543 -#endif
81544 -
81545 -#endif /* __OMAP_CONTROL_USB_H__ */
81546 --- a/include/linux/usb/omap_usb.h
81547 +++ /dev/null
81548 @@ -1,67 +0,0 @@
81549 -/*
81550 - * omap_usb.h -- omap usb2 phy header file
81551 - *
81552 - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com
81553 - * This program is free software; you can redistribute it and/or modify
81554 - * it under the terms of the GNU General Public License as published by
81555 - * the Free Software Foundation; either version 2 of the License, or
81556 - * (at your option) any later version.
81557 - *
81558 - * Author: Kishon Vijay Abraham I <kishon@ti.com>
81559 - *
81560 - * This program is distributed in the hope that it will be useful,
81561 - * but WITHOUT ANY WARRANTY; without even the implied warranty of
81562 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
81563 - * GNU General Public License for more details.
81564 - *
81565 - */
81566 -
81567 -#ifndef __DRIVERS_OMAP_USB2_H
81568 -#define __DRIVERS_OMAP_USB2_H
81569 -
81570 -#include <linux/io.h>
81571 -#include <linux/usb/otg.h>
81572 -
81573 -struct usb_dpll_params {
81574 - u16 m;
81575 - u8 n;
81576 - u8 freq:3;
81577 - u8 sd;
81578 - u32 mf;
81579 -};
81580 -
81581 -struct omap_usb {
81582 - struct usb_phy phy;
81583 - struct phy_companion *comparator;
81584 - void __iomem *pll_ctrl_base;
81585 - struct device *dev;
81586 - struct device *control_dev;
81587 - struct clk *wkupclk;
81588 - struct clk *sys_clk;
81589 - struct clk *optclk;
81590 - u8 is_suspended:1;
81591 -};
81592 -
81593 -#define phy_to_omapusb(x) container_of((x), struct omap_usb, phy)
81594 -
81595 -#if defined(CONFIG_OMAP_USB2) || defined(CONFIG_OMAP_USB2_MODULE)
81596 -extern int omap_usb2_set_comparator(struct phy_companion *comparator);
81597 -#else
81598 -static inline int omap_usb2_set_comparator(struct phy_companion *comparator)
81599 -{
81600 - return -ENODEV;
81601 -}
81602 -#endif
81603 -
81604 -static inline u32 omap_usb_readl(void __iomem *addr, unsigned offset)
81605 -{
81606 - return __raw_readl(addr + offset);
81607 -}
81608 -
81609 -static inline void omap_usb_writel(void __iomem *addr, unsigned offset,
81610 - u32 data)
81611 -{
81612 - __raw_writel(data, addr + offset);
81613 -}
81614 -
81615 -#endif /* __DRIVERS_OMAP_USB_H */
81616 --- a/include/linux/usb/usb_phy_gen_xceiv.h
81617 +++ b/include/linux/usb/usb_phy_gen_xceiv.h
81618 @@ -9,7 +9,8 @@ struct usb_phy_gen_xceiv_platform_data {
81619
81620 /* if set fails with -EPROBE_DEFER if can't get regulator */
81621 unsigned int needs_vcc:1;
81622 - unsigned int needs_reset:1;
81623 + unsigned int needs_reset:1; /* deprecated */
81624 + int gpio_reset;
81625 };
81626
81627 #if defined(CONFIG_NOP_USB_XCEIV) || (defined(CONFIG_NOP_USB_XCEIV_MODULE) && defined(MODULE))
81628 --- a/include/uapi/linux/v4l2-controls.h
81629 +++ b/include/uapi/linux/v4l2-controls.h
81630 @@ -160,6 +160,10 @@ enum v4l2_colorfx {
81631 * of controls. Total of 16 controls is reserved for this driver */
81632 #define V4L2_CID_USER_SI476X_BASE (V4L2_CID_USER_BASE + 0x1040)
81633
81634 +/* The base for the TI VPE driver controls. Total of 16 controls is reserved for
81635 + * this driver */
81636 +#define V4L2_CID_USER_TI_VPE_BASE (V4L2_CID_USER_BASE + 0x1050)
81637 +
81638 /* MPEG-class control IDs */
81639 /* The MPEG controls are applicable to all codec controls
81640 * and the 'MPEG' part of the define is historical */
81641 --- a/include/video/da8xx-fb.h
81642 +++ b/include/video/da8xx-fb.h
81643 @@ -12,6 +12,8 @@
81644 #ifndef DA8XX_FB_H
81645 #define DA8XX_FB_H
81646
81647 +#include <linux/fb.h>
81648 +
81649 enum panel_shade {
81650 MONOCHROME = 0,
81651 COLOR_ACTIVE,
81652 @@ -91,5 +93,22 @@ struct lcd_sync_arg {
81653 /* Proprietary FB_SYNC_ flags */
81654 #define FB_SYNC_CLK_INVERT 0x40000000
81655
81656 +struct da8xx_encoder {
81657 + struct list_head list; /* internal use only */
81658 + struct i2c_client *client;
81659 + void *priv;
81660 + void (*set_mode)(struct da8xx_encoder *encoder,
81661 + struct fb_videomode *panel);
81662 + struct device_node *node;
81663 +};
81664 +
81665 +void da8xx_register_encoder(struct da8xx_encoder *encoder);
81666 +void da8xx_unregister_encoder(struct da8xx_encoder *encoder);
81667 +
81668 +
81669 +typedef void (*vsync_callback_t)(void *arg);
81670 +int register_vsync_cb(vsync_callback_t handler, void *arg, int idx);
81671 +int unregister_vsync_cb(vsync_callback_t handler, void *arg, int idx);
81672 +
81673 #endif /* ifndef DA8XX_FB_H */
81674
81675 --- /dev/null
81676 +++ b/include/video/da8xx-tda998x-hdmi.h
81677 @@ -0,0 +1,35 @@
81678 +/*
81679 + * Header file for TI DA8XX/TDA998x Encoder Driver
81680 + *
81681 + * Copyright (C) 2013 Texas Instruments Inc
81682 + *
81683 + * This file is licensed under the terms of the GNU General Public License
81684 + * version 2. This program is licensed "as is" without any warranty of any
81685 + * kind, whether express or implied.
81686 + */
81687 +
81688 +#ifndef DA8XX_TDA998X_HDMI_H
81689 +#define DA8XX_TDA998X_HDMI_H
81690 +
81691 +#include <linux/fb.h>
81692 +
81693 +enum tda998x_audio_format {
81694 + AFMT_I2S,
81695 + AFMT_SPDIF,
81696 +};
81697 +
81698 +struct tda998x_encoder_params {
81699 + int audio_cfg;
81700 + int audio_clk_cfg;
81701 + enum tda998x_audio_format audio_format;
81702 + int audio_sample_rate;
81703 + char audio_frame[6];
81704 + int swap_a, mirr_a;
81705 + int swap_b, mirr_b;
81706 + int swap_c, mirr_c;
81707 + int swap_d, mirr_d;
81708 + int swap_e, mirr_e;
81709 + int swap_f, mirr_f;
81710 +};
81711 +
81712 +#endif
81713 --- a/include/video/omapdss.h
81714 +++ b/include/video/omapdss.h
81715 @@ -227,6 +227,8 @@ enum omap_dss_output_id {
81716 OMAP_DSS_OUTPUT_DSI2 = 1 << 4,
81717 OMAP_DSS_OUTPUT_VENC = 1 << 5,
81718 OMAP_DSS_OUTPUT_HDMI = 1 << 6,
81719 + OMAP_DSS_OUTPUT_DPI1 = 1 << 7,
81720 + OMAP_DSS_OUTPUT_DPI2 = 1 << 8,
81721 };
81722
81723 /* RFBI */
81724 @@ -319,6 +321,8 @@ enum omapdss_version {
81725 OMAPDSS_VER_OMAP4430_ES2, /* OMAP4430 ES2.0, 2.1, 2.2 */
81726 OMAPDSS_VER_OMAP4, /* All other OMAP4s */
81727 OMAPDSS_VER_OMAP5,
81728 + OMAPDSS_VER_DRA7xx,
81729 + OMAPDSS_VER_AM43xx,
81730 };
81731
81732 /* Board specific data */
81733 @@ -961,6 +965,10 @@ int dispc_ovl_enable(enum omap_plane pla
81734 bool dispc_ovl_enabled(enum omap_plane plane);
81735 void dispc_ovl_set_channel_out(enum omap_plane plane,
81736 enum omap_channel channel);
81737 +void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
81738 + u32 *fifo_low, u32 *fifo_high, bool use_fifomerge,
81739 + bool manual_update);
81740 +void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high);
81741 int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi,
81742 bool replication, const struct omap_video_timings *mgr_timings,
81743 bool mem_to_mem);
81744 --- a/include/video/omap-panel-data.h
81745 +++ b/include/video/omap-panel-data.h
81746 @@ -62,6 +62,20 @@ struct encoder_tpd12s015_platform_data {
81747 };
81748
81749 /**
81750 + * encoder_sil9022 platform data
81751 + * @name: name for this display entity
81752 + * @res_gpio: Gpio to switch lcd and hdmi. Used as reset for Sil9022
81753 + * as a temproary solution.
81754 + */
81755 +struct encoder_sil9022_platform_data {
81756 + const char *name;
81757 + const char *source;
81758 + int reset_gpio;
81759 + int data_lines;
81760 +};
81761 +
81762 +
81763 +/**
81764 * connector_dvi platform data
81765 * @name: name for this display entity
81766 * @source: name of the display entity used as a video source
81767 --- a/MAINTAINERS
81768 +++ b/MAINTAINERS
81769 @@ -3691,6 +3691,14 @@ S: Maintained
81770 F: include/asm-generic/
81771 F: include/uapi/asm-generic/
81772
81773 +GENERIC PHY FRAMEWORK
81774 +M: Kishon Vijay Abraham I <kishon@ti.com>
81775 +L: linux-kernel@vger.kernel.org
81776 +T: git git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy.git
81777 +S: Supported
81778 +F: drivers/phy/
81779 +F: include/linux/phy/
81780 +
81781 GENERIC UIO DRIVER FOR PCI DEVICES
81782 M: "Michael S. Tsirkin" <mst@redhat.com>
81783 L: kvm@vger.kernel.org
81784 --- a/sound/soc/davinci/davinci-evm.c
81785 +++ b/sound/soc/davinci/davinci-evm.c
81786 @@ -16,6 +16,7 @@
81787 #include <linux/platform_device.h>
81788 #include <linux/platform_data/edma.h>
81789 #include <linux/i2c.h>
81790 +#include <linux/of_platform.h>
81791 #include <sound/core.h>
81792 #include <sound/pcm.h>
81793 #include <sound/soc.h>
81794 @@ -23,10 +24,16 @@
81795 #include <asm/dma.h>
81796 #include <asm/mach-types.h>
81797
81798 +#include <linux/edma.h>
81799 +
81800 #include "davinci-pcm.h"
81801 #include "davinci-i2s.h"
81802 #include "davinci-mcasp.h"
81803
81804 +struct snd_soc_card_drvdata_davinci {
81805 + unsigned sysclk;
81806 +};
81807 +
81808 #define AUDIO_FORMAT (SND_SOC_DAIFMT_DSP_B | \
81809 SND_SOC_DAIFMT_CBM_CFM | SND_SOC_DAIFMT_IB_NF)
81810 static int evm_hw_params(struct snd_pcm_substream *substream,
81811 @@ -35,27 +42,11 @@ static int evm_hw_params(struct snd_pcm_
81812 struct snd_soc_pcm_runtime *rtd = substream->private_data;
81813 struct snd_soc_dai *codec_dai = rtd->codec_dai;
81814 struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
81815 + struct snd_soc_codec *codec = rtd->codec;
81816 + struct snd_soc_card *soc_card = codec->card;
81817 int ret = 0;
81818 - unsigned sysclk;
81819 -
81820 - /* ASP1 on DM355 EVM is clocked by an external oscillator */
81821 - if (machine_is_davinci_dm355_evm() || machine_is_davinci_dm6467_evm() ||
81822 - machine_is_davinci_dm365_evm())
81823 - sysclk = 27000000;
81824 -
81825 - /* ASP0 in DM6446 EVM is clocked by U55, as configured by
81826 - * board-dm644x-evm.c using GPIOs from U18. There are six
81827 - * options; here we "know" we use a 48 KHz sample rate.
81828 - */
81829 - else if (machine_is_davinci_evm())
81830 - sysclk = 12288000;
81831 -
81832 - else if (machine_is_davinci_da830_evm() ||
81833 - machine_is_davinci_da850_evm())
81834 - sysclk = 24576000;
81835 -
81836 - else
81837 - return -EINVAL;
81838 + unsigned sysclk = ((struct snd_soc_card_drvdata_davinci *)
81839 + snd_soc_card_get_drvdata(soc_card))->sysclk;
81840
81841 /* set codec DAI configuration */
81842 ret = snd_soc_dai_set_fmt(codec_dai, AUDIO_FORMAT);
81843 @@ -133,13 +124,22 @@ static int evm_aic3x_init(struct snd_soc
81844 {
81845 struct snd_soc_codec *codec = rtd->codec;
81846 struct snd_soc_dapm_context *dapm = &codec->dapm;
81847 + struct device_node *np = codec->card->dev->of_node;
81848 + int ret;
81849
81850 /* Add davinci-evm specific widgets */
81851 snd_soc_dapm_new_controls(dapm, aic3x_dapm_widgets,
81852 ARRAY_SIZE(aic3x_dapm_widgets));
81853
81854 - /* Set up davinci-evm specific audio path audio_map */
81855 - snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map));
81856 + if (np) {
81857 + ret = snd_soc_of_parse_audio_routing(codec->card,
81858 + "ti,audio-routing");
81859 + if (ret)
81860 + return ret;
81861 + } else {
81862 + /* Set up davinci-evm specific audio path audio_map */
81863 + snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map));
81864 + }
81865
81866 /* not connected */
81867 snd_soc_dapm_disable_pin(dapm, "MONO_LOUT");
81868 @@ -243,35 +243,65 @@ static struct snd_soc_dai_link da850_evm
81869 };
81870
81871 /* davinci dm6446 evm audio machine driver */
81872 +/*
81873 + * ASP0 in DM6446 EVM is clocked by U55, as configured by
81874 + * board-dm644x-evm.c using GPIOs from U18. There are six
81875 + * options; here we "know" we use a 48 KHz sample rate.
81876 + */
81877 +static struct snd_soc_card_drvdata_davinci dm6446_snd_soc_card_drvdata = {
81878 + .sysclk = 12288000,
81879 +};
81880 +
81881 static struct snd_soc_card dm6446_snd_soc_card_evm = {
81882 .name = "DaVinci DM6446 EVM",
81883 .owner = THIS_MODULE,
81884 .dai_link = &dm6446_evm_dai,
81885 .num_links = 1,
81886 + .drvdata = &dm6446_snd_soc_card_drvdata,
81887 };
81888
81889 /* davinci dm355 evm audio machine driver */
81890 +/* ASP1 on DM355 EVM is clocked by an external oscillator */
81891 +static struct snd_soc_card_drvdata_davinci dm355_snd_soc_card_drvdata = {
81892 + .sysclk = 27000000,
81893 +};
81894 +
81895 static struct snd_soc_card dm355_snd_soc_card_evm = {
81896 .name = "DaVinci DM355 EVM",
81897 .owner = THIS_MODULE,
81898 .dai_link = &dm355_evm_dai,
81899 .num_links = 1,
81900 + .drvdata = &dm355_snd_soc_card_drvdata,
81901 };
81902
81903 /* davinci dm365 evm audio machine driver */
81904 +static struct snd_soc_card_drvdata_davinci dm365_snd_soc_card_drvdata = {
81905 + .sysclk = 27000000,
81906 +};
81907 +
81908 static struct snd_soc_card dm365_snd_soc_card_evm = {
81909 .name = "DaVinci DM365 EVM",
81910 .owner = THIS_MODULE,
81911 .dai_link = &dm365_evm_dai,
81912 .num_links = 1,
81913 + .drvdata = &dm365_snd_soc_card_drvdata,
81914 };
81915
81916 /* davinci dm6467 evm audio machine driver */
81917 +static struct snd_soc_card_drvdata_davinci dm6467_snd_soc_card_drvdata = {
81918 + .sysclk = 27000000,
81919 +};
81920 +
81921 static struct snd_soc_card dm6467_snd_soc_card_evm = {
81922 .name = "DaVinci DM6467 EVM",
81923 .owner = THIS_MODULE,
81924 .dai_link = dm6467_evm_dai,
81925 .num_links = ARRAY_SIZE(dm6467_evm_dai),
81926 + .drvdata = &dm6467_snd_soc_card_drvdata,
81927 +};
81928 +
81929 +static struct snd_soc_card_drvdata_davinci da830_snd_soc_card_drvdata = {
81930 + .sysclk = 24576000,
81931 };
81932
81933 static struct snd_soc_card da830_snd_soc_card = {
81934 @@ -279,6 +309,11 @@ static struct snd_soc_card da830_snd_soc
81935 .owner = THIS_MODULE,
81936 .dai_link = &da830_evm_dai,
81937 .num_links = 1,
81938 + .drvdata = &da830_snd_soc_card_drvdata,
81939 +};
81940 +
81941 +static struct snd_soc_card_drvdata_davinci da850_snd_soc_card_drvdata = {
81942 + .sysclk = 24576000,
81943 };
81944
81945 static struct snd_soc_card da850_snd_soc_card = {
81946 @@ -286,8 +321,101 @@ static struct snd_soc_card da850_snd_soc
81947 .owner = THIS_MODULE,
81948 .dai_link = &da850_evm_dai,
81949 .num_links = 1,
81950 + .drvdata = &da850_snd_soc_card_drvdata,
81951 +};
81952 +
81953 +#if defined(CONFIG_OF)
81954 +
81955 +/*
81956 + * The struct is used as place holder. It will be completely
81957 + * filled with data from dt node.
81958 + */
81959 +static struct snd_soc_dai_link evm_dai_tlv320aic3x = {
81960 + .name = "TLV320AIC3X",
81961 + .stream_name = "AIC3X",
81962 + .codec_dai_name = "tlv320aic3x-hifi",
81963 + .ops = &evm_ops,
81964 + .init = evm_aic3x_init,
81965 +};
81966 +
81967 +static const struct of_device_id davinci_evm_dt_ids[] = {
81968 + {
81969 + .compatible = "ti,da830-evm-audio",
81970 + .data = (void *) &evm_dai_tlv320aic3x,
81971 + },
81972 + { /* sentinel */ }
81973 +};
81974 +MODULE_DEVICE_TABLE(of, davinci_evm_dt_ids);
81975 +
81976 +/* davinci evm audio machine driver */
81977 +static struct snd_soc_card evm_soc_card = {
81978 + .owner = THIS_MODULE,
81979 + .num_links = 1,
81980 };
81981
81982 +static int davinci_evm_probe(struct platform_device *pdev)
81983 +{
81984 + struct device_node *np = pdev->dev.of_node;
81985 + const struct of_device_id *match =
81986 + of_match_device(of_match_ptr(davinci_evm_dt_ids), &pdev->dev);
81987 + struct snd_soc_dai_link *dai = (struct snd_soc_dai_link *) match->data;
81988 + struct snd_soc_card_drvdata_davinci *drvdata = NULL;
81989 + int ret = 0;
81990 +
81991 + evm_soc_card.dai_link = dai;
81992 +
81993 + dai->codec_of_node = of_parse_phandle(np, "ti,audio-codec", 0);
81994 + if (!dai->codec_of_node)
81995 + return -EINVAL;
81996 +
81997 + dai->cpu_of_node = of_parse_phandle(np, "ti,mcasp-controller", 0);
81998 + if (!dai->cpu_of_node)
81999 + return -EINVAL;
82000 +
82001 + dai->platform_of_node = dai->cpu_of_node;
82002 +
82003 + evm_soc_card.dev = &pdev->dev;
82004 + ret = snd_soc_of_parse_card_name(&evm_soc_card, "ti,model");
82005 + if (ret)
82006 + return ret;
82007 +
82008 + drvdata = devm_kzalloc(&pdev->dev, sizeof(*drvdata), GFP_KERNEL);
82009 + if (!drvdata)
82010 + return -ENOMEM;
82011 +
82012 + ret = of_property_read_u32(np, "ti,codec-clock-rate", &drvdata->sysclk);
82013 + if (ret < 0)
82014 + return -EINVAL;
82015 +
82016 + snd_soc_card_set_drvdata(&evm_soc_card, drvdata);
82017 + ret = snd_soc_register_card(&evm_soc_card);
82018 +
82019 + if (ret)
82020 + dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n", ret);
82021 +
82022 + return ret;
82023 +}
82024 +
82025 +static int davinci_evm_remove(struct platform_device *pdev)
82026 +{
82027 + struct snd_soc_card *card = platform_get_drvdata(pdev);
82028 +
82029 + snd_soc_unregister_card(card);
82030 +
82031 + return 0;
82032 +}
82033 +
82034 +static struct platform_driver davinci_evm_driver = {
82035 + .probe = davinci_evm_probe,
82036 + .remove = davinci_evm_remove,
82037 + .driver = {
82038 + .name = "davinci_evm",
82039 + .owner = THIS_MODULE,
82040 + .of_match_table = of_match_ptr(davinci_evm_dt_ids),
82041 + },
82042 +};
82043 +#endif
82044 +
82045 static struct platform_device *evm_snd_device;
82046
82047 static int __init evm_init(void)
82048 @@ -296,6 +424,13 @@ static int __init evm_init(void)
82049 int index;
82050 int ret;
82051
82052 + /*
82053 + * If dtb is there, the devices will be created dynamically.
82054 + * Only register platfrom driver structure.
82055 + */
82056 + if (of_have_populated_dt())
82057 + return platform_driver_register(&davinci_evm_driver);
82058 +
82059 if (machine_is_davinci_evm()) {
82060 evm_snd_dev_data = &dm6446_snd_soc_card_evm;
82061 index = 0;
82062 @@ -331,6 +466,11 @@ static int __init evm_init(void)
82063
82064 static void __exit evm_exit(void)
82065 {
82066 + if (of_have_populated_dt()) {
82067 + platform_driver_unregister(&davinci_evm_driver);
82068 + return;
82069 + }
82070 +
82071 platform_device_unregister(evm_snd_device);
82072 }
82073
82074 --- a/sound/soc/davinci/davinci-mcasp.c
82075 +++ b/sound/soc/davinci/davinci-mcasp.c
82076 @@ -1001,18 +1001,40 @@ static const struct snd_soc_component_dr
82077 .name = "davinci-mcasp",
82078 };
82079
82080 +/* Some HW specific values and defaults. The rest is filled in from DT. */
82081 +static struct snd_platform_data dm646x_mcasp_pdata = {
82082 + .tx_dma_offset = 0x400,
82083 + .rx_dma_offset = 0x400,
82084 + .asp_chan_q = EVENTQ_0,
82085 + .version = MCASP_VERSION_1,
82086 +};
82087 +
82088 +static struct snd_platform_data da830_mcasp_pdata = {
82089 + .tx_dma_offset = 0x2000,
82090 + .rx_dma_offset = 0x2000,
82091 + .asp_chan_q = EVENTQ_0,
82092 + .version = MCASP_VERSION_2,
82093 +};
82094 +
82095 +static struct snd_platform_data omap2_mcasp_pdata = {
82096 + .tx_dma_offset = 0,
82097 + .rx_dma_offset = 0,
82098 + .asp_chan_q = EVENTQ_0,
82099 + .version = MCASP_VERSION_3,
82100 +};
82101 +
82102 static const struct of_device_id mcasp_dt_ids[] = {
82103 {
82104 .compatible = "ti,dm646x-mcasp-audio",
82105 - .data = (void *)MCASP_VERSION_1,
82106 + .data = &dm646x_mcasp_pdata,
82107 },
82108 {
82109 .compatible = "ti,da830-mcasp-audio",
82110 - .data = (void *)MCASP_VERSION_2,
82111 + .data = &da830_mcasp_pdata,
82112 },
82113 {
82114 .compatible = "ti,omap2-mcasp-audio",
82115 - .data = (void *)MCASP_VERSION_3,
82116 + .data = &omap2_mcasp_pdata,
82117 },
82118 { /* sentinel */ }
82119 };
82120 @@ -1025,9 +1047,9 @@ static struct snd_platform_data *davinci
82121 struct snd_platform_data *pdata = NULL;
82122 const struct of_device_id *match =
82123 of_match_device(mcasp_dt_ids, &pdev->dev);
82124 + struct of_phandle_args dma_spec;
82125
82126 const u32 *of_serial_dir32;
82127 - u8 *of_serial_dir;
82128 u32 val;
82129 int i, ret = 0;
82130
82131 @@ -1035,20 +1057,13 @@ static struct snd_platform_data *davinci
82132 pdata = pdev->dev.platform_data;
82133 return pdata;
82134 } else if (match) {
82135 - pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
82136 - if (!pdata) {
82137 - ret = -ENOMEM;
82138 - goto nodata;
82139 - }
82140 + pdata = (struct snd_platform_data *) match->data;
82141 } else {
82142 /* control shouldn't reach here. something is wrong */
82143 ret = -EINVAL;
82144 goto nodata;
82145 }
82146
82147 - if (match->data)
82148 - pdata->version = (u8)((int)match->data);
82149 -
82150 ret = of_property_read_u32(np, "op-mode", &val);
82151 if (ret >= 0)
82152 pdata->op_mode = val;
82153 @@ -1065,35 +1080,46 @@ static struct snd_platform_data *davinci
82154 pdata->tdm_slots = val;
82155 }
82156
82157 - ret = of_property_read_u32(np, "num-serializer", &val);
82158 - if (ret >= 0)
82159 - pdata->num_serializer = val;
82160 -
82161 of_serial_dir32 = of_get_property(np, "serial-dir", &val);
82162 val /= sizeof(u32);
82163 - if (val != pdata->num_serializer) {
82164 - dev_err(&pdev->dev,
82165 - "num-serializer(%d) != serial-dir size(%d)\n",
82166 - pdata->num_serializer, val);
82167 - ret = -EINVAL;
82168 - goto nodata;
82169 - }
82170 -
82171 if (of_serial_dir32) {
82172 - of_serial_dir = devm_kzalloc(&pdev->dev,
82173 - (sizeof(*of_serial_dir) * val),
82174 - GFP_KERNEL);
82175 + u8 *of_serial_dir = devm_kzalloc(&pdev->dev,
82176 + (sizeof(*of_serial_dir) * val),
82177 + GFP_KERNEL);
82178 if (!of_serial_dir) {
82179 ret = -ENOMEM;
82180 goto nodata;
82181 }
82182
82183 - for (i = 0; i < pdata->num_serializer; i++)
82184 + for (i = 0; i < val; i++)
82185 of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]);
82186
82187 + pdata->num_serializer = val;
82188 pdata->serial_dir = of_serial_dir;
82189 }
82190
82191 + ret = of_property_match_string(np, "dma-names", "tx");
82192 + if (ret < 0)
82193 + goto nodata;
82194 +
82195 + ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
82196 + &dma_spec);
82197 + if (ret < 0)
82198 + goto nodata;
82199 +
82200 + pdata->tx_dma_channel = dma_spec.args[0];
82201 +
82202 + ret = of_property_match_string(np, "dma-names", "rx");
82203 + if (ret < 0)
82204 + goto nodata;
82205 +
82206 + ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
82207 + &dma_spec);
82208 + if (ret < 0)
82209 + goto nodata;
82210 +
82211 + pdata->rx_dma_channel = dma_spec.args[0];
82212 +
82213 ret = of_property_read_u32(np, "tx-num-evt", &val);
82214 if (ret >= 0)
82215 pdata->txnumevt = val;
82216 @@ -1124,7 +1150,7 @@ nodata:
82217 static int davinci_mcasp_probe(struct platform_device *pdev)
82218 {
82219 struct davinci_pcm_dma_params *dma_data;
82220 - struct resource *mem, *ioarea, *res;
82221 + struct resource *mem, *ioarea, *res, *dma;
82222 struct snd_platform_data *pdata;
82223 struct davinci_audio_dev *dev;
82224 int ret;
82225 @@ -1145,10 +1171,15 @@ static int davinci_mcasp_probe(struct pl
82226 return -EINVAL;
82227 }
82228
82229 - mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
82230 + mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
82231 if (!mem) {
82232 - dev_err(&pdev->dev, "no mem resource?\n");
82233 - return -ENODEV;
82234 + dev_warn(dev->dev,
82235 + "\"mpu\" mem resource not found, using index 0\n");
82236 + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
82237 + if (!mem) {
82238 + dev_err(&pdev->dev, "no mem resource?\n");
82239 + return -ENODEV;
82240 + }
82241 }
82242
82243 ioarea = devm_request_mem_region(&pdev->dev, mem->start,
82244 @@ -1182,40 +1213,36 @@ static int davinci_mcasp_probe(struct pl
82245 dev->rxnumevt = pdata->rxnumevt;
82246 dev->dev = &pdev->dev;
82247
82248 + dma = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
82249 + if (!dma)
82250 + dma = mem;
82251 +
82252 dma_data = &dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK];
82253 dma_data->asp_chan_q = pdata->asp_chan_q;
82254 dma_data->ram_chan_q = pdata->ram_chan_q;
82255 dma_data->sram_pool = pdata->sram_pool;
82256 dma_data->sram_size = pdata->sram_size_playback;
82257 - dma_data->dma_addr = (dma_addr_t) (pdata->tx_dma_offset +
82258 - mem->start);
82259 + dma_data->dma_addr = dma->start + pdata->tx_dma_offset;
82260
82261 - /* first TX, then RX */
82262 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
82263 - if (!res) {
82264 - dev_err(&pdev->dev, "no DMA resource\n");
82265 - ret = -ENODEV;
82266 - goto err_release_clk;
82267 - }
82268 -
82269 - dma_data->channel = res->start;
82270 + if (res)
82271 + dma_data->channel = res->start;
82272 + else
82273 + dma_data->channel = pdata->tx_dma_channel;
82274
82275 dma_data = &dev->dma_params[SNDRV_PCM_STREAM_CAPTURE];
82276 dma_data->asp_chan_q = pdata->asp_chan_q;
82277 dma_data->ram_chan_q = pdata->ram_chan_q;
82278 dma_data->sram_pool = pdata->sram_pool;
82279 dma_data->sram_size = pdata->sram_size_capture;
82280 - dma_data->dma_addr = (dma_addr_t)(pdata->rx_dma_offset +
82281 - mem->start);
82282 + dma_data->dma_addr = dma->start + pdata->rx_dma_offset;
82283
82284 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
82285 - if (!res) {
82286 - dev_err(&pdev->dev, "no DMA resource\n");
82287 - ret = -ENODEV;
82288 - goto err_release_clk;
82289 - }
82290 + if (res)
82291 + dma_data->channel = res->start;
82292 + else
82293 + dma_data->channel = pdata->rx_dma_channel;
82294
82295 - dma_data->channel = res->start;
82296 dev_set_drvdata(&pdev->dev, dev);
82297 ret = snd_soc_register_component(&pdev->dev, &davinci_mcasp_component,
82298 &davinci_mcasp_dai[pdata->op_mode], 1);
82299 @@ -1266,4 +1293,3 @@ module_platform_driver(davinci_mcasp_dri
82300 MODULE_AUTHOR("Steve Chen");
82301 MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface");
82302 MODULE_LICENSE("GPL");
82303 -
82304 --- a/sound/soc/davinci/Kconfig
82305 +++ b/sound/soc/davinci/Kconfig
82306 @@ -1,9 +1,10 @@
82307 config SND_DAVINCI_SOC
82308 - tristate "SoC Audio for the TI DAVINCI chip"
82309 - depends on ARCH_DAVINCI
82310 + tristate "SoC Audio for the TI DAVINCI or AM33XX chip"
82311 + depends on ARCH_DAVINCI || SOC_AM33XX
82312 help
82313 + Platform driver for daVinci or AM33xx
82314 Say Y or M if you want to add support for codecs attached to
82315 - the DAVINCI AC97 or I2S interface. You will also need
82316 + the DAVINCI AC97, I2S, or McASP interface. You will also need
82317 to select the audio interfaces to support below.
82318
82319 config SND_DAVINCI_SOC_I2S
82320 @@ -15,6 +16,17 @@ config SND_DAVINCI_SOC_MCASP
82321 config SND_DAVINCI_SOC_VCIF
82322 tristate
82323
82324 +config SND_AM33XX_SOC_EVM
82325 + tristate "SoC Audio for the AM33XX chip based boards"
82326 + depends on SND_DAVINCI_SOC && SOC_AM33XX
82327 + select SND_SOC_TLV320AIC3X
82328 + select SND_DAVINCI_SOC_MCASP
82329 + help
82330 + Say Y or M if you want to add support for SoC audio on AM33XX
82331 + boards using McASP and TLV320AIC3X codec. For example AM335X-EVM,
82332 + AM335X-EVMSK, and BeagelBone with AudioCape boards have this
82333 + setup.
82334 +
82335 config SND_DAVINCI_SOC_EVM
82336 tristate "SoC Audio support for DaVinci DM6446, DM355 or DM365 EVM"
82337 depends on SND_DAVINCI_SOC
82338 --- a/sound/soc/davinci/Makefile
82339 +++ b/sound/soc/davinci/Makefile
82340 @@ -13,6 +13,7 @@ obj-$(CONFIG_SND_DAVINCI_SOC_VCIF) += sn
82341 snd-soc-evm-objs := davinci-evm.o
82342
82343 obj-$(CONFIG_SND_DAVINCI_SOC_EVM) += snd-soc-evm.o
82344 +obj-$(CONFIG_SND_AM33XX_SOC_EVM) += snd-soc-evm.o
82345 obj-$(CONFIG_SND_DM6467_SOC_EVM) += snd-soc-evm.o
82346 obj-$(CONFIG_SND_DA830_SOC_EVM) += snd-soc-evm.o
82347 obj-$(CONFIG_SND_DA850_SOC_EVM) += snd-soc-evm.o
82348 --- a/sound/soc/omap/Kconfig
82349 +++ b/sound/soc/omap/Kconfig
82350 @@ -87,17 +87,19 @@ config SND_OMAP_SOC_OMAP_TWL4030
82351
82352 config SND_OMAP_SOC_OMAP_ABE_TWL6040
82353 tristate "SoC Audio support for OMAP boards using ABE and twl6040 codec"
82354 - depends on TWL6040_CORE && SND_OMAP_SOC && (ARCH_OMAP4 || COMPILE_TEST)
82355 + depends on TWL6040_CORE && SND_OMAP_SOC && (ARCH_OMAP4 || SOC_OMAP5 || COMPILE_TEST)
82356 select SND_OMAP_SOC_DMIC
82357 select SND_OMAP_SOC_MCPDM
82358 select SND_SOC_TWL6040
82359 select SND_SOC_DMIC
82360 + select COMMON_CLK_PALMAS if SOC_OMAP5
82361 help
82362 Say Y if you want to add support for SoC audio on OMAP boards using
82363 ABE and twl6040 codec. This driver currently supports:
82364 - SDP4430/Blaze boards
82365 - PandaBoard (4430)
82366 - PandaBoardES (4460)
82367 + - omap5-uevm (5432)
82368
82369 config SND_OMAP_SOC_OMAP_HDMI
82370 tristate "SoC Audio support for Texas Instruments OMAP HDMI"
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