1 On OMAP we have co-processor IPs, memory controllers,
2 GPIOs which control regulators and power switches to
3 PMIC, and SoC internal Bus IPs, some or most of which
4 should either not be reset or idled or both at init.
5 (In some cases there are erratas which prevent an IP
7 Have a way to pass this information from DT.
9 Update the am33xx/omap4 and omap5 dtsi files with the
10 new bindings for modules which either should not be
11 idled. reset or both. A later patch would cleanup the
12 same information that exists today as part of the hwmod
15 Signed-off-by: Rajendra Nayak <rnayak@ti.com>
18 .../devicetree/bindings/arm/omap/omap.txt | 3 ++-
19 arch/arm/boot/dts/am33xx.dtsi | 2 ++
20 arch/arm/boot/dts/omap4.dtsi | 3 +++
21 arch/arm/boot/dts/omap5.dtsi | 2 ++
22 4 files changed, 9 insertions(+), 1 deletion(-)
24 diff --git a/Documentation/devicetree/bindings/arm/omap/omap.txt b/Documentation/devicetree/bindings/arm/omap/omap.txt
25 index 91b7049..808c154 100644
26 --- a/Documentation/devicetree/bindings/arm/omap/omap.txt
27 +++ b/Documentation/devicetree/bindings/arm/omap/omap.txt
28 @@ -21,7 +21,8 @@ Required properties:
30 - ti,no_idle_on_suspend: When present, it prevents the PM to idle the module
33 +- ti,no-reset-on-init: When present, the module should not be reset at init
34 +- ti,no-idle-on-init: When present, the module should not be idled at init
38 diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
39 index f9c5da9..ec33ea0 100644
40 --- a/arch/arm/boot/dts/am33xx.dtsi
41 +++ b/arch/arm/boot/dts/am33xx.dtsi
43 reg = <0x44d00000 0x4000 /* M3 UMEM */
44 0x44d80000 0x2000>; /* M3 DMEM */
45 ti,hwmods = "wkup_m3";
46 + ti,no-reset-on-init;
52 compatible = "ti,am3352-gpmc";
55 reg = <0x50000000 0x2000>;
58 diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
59 index 22d9f2b..e8fe797 100644
60 --- a/arch/arm/boot/dts/omap4.dtsi
61 +++ b/arch/arm/boot/dts/omap4.dtsi
64 gpmc,num-waitpins = <4>;
69 uart1: serial@4806a000 {
71 reg = <0x4c000000 0x100>;
72 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
76 hw-caps-read-idle-ctrl;
79 reg = <0x4d000000 0x100>;
80 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
84 hw-caps-read-idle-ctrl;
86 diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
87 index 7cdea1b..a9d49df 100644
88 --- a/arch/arm/boot/dts/omap5.dtsi
89 +++ b/arch/arm/boot/dts/omap5.dtsi
91 emif1: emif@0x4c000000 {
92 compatible = "ti,emif-4d5";
95 phy-type = <2>; /* DDR PHY type: Intelli PHY */
96 reg = <0x4c000000 0x400>;
97 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
99 emif2: emif@0x4d000000 {
100 compatible = "ti,emif-4d5";
102 + ti,no-idle-on-init;
103 phy-type = <2>; /* DDR PHY type: Intelli PHY */
104 reg = <0x4d000000 0x400>;
105 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;