3 * A driver to interface the 934 based sata core present in the ox820
5 * based on sata_oxnas driver by Ma Haijun <mahaijuns@gmail.com>
6 * based on ox820 sata code by:
7 * Copyright (c) 2007 Oxford Semiconductor Ltd.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2, or (at your option)
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
20 #include <linux/ata.h>
21 #include <linux/libata.h>
22 #include <linux/of_platform.h>
23 #include <linux/delay.h>
24 #include <linux/module.h>
25 #include <linux/slab.h>
26 #include <linux/spinlock.h>
27 #include <linux/of_address.h>
28 #include <linux/of_irq.h>
29 #include <linux/clk.h>
30 #include <linux/reset.h>
32 #include <mach/utils.h>
34 /* sgdma request structure */
35 struct sgdma_request
{
36 volatile u32 qualifier
;
40 } __packed
__aligned(4);
43 /* Controller information */
45 SATA_OXNAS_MAX_PRD
= 254,
46 SATA_OXNAS_DMA_SIZE
= SATA_OXNAS_MAX_PRD
*
47 sizeof(struct ata_bmdma_prd
) +
48 sizeof(struct sgdma_request
),
49 SATA_OXNAS_MAX_PORTS
= 2,
50 /** The different Oxsemi SATA core version numbers */
51 SATA_OXNAS_CORE_VERSION
= 0x1f3,
52 SATA_OXNAS_IRQ_FLAG
= IRQF_SHARED
,
53 SATA_OXNAS_HOST_FLAGS
= (ATA_FLAG_SATA
| ATA_FLAG_PIO_DMA
|
54 ATA_FLAG_NO_ATAPI
/*| ATA_FLAG_NCQ*/),
55 SATA_OXNAS_QUEUE_DEPTH
= 32,
57 SATA_OXNAS_DMA_BOUNDARY
= 0xFFFFFFFF,
65 /** sata host port register offsets */
84 /** These registers allow access to the link layer registers
85 that reside in a different clock domain to the processor bus */
98 /** sata port register bits */
101 * commands to issue in the master status to tell it to move shadow ,
102 * registers to the actual device ,
104 SATA_OPCODE_MASK
= 0x00000007,
105 CMD_WRITE_TO_ORB_REGS_NO_COMMAND
= 0x4,
106 CMD_WRITE_TO_ORB_REGS
= 0x2,
107 CMD_SYNC_ESCAPE
= 0x7,
108 CMD_CORE_BUSY
= (1 << 7),
109 CMD_DRIVE_SELECT_SHIFT
= 12,
110 CMD_DRIVE_SELECT_MASK
= (0xf << CMD_DRIVE_SELECT_SHIFT
),
112 /** interrupt bits */
113 INT_END_OF_CMD
= 1 << 0,
114 INT_LINK_SERROR
= 1 << 1,
116 INT_LINK_IRQ
= 1 << 3,
117 INT_REG_ACCESS_ERR
= 1 << 7,
118 INT_BIST_FIS
= 1 << 11,
119 INT_MASKABLE
= INT_END_OF_CMD
|
125 INT_WANT
= INT_END_OF_CMD
|
129 INT_ERRORS
= INT_LINK_SERROR
|
133 /** raw interrupt bits, unmaskable, but do not generate interrupts */
134 RAW_END_OF_CMD
= INT_END_OF_CMD
<< 16,
135 RAW_LINK_SERROR
= INT_LINK_SERROR
<< 16,
136 RAW_ERROR
= INT_ERROR
<< 16,
137 RAW_LINK_IRQ
= INT_LINK_IRQ
<< 16,
138 RAW_REG_ACCESS_ERR
= INT_REG_ACCESS_ERR
<< 16,
139 RAW_BIST_FIS
= INT_BIST_FIS
<< 16,
140 RAW_WANT
= INT_WANT
<< 16,
141 RAW_ERRORS
= INT_ERRORS
<< 16,
144 * variables to write to the device control register to set the current
145 * device, ie. master or slave.
150 SATA_CTL_ERR_MASK
= 0x00000016,
154 /* ATA SGDMA register offsets */
158 SGDMA_REQUESTPTR
= 0x8,
160 SGDMA_CORESIZE
= 0x10,
163 /* DMA controller register offsets */
168 DMA_CONTROL_RESET
= (1 << 12),
172 /* see DMA core docs for the values. Out means from memory (bus A) out
174 SGDMA_REQCTL0OUT
= 0x0497c03d,
175 /* burst mode disabled when no micro code used */
176 SGDMA_REQCTL0IN
= 0x0493a3c1,
177 SGDMA_REQCTL1OUT
= 0x0497c07d,
178 SGDMA_REQCTL1IN
= 0x0497a3c5,
179 SGDMA_CONTROL_NOGO
= 0x3e,
180 SGDMA_CONTROL_GO
= SGDMA_CONTROL_NOGO
| 1,
181 SGDMA_ERRORMASK
= 0x3f,
184 SGDMA_RESETS_CTRL
= 1 << 0,
185 SGDMA_RESETS_ARBT
= 1 << 1,
186 SGDMA_RESETS_AHB
= 1 << 2,
187 SGDMA_RESETS_ALL
= SGDMA_RESETS_CTRL
|
192 SGDMA_REQQUAL
= 0x00220001,
196 /** SATA core register offsets */
201 DATACOUNT_PORT0
= 0x010,
202 DATACOUNT_PORT1
= 0x014,
203 CORE_INT_STATUS
= 0x030,
204 CORE_INT_CLEAR
= 0x030,
205 CORE_INT_ENABLE
= 0x034,
206 CORE_INT_DISABLE
= 0x038,
207 CORE_REBUILD_ENABLE
= 0x050,
208 CORE_FAILED_PORT_R
= 0x054,
209 DEVICE_CONTROL
= 0x068,
211 RAID_SIZE_LOW
= 0x070,
212 RAID_SIZE_HIGH
= 0x074,
213 PORT_ERROR_MASK
= 0x078,
215 RAID_CONTROL
= 0x090,
216 DATA_PLANE_CTRL
= 0x0AC,
217 CORE_DATAPLANE_STAT
= 0x0b8,
222 UCODE_STORE
= 0x1000,
223 RAID_WP_BOT_LOW
= 0x1FF0,
224 RAID_WP_BOT_HIGH
= 0x1FF4,
225 RAID_WP_TOP_LOW
= 0x1FF8,
226 RAID_WP_TOP_HIGH
= 0x1FFC,
227 DATA_MUX_RAM0
= 0x8000,
228 DATA_MUX_RAM1
= 0xA000,
233 /* Sata core debug1 register bits */
234 CORE_PORT0_DATA_DIR_BIT
= 20,
235 CORE_PORT1_DATA_DIR_BIT
= 21,
236 CORE_PORT0_DATA_DIR
= 1 << CORE_PORT0_DATA_DIR_BIT
,
237 CORE_PORT1_DATA_DIR
= 1 << CORE_PORT1_DATA_DIR_BIT
,
239 /** sata core control register bits */
240 SCTL_CLR_ERR
= 0x00003016,
241 RAID_CLR_ERR
= 0x0000011e,
243 /* Interrupts direct from the ports */
244 NORMAL_INTS_WANTED
= 0x00000303,
246 /* shift these left by port number */
247 COREINT_HOST
= 0x00000001,
248 COREINT_END
= 0x00000100,
249 CORERAW_HOST
= COREINT_HOST
<< 16,
250 CORERAW_END
= COREINT_END
<< 16,
252 /* Interrupts from the RAID controller only */
253 RAID_INTS_WANTED
= 0x00008300,
255 /* The bits in the IDLE_STATUS that, when set indicate an idle core */
256 IDLE_CORES
= (1 << 18) | (1 << 19),
258 /* Data plane control error-mask mask and bit, these bit in the data
259 * plane control mask out errors from the ports that prevent the SGDMA
260 * care from sending an interrupt */
261 DPC_ERROR_MASK
= 0x00000300,
262 DPC_ERROR_MASK_BIT
= 0x00000100,
263 /* enable jbod micro-code */
264 DPC_JBOD_UCODE
= 1 << 0,
265 DPC_FIS_SWCH
= 1 << 1,
267 /** Device Control register bits */
268 DEVICE_CONTROL_DMABT
= 1 << 4,
269 DEVICE_CONTROL_ABORT
= 1 << 2,
270 DEVICE_CONTROL_PAD
= 1 << 3,
271 DEVICE_CONTROL_PADPAT
= 1 << 16,
272 DEVICE_CONTROL_PRTRST
= 1 << 8,
273 DEVICE_CONTROL_RAMRST
= 1 << 12,
274 DEVICE_CONTROL_ATA_ERR_OVERRIDE
= 1 << 28,
276 /** oxsemi HW raid modes */
277 OXNASSATA_NOTRAID
= 0,
280 /** OX820 specific HW-RAID register values */
284 CONFIG_IN_RESUME
= 2,
287 /* SATA PHY Registers */
294 STAT_READ_VALID
= (1 << 21),
295 STAT_CR_ACK
= (1 << 20),
296 STAT_CR_READ
= (1 << 19),
297 STAT_CR_WRITE
= (1 << 18),
298 STAT_CAP_DATA
= (1 << 17),
299 STAT_CAP_ADDR
= (1 << 16),
301 STAT_ACK_ANY
= STAT_CR_ACK
|
307 CR_READ_ENABLE
= (1 << 16),
308 CR_WRITE_ENABLE
= (1 << 17),
309 CR_CAP_DATA
= (1 << 18),
313 /* Link layer registers */
318 OXNAS_SATA_SOFTRESET
= 1,
319 OXNAS_SATA_REINIT
= 2,
323 OXNAS_SATA_UCODE_RAID0
,
324 OXNAS_SATA_UCODE_RAID1
,
325 OXNAS_SATA_UCODE_JBOD
,
326 OXNAS_SATA_UCODE_NONE
,
338 typedef irqreturn_t (*oxnas_sata_isr_callback_t
)(int, unsigned long, int);
340 struct sata_oxnas_host_priv
{
341 void __iomem
*port_base
;
342 void __iomem
*dmactl_base
;
343 void __iomem
*sgdma_base
;
344 void __iomem
*core_base
;
345 void __iomem
*phy_base
;
347 void __iomem
*dma_base_va
;
355 struct reset_control
*rst_sata
;
356 struct reset_control
*rst_link
;
357 struct reset_control
*rst_phy
;
359 spinlock_t core_lock
;
361 int reentrant_port_no
;
363 int direct_lock_count
;
365 int current_locker_type
;
366 int scsi_nonblocking_attempts
;
367 oxnas_sata_isr_callback_t isr_callback
;
369 wait_queue_head_t fast_wait_queue
;
370 wait_queue_head_t scsi_wait_queue
;
374 struct sata_oxnas_port_priv
{
375 void __iomem
*port_base
;
376 void __iomem
*dmactl_base
;
377 void __iomem
*sgdma_base
;
378 void __iomem
*core_base
;
379 struct sgdma_request
*sgdma_request
;
380 dma_addr_t sgdma_request_pa
;
383 static u8
sata_oxnas_check_status(struct ata_port
*ap
);
384 static int sata_oxnas_cleanup(struct ata_host
*ah
);
385 static void sata_oxnas_tf_load(struct ata_port
*ap
,
386 const struct ata_taskfile
*tf
);
387 static void sata_oxnas_irq_on(struct ata_port
*ap
);
388 static void sata_oxnas_post_reset_init(struct ata_port
*ap
);
390 static int sata_oxnas_acquire_hw(struct ata_port
*ap
, int may_sleep
,
391 int timeout_jiffies
);
392 static void sata_oxnas_release_hw(struct ata_port
*ap
);
394 static const void *HW_LOCKER_UID
= (void *)0xdeadbeef;
396 /***************************************************************************
398 ***************************************************************************/
399 static void wait_cr_ack(void __iomem
*phy_base
)
401 while ((ioread32(phy_base
+ PHY_STAT
) >> 16) & 0x1f)
402 ; /* wait for an ack bit to be set */
405 static u16
read_cr(void __iomem
*phy_base
, u16 address
)
407 iowrite32((u32
)address
, phy_base
+ PHY_STAT
);
408 wait_cr_ack(phy_base
);
409 iowrite32(CR_READ_ENABLE
, phy_base
+ PHY_DATA
);
410 wait_cr_ack(phy_base
);
411 return (u16
)ioread32(phy_base
+ PHY_STAT
);
414 static void write_cr(void __iomem
*phy_base
, u16 data
, u16 address
)
416 iowrite32((u32
)address
, phy_base
+ PHY_STAT
);
417 wait_cr_ack(phy_base
);
418 iowrite32((data
| CR_CAP_DATA
), phy_base
+ PHY_DATA
);
419 wait_cr_ack(phy_base
);
420 iowrite32(CR_WRITE_ENABLE
, phy_base
+ PHY_DATA
);
421 wait_cr_ack(phy_base
);
426 #define PH_GAIN_OFFSET 6
427 #define FR_GAIN_OFFSET 8
428 #define PH_GAIN_MASK (0x3 << PH_GAIN_OFFSET)
429 #define FR_GAIN_MASK (0x3 << FR_GAIN_OFFSET)
430 #define USE_INT_SETTING (1<<5)
432 void workaround5458(struct ata_host
*ah
)
434 struct sata_oxnas_host_priv
*hd
= ah
->private_data
;
435 void __iomem
*phy_base
= hd
->phy_base
;
439 for (i
= 0; i
< 2; i
++) {
440 rx_control
= read_cr(phy_base
, 0x201d + (i
<< 8));
441 rx_control
&= ~(PH_GAIN_MASK
| FR_GAIN_MASK
);
442 rx_control
|= PH_GAIN
<< PH_GAIN_OFFSET
;
443 rx_control
|= (FR_GAIN
<< FR_GAIN_OFFSET
) | USE_INT_SETTING
;
444 write_cr(phy_base
, rx_control
, 0x201d+(i
<<8));
449 * allows access to the link layer registers
450 * @param link_reg the link layer register to access (oxsemi indexing ie
451 * 00 = static config, 04 = phy ctrl)
453 void sata_oxnas_link_write(struct ata_port
*ap
, unsigned int link_reg
, u32 val
)
455 struct sata_oxnas_port_priv
*pd
= ap
->private_data
;
456 struct sata_oxnas_host_priv
*hd
= ap
->host
->private_data
;
457 void __iomem
*port_base
= pd
->port_base
;
461 DPRINTK("P%d [0x%02x]->0x%08x\n", ap
->port_no
, link_reg
, val
);
463 spin_lock_irqsave(&hd
->phy_lock
, flags
);
464 iowrite32(val
, port_base
+ LINK_DATA
);
466 /* accessed twice as a work around for a bug in the SATA abp bridge
467 * hardware (bug 6828) */
468 iowrite32(link_reg
, port_base
+ LINK_WR_ADDR
);
469 ioread32(port_base
+ LINK_WR_ADDR
);
471 for (patience
= 0x100000; patience
> 0; --patience
) {
472 if (ioread32(port_base
+ LINK_CONTROL
) & 0x00000001)
475 spin_unlock_irqrestore(&hd
->phy_lock
, flags
);
478 static int sata_oxnas_scr_write_port(struct ata_port
*ap
, unsigned int sc_reg
,
481 sata_oxnas_link_write(ap
, 0x20 + (sc_reg
* 4), val
);
485 static int sata_oxnas_scr_write(struct ata_link
*link
, unsigned int sc_reg
,
488 return sata_oxnas_scr_write_port(link
->ap
, sc_reg
, val
);
491 u32
sata_oxnas_link_read(struct ata_port
*ap
, unsigned int link_reg
)
493 struct sata_oxnas_port_priv
*pd
= ap
->private_data
;
494 struct sata_oxnas_host_priv
*hd
= ap
->host
->private_data
;
495 void __iomem
*port_base
= pd
->port_base
;
500 spin_lock_irqsave(&hd
->phy_lock
, flags
);
501 /* accessed twice as a work around for a bug in the SATA abp bridge
502 * hardware (bug 6828) */
503 iowrite32(link_reg
, port_base
+ LINK_RD_ADDR
);
504 ioread32(port_base
+ LINK_RD_ADDR
);
506 for (patience
= 0x100000; patience
> 0; --patience
) {
507 if (ioread32(port_base
+ LINK_CONTROL
) & 0x00000001)
511 DPRINTK("link read timed out for port %d\n", ap
->port_no
);
513 result
= ioread32(port_base
+ LINK_DATA
);
514 spin_unlock_irqrestore(&hd
->phy_lock
, flags
);
519 static int sata_oxnas_scr_read_port(struct ata_port
*ap
, unsigned int sc_reg
,
522 *val
= sata_oxnas_link_read(ap
, 0x20 + (sc_reg
*4));
526 static int sata_oxnas_scr_read(struct ata_link
*link
,
527 unsigned int sc_reg
, u32
*val
)
529 return sata_oxnas_scr_read_port(link
->ap
, sc_reg
, val
);
533 * sata_oxnas_irq_clear is called during probe just before the interrupt handler is
534 * registered, to be sure hardware is quiet. It clears and masks interrupt bits
537 * @param ap hardware with the registers in
539 static void sata_oxnas_irq_clear(struct ata_port
*ap
)
541 struct sata_oxnas_port_priv
*port_priv
= ap
->private_data
;
543 /* clear pending interrupts */
544 iowrite32(~0, port_priv
->port_base
+ INT_CLEAR
);
545 iowrite32(COREINT_END
, port_priv
->core_base
+ CORE_INT_CLEAR
);
549 * qc_issue is used to make a command active, once the hardware and S/G tables
550 * have been prepared. IDE BMDMA drivers use the helper function
551 * ata_qc_issue_prot() for taskfile protocol-based dispatch. More advanced
552 * drivers roll their own ->qc_issue implementation, using this as the
553 * "issue new ATA command to hardware" hook.
554 * @param qc the queued command to issue
556 static unsigned int sata_oxnas_qc_issue(struct ata_queued_cmd
*qc
)
558 struct sata_oxnas_port_priv
*pd
= qc
->ap
->private_data
;
559 struct sata_oxnas_host_priv
*hd
= qc
->ap
->host
->private_data
;
561 void __iomem
*port_base
= pd
->port_base
;
562 void __iomem
*core_base
= pd
->core_base
;
563 int port_no
= qc
->ap
->port_no
;
564 int no_microcode
= (hd
->current_ucode
== UNKNOWN_MODE
);
567 /* check the core is idle */
568 if (ioread32(port_base
+ SATA_COMMAND
) & CMD_CORE_BUSY
) {
571 DPRINTK("core busy for a command on port %d\n",
576 DPRINTK("core busy for a command on port %d\n",
578 /* CrazyDumpDebug(); */
579 sata_oxnas_cleanup(qc
->ap
->host
);
581 } while (ioread32(port_base
+ SATA_COMMAND
) & CMD_CORE_BUSY
);
584 /* enable passing of error signals to DMA sub-core by clearing the
586 reg
= ioread32(core_base
+ DATA_PLANE_CTRL
);
588 reg
|= (DPC_ERROR_MASK_BIT
| (DPC_ERROR_MASK_BIT
<< 1));
589 reg
&= ~(DPC_ERROR_MASK_BIT
<< port_no
);
590 iowrite32(reg
, core_base
+ DATA_PLANE_CTRL
);
592 /* Disable all interrupts for ports and RAID controller */
593 iowrite32(~0, port_base
+ INT_DISABLE
);
595 /* Disable all interrupts for core */
596 iowrite32(~0, core_base
+ CORE_INT_DISABLE
);
599 /* Load the command settings into the orb registers */
600 sata_oxnas_tf_load(qc
->ap
, &qc
->tf
);
602 /* both pio and dma commands use dma */
603 if (ata_is_dma(qc
->tf
.protocol
) || ata_is_pio(qc
->tf
.protocol
)) {
605 iowrite32(SGDMA_CONTROL_GO
, pd
->sgdma_base
+ SGDMA_CONTROL
);
609 /* enable End of command interrupt */
610 iowrite32(INT_WANT
, port_base
+ INT_ENABLE
);
611 iowrite32(COREINT_END
, core_base
+ CORE_INT_ENABLE
);
614 /* Start the command */
615 reg
= ioread32(port_base
+ SATA_COMMAND
);
616 reg
&= ~SATA_OPCODE_MASK
;
617 reg
|= CMD_WRITE_TO_ORB_REGS
;
618 iowrite32(reg
, port_base
+ SATA_COMMAND
);
625 * Will schedule the libATA error handler on the premise that there has
626 * been a hotplug event on the port specified
628 void sata_oxnas_checkforhotplug(struct ata_port
*ap
)
632 ata_ehi_hotplugged(&ap
->link
.eh_info
);
637 /**************************************************************************/
639 /**************************************************************************/
641 * The underlying function that controls access to the sata core
643 * @return non-zero indicates that you have acquired exclusive access to the
646 static int __acquire_sata_core(
649 oxnas_sata_isr_callback_t callback
,
657 unsigned long end
= jiffies
+ timeout_jiffies
;
661 struct sata_oxnas_host_priv
*hd
;
668 hd
= ah
->private_data
;
670 spin_lock_irqsave(&hd
->core_lock
, flags
);
672 DPRINTK("Entered uid %p, port %d, h/w count %d, d count %d, "
673 "callback %p, hw_access %d, core_locked %d, "
674 "reentrant_port_no %d, isr_callback %p\n",
675 uid
, port_no
, hd
->hw_lock_count
, hd
->direct_lock_count
,
676 callback
, hw_access
, hd
->core_locked
, hd
->reentrant_port_no
,
680 if (hd
->core_locked
||
681 (!hw_access
&& hd
->scsi_nonblocking_attempts
)) {
682 /* Can only allow access if from SCSI/SATA stack and if
683 * reentrant access is allowed and this access is to the
684 * same port for which the lock is current held
686 if (hw_access
&& (port_no
== hd
->reentrant_port_no
)) {
687 BUG_ON(!hd
->hw_lock_count
);
688 ++(hd
->hw_lock_count
);
690 DPRINTK("Allow SCSI/SATA re-entrant access to "
691 "uid %p port %d\n", uid
, port_no
);
694 } else if (!hw_access
) {
695 if ((locker_type
== SATA_READER
) &&
696 (hd
->current_locker_type
== SATA_READER
)) {
698 "Already locked by reader, "
699 "uid %p, locker_uid %p, "
700 "port %d, h/w count %d, "
701 "d count %d, hw_access %d\n",
702 uid
, hd
->locker_uid
, port_no
,
704 hd
->direct_lock_count
,
709 if ((locker_type
!= SATA_READER
) &&
710 (locker_type
!= SATA_WRITER
)) {
715 WARN(uid
== hd
->locker_uid
, "Attempt to lock "
716 "by locker type %d uid %p, already "
717 "locked by locker type %d with "
718 "locker_uid %p, port %d, "
719 "h/w count %d, d count %d, "
720 "hw_access %d\n", locker_type
, uid
,
721 hd
->current_locker_type
,
722 hd
->locker_uid
, port_no
,
724 hd
->direct_lock_count
, hw_access
);
727 WARN(hd
->hw_lock_count
|| hd
->direct_lock_count
,
728 "Core unlocked but counts non-zero: uid %p, "
729 "locker_uid %p, port %d, h/w count %d, "
730 "d count %d, hw_access %d\n", uid
,
731 hd
->locker_uid
, port_no
, hd
->hw_lock_count
,
732 hd
->direct_lock_count
, hw_access
);
734 BUG_ON(hd
->current_locker_type
!= SATA_UNLOCKED
);
736 WARN(hd
->locker_uid
, "Attempt to lock uid %p when "
737 "locker_uid %p is non-zero, port %d, "
738 "h/w count %d, d count %d, hw_access %d\n",
739 uid
, hd
->locker_uid
, port_no
, hd
->hw_lock_count
,
740 hd
->direct_lock_count
, hw_access
);
743 /* Direct access attempting to acquire
746 /* Must have callback for direct access */
748 /* Sanity check lock state */
749 BUG_ON(hd
->reentrant_port_no
!= -1);
751 hd
->isr_callback
= callback
;
753 ++(hd
->direct_lock_count
);
755 hd
->current_locker_type
= locker_type
;
757 /* SCSI/SATA attempting to acquire
760 /* No callbacks for SCSI/SATA access */
762 /* No callback args for SCSI/SATA access */
765 /* Sanity check lock state */
766 BUG_ON(hd
->isr_callback
);
769 ++(hd
->hw_lock_count
);
770 hd
->reentrant_port_no
= port_no
;
772 hd
->current_locker_type
= SATA_SCSI_STACK
;
776 hd
->locker_uid
= uid
;
783 DPRINTK("Denying for uid %p locker_type %d, "
784 "hw_access %d, port %d, current_locker_type %d as "
785 "cannot sleep\n", uid
, locker_type
, hw_access
, port_no
,
786 hd
->current_locker_type
);
789 ++(hd
->scsi_nonblocking_attempts
);
794 /* Core is locked and we're allowed to sleep, so wait to be
795 * awoken when the core is unlocked
798 prepare_to_wait(hw_access
? &hd
->scsi_wait_queue
:
799 &hd
->fast_wait_queue
,
800 &wait
, TASK_UNINTERRUPTIBLE
);
801 if (!hd
->core_locked
&&
802 !(!hw_access
&& hd
->scsi_nonblocking_attempts
)) {
803 /* We're going to use variables that will have
804 * been changed by the waker prior to clearing
805 * core_locked so we need to ensure we see
806 * changes to all those variables
811 if (time_after(jiffies
, end
)) {
812 printk(KERN_WARNING
"__acquire_sata_core() "
813 "uid %p failing for port %d timed out, "
814 "locker_uid %p, h/w count %d, "
815 "d count %d, callback %p, hw_access %d, "
816 "core_locked %d, reentrant_port_no %d, "
817 "isr_callback %p, isr_arg %p\n", uid
,
818 port_no
, hd
->locker_uid
,
820 hd
->direct_lock_count
, callback
,
821 hw_access
, hd
->core_locked
,
822 hd
->reentrant_port_no
, hd
->isr_callback
,
827 spin_unlock_irqrestore(&hd
->core_lock
, flags
);
828 if (!schedule_timeout(4*HZ
)) {
829 printk(KERN_INFO
"__acquire_sata_core() uid %p, "
830 "locker_uid %p, timed-out of "
831 "schedule(), checking overall timeout\n",
832 uid
, hd
->locker_uid
);
834 spin_lock_irqsave(&hd
->core_lock
, flags
);
836 finish_wait(hw_access
? &hd
->scsi_wait_queue
:
837 &hd
->fast_wait_queue
, &wait
);
840 if (hw_access
&& acquired
) {
841 if (hd
->scsi_nonblocking_attempts
)
842 hd
->scsi_nonblocking_attempts
= 0;
844 /* Wake any other SCSI/SATA waiters so they can get reentrant
845 * access to the same port if appropriate. This is because if
846 * the SATA core is locked by fast access, or SCSI/SATA access
847 * to other port, then can have >1 SCSI/SATA waiters on the wait
848 * list so want to give reentrant accessors a chance to get
851 if (!list_empty(&hd
->scsi_wait_queue
.task_list
))
852 wake_up(&hd
->scsi_wait_queue
);
855 DPRINTK("Leaving uid %p with acquired = %d, port %d, callback %p\n",
856 uid
, acquired
, port_no
, callback
);
858 spin_unlock_irqrestore(&hd
->core_lock
, flags
);
863 int sata_core_has_fast_waiters(struct ata_host
*ah
)
867 struct sata_oxnas_host_priv
*hd
= ah
->private_data
;
869 spin_lock_irqsave(&hd
->core_lock
, flags
);
870 has_waiters
= !list_empty(&hd
->fast_wait_queue
.task_list
);
871 spin_unlock_irqrestore(&hd
->core_lock
, flags
);
875 EXPORT_SYMBOL(sata_core_has_fast_waiters
);
877 int sata_core_has_scsi_waiters(struct ata_host
*ah
)
881 struct sata_oxnas_host_priv
*hd
= ah
->private_data
;
883 spin_lock_irqsave(&hd
->core_lock
, flags
);
884 has_waiters
= hd
->scsi_nonblocking_attempts
||
885 !list_empty(&hd
->scsi_wait_queue
.task_list
);
886 spin_unlock_irqrestore(&hd
->core_lock
, flags
);
890 EXPORT_SYMBOL(sata_core_has_scsi_waiters
);
893 * ata_port operation to gain ownership of the SATA hardware prior to issuing
894 * a command against a SATA host. Allows any number of users of the port against
895 * which the lock was first acquired, thus enforcing that only one SATA core
896 * port may be operated on at once.
898 static int sata_oxnas_acquire_hw(
903 return __acquire_sata_core(ap
->host
, ap
->port_no
, NULL
, 0, may_sleep
,
904 timeout_jiffies
, 1, (void *)HW_LOCKER_UID
,
909 * operation to release ownership of the SATA hardware
911 static void sata_oxnas_release_hw(struct ata_port
*ap
)
915 struct sata_oxnas_host_priv
*hd
= ap
->host
->private_data
;
917 spin_lock_irqsave(&hd
->core_lock
, flags
);
919 DPRINTK("Entered port_no = %d, h/w count %d, d count %d, "
920 "core locked = %d, reentrant_port_no = %d, isr_callback %p\n",
921 ap
->port_no
, hd
->hw_lock_count
, hd
->direct_lock_count
,
922 hd
->core_locked
, hd
->reentrant_port_no
, hd
->isr_callback
);
924 if (!hd
->core_locked
) {
925 /* Nobody holds the SATA lock */
926 printk(KERN_WARNING
"Nobody holds SATA lock, port_no %d\n",
929 } else if (!hd
->hw_lock_count
) {
930 /* SCSI/SATA has released without holding the lock */
931 printk(KERN_WARNING
"SCSI/SATA does not hold SATA lock, "
932 "port_no %d\n", ap
->port_no
);
934 /* Trap incorrect usage */
935 BUG_ON(hd
->reentrant_port_no
== -1);
936 BUG_ON(ap
->port_no
!= hd
->reentrant_port_no
);
937 BUG_ON(hd
->direct_lock_count
);
938 BUG_ON(hd
->current_locker_type
!= SATA_SCSI_STACK
);
940 WARN(!hd
->locker_uid
|| (hd
->locker_uid
!= HW_LOCKER_UID
),
941 "Invalid locker uid %p, h/w count %d, d count %d, "
942 "reentrant_port_no %d, core_locked %d, "
943 "isr_callback %p\n", hd
->locker_uid
, hd
->hw_lock_count
,
944 hd
->direct_lock_count
, hd
->reentrant_port_no
,
945 hd
->core_locked
, hd
->isr_callback
);
947 if (--(hd
->hw_lock_count
)) {
948 DPRINTK("Still nested port_no %d\n", ap
->port_no
);
950 DPRINTK("Release port_no %d\n", ap
->port_no
);
951 hd
->reentrant_port_no
= -1;
952 hd
->isr_callback
= NULL
;
953 hd
->current_locker_type
= SATA_UNLOCKED
;
957 wake_up(!list_empty(&hd
->scsi_wait_queue
.task_list
) ?
958 &hd
->scsi_wait_queue
:
959 &hd
->fast_wait_queue
);
963 DPRINTK("Leaving, port_no %d, count %d\n", ap
->port_no
,
966 spin_unlock_irqrestore(&hd
->core_lock
, flags
);
968 /* CONFIG_SATA_OX820_DIRECT_HWRAID */
970 ox820hwraid_restart_queue();
974 static inline int sata_oxnas_is_host_frozen(struct ata_host
*ah
)
976 struct sata_oxnas_host_priv
*hd
= ah
->private_data
;
979 return hd
->port_in_eh
|| hd
->port_frozen
;
983 static inline u32
sata_oxnas_hostportbusy(struct ata_port
*ap
)
985 struct sata_oxnas_host_priv
*hd
= ap
->host
->private_data
;
987 return (ioread32(hd
->port_base
+ SATA_COMMAND
) & CMD_CORE_BUSY
) ||
989 (ioread32(hd
->port_base
+ PORT_SIZE
+ SATA_COMMAND
) &
993 static inline u32
sata_oxnas_hostdmabusy(struct ata_port
*ap
)
995 struct sata_oxnas_port_priv
*pd
= ap
->private_data
;
997 return ioread32(pd
->sgdma_base
+ SGDMA_STATUS
) & SGDMA_BUSY
;
1002 * Turns on the cores clock and resets it
1004 static void sata_oxnas_reset_core(struct ata_host
*ah
)
1006 struct sata_oxnas_host_priv
*host_priv
= ah
->private_data
;
1010 clk_prepare_enable(host_priv
->clk
);
1012 reset_control_assert(host_priv
->rst_sata
);
1013 reset_control_assert(host_priv
->rst_link
);
1014 reset_control_assert(host_priv
->rst_phy
);
1018 /* un-reset the PHY, then Link and Controller */
1019 reset_control_deassert(host_priv
->rst_phy
);
1022 reset_control_deassert(host_priv
->rst_sata
);
1023 reset_control_deassert(host_priv
->rst_link
);
1027 /* tune for sata compatibility */
1028 sata_oxnas_link_write(ah
->ports
[0], 0x60, 0x2988);
1030 for (n
= 0; n
< host_priv
->n_ports
; n
++) {
1031 /* each port in turn */
1032 sata_oxnas_link_write(ah
->ports
[n
], 0x70, 0x55629);
1039 * Called after an identify device command has worked out what kind of device
1042 * @param port The port to configure
1043 * @param pdev The hardware associated with controlling the port
1045 static void sata_oxnas_dev_config(struct ata_device
*pdev
)
1047 struct sata_oxnas_port_priv
*pd
= pdev
->link
->ap
->private_data
;
1048 void __iomem
*port_base
= pd
->port_base
;
1052 /* Set the bits to put the port into 28 or 48-bit node */
1053 reg
= ioread32(port_base
+ DRIVE_CONTROL
);
1055 reg
|= (pdev
->flags
& ATA_DFLAG_LBA48
) ? DR_CON_48
: DR_CON_28
;
1056 iowrite32(reg
, port_base
+ DRIVE_CONTROL
);
1058 /* if this is an ATA-6 disk, put port into ATA-5 auto translate mode */
1059 if (pdev
->flags
& ATA_DFLAG_LBA48
) {
1060 reg
= ioread32(port_base
+ PORT_CONTROL
);
1062 iowrite32(reg
, port_base
+ PORT_CONTROL
);
1066 * called to write a taskfile into the ORB registers
1067 * @param ap hardware with the registers in
1068 * @param tf taskfile to write to the registers
1070 static void sata_oxnas_tf_load(struct ata_port
*ap
,
1071 const struct ata_taskfile
*tf
)
1080 struct sata_oxnas_port_priv
*port_priv
= ap
->private_data
;
1081 void __iomem
*port_base
= port_priv
->port_base
;
1082 unsigned int is_addr
= tf
->flags
& ATA_TFLAG_ISADDR
;
1084 /* wait a maximum of 10ms for the core to be idle */
1086 Command_Reg
= ioread32(port_base
+ SATA_COMMAND
);
1087 if (!(Command_Reg
& CMD_CORE_BUSY
))
1091 } while (count
< 200);
1093 /* check if the ctl register has interrupts disabled or enabled and
1094 * modify the interrupt enable registers on the ata core as required */
1095 if (tf
->ctl
& ATA_NIEN
) {
1096 /* interrupts disabled */
1097 u32 mask
= (COREINT_END
<< ap
->port_no
);
1099 iowrite32(mask
, port_priv
->core_base
+ CORE_INT_DISABLE
);
1100 sata_oxnas_irq_clear(ap
);
1102 sata_oxnas_irq_on(ap
);
1105 Orb2
|= (tf
->command
) << 24;
1107 /* write 48 or 28 bit tf parameters */
1109 /* set LBA bit as it's an address */
1110 Orb1
|= (tf
->device
& ATA_LBA
) << 24;
1112 if (tf
->flags
& ATA_TFLAG_LBA48
) {
1113 Orb1
|= ATA_LBA
<< 24;
1114 Orb2
|= (tf
->hob_nsect
) << 8;
1115 Orb3
|= (tf
->hob_lbal
) << 24;
1116 Orb4
|= (tf
->hob_lbam
) << 0;
1117 Orb4
|= (tf
->hob_lbah
) << 8;
1118 Orb4
|= (tf
->hob_feature
) << 16;
1120 Orb3
|= (tf
->device
& 0xf) << 24;
1123 /* write 28-bit lba */
1124 Orb2
|= (tf
->nsect
) << 0;
1125 Orb2
|= (tf
->feature
) << 16;
1126 Orb3
|= (tf
->lbal
) << 0;
1127 Orb3
|= (tf
->lbam
) << 8;
1128 Orb3
|= (tf
->lbah
) << 16;
1129 Orb4
|= (tf
->ctl
) << 24;
1132 if (tf
->flags
& ATA_TFLAG_DEVICE
)
1133 Orb1
|= (tf
->device
) << 24;
1135 ap
->last_ctl
= tf
->ctl
;
1137 /* write values to registers */
1138 iowrite32(Orb1
, port_base
+ ORB1
);
1139 iowrite32(Orb2
, port_base
+ ORB2
);
1140 iowrite32(Orb3
, port_base
+ ORB3
);
1141 iowrite32(Orb4
, port_base
+ ORB4
);
1145 void sata_oxnas_set_mode(struct ata_host
*ah
, u32 mode
, u32 force
)
1147 struct sata_oxnas_host_priv
*host_priv
= ah
->private_data
;
1148 void __iomem
*core_base
= host_priv
->core_base
;
1152 unsigned int progmicrocode
= 0;
1153 unsigned int changeparameters
= 0;
1157 /* these micro-code programs _should_ include the version word */
1160 static const unsigned int jbod
[] = {
1161 0x07B400AC, 0x0228A280, 0x00200001, 0x00204002, 0x00224001,
1162 0x00EE0009, 0x00724901, 0x01A24903, 0x00E40009, 0x00224001,
1163 0x00621120, 0x0183C908, 0x00E20005, 0x00718908, 0x0198A206,
1164 0x00621124, 0x0183C908, 0x00E20046, 0x00621104, 0x0183C908,
1165 0x00E20015, 0x00EE009D, 0x01A3E301, 0x00E2001B, 0x0183C900,
1166 0x00E2001B, 0x00210001, 0x00EE0020, 0x01A3E302, 0x00E2009D,
1167 0x0183C901, 0x00E2009D, 0x00210002, 0x0235D700, 0x0208A204,
1168 0x0071C908, 0x000F8207, 0x000FC207, 0x0071C920, 0x000F8507,
1169 0x000FC507, 0x0228A240, 0x02269A40, 0x00094004, 0x00621104,
1170 0x0180C908, 0x00E40031, 0x00621112, 0x01A3C801, 0x00E2002B,
1171 0x00294000, 0x0228A220, 0x01A69ABF, 0x002F8000, 0x002FC000,
1172 0x0198A204, 0x0001C022, 0x01B1A220, 0x0001C106, 0x00088007,
1173 0x0183C903, 0x00E2009D, 0x0228A220, 0x0071890C, 0x0208A206,
1174 0x0198A206, 0x0001C022, 0x01B1A220, 0x0001C106, 0x00088007,
1175 0x00EE009D, 0x00621104, 0x0183C908, 0x00E2004A, 0x00EE009D,
1176 0x01A3C901, 0x00E20050, 0x0021E7FF, 0x0183E007, 0x00E2009D,
1177 0x00EE0054, 0x0061600B, 0x0021E7FF, 0x0183C507, 0x00E2009D,
1178 0x01A3E301, 0x00E2005A, 0x0183C900, 0x00E2005A, 0x00210001,
1179 0x00EE005F, 0x01A3E302, 0x00E20005, 0x0183C901, 0x00E20005,
1180 0x00210002, 0x0235D700, 0x0208A204, 0x000F8109, 0x000FC109,
1181 0x0071C918, 0x000F8407, 0x000FC407, 0x0001C022, 0x01A1A2BF,
1182 0x0001C106, 0x00088007, 0x02269A40, 0x00094004, 0x00621112,
1183 0x01A3C801, 0x00E4007F, 0x00621104, 0x0180C908, 0x00E4008D,
1184 0x00621128, 0x0183C908, 0x00E2006C, 0x01A3C901, 0x00E2007B,
1185 0x0021E7FF, 0x0183E007, 0x00E2007F, 0x00EE006C, 0x0061600B,
1186 0x0021E7FF, 0x0183C507, 0x00E4006C, 0x00621111, 0x01A3C801,
1187 0x00E2007F, 0x00621110, 0x01A3C801, 0x00E20082, 0x0228A220,
1188 0x00621119, 0x01A3C801, 0x00E20086, 0x0001C022, 0x01B1A220,
1189 0x0001C106, 0x00088007, 0x0198A204, 0x00294000, 0x01A69ABF,
1190 0x002F8000, 0x002FC000, 0x0183C903, 0x00E20005, 0x0228A220,
1191 0x0071890C, 0x0208A206, 0x0198A206, 0x0001C022, 0x01B1A220,
1192 0x0001C106, 0x00088007, 0x00EE009D, 0x00621128, 0x0183C908,
1193 0x00E20005, 0x00621104, 0x0183C908, 0x00E200A6, 0x0062111C,
1194 0x0183C908, 0x00E20005, 0x0071890C, 0x0208A206, 0x0198A206,
1195 0x00718908, 0x0208A206, 0x00EE0005, ~0
1198 /* Bi-Modal RAID-0/1 */
1199 static const unsigned int raid
[] = {
1200 0x00F20145, 0x00EE20FA, 0x00EE20A7, 0x0001C009, 0x00EE0004,
1201 0x00220000, 0x0001000B, 0x037003FF, 0x00700018, 0x037003FE,
1202 0x037043FD, 0x00704118, 0x037043FC, 0x01A3D240, 0x00E20017,
1203 0x00B3C235, 0x00E40018, 0x0093C104, 0x00E80014, 0x0093C004,
1204 0x00E80017, 0x01020000, 0x00274020, 0x00EE0083, 0x0080C904,
1205 0x0093C104, 0x00EA0020, 0x0093C103, 0x00EC001F, 0x00220002,
1206 0x00924104, 0x0005C009, 0x00EE0058, 0x0093CF04, 0x00E80026,
1207 0x00900F01, 0x00600001, 0x00910400, 0x00EE0058, 0x00601604,
1208 0x01A00003, 0x00E2002C, 0x01018000, 0x00274040, 0x00EE0083,
1209 0x0093CF03, 0x00EC0031, 0x00220003, 0x00924F04, 0x0005C009,
1210 0x00810104, 0x00B3C235, 0x00E20037, 0x0022C000, 0x00218210,
1211 0x00EE0039, 0x0022C001, 0x00218200, 0x00600401, 0x00A04901,
1212 0x00604101, 0x01A0C401, 0x00E20040, 0x00216202, 0x00EE0041,
1213 0x00216101, 0x02018506, 0x00EE2141, 0x00904901, 0x00E20049,
1214 0x00A00401, 0x00600001, 0x02E0C301, 0x00EE2141, 0x00216303,
1215 0x037003EE, 0x01A3C001, 0x00E40105, 0x00250080, 0x00204000,
1216 0x002042F1, 0x0004C001, 0x00230001, 0x00100006, 0x02C18605,
1217 0x00100006, 0x01A3D502, 0x00E20055, 0x00EE0053, 0x00004009,
1218 0x00000004, 0x00B3C235, 0x00E40062, 0x0022C001, 0x0020C000,
1219 0x00EE2141, 0x0020C001, 0x00EE2141, 0x00EE006B, 0x0022C000,
1220 0x0060D207, 0x00EE2141, 0x00B3C242, 0x00E20069, 0x01A3D601,
1221 0x00E2006E, 0x02E0C301, 0x00EE2141, 0x00230001, 0x00301303,
1222 0x00EE007B, 0x00218210, 0x01A3C301, 0x00E20073, 0x00216202,
1223 0x00EE0074, 0x00216101, 0x02018506, 0x00214000, 0x037003EE,
1224 0x01A3C001, 0x00E40108, 0x00230001, 0x00100006, 0x00250080,
1225 0x00204000, 0x002042F1, 0x0004C001, 0x00EE007F, 0x0024C000,
1226 0x01A3D1F0, 0x00E20088, 0x00230001, 0x00300000, 0x01A3D202,
1227 0x00E20085, 0x00EE00A5, 0x00B3C800, 0x00E20096, 0x00218000,
1228 0x00924709, 0x0005C009, 0x00B20802, 0x00E40093, 0x037103FD,
1229 0x00710418, 0x037103FC, 0x00EE0006, 0x00220000, 0x0001000F,
1230 0x00EE0006, 0x00800B0C, 0x00B00001, 0x00204000, 0x00208550,
1231 0x00208440, 0x002083E0, 0x00208200, 0x00208100, 0x01008000,
1232 0x037083EE, 0x02008212, 0x02008216, 0x01A3C201, 0x00E400A5,
1233 0x0100C000, 0x00EE20FA, 0x02800000, 0x00208000, 0x00B24C00,
1234 0x00E400AD, 0x00224001, 0x00724910, 0x0005C009, 0x00B3CDC4,
1235 0x00E200D5, 0x00B3CD29, 0x00E200D5, 0x00B3CD20, 0x00E200D5,
1236 0x00B3CD24, 0x00E200D5, 0x00B3CDC5, 0x00E200D2, 0x00B3CD39,
1237 0x00E200D2, 0x00B3CD30, 0x00E200D2, 0x00B3CD34, 0x00E200D2,
1238 0x00B3CDCA, 0x00E200CF, 0x00B3CD35, 0x00E200CF, 0x00B3CDC8,
1239 0x00E200CC, 0x00B3CD25, 0x00E200CC, 0x00B3CD40, 0x00E200CB,
1240 0x00B3CD42, 0x00E200CB, 0x01018000, 0x00EE0083, 0x0025C000,
1241 0x036083EE, 0x0000800D, 0x00EE00D8, 0x036083EE, 0x00208035,
1242 0x00EE00DA, 0x036083EE, 0x00208035, 0x00EE00DA, 0x00208007,
1243 0x036083EE, 0x00208025, 0x036083EF, 0x02400000, 0x01A3D208,
1244 0x00E200D8, 0x0067120A, 0x0021C000, 0x0021C224, 0x00220000,
1245 0x00404B1C, 0x00600105, 0x00800007, 0x0020C00E, 0x00214000,
1246 0x01004000, 0x01A0411F, 0x00404E01, 0x01A3C101, 0x00E200F1,
1247 0x00B20800, 0x00E400D8, 0x00220001, 0x0080490B, 0x00B04101,
1248 0x0040411C, 0x00EE00E1, 0x02269A01, 0x01020000, 0x02275D80,
1249 0x01A3D202, 0x00E200F4, 0x01B75D80, 0x01030000, 0x01B69A01,
1250 0x00EE00D8, 0x01A3D204, 0x00E40104, 0x00224000, 0x0020C00E,
1251 0x0020001E, 0x00214000, 0x01004000, 0x0212490E, 0x00214001,
1252 0x01004000, 0x02400000, 0x00B3D702, 0x00E80112, 0x00EE010E,
1253 0x00B3D702, 0x00E80112, 0x00B3D702, 0x00E4010E, 0x00230001,
1254 0x00EE0140, 0x00200005, 0x036003EE, 0x00204001, 0x00EE0116,
1255 0x00230001, 0x00100006, 0x02C18605, 0x00100006, 0x01A3D1F0,
1256 0x00E40083, 0x037003EE, 0x01A3C002, 0x00E20121, 0x0020A300,
1257 0x0183D102, 0x00E20124, 0x037003EE, 0x01A00005, 0x036003EE,
1258 0x01A0910F, 0x00B3C20F, 0x00E2012F, 0x01A3D502, 0x00E20116,
1259 0x01A3C002, 0x00E20116, 0x00B3D702, 0x00E4012C, 0x00300000,
1260 0x00EE011F, 0x02C18605, 0x00100006, 0x00EE0116, 0x01A3D1F0,
1261 0x00E40083, 0x037003EE, 0x01A3C004, 0x00E20088, 0x00200003,
1262 0x036003EE, 0x01A3D502, 0x00E20136, 0x00230001, 0x00B3C101,
1263 0x00E4012C, 0x00100006, 0x02C18605, 0x00100006, 0x00204000,
1264 0x00EE0116, 0x00100006, 0x01A3D1F0, 0x00E40083, 0x01000000,
1268 DPRINTK("ENTER: mode:%d, force:%d\n", mode
, force
);
1271 previous_mode
= UNKNOWN_MODE
;
1273 previous_mode
= host_priv
->current_ucode
;
1275 if (mode
== previous_mode
)
1278 host_priv
->current_ucode
= mode
;
1280 /* decide what needs to be done using the STD in my logbook */
1281 switch (previous_mode
) {
1282 case OXNASSATA_RAID1
:
1284 case OXNASSATA_RAID0
:
1285 changeparameters
= 1;
1287 case OXNASSATA_NOTRAID
:
1288 changeparameters
= 1;
1293 case OXNASSATA_RAID0
:
1295 case OXNASSATA_RAID1
:
1296 changeparameters
= 1;
1298 case OXNASSATA_NOTRAID
:
1299 changeparameters
= 1;
1304 case OXNASSATA_NOTRAID
:
1306 case OXNASSATA_RAID0
:
1307 case OXNASSATA_RAID1
:
1308 changeparameters
= 1;
1314 changeparameters
= 1;
1319 /* no need to reprogram everything if already in the right mode */
1320 if (progmicrocode
) {
1321 /* reset micro-code processor */
1322 iowrite32(1, core_base
+ PROC_RESET
);
1325 /* select micro-code */
1327 case OXNASSATA_RAID1
:
1328 case OXNASSATA_RAID0
:
1329 VPRINTK("Loading RAID micro-code\n");
1330 src
= (unsigned int *)&raid
[1];
1332 case OXNASSATA_NOTRAID
:
1333 VPRINTK("Loading JBOD micro-code\n");
1334 src
= (unsigned int *)&jbod
[1];
1341 /* load micro code */
1342 dst
= core_base
+ UCODE_STORE
;
1343 while (*src
!= ~0) {
1344 iowrite32(*src
, dst
);
1346 dst
+= sizeof(*src
);
1351 if (changeparameters
) {
1353 /* set other mode dependent flags */
1355 case OXNASSATA_RAID1
:
1356 /* clear JBOD mode */
1357 reg
= ioread32(core_base
+ DATA_PLANE_CTRL
);
1358 reg
|= DPC_JBOD_UCODE
;
1359 reg
&= ~DPC_FIS_SWCH
;
1360 iowrite32(reg
, core_base
+ DATA_PLANE_CTRL
);
1363 /* set the hardware up for RAID-1 */
1364 iowrite32(0, core_base
+ RAID_WP_BOT_LOW
);
1365 iowrite32(0, core_base
+ RAID_WP_BOT_HIGH
);
1366 iowrite32(0xffffffff, core_base
+ RAID_WP_TOP_LOW
);
1367 iowrite32(0x7fffffff, core_base
+ RAID_WP_TOP_HIGH
);
1368 iowrite32(0, core_base
+ RAID_SIZE_LOW
);
1369 iowrite32(0, core_base
+ RAID_SIZE_HIGH
);
1372 case OXNASSATA_RAID0
:
1373 /* clear JBOD mode */
1374 reg
= ioread32(core_base
+ DATA_PLANE_CTRL
);
1375 reg
|= DPC_JBOD_UCODE
;
1376 reg
&= ~DPC_FIS_SWCH
;
1377 iowrite32(reg
, core_base
+ DATA_PLANE_CTRL
);
1380 /* set the hardware up for RAID-1 */
1381 iowrite32(0, core_base
+ RAID_WP_BOT_LOW
);
1382 iowrite32(0, core_base
+ RAID_WP_BOT_HIGH
);
1383 iowrite32(0xffffffff, core_base
+ RAID_WP_TOP_LOW
);
1384 iowrite32(0x7fffffff, core_base
+ RAID_WP_TOP_HIGH
);
1385 iowrite32(0xffffffff, core_base
+ RAID_SIZE_LOW
);
1386 iowrite32(0x7fffffff, core_base
+ RAID_SIZE_HIGH
);
1389 case OXNASSATA_NOTRAID
:
1390 /* enable jbod mode */
1391 reg
= ioread32(core_base
+ DATA_PLANE_CTRL
);
1392 reg
&= ~DPC_JBOD_UCODE
;
1393 reg
&= ~DPC_FIS_SWCH
;
1394 iowrite32(reg
, core_base
+ DATA_PLANE_CTRL
);
1397 /* start micro-code processor*/
1398 iowrite32(1, core_base
+ PROC_START
);
1401 reg
= ioread32(core_base
+ DATA_PLANE_CTRL
);
1402 reg
|= DPC_JBOD_UCODE
;
1403 reg
&= ~DPC_FIS_SWCH
;
1404 iowrite32(reg
, core_base
+ DATA_PLANE_CTRL
);
1412 * sends a sync-escape if there is a link present
1414 static inline void sata_oxnas_send_sync_escape(struct ata_port
*ap
)
1416 struct sata_oxnas_port_priv
*pd
= ap
->private_data
;
1419 /* read the SSTATUS register and only send a sync escape if there is a
1421 if ((sata_oxnas_link_read(ap
, 0x20) & 3) == 3) {
1422 reg
= ioread32(pd
->port_base
+ SATA_COMMAND
);
1423 reg
&= ~SATA_OPCODE_MASK
;
1424 reg
|= CMD_SYNC_ESCAPE
;
1425 iowrite32(reg
, pd
->port_base
+ SATA_COMMAND
);
1430 static inline void sata_oxnas_clear_CS_error(struct ata_port
*ap
)
1432 struct sata_oxnas_port_priv
*pd
= ap
->private_data
;
1433 u32
*base
= pd
->port_base
;
1436 reg
= ioread32(base
+ SATA_CONTROL
);
1437 reg
&= SATA_CTL_ERR_MASK
;
1438 iowrite32(reg
, base
+ SATA_CONTROL
);
1441 static inline void sata_oxnas_reset_sgdma(struct ata_port
*ap
)
1443 struct sata_oxnas_port_priv
*pd
= ap
->private_data
;
1445 iowrite32(SGDMA_RESETS_CTRL
, pd
->sgdma_base
+ SGDMA_RESETS
);
1448 static inline void sata_oxnas_reset_dma(struct ata_port
*ap
, int assert)
1450 struct sata_oxnas_port_priv
*pd
= ap
->private_data
;
1453 reg
= ioread32(pd
->dmactl_base
+ DMA_CONTROL
);
1455 reg
|= DMA_CONTROL_RESET
;
1457 reg
&= ~DMA_CONTROL_RESET
;
1459 iowrite32(reg
, pd
->dmactl_base
+ DMA_CONTROL
);
1463 * Clears the error caused by the core's registers being accessed when the
1466 static inline void sata_oxnas_clear_reg_access_error(struct ata_port
*ap
)
1468 struct sata_oxnas_port_priv
*pd
= ap
->private_data
;
1469 u32
*base
= pd
->port_base
;
1472 reg
= ioread32(base
+ INT_STATUS
);
1475 if (reg
& INT_REG_ACCESS_ERR
) {
1476 DPRINTK("clearing register access error on port %d\n",
1478 iowrite32(INT_REG_ACCESS_ERR
, base
+ INT_STATUS
);
1480 reg
= ioread32(base
+ INT_STATUS
);
1481 if (reg
& INT_REG_ACCESS_ERR
)
1482 DPRINTK("register access error didn't clear\n");
1485 static inline void sata_oxnas_clear_sctl_error(struct ata_port
*ap
)
1487 struct sata_oxnas_port_priv
*pd
= ap
->private_data
;
1488 u32
*base
= pd
->port_base
;
1491 reg
= ioread32(base
+ SATA_CONTROL
);
1492 reg
|= SCTL_CLR_ERR
;
1493 iowrite32(reg
, base
+ SATA_CONTROL
);
1496 static inline void sata_oxnas_clear_raid_error(struct ata_host
*ah
)
1502 * Clean up all the state machines in the sata core.
1503 * @return post cleanup action required
1505 static int sata_oxnas_cleanup(struct ata_host
*ah
)
1507 struct sata_oxnas_host_priv
*hd
= ah
->private_data
;
1508 int actions_required
= 0;
1511 printk(KERN_INFO
"sata_oxnas: resetting SATA core\n");
1512 /* core not recovering, reset it */
1514 sata_oxnas_reset_core(ah
);
1516 actions_required
|= OXNAS_SATA_REINIT
;
1517 /* Perform any SATA core re-initialisation after reset post reset init
1518 * needs to be called for both ports as there's one reset for both
1520 for (n
= 0; n
< hd
->n_ports
; n
++)
1521 sata_oxnas_post_reset_init(ah
->ports
[n
]);
1524 return actions_required
;
1528 * ata_qc_new - Request an available ATA command, for queueing
1529 * @ap: Port associated with device @dev
1530 * @return non zero will refuse a new command, zero will may grant on subject
1531 * to conditions elsewhere.
1534 static int sata_oxnas_qc_new(struct ata_port
*ap
)
1536 struct sata_oxnas_host_priv
*hd
= ap
->host
->private_data
;
1538 DPRINTK("port %d\n", ap
->port_no
);
1540 if (hd
->port_frozen
|| hd
->port_in_eh
)
1543 return !sata_oxnas_acquire_hw(ap
, 0, 0);
1547 * releases the lock on the port the command used
1549 static void sata_oxnas_qc_free(struct ata_queued_cmd
*qc
)
1552 sata_oxnas_release_hw(qc
->ap
);
1555 static void sata_oxnas_freeze(struct ata_port
*ap
)
1557 struct sata_oxnas_host_priv
*hd
= ap
->host
->private_data
;
1560 hd
->port_frozen
|= BIT(ap
->port_no
);
1564 static void sata_oxnas_thaw(struct ata_port
*ap
)
1566 struct sata_oxnas_host_priv
*hd
= ap
->host
->private_data
;
1569 hd
->port_frozen
&= ~BIT(ap
->port_no
);
1573 void sata_oxnas_freeze_host(struct ata_port
*ap
)
1575 struct sata_oxnas_host_priv
*hd
= ap
->host
->private_data
;
1578 hd
->port_in_eh
|= BIT(ap
->port_no
);
1582 void sata_oxnas_thaw_host(struct ata_port
*ap
)
1584 struct sata_oxnas_host_priv
*hd
= ap
->host
->private_data
;
1587 hd
->port_in_eh
&= ~BIT(ap
->port_no
);
1591 static void sata_oxnas_post_internal_cmd(struct ata_queued_cmd
*qc
)
1594 /* If the core is busy here, make it idle */
1595 if (qc
->flags
& ATA_QCFLAG_FAILED
)
1596 sata_oxnas_cleanup(qc
->ap
->host
);
1601 * turn on the interrupts
1603 * @param ap Hardware with the registers in
1605 static void sata_oxnas_irq_on(struct ata_port
*ap
)
1607 struct sata_oxnas_port_priv
*pd
= ap
->private_data
;
1608 u32 mask
= (COREINT_END
<< ap
->port_no
);
1610 /* Clear pending interrupts */
1611 iowrite32(~0, pd
->port_base
+ INT_CLEAR
);
1612 iowrite32(mask
, pd
->core_base
+ CORE_INT_STATUS
);
1615 /* enable End of command interrupt */
1616 iowrite32(INT_WANT
, pd
->port_base
+ INT_ENABLE
);
1617 iowrite32(mask
, pd
->core_base
+ CORE_INT_ENABLE
);
1621 /** @return true if the port has a cable connected */
1622 int sata_oxnas_check_link(struct ata_port
*ap
)
1626 sata_oxnas_scr_read_port(ap
, SCR_STATUS
, ®
);
1627 /* Check for the cable present indicated by SCR status bit-0 set */
1632 * ata_std_postreset - standard postreset callback
1633 * @link: the target ata_link
1634 * @classes: classes of attached devices
1636 * This function is invoked after a successful reset. Note that
1637 * the device might have been reset more than once using
1638 * different reset methods before postreset is invoked.
1641 * Kernel thread context (may sleep)
1643 static void sata_oxnas_postreset(struct ata_link
*link
, unsigned int *classes
)
1645 struct ata_port
*ap
= link
->ap
;
1646 struct sata_oxnas_host_priv
*hd
= ap
->host
->private_data
;
1651 ata_std_postreset(link
, classes
);
1653 /* turn on phy error detection by removing the masks */
1654 sata_oxnas_link_write(ap
->host
->ports
[0], 0x0c, 0x30003);
1655 if (hd
->n_ports
> 1)
1656 sata_oxnas_link_write(ap
->host
->ports
[1], 0x0c, 0x30003);
1658 /* bail out if no device is present */
1659 if (classes
[0] == ATA_DEV_NONE
&& classes
[1] == ATA_DEV_NONE
) {
1660 DPRINTK("EXIT, no device\n");
1664 /* go through all the devices and configure them */
1665 for (dev
= 0; dev
< ATA_MAX_DEVICES
; ++dev
) {
1666 if (ap
->link
.device
[dev
].class == ATA_DEV_ATA
)
1667 sata_oxnas_dev_config(&(ap
->link
.device
[dev
]));
1674 * Called to read the hardware registers / DMA buffers, to
1675 * obtain the current set of taskfile register values.
1676 * @param ap hardware with the registers in
1677 * @param tf taskfile to read the registers into
1679 static void sata_oxnas_tf_read(struct ata_port
*ap
, struct ata_taskfile
*tf
)
1681 struct sata_oxnas_port_priv
*port_priv
= ap
->private_data
;
1682 void __iomem
*port_base
= port_priv
->port_base
;
1683 /* read the orb registers */
1684 u32 Orb1
= ioread32(port_base
+ ORB1
);
1685 u32 Orb2
= ioread32(port_base
+ ORB2
);
1686 u32 Orb3
= ioread32(port_base
+ ORB3
);
1687 u32 Orb4
= ioread32(port_base
+ ORB4
);
1689 /* read common 28/48 bit tf parameters */
1690 tf
->device
= (Orb1
>> 24);
1691 tf
->nsect
= (Orb2
>> 0);
1692 tf
->feature
= (Orb2
>> 16);
1693 tf
->command
= sata_oxnas_check_status(ap
);
1695 /* read 48 or 28 bit tf parameters */
1696 if (tf
->flags
& ATA_TFLAG_LBA48
) {
1697 tf
->hob_nsect
= (Orb2
>> 8);
1698 tf
->lbal
= (Orb3
>> 0);
1699 tf
->lbam
= (Orb3
>> 8);
1700 tf
->lbah
= (Orb3
>> 16);
1701 tf
->hob_lbal
= (Orb3
>> 24);
1702 tf
->hob_lbam
= (Orb4
>> 0);
1703 tf
->hob_lbah
= (Orb4
>> 8);
1704 /* feature ext and control are write only */
1706 /* read 28-bit lba */
1707 tf
->lbal
= (Orb3
>> 0);
1708 tf
->lbam
= (Orb3
>> 8);
1709 tf
->lbah
= (Orb3
>> 16);
1714 * Read a result task-file from the sata core registers.
1716 static bool sata_oxnas_qc_fill_rtf(struct ata_queued_cmd
*qc
)
1718 /* Read the most recently received FIS from the SATA core ORB registers
1719 and convert to an ATA taskfile */
1720 sata_oxnas_tf_read(qc
->ap
, &qc
->result_tf
);
1725 * Reads the Status ATA shadow register from hardware.
1727 * @return The status register
1729 static u8
sata_oxnas_check_status(struct ata_port
*ap
)
1733 struct sata_oxnas_port_priv
*port_priv
= ap
->private_data
;
1734 void __iomem
*port_base
= port_priv
->port_base
;
1736 /* read byte 3 of Orb2 register */
1737 status
= ioread32(port_base
+ ORB2
) >> 24;
1739 /* check for the drive going missing indicated by SCR status bits
1741 sata_oxnas_scr_read_port(ap
, SCR_STATUS
, &Reg
);
1751 static inline void sata_oxnas_reset_ucode(struct ata_host
*ah
, int force
,
1754 struct sata_oxnas_host_priv
*hd
= ah
->private_data
;
1760 sata_oxnas_set_mode(ah
, UNKNOWN_MODE
, force
);
1761 reg
= ioread32(hd
->core_base
+ DEVICE_CONTROL
);
1762 reg
|= DEVICE_CONTROL_ATA_ERR_OVERRIDE
;
1763 iowrite32(reg
, hd
->core_base
+ DEVICE_CONTROL
);
1766 sata_oxnas_set_mode(ah
, OXNASSATA_NOTRAID
, force
);
1767 /* Turn the work around off as it may have been left on by any
1768 * HW-RAID code that we've been working with */
1769 iowrite32(0x0, hd
->core_base
+ PORT_ERROR_MASK
);
1774 * Prepare as much as possible for a command without involving anything that is
1775 * shared between ports.
1777 static void sata_oxnas_qc_prep(struct ata_queued_cmd
*qc
)
1779 struct sata_oxnas_port_priv
*pd
;
1780 int port_no
= qc
->ap
->port_no
;
1782 /* if the port's not connected, complete now with an error */
1783 if (!sata_oxnas_check_link(qc
->ap
)) {
1784 ata_port_err(qc
->ap
,
1785 "port %d not connected completing with error\n",
1787 qc
->err_mask
|= AC_ERR_ATA_BUS
;
1788 ata_qc_complete(qc
);
1791 sata_oxnas_reset_ucode(qc
->ap
->host
, 0, 0);
1793 /* both pio and dma commands use dma */
1794 if (ata_is_dma(qc
->tf
.protocol
) || ata_is_pio(qc
->tf
.protocol
)) {
1796 /* program the scatterlist into the prd table */
1797 ata_bmdma_qc_prep(qc
);
1799 /* point the sgdma controller at the dma request structure */
1800 pd
= qc
->ap
->private_data
;
1802 iowrite32(pd
->sgdma_request_pa
,
1803 pd
->sgdma_base
+ SGDMA_REQUESTPTR
);
1805 /* setup the request table */
1807 pd
->sgdma_request
->control
=
1808 (qc
->dma_dir
== DMA_FROM_DEVICE
) ?
1809 SGDMA_REQCTL0IN
: SGDMA_REQCTL0OUT
;
1811 pd
->sgdma_request
->control
=
1812 (qc
->dma_dir
== DMA_FROM_DEVICE
) ?
1813 SGDMA_REQCTL1IN
: SGDMA_REQCTL1OUT
;
1815 pd
->sgdma_request
->qualifier
= SGDMA_REQQUAL
;
1816 pd
->sgdma_request
->src_pa
= qc
->ap
->bmdma_prd_dma
;
1817 pd
->sgdma_request
->dst_pa
= qc
->ap
->bmdma_prd_dma
;
1820 /* tell it to wait */
1821 iowrite32(SGDMA_CONTROL_NOGO
, pd
->sgdma_base
+ SGDMA_CONTROL
);
1825 static int sata_oxnas_port_start(struct ata_port
*ap
)
1827 struct sata_oxnas_host_priv
*host_priv
= ap
->host
->private_data
;
1828 struct device
*dev
= ap
->host
->dev
;
1829 struct sata_oxnas_port_priv
*pp
;
1835 pp
= kzalloc(sizeof(*pp
), GFP_KERNEL
);
1839 pp
->port_base
= host_priv
->port_base
+
1840 (ap
->port_no
? PORT_SIZE
: 0);
1841 pp
->dmactl_base
= host_priv
->dmactl_base
+
1842 (ap
->port_no
? DMA_CORESIZE
: 0);
1843 pp
->sgdma_base
= host_priv
->sgdma_base
+
1844 (ap
->port_no
? SGDMA_CORESIZE
: 0);
1845 pp
->core_base
= host_priv
->core_base
;
1848 if (host_priv
->dma_size
>= SATA_OXNAS_DMA_SIZE
* host_priv
->n_ports
) {
1849 DPRINTK("using preallocated DMA\n");
1850 mem_dma
= host_priv
->dma_base
+
1851 (ap
->port_no
? SATA_OXNAS_DMA_SIZE
: 0);
1852 mem
= ioremap(mem_dma
, SATA_OXNAS_DMA_SIZE
);
1854 mem
= dma_alloc_coherent(dev
, SATA_OXNAS_DMA_SIZE
, &mem_dma
,
1860 pp
->sgdma_request_pa
= mem_dma
;
1861 pp
->sgdma_request
= mem
;
1863 ap
->bmdma_prd_dma
= mem_dma
+ sizeof(struct sgdma_request
);
1864 ap
->bmdma_prd
= mem
+ sizeof(struct sgdma_request
);
1866 ap
->private_data
= pp
;
1868 sata_oxnas_post_reset_init(ap
);
1878 static void sata_oxnas_port_stop(struct ata_port
*ap
)
1880 struct device
*dev
= ap
->host
->dev
;
1881 struct sata_oxnas_port_priv
*pp
= ap
->private_data
;
1882 struct sata_oxnas_host_priv
*host_priv
= ap
->host
->private_data
;
1885 ap
->private_data
= NULL
;
1886 if (host_priv
->dma_size
) {
1887 iounmap(pp
->sgdma_request
);
1889 dma_free_coherent(dev
, SATA_OXNAS_DMA_SIZE
,
1890 pp
->sgdma_request
, pp
->sgdma_request_pa
);
1897 static void sata_oxnas_post_reset_init(struct ata_port
*ap
)
1901 /* force to load u-code only once after reset */
1902 sata_oxnas_reset_ucode(ap
->host
, !ap
->port_no
, 0);
1904 /* turn on phy error detection by removing the masks */
1905 sata_oxnas_link_write(ap
, 0x0C, 0x30003);
1907 /* enable hotplug event detection */
1908 sata_oxnas_scr_write_port(ap
, SCR_ERROR
, ~0);
1909 sata_oxnas_scr_write_port(ap
, SERROR_IRQ_MASK
, 0x03feffff);
1910 sata_oxnas_scr_write_port(ap
, SCR_ACTIVE
, ~0 & ~(1 << 26) & ~(1 << 16));
1912 /* enable interrupts for ports */
1913 sata_oxnas_irq_on(ap
);
1915 /* go through all the devices and configure them */
1916 for (dev
= 0; dev
< ATA_MAX_DEVICES
; ++dev
) {
1917 if (ap
->link
.device
[dev
].class == ATA_DEV_ATA
) {
1918 sata_std_hardreset(&ap
->link
, NULL
, jiffies
+ HZ
);
1919 sata_oxnas_dev_config(&(ap
->link
.device
[dev
]));
1923 /* clean up any remaining errors */
1924 sata_oxnas_scr_write_port(ap
, SCR_ERROR
, ~0);
1929 * host_stop() is called when the rmmod or hot unplug process begins. The
1930 * hook must stop all hardware interrupts, DMA engines, etc.
1932 * @param ap hardware with the registers in
1934 static void sata_oxnas_host_stop(struct ata_host
*host_set
)
1940 #define ERROR_HW_ACQUIRE_TIMEOUT_JIFFIES (10 * HZ)
1941 static void sata_oxnas_error_handler(struct ata_port
*ap
)
1943 DPRINTK("Enter port_no %d\n", ap
->port_no
);
1944 sata_oxnas_freeze_host(ap
);
1946 /* If the core is busy here, make it idle */
1947 sata_oxnas_cleanup(ap
->host
);
1949 ata_std_error_handler(ap
);
1951 sata_oxnas_thaw_host(ap
);
1954 static int sata_oxnas_softreset(struct ata_link
*link
, unsigned int *class,
1955 unsigned long deadline
)
1957 struct ata_port
*ap
= link
->ap
;
1958 struct sata_oxnas_port_priv
*pd
= ap
->private_data
;
1959 void __iomem
*port_base
= pd
->port_base
;
1962 struct ata_taskfile tf
;
1967 port_base
= pd
->port_base
;
1969 if (ata_link_offline(link
)) {
1970 DPRINTK("PHY reports no device\n");
1971 *class = ATA_DEV_NONE
;
1975 /* write value to register */
1976 iowrite32(0, port_base
+ ORB1
);
1977 iowrite32(0, port_base
+ ORB2
);
1978 iowrite32(0, port_base
+ ORB3
);
1979 iowrite32((ap
->ctl
) << 24, port_base
+ ORB4
);
1981 /* command the core to send a control FIS */
1982 Command_Reg
= ioread32(port_base
+ SATA_COMMAND
);
1983 Command_Reg
&= ~SATA_OPCODE_MASK
;
1984 Command_Reg
|= CMD_WRITE_TO_ORB_REGS_NO_COMMAND
;
1985 iowrite32(Command_Reg
, port_base
+ SATA_COMMAND
);
1986 udelay(20); /* FIXME: flush */
1988 /* write value to register */
1989 iowrite32((ap
->ctl
| ATA_SRST
) << 24, port_base
+ ORB4
);
1991 /* command the core to send a control FIS */
1992 Command_Reg
&= ~SATA_OPCODE_MASK
;
1993 Command_Reg
|= CMD_WRITE_TO_ORB_REGS_NO_COMMAND
;
1994 iowrite32(Command_Reg
, port_base
+ SATA_COMMAND
);
1995 udelay(20); /* FIXME: flush */
1997 /* write value to register */
1998 iowrite32((ap
->ctl
) << 24, port_base
+ ORB4
);
2000 /* command the core to send a control FIS */
2001 Command_Reg
&= ~SATA_OPCODE_MASK
;
2002 Command_Reg
|= CMD_WRITE_TO_ORB_REGS_NO_COMMAND
;
2003 iowrite32(Command_Reg
, port_base
+ SATA_COMMAND
);
2007 rc
= ata_sff_wait_ready(link
, deadline
);
2009 /* if link is occupied, -ENODEV too is an error */
2010 if (rc
&& (rc
!= -ENODEV
|| sata_scr_valid(link
))) {
2011 ata_link_printk(link
, KERN_ERR
, "SRST failed (errno=%d)\n", rc
);
2015 /* determine by signature whether we have ATA or ATAPI devices */
2016 sata_oxnas_tf_read(ap
, &tf
);
2017 *class = ata_dev_classify(&tf
);
2019 if (*class == ATA_DEV_UNKNOWN
)
2020 *class = ATA_DEV_NONE
;
2023 DPRINTK("EXIT, class=%u\n", *class);
2028 int sata_oxnas_init_controller(struct ata_host
*host
)
2036 * This code is a work around for a DMA hardware bug that will repeat the
2037 * penultimate 8-bytes on some reads. This code will check that the amount
2038 * of data transferred is a multiple of 512 bytes, if not the in it will
2039 * fetch the correct data from a buffer in the SATA core and copy it into
2042 * @param port SATA port to check and if necessary, correct.
2044 static int sata_oxnas_bug_6320_workaround(struct ata_port
*ap
)
2046 struct sata_oxnas_port_priv
*pd
= ap
->private_data
;
2047 void __iomem
*core_base
= pd
->core_base
;
2049 int quads_transferred
;
2051 int sector_quads_remaining
;
2052 int bug_present
= 0;
2054 /* Only want to apply fix to reads */
2055 is_read
= !(ioread32(core_base
+ DM_DBG1
) & (ap
->port_no
?
2056 BIT(CORE_PORT1_DATA_DIR_BIT
) :
2057 BIT(CORE_PORT0_DATA_DIR_BIT
)));
2059 /* Check for an incomplete transfer, i.e. not a multiple of 512 bytes
2060 transferred (datacount_port register counts quads transferred) */
2062 ioread32(core_base
+ (ap
->port_no
?
2063 DATACOUNT_PORT1
: DATACOUNT_PORT0
));
2065 remainder
= quads_transferred
& 0x7f;
2066 sector_quads_remaining
= remainder
? (0x80 - remainder
) : 0;
2068 if (is_read
&& (sector_quads_remaining
== 2)) {
2070 } else if (sector_quads_remaining
) {
2072 ata_port_warn(ap
, "SATA read fixup cannot deal with "
2073 "%d quads remaining\n",
2074 sector_quads_remaining
);
2076 ata_port_warn(ap
, "SATA write fixup of %d quads "
2077 "remaining not supported\n",
2078 sector_quads_remaining
);
2085 /* This port done an interrupt */
2086 static void sata_oxnas_port_irq(struct ata_port
*ap
, int force_error
)
2088 struct ata_queued_cmd
*qc
;
2089 struct sata_oxnas_port_priv
*pd
= ap
->private_data
;
2090 void __iomem
*port_base
= pd
->port_base
;
2093 unsigned long flags
= 0;
2095 DPRINTK("ENTER port %d irqstatus %x\n", ap
->port_no
,
2096 ioread32(port_base
+ INT_STATUS
));
2098 if (ap
->qc_active
& (1 << ATA_TAG_INTERNAL
)) {
2099 qc
= ata_qc_from_tag(ap
, ATA_TAG_INTERNAL
);
2100 DPRINTK("completing non-ncq cmd\n");
2103 ata_qc_complete(qc
);
2108 qc
= ata_qc_from_tag(ap
, ap
->link
.active_tag
);
2111 /* record the port's interrupt */
2112 int_status
= ioread32(port_base
+ INT_STATUS
);
2114 /* If there's no command associated with this IRQ, ignore it. We may get
2115 * spurious interrupts when cleaning-up after a failed command, ignore
2118 /* get the status before any error cleanup */
2119 qc
->err_mask
= ac_err_mask(sata_oxnas_check_status(ap
));
2121 /* Pretend there has been a link error */
2122 qc
->err_mask
|= AC_ERR_ATA_BUS
;
2123 DPRINTK(" ####force error####\n");
2125 /* tell libata we're done */
2126 local_irq_save(flags
);
2127 sata_oxnas_irq_clear(ap
);
2128 local_irq_restore(flags
);
2129 ata_qc_complete(qc
);
2131 VPRINTK("Ignoring interrupt, can't find the command tag="
2132 "%d %08x\n", ap
->link
.active_tag
, ap
->qc_active
);
2135 /* maybe a hotplug event */
2136 if (unlikely(int_status
& INT_LINK_SERROR
)) {
2139 sata_oxnas_scr_read_port(ap
, SCR_ERROR
, &serror
);
2140 if (serror
& (SERR_DEV_XCHG
| SERR_PHYRDY_CHG
)) {
2141 ata_ehi_hotplugged(&ap
->link
.eh_info
);
2142 ata_port_freeze(ap
);
2148 * irq_handler is the interrupt handling routine registered with the system,
2151 static irqreturn_t
sata_oxnas_interrupt(int irq
, void *dev_instance
)
2153 struct ata_host
*ah
= dev_instance
;
2154 struct sata_oxnas_host_priv
*hd
= ah
->private_data
;
2155 void __iomem
*core_base
= hd
->core_base
;
2158 irqreturn_t ret
= IRQ_NONE
;
2163 /* loop until there are no more interrupts */
2164 while ((int_status
= (ioread32(core_base
+ CORE_INT_STATUS
)) &
2165 (COREINT_END
| (COREINT_END
<< 1)))) {
2167 /* clear any interrupt */
2168 iowrite32(int_status
, core_base
+ CORE_INT_CLEAR
);
2170 /* Only need workaround_bug_6320 for single disk systems as dual
2171 * disk will use uCode which prevents this read underrun problem
2173 * All single disk systems will use port 0 */
2174 for (port_no
= 0; port_no
< hd
->n_ports
; ++port_no
) {
2175 /* check the raw end of command interrupt to see if the
2177 mask
= (COREINT_END
<< port_no
);
2178 if (int_status
& mask
) {
2179 /* this port had an interrupt, clear it */
2180 iowrite32(mask
, core_base
+ CORE_INT_CLEAR
);
2182 (hd
->current_ucode
== UNKNOWN_MODE
) ?
2183 sata_oxnas_bug_6320_workaround(
2184 ah
->ports
[port_no
]):0;
2185 sata_oxnas_port_irq(ah
->ports
[port_no
],
2196 * scsi mid-layer and libata interface structures
2198 static struct scsi_host_template sata_oxnas_sht
= {
2199 ATA_NCQ_SHT("sata_oxnas"),
2200 .can_queue
= SATA_OXNAS_QUEUE_DEPTH
,
2201 .sg_tablesize
= SATA_OXNAS_MAX_PRD
,
2202 .dma_boundary
= ATA_DMA_BOUNDARY
,
2203 .unchecked_isa_dma
= 0,
2207 static struct ata_port_operations sata_oxnas_ops
= {
2208 .inherits
= &sata_port_ops
,
2209 .qc_prep
= sata_oxnas_qc_prep
,
2210 .qc_issue
= sata_oxnas_qc_issue
,
2211 .qc_fill_rtf
= sata_oxnas_qc_fill_rtf
,
2212 .qc_new
= sata_oxnas_qc_new
,
2213 .qc_free
= sata_oxnas_qc_free
,
2215 .scr_read
= sata_oxnas_scr_read
,
2216 .scr_write
= sata_oxnas_scr_write
,
2218 .freeze
= sata_oxnas_freeze
,
2219 .thaw
= sata_oxnas_thaw
,
2220 .softreset
= sata_oxnas_softreset
,
2221 /* .hardreset = sata_oxnas_hardreset, */
2222 .postreset
= sata_oxnas_postreset
,
2223 .error_handler
= sata_oxnas_error_handler
,
2224 .post_internal_cmd
= sata_oxnas_post_internal_cmd
,
2226 .port_start
= sata_oxnas_port_start
,
2227 .port_stop
= sata_oxnas_port_stop
,
2229 .host_stop
= sata_oxnas_host_stop
,
2230 /* .pmp_attach = sata_oxnas_pmp_attach, */
2231 /* .pmp_detach = sata_oxnas_pmp_detach, */
2232 .sff_check_status
= sata_oxnas_check_status
,
2233 .acquire_hw
= sata_oxnas_acquire_hw
,
2236 static const struct ata_port_info sata_oxnas_port_info
= {
2237 .flags
= SATA_OXNAS_HOST_FLAGS
,
2238 .pio_mask
= ATA_PIO4
,
2239 .udma_mask
= ATA_UDMA6
,
2240 .port_ops
= &sata_oxnas_ops
,
2243 static int sata_oxnas_probe(struct platform_device
*ofdev
)
2245 int retval
= -ENXIO
;
2247 void __iomem
*port_base
= NULL
;
2248 void __iomem
*dmactl_base
= NULL
;
2249 void __iomem
*sgdma_base
= NULL
;
2250 void __iomem
*core_base
= NULL
;
2251 void __iomem
*phy_base
= NULL
;
2252 struct reset_control
*rstc
;
2254 struct resource res
= {};
2255 struct sata_oxnas_host_priv
*host_priv
= NULL
;
2257 struct ata_host
*host
= NULL
;
2258 struct clk
*clk
= NULL
;
2260 const struct ata_port_info
*ppi
[] = { &sata_oxnas_port_info
, NULL
};
2262 of_property_read_u32(ofdev
->dev
.of_node
, "nr-ports", &n_ports
);
2263 if (n_ports
< 1 || n_ports
> SATA_OXNAS_MAX_PORTS
)
2264 goto error_exit_with_cleanup
;
2266 port_base
= of_iomap(ofdev
->dev
.of_node
, 0);
2268 goto error_exit_with_cleanup
;
2270 dmactl_base
= of_iomap(ofdev
->dev
.of_node
, 1);
2272 goto error_exit_with_cleanup
;
2274 sgdma_base
= of_iomap(ofdev
->dev
.of_node
, 2);
2276 goto error_exit_with_cleanup
;
2278 core_base
= of_iomap(ofdev
->dev
.of_node
, 3);
2280 goto error_exit_with_cleanup
;
2282 phy_base
= of_iomap(ofdev
->dev
.of_node
, 4);
2284 goto error_exit_with_cleanup
;
2286 host_priv
= devm_kzalloc(&ofdev
->dev
,
2287 sizeof(struct sata_oxnas_host_priv
),
2290 goto error_exit_with_cleanup
;
2292 host_priv
->port_base
= port_base
;
2293 host_priv
->dmactl_base
= dmactl_base
;
2294 host_priv
->sgdma_base
= sgdma_base
;
2295 host_priv
->core_base
= core_base
;
2296 host_priv
->phy_base
= phy_base
;
2297 host_priv
->n_ports
= n_ports
;
2298 host_priv
->current_ucode
= UNKNOWN_MODE
;
2300 if (!of_address_to_resource(ofdev
->dev
.of_node
, 5, &res
)) {
2301 host_priv
->dma_base
= res
.start
;
2302 host_priv
->dma_size
= resource_size(&res
);
2305 irq
= irq_of_parse_and_map(ofdev
->dev
.of_node
, 0);
2307 dev_err(&ofdev
->dev
, "invalid irq from platform\n");
2308 goto error_exit_with_cleanup
;
2310 host_priv
->irq
= irq
;
2312 clk
= of_clk_get(ofdev
->dev
.of_node
, 0);
2314 retval
= PTR_ERR(clk
);
2316 goto error_exit_with_cleanup
;
2318 host_priv
->clk
= clk
;
2320 rstc
= devm_reset_control_get(&ofdev
->dev
, "sata");
2322 retval
= PTR_ERR(rstc
);
2323 goto error_exit_with_cleanup
;
2325 host_priv
->rst_sata
= rstc
;
2327 rstc
= devm_reset_control_get(&ofdev
->dev
, "link");
2329 retval
= PTR_ERR(rstc
);
2330 goto error_exit_with_cleanup
;
2332 host_priv
->rst_link
= rstc
;
2334 rstc
= devm_reset_control_get(&ofdev
->dev
, "phy");
2336 retval
= PTR_ERR(rstc
);
2337 goto error_exit_with_cleanup
;
2339 host_priv
->rst_phy
= rstc
;
2341 /* allocate host structure */
2342 host
= ata_host_alloc_pinfo(&ofdev
->dev
, ppi
, n_ports
);
2346 goto error_exit_with_cleanup
;
2348 host
->private_data
= host_priv
;
2349 host
->iomap
= port_base
;
2351 /* initialize core locking and queues */
2352 init_waitqueue_head(&host_priv
->fast_wait_queue
);
2353 init_waitqueue_head(&host_priv
->scsi_wait_queue
);
2354 spin_lock_init(&host_priv
->phy_lock
);
2355 spin_lock_init(&host_priv
->core_lock
);
2356 host_priv
->core_locked
= 0;
2357 host_priv
->reentrant_port_no
= -1;
2358 host_priv
->hw_lock_count
= 0;
2359 host_priv
->direct_lock_count
= 0;
2360 host_priv
->locker_uid
= 0;
2361 host_priv
->current_locker_type
= SATA_UNLOCKED
;
2362 host_priv
->isr_arg
= NULL
;
2363 host_priv
->isr_callback
= NULL
;
2365 /* initialize host controller */
2366 retval
= sata_oxnas_init_controller(host
);
2368 goto error_exit_with_cleanup
;
2371 * Now, register with libATA core, this will also initiate the
2372 * device discovery process, invoking our port_start() handler &
2373 * error_handler() to execute a dummy softreset EH session
2375 ata_host_activate(host
, irq
, sata_oxnas_interrupt
, SATA_OXNAS_IRQ_FLAG
,
2380 error_exit_with_cleanup
:
2382 irq_dispose_mapping(host_priv
->irq
);
2386 ata_host_detach(host
);
2390 iounmap(sgdma_base
);
2399 static int sata_oxnas_remove(struct platform_device
*ofdev
)
2401 struct ata_host
*host
= dev_get_drvdata(&ofdev
->dev
);
2402 struct sata_oxnas_host_priv
*host_priv
= host
->private_data
;
2404 ata_host_detach(host
);
2406 irq_dispose_mapping(host_priv
->irq
);
2407 iounmap(host_priv
->port_base
);
2408 iounmap(host_priv
->sgdma_base
);
2409 iounmap(host_priv
->core_base
);
2411 /* reset Controller, Link and PHY */
2412 reset_control_assert(host_priv
->rst_sata
);
2413 reset_control_assert(host_priv
->rst_link
);
2414 reset_control_assert(host_priv
->rst_phy
);
2416 /* Disable the clock to the SATA block */
2417 clk_disable_unprepare(host_priv
->clk
);
2418 clk_put(host_priv
->clk
);
2424 static int sata_oxnas_suspend(struct platform_device
*op
, pm_message_t state
)
2426 struct ata_host
*host
= dev_get_drvdata(&op
->dev
);
2428 return ata_host_suspend(host
, state
);
2431 static int sata_oxnas_resume(struct platform_device
*op
)
2433 struct ata_host
*host
= dev_get_drvdata(&op
->dev
);
2436 ret
= sata_oxnas_init_controller(host
);
2438 dev_err(&op
->dev
, "Error initializing hardware\n");
2441 ata_host_resume(host
);
2448 static struct of_device_id oxnas_sata_match
[] = {
2450 .compatible
= "plxtech,nas782x-sata",
2455 MODULE_DEVICE_TABLE(of
, oxnas_sata_match
);
2457 static struct platform_driver oxnas_sata_driver
= {
2459 .name
= "oxnas-sata",
2460 .owner
= THIS_MODULE
,
2461 .of_match_table
= oxnas_sata_match
,
2463 .probe
= sata_oxnas_probe
,
2464 .remove
= sata_oxnas_remove
,
2466 .suspend
= sata_oxnas_suspend
,
2467 .resume
= sata_oxnas_resume
,
2471 module_platform_driver(oxnas_sata_driver
);
2473 MODULE_LICENSE("GPL");
2474 MODULE_VERSION("1.0");
2475 MODULE_AUTHOR("Oxford Semiconductor Ltd.");
2476 MODULE_DESCRIPTION("low-level driver for Oxford 934 SATA core");