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oxnas: sata_oxnas: refactoring phase 1
[openwrt/staging/dedeckeh.git] / target / linux / oxnas / files / drivers / ata / sata_oxnas.c
1 /*
2 * sata_oxnas
3 * A driver to interface the 934 based sata core present in the ox820
4 * with libata and scsi
5 * based on sata_oxnas driver by Ma Haijun <mahaijuns@gmail.com>
6 * based on ox820 sata code by:
7 * Copyright (c) 2007 Oxford Semiconductor Ltd.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2, or (at your option)
12 * any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 */
19
20 #include <linux/ata.h>
21 #include <linux/libata.h>
22 #include <linux/of_platform.h>
23 #include <linux/delay.h>
24 #include <linux/module.h>
25 #include <linux/slab.h>
26 #include <linux/spinlock.h>
27 #include <linux/of_address.h>
28 #include <linux/of_irq.h>
29 #include <linux/clk.h>
30 #include <linux/reset.h>
31
32 #include <mach/utils.h>
33
34 /* sgdma request structure */
35 struct sgdma_request {
36 volatile u32 qualifier;
37 volatile u32 control;
38 dma_addr_t src_pa;
39 dma_addr_t dst_pa;
40 } __packed __aligned(4);
41
42
43 /* Controller information */
44 enum {
45 SATA_OXNAS_MAX_PRD = 254,
46 SATA_OXNAS_DMA_SIZE = SATA_OXNAS_MAX_PRD *
47 sizeof(struct ata_bmdma_prd) +
48 sizeof(struct sgdma_request),
49 SATA_OXNAS_MAX_PORTS = 2,
50 /** The different Oxsemi SATA core version numbers */
51 SATA_OXNAS_CORE_VERSION = 0x1f3,
52 SATA_OXNAS_IRQ_FLAG = IRQF_SHARED,
53 SATA_OXNAS_HOST_FLAGS = (ATA_FLAG_SATA | ATA_FLAG_PIO_DMA |
54 ATA_FLAG_NO_ATAPI /*| ATA_FLAG_NCQ*/),
55 SATA_OXNAS_QUEUE_DEPTH = 32,
56
57 SATA_OXNAS_DMA_BOUNDARY = 0xFFFFFFFF,
58 };
59
60
61 /*
62 * SATA Port Registers
63 */
64 enum {
65 /** sata host port register offsets */
66 ORB1 = 0x00,
67 ORB2 = 0x04,
68 ORB3 = 0x08,
69 ORB4 = 0x0C,
70 ORB5 = 0x10,
71 MASTER_STATUS = 0x10,
72 FIS_CTRL = 0x18,
73 FIS_DATA = 0x1C,
74 INT_STATUS = 0x30,
75 INT_CLEAR = 0x30,
76 INT_ENABLE = 0x34,
77 INT_DISABLE = 0x38,
78 VERSION = 0x3C,
79 SATA_CONTROL = 0x5C,
80 SATA_COMMAND = 0x60,
81 HID_FEATURES = 0x64,
82 PORT_CONTROL = 0x68,
83 DRIVE_CONTROL = 0x6C,
84 /** These registers allow access to the link layer registers
85 that reside in a different clock domain to the processor bus */
86 LINK_DATA = 0x70,
87 LINK_RD_ADDR = 0x74,
88 LINK_WR_ADDR = 0x78,
89 LINK_CONTROL = 0x7C,
90 /* window control */
91 WIN1LO = 0x80,
92 WIN1HI = 0x84,
93 WIN2LO = 0x88,
94 WIN2HI = 0x8C,
95 WIN0_CONTROL = 0x90,
96 };
97
98 /** sata port register bits */
99 enum{
100 /**
101 * commands to issue in the master status to tell it to move shadow ,
102 * registers to the actual device ,
103 */
104 SATA_OPCODE_MASK = 0x00000007,
105 CMD_WRITE_TO_ORB_REGS_NO_COMMAND = 0x4,
106 CMD_WRITE_TO_ORB_REGS = 0x2,
107 CMD_SYNC_ESCAPE = 0x7,
108 CMD_CORE_BUSY = (1 << 7),
109 CMD_DRIVE_SELECT_SHIFT = 12,
110 CMD_DRIVE_SELECT_MASK = (0xf << CMD_DRIVE_SELECT_SHIFT),
111
112 /** interrupt bits */
113 INT_END_OF_CMD = 1 << 0,
114 INT_LINK_SERROR = 1 << 1,
115 INT_ERROR = 1 << 2,
116 INT_LINK_IRQ = 1 << 3,
117 INT_REG_ACCESS_ERR = 1 << 7,
118 INT_BIST_FIS = 1 << 11,
119 INT_MASKABLE = INT_END_OF_CMD |
120 INT_LINK_SERROR |
121 INT_ERROR |
122 INT_LINK_IRQ |
123 INT_REG_ACCESS_ERR |
124 INT_BIST_FIS,
125 INT_WANT = INT_END_OF_CMD |
126 INT_LINK_SERROR |
127 INT_REG_ACCESS_ERR |
128 INT_ERROR,
129 INT_ERRORS = INT_LINK_SERROR |
130 INT_REG_ACCESS_ERR |
131 INT_ERROR,
132
133 /** raw interrupt bits, unmaskable, but do not generate interrupts */
134 RAW_END_OF_CMD = INT_END_OF_CMD << 16,
135 RAW_LINK_SERROR = INT_LINK_SERROR << 16,
136 RAW_ERROR = INT_ERROR << 16,
137 RAW_LINK_IRQ = INT_LINK_IRQ << 16,
138 RAW_REG_ACCESS_ERR = INT_REG_ACCESS_ERR << 16,
139 RAW_BIST_FIS = INT_BIST_FIS << 16,
140 RAW_WANT = INT_WANT << 16,
141 RAW_ERRORS = INT_ERRORS << 16,
142
143 /**
144 * variables to write to the device control register to set the current
145 * device, ie. master or slave.
146 */
147 DR_CON_48 = 2,
148 DR_CON_28 = 0,
149
150 SATA_CTL_ERR_MASK = 0x00000016,
151
152 };
153
154 /* ATA SGDMA register offsets */
155 enum {
156 SGDMA_CONTROL = 0x0,
157 SGDMA_STATUS = 0x4,
158 SGDMA_REQUESTPTR = 0x8,
159 SGDMA_RESETS = 0xC,
160 SGDMA_CORESIZE = 0x10,
161 };
162
163 /* DMA controller register offsets */
164 enum {
165 DMA_CONTROL = 0x0,
166 DMA_CORESIZE = 0x20,
167
168 DMA_CONTROL_RESET = (1 << 12),
169 };
170
171 enum {
172 /* see DMA core docs for the values. Out means from memory (bus A) out
173 * to disk (bus B) */
174 SGDMA_REQCTL0OUT = 0x0497c03d,
175 /* burst mode disabled when no micro code used */
176 SGDMA_REQCTL0IN = 0x0493a3c1,
177 SGDMA_REQCTL1OUT = 0x0497c07d,
178 SGDMA_REQCTL1IN = 0x0497a3c5,
179 SGDMA_CONTROL_NOGO = 0x3e,
180 SGDMA_CONTROL_GO = SGDMA_CONTROL_NOGO | 1,
181 SGDMA_ERRORMASK = 0x3f,
182 SGDMA_BUSY = 0x80,
183
184 SGDMA_RESETS_CTRL = 1 << 0,
185 SGDMA_RESETS_ARBT = 1 << 1,
186 SGDMA_RESETS_AHB = 1 << 2,
187 SGDMA_RESETS_ALL = SGDMA_RESETS_CTRL |
188 SGDMA_RESETS_ARBT |
189 SGDMA_RESETS_AHB,
190
191 /* Final EOTs */
192 SGDMA_REQQUAL = 0x00220001,
193
194 };
195
196 /** SATA core register offsets */
197 enum {
198 DM_DBG1 = 0x000,
199 RAID_SET = 0x004,
200 DM_DBG2 = 0x008,
201 DATACOUNT_PORT0 = 0x010,
202 DATACOUNT_PORT1 = 0x014,
203 CORE_INT_STATUS = 0x030,
204 CORE_INT_CLEAR = 0x030,
205 CORE_INT_ENABLE = 0x034,
206 CORE_INT_DISABLE = 0x038,
207 CORE_REBUILD_ENABLE = 0x050,
208 CORE_FAILED_PORT_R = 0x054,
209 DEVICE_CONTROL = 0x068,
210 EXCESS = 0x06C,
211 RAID_SIZE_LOW = 0x070,
212 RAID_SIZE_HIGH = 0x074,
213 PORT_ERROR_MASK = 0x078,
214 IDLE_STATUS = 0x07C,
215 RAID_CONTROL = 0x090,
216 DATA_PLANE_CTRL = 0x0AC,
217 CORE_DATAPLANE_STAT = 0x0b8,
218 PROC_PC = 0x100,
219 CONFIG_IN = 0x3d8,
220 PROC_START = 0x3f0,
221 PROC_RESET = 0x3f4,
222 UCODE_STORE = 0x1000,
223 RAID_WP_BOT_LOW = 0x1FF0,
224 RAID_WP_BOT_HIGH = 0x1FF4,
225 RAID_WP_TOP_LOW = 0x1FF8,
226 RAID_WP_TOP_HIGH = 0x1FFC,
227 DATA_MUX_RAM0 = 0x8000,
228 DATA_MUX_RAM1 = 0xA000,
229 PORT_SIZE = 0x10000,
230 };
231
232 enum {
233 /* Sata core debug1 register bits */
234 CORE_PORT0_DATA_DIR_BIT = 20,
235 CORE_PORT1_DATA_DIR_BIT = 21,
236 CORE_PORT0_DATA_DIR = 1 << CORE_PORT0_DATA_DIR_BIT,
237 CORE_PORT1_DATA_DIR = 1 << CORE_PORT1_DATA_DIR_BIT,
238
239 /** sata core control register bits */
240 SCTL_CLR_ERR = 0x00003016,
241 RAID_CLR_ERR = 0x0000011e,
242
243 /* Interrupts direct from the ports */
244 NORMAL_INTS_WANTED = 0x00000303,
245
246 /* shift these left by port number */
247 COREINT_HOST = 0x00000001,
248 COREINT_END = 0x00000100,
249 CORERAW_HOST = COREINT_HOST << 16,
250 CORERAW_END = COREINT_END << 16,
251
252 /* Interrupts from the RAID controller only */
253 RAID_INTS_WANTED = 0x00008300,
254
255 /* The bits in the IDLE_STATUS that, when set indicate an idle core */
256 IDLE_CORES = (1 << 18) | (1 << 19),
257
258 /* Data plane control error-mask mask and bit, these bit in the data
259 * plane control mask out errors from the ports that prevent the SGDMA
260 * care from sending an interrupt */
261 DPC_ERROR_MASK = 0x00000300,
262 DPC_ERROR_MASK_BIT = 0x00000100,
263 /* enable jbod micro-code */
264 DPC_JBOD_UCODE = 1 << 0,
265 DPC_FIS_SWCH = 1 << 1,
266
267 /** Device Control register bits */
268 DEVICE_CONTROL_DMABT = 1 << 4,
269 DEVICE_CONTROL_ABORT = 1 << 2,
270 DEVICE_CONTROL_PAD = 1 << 3,
271 DEVICE_CONTROL_PADPAT = 1 << 16,
272 DEVICE_CONTROL_PRTRST = 1 << 8,
273 DEVICE_CONTROL_RAMRST = 1 << 12,
274 DEVICE_CONTROL_ATA_ERR_OVERRIDE = 1 << 28,
275
276 /** oxsemi HW raid modes */
277 OXNASSATA_NOTRAID = 0,
278 OXNASSATA_RAID0 = 1,
279 OXNASSATA_RAID1 = 2,
280 /** OX820 specific HW-RAID register values */
281 RAID_TWODISKS = 3,
282 UNKNOWN_MODE = ~0,
283
284 CONFIG_IN_RESUME = 2,
285 };
286
287 /* SATA PHY Registers */
288 enum {
289 PHY_STAT = 0x00,
290 PHY_DATA = 0x04,
291 };
292
293 enum {
294 STAT_READ_VALID = (1 << 21),
295 STAT_CR_ACK = (1 << 20),
296 STAT_CR_READ = (1 << 19),
297 STAT_CR_WRITE = (1 << 18),
298 STAT_CAP_DATA = (1 << 17),
299 STAT_CAP_ADDR = (1 << 16),
300
301 STAT_ACK_ANY = STAT_CR_ACK |
302 STAT_CR_READ |
303 STAT_CR_WRITE |
304 STAT_CAP_DATA |
305 STAT_CAP_ADDR,
306
307 CR_READ_ENABLE = (1 << 16),
308 CR_WRITE_ENABLE = (1 << 17),
309 CR_CAP_DATA = (1 << 18),
310 };
311
312 enum {
313 /* Link layer registers */
314 SERROR_IRQ_MASK = 5,
315 };
316
317 enum {
318 OXNAS_SATA_SOFTRESET = 1,
319 OXNAS_SATA_REINIT = 2,
320 };
321
322 enum {
323 OXNAS_SATA_UCODE_RAID0,
324 OXNAS_SATA_UCODE_RAID1,
325 OXNAS_SATA_UCODE_JBOD,
326 OXNAS_SATA_UCODE_NONE,
327 };
328
329 enum {
330 SATA_UNLOCKED,
331 SATA_WRITER,
332 SATA_READER,
333 SATA_REBUILD,
334 SATA_HWRAID,
335 SATA_SCSI_STACK
336 };
337
338 typedef irqreturn_t (*oxnas_sata_isr_callback_t)(int, unsigned long, int);
339
340 struct sata_oxnas_host_priv {
341 void __iomem *port_base;
342 void __iomem *dmactl_base;
343 void __iomem *sgdma_base;
344 void __iomem *core_base;
345 void __iomem *phy_base;
346 dma_addr_t dma_base;
347 void __iomem *dma_base_va;
348 size_t dma_size;
349 int irq;
350 int n_ports;
351 int current_ucode;
352 u32 port_frozen;
353 u32 port_in_eh;
354 struct clk *clk;
355 struct reset_control *rst_sata;
356 struct reset_control *rst_link;
357 struct reset_control *rst_phy;
358 spinlock_t phy_lock;
359 spinlock_t core_lock;
360 int core_locked;
361 int reentrant_port_no;
362 int hw_lock_count;
363 int direct_lock_count;
364 void *locker_uid;
365 int current_locker_type;
366 int scsi_nonblocking_attempts;
367 oxnas_sata_isr_callback_t isr_callback;
368 void *isr_arg;
369 wait_queue_head_t fast_wait_queue;
370 wait_queue_head_t scsi_wait_queue;
371 };
372
373
374 struct sata_oxnas_port_priv {
375 void __iomem *port_base;
376 void __iomem *dmactl_base;
377 void __iomem *sgdma_base;
378 void __iomem *core_base;
379 struct sgdma_request *sgdma_request;
380 dma_addr_t sgdma_request_pa;
381 };
382
383 static u8 sata_oxnas_check_status(struct ata_port *ap);
384 static int sata_oxnas_cleanup(struct ata_host *ah);
385 static void sata_oxnas_tf_load(struct ata_port *ap,
386 const struct ata_taskfile *tf);
387 static void sata_oxnas_irq_on(struct ata_port *ap);
388 static void sata_oxnas_post_reset_init(struct ata_port *ap);
389
390 static int sata_oxnas_acquire_hw(struct ata_port *ap, int may_sleep,
391 int timeout_jiffies);
392 static void sata_oxnas_release_hw(struct ata_port *ap);
393
394 static const void *HW_LOCKER_UID = (void*)0xdeadbeef;
395
396 /***************************************************************************
397 * ASIC access
398 ***************************************************************************/
399 static void wait_cr_ack(void __iomem *phy_base)
400 {
401 while ((ioread32(phy_base + PHY_STAT) >> 16) & 0x1f)
402 ; /* wait for an ack bit to be set */
403 }
404
405 static u16 read_cr(void __iomem *phy_base, u16 address)
406 {
407 iowrite32((u32)address, phy_base + PHY_STAT);
408 wait_cr_ack(phy_base);
409 iowrite32(CR_READ_ENABLE, phy_base + PHY_DATA);
410 wait_cr_ack(phy_base);
411 return (u16)ioread32(phy_base + PHY_STAT);
412 }
413
414 static void write_cr(void __iomem *phy_base, u16 data, u16 address)
415 {
416 iowrite32((u32)address, phy_base + PHY_STAT);
417 wait_cr_ack(phy_base);
418 iowrite32((data | CR_CAP_DATA), phy_base + PHY_DATA);
419 wait_cr_ack(phy_base);
420 iowrite32(CR_WRITE_ENABLE, phy_base + PHY_DATA);
421 wait_cr_ack(phy_base);
422 }
423
424 #define PH_GAIN 2
425 #define FR_GAIN 3
426 #define PH_GAIN_OFFSET 6
427 #define FR_GAIN_OFFSET 8
428 #define PH_GAIN_MASK (0x3 << PH_GAIN_OFFSET)
429 #define FR_GAIN_MASK (0x3 << FR_GAIN_OFFSET)
430 #define USE_INT_SETTING (1<<5)
431
432 void workaround5458(struct ata_host *ah)
433 {
434 struct sata_oxnas_host_priv *hd = ah->private_data;
435 void __iomem *phy_base = hd->phy_base;
436 u16 rx_control;
437 unsigned i;
438
439 for (i = 0; i < 2; i++) {
440 rx_control = read_cr(phy_base, 0x201d + (i << 8));
441 rx_control &= ~(PH_GAIN_MASK | FR_GAIN_MASK);
442 rx_control |= PH_GAIN << PH_GAIN_OFFSET;
443 rx_control |= (FR_GAIN << FR_GAIN_OFFSET) | USE_INT_SETTING;
444 write_cr(phy_base, rx_control, 0x201d+(i<<8));
445 }
446 }
447
448 /**
449 * allows access to the link layer registers
450 * @param link_reg the link layer register to access (oxsemi indexing ie
451 * 00 = static config, 04 = phy ctrl)
452 */
453 void sata_oxnas_link_write(struct ata_port *ap, unsigned int link_reg, u32 val)
454 {
455 struct sata_oxnas_port_priv *pd = ap->private_data;
456 struct sata_oxnas_host_priv *hd = ap->host->private_data;
457 void __iomem *port_base = pd->port_base;
458 u32 patience;
459 unsigned long flags;
460
461 DPRINTK("P%d [0x%02x]->0x%08x\n", ap->port_no, link_reg, val);
462
463 spin_lock_irqsave(&hd->phy_lock, flags);
464 iowrite32(val, port_base + LINK_DATA);
465
466 /* accessed twice as a work around for a bug in the SATA abp bridge
467 * hardware (bug 6828) */
468 iowrite32(link_reg , port_base + LINK_WR_ADDR);
469 ioread32(port_base + LINK_WR_ADDR);
470
471 for (patience = 0x100000; patience > 0; --patience) {
472 if (ioread32(port_base + LINK_CONTROL) & 0x00000001)
473 break;
474 }
475 spin_unlock_irqrestore(&hd->phy_lock, flags);
476 }
477
478 static int sata_oxnas_scr_write_port(struct ata_port *ap, unsigned int sc_reg,
479 u32 val)
480 {
481 sata_oxnas_link_write(ap, 0x20 + (sc_reg * 4), val);
482 return 0;
483 }
484
485 static int sata_oxnas_scr_write(struct ata_link *link, unsigned int sc_reg,
486 u32 val)
487 {
488 return sata_oxnas_scr_write_port(link->ap, sc_reg, val);
489 }
490
491 u32 sata_oxnas_link_read(struct ata_port *ap, unsigned int link_reg)
492 {
493 struct sata_oxnas_port_priv *pd = ap->private_data;
494 struct sata_oxnas_host_priv *hd = ap->host->private_data;
495 void __iomem *port_base = pd->port_base;
496 u32 result;
497 u32 patience;
498 unsigned long flags;
499
500 spin_lock_irqsave(&hd->phy_lock, flags);
501 /* accessed twice as a work around for a bug in the SATA abp bridge
502 * hardware (bug 6828) */
503 iowrite32(link_reg, port_base + LINK_RD_ADDR);
504 ioread32(port_base + LINK_RD_ADDR);
505
506 for (patience = 0x100000; patience > 0; --patience) {
507 if (ioread32(port_base + LINK_CONTROL) & 0x00000001)
508 break;
509 }
510 if (patience == 0)
511 DPRINTK("link read timed out for port %d\n", ap->port_no);
512
513 result = ioread32(port_base + LINK_DATA);
514 spin_unlock_irqrestore(&hd->phy_lock, flags);
515
516 return result;
517 }
518
519 static int sata_oxnas_scr_read_port(struct ata_port *ap, unsigned int sc_reg,
520 u32 *val)
521 {
522 *val = sata_oxnas_link_read(ap, 0x20 + (sc_reg*4));
523 return 0;
524 }
525
526 static int sata_oxnas_scr_read(struct ata_link *link,
527 unsigned int sc_reg, u32 *val)
528 {
529 return sata_oxnas_scr_read_port(link->ap, sc_reg, val);
530 }
531
532 /**
533 * sata_oxnas_irq_clear is called during probe just before the interrupt handler is
534 * registered, to be sure hardware is quiet. It clears and masks interrupt bits
535 * in the SATA core.
536 *
537 * @param ap hardware with the registers in
538 */
539 static void sata_oxnas_irq_clear(struct ata_port *ap)
540 {
541 struct sata_oxnas_port_priv *port_priv = ap->private_data;
542
543 /* clear pending interrupts */
544 iowrite32(~0, port_priv->port_base + INT_CLEAR);
545 iowrite32(COREINT_END, port_priv->core_base + CORE_INT_CLEAR);
546 }
547
548 /**
549 * qc_issue is used to make a command active, once the hardware and S/G tables
550 * have been prepared. IDE BMDMA drivers use the helper function
551 * ata_qc_issue_prot() for taskfile protocol-based dispatch. More advanced
552 * drivers roll their own ->qc_issue implementation, using this as the
553 * "issue new ATA command to hardware" hook.
554 * @param qc the queued command to issue
555 */
556 static unsigned int sata_oxnas_qc_issue(struct ata_queued_cmd *qc)
557 {
558 struct sata_oxnas_port_priv *pd = qc->ap->private_data;
559 struct sata_oxnas_host_priv *hd = qc->ap->host->private_data;
560
561 void __iomem *port_base = pd->port_base;
562 void __iomem *core_base = pd->core_base;
563 int port_no = qc->ap->port_no;
564 int no_microcode = ( hd->current_ucode == UNKNOWN_MODE );
565 u32 reg;
566
567 /* check the core is idle */
568 if (ioread32(port_base + SATA_COMMAND) & CMD_CORE_BUSY) {
569 int count = 0;
570
571 DPRINTK("core busy for a command on port %d\n",
572 qc->ap->port_no);
573 do {
574 mdelay(1);
575 if (++count > 100) {
576 DPRINTK("core busy for a command on port %d\n",
577 qc->ap->port_no);
578 /* CrazyDumpDebug(); */
579 sata_oxnas_cleanup(qc->ap->host);
580 }
581 } while (ioread32(port_base + SATA_COMMAND) & CMD_CORE_BUSY);
582 }
583
584 /* enable passing of error signals to DMA sub-core by clearing the
585 * appropriate bit */
586 reg = ioread32(core_base + DATA_PLANE_CTRL);
587 if(no_microcode)
588 reg |= (DPC_ERROR_MASK_BIT | (DPC_ERROR_MASK_BIT << 1));
589 reg &= ~(DPC_ERROR_MASK_BIT << port_no);
590 iowrite32(reg, core_base + DATA_PLANE_CTRL);
591
592 /* Disable all interrupts for ports and RAID controller */
593 iowrite32(~0, port_base + INT_DISABLE);
594
595 /* Disable all interrupts for core */
596 iowrite32(~0, core_base + CORE_INT_DISABLE);
597 wmb();
598
599 /* Load the command settings into the orb registers */
600 sata_oxnas_tf_load(qc->ap, &qc->tf);
601
602 /* both pio and dma commands use dma */
603 if (ata_is_dma(qc->tf.protocol) || ata_is_pio(qc->tf.protocol)) {
604 /* Start the DMA */
605 iowrite32(SGDMA_CONTROL_GO, pd->sgdma_base + SGDMA_CONTROL);
606 wmb();
607 }
608
609 /* enable End of command interrupt */
610 iowrite32(INT_WANT, port_base + INT_ENABLE);
611 iowrite32(COREINT_END, core_base + CORE_INT_ENABLE);
612 wmb();
613
614 /* Start the command */
615 reg = ioread32(port_base + SATA_COMMAND);
616 reg &= ~SATA_OPCODE_MASK;
617 reg |= CMD_WRITE_TO_ORB_REGS;
618 iowrite32(reg , port_base + SATA_COMMAND);
619 wmb();
620
621 return 0;
622 }
623
624 /**
625 * Will schedule the libATA error handler on the premise that there has
626 * been a hotplug event on the port specified
627 */
628 void sata_oxnas_checkforhotplug(struct ata_port *ap)
629 {
630 DPRINTK("ENTER\n");
631
632 ata_ehi_hotplugged(&ap->link.eh_info);
633 ata_port_freeze(ap);
634 }
635
636
637 /**************************************************************************/
638 /* Locking */
639 /**************************************************************************/
640 /**
641 * The underlying function that controls access to the sata core
642 *
643 * @return non-zero indicates that you have acquired exclusive access to the
644 * sata core.
645 */
646 static int __acquire_sata_core(
647 struct ata_host *ah,
648 int port_no,
649 oxnas_sata_isr_callback_t callback,
650 void *arg,
651 int may_sleep,
652 int timeout_jiffies,
653 int hw_access,
654 void *uid,
655 int locker_type)
656 {
657 unsigned long end = jiffies + timeout_jiffies;
658 int acquired = 0;
659 unsigned long flags;
660 int timed_out = 0;
661 struct sata_oxnas_host_priv *hd;
662
663 DEFINE_WAIT(wait);
664
665 if (!ah)
666 return acquired;
667
668 hd = ah->private_data;
669
670 spin_lock_irqsave(&hd->core_lock, flags);
671
672 DPRINTK("Entered uid %p, port %d, h/w count %d, d count %d, callback %p, "
673 "hw_access %d, core_locked %d, reentrant_port_no %d, isr_callback %p\n",
674 uid, port_no, hd->hw_lock_count, hd->direct_lock_count, callback, hw_access,
675 hd->core_locked, hd->reentrant_port_no, hd->isr_callback);
676
677 while (!timed_out) {
678 if (hd->core_locked || (!hw_access && hd->scsi_nonblocking_attempts)) {
679 /* Can only allow access if from SCSI/SATA stack and if
680 reentrant access is allowed and this access is to the same
681 port for which the lock is current held */
682 if (hw_access && (port_no == hd->reentrant_port_no)) {
683 BUG_ON(!hd->hw_lock_count);
684 ++(hd->hw_lock_count);
685
686 DPRINTK("Allow SCSI/SATA re-entrant access to uid %p port %d\n", uid, port_no);
687 acquired = 1;
688 break;
689 } else if (!hw_access) {
690 if ((locker_type == SATA_READER) && (hd->current_locker_type == SATA_READER)) {
691 WARN(1,
692 "Already locked by reader, uid %p, locker_uid %p, port %d, "
693 "h/w count %d, d count %d, hw_access %d\n", uid, hd->locker_uid,
694 port_no, hd->hw_lock_count, hd->direct_lock_count, hw_access);
695 goto check_uid;
696 }
697
698 if ((locker_type != SATA_READER) && (locker_type != SATA_WRITER)) {
699 goto wait_for_lock;
700 }
701
702 check_uid:
703 WARN(uid == hd->locker_uid, "Attempt to lock by locker type %d "
704 "uid %p, already locked by locker type %d with "
705 "locker_uid %p, port %d, h/w count %d, d count %d, "
706 "hw_access %d\n", locker_type, uid, hd->current_locker_type,
707 hd->locker_uid, port_no, hd->hw_lock_count, hd->direct_lock_count, hw_access);
708 }
709 } else {
710 WARN(hd->hw_lock_count || hd->direct_lock_count, "Core unlocked but counts "
711 "non-zero: uid %p, locker_uid %p, port %d, h/w count %d, "
712 "d count %d, hw_access %d\n", uid, hd->locker_uid, port_no,
713 hd->hw_lock_count, hd->direct_lock_count, hw_access);
714
715 BUG_ON(hd->current_locker_type != SATA_UNLOCKED);
716
717 WARN(hd->locker_uid, "Attempt to lock uid %p when locker_uid %p is "
718 "non-zero, port %d, h/w count %d, d count %d, hw_access %d\n",
719 uid, hd->locker_uid, port_no, hd->hw_lock_count, hd->direct_lock_count,
720 hw_access);
721
722 if (!hw_access) {
723 /* Direct access attempting to acquire non-contented lock */
724 BUG_ON(!callback); // Must have callback for direct access
725 BUG_ON(hd->reentrant_port_no != -1); // Sanity check lock state
726
727 hd->isr_callback = callback;
728 hd->isr_arg = arg;
729 ++(hd->direct_lock_count);
730
731 hd->current_locker_type = locker_type;
732 } else {
733 /* SCSI/SATA attempting to acquire non-contented lock */
734 BUG_ON(callback); // No callbacks for SCSI/SATA access
735 BUG_ON(arg); // No callback args for SCSI/SATA access
736
737 BUG_ON(hd->isr_callback); // Sanity check lock state
738 BUG_ON(hd->isr_arg); // Sanity check lock state
739
740 ++(hd->hw_lock_count);
741 hd->reentrant_port_no = port_no;
742
743 hd->current_locker_type = SATA_SCSI_STACK;
744 }
745
746 hd->core_locked = 1;
747 hd->locker_uid = uid;
748 acquired = 1;
749 break;
750 }
751
752 wait_for_lock:
753 if (!may_sleep) {
754 DPRINTK("Denying for uid %p locker_type %d, hw_access %d, port %d, "
755 "current_locker_type %d as cannot sleep\n", uid, locker_type,
756 hw_access, port_no, hd->current_locker_type);
757
758 if (hw_access) {
759 ++(hd->scsi_nonblocking_attempts);
760 }
761 break;
762 }
763
764 // Core is locked and we're allowed to sleep, so wait to be awoken when
765 // the core is unlocked
766 for (;;) {
767 prepare_to_wait(hw_access ? &hd->scsi_wait_queue : &hd->fast_wait_queue,
768 &wait, TASK_UNINTERRUPTIBLE);
769 if (!hd->core_locked && !(!hw_access && hd->scsi_nonblocking_attempts)) {
770 // We're going to use variables that will have been changed by
771 // the waker prior to clearing core_locked so we need to ensure
772 // we see changes to all those variables
773 smp_rmb();
774 break;
775 }
776 if (time_after(jiffies, end)) {
777 printk("__acquire_sata_core() uid %p failing for port %d timed out, "
778 "locker_uid %p, h/w count %d, d count %d, callback %p, hw_access %d, "
779 "core_locked %d, reentrant_port_no %d, isr_callback %p, "
780 "isr_arg %p\n", uid, port_no, hd->locker_uid,
781 hd->hw_lock_count, hd->direct_lock_count, callback, hw_access,
782 hd->core_locked, hd->reentrant_port_no, hd->isr_callback,
783 hd->isr_arg);
784 timed_out = 1;
785 break;
786 }
787 spin_unlock_irqrestore(&hd->core_lock, flags);
788 if (!schedule_timeout(4*HZ)) {
789 printk(KERN_INFO "__acquire_sata_core() uid %p, locker_uid %p, "
790 "timed-out of schedule(), checking overall timeout\n",
791 uid, hd->locker_uid);
792 }
793 spin_lock_irqsave(&hd->core_lock, flags);
794 }
795 finish_wait(hw_access ? &hd->scsi_wait_queue : &hd->fast_wait_queue, &wait);
796 }
797
798 if (hw_access && acquired) {
799 if (hd->scsi_nonblocking_attempts) {
800 hd->scsi_nonblocking_attempts = 0;
801 }
802
803 // Wake any other SCSI/SATA waiters so they can get reentrant access to
804 // the same port if appropriate. This is because if the SATA core is
805 // locked by fast access, or SCSI/SATA access to other port, then can
806 // have >1 SCSI/SATA waiters on the wait list so want to give reentrant
807 // accessors a chance to get access ASAP
808 if (!list_empty(&hd->scsi_wait_queue.task_list)) {
809 wake_up(&hd->scsi_wait_queue);
810 }
811 }
812
813 DPRINTK("Leaving uid %p with acquired = %d, port %d, callback %p\n", uid, acquired, port_no, callback);
814
815 spin_unlock_irqrestore(&hd->core_lock, flags);
816
817 return acquired;
818 }
819
820 int sata_core_has_fast_waiters(struct ata_host *ah)
821 {
822 int has_waiters;
823 unsigned long flags;
824 struct sata_oxnas_host_priv *hd = ah->private_data;
825
826 spin_lock_irqsave(&hd->core_lock, flags);
827 has_waiters = !list_empty(&hd->fast_wait_queue.task_list);
828 spin_unlock_irqrestore(&hd->core_lock, flags);
829
830 return has_waiters;
831 }
832 EXPORT_SYMBOL(sata_core_has_fast_waiters);
833
834 int sata_core_has_scsi_waiters(struct ata_host *ah)
835 {
836 int has_waiters;
837 unsigned long flags;
838 struct sata_oxnas_host_priv *hd = ah->private_data;
839
840 spin_lock_irqsave(&hd->core_lock, flags);
841 has_waiters = hd->scsi_nonblocking_attempts || !list_empty(&hd->scsi_wait_queue.task_list);
842 spin_unlock_irqrestore(&hd->core_lock, flags);
843
844 return has_waiters;
845 }
846 EXPORT_SYMBOL(sata_core_has_scsi_waiters);
847
848 /*
849 * ata_port operation to gain ownership of the SATA hardware prior to issuing
850 * a command against a SATA host. Allows any number of users of the port against
851 * which the lock was first acquired, thus enforcing that only one SATA core
852 * port may be operated on at once.
853 */
854 static int sata_oxnas_acquire_hw(
855 struct ata_port *ap,
856 int may_sleep,
857 int timeout_jiffies)
858 {
859 return __acquire_sata_core(ap->host, ap->port_no, NULL, 0, may_sleep, timeout_jiffies, 1, (void*)HW_LOCKER_UID, SATA_SCSI_STACK);
860 }
861
862 /*
863 * operation to release ownership of the SATA hardware
864 */
865 static void sata_oxnas_release_hw(struct ata_port *ap)
866 {
867 unsigned long flags;
868 int released = 0;
869 struct sata_oxnas_host_priv *hd = ap->host->private_data;
870
871 spin_lock_irqsave(&hd->core_lock, flags);
872
873 DPRINTK("Entered port_no = %d, h/w count %d, d count %d, core locked = %d, "
874 "reentrant_port_no = %d, isr_callback %p\n", ap->port_no,
875 hd->hw_lock_count, hd->direct_lock_count, hd->core_locked, hd->reentrant_port_no, hd->isr_callback);
876
877 if (!hd->core_locked) {
878 /* Nobody holds the SATA lock */
879 printk(KERN_WARNING "Nobody holds SATA lock, port_no %d\n", ap->port_no);
880 released = 1;
881 } else if (!hd->hw_lock_count) {
882 /* SCSI/SATA has released without holding the lock */
883 printk(KERN_WARNING "SCSI/SATA does not hold SATA lock, port_no %d\n", ap->port_no);
884 } else {
885 /* Trap incorrect usage */
886 BUG_ON(hd->reentrant_port_no == -1);
887 BUG_ON(ap->port_no != hd->reentrant_port_no);
888 BUG_ON(hd->direct_lock_count);
889 BUG_ON(hd->current_locker_type != SATA_SCSI_STACK);
890
891 WARN(!hd->locker_uid || (hd->locker_uid != HW_LOCKER_UID), "Invalid locker "
892 "uid %p, h/w count %d, d count %d, reentrant_port_no %d, "
893 "core_locked %d, isr_callback %p\n", hd->locker_uid,
894 hd->hw_lock_count, hd->direct_lock_count, hd->reentrant_port_no,
895 hd->core_locked, hd->isr_callback);
896
897 if (--(hd->hw_lock_count)) {
898 DPRINTK("Still nested port_no %d\n", ap->port_no);
899 } else {
900 DPRINTK("Release port_no %d\n", ap->port_no);
901 hd->reentrant_port_no = -1;
902 hd->isr_callback = NULL;
903 hd->current_locker_type = SATA_UNLOCKED;
904 hd->locker_uid = 0;
905 hd->core_locked = 0;
906 released = 1;
907 wake_up(!list_empty(&hd->scsi_wait_queue.task_list) ? &hd->scsi_wait_queue : &hd->fast_wait_queue);
908 }
909 }
910
911 DPRINTK("Leaving, port_no %d, count %d\n", ap->port_no, hd->hw_lock_count);
912
913 spin_unlock_irqrestore(&hd->core_lock, flags);
914
915 /* CONFIG_SATA_OX820_DIRECT_HWRAID */
916 /* if (released)
917 ox820hwraid_restart_queue();
918 } */
919 }
920
921 static inline int sata_oxnas_is_host_frozen(struct ata_host *ah)
922 {
923 struct sata_oxnas_host_priv *hd = ah->private_data;
924
925 smp_rmb();
926 return hd->port_in_eh || hd->port_frozen;
927 }
928
929
930 static inline u32 sata_oxnas_hostportbusy(struct ata_port *ap)
931 {
932 struct sata_oxnas_host_priv *hd = ap->host->private_data;
933
934 return (ioread32(hd->port_base + SATA_COMMAND) & CMD_CORE_BUSY) ||
935 (hd->n_ports > 1 &&
936 (ioread32(hd->port_base + PORT_SIZE + SATA_COMMAND) & CMD_CORE_BUSY));
937 }
938
939 static inline u32 sata_oxnas_hostdmabusy(struct ata_port *ap)
940 {
941 struct sata_oxnas_port_priv *pd = ap->private_data;
942
943 return ioread32(pd->sgdma_base + SGDMA_STATUS) & SGDMA_BUSY;
944 }
945
946
947 /**
948 * Turns on the cores clock and resets it
949 */
950 static void sata_oxnas_reset_core(struct ata_host *ah)
951 {
952 struct sata_oxnas_host_priv *host_priv = ah->private_data;
953 int n;
954
955 DPRINTK("ENTER\n");
956 clk_prepare_enable(host_priv->clk);
957
958 reset_control_assert(host_priv->rst_sata);
959 reset_control_assert(host_priv->rst_link);
960 reset_control_assert(host_priv->rst_phy);
961
962 udelay(50);
963
964 /* un-reset the PHY, then Link and Controller */
965 reset_control_deassert(host_priv->rst_phy);
966 udelay(50);
967
968 reset_control_deassert(host_priv->rst_sata);
969 reset_control_deassert(host_priv->rst_link);
970 udelay(50);
971
972 workaround5458(ah);
973 /* tune for sata compatability */
974 sata_oxnas_link_write(ah->ports[0], 0x60, 0x2988);
975
976 for (n=0; n < host_priv->n_ports; n++) {
977 /* each port in turn */
978 sata_oxnas_link_write(ah->ports[n], 0x70, 0x55629);
979 }
980 udelay(50);
981 }
982
983
984 /**
985 * Called after an identify device command has worked out what kind of device
986 * is on the port
987 *
988 * @param port The port to configure
989 * @param pdev The hardware associated with controlling the port
990 */
991 static void sata_oxnas_dev_config(struct ata_device *pdev)
992 {
993 struct sata_oxnas_port_priv *pd = pdev->link->ap->private_data;
994 void __iomem *port_base = pd->port_base;
995 u32 reg;
996
997 DPRINTK("ENTER\n");
998 /* Set the bits to put the port into 28 or 48-bit node */
999 reg = ioread32(port_base + DRIVE_CONTROL);
1000 reg &= ~3;
1001 reg |= (pdev->flags & ATA_DFLAG_LBA48) ? DR_CON_48 : DR_CON_28;
1002 iowrite32(reg, port_base + DRIVE_CONTROL);
1003
1004 /* if this is an ATA-6 disk, put port into ATA-5 auto translate mode */
1005 if (pdev->flags & ATA_DFLAG_LBA48) {
1006 reg = ioread32(port_base + PORT_CONTROL);
1007 reg |= 2;
1008 iowrite32(reg, port_base + PORT_CONTROL);
1009 }
1010 }
1011 /**
1012 * called to write a taskfile into the ORB registers
1013 * @param ap hardware with the registers in
1014 * @param tf taskfile to write to the registers
1015 */
1016 static void sata_oxnas_tf_load(struct ata_port *ap,
1017 const struct ata_taskfile *tf)
1018 {
1019 u32 count = 0;
1020 u32 Orb1 = 0;
1021 u32 Orb2 = 0;
1022 u32 Orb3 = 0;
1023 u32 Orb4 = 0;
1024 u32 Command_Reg;
1025
1026 struct sata_oxnas_port_priv *port_priv = ap->private_data;
1027 void __iomem *port_base = port_priv->port_base;
1028 unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
1029
1030 /* wait a maximum of 10ms for the core to be idle */
1031 do {
1032 Command_Reg = ioread32(port_base + SATA_COMMAND);
1033 if (!(Command_Reg & CMD_CORE_BUSY))
1034 break;
1035 count++;
1036 udelay(50);
1037 } while (count < 200);
1038
1039 /* check if the ctl register has interrupts disabled or enabled and
1040 * modify the interrupt enable registers on the ata core as required */
1041 if (tf->ctl & ATA_NIEN) {
1042 /* interrupts disabled */
1043 u32 mask = (COREINT_END << ap->port_no);
1044
1045 iowrite32(mask, port_priv->core_base + CORE_INT_DISABLE);
1046 sata_oxnas_irq_clear(ap);
1047 } else {
1048 sata_oxnas_irq_on(ap);
1049 }
1050
1051 Orb2 |= (tf->command) << 24;
1052
1053 /* write 48 or 28 bit tf parameters */
1054 if (is_addr) {
1055 /* set LBA bit as it's an address */
1056 Orb1 |= (tf->device & ATA_LBA) << 24;
1057
1058 if (tf->flags & ATA_TFLAG_LBA48) {
1059 Orb1 |= ATA_LBA << 24;
1060 Orb2 |= (tf->hob_nsect) << 8;
1061 Orb3 |= (tf->hob_lbal) << 24;
1062 Orb4 |= (tf->hob_lbam) << 0;
1063 Orb4 |= (tf->hob_lbah) << 8;
1064 Orb4 |= (tf->hob_feature) << 16;
1065 } else {
1066 Orb3 |= (tf->device & 0xf) << 24;
1067 }
1068
1069 /* write 28-bit lba */
1070 Orb2 |= (tf->nsect) << 0;
1071 Orb2 |= (tf->feature) << 16;
1072 Orb3 |= (tf->lbal) << 0;
1073 Orb3 |= (tf->lbam) << 8;
1074 Orb3 |= (tf->lbah) << 16;
1075 Orb4 |= (tf->ctl) << 24;
1076 }
1077
1078 if (tf->flags & ATA_TFLAG_DEVICE)
1079 Orb1 |= (tf->device) << 24;
1080
1081 ap->last_ctl = tf->ctl;
1082
1083 /* write values to registers */
1084 iowrite32(Orb1, port_base + ORB1);
1085 iowrite32(Orb2, port_base + ORB2);
1086 iowrite32(Orb3, port_base + ORB3);
1087 iowrite32(Orb4, port_base + ORB4);
1088 }
1089
1090
1091 void sata_oxnas_set_mode(struct ata_host *ah, u32 mode, u32 force)
1092 {
1093 struct sata_oxnas_host_priv *host_priv = ah->private_data;
1094 void __iomem *core_base = host_priv->core_base;
1095
1096 unsigned int *src;
1097 void __iomem *dst;
1098 unsigned int progmicrocode = 0;
1099 unsigned int changeparameters = 0;
1100
1101 u32 previous_mode;
1102
1103 /* these micro-code programs _should_ include the version word */
1104
1105 /* JBOD */
1106 static const unsigned int jbod[] = {
1107 0x07B400AC, 0x0228A280, 0x00200001, 0x00204002, 0x00224001,
1108 0x00EE0009, 0x00724901, 0x01A24903, 0x00E40009, 0x00224001,
1109 0x00621120, 0x0183C908, 0x00E20005, 0x00718908, 0x0198A206,
1110 0x00621124, 0x0183C908, 0x00E20046, 0x00621104, 0x0183C908,
1111 0x00E20015, 0x00EE009D, 0x01A3E301, 0x00E2001B, 0x0183C900,
1112 0x00E2001B, 0x00210001, 0x00EE0020, 0x01A3E302, 0x00E2009D,
1113 0x0183C901, 0x00E2009D, 0x00210002, 0x0235D700, 0x0208A204,
1114 0x0071C908, 0x000F8207, 0x000FC207, 0x0071C920, 0x000F8507,
1115 0x000FC507, 0x0228A240, 0x02269A40, 0x00094004, 0x00621104,
1116 0x0180C908, 0x00E40031, 0x00621112, 0x01A3C801, 0x00E2002B,
1117 0x00294000, 0x0228A220, 0x01A69ABF, 0x002F8000, 0x002FC000,
1118 0x0198A204, 0x0001C022, 0x01B1A220, 0x0001C106, 0x00088007,
1119 0x0183C903, 0x00E2009D, 0x0228A220, 0x0071890C, 0x0208A206,
1120 0x0198A206, 0x0001C022, 0x01B1A220, 0x0001C106, 0x00088007,
1121 0x00EE009D, 0x00621104, 0x0183C908, 0x00E2004A, 0x00EE009D,
1122 0x01A3C901, 0x00E20050, 0x0021E7FF, 0x0183E007, 0x00E2009D,
1123 0x00EE0054, 0x0061600B, 0x0021E7FF, 0x0183C507, 0x00E2009D,
1124 0x01A3E301, 0x00E2005A, 0x0183C900, 0x00E2005A, 0x00210001,
1125 0x00EE005F, 0x01A3E302, 0x00E20005, 0x0183C901, 0x00E20005,
1126 0x00210002, 0x0235D700, 0x0208A204, 0x000F8109, 0x000FC109,
1127 0x0071C918, 0x000F8407, 0x000FC407, 0x0001C022, 0x01A1A2BF,
1128 0x0001C106, 0x00088007, 0x02269A40, 0x00094004, 0x00621112,
1129 0x01A3C801, 0x00E4007F, 0x00621104, 0x0180C908, 0x00E4008D,
1130 0x00621128, 0x0183C908, 0x00E2006C, 0x01A3C901, 0x00E2007B,
1131 0x0021E7FF, 0x0183E007, 0x00E2007F, 0x00EE006C, 0x0061600B,
1132 0x0021E7FF, 0x0183C507, 0x00E4006C, 0x00621111, 0x01A3C801,
1133 0x00E2007F, 0x00621110, 0x01A3C801, 0x00E20082, 0x0228A220,
1134 0x00621119, 0x01A3C801, 0x00E20086, 0x0001C022, 0x01B1A220,
1135 0x0001C106, 0x00088007, 0x0198A204, 0x00294000, 0x01A69ABF,
1136 0x002F8000, 0x002FC000, 0x0183C903, 0x00E20005, 0x0228A220,
1137 0x0071890C, 0x0208A206, 0x0198A206, 0x0001C022, 0x01B1A220,
1138 0x0001C106, 0x00088007, 0x00EE009D, 0x00621128, 0x0183C908,
1139 0x00E20005, 0x00621104, 0x0183C908, 0x00E200A6, 0x0062111C,
1140 0x0183C908, 0x00E20005, 0x0071890C, 0x0208A206, 0x0198A206,
1141 0x00718908, 0x0208A206, 0x00EE0005, ~0
1142 };
1143
1144 /* Bi-Modal RAID-0/1 */
1145 static const unsigned int raid[] = {
1146 0x00F20145, 0x00EE20FA, 0x00EE20A7, 0x0001C009, 0x00EE0004,
1147 0x00220000, 0x0001000B, 0x037003FF, 0x00700018, 0x037003FE,
1148 0x037043FD, 0x00704118, 0x037043FC, 0x01A3D240, 0x00E20017,
1149 0x00B3C235, 0x00E40018, 0x0093C104, 0x00E80014, 0x0093C004,
1150 0x00E80017, 0x01020000, 0x00274020, 0x00EE0083, 0x0080C904,
1151 0x0093C104, 0x00EA0020, 0x0093C103, 0x00EC001F, 0x00220002,
1152 0x00924104, 0x0005C009, 0x00EE0058, 0x0093CF04, 0x00E80026,
1153 0x00900F01, 0x00600001, 0x00910400, 0x00EE0058, 0x00601604,
1154 0x01A00003, 0x00E2002C, 0x01018000, 0x00274040, 0x00EE0083,
1155 0x0093CF03, 0x00EC0031, 0x00220003, 0x00924F04, 0x0005C009,
1156 0x00810104, 0x00B3C235, 0x00E20037, 0x0022C000, 0x00218210,
1157 0x00EE0039, 0x0022C001, 0x00218200, 0x00600401, 0x00A04901,
1158 0x00604101, 0x01A0C401, 0x00E20040, 0x00216202, 0x00EE0041,
1159 0x00216101, 0x02018506, 0x00EE2141, 0x00904901, 0x00E20049,
1160 0x00A00401, 0x00600001, 0x02E0C301, 0x00EE2141, 0x00216303,
1161 0x037003EE, 0x01A3C001, 0x00E40105, 0x00250080, 0x00204000,
1162 0x002042F1, 0x0004C001, 0x00230001, 0x00100006, 0x02C18605,
1163 0x00100006, 0x01A3D502, 0x00E20055, 0x00EE0053, 0x00004009,
1164 0x00000004, 0x00B3C235, 0x00E40062, 0x0022C001, 0x0020C000,
1165 0x00EE2141, 0x0020C001, 0x00EE2141, 0x00EE006B, 0x0022C000,
1166 0x0060D207, 0x00EE2141, 0x00B3C242, 0x00E20069, 0x01A3D601,
1167 0x00E2006E, 0x02E0C301, 0x00EE2141, 0x00230001, 0x00301303,
1168 0x00EE007B, 0x00218210, 0x01A3C301, 0x00E20073, 0x00216202,
1169 0x00EE0074, 0x00216101, 0x02018506, 0x00214000, 0x037003EE,
1170 0x01A3C001, 0x00E40108, 0x00230001, 0x00100006, 0x00250080,
1171 0x00204000, 0x002042F1, 0x0004C001, 0x00EE007F, 0x0024C000,
1172 0x01A3D1F0, 0x00E20088, 0x00230001, 0x00300000, 0x01A3D202,
1173 0x00E20085, 0x00EE00A5, 0x00B3C800, 0x00E20096, 0x00218000,
1174 0x00924709, 0x0005C009, 0x00B20802, 0x00E40093, 0x037103FD,
1175 0x00710418, 0x037103FC, 0x00EE0006, 0x00220000, 0x0001000F,
1176 0x00EE0006, 0x00800B0C, 0x00B00001, 0x00204000, 0x00208550,
1177 0x00208440, 0x002083E0, 0x00208200, 0x00208100, 0x01008000,
1178 0x037083EE, 0x02008212, 0x02008216, 0x01A3C201, 0x00E400A5,
1179 0x0100C000, 0x00EE20FA, 0x02800000, 0x00208000, 0x00B24C00,
1180 0x00E400AD, 0x00224001, 0x00724910, 0x0005C009, 0x00B3CDC4,
1181 0x00E200D5, 0x00B3CD29, 0x00E200D5, 0x00B3CD20, 0x00E200D5,
1182 0x00B3CD24, 0x00E200D5, 0x00B3CDC5, 0x00E200D2, 0x00B3CD39,
1183 0x00E200D2, 0x00B3CD30, 0x00E200D2, 0x00B3CD34, 0x00E200D2,
1184 0x00B3CDCA, 0x00E200CF, 0x00B3CD35, 0x00E200CF, 0x00B3CDC8,
1185 0x00E200CC, 0x00B3CD25, 0x00E200CC, 0x00B3CD40, 0x00E200CB,
1186 0x00B3CD42, 0x00E200CB, 0x01018000, 0x00EE0083, 0x0025C000,
1187 0x036083EE, 0x0000800D, 0x00EE00D8, 0x036083EE, 0x00208035,
1188 0x00EE00DA, 0x036083EE, 0x00208035, 0x00EE00DA, 0x00208007,
1189 0x036083EE, 0x00208025, 0x036083EF, 0x02400000, 0x01A3D208,
1190 0x00E200D8, 0x0067120A, 0x0021C000, 0x0021C224, 0x00220000,
1191 0x00404B1C, 0x00600105, 0x00800007, 0x0020C00E, 0x00214000,
1192 0x01004000, 0x01A0411F, 0x00404E01, 0x01A3C101, 0x00E200F1,
1193 0x00B20800, 0x00E400D8, 0x00220001, 0x0080490B, 0x00B04101,
1194 0x0040411C, 0x00EE00E1, 0x02269A01, 0x01020000, 0x02275D80,
1195 0x01A3D202, 0x00E200F4, 0x01B75D80, 0x01030000, 0x01B69A01,
1196 0x00EE00D8, 0x01A3D204, 0x00E40104, 0x00224000, 0x0020C00E,
1197 0x0020001E, 0x00214000, 0x01004000, 0x0212490E, 0x00214001,
1198 0x01004000, 0x02400000, 0x00B3D702, 0x00E80112, 0x00EE010E,
1199 0x00B3D702, 0x00E80112, 0x00B3D702, 0x00E4010E, 0x00230001,
1200 0x00EE0140, 0x00200005, 0x036003EE, 0x00204001, 0x00EE0116,
1201 0x00230001, 0x00100006, 0x02C18605, 0x00100006, 0x01A3D1F0,
1202 0x00E40083, 0x037003EE, 0x01A3C002, 0x00E20121, 0x0020A300,
1203 0x0183D102, 0x00E20124, 0x037003EE, 0x01A00005, 0x036003EE,
1204 0x01A0910F, 0x00B3C20F, 0x00E2012F, 0x01A3D502, 0x00E20116,
1205 0x01A3C002, 0x00E20116, 0x00B3D702, 0x00E4012C, 0x00300000,
1206 0x00EE011F, 0x02C18605, 0x00100006, 0x00EE0116, 0x01A3D1F0,
1207 0x00E40083, 0x037003EE, 0x01A3C004, 0x00E20088, 0x00200003,
1208 0x036003EE, 0x01A3D502, 0x00E20136, 0x00230001, 0x00B3C101,
1209 0x00E4012C, 0x00100006, 0x02C18605, 0x00100006, 0x00204000,
1210 0x00EE0116, 0x00100006, 0x01A3D1F0, 0x00E40083, 0x01000000,
1211 0x02400000, ~0
1212 };
1213
1214 DPRINTK("ENTER: mode:%d, force:%d\n", mode, force);
1215
1216 if (force)
1217 previous_mode = UNKNOWN_MODE;
1218 else
1219 previous_mode = host_priv->current_ucode;
1220
1221 if (mode == previous_mode)
1222 return;
1223
1224 host_priv->current_ucode = mode;
1225
1226 /* decide what needs to be done using the STD in my logbook */
1227 switch (previous_mode) {
1228 case OXNASSATA_RAID1:
1229 switch (mode) {
1230 case OXNASSATA_RAID0:
1231 changeparameters = 1;
1232 break;
1233 case OXNASSATA_NOTRAID:
1234 changeparameters = 1;
1235 progmicrocode = 1;
1236 break;
1237 }
1238 break;
1239 case OXNASSATA_RAID0:
1240 switch (mode) {
1241 case OXNASSATA_RAID1:
1242 changeparameters = 1;
1243 break;
1244 case OXNASSATA_NOTRAID:
1245 changeparameters = 1;
1246 progmicrocode = 1;
1247 break;
1248 }
1249 break;
1250 case OXNASSATA_NOTRAID:
1251 switch (mode) {
1252 case OXNASSATA_RAID0:
1253 case OXNASSATA_RAID1:
1254 changeparameters = 1;
1255 progmicrocode = 1;
1256 break;
1257 }
1258 break;
1259 case UNKNOWN_MODE:
1260 changeparameters = 1;
1261 progmicrocode = 1;
1262 break;
1263 }
1264
1265 /* no need to reprogram everything if already in the right mode */
1266 if (progmicrocode) {
1267 /* reset micro-code processor */
1268 iowrite32(1, core_base + PROC_RESET);
1269 wmb();
1270
1271 /* select micro-code */
1272 switch (mode) {
1273 case OXNASSATA_RAID1:
1274 case OXNASSATA_RAID0:
1275 VPRINTK("Loading RAID micro-code\n");
1276 src = (unsigned int *)&raid[1];
1277 break;
1278 case OXNASSATA_NOTRAID:
1279 VPRINTK("Loading JBOD micro-code\n");
1280 src = (unsigned int *)&jbod[1];
1281 break;
1282 default:
1283 BUG();
1284 break;
1285 }
1286
1287 /* load micro code */
1288 dst = core_base + UCODE_STORE;
1289 while (*src != ~0) {
1290 iowrite32(*src, dst);
1291 src++;
1292 dst += sizeof(*src);
1293 }
1294 wmb();
1295 }
1296
1297 if (changeparameters) {
1298 u32 reg;
1299 /* set other mode dependent flags */
1300 switch (mode) {
1301 case OXNASSATA_RAID1:
1302 /* clear JBOD mode */
1303 reg = ioread32(core_base + DATA_PLANE_CTRL);
1304 reg |= DPC_JBOD_UCODE;
1305 reg &= ~DPC_FIS_SWCH;
1306 iowrite32(reg, core_base + DATA_PLANE_CTRL);
1307 wmb();
1308
1309 /* set the hardware up for RAID-1 */
1310 iowrite32(0, core_base + RAID_WP_BOT_LOW);
1311 iowrite32(0, core_base + RAID_WP_BOT_HIGH);
1312 iowrite32(0xffffffff, core_base + RAID_WP_TOP_LOW);
1313 iowrite32(0x7fffffff, core_base + RAID_WP_TOP_HIGH);
1314 iowrite32(0, core_base + RAID_SIZE_LOW);
1315 iowrite32(0, core_base + RAID_SIZE_HIGH);
1316 wmb();
1317 break;
1318 case OXNASSATA_RAID0:
1319 /* clear JBOD mode */
1320 reg = ioread32(core_base + DATA_PLANE_CTRL);
1321 reg |= DPC_JBOD_UCODE;
1322 reg &= ~DPC_FIS_SWCH;
1323 iowrite32(reg, core_base + DATA_PLANE_CTRL);
1324 wmb();
1325
1326 /* set the hardware up for RAID-1 */
1327 iowrite32(0, core_base + RAID_WP_BOT_LOW);
1328 iowrite32(0, core_base + RAID_WP_BOT_HIGH);
1329 iowrite32(0xffffffff, core_base + RAID_WP_TOP_LOW);
1330 iowrite32(0x7fffffff, core_base + RAID_WP_TOP_HIGH);
1331 iowrite32(0xffffffff, core_base + RAID_SIZE_LOW);
1332 iowrite32(0x7fffffff, core_base + RAID_SIZE_HIGH);
1333 wmb();
1334 break;
1335 case OXNASSATA_NOTRAID:
1336 /* enable jbod mode */
1337 reg = ioread32(core_base + DATA_PLANE_CTRL);
1338 reg &= ~DPC_JBOD_UCODE;
1339 reg &= ~DPC_FIS_SWCH;
1340 iowrite32(reg, core_base + DATA_PLANE_CTRL);
1341 wmb();
1342
1343 /* start micro-code processor*/
1344 iowrite32(1, core_base + PROC_START);
1345 break;
1346 default:
1347 reg = ioread32(core_base + DATA_PLANE_CTRL);
1348 reg |= DPC_JBOD_UCODE;
1349 reg &= ~DPC_FIS_SWCH;
1350 iowrite32(reg, core_base + DATA_PLANE_CTRL);
1351 wmb();
1352 break;
1353 }
1354 }
1355 }
1356
1357 /**
1358 * sends a sync-escape if there is a link present
1359 */
1360 static inline void sata_oxnas_send_sync_escape(struct ata_port *ap)
1361 {
1362 struct sata_oxnas_port_priv *pd = ap->private_data;
1363 u32 reg;
1364
1365 /* read the SSTATUS register and only send a sync escape if there is a
1366 * link active */
1367 if ((sata_oxnas_link_read(ap, 0x20) & 3) == 3) {
1368 reg = ioread32(pd->port_base + SATA_COMMAND);
1369 reg &= ~SATA_OPCODE_MASK;
1370 reg |= CMD_SYNC_ESCAPE;
1371 iowrite32(reg, pd->port_base + SATA_COMMAND);
1372 }
1373 }
1374
1375 /* clears errors */
1376 static inline void sata_oxnas_clear_CS_error(struct ata_port *ap)
1377 {
1378 struct sata_oxnas_port_priv *pd = ap->private_data;
1379 u32 *base = pd->port_base;
1380 u32 reg;
1381
1382 reg = ioread32(base + SATA_CONTROL);
1383 reg &= SATA_CTL_ERR_MASK;
1384 iowrite32(reg, base + SATA_CONTROL);
1385 }
1386
1387 static inline void sata_oxnas_reset_sgdma(struct ata_port *ap)
1388 {
1389 struct sata_oxnas_port_priv *pd = ap->private_data;
1390 iowrite32(SGDMA_RESETS_CTRL, pd->sgdma_base + SGDMA_RESETS);
1391 }
1392
1393 static inline void sata_oxnas_reset_dma(struct ata_port *ap, int assert)
1394 {
1395 struct sata_oxnas_port_priv *pd = ap->private_data;
1396 u32 reg;
1397
1398 reg = ioread32(pd->dmactl_base + DMA_CONTROL);
1399 if (assert)
1400 reg |= DMA_CONTROL_RESET;
1401 else
1402 reg &= ~DMA_CONTROL_RESET;
1403
1404 iowrite32(reg, pd->dmactl_base + DMA_CONTROL);
1405 };
1406
1407 /**
1408 * Clears the error caused by the core's registers being accessed when the
1409 * core is busy.
1410 */
1411 static inline void sata_oxnas_clear_reg_access_error(struct ata_port *ap)
1412 {
1413 struct sata_oxnas_port_priv *pd = ap->private_data;
1414 u32 *base = pd->port_base;
1415 u32 reg;
1416
1417 reg = ioread32(base + INT_STATUS);
1418
1419 DPRINTK("ENTER\n");
1420 if (reg & INT_REG_ACCESS_ERR) {
1421 printk(KERN_INFO "clearing register access error on port %d\n", ap->port_no);
1422 iowrite32(INT_REG_ACCESS_ERR, base + INT_STATUS);
1423 }
1424 reg = ioread32(base + INT_STATUS);
1425 if (reg & INT_REG_ACCESS_ERR)
1426 printk(KERN_INFO "register access error didn't clear\n");
1427 }
1428
1429 static inline void sata_oxnas_clear_sctl_error(struct ata_port *ap)
1430 {
1431 struct sata_oxnas_port_priv *pd = ap->private_data;
1432 u32 *base = pd->port_base;
1433 u32 reg;
1434
1435 reg = ioread32(base + SATA_CONTROL);
1436 reg |= SCTL_CLR_ERR;
1437 iowrite32(reg, base + SATA_CONTROL);
1438 }
1439
1440 static inline void sata_oxnas_clear_raid_error(struct ata_host *ah)
1441 {
1442 return;
1443 };
1444
1445 /**
1446 * Clean up all the state machines in the sata core.
1447 * @return post cleanup action required
1448 */
1449 static int sata_oxnas_cleanup(struct ata_host *ah)
1450 {
1451 struct sata_oxnas_host_priv *hd = ah->private_data;
1452 int actions_required = 0;
1453 int n;
1454 printk(KERN_INFO "sata_oxnas: reseting SATA core\n");
1455 /* core not recovering, reset it */
1456 mdelay(5);
1457 sata_oxnas_reset_core(ah);
1458 mdelay(5);
1459 actions_required |= OXNAS_SATA_REINIT;
1460 /* Perform any SATA core re-initialisation after reset post reset init
1461 * needs to be called for both ports as there's one reset for both
1462 * ports */
1463 for (n=0; n < hd->n_ports; n++)
1464 sata_oxnas_post_reset_init(ah->ports[n]);
1465
1466
1467 return actions_required;
1468 }
1469
1470 /**
1471 * ata_qc_new - Request an available ATA command, for queueing
1472 * @ap: Port associated with device @dev
1473 * @return non zero will refuse a new command, zero will may grant on subject
1474 * to conditions elsewhere.
1475 *
1476 */
1477 static int sata_oxnas_qc_new(struct ata_port *ap)
1478 {
1479 struct sata_oxnas_host_priv *hd = ap->host->private_data;
1480 DPRINTK("port %d\n", ap->port_no);
1481 smp_rmb();
1482 if (hd->port_frozen || hd->port_in_eh)
1483 return 1;
1484 else
1485 return !sata_oxnas_acquire_hw(ap, 0, 0);
1486 }
1487
1488 /**
1489 * releases the lock on the port the command used
1490 */
1491 static void sata_oxnas_qc_free(struct ata_queued_cmd *qc)
1492 {
1493 DPRINTK("\n");
1494 sata_oxnas_release_hw(qc->ap);
1495 }
1496
1497 static void sata_oxnas_freeze(struct ata_port* ap)
1498 {
1499 struct sata_oxnas_host_priv *hd = ap->host->private_data;
1500 DPRINTK("\n");
1501 hd->port_frozen |= BIT(ap->port_no);
1502 smp_wmb();
1503 }
1504
1505 static void sata_oxnas_thaw(struct ata_port* ap)
1506 {
1507 struct sata_oxnas_host_priv *hd = ap->host->private_data;
1508 DPRINTK("\n");
1509 hd->port_frozen &= ~BIT(ap->port_no);
1510 smp_wmb();
1511 }
1512
1513 void sata_oxnas_freeze_host(struct ata_port *ap)
1514 {
1515 struct sata_oxnas_host_priv *hd = ap->host->private_data;
1516
1517 DPRINTK("ENTER\n");
1518 hd->port_in_eh |= BIT(ap->port_no);
1519 smp_wmb();
1520 }
1521
1522 void sata_oxnas_thaw_host(struct ata_port *ap)
1523 {
1524 struct sata_oxnas_host_priv *hd = ap->host->private_data;
1525
1526 DPRINTK("ENTER\n");
1527 hd->port_in_eh &= ~BIT(ap->port_no);
1528 smp_wmb();
1529 }
1530
1531 static void sata_oxnas_post_internal_cmd(struct ata_queued_cmd *qc)
1532 {
1533 DPRINTK("ENTER\n");
1534 /* If the core is busy here, make it idle */
1535 if (qc->flags & ATA_QCFLAG_FAILED)
1536 sata_oxnas_cleanup(qc->ap->host);
1537 }
1538
1539
1540 /**
1541 * turn on the interrupts
1542 *
1543 * @param ap Hardware with the registers in
1544 */
1545 static void sata_oxnas_irq_on(struct ata_port *ap)
1546 {
1547 struct sata_oxnas_port_priv *pd = ap->private_data;
1548 u32 mask = (COREINT_END << ap->port_no);
1549
1550 /* Clear pending interrupts */
1551 iowrite32(~0, pd->port_base + INT_CLEAR);
1552 iowrite32(mask, pd->core_base + CORE_INT_STATUS);
1553 wmb();
1554
1555 /* enable End of command interrupt */
1556 iowrite32(INT_WANT, pd->port_base + INT_ENABLE);
1557 iowrite32(mask, pd->core_base + CORE_INT_ENABLE);
1558 }
1559
1560
1561 /** @return true if the port has a cable connected */
1562 int sata_oxnas_check_link(struct ata_port *ap)
1563 {
1564 int reg;
1565
1566 sata_oxnas_scr_read_port(ap, SCR_STATUS, &reg);
1567 /* Check for the cable present indicated by SCR status bit-0 set */
1568 return reg & 0x1;
1569 }
1570
1571 /**
1572 * ata_std_postreset - standard postreset callback
1573 * @link: the target ata_link
1574 * @classes: classes of attached devices
1575 *
1576 * This function is invoked after a successful reset. Note that
1577 * the device might have been reset more than once using
1578 * different reset methods before postreset is invoked.
1579 *
1580 * LOCKING:
1581 * Kernel thread context (may sleep)
1582 */
1583 static void sata_oxnas_postreset(struct ata_link *link, unsigned int *classes)
1584 {
1585 struct ata_port *ap = link->ap;
1586 struct sata_oxnas_host_priv *hd = ap->host->private_data;
1587
1588 unsigned int dev;
1589
1590 DPRINTK("ENTER\n");
1591 ata_std_postreset(link, classes);
1592
1593 /* turn on phy error detection by removing the masks */
1594 sata_oxnas_link_write(ap->host->ports[0], 0x0c, 0x30003);
1595 if (hd->n_ports > 1)
1596 sata_oxnas_link_write(ap->host->ports[1], 0x0c, 0x30003);
1597
1598 /* bail out if no device is present */
1599 if (classes[0] == ATA_DEV_NONE && classes[1] == ATA_DEV_NONE) {
1600 DPRINTK("EXIT, no device\n");
1601 return;
1602 }
1603
1604 /* go through all the devices and configure them */
1605 for (dev = 0; dev < ATA_MAX_DEVICES; ++dev) {
1606 if (ap->link.device[dev].class == ATA_DEV_ATA)
1607 sata_oxnas_dev_config(&(ap->link.device[dev]));
1608 }
1609
1610 DPRINTK("EXIT\n");
1611 }
1612
1613 /**
1614 * Called to read the hardware registers / DMA buffers, to
1615 * obtain the current set of taskfile register values.
1616 * @param ap hardware with the registers in
1617 * @param tf taskfile to read the registers into
1618 */
1619 static void sata_oxnas_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
1620 {
1621 struct sata_oxnas_port_priv *port_priv = ap->private_data;
1622 void __iomem *port_base = port_priv->port_base;
1623 /* read the orb registers */
1624 u32 Orb1 = ioread32(port_base + ORB1);
1625 u32 Orb2 = ioread32(port_base + ORB2);
1626 u32 Orb3 = ioread32(port_base + ORB3);
1627 u32 Orb4 = ioread32(port_base + ORB4);
1628
1629 /* read common 28/48 bit tf parameters */
1630 tf->device = (Orb1 >> 24);
1631 tf->nsect = (Orb2 >> 0);
1632 tf->feature = (Orb2 >> 16);
1633 tf->command = sata_oxnas_check_status(ap);
1634
1635 /* read 48 or 28 bit tf parameters */
1636 if (tf->flags & ATA_TFLAG_LBA48) {
1637 tf->hob_nsect = (Orb2 >> 8);
1638 tf->lbal = (Orb3 >> 0);
1639 tf->lbam = (Orb3 >> 8);
1640 tf->lbah = (Orb3 >> 16);
1641 tf->hob_lbal = (Orb3 >> 24);
1642 tf->hob_lbam = (Orb4 >> 0);
1643 tf->hob_lbah = (Orb4 >> 8);
1644 /* feature ext and control are write only */
1645 } else {
1646 /* read 28-bit lba */
1647 tf->lbal = (Orb3 >> 0);
1648 tf->lbam = (Orb3 >> 8);
1649 tf->lbah = (Orb3 >> 16);
1650 }
1651 }
1652
1653 /**
1654 * Read a result task-file from the sata core registers.
1655 */
1656 static bool sata_oxnas_qc_fill_rtf(struct ata_queued_cmd *qc)
1657 {
1658 /* Read the most recently received FIS from the SATA core ORB registers
1659 and convert to an ATA taskfile */
1660 sata_oxnas_tf_read(qc->ap, &qc->result_tf);
1661 return true;
1662 }
1663
1664 /**
1665 * Reads the Status ATA shadow register from hardware.
1666 *
1667 * @return The status register
1668 */
1669 static u8 sata_oxnas_check_status(struct ata_port *ap)
1670 {
1671 u32 Reg;
1672 u8 status;
1673 struct sata_oxnas_port_priv *port_priv = ap->private_data;
1674 void __iomem *port_base = port_priv->port_base;
1675
1676 /* read byte 3 of Orb2 register */
1677 status = ioread32(port_base + ORB2) >> 24;
1678
1679 /* check for the drive going missing indicated by SCR status bits
1680 * 0-3 = 0 */
1681 sata_oxnas_scr_read_port(ap, SCR_STATUS, &Reg);
1682
1683 if (!(Reg & 0x1)) {
1684 status |= ATA_DF;
1685 status |= ATA_ERR;
1686 }
1687
1688 return status;
1689 }
1690
1691 static inline void sata_oxnas_reset_ucode(struct ata_host *ah, int force, int no_microcode)
1692 {
1693 struct sata_oxnas_host_priv *hd = ah->private_data;
1694
1695 DPRINTK("ENTER\n");
1696 if (no_microcode) {
1697 u32 reg;
1698 sata_oxnas_set_mode(ah, UNKNOWN_MODE, force);
1699 reg = ioread32(hd->core_base + DEVICE_CONTROL);
1700 reg |= DEVICE_CONTROL_ATA_ERR_OVERRIDE;
1701 iowrite32(reg, hd->core_base + DEVICE_CONTROL);
1702 } else {
1703 /* JBOD uCode */
1704 sata_oxnas_set_mode(ah, OXNASSATA_NOTRAID, force);
1705 /* Turn the work around off as it may have been left on by any
1706 * HW-RAID code that we've been working with */
1707 iowrite32(0x0, hd->core_base + PORT_ERROR_MASK);
1708 }
1709 }
1710
1711 /**
1712 * Prepare as much as possible for a command without involving anything that is
1713 * shared between ports.
1714 */
1715 static void sata_oxnas_qc_prep(struct ata_queued_cmd *qc)
1716 {
1717 struct sata_oxnas_port_priv *pd;
1718 int port_no = qc->ap->port_no;
1719
1720 /* if the port's not connected, complete now with an error */
1721 if (!sata_oxnas_check_link(qc->ap)) {
1722 printk(KERN_ERR "port %d not connected completing with error\n",
1723 port_no);
1724 qc->err_mask |= AC_ERR_ATA_BUS;
1725 ata_qc_complete(qc);
1726 }
1727
1728 sata_oxnas_reset_ucode(qc->ap->host, 0, 0);
1729
1730 /* both pio and dma commands use dma */
1731 if (ata_is_dma(qc->tf.protocol) || ata_is_pio(qc->tf.protocol)) {
1732
1733 /* program the scatterlist into the prd table */
1734 ata_bmdma_qc_prep(qc);
1735
1736 /* point the sgdma controller at the dma request structure */
1737 pd = qc->ap->private_data;
1738
1739 iowrite32(pd->sgdma_request_pa,
1740 pd->sgdma_base + SGDMA_REQUESTPTR);
1741
1742 /* setup the request table */
1743 if (port_no == 0) {
1744 pd->sgdma_request->control =
1745 (qc->dma_dir == DMA_FROM_DEVICE) ?
1746 SGDMA_REQCTL0IN : SGDMA_REQCTL0OUT;
1747 } else {
1748 pd->sgdma_request->control =
1749 (qc->dma_dir == DMA_FROM_DEVICE) ?
1750 SGDMA_REQCTL1IN : SGDMA_REQCTL1OUT;
1751 }
1752 pd->sgdma_request->qualifier = SGDMA_REQQUAL;
1753 pd->sgdma_request->src_pa = qc->ap->bmdma_prd_dma;
1754 pd->sgdma_request->dst_pa = qc->ap->bmdma_prd_dma;
1755 smp_wmb();
1756
1757 /* tell it to wait */
1758 iowrite32(SGDMA_CONTROL_NOGO, pd->sgdma_base + SGDMA_CONTROL);
1759 }
1760 }
1761
1762 static int sata_oxnas_port_start(struct ata_port *ap)
1763 {
1764 struct sata_oxnas_host_priv *host_priv = ap->host->private_data;
1765 struct device *dev = ap->host->dev;
1766 struct sata_oxnas_port_priv *pp;
1767 void *mem;
1768 dma_addr_t mem_dma;
1769
1770 DPRINTK("ENTER\n");
1771
1772 pp = kzalloc(sizeof(*pp), GFP_KERNEL);
1773 if (!pp)
1774 return -ENOMEM;
1775
1776 pp->port_base = host_priv->port_base +
1777 (ap->port_no ? PORT_SIZE : 0);
1778 pp->dmactl_base = host_priv->dmactl_base +
1779 (ap->port_no ? DMA_CORESIZE : 0);
1780 pp->sgdma_base = host_priv->sgdma_base +
1781 (ap->port_no ? SGDMA_CORESIZE : 0);
1782 pp->core_base = host_priv->core_base;
1783
1784 /* preallocated */
1785 if (host_priv->dma_size >= SATA_OXNAS_DMA_SIZE * host_priv->n_ports) {
1786 DPRINTK("using preallocated DMA\n");
1787 mem_dma = host_priv->dma_base +
1788 (ap->port_no ? SATA_OXNAS_DMA_SIZE : 0);
1789 mem = ioremap(mem_dma, SATA_OXNAS_DMA_SIZE);
1790 } else {
1791 mem = dma_alloc_coherent(dev, SATA_OXNAS_DMA_SIZE, &mem_dma,
1792 GFP_KERNEL);
1793 }
1794 if (!mem)
1795 goto err_ret;
1796
1797 pp->sgdma_request_pa = mem_dma;
1798 pp->sgdma_request = mem;
1799
1800 ap->bmdma_prd_dma = mem_dma + sizeof(struct sgdma_request);
1801 ap->bmdma_prd = mem + sizeof(struct sgdma_request);
1802
1803 ap->private_data = pp;
1804
1805 sata_oxnas_post_reset_init(ap);
1806
1807 return 0;
1808
1809 err_ret:
1810 kfree(pp);
1811 return -ENOMEM;
1812
1813 }
1814
1815 static void sata_oxnas_port_stop(struct ata_port *ap)
1816 {
1817 struct device *dev = ap->host->dev;
1818 struct sata_oxnas_port_priv *pp = ap->private_data;
1819 struct sata_oxnas_host_priv *host_priv = ap->host->private_data;
1820
1821 DPRINTK("ENTER\n");
1822 ap->private_data = NULL;
1823 if (host_priv->dma_size) {
1824 iounmap(pp->sgdma_request);
1825 } else {
1826 dma_free_coherent(dev, SATA_OXNAS_DMA_SIZE,
1827 pp->sgdma_request, pp->sgdma_request_pa);
1828 }
1829
1830 kfree(pp);
1831 }
1832
1833
1834 static void sata_oxnas_post_reset_init(struct ata_port *ap)
1835 {
1836 uint dev;
1837
1838 /* force to load u-code only once after reset */
1839 sata_oxnas_reset_ucode(ap->host, !ap->port_no, 0);
1840
1841 /* turn on phy error detection by removing the masks */
1842 sata_oxnas_link_write(ap, 0x0C, 0x30003);
1843
1844 /* enable hotplug event detection */
1845 sata_oxnas_scr_write_port(ap, SCR_ERROR, ~0);
1846 sata_oxnas_scr_write_port(ap, SERROR_IRQ_MASK, 0x03feffff);
1847 sata_oxnas_scr_write_port(ap, SCR_ACTIVE, ~0 & ~(1 << 26) & ~(1 << 16));
1848
1849 /* enable interrupts for ports */
1850 sata_oxnas_irq_on(ap);
1851
1852 /* go through all the devices and configure them */
1853 for (dev = 0; dev < ATA_MAX_DEVICES; ++dev) {
1854 if (ap->link.device[dev].class == ATA_DEV_ATA) {
1855 sata_std_hardreset(&ap->link, NULL, jiffies + HZ);
1856 sata_oxnas_dev_config(&(ap->link.device[dev]));
1857 }
1858 }
1859
1860 /* clean up any remaining errors */
1861 sata_oxnas_scr_write_port(ap, SCR_ERROR, ~0);
1862 VPRINTK("done\n");
1863 }
1864
1865 /**
1866 * host_stop() is called when the rmmod or hot unplug process begins. The
1867 * hook must stop all hardware interrupts, DMA engines, etc.
1868 *
1869 * @param ap hardware with the registers in
1870 */
1871 static void sata_oxnas_host_stop(struct ata_host *host_set)
1872 {
1873 DPRINTK("\n");
1874 }
1875
1876
1877 #define ERROR_HW_ACQUIRE_TIMEOUT_JIFFIES (10 * HZ)
1878 static void sata_oxnas_error_handler(struct ata_port *ap)
1879 {
1880 DPRINTK("Enter port_no %d\n", ap->port_no);
1881 sata_oxnas_freeze_host(ap);
1882
1883 /* If the core is busy here, make it idle */
1884 sata_oxnas_cleanup(ap->host);
1885
1886 ata_std_error_handler(ap);
1887
1888 sata_oxnas_thaw_host(ap);
1889 }
1890
1891 static int sata_oxnas_softreset(struct ata_link *link, unsigned int *class,
1892 unsigned long deadline)
1893 {
1894 struct ata_port *ap = link->ap;
1895 struct sata_oxnas_port_priv *pd = ap->private_data;
1896 void __iomem *port_base = pd->port_base;
1897 int rc;
1898
1899 struct ata_taskfile tf;
1900 u32 Command_Reg;
1901
1902 DPRINTK("ENTER\n");
1903
1904 port_base = pd->port_base;
1905
1906 if (ata_link_offline(link)) {
1907 DPRINTK("PHY reports no device\n");
1908 *class = ATA_DEV_NONE;
1909 goto out;
1910 }
1911
1912 /* write value to register */
1913 iowrite32(0, port_base + ORB1);
1914 iowrite32(0, port_base + ORB2);
1915 iowrite32(0, port_base + ORB3);
1916 iowrite32((ap->ctl) << 24, port_base + ORB4);
1917
1918 /* command the core to send a control FIS */
1919 Command_Reg = ioread32(port_base + SATA_COMMAND);
1920 Command_Reg &= ~SATA_OPCODE_MASK;
1921 Command_Reg |= CMD_WRITE_TO_ORB_REGS_NO_COMMAND;
1922 iowrite32(Command_Reg, port_base + SATA_COMMAND);
1923 udelay(20); /* FIXME: flush */
1924
1925 /* write value to register */
1926 iowrite32((ap->ctl | ATA_SRST) << 24, port_base + ORB4);
1927
1928 /* command the core to send a control FIS */
1929 Command_Reg &= ~SATA_OPCODE_MASK;
1930 Command_Reg |= CMD_WRITE_TO_ORB_REGS_NO_COMMAND;
1931 iowrite32(Command_Reg, port_base + SATA_COMMAND);
1932 udelay(20); /* FIXME: flush */
1933
1934 /* write value to register */
1935 iowrite32((ap->ctl) << 24, port_base + ORB4);
1936
1937 /* command the core to send a control FIS */
1938 Command_Reg &= ~SATA_OPCODE_MASK;
1939 Command_Reg |= CMD_WRITE_TO_ORB_REGS_NO_COMMAND;
1940 iowrite32(Command_Reg, port_base + SATA_COMMAND);
1941
1942 msleep(150);
1943
1944 rc = ata_sff_wait_ready(link, deadline);
1945
1946 /* if link is occupied, -ENODEV too is an error */
1947 if (rc && (rc != -ENODEV || sata_scr_valid(link))) {
1948 ata_link_printk(link, KERN_ERR, "SRST failed (errno=%d)\n", rc);
1949 return rc;
1950 }
1951
1952 /* determine by signature whether we have ATA or ATAPI devices */
1953 sata_oxnas_tf_read(ap, &tf);
1954 *class = ata_dev_classify(&tf);
1955
1956 if (*class == ATA_DEV_UNKNOWN)
1957 *class = ATA_DEV_NONE;
1958
1959 out:
1960 DPRINTK("EXIT, class=%u\n", *class);
1961 return 0;
1962 }
1963
1964
1965 int sata_oxnas_init_controller(struct ata_host *host)
1966 {
1967 return 0;
1968 }
1969
1970 /**
1971 * Ref bug-6320
1972 *
1973 * This code is a work around for a DMA hardware bug that will repeat the
1974 * penultimate 8-bytes on some reads. This code will check that the amount
1975 * of data transferred is a multiple of 512 bytes, if not the in it will
1976 * fetch the correct data from a buffer in the SATA core and copy it into
1977 * memory.
1978 *
1979 * @param port SATA port to check and if necessary, correct.
1980 */
1981 static int sata_oxnas_bug_6320_workaround(struct ata_port *ap)
1982 {
1983 struct sata_oxnas_port_priv *pd = ap->private_data;
1984 void __iomem *core_base = pd->core_base;
1985 int is_read;
1986 int quads_transferred;
1987 int remainder;
1988 int sector_quads_remaining;
1989 int bug_present = 0;
1990
1991 /* Only want to apply fix to reads */
1992 is_read = !(ioread32(core_base + DM_DBG1) & (ap->port_no ?
1993 BIT(CORE_PORT1_DATA_DIR_BIT) :
1994 BIT(CORE_PORT0_DATA_DIR_BIT)));
1995
1996 /* Check for an incomplete transfer, i.e. not a multiple of 512 bytes
1997 transferred (datacount_port register counts quads transferred) */
1998 quads_transferred =
1999 ioread32(core_base + (ap->port_no ?
2000 DATACOUNT_PORT1 : DATACOUNT_PORT0));
2001
2002 remainder = quads_transferred & 0x7f;
2003 sector_quads_remaining = remainder ? (0x80 - remainder) : 0;
2004
2005 if (is_read && (sector_quads_remaining == 2)) {
2006 bug_present = 1;
2007 } else if (sector_quads_remaining) {
2008 if (is_read) {
2009 printk(KERN_WARNING "SATA read fixup cannot deal with" \
2010 " %d quads remaining\n",
2011 sector_quads_remaining);
2012 } else {
2013 printk(KERN_WARNING "SATA write fixup of %d quads" \
2014 " remaining not supported\n",
2015 sector_quads_remaining);
2016 }
2017 }
2018
2019 return bug_present;
2020 }
2021
2022 /* This port done an interrupt */
2023 static void sata_oxnas_port_irq(struct ata_port *ap, int force_error)
2024 {
2025 struct ata_queued_cmd *qc;
2026 struct sata_oxnas_port_priv *pd = ap->private_data;
2027 void __iomem *port_base = pd->port_base;
2028
2029 u32 int_status;
2030 unsigned long flags = 0;
2031
2032 DPRINTK("ENTER port %d irqstatus %x\n", ap->port_no, ioread32(port_base + INT_STATUS));
2033
2034 if (ap->qc_active & (1 << ATA_TAG_INTERNAL)) {
2035 qc = ata_qc_from_tag(ap, ATA_TAG_INTERNAL);
2036 DPRINTK("completing non-ncq cmd\n");
2037
2038 if (qc) {
2039 ata_qc_complete(qc);
2040 }
2041 return;
2042 }
2043
2044 qc = ata_qc_from_tag(ap, ap->link.active_tag);
2045
2046
2047 /* record the port's interrupt */
2048 int_status = ioread32(port_base + INT_STATUS);
2049
2050 /* If there's no command associated with this IRQ, ignore it. We may get
2051 * spurious interrupts when cleaning-up after a failed command, ignore
2052 * these too. */
2053 if (likely(qc)) {
2054 /* get the status before any error cleanup */
2055 qc->err_mask = ac_err_mask(sata_oxnas_check_status(ap));
2056 if (force_error) {
2057 /* Pretend there has been a link error */
2058 qc->err_mask |= AC_ERR_ATA_BUS;
2059 DPRINTK(" ####force error####\n");
2060 }
2061 /* tell libata we're done */
2062 local_irq_save(flags);
2063 sata_oxnas_irq_clear(ap);
2064 local_irq_restore(flags);
2065 ata_qc_complete(qc);
2066 } else {
2067 VPRINTK("Ignoring interrupt, can't find the command tag=" \
2068 "%d %08x\n", ap->link.active_tag, ap->qc_active);
2069 }
2070
2071 /* maybe a hotplug event */
2072 if (unlikely(int_status & INT_LINK_SERROR)) {
2073 u32 serror;
2074
2075 sata_oxnas_scr_read_port(ap, SCR_ERROR, &serror);
2076 if (serror & (SERR_DEV_XCHG | SERR_PHYRDY_CHG)) {
2077 ata_ehi_hotplugged(&ap->link.eh_info);
2078 ata_port_freeze(ap);
2079 }
2080 }
2081 }
2082
2083 /**
2084 * irq_handler is the interrupt handling routine registered with the system,
2085 * by libata.
2086 */
2087 static irqreturn_t sata_oxnas_interrupt(int irq, void *dev_instance)
2088 {
2089 struct ata_host *ah = dev_instance;
2090 struct sata_oxnas_host_priv *hd = ah->private_data;
2091 void __iomem *core_base = hd->core_base;
2092
2093 u32 int_status;
2094 irqreturn_t ret = IRQ_NONE;
2095 u32 port_no;
2096 u32 mask;
2097 int bug_present;
2098
2099 /* loop until there are no more interrupts */
2100 while ((int_status = (ioread32(core_base + CORE_INT_STATUS)) &
2101 (COREINT_END | (COREINT_END << 1)) )) {
2102
2103 /* clear any interrupt */
2104 iowrite32(int_status, core_base + CORE_INT_CLEAR);
2105
2106 /* Only need workaround_bug_6320 for single disk systems as dual
2107 * disk will use uCode which prevents this read underrun problem
2108 * from occuring.
2109 * All single disk systems will use port 0 */
2110 for (port_no = 0; port_no < hd->n_ports; ++port_no) {
2111 /* check the raw end of command interrupt to see if the
2112 * port is done */
2113 mask = (COREINT_END << port_no);
2114 if (int_status & mask) {
2115 /* this port had an interrupt, clear it */
2116 iowrite32(mask, core_base + CORE_INT_CLEAR);
2117 bug_present = ( hd->current_ucode == UNKNOWN_MODE ) ?
2118 sata_oxnas_bug_6320_workaround(
2119 ah->ports[port_no]) : 0;
2120 sata_oxnas_port_irq(ah->ports[port_no],
2121 bug_present);
2122 ret = IRQ_HANDLED;
2123 }
2124 }
2125 }
2126
2127 return ret;
2128 }
2129
2130 /*
2131 * scsi mid-layer and libata interface structures
2132 */
2133 static struct scsi_host_template sata_oxnas_sht = {
2134 ATA_NCQ_SHT("sata_oxnas"),
2135 .can_queue = SATA_OXNAS_QUEUE_DEPTH,
2136 .sg_tablesize = SATA_OXNAS_MAX_PRD,
2137 .dma_boundary = ATA_DMA_BOUNDARY,
2138 .unchecked_isa_dma = 0,
2139 };
2140
2141
2142 static struct ata_port_operations sata_oxnas_ops = {
2143 .inherits = &sata_port_ops,
2144 .qc_prep = sata_oxnas_qc_prep,
2145 .qc_issue = sata_oxnas_qc_issue,
2146 .qc_fill_rtf = sata_oxnas_qc_fill_rtf,
2147 .qc_new = sata_oxnas_qc_new,
2148 .qc_free = sata_oxnas_qc_free,
2149
2150 .scr_read = sata_oxnas_scr_read,
2151 .scr_write = sata_oxnas_scr_write,
2152
2153 .freeze = sata_oxnas_freeze,
2154 .thaw = sata_oxnas_thaw,
2155 .softreset = sata_oxnas_softreset,
2156 /* .hardreset = sata_oxnas_hardreset, */
2157 .postreset = sata_oxnas_postreset,
2158 .error_handler = sata_oxnas_error_handler,
2159 .post_internal_cmd = sata_oxnas_post_internal_cmd,
2160
2161 .port_start = sata_oxnas_port_start,
2162 .port_stop = sata_oxnas_port_stop,
2163
2164 .host_stop = sata_oxnas_host_stop,
2165 /* .pmp_attach = sata_oxnas_pmp_attach, */
2166 /* .pmp_detach = sata_oxnas_pmp_detach, */
2167 .sff_check_status = sata_oxnas_check_status,
2168 .acquire_hw = sata_oxnas_acquire_hw,
2169 };
2170
2171 static const struct ata_port_info sata_oxnas_port_info = {
2172 .flags = SATA_OXNAS_HOST_FLAGS,
2173 .pio_mask = ATA_PIO4,
2174 .udma_mask = ATA_UDMA6,
2175 .port_ops = &sata_oxnas_ops,
2176 };
2177
2178 static int sata_oxnas_probe(struct platform_device *ofdev)
2179 {
2180 int retval = -ENXIO;
2181 int n_ports = 0;
2182 void __iomem *port_base = NULL;
2183 void __iomem *dmactl_base = NULL;
2184 void __iomem *sgdma_base = NULL;
2185 void __iomem *core_base = NULL;
2186 void __iomem *phy_base = NULL;
2187 struct reset_control *rstc;
2188
2189 struct resource res = {};
2190 struct sata_oxnas_host_priv *host_priv = NULL;
2191 int irq = 0;
2192 struct ata_host *host = NULL;
2193 struct clk *clk = NULL;
2194
2195 const struct ata_port_info *ppi[] = { &sata_oxnas_port_info, NULL };
2196 const struct ata_port_info *dppi[] = { &sata_oxnas_port_info, &sata_oxnas_port_info, NULL };
2197
2198 of_property_read_u32(ofdev->dev.of_node, "nr-ports", &n_ports);
2199 if (n_ports < 1 || n_ports > SATA_OXNAS_MAX_PORTS)
2200 goto error_exit_with_cleanup;
2201
2202 port_base = of_iomap(ofdev->dev.of_node, 0);
2203 if (!port_base)
2204 goto error_exit_with_cleanup;
2205
2206 dmactl_base = of_iomap(ofdev->dev.of_node, 1);
2207 if (!dmactl_base)
2208 goto error_exit_with_cleanup;
2209
2210 sgdma_base = of_iomap(ofdev->dev.of_node, 2);
2211 if (!sgdma_base)
2212 goto error_exit_with_cleanup;
2213
2214 core_base = of_iomap(ofdev->dev.of_node, 3);
2215 if (!core_base)
2216 goto error_exit_with_cleanup;
2217
2218 phy_base = of_iomap(ofdev->dev.of_node, 4);
2219 if (!phy_base)
2220 goto error_exit_with_cleanup;
2221
2222 host_priv = devm_kzalloc(&ofdev->dev,
2223 sizeof(struct sata_oxnas_host_priv),
2224 GFP_KERNEL);
2225 if (!host_priv)
2226 goto error_exit_with_cleanup;
2227
2228 host_priv->port_base = port_base;
2229 host_priv->dmactl_base = dmactl_base;
2230 host_priv->sgdma_base = sgdma_base;
2231 host_priv->core_base = core_base;
2232 host_priv->phy_base = phy_base;
2233 host_priv->n_ports = n_ports;
2234 host_priv->current_ucode = UNKNOWN_MODE;
2235
2236 if (!of_address_to_resource(ofdev->dev.of_node, 5, &res)) {
2237 host_priv->dma_base = res.start;
2238 host_priv->dma_size = resource_size(&res);
2239 }
2240
2241 irq = irq_of_parse_and_map(ofdev->dev.of_node, 0);
2242 if (!irq) {
2243 dev_err(&ofdev->dev, "invalid irq from platform\n");
2244 goto error_exit_with_cleanup;
2245 }
2246 host_priv->irq = irq;
2247
2248 clk = of_clk_get(ofdev->dev.of_node, 0);
2249 if (IS_ERR(clk)) {
2250 retval = PTR_ERR(clk);
2251 clk = NULL;
2252 goto error_exit_with_cleanup;
2253 }
2254 host_priv->clk = clk;
2255
2256 rstc = devm_reset_control_get(&ofdev->dev, "sata");
2257 if (IS_ERR(rstc)) {
2258 retval = PTR_ERR(rstc);
2259 goto error_exit_with_cleanup;
2260 }
2261 host_priv->rst_sata = rstc;
2262
2263 rstc = devm_reset_control_get(&ofdev->dev, "link");
2264 if (IS_ERR(rstc)) {
2265 retval = PTR_ERR(rstc);
2266 goto error_exit_with_cleanup;
2267 }
2268 host_priv->rst_link = rstc;
2269
2270 rstc = devm_reset_control_get(&ofdev->dev, "phy");
2271 if (IS_ERR(rstc)) {
2272 retval = PTR_ERR(rstc);
2273 goto error_exit_with_cleanup;
2274 }
2275 host_priv->rst_phy = rstc;
2276
2277 /* allocate host structure */
2278 host = ata_host_alloc_pinfo(&ofdev->dev, n_ports>1 ? dppi : ppi,
2279 n_ports);
2280
2281 if (!host) {
2282 retval = -ENOMEM;
2283 goto error_exit_with_cleanup;
2284 }
2285 host->private_data = host_priv;
2286 host->iomap = port_base;
2287
2288 /* initialize core locking and queues */
2289 init_waitqueue_head(&host_priv->fast_wait_queue);
2290 init_waitqueue_head(&host_priv->scsi_wait_queue);
2291 spin_lock_init(&host_priv->phy_lock);
2292 spin_lock_init(&host_priv->core_lock);
2293 host_priv->core_locked = 0;
2294 host_priv->reentrant_port_no = -1;
2295 host_priv->hw_lock_count = 0;
2296 host_priv->direct_lock_count = 0;
2297 host_priv->locker_uid = 0;
2298 host_priv->current_locker_type = SATA_UNLOCKED;
2299 host_priv->isr_arg = NULL;
2300 host_priv->isr_callback = NULL;
2301
2302 /* initialize host controller */
2303 retval = sata_oxnas_init_controller(host);
2304 if (retval)
2305 goto error_exit_with_cleanup;
2306
2307 /*
2308 * Now, register with libATA core, this will also initiate the
2309 * device discovery process, invoking our port_start() handler &
2310 * error_handler() to execute a dummy softreset EH session
2311 */
2312 ata_host_activate(host, irq, sata_oxnas_interrupt, SATA_OXNAS_IRQ_FLAG,
2313 &sata_oxnas_sht);
2314
2315 return 0;
2316
2317 error_exit_with_cleanup:
2318 if (irq)
2319 irq_dispose_mapping(host_priv->irq);
2320 if (clk)
2321 clk_put(clk);
2322 if (host)
2323 ata_host_detach(host);
2324 if (port_base)
2325 iounmap(port_base);
2326 if (sgdma_base)
2327 iounmap(sgdma_base);
2328 if (core_base)
2329 iounmap(core_base);
2330 if (phy_base)
2331 iounmap(phy_base);
2332 return retval;
2333 }
2334
2335
2336 static int sata_oxnas_remove(struct platform_device *ofdev)
2337 {
2338 struct ata_host *host = dev_get_drvdata(&ofdev->dev);
2339 struct sata_oxnas_host_priv *host_priv = host->private_data;
2340
2341 ata_host_detach(host);
2342
2343 irq_dispose_mapping(host_priv->irq);
2344 iounmap(host_priv->port_base);
2345 iounmap(host_priv->sgdma_base);
2346 iounmap(host_priv->core_base);
2347
2348 /* reset Controller, Link and PHY */
2349 reset_control_assert(host_priv->rst_sata);
2350 reset_control_assert(host_priv->rst_link);
2351 reset_control_assert(host_priv->rst_phy);
2352
2353 /* Disable the clock to the SATA block */
2354 clk_disable_unprepare(host_priv->clk);
2355 clk_put(host_priv->clk);
2356
2357 return 0;
2358 }
2359
2360 #ifdef CONFIG_PM
2361 static int sata_oxnas_suspend(struct platform_device *op, pm_message_t state)
2362 {
2363 struct ata_host *host = dev_get_drvdata(&op->dev);
2364
2365 return ata_host_suspend(host, state);
2366 }
2367
2368 static int sata_oxnas_resume(struct platform_device *op)
2369 {
2370 struct ata_host *host = dev_get_drvdata(&op->dev);
2371 int ret;
2372
2373 ret = sata_oxnas_init_controller(host);
2374 if (ret) {
2375 dev_err(&op->dev, "Error initializing hardware\n");
2376 return ret;
2377 }
2378 ata_host_resume(host);
2379 return 0;
2380 }
2381 #endif
2382
2383
2384
2385 static struct of_device_id oxnas_sata_match[] = {
2386 {
2387 .compatible = "plxtech,nas782x-sata",
2388 },
2389 {},
2390 };
2391
2392 MODULE_DEVICE_TABLE(of, oxnas_sata_match);
2393
2394 static struct platform_driver oxnas_sata_driver = {
2395 .driver = {
2396 .name = "oxnas-sata",
2397 .owner = THIS_MODULE,
2398 .of_match_table = oxnas_sata_match,
2399 },
2400 .probe = sata_oxnas_probe,
2401 .remove = sata_oxnas_remove,
2402 #ifdef CONFIG_PM
2403 .suspend = sata_oxnas_suspend,
2404 .resume = sata_oxnas_resume,
2405 #endif
2406 };
2407
2408 module_platform_driver(oxnas_sata_driver);
2409
2410 MODULE_LICENSE("GPL");
2411 MODULE_VERSION("1.0");
2412 MODULE_AUTHOR("Oxford Semiconductor Ltd.");
2413 MODULE_DESCRIPTION("934 SATA core controler");
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