3 * A driver to interface the 934 based sata core present in the ox820
5 * based on sata_oxnas driver by Ma Haijun <mahaijuns@gmail.com>
6 * based on ox820 sata code by:
7 * Copyright (c) 2007 Oxford Semiconductor Ltd.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2, or (at your option)
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
20 #include <linux/ata.h>
21 #include <linux/libata.h>
22 #include <linux/of_platform.h>
23 #include <linux/delay.h>
24 #include <linux/module.h>
25 #include <linux/slab.h>
26 #include <linux/spinlock.h>
27 #include <linux/of_address.h>
28 #include <linux/of_irq.h>
29 #include <linux/clk.h>
30 #include <linux/reset.h>
33 #include <linux/sizes.h>
35 static inline void oxnas_register_clear_mask(void __iomem
*p
, unsigned mask
)
37 u32 val
= readl_relaxed(p
);
40 writel_relaxed(val
, p
);
43 static inline void oxnas_register_set_mask(void __iomem
*p
, unsigned mask
)
45 u32 val
= readl_relaxed(p
);
48 writel_relaxed(val
, p
);
51 static inline void oxnas_register_value_mask(void __iomem
*p
,
52 unsigned mask
, unsigned new_value
)
54 /* TODO sanity check mask & new_value = new_value */
55 u32 val
= readl_relaxed(p
);
59 writel_relaxed(val
, p
);
62 /* sgdma request structure */
63 struct sgdma_request
{
64 volatile u32 qualifier
;
68 } __packed
__aligned(4);
71 /* Controller information */
73 SATA_OXNAS_MAX_PRD
= 63,
74 SATA_OXNAS_DMA_SIZE
= SATA_OXNAS_MAX_PRD
*
75 sizeof(struct ata_bmdma_prd
) +
76 sizeof(struct sgdma_request
),
77 SATA_OXNAS_MAX_PORTS
= 2,
78 /** The different Oxsemi SATA core version numbers */
79 SATA_OXNAS_CORE_VERSION
= 0x1f3,
80 SATA_OXNAS_IRQ_FLAG
= IRQF_SHARED
,
81 SATA_OXNAS_HOST_FLAGS
= (ATA_FLAG_SATA
| ATA_FLAG_PIO_DMA
|
82 ATA_FLAG_NO_ATAPI
/*| ATA_FLAG_NCQ*/),
83 SATA_OXNAS_QUEUE_DEPTH
= 32,
85 SATA_OXNAS_DMA_BOUNDARY
= 0xFFFFFFFF,
93 /** sata host port register offsets */
111 DRIVE_CONTROL
= 0x6C,
112 /** These registers allow access to the link layer registers
113 that reside in a different clock domain to the processor bus */
126 /** sata port register bits */
129 * commands to issue in the master status to tell it to move shadow ,
130 * registers to the actual device ,
132 SATA_OPCODE_MASK
= 0x00000007,
133 CMD_WRITE_TO_ORB_REGS_NO_COMMAND
= 0x4,
134 CMD_WRITE_TO_ORB_REGS
= 0x2,
135 CMD_SYNC_ESCAPE
= 0x7,
136 CMD_CORE_BUSY
= (1 << 7),
137 CMD_DRIVE_SELECT_SHIFT
= 12,
138 CMD_DRIVE_SELECT_MASK
= (0xf << CMD_DRIVE_SELECT_SHIFT
),
140 /** interrupt bits */
141 INT_END_OF_CMD
= 1 << 0,
142 INT_LINK_SERROR
= 1 << 1,
144 INT_LINK_IRQ
= 1 << 3,
145 INT_REG_ACCESS_ERR
= 1 << 7,
146 INT_BIST_FIS
= 1 << 11,
147 INT_MASKABLE
= INT_END_OF_CMD
|
153 INT_WANT
= INT_END_OF_CMD
|
157 INT_ERRORS
= INT_LINK_SERROR
|
161 /** raw interrupt bits, unmaskable, but do not generate interrupts */
162 RAW_END_OF_CMD
= INT_END_OF_CMD
<< 16,
163 RAW_LINK_SERROR
= INT_LINK_SERROR
<< 16,
164 RAW_ERROR
= INT_ERROR
<< 16,
165 RAW_LINK_IRQ
= INT_LINK_IRQ
<< 16,
166 RAW_REG_ACCESS_ERR
= INT_REG_ACCESS_ERR
<< 16,
167 RAW_BIST_FIS
= INT_BIST_FIS
<< 16,
168 RAW_WANT
= INT_WANT
<< 16,
169 RAW_ERRORS
= INT_ERRORS
<< 16,
172 * variables to write to the device control register to set the current
173 * device, ie. master or slave.
178 SATA_CTL_ERR_MASK
= 0x00000016,
182 /* ATA SGDMA register offsets */
186 SGDMA_REQUESTPTR
= 0x8,
188 SGDMA_CORESIZE
= 0x10,
191 /* DMA controller register offsets */
196 DMA_CONTROL_RESET
= (1 << 12),
200 /* see DMA core docs for the values. Out means from memory (bus A) out
202 SGDMA_REQCTL0OUT
= 0x0497c03d,
203 /* burst mode disabled when no micro code used */
204 SGDMA_REQCTL0IN
= 0x0493a3c1,
205 SGDMA_REQCTL1OUT
= 0x0497c07d,
206 SGDMA_REQCTL1IN
= 0x0497a3c5,
207 SGDMA_CONTROL_NOGO
= 0x3e,
208 SGDMA_CONTROL_GO
= SGDMA_CONTROL_NOGO
| 1,
209 SGDMA_ERRORMASK
= 0x3f,
212 SGDMA_RESETS_CTRL
= 1 << 0,
213 SGDMA_RESETS_ARBT
= 1 << 1,
214 SGDMA_RESETS_AHB
= 1 << 2,
215 SGDMA_RESETS_ALL
= SGDMA_RESETS_CTRL
|
220 SGDMA_REQQUAL
= 0x00220001,
224 /** SATA core register offsets */
229 DATACOUNT_PORT0
= 0x010,
230 DATACOUNT_PORT1
= 0x014,
231 CORE_INT_STATUS
= 0x030,
232 CORE_INT_CLEAR
= 0x030,
233 CORE_INT_ENABLE
= 0x034,
234 CORE_INT_DISABLE
= 0x038,
235 CORE_REBUILD_ENABLE
= 0x050,
236 CORE_FAILED_PORT_R
= 0x054,
237 DEVICE_CONTROL
= 0x068,
239 RAID_SIZE_LOW
= 0x070,
240 RAID_SIZE_HIGH
= 0x074,
241 PORT_ERROR_MASK
= 0x078,
243 RAID_CONTROL
= 0x090,
244 DATA_PLANE_CTRL
= 0x0AC,
245 CORE_DATAPLANE_STAT
= 0x0b8,
250 UCODE_STORE
= 0x1000,
251 RAID_WP_BOT_LOW
= 0x1FF0,
252 RAID_WP_BOT_HIGH
= 0x1FF4,
253 RAID_WP_TOP_LOW
= 0x1FF8,
254 RAID_WP_TOP_HIGH
= 0x1FFC,
255 DATA_MUX_RAM0
= 0x8000,
256 DATA_MUX_RAM1
= 0xA000,
261 /* Sata core debug1 register bits */
262 CORE_PORT0_DATA_DIR_BIT
= 20,
263 CORE_PORT1_DATA_DIR_BIT
= 21,
264 CORE_PORT0_DATA_DIR
= 1 << CORE_PORT0_DATA_DIR_BIT
,
265 CORE_PORT1_DATA_DIR
= 1 << CORE_PORT1_DATA_DIR_BIT
,
267 /** sata core control register bits */
268 SCTL_CLR_ERR
= 0x00003016,
269 RAID_CLR_ERR
= 0x0000011e,
271 /* Interrupts direct from the ports */
272 NORMAL_INTS_WANTED
= 0x00000303,
274 /* shift these left by port number */
275 COREINT_HOST
= 0x00000001,
276 COREINT_END
= 0x00000100,
277 CORERAW_HOST
= COREINT_HOST
<< 16,
278 CORERAW_END
= COREINT_END
<< 16,
280 /* Interrupts from the RAID controller only */
281 RAID_INTS_WANTED
= 0x00008300,
283 /* The bits in the IDLE_STATUS that, when set indicate an idle core */
284 IDLE_CORES
= (1 << 18) | (1 << 19),
286 /* Data plane control error-mask mask and bit, these bit in the data
287 * plane control mask out errors from the ports that prevent the SGDMA
288 * care from sending an interrupt */
289 DPC_ERROR_MASK
= 0x00000300,
290 DPC_ERROR_MASK_BIT
= 0x00000100,
291 /* enable jbod micro-code */
292 DPC_JBOD_UCODE
= 1 << 0,
293 DPC_FIS_SWCH
= 1 << 1,
295 /** Device Control register bits */
296 DEVICE_CONTROL_DMABT
= 1 << 4,
297 DEVICE_CONTROL_ABORT
= 1 << 2,
298 DEVICE_CONTROL_PAD
= 1 << 3,
299 DEVICE_CONTROL_PADPAT
= 1 << 16,
300 DEVICE_CONTROL_PRTRST
= 1 << 8,
301 DEVICE_CONTROL_RAMRST
= 1 << 12,
302 DEVICE_CONTROL_ATA_ERR_OVERRIDE
= 1 << 28,
304 /** oxsemi HW raid modes */
305 OXNASSATA_NOTRAID
= 0,
308 /** OX820 specific HW-RAID register values */
312 CONFIG_IN_RESUME
= 2,
315 /* SATA PHY Registers */
322 STAT_READ_VALID
= (1 << 21),
323 STAT_CR_ACK
= (1 << 20),
324 STAT_CR_READ
= (1 << 19),
325 STAT_CR_WRITE
= (1 << 18),
326 STAT_CAP_DATA
= (1 << 17),
327 STAT_CAP_ADDR
= (1 << 16),
329 STAT_ACK_ANY
= STAT_CR_ACK
|
335 CR_READ_ENABLE
= (1 << 16),
336 CR_WRITE_ENABLE
= (1 << 17),
337 CR_CAP_DATA
= (1 << 18),
341 /* Link layer registers */
346 OXNAS_SATA_SOFTRESET
= 1,
347 OXNAS_SATA_REINIT
= 2,
351 OXNAS_SATA_UCODE_RAID0
,
352 OXNAS_SATA_UCODE_RAID1
,
353 OXNAS_SATA_UCODE_JBOD
,
354 OXNAS_SATA_UCODE_NONE
,
366 typedef irqreturn_t (*oxnas_sata_isr_callback_t
)(int, unsigned long, int);
368 struct sata_oxnas_host_priv
{
369 void __iomem
*port_base
;
370 void __iomem
*dmactl_base
;
371 void __iomem
*sgdma_base
;
372 void __iomem
*core_base
;
373 void __iomem
*phy_base
;
375 void __iomem
*dma_base_va
;
383 struct reset_control
*rst_sata
;
384 struct reset_control
*rst_link
;
385 struct reset_control
*rst_phy
;
387 spinlock_t core_lock
;
389 int reentrant_port_no
;
391 int direct_lock_count
;
393 int current_locker_type
;
394 int scsi_nonblocking_attempts
;
395 oxnas_sata_isr_callback_t isr_callback
;
397 wait_queue_head_t fast_wait_queue
;
398 wait_queue_head_t scsi_wait_queue
;
402 struct sata_oxnas_port_priv
{
403 void __iomem
*port_base
;
404 void __iomem
*dmactl_base
;
405 void __iomem
*sgdma_base
;
406 void __iomem
*core_base
;
407 struct sgdma_request
*sgdma_request
;
408 dma_addr_t sgdma_request_pa
;
411 static u8
sata_oxnas_check_status(struct ata_port
*ap
);
412 static int sata_oxnas_cleanup(struct ata_host
*ah
);
413 static void sata_oxnas_tf_load(struct ata_port
*ap
,
414 const struct ata_taskfile
*tf
);
415 static void sata_oxnas_irq_on(struct ata_port
*ap
);
416 static void sata_oxnas_post_reset_init(struct ata_port
*ap
);
418 static int sata_oxnas_acquire_hw(struct ata_port
*ap
, int may_sleep
,
419 int timeout_jiffies
);
420 static void sata_oxnas_release_hw(struct ata_port
*ap
);
422 static const void *HW_LOCKER_UID
= (void *)0xdeadbeef;
424 /***************************************************************************
426 ***************************************************************************/
427 static void wait_cr_ack(void __iomem
*phy_base
)
429 while ((ioread32(phy_base
+ PHY_STAT
) >> 16) & 0x1f)
430 ; /* wait for an ack bit to be set */
433 static u16
read_cr(void __iomem
*phy_base
, u16 address
)
435 iowrite32((u32
)address
, phy_base
+ PHY_STAT
);
436 wait_cr_ack(phy_base
);
437 iowrite32(CR_READ_ENABLE
, phy_base
+ PHY_DATA
);
438 wait_cr_ack(phy_base
);
439 return (u16
)ioread32(phy_base
+ PHY_STAT
);
442 static void write_cr(void __iomem
*phy_base
, u16 data
, u16 address
)
444 iowrite32((u32
)address
, phy_base
+ PHY_STAT
);
445 wait_cr_ack(phy_base
);
446 iowrite32((data
| CR_CAP_DATA
), phy_base
+ PHY_DATA
);
447 wait_cr_ack(phy_base
);
448 iowrite32(CR_WRITE_ENABLE
, phy_base
+ PHY_DATA
);
449 wait_cr_ack(phy_base
);
454 #define PH_GAIN_OFFSET 6
455 #define FR_GAIN_OFFSET 8
456 #define PH_GAIN_MASK (0x3 << PH_GAIN_OFFSET)
457 #define FR_GAIN_MASK (0x3 << FR_GAIN_OFFSET)
458 #define USE_INT_SETTING (1<<5)
460 void workaround5458(struct ata_host
*ah
)
462 struct sata_oxnas_host_priv
*hd
= ah
->private_data
;
463 void __iomem
*phy_base
= hd
->phy_base
;
467 for (i
= 0; i
< 2; i
++) {
468 rx_control
= read_cr(phy_base
, 0x201d + (i
<< 8));
469 rx_control
&= ~(PH_GAIN_MASK
| FR_GAIN_MASK
);
470 rx_control
|= PH_GAIN
<< PH_GAIN_OFFSET
;
471 rx_control
|= (FR_GAIN
<< FR_GAIN_OFFSET
) | USE_INT_SETTING
;
472 write_cr(phy_base
, rx_control
, 0x201d+(i
<<8));
477 * allows access to the link layer registers
478 * @param link_reg the link layer register to access (oxsemi indexing ie
479 * 00 = static config, 04 = phy ctrl)
481 void sata_oxnas_link_write(struct ata_port
*ap
, unsigned int link_reg
, u32 val
)
483 struct sata_oxnas_port_priv
*pd
= ap
->private_data
;
484 struct sata_oxnas_host_priv
*hd
= ap
->host
->private_data
;
485 void __iomem
*port_base
= pd
->port_base
;
489 DPRINTK("P%d [0x%02x]->0x%08x\n", ap
->port_no
, link_reg
, val
);
491 spin_lock_irqsave(&hd
->phy_lock
, flags
);
492 iowrite32(val
, port_base
+ LINK_DATA
);
494 /* accessed twice as a work around for a bug in the SATA abp bridge
495 * hardware (bug 6828) */
496 iowrite32(link_reg
, port_base
+ LINK_WR_ADDR
);
497 ioread32(port_base
+ LINK_WR_ADDR
);
499 for (patience
= 0x100000; patience
> 0; --patience
) {
500 if (ioread32(port_base
+ LINK_CONTROL
) & 0x00000001)
503 spin_unlock_irqrestore(&hd
->phy_lock
, flags
);
506 static int sata_oxnas_scr_write_port(struct ata_port
*ap
, unsigned int sc_reg
,
509 sata_oxnas_link_write(ap
, 0x20 + (sc_reg
* 4), val
);
513 static int sata_oxnas_scr_write(struct ata_link
*link
, unsigned int sc_reg
,
516 return sata_oxnas_scr_write_port(link
->ap
, sc_reg
, val
);
519 u32
sata_oxnas_link_read(struct ata_port
*ap
, unsigned int link_reg
)
521 struct sata_oxnas_port_priv
*pd
= ap
->private_data
;
522 struct sata_oxnas_host_priv
*hd
= ap
->host
->private_data
;
523 void __iomem
*port_base
= pd
->port_base
;
528 spin_lock_irqsave(&hd
->phy_lock
, flags
);
529 /* accessed twice as a work around for a bug in the SATA abp bridge
530 * hardware (bug 6828) */
531 iowrite32(link_reg
, port_base
+ LINK_RD_ADDR
);
532 ioread32(port_base
+ LINK_RD_ADDR
);
534 for (patience
= 0x100000; patience
> 0; --patience
) {
535 if (ioread32(port_base
+ LINK_CONTROL
) & 0x00000001)
539 DPRINTK("link read timed out for port %d\n", ap
->port_no
);
541 result
= ioread32(port_base
+ LINK_DATA
);
542 spin_unlock_irqrestore(&hd
->phy_lock
, flags
);
547 static int sata_oxnas_scr_read_port(struct ata_port
*ap
, unsigned int sc_reg
,
550 *val
= sata_oxnas_link_read(ap
, 0x20 + (sc_reg
*4));
554 static int sata_oxnas_scr_read(struct ata_link
*link
,
555 unsigned int sc_reg
, u32
*val
)
557 return sata_oxnas_scr_read_port(link
->ap
, sc_reg
, val
);
561 * sata_oxnas_irq_clear is called during probe just before the interrupt handler is
562 * registered, to be sure hardware is quiet. It clears and masks interrupt bits
565 * @param ap hardware with the registers in
567 static void sata_oxnas_irq_clear(struct ata_port
*ap
)
569 struct sata_oxnas_port_priv
*port_priv
= ap
->private_data
;
571 /* clear pending interrupts */
572 iowrite32(~0, port_priv
->port_base
+ INT_CLEAR
);
573 iowrite32(COREINT_END
, port_priv
->core_base
+ CORE_INT_CLEAR
);
577 * qc_issue is used to make a command active, once the hardware and S/G tables
578 * have been prepared. IDE BMDMA drivers use the helper function
579 * ata_qc_issue_prot() for taskfile protocol-based dispatch. More advanced
580 * drivers roll their own ->qc_issue implementation, using this as the
581 * "issue new ATA command to hardware" hook.
582 * @param qc the queued command to issue
584 static unsigned int sata_oxnas_qc_issue(struct ata_queued_cmd
*qc
)
586 struct sata_oxnas_port_priv
*pd
= qc
->ap
->private_data
;
587 struct sata_oxnas_host_priv
*hd
= qc
->ap
->host
->private_data
;
589 void __iomem
*port_base
= pd
->port_base
;
590 void __iomem
*core_base
= pd
->core_base
;
591 int port_no
= qc
->ap
->port_no
;
592 int no_microcode
= (hd
->current_ucode
== UNKNOWN_MODE
);
595 /* check the core is idle */
596 if (ioread32(port_base
+ SATA_COMMAND
) & CMD_CORE_BUSY
) {
599 DPRINTK("core busy for a command on port %d\n",
604 DPRINTK("core busy for a command on port %d\n",
606 /* CrazyDumpDebug(); */
607 sata_oxnas_cleanup(qc
->ap
->host
);
609 } while (ioread32(port_base
+ SATA_COMMAND
) & CMD_CORE_BUSY
);
612 /* enable passing of error signals to DMA sub-core by clearing the
614 reg
= ioread32(core_base
+ DATA_PLANE_CTRL
);
616 reg
|= (DPC_ERROR_MASK_BIT
| (DPC_ERROR_MASK_BIT
<< 1));
617 reg
&= ~(DPC_ERROR_MASK_BIT
<< port_no
);
618 iowrite32(reg
, core_base
+ DATA_PLANE_CTRL
);
620 /* Disable all interrupts for ports and RAID controller */
621 iowrite32(~0, port_base
+ INT_DISABLE
);
623 /* Disable all interrupts for core */
624 iowrite32(~0, core_base
+ CORE_INT_DISABLE
);
627 /* Load the command settings into the orb registers */
628 sata_oxnas_tf_load(qc
->ap
, &qc
->tf
);
630 /* both pio and dma commands use dma */
631 if (ata_is_dma(qc
->tf
.protocol
) || ata_is_pio(qc
->tf
.protocol
)) {
633 iowrite32(SGDMA_CONTROL_GO
, pd
->sgdma_base
+ SGDMA_CONTROL
);
637 /* enable End of command interrupt */
638 iowrite32(INT_WANT
, port_base
+ INT_ENABLE
);
639 iowrite32(COREINT_END
, core_base
+ CORE_INT_ENABLE
);
642 /* Start the command */
643 reg
= ioread32(port_base
+ SATA_COMMAND
);
644 reg
&= ~SATA_OPCODE_MASK
;
645 reg
|= CMD_WRITE_TO_ORB_REGS
;
646 iowrite32(reg
, port_base
+ SATA_COMMAND
);
653 * Will schedule the libATA error handler on the premise that there has
654 * been a hotplug event on the port specified
656 void sata_oxnas_checkforhotplug(struct ata_port
*ap
)
660 ata_ehi_hotplugged(&ap
->link
.eh_info
);
665 /**************************************************************************/
667 /**************************************************************************/
669 * The underlying function that controls access to the sata core
671 * @return non-zero indicates that you have acquired exclusive access to the
674 static int __acquire_sata_core(
677 oxnas_sata_isr_callback_t callback
,
685 unsigned long end
= jiffies
+ timeout_jiffies
;
689 struct sata_oxnas_host_priv
*hd
;
696 hd
= ah
->private_data
;
698 spin_lock_irqsave(&hd
->core_lock
, flags
);
700 DPRINTK("Entered uid %p, port %d, h/w count %d, d count %d, "
701 "callback %p, hw_access %d, core_locked %d, "
702 "reentrant_port_no %d, isr_callback %p\n",
703 uid
, port_no
, hd
->hw_lock_count
, hd
->direct_lock_count
,
704 callback
, hw_access
, hd
->core_locked
, hd
->reentrant_port_no
,
708 if (hd
->core_locked
||
709 (!hw_access
&& hd
->scsi_nonblocking_attempts
)) {
710 /* Can only allow access if from SCSI/SATA stack and if
711 * reentrant access is allowed and this access is to the
712 * same port for which the lock is current held
714 if (hw_access
&& (port_no
== hd
->reentrant_port_no
)) {
715 BUG_ON(!hd
->hw_lock_count
);
716 ++(hd
->hw_lock_count
);
718 DPRINTK("Allow SCSI/SATA re-entrant access to "
719 "uid %p port %d\n", uid
, port_no
);
722 } else if (!hw_access
) {
723 if ((locker_type
== SATA_READER
) &&
724 (hd
->current_locker_type
== SATA_READER
)) {
726 "Already locked by reader, "
727 "uid %p, locker_uid %p, "
728 "port %d, h/w count %d, "
729 "d count %d, hw_access %d\n",
730 uid
, hd
->locker_uid
, port_no
,
732 hd
->direct_lock_count
,
737 if ((locker_type
!= SATA_READER
) &&
738 (locker_type
!= SATA_WRITER
)) {
743 WARN(uid
== hd
->locker_uid
, "Attempt to lock "
744 "by locker type %d uid %p, already "
745 "locked by locker type %d with "
746 "locker_uid %p, port %d, "
747 "h/w count %d, d count %d, "
748 "hw_access %d\n", locker_type
, uid
,
749 hd
->current_locker_type
,
750 hd
->locker_uid
, port_no
,
752 hd
->direct_lock_count
, hw_access
);
755 WARN(hd
->hw_lock_count
|| hd
->direct_lock_count
,
756 "Core unlocked but counts non-zero: uid %p, "
757 "locker_uid %p, port %d, h/w count %d, "
758 "d count %d, hw_access %d\n", uid
,
759 hd
->locker_uid
, port_no
, hd
->hw_lock_count
,
760 hd
->direct_lock_count
, hw_access
);
762 BUG_ON(hd
->current_locker_type
!= SATA_UNLOCKED
);
764 WARN(hd
->locker_uid
, "Attempt to lock uid %p when "
765 "locker_uid %p is non-zero, port %d, "
766 "h/w count %d, d count %d, hw_access %d\n",
767 uid
, hd
->locker_uid
, port_no
, hd
->hw_lock_count
,
768 hd
->direct_lock_count
, hw_access
);
771 /* Direct access attempting to acquire
774 /* Must have callback for direct access */
776 /* Sanity check lock state */
777 BUG_ON(hd
->reentrant_port_no
!= -1);
779 hd
->isr_callback
= callback
;
781 ++(hd
->direct_lock_count
);
783 hd
->current_locker_type
= locker_type
;
785 /* SCSI/SATA attempting to acquire
788 /* No callbacks for SCSI/SATA access */
790 /* No callback args for SCSI/SATA access */
793 /* Sanity check lock state */
794 BUG_ON(hd
->isr_callback
);
797 ++(hd
->hw_lock_count
);
798 hd
->reentrant_port_no
= port_no
;
800 hd
->current_locker_type
= SATA_SCSI_STACK
;
804 hd
->locker_uid
= uid
;
811 DPRINTK("Denying for uid %p locker_type %d, "
812 "hw_access %d, port %d, current_locker_type %d as "
813 "cannot sleep\n", uid
, locker_type
, hw_access
, port_no
,
814 hd
->current_locker_type
);
817 ++(hd
->scsi_nonblocking_attempts
);
822 /* Core is locked and we're allowed to sleep, so wait to be
823 * awoken when the core is unlocked
826 prepare_to_wait(hw_access
? &hd
->scsi_wait_queue
:
827 &hd
->fast_wait_queue
,
828 &wait
, TASK_UNINTERRUPTIBLE
);
829 if (!hd
->core_locked
&&
830 !(!hw_access
&& hd
->scsi_nonblocking_attempts
)) {
831 /* We're going to use variables that will have
832 * been changed by the waker prior to clearing
833 * core_locked so we need to ensure we see
834 * changes to all those variables
839 if (time_after(jiffies
, end
)) {
840 printk(KERN_WARNING
"__acquire_sata_core() "
841 "uid %p failing for port %d timed out, "
842 "locker_uid %p, h/w count %d, "
843 "d count %d, callback %p, hw_access %d, "
844 "core_locked %d, reentrant_port_no %d, "
845 "isr_callback %p, isr_arg %p\n", uid
,
846 port_no
, hd
->locker_uid
,
848 hd
->direct_lock_count
, callback
,
849 hw_access
, hd
->core_locked
,
850 hd
->reentrant_port_no
, hd
->isr_callback
,
855 spin_unlock_irqrestore(&hd
->core_lock
, flags
);
856 if (!schedule_timeout(4*HZ
)) {
857 printk(KERN_INFO
"__acquire_sata_core() uid %p, "
858 "locker_uid %p, timed-out of "
859 "schedule(), checking overall timeout\n",
860 uid
, hd
->locker_uid
);
862 spin_lock_irqsave(&hd
->core_lock
, flags
);
864 finish_wait(hw_access
? &hd
->scsi_wait_queue
:
865 &hd
->fast_wait_queue
, &wait
);
868 if (hw_access
&& acquired
) {
869 if (hd
->scsi_nonblocking_attempts
)
870 hd
->scsi_nonblocking_attempts
= 0;
872 /* Wake any other SCSI/SATA waiters so they can get reentrant
873 * access to the same port if appropriate. This is because if
874 * the SATA core is locked by fast access, or SCSI/SATA access
875 * to other port, then can have >1 SCSI/SATA waiters on the wait
876 * list so want to give reentrant accessors a chance to get
879 if (!list_empty(&hd
->scsi_wait_queue
.head
))
880 wake_up(&hd
->scsi_wait_queue
);
883 DPRINTK("Leaving uid %p with acquired = %d, port %d, callback %p\n",
884 uid
, acquired
, port_no
, callback
);
886 spin_unlock_irqrestore(&hd
->core_lock
, flags
);
891 int sata_core_has_fast_waiters(struct ata_host
*ah
)
895 struct sata_oxnas_host_priv
*hd
= ah
->private_data
;
897 spin_lock_irqsave(&hd
->core_lock
, flags
);
898 has_waiters
= !list_empty(&hd
->fast_wait_queue
.head
);
899 spin_unlock_irqrestore(&hd
->core_lock
, flags
);
903 EXPORT_SYMBOL(sata_core_has_fast_waiters
);
905 int sata_core_has_scsi_waiters(struct ata_host
*ah
)
909 struct sata_oxnas_host_priv
*hd
= ah
->private_data
;
911 spin_lock_irqsave(&hd
->core_lock
, flags
);
912 has_waiters
= hd
->scsi_nonblocking_attempts
||
913 !list_empty(&hd
->scsi_wait_queue
.head
);
914 spin_unlock_irqrestore(&hd
->core_lock
, flags
);
918 EXPORT_SYMBOL(sata_core_has_scsi_waiters
);
921 * ata_port operation to gain ownership of the SATA hardware prior to issuing
922 * a command against a SATA host. Allows any number of users of the port against
923 * which the lock was first acquired, thus enforcing that only one SATA core
924 * port may be operated on at once.
926 static int sata_oxnas_acquire_hw(
931 return __acquire_sata_core(ap
->host
, ap
->port_no
, NULL
, 0, may_sleep
,
932 timeout_jiffies
, 1, (void *)HW_LOCKER_UID
,
937 * operation to release ownership of the SATA hardware
939 static void sata_oxnas_release_hw(struct ata_port
*ap
)
943 struct sata_oxnas_host_priv
*hd
= ap
->host
->private_data
;
945 spin_lock_irqsave(&hd
->core_lock
, flags
);
947 DPRINTK("Entered port_no = %d, h/w count %d, d count %d, "
948 "core locked = %d, reentrant_port_no = %d, isr_callback %p\n",
949 ap
->port_no
, hd
->hw_lock_count
, hd
->direct_lock_count
,
950 hd
->core_locked
, hd
->reentrant_port_no
, hd
->isr_callback
);
952 if (!hd
->core_locked
) {
953 /* Nobody holds the SATA lock */
954 printk(KERN_WARNING
"Nobody holds SATA lock, port_no %d\n",
957 } else if (!hd
->hw_lock_count
) {
958 /* SCSI/SATA has released without holding the lock */
959 printk(KERN_WARNING
"SCSI/SATA does not hold SATA lock, "
960 "port_no %d\n", ap
->port_no
);
962 /* Trap incorrect usage */
963 BUG_ON(hd
->reentrant_port_no
== -1);
964 BUG_ON(ap
->port_no
!= hd
->reentrant_port_no
);
965 BUG_ON(hd
->direct_lock_count
);
966 BUG_ON(hd
->current_locker_type
!= SATA_SCSI_STACK
);
968 WARN(!hd
->locker_uid
|| (hd
->locker_uid
!= HW_LOCKER_UID
),
969 "Invalid locker uid %p, h/w count %d, d count %d, "
970 "reentrant_port_no %d, core_locked %d, "
971 "isr_callback %p\n", hd
->locker_uid
, hd
->hw_lock_count
,
972 hd
->direct_lock_count
, hd
->reentrant_port_no
,
973 hd
->core_locked
, hd
->isr_callback
);
975 if (--(hd
->hw_lock_count
)) {
976 DPRINTK("Still nested port_no %d\n", ap
->port_no
);
978 DPRINTK("Release port_no %d\n", ap
->port_no
);
979 hd
->reentrant_port_no
= -1;
980 hd
->isr_callback
= NULL
;
981 hd
->current_locker_type
= SATA_UNLOCKED
;
985 wake_up(!list_empty(&hd
->scsi_wait_queue
.head
) ?
986 &hd
->scsi_wait_queue
:
987 &hd
->fast_wait_queue
);
991 DPRINTK("Leaving, port_no %d, count %d\n", ap
->port_no
,
994 spin_unlock_irqrestore(&hd
->core_lock
, flags
);
996 /* CONFIG_SATA_OX820_DIRECT_HWRAID */
998 ox820hwraid_restart_queue();
1002 static inline int sata_oxnas_is_host_frozen(struct ata_host
*ah
)
1004 struct sata_oxnas_host_priv
*hd
= ah
->private_data
;
1007 return hd
->port_in_eh
|| hd
->port_frozen
;
1011 static inline u32
sata_oxnas_hostportbusy(struct ata_port
*ap
)
1013 struct sata_oxnas_host_priv
*hd
= ap
->host
->private_data
;
1015 return (ioread32(hd
->port_base
+ SATA_COMMAND
) & CMD_CORE_BUSY
) ||
1017 (ioread32(hd
->port_base
+ PORT_SIZE
+ SATA_COMMAND
) &
1021 static inline u32
sata_oxnas_hostdmabusy(struct ata_port
*ap
)
1023 struct sata_oxnas_port_priv
*pd
= ap
->private_data
;
1025 return ioread32(pd
->sgdma_base
+ SGDMA_STATUS
) & SGDMA_BUSY
;
1030 * Turns on the cores clock and resets it
1032 static void sata_oxnas_reset_core(struct ata_host
*ah
)
1034 struct sata_oxnas_host_priv
*host_priv
= ah
->private_data
;
1038 clk_prepare_enable(host_priv
->clk
);
1040 reset_control_assert(host_priv
->rst_sata
);
1041 reset_control_assert(host_priv
->rst_link
);
1042 reset_control_assert(host_priv
->rst_phy
);
1046 /* un-reset the PHY, then Link and Controller */
1047 reset_control_deassert(host_priv
->rst_phy
);
1050 reset_control_deassert(host_priv
->rst_sata
);
1051 reset_control_deassert(host_priv
->rst_link
);
1055 /* tune for sata compatibility */
1056 sata_oxnas_link_write(ah
->ports
[0], 0x60, 0x2988);
1058 for (n
= 0; n
< host_priv
->n_ports
; n
++) {
1059 /* each port in turn */
1060 sata_oxnas_link_write(ah
->ports
[n
], 0x70, 0x55629);
1067 * Called after an identify device command has worked out what kind of device
1070 * @param port The port to configure
1071 * @param pdev The hardware associated with controlling the port
1073 static void sata_oxnas_dev_config(struct ata_device
*pdev
)
1075 struct sata_oxnas_port_priv
*pd
= pdev
->link
->ap
->private_data
;
1076 void __iomem
*port_base
= pd
->port_base
;
1080 /* Set the bits to put the port into 28 or 48-bit node */
1081 reg
= ioread32(port_base
+ DRIVE_CONTROL
);
1083 reg
|= (pdev
->flags
& ATA_DFLAG_LBA48
) ? DR_CON_48
: DR_CON_28
;
1084 iowrite32(reg
, port_base
+ DRIVE_CONTROL
);
1086 /* if this is an ATA-6 disk, put port into ATA-5 auto translate mode */
1087 if (pdev
->flags
& ATA_DFLAG_LBA48
) {
1088 reg
= ioread32(port_base
+ PORT_CONTROL
);
1090 iowrite32(reg
, port_base
+ PORT_CONTROL
);
1094 * called to write a taskfile into the ORB registers
1095 * @param ap hardware with the registers in
1096 * @param tf taskfile to write to the registers
1098 static void sata_oxnas_tf_load(struct ata_port
*ap
,
1099 const struct ata_taskfile
*tf
)
1108 struct sata_oxnas_port_priv
*port_priv
= ap
->private_data
;
1109 void __iomem
*port_base
= port_priv
->port_base
;
1110 unsigned int is_addr
= tf
->flags
& ATA_TFLAG_ISADDR
;
1112 /* wait a maximum of 10ms for the core to be idle */
1114 Command_Reg
= ioread32(port_base
+ SATA_COMMAND
);
1115 if (!(Command_Reg
& CMD_CORE_BUSY
))
1119 } while (count
< 200);
1121 /* check if the ctl register has interrupts disabled or enabled and
1122 * modify the interrupt enable registers on the ata core as required */
1123 if (tf
->ctl
& ATA_NIEN
) {
1124 /* interrupts disabled */
1125 u32 mask
= (COREINT_END
<< ap
->port_no
);
1127 iowrite32(mask
, port_priv
->core_base
+ CORE_INT_DISABLE
);
1128 sata_oxnas_irq_clear(ap
);
1130 sata_oxnas_irq_on(ap
);
1133 Orb2
|= (tf
->command
) << 24;
1135 /* write 48 or 28 bit tf parameters */
1137 /* set LBA bit as it's an address */
1138 Orb1
|= (tf
->device
& ATA_LBA
) << 24;
1140 if (tf
->flags
& ATA_TFLAG_LBA48
) {
1141 Orb1
|= ATA_LBA
<< 24;
1142 Orb2
|= (tf
->hob_nsect
) << 8;
1143 Orb3
|= (tf
->hob_lbal
) << 24;
1144 Orb4
|= (tf
->hob_lbam
) << 0;
1145 Orb4
|= (tf
->hob_lbah
) << 8;
1146 Orb4
|= (tf
->hob_feature
) << 16;
1148 Orb3
|= (tf
->device
& 0xf) << 24;
1151 /* write 28-bit lba */
1152 Orb2
|= (tf
->nsect
) << 0;
1153 Orb2
|= (tf
->feature
) << 16;
1154 Orb3
|= (tf
->lbal
) << 0;
1155 Orb3
|= (tf
->lbam
) << 8;
1156 Orb3
|= (tf
->lbah
) << 16;
1157 Orb4
|= (tf
->ctl
) << 24;
1160 if (tf
->flags
& ATA_TFLAG_DEVICE
)
1161 Orb1
|= (tf
->device
) << 24;
1163 ap
->last_ctl
= tf
->ctl
;
1165 /* write values to registers */
1166 iowrite32(Orb1
, port_base
+ ORB1
);
1167 iowrite32(Orb2
, port_base
+ ORB2
);
1168 iowrite32(Orb3
, port_base
+ ORB3
);
1169 iowrite32(Orb4
, port_base
+ ORB4
);
1173 void sata_oxnas_set_mode(struct ata_host
*ah
, u32 mode
, u32 force
)
1175 struct sata_oxnas_host_priv
*host_priv
= ah
->private_data
;
1176 void __iomem
*core_base
= host_priv
->core_base
;
1180 unsigned int progmicrocode
= 0;
1181 unsigned int changeparameters
= 0;
1185 /* these micro-code programs _should_ include the version word */
1188 static const unsigned int jbod
[] = {
1189 0x07B400AC, 0x0228A280, 0x00200001, 0x00204002, 0x00224001,
1190 0x00EE0009, 0x00724901, 0x01A24903, 0x00E40009, 0x00224001,
1191 0x00621120, 0x0183C908, 0x00E20005, 0x00718908, 0x0198A206,
1192 0x00621124, 0x0183C908, 0x00E20046, 0x00621104, 0x0183C908,
1193 0x00E20015, 0x00EE009D, 0x01A3E301, 0x00E2001B, 0x0183C900,
1194 0x00E2001B, 0x00210001, 0x00EE0020, 0x01A3E302, 0x00E2009D,
1195 0x0183C901, 0x00E2009D, 0x00210002, 0x0235D700, 0x0208A204,
1196 0x0071C908, 0x000F8207, 0x000FC207, 0x0071C920, 0x000F8507,
1197 0x000FC507, 0x0228A240, 0x02269A40, 0x00094004, 0x00621104,
1198 0x0180C908, 0x00E40031, 0x00621112, 0x01A3C801, 0x00E2002B,
1199 0x00294000, 0x0228A220, 0x01A69ABF, 0x002F8000, 0x002FC000,
1200 0x0198A204, 0x0001C022, 0x01B1A220, 0x0001C106, 0x00088007,
1201 0x0183C903, 0x00E2009D, 0x0228A220, 0x0071890C, 0x0208A206,
1202 0x0198A206, 0x0001C022, 0x01B1A220, 0x0001C106, 0x00088007,
1203 0x00EE009D, 0x00621104, 0x0183C908, 0x00E2004A, 0x00EE009D,
1204 0x01A3C901, 0x00E20050, 0x0021E7FF, 0x0183E007, 0x00E2009D,
1205 0x00EE0054, 0x0061600B, 0x0021E7FF, 0x0183C507, 0x00E2009D,
1206 0x01A3E301, 0x00E2005A, 0x0183C900, 0x00E2005A, 0x00210001,
1207 0x00EE005F, 0x01A3E302, 0x00E20005, 0x0183C901, 0x00E20005,
1208 0x00210002, 0x0235D700, 0x0208A204, 0x000F8109, 0x000FC109,
1209 0x0071C918, 0x000F8407, 0x000FC407, 0x0001C022, 0x01A1A2BF,
1210 0x0001C106, 0x00088007, 0x02269A40, 0x00094004, 0x00621112,
1211 0x01A3C801, 0x00E4007F, 0x00621104, 0x0180C908, 0x00E4008D,
1212 0x00621128, 0x0183C908, 0x00E2006C, 0x01A3C901, 0x00E2007B,
1213 0x0021E7FF, 0x0183E007, 0x00E2007F, 0x00EE006C, 0x0061600B,
1214 0x0021E7FF, 0x0183C507, 0x00E4006C, 0x00621111, 0x01A3C801,
1215 0x00E2007F, 0x00621110, 0x01A3C801, 0x00E20082, 0x0228A220,
1216 0x00621119, 0x01A3C801, 0x00E20086, 0x0001C022, 0x01B1A220,
1217 0x0001C106, 0x00088007, 0x0198A204, 0x00294000, 0x01A69ABF,
1218 0x002F8000, 0x002FC000, 0x0183C903, 0x00E20005, 0x0228A220,
1219 0x0071890C, 0x0208A206, 0x0198A206, 0x0001C022, 0x01B1A220,
1220 0x0001C106, 0x00088007, 0x00EE009D, 0x00621128, 0x0183C908,
1221 0x00E20005, 0x00621104, 0x0183C908, 0x00E200A6, 0x0062111C,
1222 0x0183C908, 0x00E20005, 0x0071890C, 0x0208A206, 0x0198A206,
1223 0x00718908, 0x0208A206, 0x00EE0005, ~0
1226 /* Bi-Modal RAID-0/1 */
1227 static const unsigned int raid
[] = {
1228 0x00F20145, 0x00EE20FA, 0x00EE20A7, 0x0001C009, 0x00EE0004,
1229 0x00220000, 0x0001000B, 0x037003FF, 0x00700018, 0x037003FE,
1230 0x037043FD, 0x00704118, 0x037043FC, 0x01A3D240, 0x00E20017,
1231 0x00B3C235, 0x00E40018, 0x0093C104, 0x00E80014, 0x0093C004,
1232 0x00E80017, 0x01020000, 0x00274020, 0x00EE0083, 0x0080C904,
1233 0x0093C104, 0x00EA0020, 0x0093C103, 0x00EC001F, 0x00220002,
1234 0x00924104, 0x0005C009, 0x00EE0058, 0x0093CF04, 0x00E80026,
1235 0x00900F01, 0x00600001, 0x00910400, 0x00EE0058, 0x00601604,
1236 0x01A00003, 0x00E2002C, 0x01018000, 0x00274040, 0x00EE0083,
1237 0x0093CF03, 0x00EC0031, 0x00220003, 0x00924F04, 0x0005C009,
1238 0x00810104, 0x00B3C235, 0x00E20037, 0x0022C000, 0x00218210,
1239 0x00EE0039, 0x0022C001, 0x00218200, 0x00600401, 0x00A04901,
1240 0x00604101, 0x01A0C401, 0x00E20040, 0x00216202, 0x00EE0041,
1241 0x00216101, 0x02018506, 0x00EE2141, 0x00904901, 0x00E20049,
1242 0x00A00401, 0x00600001, 0x02E0C301, 0x00EE2141, 0x00216303,
1243 0x037003EE, 0x01A3C001, 0x00E40105, 0x00250080, 0x00204000,
1244 0x002042F1, 0x0004C001, 0x00230001, 0x00100006, 0x02C18605,
1245 0x00100006, 0x01A3D502, 0x00E20055, 0x00EE0053, 0x00004009,
1246 0x00000004, 0x00B3C235, 0x00E40062, 0x0022C001, 0x0020C000,
1247 0x00EE2141, 0x0020C001, 0x00EE2141, 0x00EE006B, 0x0022C000,
1248 0x0060D207, 0x00EE2141, 0x00B3C242, 0x00E20069, 0x01A3D601,
1249 0x00E2006E, 0x02E0C301, 0x00EE2141, 0x00230001, 0x00301303,
1250 0x00EE007B, 0x00218210, 0x01A3C301, 0x00E20073, 0x00216202,
1251 0x00EE0074, 0x00216101, 0x02018506, 0x00214000, 0x037003EE,
1252 0x01A3C001, 0x00E40108, 0x00230001, 0x00100006, 0x00250080,
1253 0x00204000, 0x002042F1, 0x0004C001, 0x00EE007F, 0x0024C000,
1254 0x01A3D1F0, 0x00E20088, 0x00230001, 0x00300000, 0x01A3D202,
1255 0x00E20085, 0x00EE00A5, 0x00B3C800, 0x00E20096, 0x00218000,
1256 0x00924709, 0x0005C009, 0x00B20802, 0x00E40093, 0x037103FD,
1257 0x00710418, 0x037103FC, 0x00EE0006, 0x00220000, 0x0001000F,
1258 0x00EE0006, 0x00800B0C, 0x00B00001, 0x00204000, 0x00208550,
1259 0x00208440, 0x002083E0, 0x00208200, 0x00208100, 0x01008000,
1260 0x037083EE, 0x02008212, 0x02008216, 0x01A3C201, 0x00E400A5,
1261 0x0100C000, 0x00EE20FA, 0x02800000, 0x00208000, 0x00B24C00,
1262 0x00E400AD, 0x00224001, 0x00724910, 0x0005C009, 0x00B3CDC4,
1263 0x00E200D5, 0x00B3CD29, 0x00E200D5, 0x00B3CD20, 0x00E200D5,
1264 0x00B3CD24, 0x00E200D5, 0x00B3CDC5, 0x00E200D2, 0x00B3CD39,
1265 0x00E200D2, 0x00B3CD30, 0x00E200D2, 0x00B3CD34, 0x00E200D2,
1266 0x00B3CDCA, 0x00E200CF, 0x00B3CD35, 0x00E200CF, 0x00B3CDC8,
1267 0x00E200CC, 0x00B3CD25, 0x00E200CC, 0x00B3CD40, 0x00E200CB,
1268 0x00B3CD42, 0x00E200CB, 0x01018000, 0x00EE0083, 0x0025C000,
1269 0x036083EE, 0x0000800D, 0x00EE00D8, 0x036083EE, 0x00208035,
1270 0x00EE00DA, 0x036083EE, 0x00208035, 0x00EE00DA, 0x00208007,
1271 0x036083EE, 0x00208025, 0x036083EF, 0x02400000, 0x01A3D208,
1272 0x00E200D8, 0x0067120A, 0x0021C000, 0x0021C224, 0x00220000,
1273 0x00404B1C, 0x00600105, 0x00800007, 0x0020C00E, 0x00214000,
1274 0x01004000, 0x01A0411F, 0x00404E01, 0x01A3C101, 0x00E200F1,
1275 0x00B20800, 0x00E400D8, 0x00220001, 0x0080490B, 0x00B04101,
1276 0x0040411C, 0x00EE00E1, 0x02269A01, 0x01020000, 0x02275D80,
1277 0x01A3D202, 0x00E200F4, 0x01B75D80, 0x01030000, 0x01B69A01,
1278 0x00EE00D8, 0x01A3D204, 0x00E40104, 0x00224000, 0x0020C00E,
1279 0x0020001E, 0x00214000, 0x01004000, 0x0212490E, 0x00214001,
1280 0x01004000, 0x02400000, 0x00B3D702, 0x00E80112, 0x00EE010E,
1281 0x00B3D702, 0x00E80112, 0x00B3D702, 0x00E4010E, 0x00230001,
1282 0x00EE0140, 0x00200005, 0x036003EE, 0x00204001, 0x00EE0116,
1283 0x00230001, 0x00100006, 0x02C18605, 0x00100006, 0x01A3D1F0,
1284 0x00E40083, 0x037003EE, 0x01A3C002, 0x00E20121, 0x0020A300,
1285 0x0183D102, 0x00E20124, 0x037003EE, 0x01A00005, 0x036003EE,
1286 0x01A0910F, 0x00B3C20F, 0x00E2012F, 0x01A3D502, 0x00E20116,
1287 0x01A3C002, 0x00E20116, 0x00B3D702, 0x00E4012C, 0x00300000,
1288 0x00EE011F, 0x02C18605, 0x00100006, 0x00EE0116, 0x01A3D1F0,
1289 0x00E40083, 0x037003EE, 0x01A3C004, 0x00E20088, 0x00200003,
1290 0x036003EE, 0x01A3D502, 0x00E20136, 0x00230001, 0x00B3C101,
1291 0x00E4012C, 0x00100006, 0x02C18605, 0x00100006, 0x00204000,
1292 0x00EE0116, 0x00100006, 0x01A3D1F0, 0x00E40083, 0x01000000,
1296 DPRINTK("ENTER: mode:%d, force:%d\n", mode
, force
);
1299 previous_mode
= UNKNOWN_MODE
;
1301 previous_mode
= host_priv
->current_ucode
;
1303 if (mode
== previous_mode
)
1306 host_priv
->current_ucode
= mode
;
1308 /* decide what needs to be done using the STD in my logbook */
1309 switch (previous_mode
) {
1310 case OXNASSATA_RAID1
:
1312 case OXNASSATA_RAID0
:
1313 changeparameters
= 1;
1315 case OXNASSATA_NOTRAID
:
1316 changeparameters
= 1;
1321 case OXNASSATA_RAID0
:
1323 case OXNASSATA_RAID1
:
1324 changeparameters
= 1;
1326 case OXNASSATA_NOTRAID
:
1327 changeparameters
= 1;
1332 case OXNASSATA_NOTRAID
:
1334 case OXNASSATA_RAID0
:
1335 case OXNASSATA_RAID1
:
1336 changeparameters
= 1;
1342 changeparameters
= 1;
1347 /* no need to reprogram everything if already in the right mode */
1348 if (progmicrocode
) {
1349 /* reset micro-code processor */
1350 iowrite32(1, core_base
+ PROC_RESET
);
1353 /* select micro-code */
1355 case OXNASSATA_RAID1
:
1356 case OXNASSATA_RAID0
:
1357 VPRINTK("Loading RAID micro-code\n");
1358 src
= (unsigned int *)&raid
[1];
1360 case OXNASSATA_NOTRAID
:
1361 VPRINTK("Loading JBOD micro-code\n");
1362 src
= (unsigned int *)&jbod
[1];
1369 /* load micro code */
1370 dst
= core_base
+ UCODE_STORE
;
1371 while (*src
!= ~0) {
1372 iowrite32(*src
, dst
);
1374 dst
+= sizeof(*src
);
1379 if (changeparameters
) {
1381 /* set other mode dependent flags */
1383 case OXNASSATA_RAID1
:
1384 /* clear JBOD mode */
1385 reg
= ioread32(core_base
+ DATA_PLANE_CTRL
);
1386 reg
|= DPC_JBOD_UCODE
;
1387 reg
&= ~DPC_FIS_SWCH
;
1388 iowrite32(reg
, core_base
+ DATA_PLANE_CTRL
);
1391 /* set the hardware up for RAID-1 */
1392 iowrite32(0, core_base
+ RAID_WP_BOT_LOW
);
1393 iowrite32(0, core_base
+ RAID_WP_BOT_HIGH
);
1394 iowrite32(0xffffffff, core_base
+ RAID_WP_TOP_LOW
);
1395 iowrite32(0x7fffffff, core_base
+ RAID_WP_TOP_HIGH
);
1396 iowrite32(0, core_base
+ RAID_SIZE_LOW
);
1397 iowrite32(0, core_base
+ RAID_SIZE_HIGH
);
1400 case OXNASSATA_RAID0
:
1401 /* clear JBOD mode */
1402 reg
= ioread32(core_base
+ DATA_PLANE_CTRL
);
1403 reg
|= DPC_JBOD_UCODE
;
1404 reg
&= ~DPC_FIS_SWCH
;
1405 iowrite32(reg
, core_base
+ DATA_PLANE_CTRL
);
1408 /* set the hardware up for RAID-1 */
1409 iowrite32(0, core_base
+ RAID_WP_BOT_LOW
);
1410 iowrite32(0, core_base
+ RAID_WP_BOT_HIGH
);
1411 iowrite32(0xffffffff, core_base
+ RAID_WP_TOP_LOW
);
1412 iowrite32(0x7fffffff, core_base
+ RAID_WP_TOP_HIGH
);
1413 iowrite32(0xffffffff, core_base
+ RAID_SIZE_LOW
);
1414 iowrite32(0x7fffffff, core_base
+ RAID_SIZE_HIGH
);
1417 case OXNASSATA_NOTRAID
:
1418 /* enable jbod mode */
1419 reg
= ioread32(core_base
+ DATA_PLANE_CTRL
);
1420 reg
&= ~DPC_JBOD_UCODE
;
1421 reg
&= ~DPC_FIS_SWCH
;
1422 iowrite32(reg
, core_base
+ DATA_PLANE_CTRL
);
1425 /* start micro-code processor*/
1426 iowrite32(1, core_base
+ PROC_START
);
1429 reg
= ioread32(core_base
+ DATA_PLANE_CTRL
);
1430 reg
|= DPC_JBOD_UCODE
;
1431 reg
&= ~DPC_FIS_SWCH
;
1432 iowrite32(reg
, core_base
+ DATA_PLANE_CTRL
);
1440 * sends a sync-escape if there is a link present
1442 static inline void sata_oxnas_send_sync_escape(struct ata_port
*ap
)
1444 struct sata_oxnas_port_priv
*pd
= ap
->private_data
;
1447 /* read the SSTATUS register and only send a sync escape if there is a
1449 if ((sata_oxnas_link_read(ap
, 0x20) & 3) == 3) {
1450 reg
= ioread32(pd
->port_base
+ SATA_COMMAND
);
1451 reg
&= ~SATA_OPCODE_MASK
;
1452 reg
|= CMD_SYNC_ESCAPE
;
1453 iowrite32(reg
, pd
->port_base
+ SATA_COMMAND
);
1458 static inline void sata_oxnas_clear_CS_error(struct ata_port
*ap
)
1460 struct sata_oxnas_port_priv
*pd
= ap
->private_data
;
1461 u32
*base
= pd
->port_base
;
1464 reg
= ioread32(base
+ SATA_CONTROL
);
1465 reg
&= SATA_CTL_ERR_MASK
;
1466 iowrite32(reg
, base
+ SATA_CONTROL
);
1469 static inline void sata_oxnas_reset_sgdma(struct ata_port
*ap
)
1471 struct sata_oxnas_port_priv
*pd
= ap
->private_data
;
1473 iowrite32(SGDMA_RESETS_CTRL
, pd
->sgdma_base
+ SGDMA_RESETS
);
1476 static inline void sata_oxnas_reset_dma(struct ata_port
*ap
, int assert)
1478 struct sata_oxnas_port_priv
*pd
= ap
->private_data
;
1481 reg
= ioread32(pd
->dmactl_base
+ DMA_CONTROL
);
1483 reg
|= DMA_CONTROL_RESET
;
1485 reg
&= ~DMA_CONTROL_RESET
;
1487 iowrite32(reg
, pd
->dmactl_base
+ DMA_CONTROL
);
1491 * Clears the error caused by the core's registers being accessed when the
1494 static inline void sata_oxnas_clear_reg_access_error(struct ata_port
*ap
)
1496 struct sata_oxnas_port_priv
*pd
= ap
->private_data
;
1497 u32
*base
= pd
->port_base
;
1500 reg
= ioread32(base
+ INT_STATUS
);
1503 if (reg
& INT_REG_ACCESS_ERR
) {
1504 DPRINTK("clearing register access error on port %d\n",
1506 iowrite32(INT_REG_ACCESS_ERR
, base
+ INT_STATUS
);
1508 reg
= ioread32(base
+ INT_STATUS
);
1509 if (reg
& INT_REG_ACCESS_ERR
)
1510 DPRINTK("register access error didn't clear\n");
1513 static inline void sata_oxnas_clear_sctl_error(struct ata_port
*ap
)
1515 struct sata_oxnas_port_priv
*pd
= ap
->private_data
;
1516 u32
*base
= pd
->port_base
;
1519 reg
= ioread32(base
+ SATA_CONTROL
);
1520 reg
|= SCTL_CLR_ERR
;
1521 iowrite32(reg
, base
+ SATA_CONTROL
);
1524 static inline void sata_oxnas_clear_raid_error(struct ata_host
*ah
)
1530 * Clean up all the state machines in the sata core.
1531 * @return post cleanup action required
1533 static int sata_oxnas_cleanup(struct ata_host
*ah
)
1535 struct sata_oxnas_host_priv
*hd
= ah
->private_data
;
1536 int actions_required
= 0;
1539 printk(KERN_INFO
"sata_oxnas: resetting SATA core\n");
1540 /* core not recovering, reset it */
1542 sata_oxnas_reset_core(ah
);
1544 actions_required
|= OXNAS_SATA_REINIT
;
1545 /* Perform any SATA core re-initialisation after reset post reset init
1546 * needs to be called for both ports as there's one reset for both
1548 for (n
= 0; n
< hd
->n_ports
; n
++)
1549 sata_oxnas_post_reset_init(ah
->ports
[n
]);
1552 return actions_required
;
1556 * ata_qc_new - Request an available ATA command, for queueing
1557 * @ap: Port associated with device @dev
1558 * @return non zero will refuse a new command, zero will may grant on subject
1559 * to conditions elsewhere.
1562 static int sata_oxnas_qc_new(struct ata_port
*ap
)
1564 struct sata_oxnas_host_priv
*hd
= ap
->host
->private_data
;
1566 DPRINTK("port %d\n", ap
->port_no
);
1568 if (hd
->port_frozen
|| hd
->port_in_eh
)
1571 return !sata_oxnas_acquire_hw(ap
, 0, 0);
1575 * releases the lock on the port the command used
1577 static void sata_oxnas_qc_free(struct ata_queued_cmd
*qc
)
1580 sata_oxnas_release_hw(qc
->ap
);
1583 static void sata_oxnas_freeze(struct ata_port
*ap
)
1585 struct sata_oxnas_host_priv
*hd
= ap
->host
->private_data
;
1588 hd
->port_frozen
|= BIT(ap
->port_no
);
1592 static void sata_oxnas_thaw(struct ata_port
*ap
)
1594 struct sata_oxnas_host_priv
*hd
= ap
->host
->private_data
;
1597 hd
->port_frozen
&= ~BIT(ap
->port_no
);
1601 void sata_oxnas_freeze_host(struct ata_port
*ap
)
1603 struct sata_oxnas_host_priv
*hd
= ap
->host
->private_data
;
1606 hd
->port_in_eh
|= BIT(ap
->port_no
);
1610 void sata_oxnas_thaw_host(struct ata_port
*ap
)
1612 struct sata_oxnas_host_priv
*hd
= ap
->host
->private_data
;
1615 hd
->port_in_eh
&= ~BIT(ap
->port_no
);
1619 static void sata_oxnas_post_internal_cmd(struct ata_queued_cmd
*qc
)
1622 /* If the core is busy here, make it idle */
1623 if (qc
->flags
& ATA_QCFLAG_FAILED
)
1624 sata_oxnas_cleanup(qc
->ap
->host
);
1629 * turn on the interrupts
1631 * @param ap Hardware with the registers in
1633 static void sata_oxnas_irq_on(struct ata_port
*ap
)
1635 struct sata_oxnas_port_priv
*pd
= ap
->private_data
;
1636 u32 mask
= (COREINT_END
<< ap
->port_no
);
1638 /* Clear pending interrupts */
1639 iowrite32(~0, pd
->port_base
+ INT_CLEAR
);
1640 iowrite32(mask
, pd
->core_base
+ CORE_INT_STATUS
);
1643 /* enable End of command interrupt */
1644 iowrite32(INT_WANT
, pd
->port_base
+ INT_ENABLE
);
1645 iowrite32(mask
, pd
->core_base
+ CORE_INT_ENABLE
);
1649 /** @return true if the port has a cable connected */
1650 int sata_oxnas_check_link(struct ata_port
*ap
)
1654 sata_oxnas_scr_read_port(ap
, SCR_STATUS
, ®
);
1655 /* Check for the cable present indicated by SCR status bit-0 set */
1660 * ata_std_postreset - standard postreset callback
1661 * @link: the target ata_link
1662 * @classes: classes of attached devices
1664 * This function is invoked after a successful reset. Note that
1665 * the device might have been reset more than once using
1666 * different reset methods before postreset is invoked.
1669 * Kernel thread context (may sleep)
1671 static void sata_oxnas_postreset(struct ata_link
*link
, unsigned int *classes
)
1673 struct ata_port
*ap
= link
->ap
;
1674 struct sata_oxnas_host_priv
*hd
= ap
->host
->private_data
;
1679 ata_std_postreset(link
, classes
);
1681 /* turn on phy error detection by removing the masks */
1682 sata_oxnas_link_write(ap
->host
->ports
[0], 0x0c, 0x30003);
1683 if (hd
->n_ports
> 1)
1684 sata_oxnas_link_write(ap
->host
->ports
[1], 0x0c, 0x30003);
1686 /* bail out if no device is present */
1687 if (classes
[0] == ATA_DEV_NONE
&& classes
[1] == ATA_DEV_NONE
) {
1688 DPRINTK("EXIT, no device\n");
1692 /* go through all the devices and configure them */
1693 for (dev
= 0; dev
< ATA_MAX_DEVICES
; ++dev
) {
1694 if (ap
->link
.device
[dev
].class == ATA_DEV_ATA
)
1695 sata_oxnas_dev_config(&(ap
->link
.device
[dev
]));
1702 * Called to read the hardware registers / DMA buffers, to
1703 * obtain the current set of taskfile register values.
1704 * @param ap hardware with the registers in
1705 * @param tf taskfile to read the registers into
1707 static void sata_oxnas_tf_read(struct ata_port
*ap
, struct ata_taskfile
*tf
)
1709 struct sata_oxnas_port_priv
*port_priv
= ap
->private_data
;
1710 void __iomem
*port_base
= port_priv
->port_base
;
1711 /* read the orb registers */
1712 u32 Orb1
= ioread32(port_base
+ ORB1
);
1713 u32 Orb2
= ioread32(port_base
+ ORB2
);
1714 u32 Orb3
= ioread32(port_base
+ ORB3
);
1715 u32 Orb4
= ioread32(port_base
+ ORB4
);
1717 /* read common 28/48 bit tf parameters */
1718 tf
->device
= (Orb1
>> 24);
1719 tf
->nsect
= (Orb2
>> 0);
1720 tf
->feature
= (Orb2
>> 16);
1721 tf
->command
= sata_oxnas_check_status(ap
);
1723 /* read 48 or 28 bit tf parameters */
1724 if (tf
->flags
& ATA_TFLAG_LBA48
) {
1725 tf
->hob_nsect
= (Orb2
>> 8);
1726 tf
->lbal
= (Orb3
>> 0);
1727 tf
->lbam
= (Orb3
>> 8);
1728 tf
->lbah
= (Orb3
>> 16);
1729 tf
->hob_lbal
= (Orb3
>> 24);
1730 tf
->hob_lbam
= (Orb4
>> 0);
1731 tf
->hob_lbah
= (Orb4
>> 8);
1732 /* feature ext and control are write only */
1734 /* read 28-bit lba */
1735 tf
->lbal
= (Orb3
>> 0);
1736 tf
->lbam
= (Orb3
>> 8);
1737 tf
->lbah
= (Orb3
>> 16);
1742 * Read a result task-file from the sata core registers.
1744 static bool sata_oxnas_qc_fill_rtf(struct ata_queued_cmd
*qc
)
1746 /* Read the most recently received FIS from the SATA core ORB registers
1747 and convert to an ATA taskfile */
1748 sata_oxnas_tf_read(qc
->ap
, &qc
->result_tf
);
1753 * Reads the Status ATA shadow register from hardware.
1755 * @return The status register
1757 static u8
sata_oxnas_check_status(struct ata_port
*ap
)
1761 struct sata_oxnas_port_priv
*port_priv
= ap
->private_data
;
1762 void __iomem
*port_base
= port_priv
->port_base
;
1764 /* read byte 3 of Orb2 register */
1765 status
= ioread32(port_base
+ ORB2
) >> 24;
1767 /* check for the drive going missing indicated by SCR status bits
1769 sata_oxnas_scr_read_port(ap
, SCR_STATUS
, &Reg
);
1779 static inline void sata_oxnas_reset_ucode(struct ata_host
*ah
, int force
,
1782 struct sata_oxnas_host_priv
*hd
= ah
->private_data
;
1788 sata_oxnas_set_mode(ah
, UNKNOWN_MODE
, force
);
1789 reg
= ioread32(hd
->core_base
+ DEVICE_CONTROL
);
1790 reg
|= DEVICE_CONTROL_ATA_ERR_OVERRIDE
;
1791 iowrite32(reg
, hd
->core_base
+ DEVICE_CONTROL
);
1794 sata_oxnas_set_mode(ah
, OXNASSATA_NOTRAID
, force
);
1795 /* Turn the work around off as it may have been left on by any
1796 * HW-RAID code that we've been working with */
1797 iowrite32(0x0, hd
->core_base
+ PORT_ERROR_MASK
);
1802 * Prepare as much as possible for a command without involving anything that is
1803 * shared between ports.
1805 static enum ata_completion_errors
sata_oxnas_qc_prep(struct ata_queued_cmd
*qc
)
1807 struct sata_oxnas_port_priv
*pd
;
1808 int port_no
= qc
->ap
->port_no
;
1810 /* if the port's not connected, complete now with an error */
1811 if (!sata_oxnas_check_link(qc
->ap
)) {
1812 ata_port_err(qc
->ap
,
1813 "port %d not connected completing with error\n",
1815 qc
->err_mask
|= AC_ERR_ATA_BUS
;
1816 ata_qc_complete(qc
);
1819 sata_oxnas_reset_ucode(qc
->ap
->host
, 0, 0);
1821 /* both pio and dma commands use dma */
1822 if (ata_is_dma(qc
->tf
.protocol
) || ata_is_pio(qc
->tf
.protocol
)) {
1824 /* program the scatterlist into the prd table */
1825 ata_bmdma_qc_prep(qc
);
1827 /* point the sgdma controller at the dma request structure */
1828 pd
= qc
->ap
->private_data
;
1830 iowrite32(pd
->sgdma_request_pa
,
1831 pd
->sgdma_base
+ SGDMA_REQUESTPTR
);
1833 /* setup the request table */
1835 pd
->sgdma_request
->control
=
1836 (qc
->dma_dir
== DMA_FROM_DEVICE
) ?
1837 SGDMA_REQCTL0IN
: SGDMA_REQCTL0OUT
;
1839 pd
->sgdma_request
->control
=
1840 (qc
->dma_dir
== DMA_FROM_DEVICE
) ?
1841 SGDMA_REQCTL1IN
: SGDMA_REQCTL1OUT
;
1843 pd
->sgdma_request
->qualifier
= SGDMA_REQQUAL
;
1844 pd
->sgdma_request
->src_pa
= qc
->ap
->bmdma_prd_dma
;
1845 pd
->sgdma_request
->dst_pa
= qc
->ap
->bmdma_prd_dma
;
1848 /* tell it to wait */
1849 iowrite32(SGDMA_CONTROL_NOGO
, pd
->sgdma_base
+ SGDMA_CONTROL
);
1855 static int sata_oxnas_port_start(struct ata_port
*ap
)
1857 struct sata_oxnas_host_priv
*host_priv
= ap
->host
->private_data
;
1858 struct device
*dev
= ap
->host
->dev
;
1859 struct sata_oxnas_port_priv
*pp
;
1865 pp
= kzalloc(sizeof(*pp
), GFP_KERNEL
);
1869 pp
->port_base
= host_priv
->port_base
+
1870 (ap
->port_no
? PORT_SIZE
: 0);
1871 pp
->dmactl_base
= host_priv
->dmactl_base
+
1872 (ap
->port_no
? DMA_CORESIZE
: 0);
1873 pp
->sgdma_base
= host_priv
->sgdma_base
+
1874 (ap
->port_no
? SGDMA_CORESIZE
: 0);
1875 pp
->core_base
= host_priv
->core_base
;
1878 if (host_priv
->dma_size
>= SATA_OXNAS_DMA_SIZE
* host_priv
->n_ports
) {
1879 DPRINTK("using preallocated DMA\n");
1880 mem_dma
= host_priv
->dma_base
+
1881 (ap
->port_no
? SATA_OXNAS_DMA_SIZE
: 0);
1882 mem
= ioremap(mem_dma
, SATA_OXNAS_DMA_SIZE
);
1884 mem
= dma_alloc_coherent(dev
, SATA_OXNAS_DMA_SIZE
, &mem_dma
,
1890 pp
->sgdma_request_pa
= mem_dma
;
1891 pp
->sgdma_request
= mem
;
1893 ap
->bmdma_prd_dma
= mem_dma
+ sizeof(struct sgdma_request
);
1894 ap
->bmdma_prd
= mem
+ sizeof(struct sgdma_request
);
1896 ap
->private_data
= pp
;
1898 sata_oxnas_post_reset_init(ap
);
1908 static void sata_oxnas_port_stop(struct ata_port
*ap
)
1910 struct device
*dev
= ap
->host
->dev
;
1911 struct sata_oxnas_port_priv
*pp
= ap
->private_data
;
1912 struct sata_oxnas_host_priv
*host_priv
= ap
->host
->private_data
;
1915 ap
->private_data
= NULL
;
1916 if (host_priv
->dma_size
) {
1917 iounmap(pp
->sgdma_request
);
1919 dma_free_coherent(dev
, SATA_OXNAS_DMA_SIZE
,
1920 pp
->sgdma_request
, pp
->sgdma_request_pa
);
1927 static void sata_oxnas_post_reset_init(struct ata_port
*ap
)
1931 /* force to load u-code only once after reset */
1932 sata_oxnas_reset_ucode(ap
->host
, !ap
->port_no
, 0);
1934 /* turn on phy error detection by removing the masks */
1935 sata_oxnas_link_write(ap
, 0x0C, 0x30003);
1937 /* enable hotplug event detection */
1938 sata_oxnas_scr_write_port(ap
, SCR_ERROR
, ~0);
1939 sata_oxnas_scr_write_port(ap
, SERROR_IRQ_MASK
, 0x03feffff);
1940 sata_oxnas_scr_write_port(ap
, SCR_ACTIVE
, ~0 & ~(1 << 26) & ~(1 << 16));
1942 /* enable interrupts for ports */
1943 sata_oxnas_irq_on(ap
);
1945 /* go through all the devices and configure them */
1946 for (dev
= 0; dev
< ATA_MAX_DEVICES
; ++dev
) {
1947 if (ap
->link
.device
[dev
].class == ATA_DEV_ATA
) {
1948 sata_std_hardreset(&ap
->link
, NULL
, jiffies
+ HZ
);
1949 sata_oxnas_dev_config(&(ap
->link
.device
[dev
]));
1953 /* clean up any remaining errors */
1954 sata_oxnas_scr_write_port(ap
, SCR_ERROR
, ~0);
1959 * host_stop() is called when the rmmod or hot unplug process begins. The
1960 * hook must stop all hardware interrupts, DMA engines, etc.
1962 * @param ap hardware with the registers in
1964 static void sata_oxnas_host_stop(struct ata_host
*host_set
)
1970 #define ERROR_HW_ACQUIRE_TIMEOUT_JIFFIES (10 * HZ)
1971 static void sata_oxnas_error_handler(struct ata_port
*ap
)
1973 DPRINTK("Enter port_no %d\n", ap
->port_no
);
1974 sata_oxnas_freeze_host(ap
);
1976 /* If the core is busy here, make it idle */
1977 sata_oxnas_cleanup(ap
->host
);
1979 ata_std_error_handler(ap
);
1981 sata_oxnas_thaw_host(ap
);
1984 static int sata_oxnas_softreset(struct ata_link
*link
, unsigned int *class,
1985 unsigned long deadline
)
1987 struct ata_port
*ap
= link
->ap
;
1988 struct sata_oxnas_port_priv
*pd
= ap
->private_data
;
1989 void __iomem
*port_base
= pd
->port_base
;
1992 struct ata_taskfile tf
;
1997 port_base
= pd
->port_base
;
1999 if (ata_link_offline(link
)) {
2000 DPRINTK("PHY reports no device\n");
2001 *class = ATA_DEV_NONE
;
2005 /* write value to register */
2006 iowrite32(0, port_base
+ ORB1
);
2007 iowrite32(0, port_base
+ ORB2
);
2008 iowrite32(0, port_base
+ ORB3
);
2009 iowrite32((ap
->ctl
) << 24, port_base
+ ORB4
);
2011 /* command the core to send a control FIS */
2012 Command_Reg
= ioread32(port_base
+ SATA_COMMAND
);
2013 Command_Reg
&= ~SATA_OPCODE_MASK
;
2014 Command_Reg
|= CMD_WRITE_TO_ORB_REGS_NO_COMMAND
;
2015 iowrite32(Command_Reg
, port_base
+ SATA_COMMAND
);
2016 udelay(20); /* FIXME: flush */
2018 /* write value to register */
2019 iowrite32((ap
->ctl
| ATA_SRST
) << 24, port_base
+ ORB4
);
2021 /* command the core to send a control FIS */
2022 Command_Reg
&= ~SATA_OPCODE_MASK
;
2023 Command_Reg
|= CMD_WRITE_TO_ORB_REGS_NO_COMMAND
;
2024 iowrite32(Command_Reg
, port_base
+ SATA_COMMAND
);
2025 udelay(20); /* FIXME: flush */
2027 /* write value to register */
2028 iowrite32((ap
->ctl
) << 24, port_base
+ ORB4
);
2030 /* command the core to send a control FIS */
2031 Command_Reg
&= ~SATA_OPCODE_MASK
;
2032 Command_Reg
|= CMD_WRITE_TO_ORB_REGS_NO_COMMAND
;
2033 iowrite32(Command_Reg
, port_base
+ SATA_COMMAND
);
2037 rc
= ata_sff_wait_ready(link
, deadline
);
2039 /* if link is occupied, -ENODEV too is an error */
2040 if (rc
&& (rc
!= -ENODEV
|| sata_scr_valid(link
))) {
2041 ata_link_printk(link
, KERN_ERR
, "SRST failed (errno=%d)\n", rc
);
2045 /* determine by signature whether we have ATA or ATAPI devices */
2046 sata_oxnas_tf_read(ap
, &tf
);
2047 *class = ata_dev_classify(&tf
);
2049 if (*class == ATA_DEV_UNKNOWN
)
2050 *class = ATA_DEV_NONE
;
2053 DPRINTK("EXIT, class=%u\n", *class);
2058 int sata_oxnas_init_controller(struct ata_host
*host
)
2066 * This code is a work around for a DMA hardware bug that will repeat the
2067 * penultimate 8-bytes on some reads. This code will check that the amount
2068 * of data transferred is a multiple of 512 bytes, if not the in it will
2069 * fetch the correct data from a buffer in the SATA core and copy it into
2072 * @param port SATA port to check and if necessary, correct.
2074 static int sata_oxnas_bug_6320_detect(struct ata_port
*ap
)
2076 struct sata_oxnas_port_priv
*pd
= ap
->private_data
;
2077 void __iomem
*core_base
= pd
->core_base
;
2079 int quads_transferred
;
2081 int sector_quads_remaining
;
2082 int bug_present
= 0;
2084 /* Only want to apply fix to reads */
2085 is_read
= !(ioread32(core_base
+ DM_DBG1
) & (ap
->port_no
?
2086 BIT(CORE_PORT1_DATA_DIR_BIT
) :
2087 BIT(CORE_PORT0_DATA_DIR_BIT
)));
2089 /* Check for an incomplete transfer, i.e. not a multiple of 512 bytes
2090 transferred (datacount_port register counts quads transferred) */
2092 ioread32(core_base
+ (ap
->port_no
?
2093 DATACOUNT_PORT1
: DATACOUNT_PORT0
));
2095 remainder
= quads_transferred
& 0x7f;
2096 sector_quads_remaining
= remainder
? (0x80 - remainder
) : 0;
2098 if (is_read
&& (sector_quads_remaining
== 2)) {
2100 } else if (sector_quads_remaining
) {
2102 ata_port_warn(ap
, "SATA read fixup cannot deal with "
2103 "%d quads remaining\n",
2104 sector_quads_remaining
);
2106 ata_port_warn(ap
, "SATA write fixup of %d quads "
2107 "remaining not supported\n",
2108 sector_quads_remaining
);
2115 /* This port done an interrupt */
2116 static void sata_oxnas_port_irq(struct ata_port
*ap
, int force_error
)
2118 struct ata_queued_cmd
*qc
;
2119 struct sata_oxnas_port_priv
*pd
= ap
->private_data
;
2120 void __iomem
*port_base
= pd
->port_base
;
2123 unsigned long flags
= 0;
2125 DPRINTK("ENTER port %d irqstatus %x\n", ap
->port_no
,
2126 ioread32(port_base
+ INT_STATUS
));
2128 if (ap
->qc_active
& (1ULL << ATA_TAG_INTERNAL
)) {
2129 qc
= ata_qc_from_tag(ap
, ATA_TAG_INTERNAL
);
2130 DPRINTK("completing non-ncq cmd\n");
2133 ata_qc_complete(qc
);
2138 qc
= ata_qc_from_tag(ap
, ap
->link
.active_tag
);
2141 /* record the port's interrupt */
2142 int_status
= ioread32(port_base
+ INT_STATUS
);
2144 /* If there's no command associated with this IRQ, ignore it. We may get
2145 * spurious interrupts when cleaning-up after a failed command, ignore
2148 /* get the status before any error cleanup */
2149 qc
->err_mask
= ac_err_mask(sata_oxnas_check_status(ap
));
2151 /* Pretend there has been a link error */
2152 qc
->err_mask
|= AC_ERR_ATA_BUS
;
2153 DPRINTK(" ####force error####\n");
2155 /* tell libata we're done */
2156 local_irq_save(flags
);
2157 sata_oxnas_irq_clear(ap
);
2158 local_irq_restore(flags
);
2159 ata_qc_complete(qc
);
2161 VPRINTK("Ignoring interrupt, can't find the command tag="
2162 "%d %08x\n", ap
->link
.active_tag
, ap
->qc_active
);
2165 /* maybe a hotplug event */
2166 if (unlikely(int_status
& INT_LINK_SERROR
)) {
2169 sata_oxnas_scr_read_port(ap
, SCR_ERROR
, &serror
);
2170 if (serror
& (SERR_DEV_XCHG
| SERR_PHYRDY_CHG
)) {
2171 ata_ehi_hotplugged(&ap
->link
.eh_info
);
2172 ata_port_freeze(ap
);
2178 * irq_handler is the interrupt handling routine registered with the system,
2181 static irqreturn_t
sata_oxnas_interrupt(int irq
, void *dev_instance
)
2183 struct ata_host
*ah
= dev_instance
;
2184 struct sata_oxnas_host_priv
*hd
= ah
->private_data
;
2185 void __iomem
*core_base
= hd
->core_base
;
2188 irqreturn_t ret
= IRQ_NONE
;
2193 /* loop until there are no more interrupts */
2194 while ((int_status
= (ioread32(core_base
+ CORE_INT_STATUS
)) &
2195 (COREINT_END
| (COREINT_END
<< 1)))) {
2197 /* clear any interrupt */
2198 iowrite32(int_status
, core_base
+ CORE_INT_CLEAR
);
2200 /* Only need workaround_bug_6320 for single disk systems as dual
2201 * disk will use uCode which prevents this read underrun problem
2203 * All single disk systems will use port 0 */
2204 for (port_no
= 0; port_no
< hd
->n_ports
; ++port_no
) {
2205 /* check the raw end of command interrupt to see if the
2207 mask
= (COREINT_END
<< port_no
);
2208 if (!(int_status
& mask
))
2211 /* this port had an interrupt, clear it */
2212 iowrite32(mask
, core_base
+ CORE_INT_CLEAR
);
2213 /* check for bug 6320 only if no microcode was loaded */
2214 bug_present
= (hd
->current_ucode
== UNKNOWN_MODE
) &&
2215 sata_oxnas_bug_6320_detect(ah
->ports
[port_no
]);
2217 sata_oxnas_port_irq(ah
->ports
[port_no
],
2227 * scsi mid-layer and libata interface structures
2229 static struct scsi_host_template sata_oxnas_sht
= {
2230 ATA_NCQ_SHT("sata_oxnas"),
2231 .can_queue
= SATA_OXNAS_QUEUE_DEPTH
,
2232 .sg_tablesize
= SATA_OXNAS_MAX_PRD
,
2233 .dma_boundary
= ATA_DMA_BOUNDARY
,
2234 .unchecked_isa_dma
= 0,
2238 static struct ata_port_operations sata_oxnas_ops
= {
2239 .inherits
= &sata_port_ops
,
2240 .qc_prep
= sata_oxnas_qc_prep
,
2241 .qc_issue
= sata_oxnas_qc_issue
,
2242 .qc_fill_rtf
= sata_oxnas_qc_fill_rtf
,
2243 .qc_new
= sata_oxnas_qc_new
,
2244 .qc_free
= sata_oxnas_qc_free
,
2246 .scr_read
= sata_oxnas_scr_read
,
2247 .scr_write
= sata_oxnas_scr_write
,
2249 .freeze
= sata_oxnas_freeze
,
2250 .thaw
= sata_oxnas_thaw
,
2251 .softreset
= sata_oxnas_softreset
,
2252 /* .hardreset = sata_oxnas_hardreset, */
2253 .postreset
= sata_oxnas_postreset
,
2254 .error_handler
= sata_oxnas_error_handler
,
2255 .post_internal_cmd
= sata_oxnas_post_internal_cmd
,
2257 .port_start
= sata_oxnas_port_start
,
2258 .port_stop
= sata_oxnas_port_stop
,
2260 .host_stop
= sata_oxnas_host_stop
,
2261 /* .pmp_attach = sata_oxnas_pmp_attach, */
2262 /* .pmp_detach = sata_oxnas_pmp_detach, */
2263 .sff_check_status
= sata_oxnas_check_status
,
2264 .acquire_hw
= sata_oxnas_acquire_hw
,
2267 static const struct ata_port_info sata_oxnas_port_info
= {
2268 .flags
= SATA_OXNAS_HOST_FLAGS
,
2269 .pio_mask
= ATA_PIO4
,
2270 .udma_mask
= ATA_UDMA6
,
2271 .port_ops
= &sata_oxnas_ops
,
2274 static int sata_oxnas_probe(struct platform_device
*ofdev
)
2276 int retval
= -ENXIO
;
2278 void __iomem
*port_base
= NULL
;
2279 void __iomem
*dmactl_base
= NULL
;
2280 void __iomem
*sgdma_base
= NULL
;
2281 void __iomem
*core_base
= NULL
;
2282 void __iomem
*phy_base
= NULL
;
2283 struct reset_control
*rstc
;
2285 struct resource res
= {};
2286 struct sata_oxnas_host_priv
*host_priv
= NULL
;
2288 struct ata_host
*host
= NULL
;
2289 struct clk
*clk
= NULL
;
2291 const struct ata_port_info
*ppi
[] = { &sata_oxnas_port_info
, NULL
};
2293 of_property_read_u32(ofdev
->dev
.of_node
, "nr-ports", &n_ports
);
2294 if (n_ports
< 1 || n_ports
> SATA_OXNAS_MAX_PORTS
)
2295 goto error_exit_with_cleanup
;
2297 port_base
= of_iomap(ofdev
->dev
.of_node
, 0);
2299 goto error_exit_with_cleanup
;
2301 dmactl_base
= of_iomap(ofdev
->dev
.of_node
, 1);
2303 goto error_exit_with_cleanup
;
2305 sgdma_base
= of_iomap(ofdev
->dev
.of_node
, 2);
2307 goto error_exit_with_cleanup
;
2309 core_base
= of_iomap(ofdev
->dev
.of_node
, 3);
2311 goto error_exit_with_cleanup
;
2313 phy_base
= of_iomap(ofdev
->dev
.of_node
, 4);
2315 goto error_exit_with_cleanup
;
2317 host_priv
= devm_kzalloc(&ofdev
->dev
,
2318 sizeof(struct sata_oxnas_host_priv
),
2321 goto error_exit_with_cleanup
;
2323 host_priv
->port_base
= port_base
;
2324 host_priv
->dmactl_base
= dmactl_base
;
2325 host_priv
->sgdma_base
= sgdma_base
;
2326 host_priv
->core_base
= core_base
;
2327 host_priv
->phy_base
= phy_base
;
2328 host_priv
->n_ports
= n_ports
;
2329 host_priv
->current_ucode
= UNKNOWN_MODE
;
2331 if (!of_address_to_resource(ofdev
->dev
.of_node
, 5, &res
)) {
2332 host_priv
->dma_base
= res
.start
;
2333 host_priv
->dma_size
= resource_size(&res
);
2336 irq
= irq_of_parse_and_map(ofdev
->dev
.of_node
, 0);
2338 dev_err(&ofdev
->dev
, "invalid irq from platform\n");
2339 goto error_exit_with_cleanup
;
2341 host_priv
->irq
= irq
;
2343 clk
= of_clk_get(ofdev
->dev
.of_node
, 0);
2345 retval
= PTR_ERR(clk
);
2347 goto error_exit_with_cleanup
;
2349 host_priv
->clk
= clk
;
2351 rstc
= devm_reset_control_get(&ofdev
->dev
, "sata");
2353 retval
= PTR_ERR(rstc
);
2354 goto error_exit_with_cleanup
;
2356 host_priv
->rst_sata
= rstc
;
2358 rstc
= devm_reset_control_get(&ofdev
->dev
, "link");
2360 retval
= PTR_ERR(rstc
);
2361 goto error_exit_with_cleanup
;
2363 host_priv
->rst_link
= rstc
;
2365 rstc
= devm_reset_control_get(&ofdev
->dev
, "phy");
2367 retval
= PTR_ERR(rstc
);
2368 goto error_exit_with_cleanup
;
2370 host_priv
->rst_phy
= rstc
;
2372 /* allocate host structure */
2373 host
= ata_host_alloc_pinfo(&ofdev
->dev
, ppi
, n_ports
);
2377 goto error_exit_with_cleanup
;
2379 host
->private_data
= host_priv
;
2380 host
->iomap
= port_base
;
2382 /* initialize core locking and queues */
2383 init_waitqueue_head(&host_priv
->fast_wait_queue
);
2384 init_waitqueue_head(&host_priv
->scsi_wait_queue
);
2385 spin_lock_init(&host_priv
->phy_lock
);
2386 spin_lock_init(&host_priv
->core_lock
);
2387 host_priv
->core_locked
= 0;
2388 host_priv
->reentrant_port_no
= -1;
2389 host_priv
->hw_lock_count
= 0;
2390 host_priv
->direct_lock_count
= 0;
2391 host_priv
->locker_uid
= 0;
2392 host_priv
->current_locker_type
= SATA_UNLOCKED
;
2393 host_priv
->isr_arg
= NULL
;
2394 host_priv
->isr_callback
= NULL
;
2396 /* initialize host controller */
2397 retval
= sata_oxnas_init_controller(host
);
2399 goto error_exit_with_cleanup
;
2402 * Now, register with libATA core, this will also initiate the
2403 * device discovery process, invoking our port_start() handler &
2404 * error_handler() to execute a dummy softreset EH session
2406 ata_host_activate(host
, irq
, sata_oxnas_interrupt
, SATA_OXNAS_IRQ_FLAG
,
2411 error_exit_with_cleanup
:
2413 irq_dispose_mapping(host_priv
->irq
);
2417 ata_host_detach(host
);
2421 iounmap(sgdma_base
);
2430 static int sata_oxnas_remove(struct platform_device
*ofdev
)
2432 struct ata_host
*host
= dev_get_drvdata(&ofdev
->dev
);
2433 struct sata_oxnas_host_priv
*host_priv
= host
->private_data
;
2435 ata_host_detach(host
);
2437 irq_dispose_mapping(host_priv
->irq
);
2438 iounmap(host_priv
->port_base
);
2439 iounmap(host_priv
->sgdma_base
);
2440 iounmap(host_priv
->core_base
);
2442 /* reset Controller, Link and PHY */
2443 reset_control_assert(host_priv
->rst_sata
);
2444 reset_control_assert(host_priv
->rst_link
);
2445 reset_control_assert(host_priv
->rst_phy
);
2447 /* Disable the clock to the SATA block */
2448 clk_disable_unprepare(host_priv
->clk
);
2449 clk_put(host_priv
->clk
);
2455 static int sata_oxnas_suspend(struct platform_device
*op
, pm_message_t state
)
2457 struct ata_host
*host
= dev_get_drvdata(&op
->dev
);
2459 return ata_host_suspend(host
, state
);
2462 static int sata_oxnas_resume(struct platform_device
*op
)
2464 struct ata_host
*host
= dev_get_drvdata(&op
->dev
);
2467 ret
= sata_oxnas_init_controller(host
);
2469 dev_err(&op
->dev
, "Error initializing hardware\n");
2472 ata_host_resume(host
);
2479 static struct of_device_id oxnas_sata_match
[] = {
2481 .compatible
= "plxtech,nas782x-sata",
2486 MODULE_DEVICE_TABLE(of
, oxnas_sata_match
);
2488 static struct platform_driver oxnas_sata_driver
= {
2490 .name
= "oxnas-sata",
2491 .owner
= THIS_MODULE
,
2492 .of_match_table
= oxnas_sata_match
,
2494 .probe
= sata_oxnas_probe
,
2495 .remove
= sata_oxnas_remove
,
2497 .suspend
= sata_oxnas_suspend
,
2498 .resume
= sata_oxnas_resume
,
2502 module_platform_driver(oxnas_sata_driver
);
2504 MODULE_LICENSE("GPL");
2505 MODULE_VERSION("1.0");
2506 MODULE_AUTHOR("Oxford Semiconductor Ltd.");
2507 MODULE_DESCRIPTION("low-level driver for Oxford 934 SATA core");