3 * A driver to interface the 934 based sata core present in the ox820
5 * based on sata_oxnas driver by Ma Haijun <mahaijuns@gmail.com>
6 * based on ox820 sata code by:
7 * Copyright (c) 2007 Oxford Semiconductor Ltd.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2, or (at your option)
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
20 #include <linux/ata.h>
21 #include <linux/libata.h>
22 #include <linux/of_platform.h>
23 #include <linux/delay.h>
24 #include <linux/module.h>
25 #include <linux/slab.h>
26 #include <linux/spinlock.h>
27 #include <linux/of_address.h>
28 #include <linux/of_irq.h>
29 #include <linux/clk.h>
30 #include <linux/reset.h>
33 #include <linux/sizes.h>
34 #include <linux/version.h>
36 static inline void oxnas_register_clear_mask(void __iomem
*p
, unsigned mask
)
38 u32 val
= readl_relaxed(p
);
41 writel_relaxed(val
, p
);
44 static inline void oxnas_register_set_mask(void __iomem
*p
, unsigned mask
)
46 u32 val
= readl_relaxed(p
);
49 writel_relaxed(val
, p
);
52 static inline void oxnas_register_value_mask(void __iomem
*p
,
53 unsigned mask
, unsigned new_value
)
55 /* TODO sanity check mask & new_value = new_value */
56 u32 val
= readl_relaxed(p
);
60 writel_relaxed(val
, p
);
63 /* sgdma request structure */
64 struct sgdma_request
{
65 volatile u32 qualifier
;
69 } __packed
__aligned(4);
72 /* Controller information */
74 SATA_OXNAS_MAX_PRD
= 63,
75 SATA_OXNAS_DMA_SIZE
= SATA_OXNAS_MAX_PRD
*
76 sizeof(struct ata_bmdma_prd
) +
77 sizeof(struct sgdma_request
),
78 SATA_OXNAS_MAX_PORTS
= 2,
79 /** The different Oxsemi SATA core version numbers */
80 SATA_OXNAS_CORE_VERSION
= 0x1f3,
81 SATA_OXNAS_IRQ_FLAG
= IRQF_SHARED
,
82 SATA_OXNAS_HOST_FLAGS
= (ATA_FLAG_SATA
| ATA_FLAG_PIO_DMA
|
83 ATA_FLAG_NO_ATAPI
/*| ATA_FLAG_NCQ*/),
84 SATA_OXNAS_QUEUE_DEPTH
= 32,
86 SATA_OXNAS_DMA_BOUNDARY
= 0xFFFFFFFF,
94 /** sata host port register offsets */
100 MASTER_STATUS
= 0x10,
112 DRIVE_CONTROL
= 0x6C,
113 /** These registers allow access to the link layer registers
114 that reside in a different clock domain to the processor bus */
127 /** sata port register bits */
130 * commands to issue in the master status to tell it to move shadow ,
131 * registers to the actual device ,
133 SATA_OPCODE_MASK
= 0x00000007,
134 CMD_WRITE_TO_ORB_REGS_NO_COMMAND
= 0x4,
135 CMD_WRITE_TO_ORB_REGS
= 0x2,
136 CMD_SYNC_ESCAPE
= 0x7,
137 CMD_CORE_BUSY
= (1 << 7),
138 CMD_DRIVE_SELECT_SHIFT
= 12,
139 CMD_DRIVE_SELECT_MASK
= (0xf << CMD_DRIVE_SELECT_SHIFT
),
141 /** interrupt bits */
142 INT_END_OF_CMD
= 1 << 0,
143 INT_LINK_SERROR
= 1 << 1,
145 INT_LINK_IRQ
= 1 << 3,
146 INT_REG_ACCESS_ERR
= 1 << 7,
147 INT_BIST_FIS
= 1 << 11,
148 INT_MASKABLE
= INT_END_OF_CMD
|
154 INT_WANT
= INT_END_OF_CMD
|
158 INT_ERRORS
= INT_LINK_SERROR
|
162 /** raw interrupt bits, unmaskable, but do not generate interrupts */
163 RAW_END_OF_CMD
= INT_END_OF_CMD
<< 16,
164 RAW_LINK_SERROR
= INT_LINK_SERROR
<< 16,
165 RAW_ERROR
= INT_ERROR
<< 16,
166 RAW_LINK_IRQ
= INT_LINK_IRQ
<< 16,
167 RAW_REG_ACCESS_ERR
= INT_REG_ACCESS_ERR
<< 16,
168 RAW_BIST_FIS
= INT_BIST_FIS
<< 16,
169 RAW_WANT
= INT_WANT
<< 16,
170 RAW_ERRORS
= INT_ERRORS
<< 16,
173 * variables to write to the device control register to set the current
174 * device, ie. master or slave.
179 SATA_CTL_ERR_MASK
= 0x00000016,
183 /* ATA SGDMA register offsets */
187 SGDMA_REQUESTPTR
= 0x8,
189 SGDMA_CORESIZE
= 0x10,
192 /* DMA controller register offsets */
197 DMA_CONTROL_RESET
= (1 << 12),
201 /* see DMA core docs for the values. Out means from memory (bus A) out
203 SGDMA_REQCTL0OUT
= 0x0497c03d,
204 /* burst mode disabled when no micro code used */
205 SGDMA_REQCTL0IN
= 0x0493a3c1,
206 SGDMA_REQCTL1OUT
= 0x0497c07d,
207 SGDMA_REQCTL1IN
= 0x0497a3c5,
208 SGDMA_CONTROL_NOGO
= 0x3e,
209 SGDMA_CONTROL_GO
= SGDMA_CONTROL_NOGO
| 1,
210 SGDMA_ERRORMASK
= 0x3f,
213 SGDMA_RESETS_CTRL
= 1 << 0,
214 SGDMA_RESETS_ARBT
= 1 << 1,
215 SGDMA_RESETS_AHB
= 1 << 2,
216 SGDMA_RESETS_ALL
= SGDMA_RESETS_CTRL
|
221 SGDMA_REQQUAL
= 0x00220001,
225 /** SATA core register offsets */
230 DATACOUNT_PORT0
= 0x010,
231 DATACOUNT_PORT1
= 0x014,
232 CORE_INT_STATUS
= 0x030,
233 CORE_INT_CLEAR
= 0x030,
234 CORE_INT_ENABLE
= 0x034,
235 CORE_INT_DISABLE
= 0x038,
236 CORE_REBUILD_ENABLE
= 0x050,
237 CORE_FAILED_PORT_R
= 0x054,
238 DEVICE_CONTROL
= 0x068,
240 RAID_SIZE_LOW
= 0x070,
241 RAID_SIZE_HIGH
= 0x074,
242 PORT_ERROR_MASK
= 0x078,
244 RAID_CONTROL
= 0x090,
245 DATA_PLANE_CTRL
= 0x0AC,
246 CORE_DATAPLANE_STAT
= 0x0b8,
251 UCODE_STORE
= 0x1000,
252 RAID_WP_BOT_LOW
= 0x1FF0,
253 RAID_WP_BOT_HIGH
= 0x1FF4,
254 RAID_WP_TOP_LOW
= 0x1FF8,
255 RAID_WP_TOP_HIGH
= 0x1FFC,
256 DATA_MUX_RAM0
= 0x8000,
257 DATA_MUX_RAM1
= 0xA000,
262 /* Sata core debug1 register bits */
263 CORE_PORT0_DATA_DIR_BIT
= 20,
264 CORE_PORT1_DATA_DIR_BIT
= 21,
265 CORE_PORT0_DATA_DIR
= 1 << CORE_PORT0_DATA_DIR_BIT
,
266 CORE_PORT1_DATA_DIR
= 1 << CORE_PORT1_DATA_DIR_BIT
,
268 /** sata core control register bits */
269 SCTL_CLR_ERR
= 0x00003016,
270 RAID_CLR_ERR
= 0x0000011e,
272 /* Interrupts direct from the ports */
273 NORMAL_INTS_WANTED
= 0x00000303,
275 /* shift these left by port number */
276 COREINT_HOST
= 0x00000001,
277 COREINT_END
= 0x00000100,
278 CORERAW_HOST
= COREINT_HOST
<< 16,
279 CORERAW_END
= COREINT_END
<< 16,
281 /* Interrupts from the RAID controller only */
282 RAID_INTS_WANTED
= 0x00008300,
284 /* The bits in the IDLE_STATUS that, when set indicate an idle core */
285 IDLE_CORES
= (1 << 18) | (1 << 19),
287 /* Data plane control error-mask mask and bit, these bit in the data
288 * plane control mask out errors from the ports that prevent the SGDMA
289 * care from sending an interrupt */
290 DPC_ERROR_MASK
= 0x00000300,
291 DPC_ERROR_MASK_BIT
= 0x00000100,
292 /* enable jbod micro-code */
293 DPC_JBOD_UCODE
= 1 << 0,
294 DPC_FIS_SWCH
= 1 << 1,
296 /** Device Control register bits */
297 DEVICE_CONTROL_DMABT
= 1 << 4,
298 DEVICE_CONTROL_ABORT
= 1 << 2,
299 DEVICE_CONTROL_PAD
= 1 << 3,
300 DEVICE_CONTROL_PADPAT
= 1 << 16,
301 DEVICE_CONTROL_PRTRST
= 1 << 8,
302 DEVICE_CONTROL_RAMRST
= 1 << 12,
303 DEVICE_CONTROL_ATA_ERR_OVERRIDE
= 1 << 28,
305 /** oxsemi HW raid modes */
306 OXNASSATA_NOTRAID
= 0,
309 /** OX820 specific HW-RAID register values */
313 CONFIG_IN_RESUME
= 2,
316 /* SATA PHY Registers */
323 STAT_READ_VALID
= (1 << 21),
324 STAT_CR_ACK
= (1 << 20),
325 STAT_CR_READ
= (1 << 19),
326 STAT_CR_WRITE
= (1 << 18),
327 STAT_CAP_DATA
= (1 << 17),
328 STAT_CAP_ADDR
= (1 << 16),
330 STAT_ACK_ANY
= STAT_CR_ACK
|
336 CR_READ_ENABLE
= (1 << 16),
337 CR_WRITE_ENABLE
= (1 << 17),
338 CR_CAP_DATA
= (1 << 18),
342 /* Link layer registers */
347 OXNAS_SATA_SOFTRESET
= 1,
348 OXNAS_SATA_REINIT
= 2,
352 OXNAS_SATA_UCODE_RAID0
,
353 OXNAS_SATA_UCODE_RAID1
,
354 OXNAS_SATA_UCODE_JBOD
,
355 OXNAS_SATA_UCODE_NONE
,
367 typedef irqreturn_t (*oxnas_sata_isr_callback_t
)(int, unsigned long, int);
369 struct sata_oxnas_host_priv
{
370 void __iomem
*port_base
;
371 void __iomem
*dmactl_base
;
372 void __iomem
*sgdma_base
;
373 void __iomem
*core_base
;
374 void __iomem
*phy_base
;
376 void __iomem
*dma_base_va
;
384 struct reset_control
*rst_sata
;
385 struct reset_control
*rst_link
;
386 struct reset_control
*rst_phy
;
388 spinlock_t core_lock
;
390 int reentrant_port_no
;
392 int direct_lock_count
;
394 int current_locker_type
;
395 int scsi_nonblocking_attempts
;
396 oxnas_sata_isr_callback_t isr_callback
;
398 wait_queue_head_t fast_wait_queue
;
399 wait_queue_head_t scsi_wait_queue
;
403 struct sata_oxnas_port_priv
{
404 void __iomem
*port_base
;
405 void __iomem
*dmactl_base
;
406 void __iomem
*sgdma_base
;
407 void __iomem
*core_base
;
408 struct sgdma_request
*sgdma_request
;
409 dma_addr_t sgdma_request_pa
;
412 static u8
sata_oxnas_check_status(struct ata_port
*ap
);
413 static int sata_oxnas_cleanup(struct ata_host
*ah
);
414 static void sata_oxnas_tf_load(struct ata_port
*ap
,
415 const struct ata_taskfile
*tf
);
416 static void sata_oxnas_irq_on(struct ata_port
*ap
);
417 static void sata_oxnas_post_reset_init(struct ata_port
*ap
);
419 static int sata_oxnas_acquire_hw(struct ata_port
*ap
, int may_sleep
,
420 int timeout_jiffies
);
421 static void sata_oxnas_release_hw(struct ata_port
*ap
);
423 static const void *HW_LOCKER_UID
= (void *)0xdeadbeef;
425 /***************************************************************************
427 ***************************************************************************/
428 static void wait_cr_ack(void __iomem
*phy_base
)
430 while ((ioread32(phy_base
+ PHY_STAT
) >> 16) & 0x1f)
431 ; /* wait for an ack bit to be set */
434 static u16
read_cr(void __iomem
*phy_base
, u16 address
)
436 iowrite32((u32
)address
, phy_base
+ PHY_STAT
);
437 wait_cr_ack(phy_base
);
438 iowrite32(CR_READ_ENABLE
, phy_base
+ PHY_DATA
);
439 wait_cr_ack(phy_base
);
440 return (u16
)ioread32(phy_base
+ PHY_STAT
);
443 static void write_cr(void __iomem
*phy_base
, u16 data
, u16 address
)
445 iowrite32((u32
)address
, phy_base
+ PHY_STAT
);
446 wait_cr_ack(phy_base
);
447 iowrite32((data
| CR_CAP_DATA
), phy_base
+ PHY_DATA
);
448 wait_cr_ack(phy_base
);
449 iowrite32(CR_WRITE_ENABLE
, phy_base
+ PHY_DATA
);
450 wait_cr_ack(phy_base
);
455 #define PH_GAIN_OFFSET 6
456 #define FR_GAIN_OFFSET 8
457 #define PH_GAIN_MASK (0x3 << PH_GAIN_OFFSET)
458 #define FR_GAIN_MASK (0x3 << FR_GAIN_OFFSET)
459 #define USE_INT_SETTING (1<<5)
461 void workaround5458(struct ata_host
*ah
)
463 struct sata_oxnas_host_priv
*hd
= ah
->private_data
;
464 void __iomem
*phy_base
= hd
->phy_base
;
468 for (i
= 0; i
< 2; i
++) {
469 rx_control
= read_cr(phy_base
, 0x201d + (i
<< 8));
470 rx_control
&= ~(PH_GAIN_MASK
| FR_GAIN_MASK
);
471 rx_control
|= PH_GAIN
<< PH_GAIN_OFFSET
;
472 rx_control
|= (FR_GAIN
<< FR_GAIN_OFFSET
) | USE_INT_SETTING
;
473 write_cr(phy_base
, rx_control
, 0x201d+(i
<<8));
478 * allows access to the link layer registers
479 * @param link_reg the link layer register to access (oxsemi indexing ie
480 * 00 = static config, 04 = phy ctrl)
482 void sata_oxnas_link_write(struct ata_port
*ap
, unsigned int link_reg
, u32 val
)
484 struct sata_oxnas_port_priv
*pd
= ap
->private_data
;
485 struct sata_oxnas_host_priv
*hd
= ap
->host
->private_data
;
486 void __iomem
*port_base
= pd
->port_base
;
490 DPRINTK("P%d [0x%02x]->0x%08x\n", ap
->port_no
, link_reg
, val
);
492 spin_lock_irqsave(&hd
->phy_lock
, flags
);
493 iowrite32(val
, port_base
+ LINK_DATA
);
495 /* accessed twice as a work around for a bug in the SATA abp bridge
496 * hardware (bug 6828) */
497 iowrite32(link_reg
, port_base
+ LINK_WR_ADDR
);
498 ioread32(port_base
+ LINK_WR_ADDR
);
500 for (patience
= 0x100000; patience
> 0; --patience
) {
501 if (ioread32(port_base
+ LINK_CONTROL
) & 0x00000001)
504 spin_unlock_irqrestore(&hd
->phy_lock
, flags
);
507 static int sata_oxnas_scr_write_port(struct ata_port
*ap
, unsigned int sc_reg
,
510 sata_oxnas_link_write(ap
, 0x20 + (sc_reg
* 4), val
);
514 static int sata_oxnas_scr_write(struct ata_link
*link
, unsigned int sc_reg
,
517 return sata_oxnas_scr_write_port(link
->ap
, sc_reg
, val
);
520 u32
sata_oxnas_link_read(struct ata_port
*ap
, unsigned int link_reg
)
522 struct sata_oxnas_port_priv
*pd
= ap
->private_data
;
523 struct sata_oxnas_host_priv
*hd
= ap
->host
->private_data
;
524 void __iomem
*port_base
= pd
->port_base
;
529 spin_lock_irqsave(&hd
->phy_lock
, flags
);
530 /* accessed twice as a work around for a bug in the SATA abp bridge
531 * hardware (bug 6828) */
532 iowrite32(link_reg
, port_base
+ LINK_RD_ADDR
);
533 ioread32(port_base
+ LINK_RD_ADDR
);
535 for (patience
= 0x100000; patience
> 0; --patience
) {
536 if (ioread32(port_base
+ LINK_CONTROL
) & 0x00000001)
540 DPRINTK("link read timed out for port %d\n", ap
->port_no
);
542 result
= ioread32(port_base
+ LINK_DATA
);
543 spin_unlock_irqrestore(&hd
->phy_lock
, flags
);
548 static int sata_oxnas_scr_read_port(struct ata_port
*ap
, unsigned int sc_reg
,
551 *val
= sata_oxnas_link_read(ap
, 0x20 + (sc_reg
*4));
555 static int sata_oxnas_scr_read(struct ata_link
*link
,
556 unsigned int sc_reg
, u32
*val
)
558 return sata_oxnas_scr_read_port(link
->ap
, sc_reg
, val
);
562 * sata_oxnas_irq_clear is called during probe just before the interrupt handler is
563 * registered, to be sure hardware is quiet. It clears and masks interrupt bits
566 * @param ap hardware with the registers in
568 static void sata_oxnas_irq_clear(struct ata_port
*ap
)
570 struct sata_oxnas_port_priv
*port_priv
= ap
->private_data
;
572 /* clear pending interrupts */
573 iowrite32(~0, port_priv
->port_base
+ INT_CLEAR
);
574 iowrite32(COREINT_END
, port_priv
->core_base
+ CORE_INT_CLEAR
);
578 * qc_issue is used to make a command active, once the hardware and S/G tables
579 * have been prepared. IDE BMDMA drivers use the helper function
580 * ata_qc_issue_prot() for taskfile protocol-based dispatch. More advanced
581 * drivers roll their own ->qc_issue implementation, using this as the
582 * "issue new ATA command to hardware" hook.
583 * @param qc the queued command to issue
585 static unsigned int sata_oxnas_qc_issue(struct ata_queued_cmd
*qc
)
587 struct sata_oxnas_port_priv
*pd
= qc
->ap
->private_data
;
588 struct sata_oxnas_host_priv
*hd
= qc
->ap
->host
->private_data
;
590 void __iomem
*port_base
= pd
->port_base
;
591 void __iomem
*core_base
= pd
->core_base
;
592 int port_no
= qc
->ap
->port_no
;
593 int no_microcode
= (hd
->current_ucode
== UNKNOWN_MODE
);
596 /* check the core is idle */
597 if (ioread32(port_base
+ SATA_COMMAND
) & CMD_CORE_BUSY
) {
600 DPRINTK("core busy for a command on port %d\n",
605 DPRINTK("core busy for a command on port %d\n",
607 /* CrazyDumpDebug(); */
608 sata_oxnas_cleanup(qc
->ap
->host
);
610 } while (ioread32(port_base
+ SATA_COMMAND
) & CMD_CORE_BUSY
);
613 /* enable passing of error signals to DMA sub-core by clearing the
615 reg
= ioread32(core_base
+ DATA_PLANE_CTRL
);
617 reg
|= (DPC_ERROR_MASK_BIT
| (DPC_ERROR_MASK_BIT
<< 1));
618 reg
&= ~(DPC_ERROR_MASK_BIT
<< port_no
);
619 iowrite32(reg
, core_base
+ DATA_PLANE_CTRL
);
621 /* Disable all interrupts for ports and RAID controller */
622 iowrite32(~0, port_base
+ INT_DISABLE
);
624 /* Disable all interrupts for core */
625 iowrite32(~0, core_base
+ CORE_INT_DISABLE
);
628 /* Load the command settings into the orb registers */
629 sata_oxnas_tf_load(qc
->ap
, &qc
->tf
);
631 /* both pio and dma commands use dma */
632 if (ata_is_dma(qc
->tf
.protocol
) || ata_is_pio(qc
->tf
.protocol
)) {
634 iowrite32(SGDMA_CONTROL_GO
, pd
->sgdma_base
+ SGDMA_CONTROL
);
638 /* enable End of command interrupt */
639 iowrite32(INT_WANT
, port_base
+ INT_ENABLE
);
640 iowrite32(COREINT_END
, core_base
+ CORE_INT_ENABLE
);
643 /* Start the command */
644 reg
= ioread32(port_base
+ SATA_COMMAND
);
645 reg
&= ~SATA_OPCODE_MASK
;
646 reg
|= CMD_WRITE_TO_ORB_REGS
;
647 iowrite32(reg
, port_base
+ SATA_COMMAND
);
654 * Will schedule the libATA error handler on the premise that there has
655 * been a hotplug event on the port specified
657 void sata_oxnas_checkforhotplug(struct ata_port
*ap
)
661 ata_ehi_hotplugged(&ap
->link
.eh_info
);
666 /**************************************************************************/
668 /**************************************************************************/
670 * The underlying function that controls access to the sata core
672 * @return non-zero indicates that you have acquired exclusive access to the
675 static int __acquire_sata_core(
678 oxnas_sata_isr_callback_t callback
,
686 unsigned long end
= jiffies
+ timeout_jiffies
;
690 struct sata_oxnas_host_priv
*hd
;
697 hd
= ah
->private_data
;
699 spin_lock_irqsave(&hd
->core_lock
, flags
);
701 DPRINTK("Entered uid %p, port %d, h/w count %d, d count %d, "
702 "callback %p, hw_access %d, core_locked %d, "
703 "reentrant_port_no %d, isr_callback %p\n",
704 uid
, port_no
, hd
->hw_lock_count
, hd
->direct_lock_count
,
705 callback
, hw_access
, hd
->core_locked
, hd
->reentrant_port_no
,
709 if (hd
->core_locked
||
710 (!hw_access
&& hd
->scsi_nonblocking_attempts
)) {
711 /* Can only allow access if from SCSI/SATA stack and if
712 * reentrant access is allowed and this access is to the
713 * same port for which the lock is current held
715 if (hw_access
&& (port_no
== hd
->reentrant_port_no
)) {
716 BUG_ON(!hd
->hw_lock_count
);
717 ++(hd
->hw_lock_count
);
719 DPRINTK("Allow SCSI/SATA re-entrant access to "
720 "uid %p port %d\n", uid
, port_no
);
723 } else if (!hw_access
) {
724 if ((locker_type
== SATA_READER
) &&
725 (hd
->current_locker_type
== SATA_READER
)) {
727 "Already locked by reader, "
728 "uid %p, locker_uid %p, "
729 "port %d, h/w count %d, "
730 "d count %d, hw_access %d\n",
731 uid
, hd
->locker_uid
, port_no
,
733 hd
->direct_lock_count
,
738 if ((locker_type
!= SATA_READER
) &&
739 (locker_type
!= SATA_WRITER
)) {
744 WARN(uid
== hd
->locker_uid
, "Attempt to lock "
745 "by locker type %d uid %p, already "
746 "locked by locker type %d with "
747 "locker_uid %p, port %d, "
748 "h/w count %d, d count %d, "
749 "hw_access %d\n", locker_type
, uid
,
750 hd
->current_locker_type
,
751 hd
->locker_uid
, port_no
,
753 hd
->direct_lock_count
, hw_access
);
756 WARN(hd
->hw_lock_count
|| hd
->direct_lock_count
,
757 "Core unlocked but counts non-zero: uid %p, "
758 "locker_uid %p, port %d, h/w count %d, "
759 "d count %d, hw_access %d\n", uid
,
760 hd
->locker_uid
, port_no
, hd
->hw_lock_count
,
761 hd
->direct_lock_count
, hw_access
);
763 BUG_ON(hd
->current_locker_type
!= SATA_UNLOCKED
);
765 WARN(hd
->locker_uid
, "Attempt to lock uid %p when "
766 "locker_uid %p is non-zero, port %d, "
767 "h/w count %d, d count %d, hw_access %d\n",
768 uid
, hd
->locker_uid
, port_no
, hd
->hw_lock_count
,
769 hd
->direct_lock_count
, hw_access
);
772 /* Direct access attempting to acquire
775 /* Must have callback for direct access */
777 /* Sanity check lock state */
778 BUG_ON(hd
->reentrant_port_no
!= -1);
780 hd
->isr_callback
= callback
;
782 ++(hd
->direct_lock_count
);
784 hd
->current_locker_type
= locker_type
;
786 /* SCSI/SATA attempting to acquire
789 /* No callbacks for SCSI/SATA access */
791 /* No callback args for SCSI/SATA access */
794 /* Sanity check lock state */
795 BUG_ON(hd
->isr_callback
);
798 ++(hd
->hw_lock_count
);
799 hd
->reentrant_port_no
= port_no
;
801 hd
->current_locker_type
= SATA_SCSI_STACK
;
805 hd
->locker_uid
= uid
;
812 DPRINTK("Denying for uid %p locker_type %d, "
813 "hw_access %d, port %d, current_locker_type %d as "
814 "cannot sleep\n", uid
, locker_type
, hw_access
, port_no
,
815 hd
->current_locker_type
);
818 ++(hd
->scsi_nonblocking_attempts
);
823 /* Core is locked and we're allowed to sleep, so wait to be
824 * awoken when the core is unlocked
827 prepare_to_wait(hw_access
? &hd
->scsi_wait_queue
:
828 &hd
->fast_wait_queue
,
829 &wait
, TASK_UNINTERRUPTIBLE
);
830 if (!hd
->core_locked
&&
831 !(!hw_access
&& hd
->scsi_nonblocking_attempts
)) {
832 /* We're going to use variables that will have
833 * been changed by the waker prior to clearing
834 * core_locked so we need to ensure we see
835 * changes to all those variables
840 if (time_after(jiffies
, end
)) {
841 printk(KERN_WARNING
"__acquire_sata_core() "
842 "uid %p failing for port %d timed out, "
843 "locker_uid %p, h/w count %d, "
844 "d count %d, callback %p, hw_access %d, "
845 "core_locked %d, reentrant_port_no %d, "
846 "isr_callback %p, isr_arg %p\n", uid
,
847 port_no
, hd
->locker_uid
,
849 hd
->direct_lock_count
, callback
,
850 hw_access
, hd
->core_locked
,
851 hd
->reentrant_port_no
, hd
->isr_callback
,
856 spin_unlock_irqrestore(&hd
->core_lock
, flags
);
857 if (!schedule_timeout(4*HZ
)) {
858 printk(KERN_INFO
"__acquire_sata_core() uid %p, "
859 "locker_uid %p, timed-out of "
860 "schedule(), checking overall timeout\n",
861 uid
, hd
->locker_uid
);
863 spin_lock_irqsave(&hd
->core_lock
, flags
);
865 finish_wait(hw_access
? &hd
->scsi_wait_queue
:
866 &hd
->fast_wait_queue
, &wait
);
869 if (hw_access
&& acquired
) {
870 if (hd
->scsi_nonblocking_attempts
)
871 hd
->scsi_nonblocking_attempts
= 0;
873 /* Wake any other SCSI/SATA waiters so they can get reentrant
874 * access to the same port if appropriate. This is because if
875 * the SATA core is locked by fast access, or SCSI/SATA access
876 * to other port, then can have >1 SCSI/SATA waiters on the wait
877 * list so want to give reentrant accessors a chance to get
880 if (!list_empty(&hd
->scsi_wait_queue
.head
))
881 wake_up(&hd
->scsi_wait_queue
);
884 DPRINTK("Leaving uid %p with acquired = %d, port %d, callback %p\n",
885 uid
, acquired
, port_no
, callback
);
887 spin_unlock_irqrestore(&hd
->core_lock
, flags
);
892 int sata_core_has_fast_waiters(struct ata_host
*ah
)
896 struct sata_oxnas_host_priv
*hd
= ah
->private_data
;
898 spin_lock_irqsave(&hd
->core_lock
, flags
);
899 has_waiters
= !list_empty(&hd
->fast_wait_queue
.head
);
900 spin_unlock_irqrestore(&hd
->core_lock
, flags
);
904 EXPORT_SYMBOL(sata_core_has_fast_waiters
);
906 int sata_core_has_scsi_waiters(struct ata_host
*ah
)
910 struct sata_oxnas_host_priv
*hd
= ah
->private_data
;
912 spin_lock_irqsave(&hd
->core_lock
, flags
);
913 has_waiters
= hd
->scsi_nonblocking_attempts
||
914 !list_empty(&hd
->scsi_wait_queue
.head
);
915 spin_unlock_irqrestore(&hd
->core_lock
, flags
);
919 EXPORT_SYMBOL(sata_core_has_scsi_waiters
);
922 * ata_port operation to gain ownership of the SATA hardware prior to issuing
923 * a command against a SATA host. Allows any number of users of the port against
924 * which the lock was first acquired, thus enforcing that only one SATA core
925 * port may be operated on at once.
927 static int sata_oxnas_acquire_hw(
932 return __acquire_sata_core(ap
->host
, ap
->port_no
, NULL
, 0, may_sleep
,
933 timeout_jiffies
, 1, (void *)HW_LOCKER_UID
,
938 * operation to release ownership of the SATA hardware
940 static void sata_oxnas_release_hw(struct ata_port
*ap
)
944 struct sata_oxnas_host_priv
*hd
= ap
->host
->private_data
;
946 spin_lock_irqsave(&hd
->core_lock
, flags
);
948 DPRINTK("Entered port_no = %d, h/w count %d, d count %d, "
949 "core locked = %d, reentrant_port_no = %d, isr_callback %p\n",
950 ap
->port_no
, hd
->hw_lock_count
, hd
->direct_lock_count
,
951 hd
->core_locked
, hd
->reentrant_port_no
, hd
->isr_callback
);
953 if (!hd
->core_locked
) {
954 /* Nobody holds the SATA lock */
955 printk(KERN_WARNING
"Nobody holds SATA lock, port_no %d\n",
958 } else if (!hd
->hw_lock_count
) {
959 /* SCSI/SATA has released without holding the lock */
960 printk(KERN_WARNING
"SCSI/SATA does not hold SATA lock, "
961 "port_no %d\n", ap
->port_no
);
963 /* Trap incorrect usage */
964 BUG_ON(hd
->reentrant_port_no
== -1);
965 BUG_ON(ap
->port_no
!= hd
->reentrant_port_no
);
966 BUG_ON(hd
->direct_lock_count
);
967 BUG_ON(hd
->current_locker_type
!= SATA_SCSI_STACK
);
969 WARN(!hd
->locker_uid
|| (hd
->locker_uid
!= HW_LOCKER_UID
),
970 "Invalid locker uid %p, h/w count %d, d count %d, "
971 "reentrant_port_no %d, core_locked %d, "
972 "isr_callback %p\n", hd
->locker_uid
, hd
->hw_lock_count
,
973 hd
->direct_lock_count
, hd
->reentrant_port_no
,
974 hd
->core_locked
, hd
->isr_callback
);
976 if (--(hd
->hw_lock_count
)) {
977 DPRINTK("Still nested port_no %d\n", ap
->port_no
);
979 DPRINTK("Release port_no %d\n", ap
->port_no
);
980 hd
->reentrant_port_no
= -1;
981 hd
->isr_callback
= NULL
;
982 hd
->current_locker_type
= SATA_UNLOCKED
;
986 wake_up(!list_empty(&hd
->scsi_wait_queue
.head
) ?
987 &hd
->scsi_wait_queue
:
988 &hd
->fast_wait_queue
);
992 DPRINTK("Leaving, port_no %d, count %d\n", ap
->port_no
,
995 spin_unlock_irqrestore(&hd
->core_lock
, flags
);
997 /* CONFIG_SATA_OX820_DIRECT_HWRAID */
999 ox820hwraid_restart_queue();
1003 static inline int sata_oxnas_is_host_frozen(struct ata_host
*ah
)
1005 struct sata_oxnas_host_priv
*hd
= ah
->private_data
;
1008 return hd
->port_in_eh
|| hd
->port_frozen
;
1012 static inline u32
sata_oxnas_hostportbusy(struct ata_port
*ap
)
1014 struct sata_oxnas_host_priv
*hd
= ap
->host
->private_data
;
1016 return (ioread32(hd
->port_base
+ SATA_COMMAND
) & CMD_CORE_BUSY
) ||
1018 (ioread32(hd
->port_base
+ PORT_SIZE
+ SATA_COMMAND
) &
1022 static inline u32
sata_oxnas_hostdmabusy(struct ata_port
*ap
)
1024 struct sata_oxnas_port_priv
*pd
= ap
->private_data
;
1026 return ioread32(pd
->sgdma_base
+ SGDMA_STATUS
) & SGDMA_BUSY
;
1031 * Turns on the cores clock and resets it
1033 static void sata_oxnas_reset_core(struct ata_host
*ah
)
1035 struct sata_oxnas_host_priv
*host_priv
= ah
->private_data
;
1039 clk_prepare_enable(host_priv
->clk
);
1041 reset_control_assert(host_priv
->rst_sata
);
1042 reset_control_assert(host_priv
->rst_link
);
1043 reset_control_assert(host_priv
->rst_phy
);
1047 /* un-reset the PHY, then Link and Controller */
1048 reset_control_deassert(host_priv
->rst_phy
);
1051 reset_control_deassert(host_priv
->rst_sata
);
1052 reset_control_deassert(host_priv
->rst_link
);
1056 /* tune for sata compatibility */
1057 sata_oxnas_link_write(ah
->ports
[0], 0x60, 0x2988);
1059 for (n
= 0; n
< host_priv
->n_ports
; n
++) {
1060 /* each port in turn */
1061 sata_oxnas_link_write(ah
->ports
[n
], 0x70, 0x55629);
1068 * Called after an identify device command has worked out what kind of device
1071 * @param port The port to configure
1072 * @param pdev The hardware associated with controlling the port
1074 static void sata_oxnas_dev_config(struct ata_device
*pdev
)
1076 struct sata_oxnas_port_priv
*pd
= pdev
->link
->ap
->private_data
;
1077 void __iomem
*port_base
= pd
->port_base
;
1081 /* Set the bits to put the port into 28 or 48-bit node */
1082 reg
= ioread32(port_base
+ DRIVE_CONTROL
);
1084 reg
|= (pdev
->flags
& ATA_DFLAG_LBA48
) ? DR_CON_48
: DR_CON_28
;
1085 iowrite32(reg
, port_base
+ DRIVE_CONTROL
);
1087 /* if this is an ATA-6 disk, put port into ATA-5 auto translate mode */
1088 if (pdev
->flags
& ATA_DFLAG_LBA48
) {
1089 reg
= ioread32(port_base
+ PORT_CONTROL
);
1091 iowrite32(reg
, port_base
+ PORT_CONTROL
);
1095 * called to write a taskfile into the ORB registers
1096 * @param ap hardware with the registers in
1097 * @param tf taskfile to write to the registers
1099 static void sata_oxnas_tf_load(struct ata_port
*ap
,
1100 const struct ata_taskfile
*tf
)
1109 struct sata_oxnas_port_priv
*port_priv
= ap
->private_data
;
1110 void __iomem
*port_base
= port_priv
->port_base
;
1111 unsigned int is_addr
= tf
->flags
& ATA_TFLAG_ISADDR
;
1113 /* wait a maximum of 10ms for the core to be idle */
1115 Command_Reg
= ioread32(port_base
+ SATA_COMMAND
);
1116 if (!(Command_Reg
& CMD_CORE_BUSY
))
1120 } while (count
< 200);
1122 /* check if the ctl register has interrupts disabled or enabled and
1123 * modify the interrupt enable registers on the ata core as required */
1124 if (tf
->ctl
& ATA_NIEN
) {
1125 /* interrupts disabled */
1126 u32 mask
= (COREINT_END
<< ap
->port_no
);
1128 iowrite32(mask
, port_priv
->core_base
+ CORE_INT_DISABLE
);
1129 sata_oxnas_irq_clear(ap
);
1131 sata_oxnas_irq_on(ap
);
1134 Orb2
|= (tf
->command
) << 24;
1136 /* write 48 or 28 bit tf parameters */
1138 /* set LBA bit as it's an address */
1139 Orb1
|= (tf
->device
& ATA_LBA
) << 24;
1141 if (tf
->flags
& ATA_TFLAG_LBA48
) {
1142 Orb1
|= ATA_LBA
<< 24;
1143 Orb2
|= (tf
->hob_nsect
) << 8;
1144 Orb3
|= (tf
->hob_lbal
) << 24;
1145 Orb4
|= (tf
->hob_lbam
) << 0;
1146 Orb4
|= (tf
->hob_lbah
) << 8;
1147 Orb4
|= (tf
->hob_feature
) << 16;
1149 Orb3
|= (tf
->device
& 0xf) << 24;
1152 /* write 28-bit lba */
1153 Orb2
|= (tf
->nsect
) << 0;
1154 Orb2
|= (tf
->feature
) << 16;
1155 Orb3
|= (tf
->lbal
) << 0;
1156 Orb3
|= (tf
->lbam
) << 8;
1157 Orb3
|= (tf
->lbah
) << 16;
1158 Orb4
|= (tf
->ctl
) << 24;
1161 if (tf
->flags
& ATA_TFLAG_DEVICE
)
1162 Orb1
|= (tf
->device
) << 24;
1164 ap
->last_ctl
= tf
->ctl
;
1166 /* write values to registers */
1167 iowrite32(Orb1
, port_base
+ ORB1
);
1168 iowrite32(Orb2
, port_base
+ ORB2
);
1169 iowrite32(Orb3
, port_base
+ ORB3
);
1170 iowrite32(Orb4
, port_base
+ ORB4
);
1174 void sata_oxnas_set_mode(struct ata_host
*ah
, u32 mode
, u32 force
)
1176 struct sata_oxnas_host_priv
*host_priv
= ah
->private_data
;
1177 void __iomem
*core_base
= host_priv
->core_base
;
1181 unsigned int progmicrocode
= 0;
1182 unsigned int changeparameters
= 0;
1186 /* these micro-code programs _should_ include the version word */
1189 static const unsigned int jbod
[] = {
1190 0x07B400AC, 0x0228A280, 0x00200001, 0x00204002, 0x00224001,
1191 0x00EE0009, 0x00724901, 0x01A24903, 0x00E40009, 0x00224001,
1192 0x00621120, 0x0183C908, 0x00E20005, 0x00718908, 0x0198A206,
1193 0x00621124, 0x0183C908, 0x00E20046, 0x00621104, 0x0183C908,
1194 0x00E20015, 0x00EE009D, 0x01A3E301, 0x00E2001B, 0x0183C900,
1195 0x00E2001B, 0x00210001, 0x00EE0020, 0x01A3E302, 0x00E2009D,
1196 0x0183C901, 0x00E2009D, 0x00210002, 0x0235D700, 0x0208A204,
1197 0x0071C908, 0x000F8207, 0x000FC207, 0x0071C920, 0x000F8507,
1198 0x000FC507, 0x0228A240, 0x02269A40, 0x00094004, 0x00621104,
1199 0x0180C908, 0x00E40031, 0x00621112, 0x01A3C801, 0x00E2002B,
1200 0x00294000, 0x0228A220, 0x01A69ABF, 0x002F8000, 0x002FC000,
1201 0x0198A204, 0x0001C022, 0x01B1A220, 0x0001C106, 0x00088007,
1202 0x0183C903, 0x00E2009D, 0x0228A220, 0x0071890C, 0x0208A206,
1203 0x0198A206, 0x0001C022, 0x01B1A220, 0x0001C106, 0x00088007,
1204 0x00EE009D, 0x00621104, 0x0183C908, 0x00E2004A, 0x00EE009D,
1205 0x01A3C901, 0x00E20050, 0x0021E7FF, 0x0183E007, 0x00E2009D,
1206 0x00EE0054, 0x0061600B, 0x0021E7FF, 0x0183C507, 0x00E2009D,
1207 0x01A3E301, 0x00E2005A, 0x0183C900, 0x00E2005A, 0x00210001,
1208 0x00EE005F, 0x01A3E302, 0x00E20005, 0x0183C901, 0x00E20005,
1209 0x00210002, 0x0235D700, 0x0208A204, 0x000F8109, 0x000FC109,
1210 0x0071C918, 0x000F8407, 0x000FC407, 0x0001C022, 0x01A1A2BF,
1211 0x0001C106, 0x00088007, 0x02269A40, 0x00094004, 0x00621112,
1212 0x01A3C801, 0x00E4007F, 0x00621104, 0x0180C908, 0x00E4008D,
1213 0x00621128, 0x0183C908, 0x00E2006C, 0x01A3C901, 0x00E2007B,
1214 0x0021E7FF, 0x0183E007, 0x00E2007F, 0x00EE006C, 0x0061600B,
1215 0x0021E7FF, 0x0183C507, 0x00E4006C, 0x00621111, 0x01A3C801,
1216 0x00E2007F, 0x00621110, 0x01A3C801, 0x00E20082, 0x0228A220,
1217 0x00621119, 0x01A3C801, 0x00E20086, 0x0001C022, 0x01B1A220,
1218 0x0001C106, 0x00088007, 0x0198A204, 0x00294000, 0x01A69ABF,
1219 0x002F8000, 0x002FC000, 0x0183C903, 0x00E20005, 0x0228A220,
1220 0x0071890C, 0x0208A206, 0x0198A206, 0x0001C022, 0x01B1A220,
1221 0x0001C106, 0x00088007, 0x00EE009D, 0x00621128, 0x0183C908,
1222 0x00E20005, 0x00621104, 0x0183C908, 0x00E200A6, 0x0062111C,
1223 0x0183C908, 0x00E20005, 0x0071890C, 0x0208A206, 0x0198A206,
1224 0x00718908, 0x0208A206, 0x00EE0005, ~0
1227 /* Bi-Modal RAID-0/1 */
1228 static const unsigned int raid
[] = {
1229 0x00F20145, 0x00EE20FA, 0x00EE20A7, 0x0001C009, 0x00EE0004,
1230 0x00220000, 0x0001000B, 0x037003FF, 0x00700018, 0x037003FE,
1231 0x037043FD, 0x00704118, 0x037043FC, 0x01A3D240, 0x00E20017,
1232 0x00B3C235, 0x00E40018, 0x0093C104, 0x00E80014, 0x0093C004,
1233 0x00E80017, 0x01020000, 0x00274020, 0x00EE0083, 0x0080C904,
1234 0x0093C104, 0x00EA0020, 0x0093C103, 0x00EC001F, 0x00220002,
1235 0x00924104, 0x0005C009, 0x00EE0058, 0x0093CF04, 0x00E80026,
1236 0x00900F01, 0x00600001, 0x00910400, 0x00EE0058, 0x00601604,
1237 0x01A00003, 0x00E2002C, 0x01018000, 0x00274040, 0x00EE0083,
1238 0x0093CF03, 0x00EC0031, 0x00220003, 0x00924F04, 0x0005C009,
1239 0x00810104, 0x00B3C235, 0x00E20037, 0x0022C000, 0x00218210,
1240 0x00EE0039, 0x0022C001, 0x00218200, 0x00600401, 0x00A04901,
1241 0x00604101, 0x01A0C401, 0x00E20040, 0x00216202, 0x00EE0041,
1242 0x00216101, 0x02018506, 0x00EE2141, 0x00904901, 0x00E20049,
1243 0x00A00401, 0x00600001, 0x02E0C301, 0x00EE2141, 0x00216303,
1244 0x037003EE, 0x01A3C001, 0x00E40105, 0x00250080, 0x00204000,
1245 0x002042F1, 0x0004C001, 0x00230001, 0x00100006, 0x02C18605,
1246 0x00100006, 0x01A3D502, 0x00E20055, 0x00EE0053, 0x00004009,
1247 0x00000004, 0x00B3C235, 0x00E40062, 0x0022C001, 0x0020C000,
1248 0x00EE2141, 0x0020C001, 0x00EE2141, 0x00EE006B, 0x0022C000,
1249 0x0060D207, 0x00EE2141, 0x00B3C242, 0x00E20069, 0x01A3D601,
1250 0x00E2006E, 0x02E0C301, 0x00EE2141, 0x00230001, 0x00301303,
1251 0x00EE007B, 0x00218210, 0x01A3C301, 0x00E20073, 0x00216202,
1252 0x00EE0074, 0x00216101, 0x02018506, 0x00214000, 0x037003EE,
1253 0x01A3C001, 0x00E40108, 0x00230001, 0x00100006, 0x00250080,
1254 0x00204000, 0x002042F1, 0x0004C001, 0x00EE007F, 0x0024C000,
1255 0x01A3D1F0, 0x00E20088, 0x00230001, 0x00300000, 0x01A3D202,
1256 0x00E20085, 0x00EE00A5, 0x00B3C800, 0x00E20096, 0x00218000,
1257 0x00924709, 0x0005C009, 0x00B20802, 0x00E40093, 0x037103FD,
1258 0x00710418, 0x037103FC, 0x00EE0006, 0x00220000, 0x0001000F,
1259 0x00EE0006, 0x00800B0C, 0x00B00001, 0x00204000, 0x00208550,
1260 0x00208440, 0x002083E0, 0x00208200, 0x00208100, 0x01008000,
1261 0x037083EE, 0x02008212, 0x02008216, 0x01A3C201, 0x00E400A5,
1262 0x0100C000, 0x00EE20FA, 0x02800000, 0x00208000, 0x00B24C00,
1263 0x00E400AD, 0x00224001, 0x00724910, 0x0005C009, 0x00B3CDC4,
1264 0x00E200D5, 0x00B3CD29, 0x00E200D5, 0x00B3CD20, 0x00E200D5,
1265 0x00B3CD24, 0x00E200D5, 0x00B3CDC5, 0x00E200D2, 0x00B3CD39,
1266 0x00E200D2, 0x00B3CD30, 0x00E200D2, 0x00B3CD34, 0x00E200D2,
1267 0x00B3CDCA, 0x00E200CF, 0x00B3CD35, 0x00E200CF, 0x00B3CDC8,
1268 0x00E200CC, 0x00B3CD25, 0x00E200CC, 0x00B3CD40, 0x00E200CB,
1269 0x00B3CD42, 0x00E200CB, 0x01018000, 0x00EE0083, 0x0025C000,
1270 0x036083EE, 0x0000800D, 0x00EE00D8, 0x036083EE, 0x00208035,
1271 0x00EE00DA, 0x036083EE, 0x00208035, 0x00EE00DA, 0x00208007,
1272 0x036083EE, 0x00208025, 0x036083EF, 0x02400000, 0x01A3D208,
1273 0x00E200D8, 0x0067120A, 0x0021C000, 0x0021C224, 0x00220000,
1274 0x00404B1C, 0x00600105, 0x00800007, 0x0020C00E, 0x00214000,
1275 0x01004000, 0x01A0411F, 0x00404E01, 0x01A3C101, 0x00E200F1,
1276 0x00B20800, 0x00E400D8, 0x00220001, 0x0080490B, 0x00B04101,
1277 0x0040411C, 0x00EE00E1, 0x02269A01, 0x01020000, 0x02275D80,
1278 0x01A3D202, 0x00E200F4, 0x01B75D80, 0x01030000, 0x01B69A01,
1279 0x00EE00D8, 0x01A3D204, 0x00E40104, 0x00224000, 0x0020C00E,
1280 0x0020001E, 0x00214000, 0x01004000, 0x0212490E, 0x00214001,
1281 0x01004000, 0x02400000, 0x00B3D702, 0x00E80112, 0x00EE010E,
1282 0x00B3D702, 0x00E80112, 0x00B3D702, 0x00E4010E, 0x00230001,
1283 0x00EE0140, 0x00200005, 0x036003EE, 0x00204001, 0x00EE0116,
1284 0x00230001, 0x00100006, 0x02C18605, 0x00100006, 0x01A3D1F0,
1285 0x00E40083, 0x037003EE, 0x01A3C002, 0x00E20121, 0x0020A300,
1286 0x0183D102, 0x00E20124, 0x037003EE, 0x01A00005, 0x036003EE,
1287 0x01A0910F, 0x00B3C20F, 0x00E2012F, 0x01A3D502, 0x00E20116,
1288 0x01A3C002, 0x00E20116, 0x00B3D702, 0x00E4012C, 0x00300000,
1289 0x00EE011F, 0x02C18605, 0x00100006, 0x00EE0116, 0x01A3D1F0,
1290 0x00E40083, 0x037003EE, 0x01A3C004, 0x00E20088, 0x00200003,
1291 0x036003EE, 0x01A3D502, 0x00E20136, 0x00230001, 0x00B3C101,
1292 0x00E4012C, 0x00100006, 0x02C18605, 0x00100006, 0x00204000,
1293 0x00EE0116, 0x00100006, 0x01A3D1F0, 0x00E40083, 0x01000000,
1297 DPRINTK("ENTER: mode:%d, force:%d\n", mode
, force
);
1300 previous_mode
= UNKNOWN_MODE
;
1302 previous_mode
= host_priv
->current_ucode
;
1304 if (mode
== previous_mode
)
1307 host_priv
->current_ucode
= mode
;
1309 /* decide what needs to be done using the STD in my logbook */
1310 switch (previous_mode
) {
1311 case OXNASSATA_RAID1
:
1313 case OXNASSATA_RAID0
:
1314 changeparameters
= 1;
1316 case OXNASSATA_NOTRAID
:
1317 changeparameters
= 1;
1322 case OXNASSATA_RAID0
:
1324 case OXNASSATA_RAID1
:
1325 changeparameters
= 1;
1327 case OXNASSATA_NOTRAID
:
1328 changeparameters
= 1;
1333 case OXNASSATA_NOTRAID
:
1335 case OXNASSATA_RAID0
:
1336 case OXNASSATA_RAID1
:
1337 changeparameters
= 1;
1343 changeparameters
= 1;
1348 /* no need to reprogram everything if already in the right mode */
1349 if (progmicrocode
) {
1350 /* reset micro-code processor */
1351 iowrite32(1, core_base
+ PROC_RESET
);
1354 /* select micro-code */
1356 case OXNASSATA_RAID1
:
1357 case OXNASSATA_RAID0
:
1358 VPRINTK("Loading RAID micro-code\n");
1359 src
= (unsigned int *)&raid
[1];
1361 case OXNASSATA_NOTRAID
:
1362 VPRINTK("Loading JBOD micro-code\n");
1363 src
= (unsigned int *)&jbod
[1];
1370 /* load micro code */
1371 dst
= core_base
+ UCODE_STORE
;
1372 while (*src
!= ~0) {
1373 iowrite32(*src
, dst
);
1375 dst
+= sizeof(*src
);
1380 if (changeparameters
) {
1382 /* set other mode dependent flags */
1384 case OXNASSATA_RAID1
:
1385 /* clear JBOD mode */
1386 reg
= ioread32(core_base
+ DATA_PLANE_CTRL
);
1387 reg
|= DPC_JBOD_UCODE
;
1388 reg
&= ~DPC_FIS_SWCH
;
1389 iowrite32(reg
, core_base
+ DATA_PLANE_CTRL
);
1392 /* set the hardware up for RAID-1 */
1393 iowrite32(0, core_base
+ RAID_WP_BOT_LOW
);
1394 iowrite32(0, core_base
+ RAID_WP_BOT_HIGH
);
1395 iowrite32(0xffffffff, core_base
+ RAID_WP_TOP_LOW
);
1396 iowrite32(0x7fffffff, core_base
+ RAID_WP_TOP_HIGH
);
1397 iowrite32(0, core_base
+ RAID_SIZE_LOW
);
1398 iowrite32(0, core_base
+ RAID_SIZE_HIGH
);
1401 case OXNASSATA_RAID0
:
1402 /* clear JBOD mode */
1403 reg
= ioread32(core_base
+ DATA_PLANE_CTRL
);
1404 reg
|= DPC_JBOD_UCODE
;
1405 reg
&= ~DPC_FIS_SWCH
;
1406 iowrite32(reg
, core_base
+ DATA_PLANE_CTRL
);
1409 /* set the hardware up for RAID-1 */
1410 iowrite32(0, core_base
+ RAID_WP_BOT_LOW
);
1411 iowrite32(0, core_base
+ RAID_WP_BOT_HIGH
);
1412 iowrite32(0xffffffff, core_base
+ RAID_WP_TOP_LOW
);
1413 iowrite32(0x7fffffff, core_base
+ RAID_WP_TOP_HIGH
);
1414 iowrite32(0xffffffff, core_base
+ RAID_SIZE_LOW
);
1415 iowrite32(0x7fffffff, core_base
+ RAID_SIZE_HIGH
);
1418 case OXNASSATA_NOTRAID
:
1419 /* enable jbod mode */
1420 reg
= ioread32(core_base
+ DATA_PLANE_CTRL
);
1421 reg
&= ~DPC_JBOD_UCODE
;
1422 reg
&= ~DPC_FIS_SWCH
;
1423 iowrite32(reg
, core_base
+ DATA_PLANE_CTRL
);
1426 /* start micro-code processor*/
1427 iowrite32(1, core_base
+ PROC_START
);
1430 reg
= ioread32(core_base
+ DATA_PLANE_CTRL
);
1431 reg
|= DPC_JBOD_UCODE
;
1432 reg
&= ~DPC_FIS_SWCH
;
1433 iowrite32(reg
, core_base
+ DATA_PLANE_CTRL
);
1441 * sends a sync-escape if there is a link present
1443 static inline void sata_oxnas_send_sync_escape(struct ata_port
*ap
)
1445 struct sata_oxnas_port_priv
*pd
= ap
->private_data
;
1448 /* read the SSTATUS register and only send a sync escape if there is a
1450 if ((sata_oxnas_link_read(ap
, 0x20) & 3) == 3) {
1451 reg
= ioread32(pd
->port_base
+ SATA_COMMAND
);
1452 reg
&= ~SATA_OPCODE_MASK
;
1453 reg
|= CMD_SYNC_ESCAPE
;
1454 iowrite32(reg
, pd
->port_base
+ SATA_COMMAND
);
1459 static inline void sata_oxnas_clear_CS_error(struct ata_port
*ap
)
1461 struct sata_oxnas_port_priv
*pd
= ap
->private_data
;
1462 u32
*base
= pd
->port_base
;
1465 reg
= ioread32(base
+ SATA_CONTROL
);
1466 reg
&= SATA_CTL_ERR_MASK
;
1467 iowrite32(reg
, base
+ SATA_CONTROL
);
1470 static inline void sata_oxnas_reset_sgdma(struct ata_port
*ap
)
1472 struct sata_oxnas_port_priv
*pd
= ap
->private_data
;
1474 iowrite32(SGDMA_RESETS_CTRL
, pd
->sgdma_base
+ SGDMA_RESETS
);
1477 static inline void sata_oxnas_reset_dma(struct ata_port
*ap
, int assert)
1479 struct sata_oxnas_port_priv
*pd
= ap
->private_data
;
1482 reg
= ioread32(pd
->dmactl_base
+ DMA_CONTROL
);
1484 reg
|= DMA_CONTROL_RESET
;
1486 reg
&= ~DMA_CONTROL_RESET
;
1488 iowrite32(reg
, pd
->dmactl_base
+ DMA_CONTROL
);
1492 * Clears the error caused by the core's registers being accessed when the
1495 static inline void sata_oxnas_clear_reg_access_error(struct ata_port
*ap
)
1497 struct sata_oxnas_port_priv
*pd
= ap
->private_data
;
1498 u32
*base
= pd
->port_base
;
1501 reg
= ioread32(base
+ INT_STATUS
);
1504 if (reg
& INT_REG_ACCESS_ERR
) {
1505 DPRINTK("clearing register access error on port %d\n",
1507 iowrite32(INT_REG_ACCESS_ERR
, base
+ INT_STATUS
);
1509 reg
= ioread32(base
+ INT_STATUS
);
1510 if (reg
& INT_REG_ACCESS_ERR
)
1511 DPRINTK("register access error didn't clear\n");
1514 static inline void sata_oxnas_clear_sctl_error(struct ata_port
*ap
)
1516 struct sata_oxnas_port_priv
*pd
= ap
->private_data
;
1517 u32
*base
= pd
->port_base
;
1520 reg
= ioread32(base
+ SATA_CONTROL
);
1521 reg
|= SCTL_CLR_ERR
;
1522 iowrite32(reg
, base
+ SATA_CONTROL
);
1525 static inline void sata_oxnas_clear_raid_error(struct ata_host
*ah
)
1531 * Clean up all the state machines in the sata core.
1532 * @return post cleanup action required
1534 static int sata_oxnas_cleanup(struct ata_host
*ah
)
1536 struct sata_oxnas_host_priv
*hd
= ah
->private_data
;
1537 int actions_required
= 0;
1540 printk(KERN_INFO
"sata_oxnas: resetting SATA core\n");
1541 /* core not recovering, reset it */
1543 sata_oxnas_reset_core(ah
);
1545 actions_required
|= OXNAS_SATA_REINIT
;
1546 /* Perform any SATA core re-initialisation after reset post reset init
1547 * needs to be called for both ports as there's one reset for both
1549 for (n
= 0; n
< hd
->n_ports
; n
++)
1550 sata_oxnas_post_reset_init(ah
->ports
[n
]);
1553 return actions_required
;
1557 * ata_qc_new - Request an available ATA command, for queueing
1558 * @ap: Port associated with device @dev
1559 * @return non zero will refuse a new command, zero will may grant on subject
1560 * to conditions elsewhere.
1563 static int sata_oxnas_qc_new(struct ata_port
*ap
)
1565 struct sata_oxnas_host_priv
*hd
= ap
->host
->private_data
;
1567 DPRINTK("port %d\n", ap
->port_no
);
1569 if (hd
->port_frozen
|| hd
->port_in_eh
)
1572 return !sata_oxnas_acquire_hw(ap
, 0, 0);
1576 * releases the lock on the port the command used
1578 static void sata_oxnas_qc_free(struct ata_queued_cmd
*qc
)
1581 sata_oxnas_release_hw(qc
->ap
);
1584 static void sata_oxnas_freeze(struct ata_port
*ap
)
1586 struct sata_oxnas_host_priv
*hd
= ap
->host
->private_data
;
1589 hd
->port_frozen
|= BIT(ap
->port_no
);
1593 static void sata_oxnas_thaw(struct ata_port
*ap
)
1595 struct sata_oxnas_host_priv
*hd
= ap
->host
->private_data
;
1598 hd
->port_frozen
&= ~BIT(ap
->port_no
);
1602 void sata_oxnas_freeze_host(struct ata_port
*ap
)
1604 struct sata_oxnas_host_priv
*hd
= ap
->host
->private_data
;
1607 hd
->port_in_eh
|= BIT(ap
->port_no
);
1611 void sata_oxnas_thaw_host(struct ata_port
*ap
)
1613 struct sata_oxnas_host_priv
*hd
= ap
->host
->private_data
;
1616 hd
->port_in_eh
&= ~BIT(ap
->port_no
);
1620 static void sata_oxnas_post_internal_cmd(struct ata_queued_cmd
*qc
)
1623 /* If the core is busy here, make it idle */
1624 if (qc
->flags
& ATA_QCFLAG_FAILED
)
1625 sata_oxnas_cleanup(qc
->ap
->host
);
1630 * turn on the interrupts
1632 * @param ap Hardware with the registers in
1634 static void sata_oxnas_irq_on(struct ata_port
*ap
)
1636 struct sata_oxnas_port_priv
*pd
= ap
->private_data
;
1637 u32 mask
= (COREINT_END
<< ap
->port_no
);
1639 /* Clear pending interrupts */
1640 iowrite32(~0, pd
->port_base
+ INT_CLEAR
);
1641 iowrite32(mask
, pd
->core_base
+ CORE_INT_STATUS
);
1644 /* enable End of command interrupt */
1645 iowrite32(INT_WANT
, pd
->port_base
+ INT_ENABLE
);
1646 iowrite32(mask
, pd
->core_base
+ CORE_INT_ENABLE
);
1650 /** @return true if the port has a cable connected */
1651 int sata_oxnas_check_link(struct ata_port
*ap
)
1655 sata_oxnas_scr_read_port(ap
, SCR_STATUS
, ®
);
1656 /* Check for the cable present indicated by SCR status bit-0 set */
1661 * ata_std_postreset - standard postreset callback
1662 * @link: the target ata_link
1663 * @classes: classes of attached devices
1665 * This function is invoked after a successful reset. Note that
1666 * the device might have been reset more than once using
1667 * different reset methods before postreset is invoked.
1670 * Kernel thread context (may sleep)
1672 static void sata_oxnas_postreset(struct ata_link
*link
, unsigned int *classes
)
1674 struct ata_port
*ap
= link
->ap
;
1675 struct sata_oxnas_host_priv
*hd
= ap
->host
->private_data
;
1680 ata_std_postreset(link
, classes
);
1682 /* turn on phy error detection by removing the masks */
1683 sata_oxnas_link_write(ap
->host
->ports
[0], 0x0c, 0x30003);
1684 if (hd
->n_ports
> 1)
1685 sata_oxnas_link_write(ap
->host
->ports
[1], 0x0c, 0x30003);
1687 /* bail out if no device is present */
1688 if (classes
[0] == ATA_DEV_NONE
&& classes
[1] == ATA_DEV_NONE
) {
1689 DPRINTK("EXIT, no device\n");
1693 /* go through all the devices and configure them */
1694 for (dev
= 0; dev
< ATA_MAX_DEVICES
; ++dev
) {
1695 if (ap
->link
.device
[dev
].class == ATA_DEV_ATA
)
1696 sata_oxnas_dev_config(&(ap
->link
.device
[dev
]));
1703 * Called to read the hardware registers / DMA buffers, to
1704 * obtain the current set of taskfile register values.
1705 * @param ap hardware with the registers in
1706 * @param tf taskfile to read the registers into
1708 static void sata_oxnas_tf_read(struct ata_port
*ap
, struct ata_taskfile
*tf
)
1710 struct sata_oxnas_port_priv
*port_priv
= ap
->private_data
;
1711 void __iomem
*port_base
= port_priv
->port_base
;
1712 /* read the orb registers */
1713 u32 Orb1
= ioread32(port_base
+ ORB1
);
1714 u32 Orb2
= ioread32(port_base
+ ORB2
);
1715 u32 Orb3
= ioread32(port_base
+ ORB3
);
1716 u32 Orb4
= ioread32(port_base
+ ORB4
);
1718 /* read common 28/48 bit tf parameters */
1719 tf
->device
= (Orb1
>> 24);
1720 tf
->nsect
= (Orb2
>> 0);
1721 tf
->feature
= (Orb2
>> 16);
1722 tf
->command
= sata_oxnas_check_status(ap
);
1724 /* read 48 or 28 bit tf parameters */
1725 if (tf
->flags
& ATA_TFLAG_LBA48
) {
1726 tf
->hob_nsect
= (Orb2
>> 8);
1727 tf
->lbal
= (Orb3
>> 0);
1728 tf
->lbam
= (Orb3
>> 8);
1729 tf
->lbah
= (Orb3
>> 16);
1730 tf
->hob_lbal
= (Orb3
>> 24);
1731 tf
->hob_lbam
= (Orb4
>> 0);
1732 tf
->hob_lbah
= (Orb4
>> 8);
1733 /* feature ext and control are write only */
1735 /* read 28-bit lba */
1736 tf
->lbal
= (Orb3
>> 0);
1737 tf
->lbam
= (Orb3
>> 8);
1738 tf
->lbah
= (Orb3
>> 16);
1743 * Read a result task-file from the sata core registers.
1745 static bool sata_oxnas_qc_fill_rtf(struct ata_queued_cmd
*qc
)
1747 /* Read the most recently received FIS from the SATA core ORB registers
1748 and convert to an ATA taskfile */
1749 sata_oxnas_tf_read(qc
->ap
, &qc
->result_tf
);
1754 * Reads the Status ATA shadow register from hardware.
1756 * @return The status register
1758 static u8
sata_oxnas_check_status(struct ata_port
*ap
)
1762 struct sata_oxnas_port_priv
*port_priv
= ap
->private_data
;
1763 void __iomem
*port_base
= port_priv
->port_base
;
1765 /* read byte 3 of Orb2 register */
1766 status
= ioread32(port_base
+ ORB2
) >> 24;
1768 /* check for the drive going missing indicated by SCR status bits
1770 sata_oxnas_scr_read_port(ap
, SCR_STATUS
, &Reg
);
1780 static inline void sata_oxnas_reset_ucode(struct ata_host
*ah
, int force
,
1783 struct sata_oxnas_host_priv
*hd
= ah
->private_data
;
1789 sata_oxnas_set_mode(ah
, UNKNOWN_MODE
, force
);
1790 reg
= ioread32(hd
->core_base
+ DEVICE_CONTROL
);
1791 reg
|= DEVICE_CONTROL_ATA_ERR_OVERRIDE
;
1792 iowrite32(reg
, hd
->core_base
+ DEVICE_CONTROL
);
1795 sata_oxnas_set_mode(ah
, OXNASSATA_NOTRAID
, force
);
1796 /* Turn the work around off as it may have been left on by any
1797 * HW-RAID code that we've been working with */
1798 iowrite32(0x0, hd
->core_base
+ PORT_ERROR_MASK
);
1803 * Prepare as much as possible for a command without involving anything that is
1804 * shared between ports.
1806 static enum ata_completion_errors
sata_oxnas_qc_prep(struct ata_queued_cmd
*qc
)
1808 struct sata_oxnas_port_priv
*pd
;
1809 int port_no
= qc
->ap
->port_no
;
1811 /* if the port's not connected, complete now with an error */
1812 if (!sata_oxnas_check_link(qc
->ap
)) {
1813 ata_port_err(qc
->ap
,
1814 "port %d not connected completing with error\n",
1816 qc
->err_mask
|= AC_ERR_ATA_BUS
;
1817 ata_qc_complete(qc
);
1820 sata_oxnas_reset_ucode(qc
->ap
->host
, 0, 0);
1822 /* both pio and dma commands use dma */
1823 if (ata_is_dma(qc
->tf
.protocol
) || ata_is_pio(qc
->tf
.protocol
)) {
1825 /* program the scatterlist into the prd table */
1826 ata_bmdma_qc_prep(qc
);
1828 /* point the sgdma controller at the dma request structure */
1829 pd
= qc
->ap
->private_data
;
1831 iowrite32(pd
->sgdma_request_pa
,
1832 pd
->sgdma_base
+ SGDMA_REQUESTPTR
);
1834 /* setup the request table */
1836 pd
->sgdma_request
->control
=
1837 (qc
->dma_dir
== DMA_FROM_DEVICE
) ?
1838 SGDMA_REQCTL0IN
: SGDMA_REQCTL0OUT
;
1840 pd
->sgdma_request
->control
=
1841 (qc
->dma_dir
== DMA_FROM_DEVICE
) ?
1842 SGDMA_REQCTL1IN
: SGDMA_REQCTL1OUT
;
1844 pd
->sgdma_request
->qualifier
= SGDMA_REQQUAL
;
1845 pd
->sgdma_request
->src_pa
= qc
->ap
->bmdma_prd_dma
;
1846 pd
->sgdma_request
->dst_pa
= qc
->ap
->bmdma_prd_dma
;
1849 /* tell it to wait */
1850 iowrite32(SGDMA_CONTROL_NOGO
, pd
->sgdma_base
+ SGDMA_CONTROL
);
1856 static int sata_oxnas_port_start(struct ata_port
*ap
)
1858 struct sata_oxnas_host_priv
*host_priv
= ap
->host
->private_data
;
1859 struct device
*dev
= ap
->host
->dev
;
1860 struct sata_oxnas_port_priv
*pp
;
1866 pp
= kzalloc(sizeof(*pp
), GFP_KERNEL
);
1870 pp
->port_base
= host_priv
->port_base
+
1871 (ap
->port_no
? PORT_SIZE
: 0);
1872 pp
->dmactl_base
= host_priv
->dmactl_base
+
1873 (ap
->port_no
? DMA_CORESIZE
: 0);
1874 pp
->sgdma_base
= host_priv
->sgdma_base
+
1875 (ap
->port_no
? SGDMA_CORESIZE
: 0);
1876 pp
->core_base
= host_priv
->core_base
;
1879 if (host_priv
->dma_size
>= SATA_OXNAS_DMA_SIZE
* host_priv
->n_ports
) {
1880 DPRINTK("using preallocated DMA\n");
1881 mem_dma
= host_priv
->dma_base
+
1882 (ap
->port_no
? SATA_OXNAS_DMA_SIZE
: 0);
1883 mem
= ioremap(mem_dma
, SATA_OXNAS_DMA_SIZE
);
1885 mem
= dma_alloc_coherent(dev
, SATA_OXNAS_DMA_SIZE
, &mem_dma
,
1891 pp
->sgdma_request_pa
= mem_dma
;
1892 pp
->sgdma_request
= mem
;
1894 ap
->bmdma_prd_dma
= mem_dma
+ sizeof(struct sgdma_request
);
1895 ap
->bmdma_prd
= mem
+ sizeof(struct sgdma_request
);
1897 ap
->private_data
= pp
;
1899 sata_oxnas_post_reset_init(ap
);
1909 static void sata_oxnas_port_stop(struct ata_port
*ap
)
1911 struct device
*dev
= ap
->host
->dev
;
1912 struct sata_oxnas_port_priv
*pp
= ap
->private_data
;
1913 struct sata_oxnas_host_priv
*host_priv
= ap
->host
->private_data
;
1916 ap
->private_data
= NULL
;
1917 if (host_priv
->dma_size
) {
1918 iounmap(pp
->sgdma_request
);
1920 dma_free_coherent(dev
, SATA_OXNAS_DMA_SIZE
,
1921 pp
->sgdma_request
, pp
->sgdma_request_pa
);
1928 static void sata_oxnas_post_reset_init(struct ata_port
*ap
)
1932 /* force to load u-code only once after reset */
1933 sata_oxnas_reset_ucode(ap
->host
, !ap
->port_no
, 0);
1935 /* turn on phy error detection by removing the masks */
1936 sata_oxnas_link_write(ap
, 0x0C, 0x30003);
1938 /* enable hotplug event detection */
1939 sata_oxnas_scr_write_port(ap
, SCR_ERROR
, ~0);
1940 sata_oxnas_scr_write_port(ap
, SERROR_IRQ_MASK
, 0x03feffff);
1941 sata_oxnas_scr_write_port(ap
, SCR_ACTIVE
, ~0 & ~(1 << 26) & ~(1 << 16));
1943 /* enable interrupts for ports */
1944 sata_oxnas_irq_on(ap
);
1946 /* go through all the devices and configure them */
1947 for (dev
= 0; dev
< ATA_MAX_DEVICES
; ++dev
) {
1948 if (ap
->link
.device
[dev
].class == ATA_DEV_ATA
) {
1949 sata_std_hardreset(&ap
->link
, NULL
, jiffies
+ HZ
);
1950 sata_oxnas_dev_config(&(ap
->link
.device
[dev
]));
1954 /* clean up any remaining errors */
1955 sata_oxnas_scr_write_port(ap
, SCR_ERROR
, ~0);
1960 * host_stop() is called when the rmmod or hot unplug process begins. The
1961 * hook must stop all hardware interrupts, DMA engines, etc.
1963 * @param ap hardware with the registers in
1965 static void sata_oxnas_host_stop(struct ata_host
*host_set
)
1971 #define ERROR_HW_ACQUIRE_TIMEOUT_JIFFIES (10 * HZ)
1972 static void sata_oxnas_error_handler(struct ata_port
*ap
)
1974 DPRINTK("Enter port_no %d\n", ap
->port_no
);
1975 sata_oxnas_freeze_host(ap
);
1977 /* If the core is busy here, make it idle */
1978 sata_oxnas_cleanup(ap
->host
);
1980 ata_std_error_handler(ap
);
1982 sata_oxnas_thaw_host(ap
);
1985 static int sata_oxnas_softreset(struct ata_link
*link
, unsigned int *class,
1986 unsigned long deadline
)
1988 struct ata_port
*ap
= link
->ap
;
1989 struct sata_oxnas_port_priv
*pd
= ap
->private_data
;
1990 void __iomem
*port_base
= pd
->port_base
;
1993 struct ata_taskfile tf
;
1998 port_base
= pd
->port_base
;
2000 if (ata_link_offline(link
)) {
2001 DPRINTK("PHY reports no device\n");
2002 *class = ATA_DEV_NONE
;
2006 /* write value to register */
2007 iowrite32(0, port_base
+ ORB1
);
2008 iowrite32(0, port_base
+ ORB2
);
2009 iowrite32(0, port_base
+ ORB3
);
2010 iowrite32((ap
->ctl
) << 24, port_base
+ ORB4
);
2012 /* command the core to send a control FIS */
2013 Command_Reg
= ioread32(port_base
+ SATA_COMMAND
);
2014 Command_Reg
&= ~SATA_OPCODE_MASK
;
2015 Command_Reg
|= CMD_WRITE_TO_ORB_REGS_NO_COMMAND
;
2016 iowrite32(Command_Reg
, port_base
+ SATA_COMMAND
);
2017 udelay(20); /* FIXME: flush */
2019 /* write value to register */
2020 iowrite32((ap
->ctl
| ATA_SRST
) << 24, port_base
+ ORB4
);
2022 /* command the core to send a control FIS */
2023 Command_Reg
&= ~SATA_OPCODE_MASK
;
2024 Command_Reg
|= CMD_WRITE_TO_ORB_REGS_NO_COMMAND
;
2025 iowrite32(Command_Reg
, port_base
+ SATA_COMMAND
);
2026 udelay(20); /* FIXME: flush */
2028 /* write value to register */
2029 iowrite32((ap
->ctl
) << 24, port_base
+ ORB4
);
2031 /* command the core to send a control FIS */
2032 Command_Reg
&= ~SATA_OPCODE_MASK
;
2033 Command_Reg
|= CMD_WRITE_TO_ORB_REGS_NO_COMMAND
;
2034 iowrite32(Command_Reg
, port_base
+ SATA_COMMAND
);
2038 rc
= ata_sff_wait_ready(link
, deadline
);
2040 /* if link is occupied, -ENODEV too is an error */
2041 if (rc
&& (rc
!= -ENODEV
|| sata_scr_valid(link
))) {
2042 ata_link_err(link
, "SRST failed (errno=%d)\n", rc
);
2046 /* determine by signature whether we have ATA or ATAPI devices */
2047 sata_oxnas_tf_read(ap
, &tf
);
2048 *class = ata_dev_classify(&tf
);
2050 if (*class == ATA_DEV_UNKNOWN
)
2051 *class = ATA_DEV_NONE
;
2054 DPRINTK("EXIT, class=%u\n", *class);
2059 int sata_oxnas_init_controller(struct ata_host
*host
)
2067 * This code is a work around for a DMA hardware bug that will repeat the
2068 * penultimate 8-bytes on some reads. This code will check that the amount
2069 * of data transferred is a multiple of 512 bytes, if not the in it will
2070 * fetch the correct data from a buffer in the SATA core and copy it into
2073 * @param port SATA port to check and if necessary, correct.
2075 static int sata_oxnas_bug_6320_detect(struct ata_port
*ap
)
2077 struct sata_oxnas_port_priv
*pd
= ap
->private_data
;
2078 void __iomem
*core_base
= pd
->core_base
;
2080 int quads_transferred
;
2082 int sector_quads_remaining
;
2083 int bug_present
= 0;
2085 /* Only want to apply fix to reads */
2086 is_read
= !(ioread32(core_base
+ DM_DBG1
) & (ap
->port_no
?
2087 BIT(CORE_PORT1_DATA_DIR_BIT
) :
2088 BIT(CORE_PORT0_DATA_DIR_BIT
)));
2090 /* Check for an incomplete transfer, i.e. not a multiple of 512 bytes
2091 transferred (datacount_port register counts quads transferred) */
2093 ioread32(core_base
+ (ap
->port_no
?
2094 DATACOUNT_PORT1
: DATACOUNT_PORT0
));
2096 remainder
= quads_transferred
& 0x7f;
2097 sector_quads_remaining
= remainder
? (0x80 - remainder
) : 0;
2099 if (is_read
&& (sector_quads_remaining
== 2)) {
2101 } else if (sector_quads_remaining
) {
2103 ata_port_warn(ap
, "SATA read fixup cannot deal with "
2104 "%d quads remaining\n",
2105 sector_quads_remaining
);
2107 ata_port_warn(ap
, "SATA write fixup of %d quads "
2108 "remaining not supported\n",
2109 sector_quads_remaining
);
2116 /* This port done an interrupt */
2117 static void sata_oxnas_port_irq(struct ata_port
*ap
, int force_error
)
2119 struct ata_queued_cmd
*qc
;
2120 struct sata_oxnas_port_priv
*pd
= ap
->private_data
;
2121 void __iomem
*port_base
= pd
->port_base
;
2124 unsigned long flags
= 0;
2126 DPRINTK("ENTER port %d irqstatus %x\n", ap
->port_no
,
2127 ioread32(port_base
+ INT_STATUS
));
2129 if (ap
->qc_active
& (1ULL << ATA_TAG_INTERNAL
)) {
2130 qc
= ata_qc_from_tag(ap
, ATA_TAG_INTERNAL
);
2131 DPRINTK("completing non-ncq cmd\n");
2134 ata_qc_complete(qc
);
2139 qc
= ata_qc_from_tag(ap
, ap
->link
.active_tag
);
2142 /* record the port's interrupt */
2143 int_status
= ioread32(port_base
+ INT_STATUS
);
2145 /* If there's no command associated with this IRQ, ignore it. We may get
2146 * spurious interrupts when cleaning-up after a failed command, ignore
2149 /* get the status before any error cleanup */
2150 qc
->err_mask
= ac_err_mask(sata_oxnas_check_status(ap
));
2152 /* Pretend there has been a link error */
2153 qc
->err_mask
|= AC_ERR_ATA_BUS
;
2154 DPRINTK(" ####force error####\n");
2156 /* tell libata we're done */
2157 local_irq_save(flags
);
2158 sata_oxnas_irq_clear(ap
);
2159 local_irq_restore(flags
);
2160 ata_qc_complete(qc
);
2162 VPRINTK("Ignoring interrupt, can't find the command tag="
2163 "%d %08x\n", ap
->link
.active_tag
, ap
->qc_active
);
2166 /* maybe a hotplug event */
2167 if (unlikely(int_status
& INT_LINK_SERROR
)) {
2170 sata_oxnas_scr_read_port(ap
, SCR_ERROR
, &serror
);
2171 if (serror
& (SERR_DEV_XCHG
| SERR_PHYRDY_CHG
)) {
2172 ata_ehi_hotplugged(&ap
->link
.eh_info
);
2173 ata_port_freeze(ap
);
2179 * irq_handler is the interrupt handling routine registered with the system,
2182 static irqreturn_t
sata_oxnas_interrupt(int irq
, void *dev_instance
)
2184 struct ata_host
*ah
= dev_instance
;
2185 struct sata_oxnas_host_priv
*hd
= ah
->private_data
;
2186 void __iomem
*core_base
= hd
->core_base
;
2189 irqreturn_t ret
= IRQ_NONE
;
2194 /* loop until there are no more interrupts */
2195 while ((int_status
= (ioread32(core_base
+ CORE_INT_STATUS
)) &
2196 (COREINT_END
| (COREINT_END
<< 1)))) {
2198 /* clear any interrupt */
2199 iowrite32(int_status
, core_base
+ CORE_INT_CLEAR
);
2201 /* Only need workaround_bug_6320 for single disk systems as dual
2202 * disk will use uCode which prevents this read underrun problem
2204 * All single disk systems will use port 0 */
2205 for (port_no
= 0; port_no
< hd
->n_ports
; ++port_no
) {
2206 /* check the raw end of command interrupt to see if the
2208 mask
= (COREINT_END
<< port_no
);
2209 if (!(int_status
& mask
))
2212 /* this port had an interrupt, clear it */
2213 iowrite32(mask
, core_base
+ CORE_INT_CLEAR
);
2214 /* check for bug 6320 only if no microcode was loaded */
2215 bug_present
= (hd
->current_ucode
== UNKNOWN_MODE
) &&
2216 sata_oxnas_bug_6320_detect(ah
->ports
[port_no
]);
2218 sata_oxnas_port_irq(ah
->ports
[port_no
],
2228 * scsi mid-layer and libata interface structures
2230 static struct scsi_host_template sata_oxnas_sht
= {
2231 ATA_NCQ_SHT("sata_oxnas"),
2232 .can_queue
= SATA_OXNAS_QUEUE_DEPTH
,
2233 .sg_tablesize
= SATA_OXNAS_MAX_PRD
,
2234 .dma_boundary
= ATA_DMA_BOUNDARY
,
2238 static struct ata_port_operations sata_oxnas_ops
= {
2239 .inherits
= &sata_port_ops
,
2240 .qc_prep
= sata_oxnas_qc_prep
,
2241 .qc_issue
= sata_oxnas_qc_issue
,
2242 .qc_fill_rtf
= sata_oxnas_qc_fill_rtf
,
2243 .qc_new
= sata_oxnas_qc_new
,
2244 .qc_free
= sata_oxnas_qc_free
,
2246 .scr_read
= sata_oxnas_scr_read
,
2247 .scr_write
= sata_oxnas_scr_write
,
2249 .freeze
= sata_oxnas_freeze
,
2250 .thaw
= sata_oxnas_thaw
,
2251 .softreset
= sata_oxnas_softreset
,
2252 /* .hardreset = sata_oxnas_hardreset, */
2253 .postreset
= sata_oxnas_postreset
,
2254 .error_handler
= sata_oxnas_error_handler
,
2255 .post_internal_cmd
= sata_oxnas_post_internal_cmd
,
2257 .port_start
= sata_oxnas_port_start
,
2258 .port_stop
= sata_oxnas_port_stop
,
2260 .host_stop
= sata_oxnas_host_stop
,
2261 /* .pmp_attach = sata_oxnas_pmp_attach, */
2262 /* .pmp_detach = sata_oxnas_pmp_detach, */
2263 .sff_check_status
= sata_oxnas_check_status
,
2264 .acquire_hw
= sata_oxnas_acquire_hw
,
2267 static const struct ata_port_info sata_oxnas_port_info
= {
2268 .flags
= SATA_OXNAS_HOST_FLAGS
,
2269 .pio_mask
= ATA_PIO4
,
2270 .udma_mask
= ATA_UDMA6
,
2271 .port_ops
= &sata_oxnas_ops
,
2274 static int sata_oxnas_probe(struct platform_device
*ofdev
)
2276 int retval
= -ENXIO
;
2278 void __iomem
*port_base
= NULL
;
2279 void __iomem
*dmactl_base
= NULL
;
2280 void __iomem
*sgdma_base
= NULL
;
2281 void __iomem
*core_base
= NULL
;
2282 void __iomem
*phy_base
= NULL
;
2283 struct reset_control
*rstc
;
2285 struct resource res
= {};
2286 struct sata_oxnas_host_priv
*host_priv
= NULL
;
2288 struct ata_host
*host
= NULL
;
2289 struct clk
*clk
= NULL
;
2291 const struct ata_port_info
*ppi
[] = { &sata_oxnas_port_info
, NULL
};
2293 of_property_read_u32(ofdev
->dev
.of_node
, "nr-ports", &n_ports
);
2294 if (n_ports
< 1 || n_ports
> SATA_OXNAS_MAX_PORTS
)
2295 goto error_exit_with_cleanup
;
2297 port_base
= of_iomap(ofdev
->dev
.of_node
, 0);
2299 goto error_exit_with_cleanup
;
2301 dmactl_base
= of_iomap(ofdev
->dev
.of_node
, 1);
2303 goto error_exit_with_cleanup
;
2305 sgdma_base
= of_iomap(ofdev
->dev
.of_node
, 2);
2307 goto error_exit_with_cleanup
;
2309 core_base
= of_iomap(ofdev
->dev
.of_node
, 3);
2311 goto error_exit_with_cleanup
;
2313 phy_base
= of_iomap(ofdev
->dev
.of_node
, 4);
2315 goto error_exit_with_cleanup
;
2317 host_priv
= devm_kzalloc(&ofdev
->dev
,
2318 sizeof(struct sata_oxnas_host_priv
),
2321 goto error_exit_with_cleanup
;
2323 host_priv
->port_base
= port_base
;
2324 host_priv
->dmactl_base
= dmactl_base
;
2325 host_priv
->sgdma_base
= sgdma_base
;
2326 host_priv
->core_base
= core_base
;
2327 host_priv
->phy_base
= phy_base
;
2328 host_priv
->n_ports
= n_ports
;
2329 host_priv
->current_ucode
= UNKNOWN_MODE
;
2331 if (!of_address_to_resource(ofdev
->dev
.of_node
, 5, &res
)) {
2332 host_priv
->dma_base
= res
.start
;
2333 host_priv
->dma_size
= resource_size(&res
);
2336 irq
= irq_of_parse_and_map(ofdev
->dev
.of_node
, 0);
2338 dev_err(&ofdev
->dev
, "invalid irq from platform\n");
2339 goto error_exit_with_cleanup
;
2341 host_priv
->irq
= irq
;
2343 clk
= of_clk_get(ofdev
->dev
.of_node
, 0);
2345 retval
= PTR_ERR(clk
);
2347 goto error_exit_with_cleanup
;
2349 host_priv
->clk
= clk
;
2351 rstc
= devm_reset_control_get(&ofdev
->dev
, "sata");
2353 retval
= PTR_ERR(rstc
);
2354 goto error_exit_with_cleanup
;
2356 host_priv
->rst_sata
= rstc
;
2358 rstc
= devm_reset_control_get(&ofdev
->dev
, "link");
2360 retval
= PTR_ERR(rstc
);
2361 goto error_exit_with_cleanup
;
2363 host_priv
->rst_link
= rstc
;
2365 rstc
= devm_reset_control_get(&ofdev
->dev
, "phy");
2367 retval
= PTR_ERR(rstc
);
2368 goto error_exit_with_cleanup
;
2370 host_priv
->rst_phy
= rstc
;
2372 /* allocate host structure */
2373 host
= ata_host_alloc_pinfo(&ofdev
->dev
, ppi
, n_ports
);
2377 goto error_exit_with_cleanup
;
2379 host
->private_data
= host_priv
;
2380 host
->iomap
= port_base
;
2382 /* initialize core locking and queues */
2383 init_waitqueue_head(&host_priv
->fast_wait_queue
);
2384 init_waitqueue_head(&host_priv
->scsi_wait_queue
);
2385 spin_lock_init(&host_priv
->phy_lock
);
2386 spin_lock_init(&host_priv
->core_lock
);
2387 host_priv
->core_locked
= 0;
2388 host_priv
->reentrant_port_no
= -1;
2389 host_priv
->hw_lock_count
= 0;
2390 host_priv
->direct_lock_count
= 0;
2391 host_priv
->locker_uid
= 0;
2392 host_priv
->current_locker_type
= SATA_UNLOCKED
;
2393 host_priv
->isr_arg
= NULL
;
2394 host_priv
->isr_callback
= NULL
;
2396 /* initialize host controller */
2397 retval
= sata_oxnas_init_controller(host
);
2399 goto error_exit_with_cleanup
;
2402 * Now, register with libATA core, this will also initiate the
2403 * device discovery process, invoking our port_start() handler &
2404 * error_handler() to execute a dummy softreset EH session
2406 ata_host_activate(host
, irq
, sata_oxnas_interrupt
, SATA_OXNAS_IRQ_FLAG
,
2411 error_exit_with_cleanup
:
2413 irq_dispose_mapping(host_priv
->irq
);
2417 ata_host_detach(host
);
2421 iounmap(sgdma_base
);
2430 static int sata_oxnas_remove(struct platform_device
*ofdev
)
2432 struct ata_host
*host
= dev_get_drvdata(&ofdev
->dev
);
2433 struct sata_oxnas_host_priv
*host_priv
= host
->private_data
;
2435 ata_host_detach(host
);
2437 irq_dispose_mapping(host_priv
->irq
);
2438 iounmap(host_priv
->port_base
);
2439 iounmap(host_priv
->sgdma_base
);
2440 iounmap(host_priv
->core_base
);
2442 /* reset Controller, Link and PHY */
2443 reset_control_assert(host_priv
->rst_sata
);
2444 reset_control_assert(host_priv
->rst_link
);
2445 reset_control_assert(host_priv
->rst_phy
);
2447 /* Disable the clock to the SATA block */
2448 clk_disable_unprepare(host_priv
->clk
);
2449 clk_put(host_priv
->clk
);
2455 static int sata_oxnas_suspend(struct platform_device
*op
, pm_message_t state
)
2457 struct ata_host
*host
= dev_get_drvdata(&op
->dev
);
2459 return ata_host_suspend(host
, state
);
2462 static int sata_oxnas_resume(struct platform_device
*op
)
2464 struct ata_host
*host
= dev_get_drvdata(&op
->dev
);
2467 ret
= sata_oxnas_init_controller(host
);
2469 dev_err(&op
->dev
, "Error initializing hardware\n");
2472 ata_host_resume(host
);
2479 static struct of_device_id oxnas_sata_match
[] = {
2481 .compatible
= "plxtech,nas782x-sata",
2486 MODULE_DEVICE_TABLE(of
, oxnas_sata_match
);
2488 static struct platform_driver oxnas_sata_driver
= {
2490 .name
= "oxnas-sata",
2491 .owner
= THIS_MODULE
,
2492 .of_match_table
= oxnas_sata_match
,
2494 .probe
= sata_oxnas_probe
,
2495 .remove
= sata_oxnas_remove
,
2497 .suspend
= sata_oxnas_suspend
,
2498 .resume
= sata_oxnas_resume
,
2502 module_platform_driver(oxnas_sata_driver
);
2504 MODULE_LICENSE("GPL");
2505 MODULE_VERSION("1.0");
2506 MODULE_AUTHOR("Oxford Semiconductor Ltd.");
2507 MODULE_DESCRIPTION("low-level driver for Oxford 934 SATA core");