1 #include <linux/irqdomain.h>
4 #include <linux/of_address.h>
5 #include <linux/of_irq.h>
6 #include <linux/irqchip/chained_irq.h>
9 #include <linux/irqchip.h>
11 struct rps_chip_data
{
14 struct irq_domain
*domain
;
29 * Routines to acknowledge, disable and enable interrupts
31 static void rps_mask_irq(struct irq_data
*d
)
33 struct rps_chip_data
*chip_data
= irq_data_get_irq_chip_data(d
);
34 u32 mask
= BIT(d
->hwirq
);
36 iowrite32(mask
, chip_data
->base
+ RPS_MASK
);
39 static void rps_unmask_irq(struct irq_data
*d
)
41 struct rps_chip_data
*chip_data
= irq_data_get_irq_chip_data(d
);
42 u32 mask
= BIT(d
->hwirq
);
44 iowrite32(mask
, chip_data
->base
+ RPS_UNMASK
);
47 static struct irq_chip rps_chip
= {
49 .irq_mask
= rps_mask_irq
,
50 .irq_unmask
= rps_unmask_irq
,
53 static int rps_irq_domain_xlate(struct irq_domain
*d
,
54 struct device_node
*controller
,
55 const u32
*intspec
, unsigned int intsize
,
56 unsigned long *out_hwirq
,
57 unsigned int *out_type
)
59 if (irq_domain_get_of_node(d
) != controller
)
64 *out_hwirq
= intspec
[0];
65 /* Honestly I do not know the type */
66 *out_type
= IRQ_TYPE_LEVEL_HIGH
;
71 static int rps_irq_domain_map(struct irq_domain
*d
, unsigned int irq
,
74 irq_set_chip_and_handler(irq
, &rps_chip
, handle_level_irq
);
76 irq_set_chip_data(irq
, d
->host_data
);
80 const struct irq_domain_ops rps_irq_domain_ops
= {
81 .map
= rps_irq_domain_map
,
82 .xlate
= rps_irq_domain_xlate
,
85 static void rps_handle_cascade_irq(struct irq_desc
*desc
)
87 struct rps_chip_data
*chip_data
= irq_desc_get_handler_data(desc
);
88 struct irq_chip
*chip
= irq_desc_get_chip(desc
);
89 unsigned int cascade_irq
, rps_irq
;
92 chained_irq_enter(chip
, desc
);
94 status
= ioread32(chip_data
->base
+ RPS_STATUS
);
95 rps_irq
= __ffs(status
);
96 cascade_irq
= irq_find_mapping(chip_data
->domain
, rps_irq
);
98 if (unlikely(rps_irq
>= RPS_IRQ_COUNT
))
101 generic_handle_irq(cascade_irq
);
103 chained_irq_exit(chip
, desc
);
107 int __init
rps_of_init(struct device_node
*node
, struct device_node
*parent
)
109 void __iomem
*rps_base
;
110 int irq_start
= RPS_IRQ_BASE
;
117 rps_base
= of_iomap(node
, 0);
118 WARN(!rps_base
, "unable to map rps registers\n");
119 rps_data
.base
= rps_base
;
121 irq_base
= irq_alloc_descs(irq_start
, 0, RPS_IRQ_COUNT
, numa_node_id());
122 if (IS_ERR_VALUE(irq_base
)) {
123 WARN(1, "Cannot allocate irq_descs @ IRQ%d, assuming pre-allocated\n",
125 irq_base
= irq_start
;
128 rps_data
.domain
= irq_domain_add_legacy(node
, RPS_IRQ_COUNT
, irq_base
,
129 PRS_HWIRQ_BASE
, &rps_irq_domain_ops
, &rps_data
);
131 if (WARN_ON(!rps_data
.domain
))
135 irq
= irq_of_parse_and_map(node
, 0);
136 if (irq_set_handler_data(irq
, &rps_data
) != 0)
138 irq_set_chained_handler(irq
, rps_handle_cascade_irq
);
144 IRQCHIP_DECLARE(nas782x
, "plxtech,nas782x-rps", rps_of_init
);