2 * oxnas pinctrl driver based on at91 pinctrl driver
4 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
10 #include <linux/init.h>
11 #include <linux/module.h>
13 #include <linux/of_device.h>
14 #include <linux/of_address.h>
15 #include <linux/of_irq.h>
16 #include <linux/slab.h>
17 #include <linux/interrupt.h>
18 #include <linux/irq.h>
19 #include <linux/irqdomain.h>
20 #include <linux/irqchip/chained_irq.h>
22 #include <linux/gpio.h>
23 #include <linux/pinctrl/machine.h>
24 #include <linux/pinctrl/pinconf.h>
25 #include <linux/pinctrl/pinctrl.h>
26 #include <linux/pinctrl/pinmux.h>
27 /* Since we request GPIOs from ourself */
28 #include <linux/pinctrl/consumer.h>
29 #include <linux/spinlock.h>
30 #include <linux/version.h>
34 #include <mach/utils.h>
36 #define MAX_NB_GPIO_PER_BANK 32
37 #define MAX_GPIO_BANKS 2
39 struct oxnas_gpio_chip
{
40 struct gpio_chip chip
;
41 struct pinctrl_gpio_range range
;
42 void __iomem
*regbase
; /* GPIOA/B virtual address */
43 void __iomem
*ctrlbase
; /* SYS/SEC_CTRL virtual address */
44 struct irq_domain
*domain
; /* associated irq domain */
48 #define to_oxnas_gpio_chip(c) container_of(c, struct oxnas_gpio_chip, chip)
50 static struct oxnas_gpio_chip
*gpio_chips
[MAX_GPIO_BANKS
];
52 static int gpio_banks
;
54 #define PULL_UP (1 << 0)
55 #define PULL_DOWN (1 << 1)
56 #define DEBOUNCE (1 << 2)
59 * struct oxnas_pmx_func - describes pinmux functions
60 * @name: the name of this specific function
61 * @groups: corresponding pin groups
62 * @ngroups: the number of groups
64 struct oxnas_pmx_func
{
87 OUTPUT_EN_CLEAR
= 0x20,
88 DEBOUNCE_ENABLE
= 0x24,
89 RE_IRQ_ENABLE
= 0x28, /* rising edge */
90 FE_IRQ_ENABLE
= 0x2C, /* falling edge */
91 RE_IRQ_PENDING
= 0x30, /* rising edge */
92 FE_IRQ_PENDING
= 0x34, /* falling edge */
95 PULL_SENSE
= 0x54, /* 1 up, 0 down */
98 DEBOUNCE_MASK
= 0x3FFF0000,
99 /* put hw debounce and soft config at same bit position*/
104 PINMUX_SECONDARY_SEL
= 0x14,
105 PINMUX_TERTIARY_SEL
= 0x8c,
106 PINMUX_QUATERNARY_SEL
= 0x94,
107 PINMUX_DEBUG_SEL
= 0x9c,
108 PINMUX_ALTERNATIVE_SEL
= 0xa4,
109 PINMUX_PULLUP_SEL
= 0xac,
113 * struct oxnas_pmx_pin - describes an pin mux
114 * @bank: the bank of the pin
115 * @pin: the pin number in the @bank
116 * @mux: the mux mode : gpio or periph_x of the pin i.e. alternate function.
117 * @conf: the configuration of the pin: PULL_UP, MULTIDRIVE etc...
119 struct oxnas_pmx_pin
{
127 * struct oxnas_pin_group - describes an pin group
128 * @name: the name of this specific pin group
129 * @pins_conf: the mux mode for each pin in this group. The size of this
130 * array is the same as pins.
131 * @pins: an array of discrete physical pins used in this group, taken
132 * from the driver-local pin enumeration space
133 * @npins: the number of pins in this group array, i.e. the number of
134 * elements in .pins so we can iterate over that array
136 struct oxnas_pin_group
{
138 struct oxnas_pmx_pin
*pins_conf
;
143 struct oxnas_pinctrl
{
145 struct pinctrl_dev
*pctl
;
152 struct oxnas_pmx_func
*functions
;
155 struct oxnas_pin_group
*groups
;
159 static const inline struct oxnas_pin_group
*oxnas_pinctrl_find_group_by_name(
160 const struct oxnas_pinctrl
*info
,
163 const struct oxnas_pin_group
*grp
= NULL
;
166 for (i
= 0; i
< info
->ngroups
; i
++) {
167 if (strcmp(info
->groups
[i
].name
, name
))
170 grp
= &info
->groups
[i
];
171 dev_dbg(info
->dev
, "%s: %d 0:%d\n", name
, grp
->npins
,
179 static int oxnas_get_groups_count(struct pinctrl_dev
*pctldev
)
181 struct oxnas_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
183 return info
->ngroups
;
186 static const char *oxnas_get_group_name(struct pinctrl_dev
*pctldev
,
189 struct oxnas_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
191 return info
->groups
[selector
].name
;
194 static int oxnas_get_group_pins(struct pinctrl_dev
*pctldev
, unsigned selector
,
195 const unsigned **pins
,
198 struct oxnas_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
200 if (selector
>= info
->ngroups
)
203 *pins
= info
->groups
[selector
].pins
;
204 *npins
= info
->groups
[selector
].npins
;
209 static void oxnas_pin_dbg_show(struct pinctrl_dev
*pctldev
, struct seq_file
*s
,
212 seq_printf(s
, "%s", dev_name(pctldev
->dev
));
215 static int oxnas_dt_node_to_map(struct pinctrl_dev
*pctldev
,
216 struct device_node
*np
,
217 struct pinctrl_map
**map
, unsigned *num_maps
)
219 struct oxnas_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
220 const struct oxnas_pin_group
*grp
;
221 struct pinctrl_map
*new_map
;
222 struct device_node
*parent
;
227 * first find the group of this node and check if we need create
228 * config maps for pins
230 grp
= oxnas_pinctrl_find_group_by_name(info
, np
->name
);
232 dev_err(info
->dev
, "unable to find group for node %s\n",
237 map_num
+= grp
->npins
;
238 new_map
= devm_kzalloc(pctldev
->dev
, sizeof(*new_map
) * map_num
,
247 parent
= of_get_parent(np
);
249 devm_kfree(pctldev
->dev
, new_map
);
252 new_map
[0].type
= PIN_MAP_TYPE_MUX_GROUP
;
253 new_map
[0].data
.mux
.function
= parent
->name
;
254 new_map
[0].data
.mux
.group
= np
->name
;
257 /* create config map */
259 for (i
= 0; i
< grp
->npins
; i
++) {
260 new_map
[i
].type
= PIN_MAP_TYPE_CONFIGS_PIN
;
261 new_map
[i
].data
.configs
.group_or_pin
=
262 pin_get_name(pctldev
, grp
->pins
[i
]);
263 new_map
[i
].data
.configs
.configs
= &grp
->pins_conf
[i
].conf
;
264 new_map
[i
].data
.configs
.num_configs
= 1;
267 dev_dbg(pctldev
->dev
, "maps: function %s group %s num %d\n",
268 (*map
)->data
.mux
.function
, (*map
)->data
.mux
.group
, map_num
);
273 static void oxnas_dt_free_map(struct pinctrl_dev
*pctldev
,
274 struct pinctrl_map
*map
, unsigned num_maps
)
278 static const struct pinctrl_ops oxnas_pctrl_ops
= {
279 .get_groups_count
= oxnas_get_groups_count
,
280 .get_group_name
= oxnas_get_group_name
,
281 .get_group_pins
= oxnas_get_group_pins
,
282 .pin_dbg_show
= oxnas_pin_dbg_show
,
283 .dt_node_to_map
= oxnas_dt_node_to_map
,
284 .dt_free_map
= oxnas_dt_free_map
,
287 static void __iomem
*pin_to_gpioctrl(struct oxnas_pinctrl
*info
,
290 return gpio_chips
[bank
]->regbase
;
293 static void __iomem
*pin_to_muxctrl(struct oxnas_pinctrl
*info
,
296 return gpio_chips
[bank
]->ctrlbase
;
300 static inline int pin_to_bank(unsigned pin
)
302 return pin
/ MAX_NB_GPIO_PER_BANK
;
305 static unsigned pin_to_mask(unsigned int pin
)
310 static void oxnas_mux_disable_interrupt(void __iomem
*pio
, unsigned mask
)
312 oxnas_register_clear_mask(pio
+ RE_IRQ_ENABLE
, mask
);
313 oxnas_register_clear_mask(pio
+ FE_IRQ_ENABLE
, mask
);
316 static unsigned oxnas_mux_get_pullup(void __iomem
*pio
, unsigned pin
)
318 return (readl_relaxed(pio
+ PULL_ENABLE
) & BIT(pin
)) &&
319 (readl_relaxed(pio
+ PULL_SENSE
) & BIT(pin
));
322 static void oxnas_mux_set_pullup(void __iomem
*pio
, unsigned mask
, bool on
)
325 oxnas_register_set_mask(pio
+ PULL_SENSE
, mask
);
326 oxnas_register_set_mask(pio
+ PULL_ENABLE
, mask
);
328 oxnas_register_clear_mask(pio
+ PULL_ENABLE
, mask
);
332 static bool oxnas_mux_get_pulldown(void __iomem
*pio
, unsigned pin
)
334 return (readl_relaxed(pio
+ PULL_ENABLE
) & BIT(pin
)) &&
335 (!(readl_relaxed(pio
+ PULL_SENSE
) & BIT(pin
)));
338 static void oxnas_mux_set_pulldown(void __iomem
*pio
, unsigned mask
, bool on
)
341 oxnas_register_clear_mask(pio
+ PULL_SENSE
, mask
);
342 oxnas_register_set_mask(pio
+ PULL_ENABLE
, mask
);
344 oxnas_register_clear_mask(pio
+ PULL_ENABLE
, mask
);
348 /* unfortunately debounce control are shared */
349 static bool oxnas_mux_get_debounce(void __iomem
*pio
, unsigned pin
, u32
*div
)
351 *div
= __raw_readl(pio
+ CLOCK_DIV
) & DEBOUNCE_MASK
;
352 return __raw_readl(pio
+ DEBOUNCE_ENABLE
) & BIT(pin
);
355 static void oxnas_mux_set_debounce(void __iomem
*pio
, unsigned mask
,
359 oxnas_register_value_mask(pio
+ CLOCK_DIV
, DEBOUNCE_MASK
, div
);
360 oxnas_register_set_mask(pio
+ DEBOUNCE_ENABLE
, mask
);
362 oxnas_register_clear_mask(pio
+ DEBOUNCE_ENABLE
, mask
);
367 static void oxnas_mux_set_func2(void __iomem
*cio
, unsigned mask
)
369 /* in fact, SECONDARY takes precedence, so clear others is not necessary */
370 oxnas_register_set_mask(cio
+ PINMUX_SECONDARY_SEL
, mask
);
371 oxnas_register_clear_mask(cio
+ PINMUX_TERTIARY_SEL
, mask
);
372 oxnas_register_clear_mask(cio
+ PINMUX_QUATERNARY_SEL
, mask
);
373 oxnas_register_clear_mask(cio
+ PINMUX_DEBUG_SEL
, mask
);
374 oxnas_register_clear_mask(cio
+ PINMUX_ALTERNATIVE_SEL
, mask
);
377 static void oxnas_mux_set_func3(void __iomem
*cio
, unsigned mask
)
379 oxnas_register_clear_mask(cio
+ PINMUX_SECONDARY_SEL
, mask
);
380 oxnas_register_set_mask(cio
+ PINMUX_TERTIARY_SEL
, mask
);
381 oxnas_register_clear_mask(cio
+ PINMUX_QUATERNARY_SEL
, mask
);
382 oxnas_register_clear_mask(cio
+ PINMUX_DEBUG_SEL
, mask
);
383 oxnas_register_clear_mask(cio
+ PINMUX_ALTERNATIVE_SEL
, mask
);
386 static void oxnas_mux_set_func4(void __iomem
*cio
, unsigned mask
)
388 oxnas_register_clear_mask(cio
+ PINMUX_SECONDARY_SEL
, mask
);
389 oxnas_register_clear_mask(cio
+ PINMUX_TERTIARY_SEL
, mask
);
390 oxnas_register_set_mask(cio
+ PINMUX_QUATERNARY_SEL
, mask
);
391 oxnas_register_clear_mask(cio
+ PINMUX_DEBUG_SEL
, mask
);
392 oxnas_register_clear_mask(cio
+ PINMUX_ALTERNATIVE_SEL
, mask
);
395 static void oxnas_mux_set_func_dbg(void __iomem
*cio
, unsigned mask
)
397 oxnas_register_clear_mask(cio
+ PINMUX_SECONDARY_SEL
, mask
);
398 oxnas_register_clear_mask(cio
+ PINMUX_TERTIARY_SEL
, mask
);
399 oxnas_register_clear_mask(cio
+ PINMUX_QUATERNARY_SEL
, mask
);
400 oxnas_register_set_mask(cio
+ PINMUX_DEBUG_SEL
, mask
);
401 oxnas_register_clear_mask(cio
+ PINMUX_ALTERNATIVE_SEL
, mask
);
404 static void oxnas_mux_set_func_alt(void __iomem
*cio
, unsigned mask
)
406 oxnas_register_clear_mask(cio
+ PINMUX_SECONDARY_SEL
, mask
);
407 oxnas_register_clear_mask(cio
+ PINMUX_TERTIARY_SEL
, mask
);
408 oxnas_register_clear_mask(cio
+ PINMUX_QUATERNARY_SEL
, mask
);
409 oxnas_register_clear_mask(cio
+ PINMUX_DEBUG_SEL
, mask
);
410 oxnas_register_set_mask(cio
+ PINMUX_ALTERNATIVE_SEL
, mask
);
413 static void oxnas_mux_set_gpio(void __iomem
*cio
, unsigned mask
)
415 oxnas_register_clear_mask(cio
+ PINMUX_SECONDARY_SEL
, mask
);
416 oxnas_register_clear_mask(cio
+ PINMUX_TERTIARY_SEL
, mask
);
417 oxnas_register_clear_mask(cio
+ PINMUX_QUATERNARY_SEL
, mask
);
418 oxnas_register_clear_mask(cio
+ PINMUX_DEBUG_SEL
, mask
);
419 oxnas_register_clear_mask(cio
+ PINMUX_ALTERNATIVE_SEL
, mask
);
422 static enum oxnas_mux
oxnas_mux_get_func(void __iomem
*cio
, unsigned mask
)
424 if (readl_relaxed(cio
+ PINMUX_SECONDARY_SEL
) & mask
)
425 return OXNAS_PINMUX_FUNC2
;
426 if (readl_relaxed(cio
+ PINMUX_TERTIARY_SEL
) & mask
)
427 return OXNAS_PINMUX_FUNC3
;
428 if (readl_relaxed(cio
+ PINMUX_QUATERNARY_SEL
) & mask
)
429 return OXNAS_PINMUX_FUNC4
;
430 if (readl_relaxed(cio
+ PINMUX_DEBUG_SEL
) & mask
)
431 return OXNAS_PINMUX_DEBUG
;
432 if (readl_relaxed(cio
+ PINMUX_ALTERNATIVE_SEL
) & mask
)
433 return OXNAS_PINMUX_ALT
;
434 return OXNAS_PINMUX_GPIO
;
438 static void oxnas_pin_dbg(const struct device
*dev
,
439 const struct oxnas_pmx_pin
*pin
)
443 "MF_%c%d configured as periph%c with conf = 0x%lu\n",
444 pin
->bank
+ 'A', pin
->pin
, pin
->mux
- 1 + 'A',
447 dev_dbg(dev
, "MF_%c%d configured as gpio with conf = 0x%lu\n",
448 pin
->bank
+ 'A', pin
->pin
, pin
->conf
);
452 static int pin_check_config(struct oxnas_pinctrl
*info
, const char *name
,
453 int index
, const struct oxnas_pmx_pin
*pin
)
457 /* check if it's a valid config */
458 if (pin
->bank
>= info
->nbanks
) {
459 dev_err(info
->dev
, "%s: pin conf %d bank_id %d >= nbanks %d\n",
460 name
, index
, pin
->bank
, info
->nbanks
);
464 if (pin
->pin
>= MAX_NB_GPIO_PER_BANK
) {
465 dev_err(info
->dev
, "%s: pin conf %d pin_bank_id %d >= %d\n",
466 name
, index
, pin
->pin
, MAX_NB_GPIO_PER_BANK
);
469 /* gpio always allowed */
475 if (mux
>= info
->nmux
) {
476 dev_err(info
->dev
, "%s: pin conf %d mux_id %d >= nmux %d\n",
477 name
, index
, mux
, info
->nmux
);
481 if (!(info
->mux_mask
[pin
->bank
* info
->nmux
+ mux
] & 1 << pin
->pin
)) {
482 dev_err(info
->dev
, "%s: pin conf %d mux_id %d not supported for MF_%c%d\n",
483 name
, index
, mux
, pin
->bank
+ 'A', pin
->pin
);
490 static void oxnas_mux_gpio_enable(void __iomem
*cio
, void __iomem
*pio
,
491 unsigned mask
, bool input
)
493 oxnas_mux_set_gpio(cio
, mask
);
495 writel_relaxed(mask
, pio
+ OUTPUT_EN_CLEAR
);
497 writel_relaxed(mask
, pio
+ OUTPUT_EN_SET
);
500 static void oxnas_mux_gpio_disable(void __iomem
*cio
, void __iomem
*pio
,
503 /* when switch to other function, gpio is disabled automatically */
507 static int oxnas_pmx_set_mux(struct pinctrl_dev
*pctldev
, unsigned selector
,
510 struct oxnas_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
511 const struct oxnas_pmx_pin
*pins_conf
= info
->groups
[group
].pins_conf
;
512 const struct oxnas_pmx_pin
*pin
;
513 uint32_t npins
= info
->groups
[group
].npins
;
519 dev_dbg(info
->dev
, "enable function %s group %s\n",
520 info
->functions
[selector
].name
, info
->groups
[group
].name
);
522 /* first check that all the pins of the group are valid with a valid
524 for (i
= 0; i
< npins
; i
++) {
526 ret
= pin_check_config(info
, info
->groups
[group
].name
, i
, pin
);
531 for (i
= 0; i
< npins
; i
++) {
533 oxnas_pin_dbg(info
->dev
, pin
);
535 pio
= pin_to_gpioctrl(info
, pin
->bank
);
536 cio
= pin_to_muxctrl(info
, pin
->bank
);
538 mask
= pin_to_mask(pin
->pin
);
539 oxnas_mux_disable_interrupt(pio
, mask
);
542 case OXNAS_PINMUX_GPIO
:
543 oxnas_mux_gpio_enable(cio
, pio
, mask
, 1);
545 case OXNAS_PINMUX_FUNC2
:
546 oxnas_mux_set_func2(cio
, mask
);
548 case OXNAS_PINMUX_FUNC3
:
549 oxnas_mux_set_func3(cio
, mask
);
551 case OXNAS_PINMUX_FUNC4
:
552 oxnas_mux_set_func4(cio
, mask
);
554 case OXNAS_PINMUX_DEBUG
:
555 oxnas_mux_set_func_dbg(cio
, mask
);
557 case OXNAS_PINMUX_ALT
:
558 oxnas_mux_set_func_alt(cio
, mask
);
562 oxnas_mux_gpio_disable(cio
, pio
, mask
);
568 static int oxnas_pmx_get_funcs_count(struct pinctrl_dev
*pctldev
)
570 struct oxnas_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
572 return info
->nfunctions
;
575 static const char *oxnas_pmx_get_func_name(struct pinctrl_dev
*pctldev
,
578 struct oxnas_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
580 return info
->functions
[selector
].name
;
583 static int oxnas_pmx_get_groups(struct pinctrl_dev
*pctldev
, unsigned selector
,
584 const char * const **groups
,
585 unsigned * const num_groups
)
587 struct oxnas_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
589 *groups
= info
->functions
[selector
].groups
;
590 *num_groups
= info
->functions
[selector
].ngroups
;
595 static int oxnas_gpio_request_enable(struct pinctrl_dev
*pctldev
,
596 struct pinctrl_gpio_range
*range
,
599 struct oxnas_pinctrl
*npct
= pinctrl_dev_get_drvdata(pctldev
);
600 struct oxnas_gpio_chip
*oxnas_chip
;
601 struct gpio_chip
*chip
;
605 dev_err(npct
->dev
, "invalid range\n");
609 dev_err(npct
->dev
, "missing GPIO chip in range\n");
613 oxnas_chip
= container_of(chip
, struct oxnas_gpio_chip
, chip
);
615 dev_dbg(npct
->dev
, "enable pin %u as GPIO\n", offset
);
617 mask
= 1 << (offset
- chip
->base
);
619 dev_dbg(npct
->dev
, "enable pin %u as MF_%c%d 0x%x\n",
620 offset
, 'A' + range
->id
, offset
- chip
->base
, mask
);
622 oxnas_mux_set_gpio(oxnas_chip
->ctrlbase
, mask
);
627 static void oxnas_gpio_disable_free(struct pinctrl_dev
*pctldev
,
628 struct pinctrl_gpio_range
*range
,
631 struct oxnas_pinctrl
*npct
= pinctrl_dev_get_drvdata(pctldev
);
633 dev_dbg(npct
->dev
, "disable pin %u as GPIO\n", offset
);
634 /* Set the pin to some default state, GPIO is usually default */
637 static const struct pinmux_ops oxnas_pmx_ops
= {
638 .get_functions_count
= oxnas_pmx_get_funcs_count
,
639 .get_function_name
= oxnas_pmx_get_func_name
,
640 .get_function_groups
= oxnas_pmx_get_groups
,
641 .set_mux
= oxnas_pmx_set_mux
,
642 .gpio_request_enable
= oxnas_gpio_request_enable
,
643 .gpio_disable_free
= oxnas_gpio_disable_free
,
646 static int oxnas_pinconf_get(struct pinctrl_dev
*pctldev
,
647 unsigned pin_id
, unsigned long *config
)
649 struct oxnas_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
654 dev_dbg(info
->dev
, "%s:%d, pin_id=%d, config=0x%lx", __func__
,
655 __LINE__
, pin_id
, *config
);
656 pio
= pin_to_gpioctrl(info
, pin_to_bank(pin_id
));
657 pin
= pin_id
% MAX_NB_GPIO_PER_BANK
;
659 if (oxnas_mux_get_pullup(pio
, pin
))
662 if (oxnas_mux_get_pulldown(pio
, pin
))
663 *config
|= PULL_DOWN
;
665 if (oxnas_mux_get_debounce(pio
, pin
, &div
))
666 *config
|= DEBOUNCE
| div
;
670 static int oxnas_pinconf_set(struct pinctrl_dev
*pctldev
,
671 unsigned pin_id
, unsigned long *configs
,
672 unsigned num_configs
)
674 struct oxnas_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
678 unsigned long config
;
680 pio
= pin_to_gpioctrl(info
, pin_to_bank(pin_id
));
681 mask
= pin_to_mask(pin_id
% MAX_NB_GPIO_PER_BANK
);
683 for (i
= 0; i
< num_configs
; i
++) {
687 "%s:%d, pin_id=%d, config=0x%lx",
688 __func__
, __LINE__
, pin_id
, config
);
690 if ((config
& PULL_UP
) && (config
& PULL_DOWN
))
693 oxnas_mux_set_pullup(pio
, mask
, config
& PULL_UP
);
694 oxnas_mux_set_pulldown(pio
, mask
, config
& PULL_DOWN
);
695 oxnas_mux_set_debounce(pio
, mask
, config
& DEBOUNCE
,
696 config
& DEBOUNCE_MASK
);
698 } /* for each config */
703 static void oxnas_pinconf_dbg_show(struct pinctrl_dev
*pctldev
,
704 struct seq_file
*s
, unsigned pin_id
)
709 static void oxnas_pinconf_group_dbg_show(struct pinctrl_dev
*pctldev
,
710 struct seq_file
*s
, unsigned group
)
714 static const struct pinconf_ops oxnas_pinconf_ops
= {
715 .pin_config_get
= oxnas_pinconf_get
,
716 .pin_config_set
= oxnas_pinconf_set
,
717 .pin_config_dbg_show
= oxnas_pinconf_dbg_show
,
718 .pin_config_group_dbg_show
= oxnas_pinconf_group_dbg_show
,
721 static struct pinctrl_desc oxnas_pinctrl_desc
= {
722 .pctlops
= &oxnas_pctrl_ops
,
723 .pmxops
= &oxnas_pmx_ops
,
724 .confops
= &oxnas_pinconf_ops
,
725 .owner
= THIS_MODULE
,
728 static const char *gpio_compat
= "plxtech,nas782x-gpio";
730 static void oxnas_pinctrl_child_count(struct oxnas_pinctrl
*info
,
731 struct device_node
*np
)
733 struct device_node
*child
;
735 for_each_child_of_node(np
, child
) {
736 if (of_device_is_compatible(child
, gpio_compat
)) {
740 info
->ngroups
+= of_get_child_count(child
);
745 static int oxnas_pinctrl_mux_mask(struct oxnas_pinctrl
*info
,
746 struct device_node
*np
)
752 list
= of_get_property(np
, "plxtech,mux-mask", &size
);
754 dev_err(info
->dev
, "can not read the mux-mask of %d\n", size
);
758 size
/= sizeof(*list
);
759 if (!size
|| size
% info
->nbanks
) {
760 dev_err(info
->dev
, "wrong mux mask array should be by %d\n",
764 info
->nmux
= size
/ info
->nbanks
;
766 info
->mux_mask
= devm_kzalloc(info
->dev
, sizeof(u32
) * size
, GFP_KERNEL
);
767 if (!info
->mux_mask
) {
768 dev_err(info
->dev
, "could not alloc mux_mask\n");
772 ret
= of_property_read_u32_array(np
, "plxtech,mux-mask",
773 info
->mux_mask
, size
);
775 dev_err(info
->dev
, "can not read the mux-mask of %d\n", size
);
779 static int oxnas_pinctrl_parse_groups(struct device_node
*np
,
780 struct oxnas_pin_group
*grp
,
781 struct oxnas_pinctrl
*info
, u32 index
)
783 struct oxnas_pmx_pin
*pin
;
788 dev_dbg(info
->dev
, "group(%d): %s\n", index
, np
->name
);
790 /* Initialise group */
791 grp
->name
= np
->name
;
794 * the binding format is plxtech,pins = <bank pin mux CONFIG ...>,
795 * do sanity check and calculate pins number
797 list
= of_get_property(np
, "plxtech,pins", &size
);
798 /* we do not check return since it's safe node passed down */
799 size
/= sizeof(*list
);
800 if (!size
|| size
% 4) {
801 dev_err(info
->dev
, "wrong pins number or pins and configs"
802 " should be divisible by 4\n");
806 grp
->npins
= size
/ 4;
807 pin
= grp
->pins_conf
= devm_kzalloc(info
->dev
,
808 grp
->npins
* sizeof(struct oxnas_pmx_pin
),
810 grp
->pins
= devm_kzalloc(info
->dev
, grp
->npins
* sizeof(unsigned int),
812 if (!grp
->pins_conf
|| !grp
->pins
)
815 for (i
= 0, j
= 0; i
< size
; i
+= 4, j
++) {
816 pin
->bank
= be32_to_cpu(*list
++);
817 pin
->pin
= be32_to_cpu(*list
++);
818 grp
->pins
[j
] = pin
->bank
* MAX_NB_GPIO_PER_BANK
+ pin
->pin
;
819 pin
->mux
= be32_to_cpu(*list
++);
820 pin
->conf
= be32_to_cpu(*list
++);
822 oxnas_pin_dbg(info
->dev
, pin
);
829 static int oxnas_pinctrl_parse_functions(struct device_node
*np
,
830 struct oxnas_pinctrl
*info
, u32 index
)
832 struct device_node
*child
;
833 struct oxnas_pmx_func
*func
;
834 struct oxnas_pin_group
*grp
;
836 static u32 grp_index
;
839 dev_dbg(info
->dev
, "parse function(%d): %s\n", index
, np
->name
);
841 func
= &info
->functions
[index
];
843 /* Initialise function */
844 func
->name
= np
->name
;
845 func
->ngroups
= of_get_child_count(np
);
846 if (func
->ngroups
<= 0) {
847 dev_err(info
->dev
, "no groups defined\n");
850 func
->groups
= devm_kzalloc(info
->dev
,
851 func
->ngroups
* sizeof(char *), GFP_KERNEL
);
855 for_each_child_of_node(np
, child
) {
856 func
->groups
[i
] = child
->name
;
857 grp
= &info
->groups
[grp_index
++];
858 ret
= oxnas_pinctrl_parse_groups(child
, grp
, info
, i
++);
866 static struct of_device_id oxnas_pinctrl_of_match
[] = {
867 { .compatible
= "plxtech,nas782x-pinctrl"},
871 static int oxnas_pinctrl_probe_dt(struct platform_device
*pdev
,
872 struct oxnas_pinctrl
*info
)
877 struct device_node
*np
= pdev
->dev
.of_node
;
878 struct device_node
*child
;
883 info
->dev
= &pdev
->dev
;
885 oxnas_pinctrl_child_count(info
, np
);
887 if (info
->nbanks
< 1) {
888 dev_err(&pdev
->dev
, "you need to specify atleast one gpio-controller\n");
892 ret
= oxnas_pinctrl_mux_mask(info
, np
);
896 dev_dbg(&pdev
->dev
, "nmux = %d\n", info
->nmux
);
898 dev_dbg(&pdev
->dev
, "mux-mask\n");
899 tmp
= info
->mux_mask
;
900 for (i
= 0; i
< info
->nbanks
; i
++)
901 for (j
= 0; j
< info
->nmux
; j
++, tmp
++)
902 dev_dbg(&pdev
->dev
, "%d:%d\t0x%x\n", i
, j
, tmp
[0]);
904 dev_dbg(&pdev
->dev
, "nfunctions = %d\n", info
->nfunctions
);
905 dev_dbg(&pdev
->dev
, "ngroups = %d\n", info
->ngroups
);
906 info
->functions
= devm_kzalloc(&pdev
->dev
, info
->nfunctions
*
907 sizeof(struct oxnas_pmx_func
),
909 if (!info
->functions
)
912 info
->groups
= devm_kzalloc(&pdev
->dev
, info
->ngroups
*
913 sizeof(struct oxnas_pin_group
),
918 dev_dbg(&pdev
->dev
, "nbanks = %d\n", info
->nbanks
);
919 dev_dbg(&pdev
->dev
, "nfunctions = %d\n", info
->nfunctions
);
920 dev_dbg(&pdev
->dev
, "ngroups = %d\n", info
->ngroups
);
924 for_each_child_of_node(np
, child
) {
925 if (of_device_is_compatible(child
, gpio_compat
))
927 ret
= oxnas_pinctrl_parse_functions(child
, info
, i
++);
929 dev_err(&pdev
->dev
, "failed to parse function\n");
937 static int oxnas_pinctrl_probe(struct platform_device
*pdev
)
939 struct oxnas_pinctrl
*info
;
940 struct pinctrl_pin_desc
*pdesc
;
943 info
= devm_kzalloc(&pdev
->dev
, sizeof(*info
), GFP_KERNEL
);
947 ret
= oxnas_pinctrl_probe_dt(pdev
, info
);
952 * We need all the GPIO drivers to probe FIRST, or we will not be able
953 * to obtain references to the struct gpio_chip * for them, and we
954 * need this to proceed.
956 for (i
= 0; i
< info
->nbanks
; i
++) {
957 if (!gpio_chips
[i
]) {
959 "GPIO chip %d not registered yet\n", i
);
960 devm_kfree(&pdev
->dev
, info
);
961 return -EPROBE_DEFER
;
965 oxnas_pinctrl_desc
.name
= dev_name(&pdev
->dev
);
966 oxnas_pinctrl_desc
.npins
= info
->nbanks
* MAX_NB_GPIO_PER_BANK
;
967 oxnas_pinctrl_desc
.pins
= pdesc
=
968 devm_kzalloc(&pdev
->dev
, sizeof(*pdesc
) *
969 oxnas_pinctrl_desc
.npins
, GFP_KERNEL
);
971 if (!oxnas_pinctrl_desc
.pins
)
974 for (i
= 0 , k
= 0; i
< info
->nbanks
; i
++) {
975 for (j
= 0; j
< MAX_NB_GPIO_PER_BANK
; j
++, k
++) {
977 pdesc
->name
= kasprintf(GFP_KERNEL
, "MF_%c%d", i
+ 'A',
983 platform_set_drvdata(pdev
, info
);
984 info
->pctl
= pinctrl_register(&oxnas_pinctrl_desc
, &pdev
->dev
, info
);
987 dev_err(&pdev
->dev
, "could not register OX820 pinctrl driver\n");
992 /* We will handle a range of GPIO pins */
993 for (i
= 0; i
< info
->nbanks
; i
++)
994 pinctrl_add_gpio_range(info
->pctl
, &gpio_chips
[i
]->range
);
996 dev_info(&pdev
->dev
, "initialized OX820 pinctrl driver\n");
1004 static int oxnas_pinctrl_remove(struct platform_device
*pdev
)
1006 struct oxnas_pinctrl
*info
= platform_get_drvdata(pdev
);
1008 pinctrl_unregister(info
->pctl
);
1013 static int oxnas_gpio_request(struct gpio_chip
*chip
, unsigned offset
)
1016 * Map back to global GPIO space and request muxing, the direction
1017 * parameter does not matter for this controller.
1019 int gpio
= chip
->base
+ offset
;
1020 int bank
= chip
->base
/ chip
->ngpio
;
1022 dev_dbg(chip
->dev
, "%s:%d MF_%c%d(%d)\n", __func__
, __LINE__
,
1023 'A' + bank
, offset
, gpio
);
1025 return pinctrl_request_gpio(gpio
);
1028 static void oxnas_gpio_free(struct gpio_chip
*chip
, unsigned offset
)
1030 int gpio
= chip
->base
+ offset
;
1032 pinctrl_free_gpio(gpio
);
1035 static int oxnas_gpio_direction_input(struct gpio_chip
*chip
, unsigned offset
)
1037 struct oxnas_gpio_chip
*oxnas_gpio
= to_oxnas_gpio_chip(chip
);
1038 void __iomem
*pio
= oxnas_gpio
->regbase
;
1040 writel_relaxed(BIT(offset
), pio
+ OUTPUT_EN_CLEAR
);
1044 static int oxnas_gpio_get(struct gpio_chip
*chip
, unsigned offset
)
1046 struct oxnas_gpio_chip
*oxnas_gpio
= to_oxnas_gpio_chip(chip
);
1047 void __iomem
*pio
= oxnas_gpio
->regbase
;
1048 unsigned mask
= 1 << offset
;
1051 pdsr
= readl_relaxed(pio
+ INPUT_VALUE
);
1052 return (pdsr
& mask
) != 0;
1055 static void oxnas_gpio_set(struct gpio_chip
*chip
, unsigned offset
,
1058 struct oxnas_gpio_chip
*oxnas_gpio
= to_oxnas_gpio_chip(chip
);
1059 void __iomem
*pio
= oxnas_gpio
->regbase
;
1062 writel_relaxed(BIT(offset
), pio
+ OUTPUT_SET
);
1064 writel_relaxed(BIT(offset
), pio
+ OUTPUT_CLEAR
);
1068 static int oxnas_gpio_direction_output(struct gpio_chip
*chip
, unsigned offset
,
1071 struct oxnas_gpio_chip
*oxnas_gpio
= to_oxnas_gpio_chip(chip
);
1072 void __iomem
*pio
= oxnas_gpio
->regbase
;
1075 writel_relaxed(BIT(offset
), pio
+ OUTPUT_SET
);
1077 writel_relaxed(BIT(offset
), pio
+ OUTPUT_CLEAR
);
1079 writel_relaxed(BIT(offset
), pio
+ OUTPUT_EN_SET
);
1084 static int oxnas_gpio_to_irq(struct gpio_chip
*chip
, unsigned offset
)
1086 struct oxnas_gpio_chip
*oxnas_gpio
= to_oxnas_gpio_chip(chip
);
1089 if (offset
< chip
->ngpio
)
1090 virq
= irq_create_mapping(oxnas_gpio
->domain
, offset
);
1094 dev_dbg(chip
->dev
, "%s: request IRQ for GPIO %d, return %d\n",
1095 chip
->label
, offset
+ chip
->base
, virq
);
1099 #ifdef CONFIG_DEBUG_FS
1100 static void oxnas_gpio_dbg_show(struct seq_file
*s
, struct gpio_chip
*chip
)
1102 enum oxnas_mux mode
;
1104 struct oxnas_gpio_chip
*oxnas_gpio
= to_oxnas_gpio_chip(chip
);
1105 void __iomem
*pio
= oxnas_gpio
->regbase
;
1106 void __iomem
*cio
= oxnas_gpio
->ctrlbase
;
1108 for (i
= 0; i
< chip
->ngpio
; i
++) {
1109 unsigned pin
= chip
->base
+ i
;
1110 unsigned mask
= pin_to_mask(pin
);
1111 const char *gpio_label
;
1114 gpio_label
= gpiochip_is_requested(chip
, i
);
1118 mode
= oxnas_mux_get_func(cio
, mask
);
1119 seq_printf(s
, "[%s] GPIO%s%d: ",
1120 gpio_label
, chip
->label
, i
);
1121 if (mode
== OXNAS_PINMUX_GPIO
) {
1122 pdsr
= readl_relaxed(pio
+ INPUT_VALUE
);
1124 seq_printf(s
, "[gpio] %s\n",
1128 seq_printf(s
, "[periph %c]\n",
1134 #define oxnas_gpio_dbg_show NULL
1137 /* Several AIC controller irqs are dispatched through this GPIO handler.
1138 * To use any AT91_PIN_* as an externally triggered IRQ, first call
1139 * oxnas_set_gpio_input() then maybe enable its glitch filter.
1140 * Then just request_irq() with the pin ID; it works like any ARM IRQ
1144 static void gpio_irq_mask(struct irq_data
*d
)
1146 struct oxnas_gpio_chip
*oxnas_gpio
= irq_data_get_irq_chip_data(d
);
1147 void __iomem
*pio
= oxnas_gpio
->regbase
;
1148 unsigned mask
= 1 << d
->hwirq
;
1149 unsigned type
= irqd_get_trigger_type(d
);
1150 unsigned long flags
;
1152 if (!(type
& IRQ_TYPE_EDGE_BOTH
))
1155 spin_lock_irqsave(&oxnas_gpio
->lock
, flags
);
1156 if (type
& IRQ_TYPE_EDGE_RISING
)
1157 oxnas_register_clear_mask(pio
+ RE_IRQ_ENABLE
, mask
);
1158 if (type
& IRQ_TYPE_EDGE_FALLING
)
1159 oxnas_register_clear_mask(pio
+ FE_IRQ_ENABLE
, mask
);
1160 spin_unlock_irqrestore(&oxnas_gpio
->lock
, flags
);
1163 static void gpio_irq_unmask(struct irq_data
*d
)
1165 struct oxnas_gpio_chip
*oxnas_gpio
= irq_data_get_irq_chip_data(d
);
1166 void __iomem
*pio
= oxnas_gpio
->regbase
;
1167 unsigned mask
= 1 << d
->hwirq
;
1168 unsigned type
= irqd_get_trigger_type(d
);
1169 unsigned long flags
;
1171 if (!(type
& IRQ_TYPE_EDGE_BOTH
))
1174 spin_lock_irqsave(&oxnas_gpio
->lock
, flags
);
1175 if (type
& IRQ_TYPE_EDGE_RISING
)
1176 oxnas_register_set_mask(pio
+ RE_IRQ_ENABLE
, mask
);
1177 if (type
& IRQ_TYPE_EDGE_FALLING
)
1178 oxnas_register_set_mask(pio
+ FE_IRQ_ENABLE
, mask
);
1179 spin_unlock_irqrestore(&oxnas_gpio
->lock
, flags
);
1183 static int gpio_irq_type(struct irq_data
*d
, unsigned type
)
1185 if ((type
& IRQ_TYPE_EDGE_BOTH
) == 0) {
1186 pr_warn("OX820: Unsupported type for irq %d\n",
1187 gpio_to_irq(d
->irq
));
1190 /* seems no way to set trigger type without enable irq, so leave it to unmask time */
1195 static struct irq_chip gpio_irqchip
= {
1197 .irq_disable
= gpio_irq_mask
,
1198 .irq_mask
= gpio_irq_mask
,
1199 .irq_unmask
= gpio_irq_unmask
,
1200 .irq_set_type
= gpio_irq_type
,
1203 #if LINUX_VERSION_CODE < KERNEL_VERSION(4,2,0)
1204 static void gpio_irq_handler(unsigned irq
, struct irq_desc
*desc
)
1206 static void gpio_irq_handler(struct irq_desc
*desc
)
1209 struct irq_chip
*chip
= irq_desc_get_chip(desc
);
1210 struct irq_data
*idata
= irq_desc_get_irq_data(desc
);
1211 struct oxnas_gpio_chip
*oxnas_gpio
= irq_data_get_irq_chip_data(idata
);
1212 void __iomem
*pio
= oxnas_gpio
->regbase
;
1216 chained_irq_enter(chip
, desc
);
1218 /* TODO: see if it works */
1219 isr
= readl_relaxed(pio
+ IRQ_PENDING
);
1222 /* acks pending interrupts */
1223 writel_relaxed(isr
, pio
+ IRQ_PENDING
);
1225 for_each_set_bit(n
, &isr
, BITS_PER_LONG
) {
1226 generic_handle_irq(irq_find_mapping(oxnas_gpio
->domain
,
1230 chained_irq_exit(chip
, desc
);
1231 /* now it may re-trigger */
1235 * This lock class tells lockdep that GPIO irqs are in a different
1236 * category than their parents, so it won't report false recursion.
1238 static struct lock_class_key gpio_lock_class
;
1240 static int oxnas_gpio_irq_map(struct irq_domain
*h
, unsigned int virq
,
1243 struct oxnas_gpio_chip
*oxnas_gpio
= h
->host_data
;
1245 irq_set_lockdep_class(virq
, &gpio_lock_class
);
1247 irq_set_chip_and_handler(virq
, &gpio_irqchip
, handle_edge_irq
);
1248 #if LINUX_VERSION_CODE < KERNEL_VERSION(4,2,0)
1249 set_irq_flags(virq
, IRQF_VALID
);
1251 irq_set_chip_data(virq
, oxnas_gpio
);
1256 static int oxnas_gpio_irq_domain_xlate(struct irq_domain
*d
,
1257 struct device_node
*ctrlr
,
1259 unsigned int intsize
,
1260 irq_hw_number_t
*out_hwirq
,
1261 unsigned int *out_type
)
1263 struct oxnas_gpio_chip
*oxnas_gpio
= d
->host_data
;
1265 int pin
= oxnas_gpio
->chip
.base
+ intspec
[0];
1267 if (WARN_ON(intsize
< 2))
1269 *out_hwirq
= intspec
[0];
1270 *out_type
= intspec
[1] & IRQ_TYPE_SENSE_MASK
;
1272 ret
= gpio_request(pin
, ctrlr
->full_name
);
1276 ret
= gpio_direction_input(pin
);
1283 static struct irq_domain_ops oxnas_gpio_ops
= {
1284 .map
= oxnas_gpio_irq_map
,
1285 .xlate
= oxnas_gpio_irq_domain_xlate
,
1288 static int oxnas_gpio_of_irq_setup(struct device_node
*node
,
1289 struct oxnas_gpio_chip
*oxnas_gpio
,
1292 /* Disable irqs of this controller */
1293 writel_relaxed(0, oxnas_gpio
->regbase
+ RE_IRQ_ENABLE
);
1294 writel_relaxed(0, oxnas_gpio
->regbase
+ FE_IRQ_ENABLE
);
1296 /* Setup irq domain */
1297 oxnas_gpio
->domain
= irq_domain_add_linear(node
, oxnas_gpio
->chip
.ngpio
,
1298 &oxnas_gpio_ops
, oxnas_gpio
);
1299 if (!oxnas_gpio
->domain
)
1300 panic("oxnas_gpio: couldn't allocate irq domain (DT).\n");
1302 irq_set_chip_data(irq
, oxnas_gpio
);
1303 irq_set_chained_handler(irq
, gpio_irq_handler
);
1308 /* This structure is replicated for each GPIO block allocated at probe time */
1309 static struct gpio_chip oxnas_gpio_template
= {
1310 .request
= oxnas_gpio_request
,
1311 .free
= oxnas_gpio_free
,
1312 .direction_input
= oxnas_gpio_direction_input
,
1313 .get
= oxnas_gpio_get
,
1314 .direction_output
= oxnas_gpio_direction_output
,
1315 .set
= oxnas_gpio_set
,
1316 .to_irq
= oxnas_gpio_to_irq
,
1317 .dbg_show
= oxnas_gpio_dbg_show
,
1319 .ngpio
= MAX_NB_GPIO_PER_BANK
,
1322 static struct of_device_id oxnas_gpio_of_match
[] = {
1323 { .compatible
= "plxtech,nas782x-gpio"},
1327 static int oxnas_gpio_probe(struct platform_device
*pdev
)
1329 struct device_node
*np
= pdev
->dev
.of_node
;
1330 struct resource
*res
;
1331 struct oxnas_gpio_chip
*oxnas_chip
= NULL
;
1332 struct gpio_chip
*chip
;
1333 struct pinctrl_gpio_range
*range
;
1336 int alias_idx
= of_alias_get_id(np
, "gpio");
1340 BUG_ON(alias_idx
>= ARRAY_SIZE(gpio_chips
));
1341 if (gpio_chips
[alias_idx
]) {
1346 irq
= platform_get_irq(pdev
, 0);
1352 oxnas_chip
= devm_kzalloc(&pdev
->dev
, sizeof(*oxnas_chip
), GFP_KERNEL
);
1358 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1359 oxnas_chip
->regbase
= devm_ioremap_resource(&pdev
->dev
, res
);
1360 if (IS_ERR(oxnas_chip
->regbase
)) {
1361 ret
= PTR_ERR(oxnas_chip
->regbase
);
1365 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 1);
1366 oxnas_chip
->ctrlbase
= devm_ioremap_resource(&pdev
->dev
, res
);
1367 if (IS_ERR(oxnas_chip
->ctrlbase
)) {
1368 ret
= PTR_ERR(oxnas_chip
->ctrlbase
);
1372 oxnas_chip
->chip
= oxnas_gpio_template
;
1374 spin_lock_init(&oxnas_chip
->lock
);
1376 chip
= &oxnas_chip
->chip
;
1378 chip
->label
= dev_name(&pdev
->dev
);
1379 chip
->dev
= &pdev
->dev
;
1380 chip
->owner
= THIS_MODULE
;
1381 chip
->base
= alias_idx
* MAX_NB_GPIO_PER_BANK
;
1383 if (!of_property_read_u32(np
, "#gpio-lines", &ngpio
)) {
1384 if (ngpio
> MAX_NB_GPIO_PER_BANK
)
1385 pr_err("oxnas_gpio.%d, gpio-nb >= %d failback to %d\n",
1386 alias_idx
, MAX_NB_GPIO_PER_BANK
,
1387 MAX_NB_GPIO_PER_BANK
);
1389 chip
->ngpio
= ngpio
;
1392 names
= devm_kzalloc(&pdev
->dev
, sizeof(char *) * chip
->ngpio
,
1400 for (i
= 0; i
< chip
->ngpio
; i
++)
1401 names
[i
] = kasprintf(GFP_KERNEL
, "MF_%c%d", alias_idx
+ 'A', i
);
1403 chip
->names
= (const char *const *)names
;
1405 range
= &oxnas_chip
->range
;
1406 range
->name
= chip
->label
;
1407 range
->id
= alias_idx
;
1408 range
->pin_base
= range
->base
= range
->id
* MAX_NB_GPIO_PER_BANK
;
1410 range
->npins
= chip
->ngpio
;
1413 ret
= gpiochip_add(chip
);
1417 gpio_chips
[alias_idx
] = oxnas_chip
;
1418 gpio_banks
= max(gpio_banks
, alias_idx
+ 1);
1420 oxnas_gpio_of_irq_setup(np
, oxnas_chip
, irq
);
1422 dev_info(&pdev
->dev
, "at address %p\n", oxnas_chip
->regbase
);
1426 dev_err(&pdev
->dev
, "Failure %i for GPIO %i\n", ret
, alias_idx
);
1431 static struct platform_driver oxnas_gpio_driver
= {
1433 .name
= "gpio-oxnas",
1434 .owner
= THIS_MODULE
,
1435 .of_match_table
= of_match_ptr(oxnas_gpio_of_match
),
1437 .probe
= oxnas_gpio_probe
,
1440 static struct platform_driver oxnas_pinctrl_driver
= {
1442 .name
= "pinctrl-oxnas",
1443 .owner
= THIS_MODULE
,
1444 .of_match_table
= of_match_ptr(oxnas_pinctrl_of_match
),
1446 .probe
= oxnas_pinctrl_probe
,
1447 .remove
= oxnas_pinctrl_remove
,
1450 static int __init
oxnas_pinctrl_init(void)
1454 ret
= platform_driver_register(&oxnas_gpio_driver
);
1457 return platform_driver_register(&oxnas_pinctrl_driver
);
1459 arch_initcall(oxnas_pinctrl_init
);
1461 static void __exit
oxnas_pinctrl_exit(void)
1463 platform_driver_unregister(&oxnas_pinctrl_driver
);
1466 module_exit(oxnas_pinctrl_exit
);
1467 MODULE_AUTHOR("Ma Hajun <mahaijuns@gmail.com>");
1468 MODULE_DESCRIPTION("Plxtech Nas782x pinctrl driver");
1469 MODULE_LICENSE("GPL v2");