2 * oxnas pinctrl driver based on at91 pinctrl driver
4 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
10 #include <linux/init.h>
11 #include <linux/module.h>
13 #include <linux/of_device.h>
14 #include <linux/of_address.h>
15 #include <linux/of_irq.h>
16 #include <linux/slab.h>
17 #include <linux/interrupt.h>
18 #include <linux/irq.h>
19 #include <linux/irqdomain.h>
20 #include <linux/irqchip/chained_irq.h>
22 #include <linux/gpio.h>
23 #include <linux/pinctrl/machine.h>
24 #include <linux/pinctrl/pinconf.h>
25 #include <linux/pinctrl/pinctrl.h>
26 #include <linux/pinctrl/pinmux.h>
27 /* Since we request GPIOs from ourself */
28 #include <linux/pinctrl/consumer.h>
32 #include <mach/utils.h>
34 #define MAX_NB_GPIO_PER_BANK 32
35 #define MAX_GPIO_BANKS 2
37 struct oxnas_gpio_chip
{
38 struct gpio_chip chip
;
39 struct pinctrl_gpio_range range
;
40 void __iomem
*regbase
; /* GPIOA/B virtual address */
41 void __iomem
*ctrlbase
; /* SYS/SEC_CTRL virtual address */
42 struct irq_domain
*domain
; /* associated irq domain */
45 #define to_oxnas_gpio_chip(c) container_of(c, struct oxnas_gpio_chip, chip)
47 static struct oxnas_gpio_chip
*gpio_chips
[MAX_GPIO_BANKS
];
49 static int gpio_banks
;
51 #define PULL_UP (1 << 0)
52 #define PULL_DOWN (1 << 1)
53 #define DEBOUNCE (1 << 2)
56 * struct oxnas_pmx_func - describes pinmux functions
57 * @name: the name of this specific function
58 * @groups: corresponding pin groups
59 * @ngroups: the number of groups
61 struct oxnas_pmx_func
{
84 OUTPUT_EN_CLEAR
= 0x20,
85 DEBOUNCE_ENABLE
= 0x24,
86 RE_IRQ_ENABLE
= 0x28, /* rising edge */
87 FE_IRQ_ENABLE
= 0x2C, /* falling edge */
88 RE_IRQ_PENDING
= 0x30, /* rising edge */
89 FE_IRQ_PENDING
= 0x34, /* falling edge */
92 PULL_SENSE
= 0x54, /* 1 up, 0 down */
95 DEBOUNCE_MASK
= 0x3FFF0000,
96 /* put hw debounce and soft config at same bit position*/
101 PINMUX_SECONDARY_SEL
= 0x14,
102 PINMUX_TERTIARY_SEL
= 0x8c,
103 PINMUX_QUATERNARY_SEL
= 0x94,
104 PINMUX_DEBUG_SEL
= 0x9c,
105 PINMUX_ALTERNATIVE_SEL
= 0xa4,
106 PINMUX_PULLUP_SEL
= 0xac,
110 * struct oxnas_pmx_pin - describes an pin mux
111 * @bank: the bank of the pin
112 * @pin: the pin number in the @bank
113 * @mux: the mux mode : gpio or periph_x of the pin i.e. alternate function.
114 * @conf: the configuration of the pin: PULL_UP, MULTIDRIVE etc...
116 struct oxnas_pmx_pin
{
124 * struct oxnas_pin_group - describes an pin group
125 * @name: the name of this specific pin group
126 * @pins_conf: the mux mode for each pin in this group. The size of this
127 * array is the same as pins.
128 * @pins: an array of discrete physical pins used in this group, taken
129 * from the driver-local pin enumeration space
130 * @npins: the number of pins in this group array, i.e. the number of
131 * elements in .pins so we can iterate over that array
133 struct oxnas_pin_group
{
135 struct oxnas_pmx_pin
*pins_conf
;
140 struct oxnas_pinctrl
{
142 struct pinctrl_dev
*pctl
;
149 struct oxnas_pmx_func
*functions
;
152 struct oxnas_pin_group
*groups
;
156 static const inline struct oxnas_pin_group
*oxnas_pinctrl_find_group_by_name(
157 const struct oxnas_pinctrl
*info
,
160 const struct oxnas_pin_group
*grp
= NULL
;
163 for (i
= 0; i
< info
->ngroups
; i
++) {
164 if (strcmp(info
->groups
[i
].name
, name
))
167 grp
= &info
->groups
[i
];
168 dev_dbg(info
->dev
, "%s: %d 0:%d\n", name
, grp
->npins
,
176 static int oxnas_get_groups_count(struct pinctrl_dev
*pctldev
)
178 struct oxnas_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
180 return info
->ngroups
;
183 static const char *oxnas_get_group_name(struct pinctrl_dev
*pctldev
,
186 struct oxnas_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
188 return info
->groups
[selector
].name
;
191 static int oxnas_get_group_pins(struct pinctrl_dev
*pctldev
, unsigned selector
,
192 const unsigned **pins
,
195 struct oxnas_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
197 if (selector
>= info
->ngroups
)
200 *pins
= info
->groups
[selector
].pins
;
201 *npins
= info
->groups
[selector
].npins
;
206 static void oxnas_pin_dbg_show(struct pinctrl_dev
*pctldev
, struct seq_file
*s
,
209 seq_printf(s
, "%s", dev_name(pctldev
->dev
));
212 static int oxnas_dt_node_to_map(struct pinctrl_dev
*pctldev
,
213 struct device_node
*np
,
214 struct pinctrl_map
**map
, unsigned *num_maps
)
216 struct oxnas_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
217 const struct oxnas_pin_group
*grp
;
218 struct pinctrl_map
*new_map
;
219 struct device_node
*parent
;
224 * first find the group of this node and check if we need create
225 * config maps for pins
227 grp
= oxnas_pinctrl_find_group_by_name(info
, np
->name
);
229 dev_err(info
->dev
, "unable to find group for node %s\n",
234 map_num
+= grp
->npins
;
235 new_map
= devm_kzalloc(pctldev
->dev
, sizeof(*new_map
) * map_num
,
244 parent
= of_get_parent(np
);
246 devm_kfree(pctldev
->dev
, new_map
);
249 new_map
[0].type
= PIN_MAP_TYPE_MUX_GROUP
;
250 new_map
[0].data
.mux
.function
= parent
->name
;
251 new_map
[0].data
.mux
.group
= np
->name
;
254 /* create config map */
256 for (i
= 0; i
< grp
->npins
; i
++) {
257 new_map
[i
].type
= PIN_MAP_TYPE_CONFIGS_PIN
;
258 new_map
[i
].data
.configs
.group_or_pin
=
259 pin_get_name(pctldev
, grp
->pins
[i
]);
260 new_map
[i
].data
.configs
.configs
= &grp
->pins_conf
[i
].conf
;
261 new_map
[i
].data
.configs
.num_configs
= 1;
264 dev_dbg(pctldev
->dev
, "maps: function %s group %s num %d\n",
265 (*map
)->data
.mux
.function
, (*map
)->data
.mux
.group
, map_num
);
270 static void oxnas_dt_free_map(struct pinctrl_dev
*pctldev
,
271 struct pinctrl_map
*map
, unsigned num_maps
)
275 static const struct pinctrl_ops oxnas_pctrl_ops
= {
276 .get_groups_count
= oxnas_get_groups_count
,
277 .get_group_name
= oxnas_get_group_name
,
278 .get_group_pins
= oxnas_get_group_pins
,
279 .pin_dbg_show
= oxnas_pin_dbg_show
,
280 .dt_node_to_map
= oxnas_dt_node_to_map
,
281 .dt_free_map
= oxnas_dt_free_map
,
284 static void __iomem
*pin_to_gpioctrl(struct oxnas_pinctrl
*info
,
287 return gpio_chips
[bank
]->regbase
;
290 static void __iomem
*pin_to_muxctrl(struct oxnas_pinctrl
*info
,
293 return gpio_chips
[bank
]->ctrlbase
;
297 static inline int pin_to_bank(unsigned pin
)
299 return pin
/ MAX_NB_GPIO_PER_BANK
;
302 static unsigned pin_to_mask(unsigned int pin
)
307 static void oxnas_mux_disable_interrupt(void __iomem
*pio
, unsigned mask
)
309 oxnas_register_clear_mask(pio
+ RE_IRQ_ENABLE
, mask
);
310 oxnas_register_clear_mask(pio
+ FE_IRQ_ENABLE
, mask
);
313 static unsigned oxnas_mux_get_pullup(void __iomem
*pio
, unsigned pin
)
315 return (readl_relaxed(pio
+ PULL_ENABLE
) & BIT(pin
)) &&
316 (readl_relaxed(pio
+ PULL_SENSE
) & BIT(pin
));
319 static void oxnas_mux_set_pullup(void __iomem
*pio
, unsigned mask
, bool on
)
322 oxnas_register_set_mask(pio
+ PULL_SENSE
, mask
);
323 oxnas_register_set_mask(pio
+ PULL_ENABLE
, mask
);
325 oxnas_register_clear_mask(pio
+ PULL_ENABLE
, mask
);
329 static bool oxnas_mux_get_pulldown(void __iomem
*pio
, unsigned pin
)
331 return (readl_relaxed(pio
+ PULL_ENABLE
) & BIT(pin
)) &&
332 (!(readl_relaxed(pio
+ PULL_SENSE
) & BIT(pin
)));
335 static void oxnas_mux_set_pulldown(void __iomem
*pio
, unsigned mask
, bool on
)
338 oxnas_register_clear_mask(pio
+ PULL_SENSE
, mask
);
339 oxnas_register_set_mask(pio
+ PULL_ENABLE
, mask
);
341 oxnas_register_clear_mask(pio
+ PULL_ENABLE
, mask
);
345 /* unfortunately debounce control are shared */
346 static bool oxnas_mux_get_debounce(void __iomem
*pio
, unsigned pin
, u32
*div
)
348 *div
= __raw_readl(pio
+ CLOCK_DIV
) & DEBOUNCE_MASK
;
349 return __raw_readl(pio
+ DEBOUNCE_ENABLE
) & BIT(pin
);
352 static void oxnas_mux_set_debounce(void __iomem
*pio
, unsigned mask
,
356 oxnas_register_value_mask(pio
+ CLOCK_DIV
, DEBOUNCE_MASK
, div
);
357 oxnas_register_set_mask(pio
+ DEBOUNCE_ENABLE
, mask
);
359 oxnas_register_clear_mask(pio
+ DEBOUNCE_ENABLE
, mask
);
364 static void oxnas_mux_set_func2(void __iomem
*cio
, unsigned mask
)
366 /* in fact, SECONDARY takes precedence, so clear others is not necessary */
367 oxnas_register_set_mask(cio
+ PINMUX_SECONDARY_SEL
, mask
);
368 oxnas_register_clear_mask(cio
+ PINMUX_TERTIARY_SEL
, mask
);
369 oxnas_register_clear_mask(cio
+ PINMUX_QUATERNARY_SEL
, mask
);
370 oxnas_register_clear_mask(cio
+ PINMUX_DEBUG_SEL
, mask
);
371 oxnas_register_clear_mask(cio
+ PINMUX_ALTERNATIVE_SEL
, mask
);
374 static void oxnas_mux_set_func3(void __iomem
*cio
, unsigned mask
)
376 oxnas_register_clear_mask(cio
+ PINMUX_SECONDARY_SEL
, mask
);
377 oxnas_register_set_mask(cio
+ PINMUX_TERTIARY_SEL
, mask
);
378 oxnas_register_clear_mask(cio
+ PINMUX_QUATERNARY_SEL
, mask
);
379 oxnas_register_clear_mask(cio
+ PINMUX_DEBUG_SEL
, mask
);
380 oxnas_register_clear_mask(cio
+ PINMUX_ALTERNATIVE_SEL
, mask
);
383 static void oxnas_mux_set_func4(void __iomem
*cio
, unsigned mask
)
385 oxnas_register_clear_mask(cio
+ PINMUX_SECONDARY_SEL
, mask
);
386 oxnas_register_clear_mask(cio
+ PINMUX_TERTIARY_SEL
, mask
);
387 oxnas_register_set_mask(cio
+ PINMUX_QUATERNARY_SEL
, mask
);
388 oxnas_register_clear_mask(cio
+ PINMUX_DEBUG_SEL
, mask
);
389 oxnas_register_clear_mask(cio
+ PINMUX_ALTERNATIVE_SEL
, mask
);
392 static void oxnas_mux_set_func_dbg(void __iomem
*cio
, unsigned mask
)
394 oxnas_register_clear_mask(cio
+ PINMUX_SECONDARY_SEL
, mask
);
395 oxnas_register_clear_mask(cio
+ PINMUX_TERTIARY_SEL
, mask
);
396 oxnas_register_clear_mask(cio
+ PINMUX_QUATERNARY_SEL
, mask
);
397 oxnas_register_set_mask(cio
+ PINMUX_DEBUG_SEL
, mask
);
398 oxnas_register_clear_mask(cio
+ PINMUX_ALTERNATIVE_SEL
, mask
);
401 static void oxnas_mux_set_func_alt(void __iomem
*cio
, unsigned mask
)
403 oxnas_register_clear_mask(cio
+ PINMUX_SECONDARY_SEL
, mask
);
404 oxnas_register_clear_mask(cio
+ PINMUX_TERTIARY_SEL
, mask
);
405 oxnas_register_clear_mask(cio
+ PINMUX_QUATERNARY_SEL
, mask
);
406 oxnas_register_clear_mask(cio
+ PINMUX_DEBUG_SEL
, mask
);
407 oxnas_register_set_mask(cio
+ PINMUX_ALTERNATIVE_SEL
, mask
);
410 static void oxnas_mux_set_gpio(void __iomem
*cio
, unsigned mask
)
412 oxnas_register_clear_mask(cio
+ PINMUX_SECONDARY_SEL
, mask
);
413 oxnas_register_clear_mask(cio
+ PINMUX_TERTIARY_SEL
, mask
);
414 oxnas_register_clear_mask(cio
+ PINMUX_QUATERNARY_SEL
, mask
);
415 oxnas_register_clear_mask(cio
+ PINMUX_DEBUG_SEL
, mask
);
416 oxnas_register_clear_mask(cio
+ PINMUX_ALTERNATIVE_SEL
, mask
);
419 static enum oxnas_mux
oxnas_mux_get_func(void __iomem
*cio
, unsigned mask
)
421 if (readl_relaxed(cio
+ PINMUX_SECONDARY_SEL
) & mask
)
422 return OXNAS_PINMUX_FUNC2
;
423 if (readl_relaxed(cio
+ PINMUX_TERTIARY_SEL
) & mask
)
424 return OXNAS_PINMUX_FUNC3
;
425 if (readl_relaxed(cio
+ PINMUX_QUATERNARY_SEL
) & mask
)
426 return OXNAS_PINMUX_FUNC4
;
427 if (readl_relaxed(cio
+ PINMUX_DEBUG_SEL
) & mask
)
428 return OXNAS_PINMUX_DEBUG
;
429 if (readl_relaxed(cio
+ PINMUX_ALTERNATIVE_SEL
) & mask
)
430 return OXNAS_PINMUX_ALT
;
431 return OXNAS_PINMUX_GPIO
;
435 static void oxnas_pin_dbg(const struct device
*dev
,
436 const struct oxnas_pmx_pin
*pin
)
440 "MF_%c%d configured as periph%c with conf = 0x%lu\n",
441 pin
->bank
+ 'A', pin
->pin
, pin
->mux
- 1 + 'A',
444 dev_dbg(dev
, "MF_%c%d configured as gpio with conf = 0x%lu\n",
445 pin
->bank
+ 'A', pin
->pin
, pin
->conf
);
449 static int pin_check_config(struct oxnas_pinctrl
*info
, const char *name
,
450 int index
, const struct oxnas_pmx_pin
*pin
)
454 /* check if it's a valid config */
455 if (pin
->bank
>= info
->nbanks
) {
456 dev_err(info
->dev
, "%s: pin conf %d bank_id %d >= nbanks %d\n",
457 name
, index
, pin
->bank
, info
->nbanks
);
461 if (pin
->pin
>= MAX_NB_GPIO_PER_BANK
) {
462 dev_err(info
->dev
, "%s: pin conf %d pin_bank_id %d >= %d\n",
463 name
, index
, pin
->pin
, MAX_NB_GPIO_PER_BANK
);
466 /* gpio always allowed */
472 if (mux
>= info
->nmux
) {
473 dev_err(info
->dev
, "%s: pin conf %d mux_id %d >= nmux %d\n",
474 name
, index
, mux
, info
->nmux
);
478 if (!(info
->mux_mask
[pin
->bank
* info
->nmux
+ mux
] & 1 << pin
->pin
)) {
479 dev_err(info
->dev
, "%s: pin conf %d mux_id %d not supported for MF_%c%d\n",
480 name
, index
, mux
, pin
->bank
+ 'A', pin
->pin
);
487 static void oxnas_mux_gpio_enable(void __iomem
*cio
, void __iomem
*pio
,
488 unsigned mask
, bool input
)
490 oxnas_mux_set_gpio(cio
, mask
);
492 writel_relaxed(mask
, pio
+ OUTPUT_EN_CLEAR
);
494 writel_relaxed(mask
, pio
+ OUTPUT_EN_SET
);
497 static void oxnas_mux_gpio_disable(void __iomem
*cio
, void __iomem
*pio
,
500 /* when switch to other function, gpio is disabled automatically */
504 static int oxnas_pmx_set_mux(struct pinctrl_dev
*pctldev
, unsigned selector
,
507 struct oxnas_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
508 const struct oxnas_pmx_pin
*pins_conf
= info
->groups
[group
].pins_conf
;
509 const struct oxnas_pmx_pin
*pin
;
510 uint32_t npins
= info
->groups
[group
].npins
;
516 dev_dbg(info
->dev
, "enable function %s group %s\n",
517 info
->functions
[selector
].name
, info
->groups
[group
].name
);
519 /* first check that all the pins of the group are valid with a valid
521 for (i
= 0; i
< npins
; i
++) {
523 ret
= pin_check_config(info
, info
->groups
[group
].name
, i
, pin
);
528 for (i
= 0; i
< npins
; i
++) {
530 oxnas_pin_dbg(info
->dev
, pin
);
532 pio
= pin_to_gpioctrl(info
, pin
->bank
);
533 cio
= pin_to_muxctrl(info
, pin
->bank
);
535 mask
= pin_to_mask(pin
->pin
);
536 oxnas_mux_disable_interrupt(pio
, mask
);
539 case OXNAS_PINMUX_GPIO
:
540 oxnas_mux_gpio_enable(cio
, pio
, mask
, 1);
542 case OXNAS_PINMUX_FUNC2
:
543 oxnas_mux_set_func2(cio
, mask
);
545 case OXNAS_PINMUX_FUNC3
:
546 oxnas_mux_set_func3(cio
, mask
);
548 case OXNAS_PINMUX_FUNC4
:
549 oxnas_mux_set_func4(cio
, mask
);
551 case OXNAS_PINMUX_DEBUG
:
552 oxnas_mux_set_func_dbg(cio
, mask
);
554 case OXNAS_PINMUX_ALT
:
555 oxnas_mux_set_func_alt(cio
, mask
);
559 oxnas_mux_gpio_disable(cio
, pio
, mask
);
565 static int oxnas_pmx_get_funcs_count(struct pinctrl_dev
*pctldev
)
567 struct oxnas_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
569 return info
->nfunctions
;
572 static const char *oxnas_pmx_get_func_name(struct pinctrl_dev
*pctldev
,
575 struct oxnas_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
577 return info
->functions
[selector
].name
;
580 static int oxnas_pmx_get_groups(struct pinctrl_dev
*pctldev
, unsigned selector
,
581 const char * const **groups
,
582 unsigned * const num_groups
)
584 struct oxnas_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
586 *groups
= info
->functions
[selector
].groups
;
587 *num_groups
= info
->functions
[selector
].ngroups
;
592 static int oxnas_gpio_request_enable(struct pinctrl_dev
*pctldev
,
593 struct pinctrl_gpio_range
*range
,
596 struct oxnas_pinctrl
*npct
= pinctrl_dev_get_drvdata(pctldev
);
597 struct oxnas_gpio_chip
*oxnas_chip
;
598 struct gpio_chip
*chip
;
602 dev_err(npct
->dev
, "invalid range\n");
606 dev_err(npct
->dev
, "missing GPIO chip in range\n");
610 oxnas_chip
= container_of(chip
, struct oxnas_gpio_chip
, chip
);
612 dev_dbg(npct
->dev
, "enable pin %u as GPIO\n", offset
);
614 mask
= 1 << (offset
- chip
->base
);
616 dev_dbg(npct
->dev
, "enable pin %u as MF_%c%d 0x%x\n",
617 offset
, 'A' + range
->id
, offset
- chip
->base
, mask
);
619 oxnas_mux_set_gpio(oxnas_chip
->ctrlbase
, mask
);
624 static void oxnas_gpio_disable_free(struct pinctrl_dev
*pctldev
,
625 struct pinctrl_gpio_range
*range
,
628 struct oxnas_pinctrl
*npct
= pinctrl_dev_get_drvdata(pctldev
);
630 dev_dbg(npct
->dev
, "disable pin %u as GPIO\n", offset
);
631 /* Set the pin to some default state, GPIO is usually default */
634 static const struct pinmux_ops oxnas_pmx_ops
= {
635 .get_functions_count
= oxnas_pmx_get_funcs_count
,
636 .get_function_name
= oxnas_pmx_get_func_name
,
637 .get_function_groups
= oxnas_pmx_get_groups
,
638 .set_mux
= oxnas_pmx_set_mux
,
639 .gpio_request_enable
= oxnas_gpio_request_enable
,
640 .gpio_disable_free
= oxnas_gpio_disable_free
,
643 static int oxnas_pinconf_get(struct pinctrl_dev
*pctldev
,
644 unsigned pin_id
, unsigned long *config
)
646 struct oxnas_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
651 dev_dbg(info
->dev
, "%s:%d, pin_id=%d, config=0x%lx", __func__
,
652 __LINE__
, pin_id
, *config
);
653 pio
= pin_to_gpioctrl(info
, pin_to_bank(pin_id
));
654 pin
= pin_id
% MAX_NB_GPIO_PER_BANK
;
656 if (oxnas_mux_get_pullup(pio
, pin
))
659 if (oxnas_mux_get_pulldown(pio
, pin
))
660 *config
|= PULL_DOWN
;
662 if (oxnas_mux_get_debounce(pio
, pin
, &div
))
663 *config
|= DEBOUNCE
| div
;
667 static int oxnas_pinconf_set(struct pinctrl_dev
*pctldev
,
668 unsigned pin_id
, unsigned long *configs
,
669 unsigned num_configs
)
671 struct oxnas_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
675 unsigned long config
;
677 pio
= pin_to_gpioctrl(info
, pin_to_bank(pin_id
));
678 mask
= pin_to_mask(pin_id
% MAX_NB_GPIO_PER_BANK
);
680 for (i
= 0; i
< num_configs
; i
++) {
684 "%s:%d, pin_id=%d, config=0x%lx",
685 __func__
, __LINE__
, pin_id
, config
);
687 if ((config
& PULL_UP
) && (config
& PULL_DOWN
))
690 oxnas_mux_set_pullup(pio
, mask
, config
& PULL_UP
);
691 oxnas_mux_set_pulldown(pio
, mask
, config
& PULL_DOWN
);
692 oxnas_mux_set_debounce(pio
, mask
, config
& DEBOUNCE
,
693 config
& DEBOUNCE_MASK
);
695 } /* for each config */
700 static void oxnas_pinconf_dbg_show(struct pinctrl_dev
*pctldev
,
701 struct seq_file
*s
, unsigned pin_id
)
706 static void oxnas_pinconf_group_dbg_show(struct pinctrl_dev
*pctldev
,
707 struct seq_file
*s
, unsigned group
)
711 static const struct pinconf_ops oxnas_pinconf_ops
= {
712 .pin_config_get
= oxnas_pinconf_get
,
713 .pin_config_set
= oxnas_pinconf_set
,
714 .pin_config_dbg_show
= oxnas_pinconf_dbg_show
,
715 .pin_config_group_dbg_show
= oxnas_pinconf_group_dbg_show
,
718 static struct pinctrl_desc oxnas_pinctrl_desc
= {
719 .pctlops
= &oxnas_pctrl_ops
,
720 .pmxops
= &oxnas_pmx_ops
,
721 .confops
= &oxnas_pinconf_ops
,
722 .owner
= THIS_MODULE
,
725 static const char *gpio_compat
= "plxtech,nas782x-gpio";
727 static void oxnas_pinctrl_child_count(struct oxnas_pinctrl
*info
,
728 struct device_node
*np
)
730 struct device_node
*child
;
732 for_each_child_of_node(np
, child
) {
733 if (of_device_is_compatible(child
, gpio_compat
)) {
737 info
->ngroups
+= of_get_child_count(child
);
742 static int oxnas_pinctrl_mux_mask(struct oxnas_pinctrl
*info
,
743 struct device_node
*np
)
749 list
= of_get_property(np
, "plxtech,mux-mask", &size
);
751 dev_err(info
->dev
, "can not read the mux-mask of %d\n", size
);
755 size
/= sizeof(*list
);
756 if (!size
|| size
% info
->nbanks
) {
757 dev_err(info
->dev
, "wrong mux mask array should be by %d\n",
761 info
->nmux
= size
/ info
->nbanks
;
763 info
->mux_mask
= devm_kzalloc(info
->dev
, sizeof(u32
) * size
, GFP_KERNEL
);
764 if (!info
->mux_mask
) {
765 dev_err(info
->dev
, "could not alloc mux_mask\n");
769 ret
= of_property_read_u32_array(np
, "plxtech,mux-mask",
770 info
->mux_mask
, size
);
772 dev_err(info
->dev
, "can not read the mux-mask of %d\n", size
);
776 static int oxnas_pinctrl_parse_groups(struct device_node
*np
,
777 struct oxnas_pin_group
*grp
,
778 struct oxnas_pinctrl
*info
, u32 index
)
780 struct oxnas_pmx_pin
*pin
;
785 dev_dbg(info
->dev
, "group(%d): %s\n", index
, np
->name
);
787 /* Initialise group */
788 grp
->name
= np
->name
;
791 * the binding format is plxtech,pins = <bank pin mux CONFIG ...>,
792 * do sanity check and calculate pins number
794 list
= of_get_property(np
, "plxtech,pins", &size
);
795 /* we do not check return since it's safe node passed down */
796 size
/= sizeof(*list
);
797 if (!size
|| size
% 4) {
798 dev_err(info
->dev
, "wrong pins number or pins and configs"
799 " should be divisible by 4\n");
803 grp
->npins
= size
/ 4;
804 pin
= grp
->pins_conf
= devm_kzalloc(info
->dev
,
805 grp
->npins
* sizeof(struct oxnas_pmx_pin
),
807 grp
->pins
= devm_kzalloc(info
->dev
, grp
->npins
* sizeof(unsigned int),
809 if (!grp
->pins_conf
|| !grp
->pins
)
812 for (i
= 0, j
= 0; i
< size
; i
+= 4, j
++) {
813 pin
->bank
= be32_to_cpu(*list
++);
814 pin
->pin
= be32_to_cpu(*list
++);
815 grp
->pins
[j
] = pin
->bank
* MAX_NB_GPIO_PER_BANK
+ pin
->pin
;
816 pin
->mux
= be32_to_cpu(*list
++);
817 pin
->conf
= be32_to_cpu(*list
++);
819 oxnas_pin_dbg(info
->dev
, pin
);
826 static int oxnas_pinctrl_parse_functions(struct device_node
*np
,
827 struct oxnas_pinctrl
*info
, u32 index
)
829 struct device_node
*child
;
830 struct oxnas_pmx_func
*func
;
831 struct oxnas_pin_group
*grp
;
833 static u32 grp_index
;
836 dev_dbg(info
->dev
, "parse function(%d): %s\n", index
, np
->name
);
838 func
= &info
->functions
[index
];
840 /* Initialise function */
841 func
->name
= np
->name
;
842 func
->ngroups
= of_get_child_count(np
);
843 if (func
->ngroups
<= 0) {
844 dev_err(info
->dev
, "no groups defined\n");
847 func
->groups
= devm_kzalloc(info
->dev
,
848 func
->ngroups
* sizeof(char *), GFP_KERNEL
);
852 for_each_child_of_node(np
, child
) {
853 func
->groups
[i
] = child
->name
;
854 grp
= &info
->groups
[grp_index
++];
855 ret
= oxnas_pinctrl_parse_groups(child
, grp
, info
, i
++);
863 static struct of_device_id oxnas_pinctrl_of_match
[] = {
864 { .compatible
= "plxtech,nas782x-pinctrl"},
868 static int oxnas_pinctrl_probe_dt(struct platform_device
*pdev
,
869 struct oxnas_pinctrl
*info
)
874 struct device_node
*np
= pdev
->dev
.of_node
;
875 struct device_node
*child
;
880 info
->dev
= &pdev
->dev
;
882 oxnas_pinctrl_child_count(info
, np
);
884 if (info
->nbanks
< 1) {
885 dev_err(&pdev
->dev
, "you need to specify atleast one gpio-controller\n");
889 ret
= oxnas_pinctrl_mux_mask(info
, np
);
893 dev_dbg(&pdev
->dev
, "nmux = %d\n", info
->nmux
);
895 dev_dbg(&pdev
->dev
, "mux-mask\n");
896 tmp
= info
->mux_mask
;
897 for (i
= 0; i
< info
->nbanks
; i
++)
898 for (j
= 0; j
< info
->nmux
; j
++, tmp
++)
899 dev_dbg(&pdev
->dev
, "%d:%d\t0x%x\n", i
, j
, tmp
[0]);
901 dev_dbg(&pdev
->dev
, "nfunctions = %d\n", info
->nfunctions
);
902 dev_dbg(&pdev
->dev
, "ngroups = %d\n", info
->ngroups
);
903 info
->functions
= devm_kzalloc(&pdev
->dev
, info
->nfunctions
*
904 sizeof(struct oxnas_pmx_func
),
906 if (!info
->functions
)
909 info
->groups
= devm_kzalloc(&pdev
->dev
, info
->ngroups
*
910 sizeof(struct oxnas_pin_group
),
915 dev_dbg(&pdev
->dev
, "nbanks = %d\n", info
->nbanks
);
916 dev_dbg(&pdev
->dev
, "nfunctions = %d\n", info
->nfunctions
);
917 dev_dbg(&pdev
->dev
, "ngroups = %d\n", info
->ngroups
);
921 for_each_child_of_node(np
, child
) {
922 if (of_device_is_compatible(child
, gpio_compat
))
924 ret
= oxnas_pinctrl_parse_functions(child
, info
, i
++);
926 dev_err(&pdev
->dev
, "failed to parse function\n");
934 static int oxnas_pinctrl_probe(struct platform_device
*pdev
)
936 struct oxnas_pinctrl
*info
;
937 struct pinctrl_pin_desc
*pdesc
;
940 info
= devm_kzalloc(&pdev
->dev
, sizeof(*info
), GFP_KERNEL
);
944 ret
= oxnas_pinctrl_probe_dt(pdev
, info
);
949 * We need all the GPIO drivers to probe FIRST, or we will not be able
950 * to obtain references to the struct gpio_chip * for them, and we
951 * need this to proceed.
953 for (i
= 0; i
< info
->nbanks
; i
++) {
954 if (!gpio_chips
[i
]) {
956 "GPIO chip %d not registered yet\n", i
);
957 devm_kfree(&pdev
->dev
, info
);
958 return -EPROBE_DEFER
;
962 oxnas_pinctrl_desc
.name
= dev_name(&pdev
->dev
);
963 oxnas_pinctrl_desc
.npins
= info
->nbanks
* MAX_NB_GPIO_PER_BANK
;
964 oxnas_pinctrl_desc
.pins
= pdesc
=
965 devm_kzalloc(&pdev
->dev
, sizeof(*pdesc
) *
966 oxnas_pinctrl_desc
.npins
, GFP_KERNEL
);
968 if (!oxnas_pinctrl_desc
.pins
)
971 for (i
= 0 , k
= 0; i
< info
->nbanks
; i
++) {
972 for (j
= 0; j
< MAX_NB_GPIO_PER_BANK
; j
++, k
++) {
974 pdesc
->name
= kasprintf(GFP_KERNEL
, "MF_%c%d", i
+ 'A',
980 platform_set_drvdata(pdev
, info
);
981 info
->pctl
= pinctrl_register(&oxnas_pinctrl_desc
, &pdev
->dev
, info
);
984 dev_err(&pdev
->dev
, "could not register OX820 pinctrl driver\n");
989 /* We will handle a range of GPIO pins */
990 for (i
= 0; i
< info
->nbanks
; i
++)
991 pinctrl_add_gpio_range(info
->pctl
, &gpio_chips
[i
]->range
);
993 dev_info(&pdev
->dev
, "initialized OX820 pinctrl driver\n");
1001 static int oxnas_pinctrl_remove(struct platform_device
*pdev
)
1003 struct oxnas_pinctrl
*info
= platform_get_drvdata(pdev
);
1005 pinctrl_unregister(info
->pctl
);
1010 static int oxnas_gpio_request(struct gpio_chip
*chip
, unsigned offset
)
1013 * Map back to global GPIO space and request muxing, the direction
1014 * parameter does not matter for this controller.
1016 int gpio
= chip
->base
+ offset
;
1017 int bank
= chip
->base
/ chip
->ngpio
;
1019 dev_dbg(chip
->dev
, "%s:%d MF_%c%d(%d)\n", __func__
, __LINE__
,
1020 'A' + bank
, offset
, gpio
);
1022 return pinctrl_request_gpio(gpio
);
1025 static void oxnas_gpio_free(struct gpio_chip
*chip
, unsigned offset
)
1027 int gpio
= chip
->base
+ offset
;
1029 pinctrl_free_gpio(gpio
);
1032 static int oxnas_gpio_direction_input(struct gpio_chip
*chip
, unsigned offset
)
1034 struct oxnas_gpio_chip
*oxnas_gpio
= to_oxnas_gpio_chip(chip
);
1035 void __iomem
*pio
= oxnas_gpio
->regbase
;
1037 writel_relaxed(BIT(offset
), pio
+ OUTPUT_EN_CLEAR
);
1041 static int oxnas_gpio_get(struct gpio_chip
*chip
, unsigned offset
)
1043 struct oxnas_gpio_chip
*oxnas_gpio
= to_oxnas_gpio_chip(chip
);
1044 void __iomem
*pio
= oxnas_gpio
->regbase
;
1045 unsigned mask
= 1 << offset
;
1048 pdsr
= readl_relaxed(pio
+ INPUT_VALUE
);
1049 return (pdsr
& mask
) != 0;
1052 static void oxnas_gpio_set(struct gpio_chip
*chip
, unsigned offset
,
1055 struct oxnas_gpio_chip
*oxnas_gpio
= to_oxnas_gpio_chip(chip
);
1056 void __iomem
*pio
= oxnas_gpio
->regbase
;
1059 writel_relaxed(BIT(offset
), pio
+ OUTPUT_SET
);
1061 writel_relaxed(BIT(offset
), pio
+ OUTPUT_CLEAR
);
1065 static int oxnas_gpio_direction_output(struct gpio_chip
*chip
, unsigned offset
,
1068 struct oxnas_gpio_chip
*oxnas_gpio
= to_oxnas_gpio_chip(chip
);
1069 void __iomem
*pio
= oxnas_gpio
->regbase
;
1072 writel_relaxed(BIT(offset
), pio
+ OUTPUT_SET
);
1074 writel_relaxed(BIT(offset
), pio
+ OUTPUT_CLEAR
);
1076 writel_relaxed(BIT(offset
), pio
+ OUTPUT_EN_SET
);
1081 static int oxnas_gpio_to_irq(struct gpio_chip
*chip
, unsigned offset
)
1083 struct oxnas_gpio_chip
*oxnas_gpio
= to_oxnas_gpio_chip(chip
);
1086 if (offset
< chip
->ngpio
)
1087 virq
= irq_create_mapping(oxnas_gpio
->domain
, offset
);
1091 dev_dbg(chip
->dev
, "%s: request IRQ for GPIO %d, return %d\n",
1092 chip
->label
, offset
+ chip
->base
, virq
);
1096 #ifdef CONFIG_DEBUG_FS
1097 static void oxnas_gpio_dbg_show(struct seq_file
*s
, struct gpio_chip
*chip
)
1099 enum oxnas_mux mode
;
1101 struct oxnas_gpio_chip
*oxnas_gpio
= to_oxnas_gpio_chip(chip
);
1102 void __iomem
*pio
= oxnas_gpio
->regbase
;
1103 void __iomem
*cio
= oxnas_gpio
->ctrlbase
;
1105 for (i
= 0; i
< chip
->ngpio
; i
++) {
1106 unsigned pin
= chip
->base
+ i
;
1107 unsigned mask
= pin_to_mask(pin
);
1108 const char *gpio_label
;
1111 gpio_label
= gpiochip_is_requested(chip
, i
);
1115 mode
= oxnas_mux_get_func(cio
, mask
);
1116 seq_printf(s
, "[%s] GPIO%s%d: ",
1117 gpio_label
, chip
->label
, i
);
1118 if (mode
== OXNAS_PINMUX_GPIO
) {
1119 pdsr
= readl_relaxed(pio
+ INPUT_VALUE
);
1121 seq_printf(s
, "[gpio] %s\n",
1125 seq_printf(s
, "[periph %c]\n",
1131 #define oxnas_gpio_dbg_show NULL
1134 /* Several AIC controller irqs are dispatched through this GPIO handler.
1135 * To use any AT91_PIN_* as an externally triggered IRQ, first call
1136 * oxnas_set_gpio_input() then maybe enable its glitch filter.
1137 * Then just request_irq() with the pin ID; it works like any ARM IRQ
1141 static void gpio_irq_mask(struct irq_data
*d
)
1143 struct oxnas_gpio_chip
*oxnas_gpio
= irq_data_get_irq_chip_data(d
);
1144 void __iomem
*pio
= oxnas_gpio
->regbase
;
1145 unsigned mask
= 1 << d
->hwirq
;
1146 unsigned type
= irqd_get_trigger_type(d
);
1148 /* FIXME: need proper lock */
1149 if (type
& IRQ_TYPE_EDGE_RISING
)
1150 oxnas_register_clear_mask(pio
+ RE_IRQ_ENABLE
, mask
);
1151 if (type
& IRQ_TYPE_EDGE_FALLING
)
1152 oxnas_register_clear_mask(pio
+ FE_IRQ_ENABLE
, mask
);
1155 static void gpio_irq_unmask(struct irq_data
*d
)
1157 struct oxnas_gpio_chip
*oxnas_gpio
= irq_data_get_irq_chip_data(d
);
1158 void __iomem
*pio
= oxnas_gpio
->regbase
;
1159 unsigned mask
= 1 << d
->hwirq
;
1160 unsigned type
= irqd_get_trigger_type(d
);
1162 /* FIXME: need proper lock */
1163 if (type
& IRQ_TYPE_EDGE_RISING
)
1164 oxnas_register_set_mask(pio
+ RE_IRQ_ENABLE
, mask
);
1165 if (type
& IRQ_TYPE_EDGE_FALLING
)
1166 oxnas_register_set_mask(pio
+ FE_IRQ_ENABLE
, mask
);
1170 static int gpio_irq_type(struct irq_data
*d
, unsigned type
)
1172 if ((type
& IRQ_TYPE_EDGE_BOTH
) == 0) {
1173 pr_warn("OX820: Unsupported type for irq %d\n",
1174 gpio_to_irq(d
->irq
));
1177 /* seems no way to set trigger type without enable irq, so leave it to unmask time */
1182 static struct irq_chip gpio_irqchip
= {
1184 .irq_disable
= gpio_irq_mask
,
1185 .irq_mask
= gpio_irq_mask
,
1186 .irq_unmask
= gpio_irq_unmask
,
1187 .irq_set_type
= gpio_irq_type
,
1190 static void gpio_irq_handler(unsigned irq
, struct irq_desc
*desc
)
1192 struct irq_chip
*chip
= irq_desc_get_chip(desc
);
1193 struct irq_data
*idata
= irq_desc_get_irq_data(desc
);
1194 struct oxnas_gpio_chip
*oxnas_gpio
= irq_data_get_irq_chip_data(idata
);
1195 void __iomem
*pio
= oxnas_gpio
->regbase
;
1199 chained_irq_enter(chip
, desc
);
1201 /* TODO: see if it works */
1202 isr
= readl_relaxed(pio
+ IRQ_PENDING
);
1205 /* acks pending interrupts */
1206 writel_relaxed(isr
, pio
+ IRQ_PENDING
);
1208 for_each_set_bit(n
, &isr
, BITS_PER_LONG
) {
1209 generic_handle_irq(irq_find_mapping(oxnas_gpio
->domain
,
1213 chained_irq_exit(chip
, desc
);
1214 /* now it may re-trigger */
1218 * This lock class tells lockdep that GPIO irqs are in a different
1219 * category than their parents, so it won't report false recursion.
1221 static struct lock_class_key gpio_lock_class
;
1223 static int oxnas_gpio_irq_map(struct irq_domain
*h
, unsigned int virq
,
1226 struct oxnas_gpio_chip
*oxnas_gpio
= h
->host_data
;
1228 irq_set_lockdep_class(virq
, &gpio_lock_class
);
1230 irq_set_chip_and_handler(virq
, &gpio_irqchip
, handle_edge_irq
);
1231 set_irq_flags(virq
, IRQF_VALID
);
1232 irq_set_chip_data(virq
, oxnas_gpio
);
1237 static int oxnas_gpio_irq_domain_xlate(struct irq_domain
*d
,
1238 struct device_node
*ctrlr
,
1240 unsigned int intsize
,
1241 irq_hw_number_t
*out_hwirq
,
1242 unsigned int *out_type
)
1244 struct oxnas_gpio_chip
*oxnas_gpio
= d
->host_data
;
1246 int pin
= oxnas_gpio
->chip
.base
+ intspec
[0];
1248 if (WARN_ON(intsize
< 2))
1250 *out_hwirq
= intspec
[0];
1251 *out_type
= intspec
[1] & IRQ_TYPE_SENSE_MASK
;
1253 ret
= gpio_request(pin
, ctrlr
->full_name
);
1257 ret
= gpio_direction_input(pin
);
1264 static struct irq_domain_ops oxnas_gpio_ops
= {
1265 .map
= oxnas_gpio_irq_map
,
1266 .xlate
= oxnas_gpio_irq_domain_xlate
,
1269 static int oxnas_gpio_of_irq_setup(struct device_node
*node
,
1270 struct oxnas_gpio_chip
*oxnas_gpio
,
1273 /* Disable irqs of this controller */
1274 writel_relaxed(0, oxnas_gpio
->regbase
+ RE_IRQ_ENABLE
);
1275 writel_relaxed(0, oxnas_gpio
->regbase
+ FE_IRQ_ENABLE
);
1277 /* Setup irq domain */
1278 oxnas_gpio
->domain
= irq_domain_add_linear(node
, oxnas_gpio
->chip
.ngpio
,
1279 &oxnas_gpio_ops
, oxnas_gpio
);
1280 if (!oxnas_gpio
->domain
)
1281 panic("oxnas_gpio: couldn't allocate irq domain (DT).\n");
1283 irq_set_chip_data(irq
, oxnas_gpio
);
1284 irq_set_chained_handler(irq
, gpio_irq_handler
);
1289 /* This structure is replicated for each GPIO block allocated at probe time */
1290 static struct gpio_chip oxnas_gpio_template
= {
1291 .request
= oxnas_gpio_request
,
1292 .free
= oxnas_gpio_free
,
1293 .direction_input
= oxnas_gpio_direction_input
,
1294 .get
= oxnas_gpio_get
,
1295 .direction_output
= oxnas_gpio_direction_output
,
1296 .set
= oxnas_gpio_set
,
1297 .to_irq
= oxnas_gpio_to_irq
,
1298 .dbg_show
= oxnas_gpio_dbg_show
,
1300 .ngpio
= MAX_NB_GPIO_PER_BANK
,
1303 static struct of_device_id oxnas_gpio_of_match
[] = {
1304 { .compatible
= "plxtech,nas782x-gpio"},
1308 static int oxnas_gpio_probe(struct platform_device
*pdev
)
1310 struct device_node
*np
= pdev
->dev
.of_node
;
1311 struct resource
*res
;
1312 struct oxnas_gpio_chip
*oxnas_chip
= NULL
;
1313 struct gpio_chip
*chip
;
1314 struct pinctrl_gpio_range
*range
;
1317 int alias_idx
= of_alias_get_id(np
, "gpio");
1321 BUG_ON(alias_idx
>= ARRAY_SIZE(gpio_chips
));
1322 if (gpio_chips
[alias_idx
]) {
1327 irq
= platform_get_irq(pdev
, 0);
1333 oxnas_chip
= devm_kzalloc(&pdev
->dev
, sizeof(*oxnas_chip
), GFP_KERNEL
);
1339 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1340 oxnas_chip
->regbase
= devm_ioremap_resource(&pdev
->dev
, res
);
1341 if (IS_ERR(oxnas_chip
->regbase
)) {
1342 ret
= PTR_ERR(oxnas_chip
->regbase
);
1346 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 1);
1347 oxnas_chip
->ctrlbase
= devm_ioremap_resource(&pdev
->dev
, res
);
1348 if (IS_ERR(oxnas_chip
->ctrlbase
)) {
1349 ret
= PTR_ERR(oxnas_chip
->ctrlbase
);
1353 oxnas_chip
->chip
= oxnas_gpio_template
;
1355 chip
= &oxnas_chip
->chip
;
1357 chip
->label
= dev_name(&pdev
->dev
);
1358 chip
->dev
= &pdev
->dev
;
1359 chip
->owner
= THIS_MODULE
;
1360 chip
->base
= alias_idx
* MAX_NB_GPIO_PER_BANK
;
1362 if (!of_property_read_u32(np
, "#gpio-lines", &ngpio
)) {
1363 if (ngpio
> MAX_NB_GPIO_PER_BANK
)
1364 pr_err("oxnas_gpio.%d, gpio-nb >= %d failback to %d\n",
1365 alias_idx
, MAX_NB_GPIO_PER_BANK
,
1366 MAX_NB_GPIO_PER_BANK
);
1368 chip
->ngpio
= ngpio
;
1371 names
= devm_kzalloc(&pdev
->dev
, sizeof(char *) * chip
->ngpio
,
1379 for (i
= 0; i
< chip
->ngpio
; i
++)
1380 names
[i
] = kasprintf(GFP_KERNEL
, "MF_%c%d", alias_idx
+ 'A', i
);
1382 chip
->names
= (const char *const *)names
;
1384 range
= &oxnas_chip
->range
;
1385 range
->name
= chip
->label
;
1386 range
->id
= alias_idx
;
1387 range
->pin_base
= range
->base
= range
->id
* MAX_NB_GPIO_PER_BANK
;
1389 range
->npins
= chip
->ngpio
;
1392 ret
= gpiochip_add(chip
);
1396 gpio_chips
[alias_idx
] = oxnas_chip
;
1397 gpio_banks
= max(gpio_banks
, alias_idx
+ 1);
1399 oxnas_gpio_of_irq_setup(np
, oxnas_chip
, irq
);
1401 dev_info(&pdev
->dev
, "at address %p\n", oxnas_chip
->regbase
);
1405 dev_err(&pdev
->dev
, "Failure %i for GPIO %i\n", ret
, alias_idx
);
1410 static struct platform_driver oxnas_gpio_driver
= {
1412 .name
= "gpio-oxnas",
1413 .owner
= THIS_MODULE
,
1414 .of_match_table
= of_match_ptr(oxnas_gpio_of_match
),
1416 .probe
= oxnas_gpio_probe
,
1419 static struct platform_driver oxnas_pinctrl_driver
= {
1421 .name
= "pinctrl-oxnas",
1422 .owner
= THIS_MODULE
,
1423 .of_match_table
= of_match_ptr(oxnas_pinctrl_of_match
),
1425 .probe
= oxnas_pinctrl_probe
,
1426 .remove
= oxnas_pinctrl_remove
,
1429 static int __init
oxnas_pinctrl_init(void)
1433 ret
= platform_driver_register(&oxnas_gpio_driver
);
1436 return platform_driver_register(&oxnas_pinctrl_driver
);
1438 arch_initcall(oxnas_pinctrl_init
);
1440 static void __exit
oxnas_pinctrl_exit(void)
1442 platform_driver_unregister(&oxnas_pinctrl_driver
);
1445 module_exit(oxnas_pinctrl_exit
);
1446 MODULE_AUTHOR("Ma Hajun <mahaijuns@gmail.com>");
1447 MODULE_DESCRIPTION("Plxtech Nas782x pinctrl driver");
1448 MODULE_LICENSE("GPL v2");