1 --- a/drivers/pci/host/Kconfig
2 +++ b/drivers/pci/host/Kconfig
3 @@ -220,4 +220,9 @@ config VMD
4 To compile this driver as a module, choose M here: the
5 module will be called vmd.
8 + bool "PLX Oxnas PCIe controller"
9 + depends on ARCH_OXNAS
13 --- a/drivers/pci/host/Makefile
14 +++ b/drivers/pci/host/Makefile
15 @@ -20,6 +20,7 @@ obj-$(CONFIG_PCIE_ALTERA) += pcie-altera
16 obj-$(CONFIG_PCIE_ALTERA_MSI) += pcie-altera-msi.o
17 obj-$(CONFIG_PCIE_ROCKCHIP) += pcie-rockchip.o
18 obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o
19 +obj-$(CONFIG_PCIE_OXNAS) += pcie-oxnas.o
20 obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o
21 obj-$(CONFIG_VMD) += vmd.o
23 --- a/arch/arm/boot/dts/ox820.dtsi
24 +++ b/arch/arm/boot/dts/ox820.dtsi
28 compatible = "simple-bus";
29 - ranges = <0 0x47000000 0x1000000>;
30 + ranges = <0 0x47000000 0x2000>;
33 compatible = "arm,arm11mp-scu";
39 + pcie0: pcie-controller@47c00000 {
40 + compatible = "plxtech,nas782x-pcie";
41 + device_type = "pci";
42 + #address-cells = <3>;
45 + /* flag & space bus address host address size */
46 + ranges = < 0x82000000 0 0x48000000 0x48000000 0 0x2000000
47 + 0xC2000000 0 0x4A000000 0x4A000000 0 0x1E00000
48 + 0x81000000 0 0x4BE00000 0x4BE00000 0 0x0100000
49 + 0x80000000 0 0x4BF00000 0x4BF00000 0 0x0100000>;
51 + bus-range = <0x00 0x7f>;
53 + /* cfg inbound translator */
54 + reg = <0x47c00000 0x1000>, <0x47d00000 0x100>;
57 + phy-names = "pcie-phy";
59 + #interrupt-cells = <1>;
60 + /* wild card mask, match all bus address & interrupt specifier */
61 + /* format: bus address mask, interrupt specifier mask */
62 + /* each bit 1 means need match, 0 means ignored when match */
63 + interrupt-map-mask = <0 0 0 0>;
64 + /* format: a list of: bus address, interrupt specifier,
65 + * parent interrupt controller & specifier */
66 + interrupt-map = <0 0 0 0 &gic 0 19 0x304>;
67 + gpios = <&gpio1 12 0>;
68 + clocks = <&stdclk CLK_820_PCIEA>, <&pllb>;
69 + clock-names = "pcie", "busclk";
70 + resets = <&reset RESET_PCIEA>;
71 + reset-names = "pcie";
73 + plxtech,pcie-hcsl-bit = <2>;
74 + plxtech,pcie-ctrl-offset = <0x120>;
75 + plxtech,pcie-outbound-offset = <0x138>;
76 + status = "disabled";
79 + pcie1: pcie-controller@47e00000 {
80 + compatible = "plxtech,nas782x-pcie";
81 + device_type = "pci";
82 + #address-cells = <3>;
85 + /* flag & space bus address host address size */
86 + ranges = < 0x82000000 0 0x4C000000 0x4C000000 0 0x2000000
87 + 0xC2000000 0 0x4E000000 0x4E000000 0 0x1E00000
88 + 0x81000000 0 0x4FE00000 0x4FE00000 0 0x0100000
89 + 0x80000000 0 0x4FF00000 0x4FF00000 0 0x0100000>;
91 + bus-range = <0x80 0xff>;
93 + /* cfg inbound translator */
94 + reg = <0x47e00000 0x1000>, <0x47f00000 0x100>;
97 + phy-names = "pcie-phy";
99 + #interrupt-cells = <1>;
100 + /* wild card mask, match all bus address & interrupt specifier */
101 + /* format: bus address mask, interrupt specifier mask */
102 + /* each bit 1 means need match, 0 means ignored when match */
103 + interrupt-map-mask = <0 0 0 0>;
104 + /* format: a list of: bus address, interrupt specifier,
105 + * parent interrupt controller & specifier */
106 + interrupt-map = <0 0 0 0 &gic 0 20 0x304>;
108 + /* gpios = <&gpio1 12 0>; */
109 + clocks = <&stdclk CLK_820_PCIEB>, <&pllb>;
110 + clock-names = "pcie", "busclk";
111 + resets = <&reset RESET_PCIEB>;
112 + reset-names = "pcie";
114 + plxtech,pcie-hcsl-bit = <3>;
115 + plxtech,pcie-ctrl-offset = <0x124>;
116 + plxtech,pcie-outbound-offset = <0x174>;
117 + status = "disabled";