1 From 082a89a78e29b15008284df90441747cb742f149 Mon Sep 17 00:00:00 2001
2 From: Ezequiel Garcia <ezequiel.garcia@imgtec.com>
3 Date: Tue, 2 Dec 2014 09:58:52 -0300
4 Subject: mtd: Introduce SPI NAND framework
6 Add a new framework, to support SPI NAND devices. The framework registers
7 a NAND chip and handles the generic SPI NAND protocol, calling device-specific
8 hooks for each SPI NAND command.
10 The following is the stack design, from userspace to hardware. This commit
11 adds the "SPI NAND core" layer.
29 (based on http://lists.infradead.org/pipermail/linux-mtd/2014-December/056763.html)
31 Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
32 Signed-off-by: Ezequiel Garcia <ezequiel.garcia@imgtec.com>
33 Signed-off-by: Ian Pozella <Ian.Pozella@imgtec.com>
35 drivers/mtd/Kconfig | 2 +
36 drivers/mtd/Makefile | 1 +
37 drivers/mtd/spi-nand/Kconfig | 7 +
38 drivers/mtd/spi-nand/Makefile | 1 +
39 drivers/mtd/spi-nand/spi-nand-base.c | 566 +++++++++++++++++++++++++++++++++++
40 include/linux/mtd/spi-nand.h | 54 ++++
41 6 files changed, 631 insertions(+)
42 create mode 100644 drivers/mtd/spi-nand/Kconfig
43 create mode 100644 drivers/mtd/spi-nand/Makefile
44 create mode 100644 drivers/mtd/spi-nand/spi-nand-base.c
45 create mode 100644 include/linux/mtd/spi-nand.h
47 diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig
48 index e83a279..9163d7f 100644
49 --- a/drivers/mtd/Kconfig
50 +++ b/drivers/mtd/Kconfig
51 @@ -334,6 +334,8 @@ source "drivers/mtd/onenand/Kconfig"
53 source "drivers/mtd/lpddr/Kconfig"
55 +source "drivers/mtd/spi-nand/Kconfig"
57 source "drivers/mtd/spi-nor/Kconfig"
59 source "drivers/mtd/ubi/Kconfig"
60 diff --git a/drivers/mtd/Makefile b/drivers/mtd/Makefile
61 index 99bb9a1..38a4756 100644
62 --- a/drivers/mtd/Makefile
63 +++ b/drivers/mtd/Makefile
64 @@ -32,5 +32,6 @@ inftl-objs := inftlcore.o inftlmount.o
66 obj-y += chips/ lpddr/ maps/ devices/ nand/ onenand/ tests/
68 +obj-$(CONFIG_MTD_SPI_NAND) += spi-nand/
69 obj-$(CONFIG_MTD_SPI_NOR) += spi-nor/
70 obj-$(CONFIG_MTD_UBI) += ubi/
71 diff --git a/drivers/mtd/spi-nand/Kconfig b/drivers/mtd/spi-nand/Kconfig
73 index 0000000..17b31e1
75 +++ b/drivers/mtd/spi-nand/Kconfig
77 +menuconfig MTD_SPI_NAND
78 + tristate "SPI NAND device support"
82 + This is the framework for the SPI NAND.
84 diff --git a/drivers/mtd/spi-nand/Makefile b/drivers/mtd/spi-nand/Makefile
86 index 0000000..d454c52
88 +++ b/drivers/mtd/spi-nand/Makefile
90 +obj-$(CONFIG_MTD_SPI_NAND) += spi-nand-base.o
91 diff --git a/drivers/mtd/spi-nand/spi-nand-base.c b/drivers/mtd/spi-nand/spi-nand-base.c
93 index 0000000..5d79f85
95 +++ b/drivers/mtd/spi-nand/spi-nand-base.c
98 + * Copyright (C) 2014 Imagination Technologies Ltd.
100 + * This program is free software; you can redistribute it and/or modify
101 + * it under the terms of the GNU General Public License as published by
102 + * the Free Software Foundation; version 2 of the License.
105 + * 1. Erase and program operations need to call write_enable() first,
106 + * to clear the enable bit. This bit is cleared automatically after
107 + * the erase or program operation.
111 +#include <linux/device.h>
112 +#include <linux/err.h>
113 +#include <linux/errno.h>
114 +#include <linux/kernel.h>
115 +#include <linux/module.h>
116 +#include <linux/mtd/nand.h>
117 +#include <linux/mtd/mtd.h>
118 +#include <linux/mtd/partitions.h>
119 +#include <linux/mtd/spi-nand.h>
120 +#include <linux/of.h>
121 +#include <linux/slab.h>
123 +/* Registers common to all devices */
124 +#define SPI_NAND_LOCK_REG 0xa0
125 +#define SPI_NAND_PROT_UNLOCK_ALL 0x0
127 +#define SPI_NAND_FEATURE_REG 0xb0
128 +#define SPI_NAND_ECC_EN BIT(4)
129 +#define SPI_NAND_QUAD_EN BIT(0)
131 +#define SPI_NAND_STATUS_REG 0xc0
132 +#define SPI_NAND_STATUS_REG_ECC_MASK 0x3
133 +#define SPI_NAND_STATUS_REG_ECC_SHIFT 4
134 +#define SPI_NAND_STATUS_REG_PROG_FAIL BIT(3)
135 +#define SPI_NAND_STATUS_REG_ERASE_FAIL BIT(2)
136 +#define SPI_NAND_STATUS_REG_WREN BIT(1)
137 +#define SPI_NAND_STATUS_REG_BUSY BIT(0)
139 +#define SPI_NAND_CMD_BUF_LEN 8
141 +/* Rewind and fill the buffer with 0xff */
142 +static void spi_nand_clear_buffer(struct spi_nand *snand)
144 + snand->buf_start = 0;
145 + memset(snand->data_buf, 0xff, snand->buf_size);
148 +static int spi_nand_enable_ecc(struct spi_nand *snand)
152 + ret = snand->read_reg(snand, SPI_NAND_FEATURE_REG, snand->buf);
156 + snand->buf[0] |= SPI_NAND_ECC_EN;
157 + ret = snand->write_reg(snand, SPI_NAND_FEATURE_REG, snand->buf);
165 +static int spi_nand_disable_ecc(struct spi_nand *snand)
169 + ret = snand->read_reg(snand, SPI_NAND_FEATURE_REG, snand->buf);
173 + snand->buf[0] &= ~SPI_NAND_ECC_EN;
174 + ret = snand->write_reg(snand, SPI_NAND_FEATURE_REG, snand->buf);
177 + snand->ecc = false;
182 +static int spi_nand_enable_quad(struct spi_nand *snand)
186 + ret = snand->read_reg(snand, SPI_NAND_FEATURE_REG, snand->buf);
190 + snand->buf[0] |= SPI_NAND_QUAD_EN;
191 + ret = snand->write_reg(snand, SPI_NAND_FEATURE_REG, snand->buf);
198 + * Wait until the status register busy bit is cleared.
199 + * Returns a negatie errno on error or time out, and a non-negative status
200 + * value if the device is ready.
202 +static int spi_nand_wait_till_ready(struct spi_nand *snand)
204 + unsigned long deadline = jiffies + msecs_to_jiffies(100);
205 + bool timeout = false;
209 + * Perhaps we should set a different timeout for each
210 + * operation (reset, read, write, erase).
213 + if (time_after_eq(jiffies, deadline))
216 + ret = snand->read_reg(snand, SPI_NAND_STATUS_REG, snand->buf);
218 + dev_err(snand->dev, "error reading status register\n");
220 + } else if (!(snand->buf[0] & SPI_NAND_STATUS_REG_BUSY)) {
221 + return snand->buf[0];
227 + dev_err(snand->dev, "operation timed out\n");
232 +static int spi_nand_reset(struct spi_nand *snand)
236 + ret = snand->reset(snand);
238 + dev_err(snand->dev, "reset command failed\n");
243 + * The NAND core won't wait after a device reset, so we need
246 + ret = spi_nand_wait_till_ready(snand);
252 +static int spi_nand_status(struct spi_nand *snand)
256 + ret = snand->read_reg(snand, SPI_NAND_STATUS_REG, snand->buf);
258 + dev_err(snand->dev, "error reading status register\n");
261 + status = snand->buf[0];
263 + /* Convert this into standard NAND_STATUS values */
264 + if (status & SPI_NAND_STATUS_REG_BUSY)
267 + snand->buf[0] = NAND_STATUS_READY;
269 + if (status & SPI_NAND_STATUS_REG_PROG_FAIL ||
270 + status & SPI_NAND_STATUS_REG_ERASE_FAIL)
271 + snand->buf[0] |= NAND_STATUS_FAIL;
274 + * Since we unlock the entire device at initialization, unconditionally
275 + * set the WP bit to indicate it's not protected.
277 + snand->buf[0] |= NAND_STATUS_WP;
281 +static int spi_nand_erase(struct spi_nand *snand, int page_addr)
285 + ret = snand->write_enable(snand);
287 + dev_err(snand->dev, "write enable command failed\n");
291 + ret = snand->block_erase(snand, page_addr);
293 + dev_err(snand->dev, "block erase command failed\n");
300 +static int spi_nand_write(struct spi_nand *snand)
304 + /* Enable quad mode */
305 + ret = spi_nand_enable_quad(snand);
307 + dev_err(snand->dev, "error %d enabling quad mode\n", ret);
310 + /* Store the page to cache */
311 + ret = snand->store_cache(snand, 0, snand->buf_size, snand->data_buf);
313 + dev_err(snand->dev, "error %d storing page 0x%x to cache\n",
314 + ret, snand->page_addr);
318 + ret = snand->write_enable(snand);
320 + dev_err(snand->dev, "write enable command failed\n");
324 + /* Get page from the device cache into our internal buffer */
325 + ret = snand->write_page(snand, snand->page_addr);
327 + dev_err(snand->dev, "error %d reading page 0x%x from cache\n",
328 + ret, snand->page_addr);
335 +static int spi_nand_read_id(struct spi_nand *snand)
339 + ret = snand->read_id(snand, snand->data_buf);
341 + dev_err(snand->dev, "error %d reading ID\n", ret);
347 +static int spi_nand_read_page(struct spi_nand *snand, unsigned int page_addr,
348 + unsigned int page_offset, size_t length)
350 + unsigned int corrected = 0, ecc_error = 0;
353 + /* Load a page into the cache register */
354 + ret = snand->load_page(snand, page_addr);
356 + dev_err(snand->dev, "error %d loading page 0x%x to cache\n",
361 + ret = spi_nand_wait_till_ready(snand);
366 + snand->get_ecc_status(ret, &corrected, &ecc_error);
367 + snand->bitflips = corrected;
370 + * If there's an ECC error, print a message and notify MTD
371 + * about it. Then complete the read, to load actual data on
372 + * the buffer (instead of the status result).
375 + dev_err(snand->dev,
376 + "internal ECC error reading page 0x%x\n",
378 + snand->nand_chip.mtd.ecc_stats.failed++;
380 + snand->nand_chip.mtd.ecc_stats.corrected += corrected;
384 + /* Enable quad mode */
385 + ret = spi_nand_enable_quad(snand);
387 + dev_err(snand->dev, "error %d enabling quad mode\n", ret);
390 + /* Get page from the device cache into our internal buffer */
391 + ret = snand->read_cache(snand, page_offset, length, snand->data_buf);
393 + dev_err(snand->dev, "error %d reading page 0x%x from cache\n",
400 +static u8 spi_nand_read_byte(struct mtd_info *mtd)
402 + struct nand_chip *chip = mtd_to_nand(mtd);
403 + struct spi_nand *snand = nand_get_controller_data(chip);
406 + if (snand->buf_start < snand->buf_size)
407 + val = snand->data_buf[snand->buf_start++];
411 +static void spi_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
413 + struct nand_chip *chip = mtd_to_nand(mtd);
414 + struct spi_nand *snand = nand_get_controller_data(chip);
415 + size_t n = min_t(size_t, len, snand->buf_size - snand->buf_start);
417 + memcpy(snand->data_buf + snand->buf_start, buf, n);
418 + snand->buf_start += n;
421 +static void spi_nand_read_buf(struct mtd_info *mtd, u8 *buf, int len)
423 + struct nand_chip *chip = mtd_to_nand(mtd);
424 + struct spi_nand *snand = nand_get_controller_data(chip);
425 + size_t n = min_t(size_t, len, snand->buf_size - snand->buf_start);
427 + memcpy(buf, snand->data_buf + snand->buf_start, n);
428 + snand->buf_start += n;
431 +static int spi_nand_write_page_hwecc(struct mtd_info *mtd,
432 + struct nand_chip *chip, const uint8_t *buf, int oob_required,
435 + chip->write_buf(mtd, buf, mtd->writesize);
436 + chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
441 +static int spi_nand_read_page_hwecc(struct mtd_info *mtd,
442 + struct nand_chip *chip, uint8_t *buf, int oob_required,
445 + struct spi_nand *snand = nand_get_controller_data(chip);
447 + chip->read_buf(mtd, buf, mtd->writesize);
448 + chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
450 + return snand->bitflips;
453 +static int spi_nand_waitfunc(struct mtd_info *mtd, struct nand_chip *chip)
455 + struct spi_nand *snand = nand_get_controller_data(chip);
458 + ret = spi_nand_wait_till_ready(snand);
461 + return NAND_STATUS_FAIL;
462 + } else if (ret & SPI_NAND_STATUS_REG_PROG_FAIL) {
463 + dev_err(snand->dev, "page program failed\n");
464 + return NAND_STATUS_FAIL;
465 + } else if (ret & SPI_NAND_STATUS_REG_ERASE_FAIL) {
466 + dev_err(snand->dev, "block erase failed\n");
467 + return NAND_STATUS_FAIL;
470 + return NAND_STATUS_READY;
473 +static void spi_nand_cmdfunc(struct mtd_info *mtd, unsigned int command,
474 + int column, int page_addr)
476 + struct nand_chip *chip = mtd_to_nand(mtd);
477 + struct spi_nand *snand = nand_get_controller_data(chip);
480 + * In case there's any unsupported command, let's make sure
481 + * we don't keep garbage around in the buffer.
483 + if (command != NAND_CMD_PAGEPROG) {
484 + spi_nand_clear_buffer(snand);
485 + snand->page_addr = 0;
489 + case NAND_CMD_READ0:
490 + spi_nand_read_page(snand, page_addr, 0, mtd->writesize);
492 + case NAND_CMD_READOOB:
493 + spi_nand_disable_ecc(snand);
494 + spi_nand_read_page(snand, page_addr, mtd->writesize,
496 + spi_nand_enable_ecc(snand);
498 + case NAND_CMD_READID:
499 + spi_nand_read_id(snand);
501 + case NAND_CMD_ERASE1:
502 + spi_nand_erase(snand, page_addr);
504 + case NAND_CMD_ERASE2:
505 + /* There's nothing to do here, as the erase is one-step */
507 + case NAND_CMD_SEQIN:
508 + snand->buf_start = column;
509 + snand->page_addr = page_addr;
511 + case NAND_CMD_PAGEPROG:
512 + spi_nand_write(snand);
514 + case NAND_CMD_STATUS:
515 + spi_nand_status(snand);
517 + case NAND_CMD_RESET:
518 + spi_nand_reset(snand);
521 + dev_err(&mtd->dev, "unknown command 0x%x\n", command);
525 +static void spi_nand_select_chip(struct mtd_info *mtd, int chip)
527 + /* We need this to override the default */
530 +int spi_nand_check(struct spi_nand *snand)
534 + if (!snand->read_cache)
536 + if (!snand->load_page)
538 + if (!snand->store_cache)
540 + if (!snand->write_page)
542 + if (!snand->write_reg)
544 + if (!snand->read_reg)
546 + if (!snand->block_erase)
550 + if (!snand->write_enable)
552 + if (!snand->write_disable)
554 + if (!snand->get_ecc_status)
559 +int spi_nand_register(struct spi_nand *snand, struct nand_flash_dev *flash_ids)
561 + struct nand_chip *chip = &snand->nand_chip;
562 + struct mtd_info *mtd = nand_to_mtd(chip);
563 + struct device_node *np = snand->dev->of_node;
564 + const char __maybe_unused *of_mtd_name = NULL;
567 + /* Let's check all the hooks are in-place so we don't panic later */
568 + ret = spi_nand_check(snand);
572 + nand_set_controller_data(chip, snand);
573 + nand_set_flash_node(chip, np);
574 + chip->read_buf = spi_nand_read_buf;
575 + chip->write_buf = spi_nand_write_buf;
576 + chip->read_byte = spi_nand_read_byte;
577 + chip->cmdfunc = spi_nand_cmdfunc;
578 + chip->waitfunc = spi_nand_waitfunc;
579 + chip->select_chip = spi_nand_select_chip;
580 + chip->options |= NAND_NO_SUBPAGE_WRITE;
581 + chip->bits_per_cell = 1;
583 + mtd_set_ooblayout(mtd, snand->ooblayout);
584 + chip->ecc.read_page = spi_nand_read_page_hwecc;
585 + chip->ecc.write_page = spi_nand_write_page_hwecc;
586 + chip->ecc.mode = NAND_ECC_HW;
588 + if (of_property_read_bool(np, "nand-on-flash-bbt"))
589 + chip->bbt_options |= NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB;
591 +#ifdef CONFIG_MTD_OF_PARTS
592 + of_property_read_string(np, "linux,mtd-name", &of_mtd_name);
595 + mtd->name = of_mtd_name;
597 + mtd->name = snand->name;
598 + mtd->owner = THIS_MODULE;
600 + /* Allocate buffer to be used to read/write the internal registers */
601 + snand->buf = kmalloc(SPI_NAND_CMD_BUF_LEN, GFP_KERNEL);
605 + /* This is enabled at device power up but we'd better make sure */
606 + ret = spi_nand_enable_ecc(snand);
610 + /* Preallocate buffer for flash identification (NAND_CMD_READID) */
611 + snand->buf_size = SPI_NAND_CMD_BUF_LEN;
612 + snand->data_buf = kmalloc(snand->buf_size, GFP_KERNEL);
614 + ret = nand_scan_ident(mtd, 1, flash_ids);
619 + * SPI NAND has on-die ECC, which means we can correct as much as
620 + * we are required to. This must be done after identification of
623 + chip->ecc.strength = chip->ecc_strength_ds;
624 + chip->ecc.size = chip->ecc_step_ds;
627 + * Unlock all the device before calling nand_scan_tail. This is needed
628 + * in case the in-flash bad block table needs to be created.
629 + * We could override __nand_unlock(), but since it's not currently used
630 + * by the NAND core we call this explicitly.
632 + snand->buf[0] = SPI_NAND_PROT_UNLOCK_ALL;
633 + ret = snand->write_reg(snand, SPI_NAND_LOCK_REG, snand->buf);
637 + /* Free the buffer and allocate a good one, to fit a page plus OOB */
638 + kfree(snand->data_buf);
640 + snand->buf_size = mtd->writesize + mtd->oobsize;
641 + snand->data_buf = kmalloc(snand->buf_size, GFP_KERNEL);
642 + if (!snand->data_buf)
645 + ret = nand_scan_tail(mtd);
649 + return mtd_device_register(mtd, NULL, 0);
651 +EXPORT_SYMBOL_GPL(spi_nand_register);
653 +void spi_nand_unregister(struct spi_nand *snand)
656 + kfree(snand->data_buf);
658 +EXPORT_SYMBOL_GPL(spi_nand_unregister);
660 +MODULE_AUTHOR("Ezequiel Garcia <ezequiel.garcia@imgtec.com>");
661 +MODULE_DESCRIPTION("Framework for SPI NAND");
662 +MODULE_LICENSE("GPL v2");
663 diff --git a/include/linux/mtd/spi-nand.h b/include/linux/mtd/spi-nand.h
665 index 0000000..b5cc99f
667 +++ b/include/linux/mtd/spi-nand.h
670 + * Copyright (C) 2014 Imagination Technologies Ltd.
672 + * This program is free software; you can redistribute it and/or modify
673 + * it under the terms of the GNU General Public License as published by
674 + * the Free Software Foundation; version 2 of the License.
677 +#ifndef __LINUX_MTD_SPI_NAND_H
678 +#define __LINUX_MTD_SPI_NAND_H
680 +#include <linux/mtd/mtd.h>
681 +#include <linux/mtd/nand.h>
684 + struct nand_chip nand_chip;
685 + struct device *dev;
688 + u8 *buf, *data_buf;
691 + unsigned int page_addr;
692 + unsigned int bitflips;
694 + struct mtd_ooblayout_ops *ooblayout;
696 + int (*reset)(struct spi_nand *snand);
697 + int (*read_id)(struct spi_nand *snand, u8 *buf);
699 + int (*write_disable)(struct spi_nand *snand);
700 + int (*write_enable)(struct spi_nand *snand);
702 + int (*read_reg)(struct spi_nand *snand, u8 opcode, u8 *buf);
703 + int (*write_reg)(struct spi_nand *snand, u8 opcode, u8 *buf);
704 + void (*get_ecc_status)(unsigned int status,
705 + unsigned int *corrected,
706 + unsigned int *ecc_errors);
708 + int (*store_cache)(struct spi_nand *snand, unsigned int page_offset,
709 + size_t length, u8 *write_buf);
710 + int (*write_page)(struct spi_nand *snand, unsigned int page_addr);
711 + int (*load_page)(struct spi_nand *snand, unsigned int page_addr);
712 + int (*read_cache)(struct spi_nand *snand, unsigned int page_offset,
713 + size_t length, u8 *read_buf);
714 + int (*block_erase)(struct spi_nand *snand, unsigned int page_addr);
719 +int spi_nand_register(struct spi_nand *snand, struct nand_flash_dev *flash_ids);
720 +void spi_nand_unregister(struct spi_nand *snand);