target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-haze.dts

   1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
   2
   3 /dts-v1/;
   4
   5 #include "ipq8074.dtsi"
   6 #include "ipq8074-hk-cpu.dtsi"
   7 #include "ipq8074-ess.dtsi"
   8 #include <dt-bindings/gpio/gpio.h>
   9 #include <dt-bindings/input/input.h>
  10 #include <dt-bindings/leds/common.h>
  11
  12 / {
  13         model = "prpl Foundation Haze";
  14         compatible = "prpl,haze", "qcom,ipq8074";
  15
  16         aliases {
  17                 serial0 = &blsp1_uart5;
  18                 /* Aliases are required by U-Boot to patch MAC addresses */
  19                 ethernet0 = &dp6_syn;
  20                 ethernet1 = &dp4;
  21                 ethernet2 = &dp3;
  22                 ethernet3 = &dp2;
  23                 label-mac-device = &dp6_syn;
  24                 led-boot = &led_system_blue;
  25                 led-failsafe = &led_system_red;
  26                 led-running = &led_system_green;
  27                 led-upgrade = &led_system_blue;
  28         };
  29
  30         chosen {
  31                 stdout-path = "serial0:115200n8";
  32         };
  33
  34         keys {
  35                 compatible = "gpio-keys";
  36                 pinctrl-0 = <&button_pins>;
  37                 pinctrl-names = "default";
  38
  39                 wps-button {
  40                         label = "wps";
  41                         gpios = <&tlmm 42 GPIO_ACTIVE_LOW>;
  42                         linux,code = <KEY_WPS_BUTTON>;
  43                 };
  44
  45                 reset-button {
  46                         label = "reset";
  47                         gpios = <&tlmm 44 GPIO_ACTIVE_LOW>;
  48                         linux,code = <KEY_RESTART>;
  49                 };
  50         };
  51 };
  52
  53 &tlmm {
  54         mdio_pins: mdio-state {
  55                 mdc-pins {
  56                         pins = "gpio68";
  57                         function = "mdc";
  58                         drive-strength = <8>;
  59                         bias-pull-up;
  60                 };
  61
  62                 mdio-pins {
  63                         pins = "gpio69";
  64                         function = "mdio";
  65                         drive-strength = <8>;
  66                         bias-pull-up;
  67                 };
  68         };
  69
  70         button_pins: button-state {
  71                 wps-pins {
  72                         pins = "gpio42";
  73                         function = "gpio";
  74                         drive-strength = <8>;
  75                         bias-pull-up;
  76                 };
  77
  78                 rst-pins {
  79                         pins = "gpio44";
  80                         function = "gpio";
  81                         drive-strength = <8>;
  82                         bias-pull-up;
  83                 };
  84         };
  85
  86         i2c_3_pins: i2c-3-state {
  87                 pins = "gpio46", "gpio47";
  88                 function = "blsp2_i2c";
  89                 drive-strength = <8>;
  90                 bias-disable;
  91         };
  92 };
  93
  94 &blsp1_uart5 {
  95         status = "okay";
  96 };
  97
  98 &prng {
  99         status = "okay";
 100 };
 101
 102 &ssphy_0 {
 103         status = "okay";
 104 };
 105
 106 &qusb_phy_0 {
 107         status = "okay";
 108 };
 109
 110 &ssphy_1 {
 111         status = "okay";
 112 };
 113
 114 &qusb_phy_1 {
 115         status = "okay";
 116 };
 117
 118 &usb_0 {
 119         status = "okay";
 120 };
 121
 122 &usb_1 {
 123         status = "okay";
 124 };
 125
 126 &cryptobam {
 127         status = "okay";
 128 };
 129
 130 &crypto {
 131         status = "okay";
 132 };
 133
 134 &qpic_bam {
 135         status = "okay";
 136 };
 137
 138 &blsp1_spi1 { /* BLSP1 QUP1 */
 139         pinctrl-0 = <&spi_0_pins>;
 140         pinctrl-names = "default";
 141         cs-gpios = <0>;
 142         status = "okay";
 143
 144         flash@0 {
 145                 #address-cells = <1>;
 146                 #size-cells = <1>;
 147                 reg = <0>;
 148                 compatible = "jedec,spi-nor";
 149                 spi-max-frequency = <50000000>;
 150
 151                 partitions {
 152                         compatible = "qcom,smem-part";
 153                 };
 154         };
 155 };
 156
 157 &mdio {
 158         status = "okay";
 159
 160         pinctrl-0 = <&mdio_pins>;
 161         pinctrl-names = "default";
 162         reset-gpios = <&tlmm 22 GPIO_ACTIVE_LOW>;
 163
 164         qca8075_1: ethernet-phy@0 {
 165                 compatible = "ethernet-phy-ieee802.3-c22";
 166                 reg = <0>;
 167         };
 168
 169         qca8075_2: ethernet-phy@1 {
 170                 compatible = "ethernet-phy-ieee802.3-c22";
 171                 reg = <1>;
 172         };
 173
 174         qca8075_3: ethernet-phy@2 {
 175                 compatible = "ethernet-phy-ieee802.3-c22";
 176                 reg = <2>;
 177         };
 178
 179         qca8075_4: ethernet-phy@3 {
 180                 compatible = "ethernet-phy-ieee802.3-c22";
 181                 reg = <3>;
 182         };
 183
 184         aqr113c: ethernet-phy@5 {
 185                 compatible ="ethernet-phy-ieee802.3-c45";
 186                 reg = <8>;
 187                 reset-gpios = <&tlmm 43 GPIO_ACTIVE_LOW>;
 188         };
 189 };
 190
 191 &sdhc_1 {
 192         status = "okay";
 193
 194         vqmmc-supply = <&l11>;
 195 };
 196
 197 &switch {
 198         status = "okay";
 199
 200         switch_lan_bmp = <(ESS_PORT1 | ESS_PORT2 | ESS_PORT3 | ESS_PORT4)>; /* lan port bitmap */
 201         switch_wan_bmp = <ESS_PORT6>; /* wan port bitmap */
 202         switch_mac_mode = <MAC_MODE_PSGMII>; /* mac mode for uniphy instance0*/
 203         switch_mac_mode1 = <MAC_MODE_10GBASE_R>; /* mac mode for uniphy instance1*/
 204         switch_mac_mode2 = <MAC_MODE_USXGMII>; /* mac mode for uniphy instance2*/
 205
 206         qcom,port_phyinfo {
 207                 port@1 {
 208                         port_id = <1>;
 209                         phy_address = <0>;
 210                 };
 211                 port@2 {
 212                         port_id = <2>;
 213                         phy_address = <1>;
 214                 };
 215                 port@3 {
 216                         port_id = <3>;
 217                         phy_address = <2>;
 218                 };
 219                 port@4 {
 220                         port_id = <4>;
 221                         phy_address = <3>;
 222                 };
 223                 port@6 {
 224                         port_id = <6>;
 225                         phy_address = <8>;
 226                         compatible = "ethernet-phy-ieee802.3-c45";
 227                         ethernet-phy-ieee802.3-c45;
 228                 };
 229         };
 230 };
 231
 232 &edma {
 233         status = "okay";
 234 };
 235
 236 /* Dummy LAN port */
 237 &dp1 {
 238         status = "disabled";
 239         phy-handle = <&qca8075_1>;
 240         label = "lan4";
 241 };
 242
 243 &dp2 {
 244         status = "okay";
 245         phy-handle = <&qca8075_2>;
 246         label = "lan3";
 247 };
 248
 249 &dp3 {
 250         status = "okay";
 251         phy-handle = <&qca8075_3>;
 252         label = "lan2";
 253 };
 254
 255 &dp4 {
 256         status = "okay";
 257         phy-handle = <&qca8075_4>;
 258         label = "lan1";
 259 };
 260
 261 &dp6_syn {
 262         status = "okay";
 263         qcom,mactype = <1>;
 264         phy-handle = <&aqr113c>;
 265         label = "wan";
 266 };
 267
 268 &pcie_qmp0 {
 269         status = "okay";
 270 };
 271
 272 &pcie0 {
 273         status = "okay";
 274
 275         perst-gpio = <&tlmm 58 GPIO_ACTIVE_LOW>;
 276
 277         bridge@0,0 {
 278                 reg = <0x00020000 0 0 0 0>;
 279                 #address-cells = <3>;
 280                 #size-cells = <2>;
 281                 ranges;
 282         };
 283 };
 284
 285 &pcie_qmp1 {
 286         status = "okay";
 287 };
 288
 289 &pcie1 {
 290         status = "okay";
 291
 292         perst-gpio = <&tlmm 61 GPIO_ACTIVE_LOW>;
 293
 294         bridge@1,0 {
 295                 reg = <0x00010000 0 0 0 0>;
 296                 #address-cells = <3>;
 297                 #size-cells = <2>;
 298                 ranges;
 299
 300                 wifi@1,0 {
 301                         status = "okay";
 302
 303                         /* ath11k has no DT compatible for PCI cards */
 304                         compatible = "pci17cb,1104";
 305                         reg = <0x00010000 0 0 0 0>;
 306
 307                         qcom,ath11k-calibration-variant = "prpl-Haze";
 308                 };
 309         };
 310 };
 311
 312 &wifi {
 313         status = "okay";
 314
 315         qcom,ath11k-calibration-variant = "prpl-Haze";
 316 };
 317
 318 &blsp1_i2c3{
 319         pinctrl-0 = <&i2c_3_pins>;
 320         pinctrl-names = "default";
 321         status = "okay";
 322
 323         led-controller@30 {
 324                 compatible = "ti,lp5562";
 325                 reg = <0x30>;
 326                 clock-mode = /bits/ 8 <2>;
 327                 #address-cells = <1>;
 328                 #size-cells = <0>;
 329
 330                 led_system_red: chan@0 {
 331                         chan-name = "red";
 332                         led-cur = /bits/ 8 <0x20>;
 333                         max-cur = /bits/ 8 <0x60>;
 334                         color = <LED_COLOR_ID_RED>;
 335                         reg = <0>;
 336                 };
 337
 338                 led_system_green: chan@1 {
 339                         chan-name = "green";
 340                         led-cur = /bits/ 8 <0x20>;
 341                         max-cur = /bits/ 8 <0x60>;
 342                         color = <LED_COLOR_ID_GREEN>;
 343                         reg = <1>;
 344                 };
 345
 346                 led_system_blue: chan@2 {
 347                         chan-name = "blue";
 348                         led-cur = /bits/ 8 <0x20>;
 349                         max-cur = /bits/ 8 <0x60>;
 350                         color = <LED_COLOR_ID_BLUE>;
 351                         reg = <2>;
 352                 };
 353         };
 354 };