1 // SPDX-License-Identifier: GPL-2.0-only
3 #include <dt-bindings/net/qcom-ipq-ess.h>
7 compatible = "fixed-clock";
8 clock-frequency = <300000000>;
12 bias_pll_nss_noc_clk {
13 compatible = "fixed-clock";
14 clock-frequency = <416500000>;
20 switch: ess-switch@3a000000 {
21 compatible = "qcom,ess-switch-ipq807x";
22 reg = <0x3a000000 0x1000000>;
23 switch_access_mode = "local bus";
24 switch_cpu_bmp = <ESS_PORT0>; /* cpu port bitmap */
25 switch_inner_bmp = <ESS_PORT7>; /*inner port bitmap*/
26 clocks = <&gcc GCC_CMN_12GPLL_AHB_CLK>,
27 <&gcc GCC_CMN_12GPLL_SYS_CLK>,
28 <&gcc GCC_UNIPHY0_AHB_CLK>,
29 <&gcc GCC_UNIPHY0_SYS_CLK>,
30 <&gcc GCC_UNIPHY1_AHB_CLK>,
31 <&gcc GCC_UNIPHY1_SYS_CLK>,
32 <&gcc GCC_UNIPHY2_AHB_CLK>,
33 <&gcc GCC_UNIPHY2_SYS_CLK>,
34 <&gcc GCC_PORT1_MAC_CLK>,
35 <&gcc GCC_PORT2_MAC_CLK>,
36 <&gcc GCC_PORT3_MAC_CLK>,
37 <&gcc GCC_PORT4_MAC_CLK>,
38 <&gcc GCC_PORT5_MAC_CLK>,
39 <&gcc GCC_PORT6_MAC_CLK>,
40 <&gcc GCC_NSS_PPE_CLK>,
41 <&gcc GCC_NSS_PPE_CFG_CLK>,
42 <&gcc GCC_NSSNOC_PPE_CLK>,
43 <&gcc GCC_NSSNOC_PPE_CFG_CLK>,
44 <&gcc GCC_NSS_EDMA_CLK>,
45 <&gcc GCC_NSS_EDMA_CFG_CLK>,
46 <&gcc GCC_NSS_PPE_IPE_CLK>,
47 <&gcc GCC_NSS_PPE_BTQ_CLK>,
48 <&gcc GCC_MDIO_AHB_CLK>,
49 <&gcc GCC_NSS_NOC_CLK>,
50 <&gcc GCC_NSSNOC_SNOC_CLK>,
51 <&gcc GCC_MEM_NOC_NSS_AXI_CLK>,
52 <&gcc GCC_NSS_CRYPTO_CLK>,
53 <&gcc GCC_NSS_IMEM_CLK>,
54 <&gcc GCC_NSS_PTP_REF_CLK>,
55 <&gcc GCC_NSS_PORT1_RX_CLK>,
56 <&gcc GCC_NSS_PORT1_TX_CLK>,
57 <&gcc GCC_NSS_PORT2_RX_CLK>,
58 <&gcc GCC_NSS_PORT2_TX_CLK>,
59 <&gcc GCC_NSS_PORT3_RX_CLK>,
60 <&gcc GCC_NSS_PORT3_TX_CLK>,
61 <&gcc GCC_NSS_PORT4_RX_CLK>,
62 <&gcc GCC_NSS_PORT4_TX_CLK>,
63 <&gcc GCC_NSS_PORT5_RX_CLK>,
64 <&gcc GCC_NSS_PORT5_TX_CLK>,
65 <&gcc GCC_NSS_PORT6_RX_CLK>,
66 <&gcc GCC_NSS_PORT6_TX_CLK>,
67 <&gcc GCC_UNIPHY0_PORT1_RX_CLK>,
68 <&gcc GCC_UNIPHY0_PORT1_TX_CLK>,
69 <&gcc GCC_UNIPHY0_PORT2_RX_CLK>,
70 <&gcc GCC_UNIPHY0_PORT2_TX_CLK>,
71 <&gcc GCC_UNIPHY0_PORT3_RX_CLK>,
72 <&gcc GCC_UNIPHY0_PORT3_TX_CLK>,
73 <&gcc GCC_UNIPHY0_PORT4_RX_CLK>,
74 <&gcc GCC_UNIPHY0_PORT4_TX_CLK>,
75 <&gcc GCC_UNIPHY0_PORT5_RX_CLK>,
76 <&gcc GCC_UNIPHY0_PORT5_TX_CLK>,
77 <&gcc GCC_UNIPHY1_PORT5_RX_CLK>,
78 <&gcc GCC_UNIPHY1_PORT5_TX_CLK>,
79 <&gcc GCC_UNIPHY2_PORT6_RX_CLK>,
80 <&gcc GCC_UNIPHY2_PORT6_TX_CLK>,
81 <&gcc NSS_PORT5_RX_CLK_SRC>,
82 <&gcc NSS_PORT5_TX_CLK_SRC>;
83 clock-names = "cmn_ahb_clk", "cmn_sys_clk",
84 "uniphy0_ahb_clk", "uniphy0_sys_clk",
85 "uniphy1_ahb_clk", "uniphy1_sys_clk",
86 "uniphy2_ahb_clk", "uniphy2_sys_clk",
87 "port1_mac_clk", "port2_mac_clk",
88 "port3_mac_clk", "port4_mac_clk",
89 "port5_mac_clk", "port6_mac_clk",
90 "nss_ppe_clk", "nss_ppe_cfg_clk",
91 "nssnoc_ppe_clk", "nssnoc_ppe_cfg_clk",
92 "nss_edma_clk", "nss_edma_cfg_clk",
93 "nss_ppe_ipe_clk", "nss_ppe_btq_clk",
94 "gcc_mdio_ahb_clk", "gcc_nss_noc_clk",
95 "gcc_nssnoc_snoc_clk",
96 "gcc_mem_noc_nss_axi_clk",
99 "gcc_nss_ptp_ref_clk",
100 "nss_port1_rx_clk", "nss_port1_tx_clk",
101 "nss_port2_rx_clk", "nss_port2_tx_clk",
102 "nss_port3_rx_clk", "nss_port3_tx_clk",
103 "nss_port4_rx_clk", "nss_port4_tx_clk",
104 "nss_port5_rx_clk", "nss_port5_tx_clk",
105 "nss_port6_rx_clk", "nss_port6_tx_clk",
106 "uniphy0_port1_rx_clk",
107 "uniphy0_port1_tx_clk",
108 "uniphy0_port2_rx_clk",
109 "uniphy0_port2_tx_clk",
110 "uniphy0_port3_rx_clk",
111 "uniphy0_port3_tx_clk",
112 "uniphy0_port4_rx_clk",
113 "uniphy0_port4_tx_clk",
114 "uniphy0_port5_rx_clk",
115 "uniphy0_port5_tx_clk",
116 "uniphy1_port5_rx_clk",
117 "uniphy1_port5_tx_clk",
118 "uniphy2_port6_rx_clk",
119 "uniphy2_port6_tx_clk",
120 "nss_port5_rx_clk_src",
121 "nss_port5_tx_clk_src";
122 resets = <&gcc GCC_PPE_FULL_RESET>,
123 <&gcc GCC_UNIPHY0_SOFT_RESET>,
124 <&gcc GCC_UNIPHY0_XPCS_RESET>,
125 <&gcc GCC_UNIPHY1_SOFT_RESET>,
126 <&gcc GCC_UNIPHY1_XPCS_RESET>,
127 <&gcc GCC_UNIPHY2_SOFT_RESET>,
128 <&gcc GCC_UNIPHY2_XPCS_RESET>,
129 <&gcc GCC_NSSPORT1_RESET>,
130 <&gcc GCC_NSSPORT2_RESET>,
131 <&gcc GCC_NSSPORT3_RESET>,
132 <&gcc GCC_NSSPORT4_RESET>,
133 <&gcc GCC_NSSPORT5_RESET>,
134 <&gcc GCC_NSSPORT6_RESET>;
135 reset-names = "ppe_rst", "uniphy0_soft_rst",
136 "uniphy0_xpcs_rst", "uniphy1_soft_rst",
137 "uniphy1_xpcs_rst", "uniphy2_soft_rst",
138 "uniphy2_xpcs_rst", "nss_port1_rst",
139 "nss_port2_rst", "nss_port3_rst",
140 "nss_port4_rst", "nss_port5_rst",
144 switch_mac_mode = <MAC_MODE_DISABLED>; /* MAC mode for UNIPHY instance 0 */
145 switch_mac_mode1 = <MAC_MODE_DISABLED>; /* MAC mode for UNIPHY instance 1 */
146 switch_mac_mode2 = <MAC_MODE_DISABLED>; /* MAC mode for UNIPHY instance 2 */
148 bm_tick_mode = <0>; /* bm tick mode */
149 tm_tick_mode = <0>; /* tm tick mode */
153 port_scheduler_resource {
156 ucast_queue = <0 143>;
157 mcast_queue = <256 271>;
166 ucast_queue = <144 159>;
167 mcast_queue = <272 275>;
176 ucast_queue = <160 175>;
177 mcast_queue = <276 279>;
186 ucast_queue = <176 191>;
187 mcast_queue = <280 283>;
196 ucast_queue = <192 207>;
197 mcast_queue = <284 287>;
206 ucast_queue = <208 223>;
207 mcast_queue = <288 291>;
216 ucast_queue = <224 239>;
217 mcast_queue = <292 295>;
226 ucast_queue = <240 255>;
227 mcast_queue = <296 299>;
235 port_scheduler_config {
240 sp = <0 1>; /*L0 SPs*/
241 /*cpri cdrr epri edrr*/
248 ucast_queue = <0 4 8>;
250 mcast_queue = <256 260>;
251 /*sp cpri cdrr epri edrr*/
255 ucast_queue = <1 5 9>;
256 mcast_queue = <257 261>;
260 ucast_queue = <2 6 10>;
261 mcast_queue = <258 262>;
265 ucast_queue = <3 7 11>;
266 mcast_queue = <259 263>;
286 ucast_loop_pri = <16>;
288 mcast_loop_pri = <4>;
289 cfg = <36 0 48 0 48>;
308 ucast_loop_pri = <16>;
310 mcast_loop_pri = <4>;
311 cfg = <40 0 64 0 64>;
330 ucast_loop_pri = <16>;
332 mcast_loop_pri = <4>;
333 cfg = <44 0 80 0 80>;
352 ucast_loop_pri = <16>;
354 mcast_loop_pri = <4>;
355 cfg = <48 0 96 0 96>;
374 ucast_loop_pri = <16>;
376 mcast_loop_pri = <4>;
377 cfg = <52 0 112 0 112>;
396 ucast_loop_pri = <16>;
398 mcast_loop_pri = <4>;
399 cfg = <56 0 128 0 128>;
418 ucast_loop_pri = <16>;
420 cfg = <60 0 144 0 144>;
428 compatible = "qcom,ess-uniphy";
429 reg = <0x7a00000 0x30000>;
430 uniphy_access_mode = "local bus";
433 edma: edma@3ab00000 {
434 compatible = "qcom,edma";
435 reg = <0x3ab00000 0x76900>;
436 reg-names = "edma-reg-base";
437 qcom,txdesc-ring-start = <23>;
438 qcom,txdesc-rings = <1>;
439 qcom,txcmpl-ring-start = <7>;
440 qcom,txcmpl-rings = <1>;
441 qcom,rxfill-ring-start = <7>;
442 qcom,rxfill-rings = <1>;
443 qcom,rxdesc-ring-start = <15>;
444 qcom,rxdesc-rings = <1>;
445 interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
446 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
447 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
448 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
449 resets = <&gcc GCC_EDMA_HW_RESET>;
450 reset-names = "edma_rst";
455 device_type = "network";
456 compatible = "qcom,nss-dp";
458 reg = <0x3a001000 0x200>;
460 local-mac-address = [000000000000];
466 device_type = "network";
467 compatible = "qcom,nss-dp";
469 reg = <0x3a001200 0x200>;
471 local-mac-address = [000000000000];
477 device_type = "network";
478 compatible = "qcom,nss-dp";
480 reg = <0x3a001400 0x200>;
482 local-mac-address = [000000000000];
488 device_type = "network";
489 compatible = "qcom,nss-dp";
491 reg = <0x3a001600 0x200>;
493 local-mac-address = [000000000000];
499 device_type = "network";
500 compatible = "qcom,nss-dp";
502 reg = <0x3a001800 0x200>;
504 local-mac-address = [000000000000];
510 device_type = "network";
511 compatible = "qcom,nss-dp";
513 reg = <0x3a001a00 0x200>;
515 local-mac-address = [000000000000];
520 dp5_syn: dp5-syn@3a003000 {
521 device_type = "network";
522 compatible = "qcom,nss-dp";
524 reg = <0x3a003000 0x3fff>;
526 local-mac-address = [000000000000];
531 dp6_syn: dp6-syn@3a007000 {
532 device_type = "network";
533 compatible = "qcom,nss-dp";
535 reg = <0x3a007000 0x3fff>;
537 local-mac-address = [000000000000];