1 From e4d7544ce092807e8c5aeb618cec30e2eb9b40c2 Mon Sep 17 00:00:00 2001
2 From: Mantas Pucka <mantas@8devices.com>
3 Date: Mon, 24 Apr 2023 15:13:32 +0300
4 Subject: [PATCH 3/3] arm64: dts: qcom: ipq6018: add SDHCI node
6 IPQ6018 has one SD/eMMC controller, add node for it.
8 Signed-off-by: Mantas Pucka <mantas@8devices.com>
9 Tested-by: Robert Marko <robimarko@gmail.com>
11 arch/arm64/boot/dts/qcom/ipq6018.dtsi | 23 +++++++++++++++++++++++
12 1 file changed, 23 insertions(+)
14 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
15 +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
17 reg = <0x0 0x01937000 0x0 0x21000>;
20 + sdhc_1: mmc@7804000 {
21 + compatible = "qcom,ipq6018-sdhci", "qcom,sdhci-msm-v5";
22 + reg = <0x0 0x07804000 0x0 0x1000>,
23 + <0x0 0x07805000 0x0 0x1000>,
24 + <0x0 0x07808000 0x0 0x2000>;
25 + reg-names = "hc", "cqhci", "ice";
27 + interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
28 + <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
29 + interrupt-names = "hc_irq", "pwr_irq";
31 + clocks = <&gcc GCC_SDCC1_AHB_CLK>,
32 + <&gcc GCC_SDCC1_APPS_CLK>,
34 + <&gcc GCC_SDCC1_ICE_CORE_CLK>;
35 + clock-names = "iface", "core", "xo", "ice";
37 + resets = <&gcc GCC_SDCC1_BCR>;
40 + status = "disabled";
43 blsp_dma: dma-controller@7884000 {
44 compatible = "qcom,bam-v1.7.0";
45 reg = <0x0 0x07884000 0x0 0x2b000>;