6 compatible = "ralink,mt7620a-soc";
19 compatible = "mips,mips24KEc";
25 bootargs = "console=ttyS0,57600";
30 #interrupt-cells = <1>;
32 compatible = "mti,cpu-interrupt-controller";
35 palmbus: palmbus@10000000 {
36 compatible = "palmbus";
37 reg = <0x10000000 0x200000>;
38 ranges = <0x0 0x10000000 0x1FFFFF>;
44 compatible = "ralink,mt7620a-sysc", "ralink,rt3050-sysc", "syscon";
49 compatible = "ralink,mt7620a-timer", "ralink,rt2880-timer";
52 interrupt-parent = <&intc>;
56 watchdog: watchdog@120 {
57 compatible = "ralink,mt7620a-wdt", "ralink,rt2880-wdt";
60 resets = <&rstctrl 8>;
63 interrupt-parent = <&intc>;
68 compatible = "ralink,mt7620a-intc", "ralink,rt2880-intc";
71 resets = <&rstctrl 19>;
75 #interrupt-cells = <1>;
77 interrupt-parent = <&cpuintc>;
82 compatible = "ralink,mt7620a-memc", "ralink,rt3050-memc";
85 resets = <&rstctrl 20>;
88 interrupt-parent = <&intc>;
93 compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a";
96 resets = <&rstctrl 12>;
99 interrupt-parent = <&intc>;
108 compatible = "ralink,mt7620a-gpio", "ralink,rt2880-gpio";
111 resets = <&rstctrl 13>;
114 interrupt-parent = <&intc>;
121 ralink,gpio-base = <0>;
122 ralink,register-map = [ 00 04 08 0c
128 compatible = "ralink,mt7620a-gpio", "ralink,rt2880-gpio";
131 interrupt-parent = <&intc>;
138 ralink,gpio-base = <24>;
139 ralink,register-map = [ 00 04 08 0c
147 compatible = "ralink,mt7620a-gpio", "ralink,rt2880-gpio";
150 interrupt-parent = <&intc>;
157 ralink,gpio-base = <40>;
158 ralink,register-map = [ 00 04 08 0c
166 compatible = "ralink,mt7620a-gpio", "ralink,rt2880-gpio";
169 interrupt-parent = <&intc>;
176 ralink,gpio-base = <72>;
177 ralink,register-map = [ 00 04 08 0c
185 compatible = "ralink,rt2880-i2c";
188 resets = <&rstctrl 16>;
191 #address-cells = <1>;
196 pinctrl-names = "default";
197 pinctrl-0 = <&i2c_pins>;
201 compatible = "mediatek,mt7620-i2s";
204 resets = <&rstctrl 17>;
207 interrupt-parent = <&intc>;
215 dma-names = "tx", "rx";
221 compatible = "ralink,mt7620a-spi", "ralink,rt2880-spi";
224 resets = <&rstctrl 18>;
227 #address-cells = <1>;
232 pinctrl-names = "default";
233 pinctrl-0 = <&spi_pins>;
237 compatible = "ralink,rt2880-spi";
240 resets = <&rstctrl 18>;
243 #address-cells = <1>;
248 pinctrl-names = "default";
249 pinctrl-0 = <&spi_cs1>;
252 uartlite: uartlite@c00 {
253 compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a";
256 resets = <&rstctrl 19>;
257 reset-names = "uartl";
259 interrupt-parent = <&intc>;
264 pinctrl-names = "default";
265 pinctrl-0 = <&uartlite_pins>;
268 systick: systick@d00 {
269 compatible = "ralink,mt7620a-systick", "ralink,cevt-systick";
272 resets = <&rstctrl 28>;
273 reset-names = "intc";
275 interrupt-parent = <&cpuintc>;
280 compatible = "ralink,mt7620a-pcm";
281 reg = <0x2000 0x800>;
283 resets = <&rstctrl 11>;
286 interrupt-parent = <&intc>;
293 compatible = "ralink,mt7620a-gdma", "ralink,rt3883-gdma";
294 reg = <0x2800 0x800>;
296 resets = <&rstctrl 14>;
299 interrupt-parent = <&intc>;
303 #dma-channels = <16>;
304 #dma-requests = <16>;
311 compatible = "ralink,rt2880-pinmux";
312 pinctrl-names = "default";
313 pinctrl-0 = <&state_default>;
315 state_default: pinctrl0 {
318 pcm_i2s_pins: pcm_i2s {
321 function = "pcm i2s";
325 uartf_gpio_pins: uartf_gpio {
328 function = "gpio uartf";
332 gpio_i2s_pins: gpio_i2s {
335 function = "gpio i2s";
348 groups = "spi refclk";
349 function = "spi refclk";
360 uartlite_pins: uartlite {
363 function = "uartlite";
374 mdio_refclk_pins: mdio_refclk {
395 rgmii1_pins: rgmii1 {
402 rgmii2_pins: rgmii2 {
412 function = "pcie rst";
423 pa_gpio_pins: pa_gpio {
439 compatible = "ralink,mt7620a-reset", "ralink,rt2880-reset";
444 compatible = "ralink,rt2880-clock";
449 compatible = "mediatek,mt7620-usbphy";
452 ralink,sysctl = <&sysc>;
453 resets = <&rstctrl 22 &rstctrl 25>;
454 reset-names = "host", "device";
456 clocks = <&clkctrl 22 &clkctrl 25>;
457 clock-names = "host", "device";
460 ethernet: ethernet@10100000 {
461 compatible = "mediatek,mt7620-eth";
462 reg = <0x10100000 0x10000>;
464 #address-cells = <1>;
467 interrupt-parent = <&cpuintc>;
470 resets = <&rstctrl 21 &rstctrl 23>;
471 reset-names = "fe", "esw";
473 mediatek,switch = <&gsw>;
476 compatible = "mediatek,mt7620a-gsw-port", "mediatek,eth-port";
483 compatible = "mediatek,mt7620a-gsw-port", "mediatek,eth-port";
490 #address-cells = <1>;
498 compatible = "mediatek,mt7620-gsw";
499 reg = <0x10110000 0x8000>;
501 resets = <&rstctrl 23>;
504 interrupt-parent = <&intc>;
508 sdhci: sdhci@10130000 {
509 compatible = "ralink,mt7620-sdhci";
510 reg = <0x10130000 0x4000>;
512 interrupt-parent = <&intc>;
515 pinctrl-names = "default";
516 pinctrl-0 = <&sdhci_pins>;
521 ehci: ehci@101c0000 {
522 #address-cells = <1>;
524 compatible = "generic-ehci";
525 reg = <0x101c0000 0x1000>;
527 interrupt-parent = <&intc>;
537 #trigger-source-cells = <0>;
541 ohci: ohci@101c1000 {
542 #address-cells = <1>;
544 compatible = "generic-ohci";
545 reg = <0x101c1000 0x1000>;
547 interrupt-parent = <&intc>;
557 #trigger-source-cells = <0>;
561 pcie: pcie@10140000 {
562 compatible = "mediatek,mt7620-pci";
563 reg = <0x10140000 0x100
566 #address-cells = <3>;
569 resets = <&rstctrl 26>;
570 reset-names = "pcie0";
572 clocks = <&clkctrl 26>;
573 clock-names = "pcie0";
575 interrupt-parent = <&cpuintc>;
578 pinctrl-names = "default";
579 pinctrl-0 = <&pcie_pins>;
585 0x02000000 0 0x00000000 0x20000000 0 0x10000000 /* pci memory */
586 0x01000000 0 0x00000000 0x10160000 0 0x00010000 /* io space */
592 reg = <0x0000 0 0 0 0>;
594 #address-cells = <3>;
603 wmac: wmac@10180000 {
604 compatible = "ralink,rt7620-wmac", "ralink,rt2880-wmac";
605 reg = <0x10180000 0x40000>;
607 interrupt-parent = <&cpuintc>;
610 ralink,eeprom = "soc_wmac.eeprom";