6 compatible = "ralink,mt7620a-soc";
19 compatible = "mips,mips24KEc";
25 bootargs = "console=ttyS0,57600";
30 #interrupt-cells = <1>;
32 compatible = "mti,cpu-interrupt-controller";
35 palmbus: palmbus@10000000 {
36 compatible = "palmbus";
37 reg = <0x10000000 0x200000>;
38 ranges = <0x0 0x10000000 0x1FFFFF>;
44 compatible = "ralink,mt7620-sysc", "syscon";
51 compatible = "ralink,mt7620a-timer", "ralink,rt2880-timer";
56 interrupt-parent = <&intc>;
60 watchdog: watchdog@120 {
61 compatible = "ralink,mt7620a-wdt", "ralink,rt2880-wdt";
69 interrupt-parent = <&intc>;
74 compatible = "ralink,mt7620a-intc", "ralink,rt2880-intc";
78 #interrupt-cells = <1>;
80 interrupt-parent = <&cpuintc>;
85 compatible = "ralink,mt7620a-memc", "ralink,rt3050-memc";
88 interrupt-parent = <&intc>;
93 compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a";
100 interrupt-parent = <&intc>;
109 compatible = "ralink,mt7620a-gpio", "ralink,rt2880-gpio";
112 interrupt-parent = <&intc>;
119 ralink,gpio-base = <0>;
120 ralink,register-map = [ 00 04 08 0c
126 compatible = "ralink,mt7620a-gpio", "ralink,rt2880-gpio";
129 interrupt-parent = <&intc>;
136 ralink,gpio-base = <24>;
137 ralink,register-map = [ 00 04 08 0c
145 compatible = "ralink,mt7620a-gpio", "ralink,rt2880-gpio";
148 interrupt-parent = <&intc>;
155 ralink,gpio-base = <40>;
156 ralink,register-map = [ 00 04 08 0c
164 compatible = "ralink,mt7620a-gpio", "ralink,rt2880-gpio";
167 interrupt-parent = <&intc>;
174 ralink,gpio-base = <72>;
175 ralink,register-map = [ 00 04 08 0c
183 compatible = "ralink,rt2880-i2c";
191 #address-cells = <1>;
196 pinctrl-names = "default";
197 pinctrl-0 = <&i2c_pins>;
201 compatible = "mediatek,mt7620-i2s";
209 interrupt-parent = <&intc>;
217 dma-names = "tx", "rx";
223 compatible = "ralink,mt7620a-spi", "ralink,rt2880-spi";
231 #address-cells = <1>;
236 pinctrl-names = "default";
237 pinctrl-0 = <&spi_pins>;
241 compatible = "ralink,rt2880-spi";
249 #address-cells = <1>;
254 pinctrl-names = "default";
255 pinctrl-0 = <&spi_cs1>;
258 uartlite: uartlite@c00 {
259 compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a";
266 interrupt-parent = <&intc>;
271 pinctrl-names = "default";
272 pinctrl-0 = <&uartlite_pins>;
275 systick: systick@d00 {
276 compatible = "ralink,mt7620a-systick", "ralink,cevt-systick";
279 interrupt-parent = <&cpuintc>;
284 compatible = "ralink,mt7620a-pcm";
285 reg = <0x2000 0x800>;
290 interrupt-parent = <&intc>;
297 compatible = "ralink,mt7620a-gdma", "ralink,rt3883-gdma";
298 reg = <0x2800 0x800>;
303 interrupt-parent = <&intc>;
307 #dma-channels = <16>;
308 #dma-requests = <16>;
315 compatible = "ralink,rt2880-pinmux";
316 pinctrl-names = "default";
317 pinctrl-0 = <&state_default>;
319 state_default: pinctrl0 {
322 pcm_i2s_pins: pcm_i2s {
325 function = "pcm i2s";
329 uartf_gpio_pins: uartf_gpio {
332 function = "gpio uartf";
336 gpio_i2s_pins: gpio_i2s {
339 function = "gpio i2s";
352 groups = "spi refclk";
353 function = "spi refclk";
364 uartlite_pins: uartlite {
367 function = "uartlite";
378 mdio_refclk_pins: mdio_refclk {
399 rgmii1_pins: rgmii1 {
406 rgmii2_pins: rgmii2 {
416 function = "pcie rst";
427 pa_gpio_pins: pa_gpio {
443 compatible = "mediatek,mt7620-usbphy";
446 ralink,sysctl = <&sysc>;
447 /* usb phy reset is only controled by RSTCTRL bit 25 */
448 resets = <&sysc 25>, <&sysc 22>;
449 reset-names = "host", "device";
452 ethernet: ethernet@10100000 {
453 compatible = "mediatek,mt7620-eth";
454 reg = <0x10100000 0x10000>;
456 #address-cells = <1>;
459 interrupt-parent = <&cpuintc>;
462 resets = <&sysc 21>, <&sysc 23>;
463 reset-names = "fe", "esw";
465 mediatek,switch = <&gsw>;
468 compatible = "mediatek,mt7620a-gsw-port", "mediatek,eth-port";
475 compatible = "mediatek,mt7620a-gsw-port", "mediatek,eth-port";
482 #address-cells = <1>;
490 compatible = "mediatek,mt7620-gsw";
491 reg = <0x10110000 0x8000>;
496 interrupt-parent = <&intc>;
500 sdhci: sdhci@10130000 {
501 compatible = "ralink,mt7620-sdhci";
502 reg = <0x10130000 0x4000>;
504 interrupt-parent = <&intc>;
507 pinctrl-names = "default";
508 pinctrl-0 = <&sdhci_pins>;
513 ehci: ehci@101c0000 {
514 #address-cells = <1>;
516 compatible = "generic-ehci";
517 reg = <0x101c0000 0x1000>;
519 interrupt-parent = <&intc>;
529 #trigger-source-cells = <0>;
533 ohci: ohci@101c1000 {
534 #address-cells = <1>;
536 compatible = "generic-ohci";
537 reg = <0x101c1000 0x1000>;
539 interrupt-parent = <&intc>;
549 #trigger-source-cells = <0>;
553 pcie: pcie@10140000 {
554 compatible = "mediatek,mt7620-pci";
555 reg = <0x10140000 0x100
558 #address-cells = <3>;
562 reset-names = "pcie0";
564 interrupt-parent = <&cpuintc>;
567 pinctrl-names = "default";
568 pinctrl-0 = <&pcie_pins>;
574 0x02000000 0 0x00000000 0x20000000 0 0x10000000 /* pci memory */
575 0x01000000 0 0x00000000 0x10160000 0 0x00010000 /* io space */
581 reg = <0x0000 0 0 0 0>;
583 #address-cells = <3>;
592 wmac: wmac@10180000 {
593 compatible = "ralink,rt7620-wmac", "ralink,rt2880-wmac";
594 reg = <0x10180000 0x40000>;
598 interrupt-parent = <&cpuintc>;
601 ralink,eeprom = "soc_wmac.eeprom";