1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 #include "mt7620a.dtsi"
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/input/input.h>
7 #include <dt-bindings/mtd/partitions/uimage.h>
10 compatible = "dlink,dwr-118-a1", "ralink,mt7620a-soc";
11 model = "D-Link DWR-118 A1";
14 led-boot = &led_internet;
15 led-failsafe = &led_internet;
16 led-upgrade = &led_internet;
20 compatible = "gpio-keys";
24 gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
25 linux,code = <KEY_WPS_BUTTON>;
30 gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
31 linux,code = <KEY_RESTART>;
36 compatible = "gpio-leds";
40 gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
43 led_internet: internet {
44 label = "green:internet";
45 gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
50 gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
54 label = "green:wlan2g";
55 gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
60 gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
61 trigger-sources = <&ohci_port1>, <&ehci_port1>;
62 linux,default-trigger = "usbport";
67 compatible = "gpio-export";
71 gpio-export,name = "usb";
72 gpio-export,output = <0>;
73 gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
94 compatible = "jedec,spi-nor";
96 spi-max-frequency = <80000000>;
99 compatible = "fixed-partitions";
100 #address-cells = <1>;
110 compatible = "openwrt,uimage", "denx,uimage";
111 openwrt,ih-magic = <IH_MAGIC_OKLI>;
112 openwrt,offset = <0x10000>;
114 reg = <0x10000 0xfe0000>;
117 config: partition@ff0000 {
118 compatible = "nvmem-cells";
120 reg = <0xff0000 0x10000>;
121 #address-cells = <1>;
125 eeprom_config_e083: eeprom@e083 {
126 reg = <0xe083 0x200>;
129 macaddr_config_e496: macaddr@e496 {
147 groups = "ephy", "uartf", "spi refclk", "wled";
158 reg = <0x0000 0 0 0 0>;
159 nvmem-cells = <&eeprom_config_e083>, <&macaddr_config_e496>;
160 nvmem-cell-names = "eeprom", "mac-address";
161 mac-address-increment = <(2)>;
171 pinctrl-names = "default";
172 pinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>;
176 phy-handle = <&phy4>;
182 phy-handle = <&phy5>;
189 phy4: ethernet-phy@4 {
191 phy-mode = "rgmii-rxid";
194 phy5: ethernet-phy@5 {
196 phy-mode = "rgmii-rxid";
203 mediatek,ephy-base = /bits/ 8 <8>;