1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2016 Rohan Murch <rohan.murch@gmail.com>
4 * Copyright (C) 2016 Hans Ulli Kroll <ulli.kroll@googlemail.com>
5 * Copyright (C) 2017 James McKenzie <openwrt@madingley.org>
8 #include "mt7620a.dtsi"
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/leds/common.h>
13 #include <dt-bindings/mtd/partitions/uimage.h>
16 compatible = "edimax,br-6478ac-v2", "ralink,mt7620a-soc";
17 model = "Edimax BR-6478AC v2";
20 led-boot = &led_power;
21 led-failsafe = &led_power;
22 led-running = &led_power;
23 led-upgrade = &led_power;
27 compatible = "gpio-keys";
31 gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
32 linux,code = <KEY_RESTART>;
37 compatible = "gpio-leds";
40 function = LED_FUNCTION_POWER;
41 color = <LED_COLOR_ID_WHITE>;
42 gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
46 label = "blue:internet";
47 gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
51 function = LED_FUNCTION_WLAN;
52 color = <LED_COLOR_ID_BLUE>;
53 gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
57 function = LED_FUNCTION_USB;
58 color = <LED_COLOR_ID_BLUE>;
59 gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
60 trigger-sources = <&ohci_port1>, <&ehci_port1>;
61 linux,default-trigger = "usbport";
66 compatible = "gpio-export";
69 gpio-export,name="usb-power";
70 gpio-export,output=<1>;
71 gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>;
84 compatible = "jedec,spi-nor";
86 spi-max-frequency = <10000000>;
89 compatible = "fixed-partitions";
100 label = "u-boot-env";
101 reg = <0x30000 0x10000>;
107 reg = <0x40000 0x10000>;
111 compatible = "fixed-layout";
112 #address-cells = <1>;
115 eeprom_factory_0: eeprom@0 {
119 eeprom_factory_8000: eeprom@8000 {
120 reg = <0x8000 0x200>;
123 macaddr_factory_4: macaddr@4 {
131 reg = <0x50000 0x20000>;
136 compatible = "openwrt,uimage", "denx,uimage";
137 openwrt,offset = <FW_EDIMAX_OFFSET>;
138 openwrt,partition-magic = <FW_MAGIC_EDIMAX>;
140 reg = <0x00070000 0x00790000>;
148 groups = "i2c", "uartf", "nd_sd";
154 pinctrl-names = "default";
155 pinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>;
157 nvmem-cells = <&macaddr_factory_4>;
158 nvmem-cell-names = "mac-address";
160 mediatek,portmap = "wllll";
164 mediatek,fixed-link = <1000 1 1 1>;
171 phy0: ethernet-phy@0 {
176 phy1: ethernet-phy@1 {
181 phy2: ethernet-phy@2 {
186 phy3: ethernet-phy@3 {
191 phy4: ethernet-phy@4 {
196 phy1f: ethernet-phy@1f {
204 mediatek,ephy-base = /bits/ 8 <12>;
208 nvmem-cells = <&eeprom_factory_0>;
209 nvmem-cell-names = "eeprom";
218 reg = <0x0000 0 0 0 0>;
219 nvmem-cells = <&eeprom_factory_8000>;
220 nvmem-cell-names = "eeprom";
221 ieee80211-freq-limit = <5000000 6000000>;