target/linux/ramips/dts/mt7620a_edimax_br-6478ac-v2.dts

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2016 Rohan Murch <rohan.murch@gmail.com>
   4  * Copyright (C) 2016 Hans Ulli Kroll <ulli.kroll@googlemail.com>
   5  * Copyright (C) 2017 James McKenzie <openwrt@madingley.org>
   6  */
   7
   8 #include "mt7620a.dtsi"
   9
  10 #include <dt-bindings/gpio/gpio.h>
  11 #include <dt-bindings/input/input.h>
  12 #include <dt-bindings/mtd/partitions/uimage.h>
  13
  14 / {
  15         compatible = "edimax,br-6478ac-v2", "ralink,mt7620a-soc";
  16         model = "Edimax BR-6478AC v2";
  17
  18         aliases {
  19                 led-boot = &led_power;
  20                 led-failsafe = &led_power;
  21                 led-running = &led_power;
  22                 led-upgrade = &led_power;
  23         };
  24
  25         keys {
  26                 compatible = "gpio-keys";
  27
  28                 reset_wps {
  29                         label = "reset_wps";
  30                         gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
  31                         linux,code = <KEY_RESTART>;
  32                 };
  33         };
  34
  35         leds {
  36                 compatible = "gpio-leds";
  37
  38                 led_power: power {
  39                         label = "white:power";
  40                         gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
  41                 };
  42
  43                 internet {
  44                         label = "blue:internet";
  45                         gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
  46                 };
  47
  48                 wlan {
  49                         label = "blue:wlan";
  50                         gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
  51                 };
  52
  53                 usb {
  54                         label = "blue:usb";
  55                         gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
  56                         trigger-sources = <&ohci_port1>, <&ehci_port1>;
  57                         linux,default-trigger = "usbport";
  58                 };
  59         };
  60
  61         gpio_export {
  62                 compatible = "gpio-export";
  63                 #size-cells = <0>;
  64                 usb-power {
  65                         gpio-export,name="usb-power";
  66                         gpio-export,output=<1>;
  67                         gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>;
  68                 };
  69         };
  70 };
  71
  72 &gpio2 {
  73         status = "okay";
  74 };
  75
  76 &spi0 {
  77         status = "okay";
  78
  79         flash@0 {
  80                 compatible = "jedec,spi-nor";
  81                 reg = <0>;
  82                 spi-max-frequency = <10000000>;
  83
  84                 partitions {
  85                         compatible = "fixed-partitions";
  86                         #address-cells = <1>;
  87                         #size-cells = <1>;
  88
  89                         partition@0 {
  90                                 label = "u-boot";
  91                                 reg = <0x0 0x30000>;
  92                                 read-only;
  93                         };
  94
  95                         partition@30000 {
  96                                 label = "u-boot-env";
  97                                 reg = <0x30000 0x10000>;
  98                                 read-only;
  99                         };
 100
 101                         factory: partition@40000 {
 102                                 compatible = "nvmem-cells";
 103                                 label = "factory";
 104                                 reg = <0x40000 0x10000>;
 105                                 #address-cells = <1>;
 106                                 #size-cells = <1>;
 107                                 read-only;
 108
 109                                 eeprom_factory_0: eeprom@0 {
 110                                         reg = <0x0 0x200>;
 111                                 };
 112
 113                                 macaddr_factory_4: macaddr@4 {
 114                                         reg = <0x4 0x6>;
 115                                 };
 116                         };
 117
 118                         partition@50000 {
 119                                 label = "cimage";
 120                                 reg = <0x50000 0x20000>;
 121                                 read-only;
 122                         };
 123
 124                         partition@70000 {
 125                                 compatible = "openwrt,uimage", "denx,uimage";
 126                                 openwrt,offset = <FW_EDIMAX_OFFSET>;
 127                                 openwrt,partition-magic = <FW_MAGIC_EDIMAX>;
 128                                 label = "firmware";
 129                                 reg = <0x00070000 0x00790000>;
 130                         };
 131                 };
 132         };
 133 };
 134
 135 &state_default {
 136         gpio {
 137                 groups = "i2c", "uartf", "nd_sd";
 138                 function = "gpio";
 139         };
 140 };
 141
 142 &ethernet {
 143         pinctrl-names = "default";
 144         pinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>;
 145
 146         nvmem-cells = <&macaddr_factory_4>;
 147         nvmem-cell-names = "mac-address";
 148
 149         mediatek,portmap = "wllll";
 150
 151         port@5 {
 152                 status = "okay";
 153                 mediatek,fixed-link = <1000 1 1 1>;
 154                 phy-mode = "rgmii";
 155         };
 156
 157         mdio-bus {
 158                 status = "okay";
 159
 160                 phy0: ethernet-phy@0 {
 161                         reg = <0>;
 162                         phy-mode = "rgmii";
 163                 };
 164
 165                 phy1: ethernet-phy@1 {
 166                         reg = <1>;
 167                         phy-mode = "rgmii";
 168                 };
 169
 170                 phy2: ethernet-phy@2 {
 171                         reg = <2>;
 172                         phy-mode = "rgmii";
 173                 };
 174
 175                 phy3: ethernet-phy@3 {
 176                         reg = <3>;
 177                         phy-mode = "rgmii";
 178                 };
 179
 180                 phy4: ethernet-phy@4 {
 181                         reg = <4>;
 182                         phy-mode = "rgmii";
 183                 };
 184
 185                 phy1f: ethernet-phy@1f {
 186                         reg = <0x1f>;
 187                         phy-mode = "rgmii";
 188                 };
 189         };
 190 };
 191
 192 &gsw {
 193         mediatek,ephy-base = /bits/ 8 <12>;
 194 };
 195
 196 &wmac {
 197         nvmem-cells = <&eeprom_factory_0>;
 198         nvmem-cell-names = "eeprom";
 199 };
 200
 201 &pcie {
 202         status = "okay";
 203 };
 204
 205 &pcie0 {
 206         wifi@0,0 {
 207                 reg = <0x0000 0 0 0 0>;
 208                 mediatek,mtd-eeprom = <&factory 0x8000>;
 209                 mediatek,2ghz = <0>;
 210         };
 211 };
 212
 213 &ehci {
 214         status = "okay";
 215 };
 216
 217 &ohci {
 218         status = "okay";
 219 };